diff options
| author | dmcmahill <dmcmahill> | 2001-02-15 07:18:57 +0000 |
|---|---|---|
| committer | dmcmahill <dmcmahill> | 2001-02-15 07:18:57 +0000 |
| commit | c85c90e0cf6b8478ab7a9d74c347035dda3affe3 (patch) | |
| tree | 7f1aaebfff5bfa3cd9a29e540e361849a1706fd8 /print/lgrind/patches | |
| parent | e6c0c401ec20ad3c4061b2071ec05b83668bad29 (diff) | |
| download | pkgsrc-c85c90e0cf6b8478ab7a9d74c347035dda3affe3.tar.gz | |
add verilog support. tried to contact the last known author/maintainer
for lgrind to feed patch back to, but email bounced.
Diffstat (limited to 'print/lgrind/patches')
| -rw-r--r-- | print/lgrind/patches/patch-ad | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/print/lgrind/patches/patch-ad b/print/lgrind/patches/patch-ad new file mode 100644 index 00000000000..c8706549671 --- /dev/null +++ b/print/lgrind/patches/patch-ad @@ -0,0 +1,41 @@ +$NetBSD: patch-ad,v 1.1 2001/02/15 07:18:57 dmcmahill Exp $ + +--- ../lgrindef.orig Tue Aug 4 09:01:00 1998 ++++ ../lgrindef Wed Feb 14 22:34:26 2001 +@@ -685,4 +685,30 @@ + tk_popup tkwait toplevel trace unknown unset update uplevel upvar while winfo wm: + ++# verilog. Written by Dan McMahill ++Verilog:\ ++ :pb=\dmodule\d?\p:np=\)\d;:bb=begin\d:be=end\d:\ ++ :cb=/*:ce=*/:sb=":se=\e":\ ++ :tl:ab=//:ae=$:id=_$`:\ ++ :zb=@:ze=@:tb=%%:te=%%:mb=%\$:me=\$%:vb=%\|:ve=\|%:\ ++ :kw=always and assign attribute begin buf bufif0 bufif1 case casex \ ++ casez cmos deassign default defparam disable edge else end endattribute \ ++ endcase endfunction endmodule endprimitive endspecify \ ++ endtable endtask event for force forever fork function highz0 highz1 if initial \ ++ inout input integer join large macromodule medium module nand negedge nmos nor \ ++ not notif0 notif1 or output parameter pmos posedge primitive pull0 pull1 \ ++ pulldown pullup rcmos real realtime reg release repeat rnmos rpmos rtran \ ++ rtranif0 rtranif1 scalared signed small specify specparam strength strong0 \ ++ strong1 supply0 supply1 table task time tran tranif0 tranif1 tri tri0 tri1 \ ++ triand trior trireg unsigned vectored wait wand weak0 weak1 while wire wor \ ++ xnor xor\ ++ $bitstoreal $countdrivers $display $fclose $fdisplay $finish $fmonitor \ ++ $fopen $fstrobe $fwrite $getpattern $history $incsave $input $itor $key \ ++ $list $log $monitor $monitoroff $monitoron $nokey $time \ ++ `accelerate `autoexpand_vectornets `celldefine `default_nettype `define \ ++ `else `endcelldefine `endif `endprotect `endprotected `expand_vectornets \ ++ `ifdef `include `noaccelerate `noexpand_vectornets `noremove_gatenames \ ++ `nounconnected_drive `protect `protected `remove_gatenames `remove_netnames \ ++ `resetall `timescale `unconnected_drive: ++ + + # JL - Added visbasic 6 Aug 1996. Note: this is not complete! +@@ -748,4 +774,5 @@ + :pro=prolog:\ + :m=matlab:\ ++ :v=verilog:\ + :f=f77:F=f77:for=f77: + |