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authordmcmahill <dmcmahill>2001-08-04 01:20:43 +0000
committerdmcmahill <dmcmahill>2001-08-04 01:20:43 +0000
commitbd8168a58b59cfc8f1e41e9c8910aa36ffd3a13c (patch)
treefb7a953d710d8aa2d602e08e725f2c97f6431ec6 /shells
parent2d464435b7876449b761f02c255d738d9b7cf355 (diff)
downloadpkgsrc-bd8168a58b59cfc8f1e41e9c8910aa36ffd3a13c.tar.gz
update to verilog-0.5
* The Big Change: VVP Past versions of Icarus Verilog performed simulation by compiling the Verilog design to intermediate C++ code, then in turn compiling that C++ (usually with G++) to a binary executable. This program was then executed to actually run the simulation. The 0.5 compiler, however, uses a custom internal language called "vvp." The vvp code generator writes a program in the vvp language that the vvp interpreter executes. This gets runtime performance similar to the older vvm method, but compile times are much faster. The result of this change is that there is a new program, ``vvp'', that is installed with the existing ``iverilog'' compiler. This program actually executes the simulation generated by the vvp code generator. There are manual pages for the iverilog command and the new vvp command, as well as a QUICK_START document to help you run your first simulation. * What Else Is New The compiler itself is now a lot more robust. While it still does not compile and understand the entire IEEE1364 standard, the compiler is less likely to crash on bad input, gives better error messages, and has generally been cleaned up.
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