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authorsmb <smb>2008-11-24 04:06:00 +0000
committersmb <smb>2008-11-24 04:06:00 +0000
commit1e711e88a276ad9c3cc0f7117af9fd8177da1c8d (patch)
treeb36b2c0d3fc1622b201532ea675237a4bab02bf7 /sysutils/memtestplus/options.mk
parenteae98f4a48be891991a8ae856846a77af40187a8 (diff)
downloadpkgsrc-1e711e88a276ad9c3cc0f7117af9fd8177da1c8d.tar.gz
Upgrade to 2.10:
*** Enhancements in v2.10 : *** * New Features o Added support for Intel Core i7 (Nehalem) CPU o Added support for Intel Atom Processors o Added support for Intel G41/G43/G45 Chipsets o Added support for Intel P43/P45 Chipsets o Added support for Intel US15W (Poulsbo) Chipset o Added support for Intel EP80579 (Tolapai) SoC CPU o Added support for ICH10 Southbridge (SPD/DMI) o Added detection for Intel 5000X o Now fully aware of CPU w/ L3 cache (Core i7 & K10) * Bug Fixes o Added workaround for DDR3 DMI detection o Fixed Intel 5000Z chipset detection o Fixed Memory Frequency on AMD K10 o Fixed cache detection on C7/Isaiah CPU o Fix Memtest86+ not recognized as Linux Kernel Enhancements in v2.01 : * Added support for i945GM/PM/GME & i946PL/GZ * Added support for iGM965/iGL960/iPM965/iGME965/iGLE960 * Added detection for SiS 649/656/671/672 * Added detection for i430MX/i430TX * Added an optional beep mode (pass completed w/o error) * Pass duration 20% reduced * Removed the blinking cursor * Reverted Test #0 to cached * Solved a major bug in Memory Address Errors Reporting * Patched for Intel-Powered Mac * Corrected Intel 3-Series (P35/X38) chipset init * Corrected a bug with SPD Display and ESB6300 * Correct a detection bug on P965/G965 C-Stepping * Solved a incoherency with pass progress indicator * Patched Makefile to compile on x86_64 * Bootable Memtest86+ ISO more compatible Enhancements in v2.00 : * Major Architectures changes * Modulo test now use random pattern for better accuracy * Added Advanced DMI Errors Reporting Mode * Added support for bus ratio changes on Intel Core CPU * Added support for non-integer bus ratio on latest Intel CPU * Added SPD Data Display for all Intel Chipsets (more to come) * Added serial support as a linux boot parameter (Thanks to Michal S.) * Added preliminary support for VIA CN Isaiah CPU * Added preliminary support for Intel Nehalem * Added support for VIA C7/C7-D/C7-M/Eden on Esther Core * Added support for AMD K10 (Phenom) CPU w/ timings detection * Added support for Intel Pentium E w/ 1 MB L2 Cache * Added support for Intel Core 2 45nm (Penryn) * Added support for FSB1333/FSB1600 Intel CPU * Added support for Intel 5400A/5400B w/ timings detection * Added support for Intel Q35/P35/G33/Q33 w/ timings detection * Added support for Intel X38/X48 w/ timings detection * Added preliminary support for Intel 5000P/V/Z * Removed on-fly memory timings change (unstable) * Numerous (really) bug fixes
Diffstat (limited to 'sysutils/memtestplus/options.mk')
-rw-r--r--sysutils/memtestplus/options.mk4
1 files changed, 2 insertions, 2 deletions
diff --git a/sysutils/memtestplus/options.mk b/sysutils/memtestplus/options.mk
index 7b8f3b59b16..fd54d147ace 100644
--- a/sysutils/memtestplus/options.mk
+++ b/sysutils/memtestplus/options.mk
@@ -1,4 +1,4 @@
-# $NetBSD: options.mk,v 1.4 2008/04/12 22:43:13 jlam Exp $
+# $NetBSD: options.mk,v 1.5 2008/11/24 04:06:00 smb Exp $
PKG_OPTIONS_VAR= PKG_OPTIONS.memtestplus
PKG_SUPPORTED_OPTIONS= iso serialconsole
@@ -8,7 +8,7 @@ PKG_SUGGESTED_OPTIONS=
PLIST_VARS+= iso
.if !empty(PKG_OPTIONS:Miso)
-BUILD_TARGET= memtest.iso
+BUILD_TARGET= iso
BUILD_DEPENDS+= {cdrtools,cdrtools-ossdvd}>=2.01:../../sysutils/cdrtools
PLIST.iso= yes
.endif