diff options
| -rw-r--r-- | cad/MyHDL-iverilog/Makefile | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/cad/MyHDL-iverilog/Makefile b/cad/MyHDL-iverilog/Makefile index 939c14aa26f..22584367e3b 100644 --- a/cad/MyHDL-iverilog/Makefile +++ b/cad/MyHDL-iverilog/Makefile @@ -1,8 +1,9 @@ -# $NetBSD: Makefile,v 1.8 2015/01/04 02:45:50 mef Exp $ +# $NetBSD: Makefile,v 1.9 2016/10/08 23:11:23 kamil Exp $ # DISTNAME= myhdl-0.8.1 PKGNAME= MyHDL-iverilog-0.7 +PKGREVISION= 1 PKGNAME= ${DISTNAME:C/myhdl/MyHDL-iverilog/} CATEGORIES= cad python MASTER_SITES= ${MASTER_SITE_SOURCEFORGE:=myhdl/} @@ -23,5 +24,5 @@ do-install: #do-test: # (cd ${WRKSRC}/cosimulation/icarus/test && ${PYTHONBIN} test_all.py) -.include "../../cad/verilog/buildlink3.mk" +.include "../../cad/iverilog/buildlink3.mk" .include "../../mk/bsd.pkg.mk" |