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Diffstat (limited to 'cad/covered-current/DESCR')
| -rw-r--r-- | cad/covered-current/DESCR | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/cad/covered-current/DESCR b/cad/covered-current/DESCR deleted file mode 100644 index 430a2339c08..00000000000 --- a/cad/covered-current/DESCR +++ /dev/null @@ -1,17 +0,0 @@ -Covered is a Verilog code coverage analysis tool that can be useful -for determining how well a diagnostic test suite is covering the -design under test. Typically in the design verification work flow, a -design verification engineer will develop a self-checking test suite -to verify design elements/functions specified by a design's -specification document. When the test suite contains all of the tests -required by the design specification, the test writer may be asking -him/herself, "How much logic in the design is actually being -exercised?", "Does my test suite cover all of the logic under test?", -and "Am I done writing tests for the logic?". When the design -verification gets to this point, it is often useful to get some -metrics for determining logic coverage. This is where a code coverage -utility, such as Covered, is very useful. - -Please note that this package is a development snapshot and while it -contains the latest and greatest features, it may be buggy as well. -There is a separate package which is made of the stable releases. |