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Diffstat (limited to 'cad/gplcver/DESCR')
| -rw-r--r-- | cad/gplcver/DESCR | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/cad/gplcver/DESCR b/cad/gplcver/DESCR new file mode 100644 index 00000000000..952b010d52b --- /dev/null +++ b/cad/gplcver/DESCR @@ -0,0 +1,4 @@ +Cver is a full 1995 IEEE P1364 standard Verilog simulator. It also +implements some of the 2001 P1364 standard features. All three +PLI interfaces (tf_, acc_, and vpi_) are implemented as defined +in the IEEE 2001 P1364 LRM. |