diff options
Diffstat (limited to 'cad/verilog-current')
| -rw-r--r-- | cad/verilog-current/DESCR | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cad/verilog-current/DESCR b/cad/verilog-current/DESCR index be6aa3ca681..5b1676fc19a 100644 --- a/cad/verilog-current/DESCR +++ b/cad/verilog-current/DESCR @@ -4,7 +4,7 @@ format. For batch simulation, the compiler can generate C++ code that is compiled and linked with a run time library (called "vvm") then executed as a command to run the simulation. For synthesis, the compiler generates netlists in the desired format. - + The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and complex standard, so it will take some time for it to get there, but that's |