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Use saner and more specific name for this package.
No objection for rename from <gdt>
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pkgsrc changes:
- note GitHub tags (but not use them for now)
- remove conflict with nonexistent verilog-current
- install additional documentation in share/doc/ivl (not share/ivl)
- drop DESTDIR gymnastics - build works without it
- (re)enable gperf dependency
- regenerate buildlink3.mk
- drop patches/patch-lexor_keyword.cc - no longer needed
- patches/patch-vpi_Makefile partially fixed upstream - rest not needed
upstream changelog
==================
Probably the only notes available:
Here are the release notes for Icarus Verilog release branch 10. The 10
release is a huge improvement over the 0.9 release series, in every
aspect. Much more of the Verilog and SystemVerilog language is supported,
many bugs have been fixed, and performance has improved. The changes
(improvements!) are so numerous that there is no point attempting to
enumerate them.
-- http://iverilog.wikia.com/wiki/Release_Notes_Icarus_Verilog_10
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Disable build dependence on gperf as the build doesn't actually run
it, and also for this workaround I need to patch the gperf output
file.
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Icarus Verilog 0.9.7 is Available (August 26th, 2013)
-----------------------------
The developers are pleased to announce the next stable release in
the 0.9 series, version 0.9.7. Icarus Verilog is a mostly complete
implementation of the hardware description language Verilog, as
described in IEEE Std 1364-2005. It also includes a number of user
requested extensions. It is freely available (open source), is
supported on most operating systems, and will be available as a
precompiled package for many of these systems.
Icarus Verilog 0.9.7 is primarily a bug fix release. Therefore, we
recommend people using the 0.9.6 or earlier releases upgrade to 0.9.7
as soon as possible. Version 0.9.7 is the recommended version for all
new users.
More details, including known limitations, deviation from IEEE Std
1364-2005, where to obtain the source code, and links to some of the
precompiled packages can be found in the Release Notes located here:
<http://iverilog.wikia.com/wiki/Release_Notes_Icarus_Verilog_0_9_7>
(pkgsrc)
0.9.4 to 0.9.7 update and
two patches are added for DESTDIR and 'mkdir: dep: Not a directory' problem.
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changes:
-Language Coverage:
-Add support for using the &&, || and ! operators with real
constant values
-Add support for passing -0.0 from the compiler to the run time
-Add support for parsing pull devices that have two strengths specified
-Allow multiple attribute instances
-bugfixes
pkgsrc change: clean up DESTDIR support
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** Release Notes for Icarus Verilog 0.8.3
This is a new release of the stable 0.8 branch. The changes from 0.8.2
are intended to be evolutionary, rather then revolutionary, to enhance
the stability of the branch.
Various simulator bugs have been fixed, including (but not limited to):
- Detect overrun of timescale vs. precision
- Handle more operators in constant expressions
- Various ivl crashes and panics fixed.
- Some performance bottlenecks have been fixed.
- Various tool compilation problems have been fixed.
Also, the internal synthesizer (for synthesis targets) has been
considerably improved. NOTE that the code generators have not been
improved to take advantage of all the changes here, so there is work
yet to be done.
The mingw build process for compiling in Windows has been reworked. It
is now possible (indeed preferable) to compile fully native Icarus
Verilog binaries on Windows with no Cygwin tools at all.
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The current release is a considerable improvement over the previous stable
release. It includes 20 months of fixes and language coverage improvements.
For a complete history of changes, see the release notes for individual
snapshots between the 0.7 and 0.8 releases found at
ftp://ftp.icarus.com/pub/eda/verilog/snapshots/pre-0.8
A brief list of highlights:
- Support for advanced standard data types such as real,
- Lots more language support in general,
- Kernel of an extensible, interactive debugger is new,
- More complete support for user supplied system functions and tasks,
including PLI system functions with various return value types,
- Better standards compliance for core system tasks and functions in
general, including some Verilog 2001 file I/O support, and
- Performance improvements in general.
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* The Big Change: VVP
Past versions of Icarus Verilog performed simulation by compiling the
Verilog design to intermediate C++ code, then in turn compiling that
C++ (usually with G++) to a binary executable. This program was then
executed to actually run the simulation.
The 0.5 compiler, however, uses a custom internal language called
"vvp." The vvp code generator writes a program in the vvp language
that the vvp interpreter executes. This gets runtime performance
similar to the older vvm method, but compile times are much faster.
The result of this change is that there is a new program, ``vvp'',
that is installed with the existing ``iverilog'' compiler. This
program actually executes the simulation generated by the vvp code
generator.
There are manual pages for the iverilog command and the new vvp
command, as well as a QUICK_START document to help you run your first
simulation.
* What Else Is New
The compiler itself is now a lot more robust. While it still does not
compile and understand the entire IEEE1364 standard, the compiler is
less likely to crash on bad input, gives better error messages, and
has generally been cleaned up.
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up a possibly out of date installed header from ${LOCALBASE}/include.
Note that while we don't support installing a pkg when a previous version
is installed, we should still be able to build it.
Problem noted in private email from Lennart Augustsson.
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from the authors announcement:
So many things have changed since version 0.3 that there is no point
in listing them. There have been tons and tons of bug fixes and the
language coverage is better, and so on and so forth. It's just so very
much better then version 0.3:-)
speaking as a user, some of my personal favorites are:
- support for signed variables
- iverilog now gives correct return codes (which makes 'make' much happier)
for a more complete list, the commit messages for
pkgsrc/cad/verilog-current/Makefile contain the changes for each
development snapshot between verilog-0.3 and verilog-0.4
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with viewers such as Dinotrace.
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Changes, from the authors release statement, are:
This release is a significant improvement over previous releases of
Icarus Verilog, including better language coverage, improved
synthesis, and increased performance.
This release adds to the 0.2 release support for Verilog-2000 style
parameters and parameter overrides, defparam, and localparam,
including proper handling of scoping rules. Also, strength modeling is
added, with support for strengths attached to gates and continuous
assignments.
Combinational user defined primitives have been added to complement
synchronous primitives that were already supported. Support for
primitives should now be fairly complete.
Force/release/assign/deassign syntax now works properly, allowing for
more sophisticated test bench design and debugging.
Bug fixes have been numerous and varied. This release of Icarus
Verilog is considerably more robust then previous versions, thanks to
diligent testing and bug reporting by users all over the world.
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NetBSD pkgsrc patches to the previous release. Thanks to Stephen Williams
(the author) for his willingness to accept patches!
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Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a
compiler, compiling source code writen in Verilog (IEEE-1364) into some target
format. For batch simulation, the compiler can generate C++ code that is
compiled and linked with a run time library (called "vvm") then executed as
a command to run the simulation. For synthesis, the compiler generates
netlists in the desired format.
The compiler proper is intended to parse and elaborate design descriptions
written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and
complex standard, so it will take some time for it to get there, but that's
the goal. I'll be tracking the upcoming IEEE Std 1364-1999 revision as well,
and some -1999 features will creep in.
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