pkgsrc - [no description]

Age	Commit message (Collapse)	Author	Files	Lines
2021-10-26	cad: Replace RMD160 checksums with BLAKE2s checksums	nia	1	-2/+2
	All checksums have been double-checked against existing RMD160 and SHA512 hashes
2021-10-07	cad: Remove SHA1 hashes for distfiles	nia	1	-2/+1

2020-05-20	mark packages that fail with -Werror=char-subscripts	rillig	1	-1/+10
	These packages are susceptible to bugs when confronted with non-ASCII characters. See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94182. It takes some time to analyze and fix these individually, therefore they are only marked as "needs work".
2020-03-18	Not really C++11 ready. Don't define bool/true/false for C++.	joerg	3	-3/+31

2016-10-09	Import veriwell-2.8.7 as cad/veriwell	kamil	4	-0/+36
	VeriWell is a full Verilog simulator. It supports nearly all of the IEEE1364-1995 standard, as well as PLI 1.0. Yes, VeriWell is the same simulator that was sold by Wellspring Solutions in the mid-1990 and was included with the Thomas and Moorby book.