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2002-06-26Substitute a couple of `mkdir' by `${MKDIR}'.seb1-2/+2
Remove `-p' from mkdir arguments, it is already part of ${MKDIR}. While here substitute a couple of ${PREFIX} by `%D' in `@exec ${MKDIR} ...' lines and add a couple of missing `%D' in such lines too!
2002-06-15claim maintainership of this (from packages)dmcmahill1-2/+2
2002-06-01add PKG_SYSCONFDIR/pcb, $HOME/.pcb and . to the search path for PCB m4dmcmahill10-16/+84
files. In addition sinclude the files 'site-config.inc', 'user-config.inc', and 'proj-config.inc' to allow for per-site, per-user, and per-project configuration instead of only per-site configuration. This is essential for use by non-sysadmin users and users who need to keep project specific setups.
2002-05-31- use getcwd() instead of getwd().dmcmahill15-2/+369
- remove all compiler warnings on alpha - add ${PKG_SYSCONFDIR}/pcb/local.inc where admins can list site specific libraries to be included instead of modifying one of the regularly installed/deinstalled files. This way a local config is preserved when the pkg is upgraded. Also a local config can be applied without modifying one of the files which is checksummed during the install.
2002-05-31- fix the gschem2pcb script (used to help go from a schematic to a netlistdmcmahill4-2/+93
and .pcb file for layout with the cad/pcb package). - fix the PCBboard netlister (needs GNU m4) - add depends on gm4.
2002-05-18use MAGIC_HOME instead of CAD_HOME as the environment variable whichdmcmahill2-4/+13
points to the magic installation. This avoids possible conflicts with some other UCB tools which use CAD_HOME. Noted in private email from Daniel Senderowitz.
2002-05-18update the gEDA suite of tools to the 20020414 snapshot.dmcmahill36-330/+333
Many bug fixes and improvements since last snapshot. Many more symbols added to the libraries.
2002-05-18Update to gwave-20020122dmcmahill2-6/+5
minor update: - interactive Y-zoom and XY-area zoom added (see Readme) - zoom-to-exact-size dialog box added
2002-05-18update to geda-docs-20020209 which is the latest documentationdmcmahill3-10/+15
2002-05-07update to gerbv 0.0.8dmcmahill3-19/+5
Graphical quirks fixed are: - zooming around the mouse pointer. - zooming several steps at once goes much faster. No calculation and redrawing in each zoom step, but in the last step. When you click with the left mouse button on a layer button you get a popup menu with color selection, load file and unload file. That is on a "per layer-basis". The "global" "Open File..." menu is removed in favor for this.
2002-05-07update to verilog-current-20020505dmcmahill4-11/+25
many improvements and bug fixes since the last packaged snapshot including: -added the $sizeof system function as a builtin -In VPI, the simulator event callbacks now work -Concatenation expressions in parameters were broken are broken -added the vpiModule iterator to VPI scope handles
2002-04-23Note explicitly that this package is USE_X11BASE. Currently, it relies onjlam2-2/+4
motif.buildlink.mk to define it.
2002-04-20On arm32, avoid egcs internal compiler errors by using gcc-2.95.3cjep1-1/+6
2002-04-20On arm32, use gcc-2.95.3 to avoid an internal egcs compiler error.cjep1-1/+6
2002-04-17Update dependency on xforms. We're mainly bumping the dependencyfredb3-10/+16
and package revision, since we may now link against the forms shared library, and because we also have to add a dependency on jpeg lib.
2002-04-06add magicdmcmahill1-1/+2
2002-04-06import of magic-7.1dmcmahill7-0/+314
Magic is an interactive system for creating and modifying VLSI circuit layouts. With Magic, you use a color graphics display and a mouse or graphics tablet to design basic cells and to combine them hierarchically into large structures. Magic is different from other layout editors you may have used. The most important difference is that Magic is more than just a color painting tool: it understands quite a bit about the nature of circuits and uses this information to provide you with additional operations. For example, Magic has built-in knowledge of layout rules; as you are editing, it continuously checks for rule violations. Magic also knows about connectivity and transistors, and contains a built-in hierarchical circuit extractor. Magic also has a plow operation that you can use to stretch or compact cells. Lastly, Magic has routing tools that you can use to make the global interconnections in your circuits. Magic is based on the Mead-Conway style of design. This means that it uses simplified design rules and circuit structures. The simplifications make it easier for you to design circuits and permit Magic to provide powerful assistance that would not be possible otherwise. However, they result in slightly less dense circuits than you could get with more complex rules and structures. For example, Magic permits only Manhattan designs (those whose edges are vertical or horizontal).
2002-04-04Use "suse_linux/Makefile.application" to pick correct SuSE packages.tron1-3/+4
2002-04-04Obey CFLAGS. In particular this lets the default -O2 for pmax get useddmcmahill2-1/+15
which fixes compile problems noted in PR pkg/16160 by Daniel Senderowicz <daniel@bicho.SynchroDS.COM>. Thanks to Simon Burge for helping on this.
2002-03-29update to gnucap-0.31dmcmahill3-6/+7
The most significant changes are the BJT model and "binning". New features: 1. BJT model. 2. "Binning" for all MOS models. 3. Internal element: non-quasi-static poly-capacitor. (needed by BJT). 4. Enhancements to the data structures and model compiler to support binning in general. 5. A line prefixed by "*>" is not ignored, in spite of the fact that "*" usually begins a comment. This is a deliberate incompatibility with Spice. If you prefix a line by "*>" it will be interpreted as a non-comment in Gnucap, but a comment in Spice. 6. Circuit line prefixes of ">" and command prefixes of "-->" are ignored. This is so you can copy and paste whole lines, without having to manually remove the prompt string. Changes that may or may not be improvements. 1. It is not the default to include stray resistance in device models. The option "norstray" will revert to the old behavior. This is only a change to the default value of "rstray". Significant internal changes: 1. The internal element non-quasi-static poly-capacitor actually works. It is used by the BJT model, and will eventually be used by MOSFET models. 2. There are now two poly_g devices: "CPOLY_G" and "FPOLY_G". There are interface differences that impact modeling. Previously, there was only one, which is equivalent to the "FPOLY_G".
2002-03-28update to verilog-current-20020317dmcmahill3-15/+8
Release Notes for snapshot 20020317 The first difference in this snapshot from the 0.6 release is that vvm is no longer compiled by default. If you want to compile vvm, you must enable it at configure time (--enable-vvm) and rebuild from scratch. Eventually, vvm will disappear from the release altogether. The next major difference is new support for user defined functions. It is new support, so it is bound to be buggy, but it should be somewhat complete. The major problem has been solved, so all that remains are bugs around the edges. The vvp run-time scheduler has been changed slightly. The run time behavior is getting increasingly precise and picky, as larger designs are thrown at the compiler. The change introduced in this snapshot fixes logic gates to not propagate zero-time pulses, and thus fixes some weird bugs in large designs. I've also added initial support for the Verilog 200x pragma comment, which are (* *) pairs. For now, the compiler ignores them as comments. This is what a compiler is supposed to do with anything that is not specifically recognized. Also, Tony (Anthony Bybell) has added LXT dump support. The LXT output file is a waveform output format that is much more compact then VCD. The gtkwave waveform viewer supports the LXT format, and should operate a bit faster when viewing LXT files. For now, there are separate system tasks for managing LXT output ($lxt_dumpvars, etc) but eventually the dump format will be selectable by environment variable or command line switch. This snapshot also includes various random bug fixes and improved error messages for incorrect code.
2002-03-17Set DIST_SUBDIR to PKGNAME_NOREV.fredb1-2/+2
2002-03-14Wildcard some dependencies.wiz1-4/+4
2002-03-13Give all packages which depend on "png" a version bump, and updatefredb12-20/+32
all dependencies on packages depending on "png" which contain shared libraries, all for the (imminent) update to the "png" package. [List courtesy of John Darrow, courtesy of "bulk-build".]
2002-03-13add and enable atlcdmcmahill1-1/+2
2002-03-13import of atlc-2.32dmcmahill4-0/+95
------ Atlc is a finite difference programme that is used to calculate the properties of a two-conductor electrical transmission line of arbitrary cross section. It is used whenever there are no analytical formula known, yet you still require an answer. It can calculate: The impedance Zo (in Ohms) The capacitance per unit length (pF/m) The inductance per unit length (nF/m) The velocity of propogation v (m/s) The velocity factor, v/c, which is dimensionless. A bitmap file (usually with the extension .bmp or .BMP) of the cross section of the transmission line is drawn in a graphics package such as The Gimp and then analyzed using Atlc.
2002-03-13add and enable electricdmcmahill1-1/+2
2002-03-13Import electric-6.05dmcmahill6-0/+534
----- Electric is a sophisticated electrical CAD system that can handle many forms of circuit design, including: Custom IC layout (ASICs), Schematic drawing, Hardware description language specifications, Electro-mechanical hybrid layout Electric has these CAD operations: Design rule checking (3 options), Electrical rule checking, Simulation and simulation interface (12 options), Generation (3 options), Compaction, Compensation, Routing (4 options), VHDL compilation, Silicon compilation, Network consistency checking (LVS), Logical Effort analysis, Project Management Electric handles these types of design: MOS (6 CMOS variations, 1 nMOS variation), Bipolar and BiCMOS, Schematics and printed circuits, Digital filters, Temporal logic, Artwork Electric handles these file formats: CIF I/O, GDS I/O, EDIF I/O, DXF I/O, SDF Input, SUE Input, VHDL I/O, Verilog Output, EAGLE, PADS, and ECAD Output, PostScript, HPGL, and QuickDraw output
2002-03-04Generalize the handling for packages where "fetch" and "fetch-list"fredb1-10/+1
only emit a message and don't actually fetch anything. This allows us to make the output of "fetch-list" for these packages consistent with other packages. While we're in here, integrate DYNAMIC_MASTER_SITES with the ${ORDERED_SITES} macro. The only functional change here is that ${MASTER_SITE_OVERRIDE} is now respected. Still to do -- something appropriate for "fetch-list" for these packages, like sourcing "getsites.sh" into the generated script. (Well, "package", but there are two others that do something similar in their "Makefile".) Also eliminate the misbegotten _FETCH_ALLFILES macro -- now that only "fetch" uses it, move it's functionality directly under "do-fetch".
2002-02-27* Strongly buildlinkify to handle readline wierdness.jlam6-75/+107
* Don't declare a bunch of extern functions that are already declared by system headers on NetBSD. XXX This change may be incorrect for non-current systems.
2002-02-26Wherever "make fetch" simply echos a message, let "make fetch-list|sh"fredb1-3/+12
echo the message, too.
2002-02-18Introduce new framework for handling info files generation and installation.seb6-12/+15
Summary of changes: - removal of USE_GTEXINFO - addition of mk/texinfo.mk - inclusion of this file in package Makefiles requiring it - `install-info' substituted by `${INSTALL_INFO}' in PLISTs - tuning of mk/bsd.pkg.mk: removal of USE_GTEXINFO INSTALL_INFO added to PLIST_SUBST `${INSTALL_INFO}' replace `install-info' in target rules print-PLIST target now generate `${INSTALL_INFO}' instead of `install-info' - a couple of new patch files added for a handful of packages - setting of the TEXINFO_OVERRIDE "switch" in packages Makefiles requiring it - devel/cssc marked requiring texinfo 4.0 - a couple of packages Makefiles were tuned with respect of INFO_FILES and makeinfo command usage See -newly added by this commit- section 10.24 of Packages.txt for further information.
2002-02-15mkdir -> ${MKDIR}skrll3-8/+8
rmdir -> ${RMDIR} rm -> ${RM} (${RM} added to PLIST_SUBST) chmod -> ${CHMOD} chown -> ${CHOWN}
2002-02-10update to dinotrace-9.1g from 9.1ddmcmahill2-5/+5
Changes in Dinotrace 9.1g 01/24/2002 *** Reread all traces on receiving a USR1 signal. [Uwe Bonnes] **** Allow value searches on one-bit signals. [Vitaly Oratovsky] Changes in Dinotrace 9.1f 01/08/2002 *** Let right button terminate Zoom click. [Uwe Bonnes] **** Fixed Emacs 21.0 incompatibility with back-annotation. **** Hacked around bug causing window manager crash when using Examine inside Zoom. [Uwe Bonnes] * Changes in Dinotrace 9.1e 11/16/2001 *** Allow 1-bit wide signals to have statenames. [Dominik Strasser] *** Eliminate common prefix from postscript dumps. [Dominik Strasser] *** Show count of posedges and negedges in value examine.
2002-02-10update to 0.0.7dmcmahill3-5/+19
What's new in 0.0.7 - Aperture macros! - Improved detection of drill- or gerber file.
2002-02-08update to verilog-0.6dmcmahill3-11/+19
WHAT'S NEW SINCE 0.5? Quite a lot. Innumerable bugs have been fixed, and standards coverage has been improved significantly. Warning and error messages have been improved, and so has compile performance. Gate delays, strength modeling, and floating point delays have all improved since the 0.5 release. If you had trouble with the 0.5 release, the 0.6 release probably fixes your problem. Support for large designs spanning multiple files has been improved dramatically. The usual preprocessor inclusion method still works, but The 0.6 release adds command files for keeping source file lists, and automatic library searches for missing modules. The library mechinisms are compatible with commercial tools, and commercial module libraries can be used with Icarus Verilog. Many compiler limitations related to the size and complexity of large designs have been relaxed or eliminated. There are no known design size limitations remaining in the compiler. Icarus Verilog should be able to handle any design that you have the patience to compile.
2002-02-05/bin/mkdir -> ${MKDIR}.skrll1-2/+2
Make the print-PLIST target output ${MKDIR} also.
2002-02-05Don't hardcode /usr/X11R6 when making directories or running X basedskrll1-2/+2
programs such as mkfontdir use ${X11BASE} instead. Also pick up a couple of /bin/chmod -> ${CHMOD}s
2002-01-26update to ngspice-14dmcmahill8-114/+182
A pkgsrc specific change is that it no longer conflicts with the cad/spice package allowing both to be installed. From the NEWS file: This is a major release in terms of bug-fixes. Some enhancements have been included: BSIM4 model and support for EKV model. The source code for the latter must be obtained from EKV web site (see DEVICE for more info). To enable EKV support you have to obtain the code first and then use the configure switch "--enable-ekv".
2002-01-21Weakly buildlinkify.wiz1-6/+5
2002-01-16update to verilog-current-20020112dmcmahill2-6/+12
many many changes since the last packaged snapshot. A brief sampling of the changes (which include many bug fixes and enhancements) is: A variety of little problems with $display format strings have been fixed. The % operand should now simulate properly. Also, the * operator is a little bit more optimized, and works in constant expressions. Several bugs in strength modeling have been fixed. This includes drive strengths on continuous assignments, which in the past generated code without the strengths. Also, vvp gained some missing support for constants with strength. I think that strength modeling is now complete. vpi_get_vlog_info support has been added to the vvp run-time. This is a PLI function that allows access to run-time command flags. Also, vpi access to root modules now works properly.
2001-12-15update to 0.0.6.dmcmahill3-6/+7
changes since 0.0.5: - Turn on and off explicit layers. - Color on button reflect color on layer. - Automatic detection of drill- or gerber file. - Tooltips over buttons to reflect loaded filename. - Handles Polygon Area Fill - Major rehacking of file IO and pan code to significantly increase speed. - Autoscaling. Loaded gerber files are automagically scaled and panned to fit in window. Also possible to do with loaded files with Zoom/Fit meny option. - configure.in enhancement to support package building in Red Hat. Thanks to Wojciech Kazubski for patch. - bzero changed to memset, which hopefully is more POSIX (for portability). - Loads of bugs squashed and hopefully fewer added.
2001-12-15update to verilog-current-20011209 snapshot.dmcmahill2-6/+6
Many changes since the last packaged snapshot. A sampling of these are: Support for hierarchical names has been largely rewritten. The major consequence of this is that escaped names now have much better support. By now, most any combination of escaped and hierarchical name should work properly, for nets, parameters, and anything else. Output delays for primitive gates, including user defined primitivies, should now work properly. Delays on nets still do not work, although the parser now parses them and prints a "sorry" message. Bugs in support for division(/) and modulus (%) have been fixed. Bugs in l-values of synthesized DFF devices have been fixed. These bugs were related to part selects of vectors in l-values. A few XNF code generator bugs and limitations were fixed. And as usual, a variety of miscellaneous bugs have been fixed in this snapshot. The bit size of the results of some unary redunction operators is now properly handled. Also, similar problems with logical functions have been fixed. force/release now works for variables, though not yet for nets. Assign/deassign already work. many other bugfixes
2001-12-07If this is personal use only and requires an account/pw to download it reallyjmc1-1/+2
needs a LICENSE set to no-redistribution to flag it
2001-11-29Get rid of manually adding "nbX" to PKGNAME when a pkg was changed inhubertf1-2/+2
pkgsrc. Instead, a new variable PKGREVISION is invented that can get bumped independent of DISTNAME and PKGNAME. Example #1: DISTNAME= foo-X.Y PKGREVISION= Z => PKGNAME= foo-X.YnbZ Example #2: DISTNAME= barthing-X.Y PKGNAME= bar-X.Y PKGREVISION= Z => PKGNAME= bar=X.YnbZ (!) On subsequent changes, only PKGREVISION needs to be bumped, no more risk of getting DISTNAME changed accidentally.
2001-11-28Buildlinkify.jlam1-5/+5
2001-11-15add and enable gerbv, gnucap, and mcalc.dmcmahill1-1/+4
2001-11-15initial import of mcalc.dmcmahill5-0/+58
Mcalc is a JavaScript based calculator for accurate microstrip transmission line analysis and synthesis. The electrical parameters may be determined from specified physical parameters, or the physical parameters required to meet a given set of electrical parameters may be found. Much attention has been given to making mcalc the most accurate online based calculator short of a full electromagnetic simulation.
2001-11-15initial import of GnuCapdmcmahill5-0/+291
GnuCap is a general purpose circuit simulator. GnuCap was formerly known as ACS. GnuCap performs nonlinear dc and transient analyses, fourier analysis, and ac analysis linearized at an operating point. It is fully interactive and command driven. It can also be run in batch mode or as a server. The output is produced as it simulates. Spice compatible models for the MOSFET (level 1-7) and diode are included in this release. Since it is fully interactive, it is possible to make changes and re-simulate quickly. The interactive design makes it well suited to the typical iterative design process used it optimizing a circuit design. Unlike Spice, the engine is designed to do true mixed-mode simulation. Most of the code is in place for future support of event driven analog simulation, and true multi-rate simulation. If you are tired of Spice and want a second opinion, you want to play with the circuit and want a simulator that is interactive, you want to study the source code and want something easier to follow than Spice, or you are a researcher working on modeling and want automated model generation tools to make your job easier, try GnuCap.
2001-11-15initial import of gerbv.dmcmahill4-0/+42
Gerber Viewer (gerbv) is a viewer for Gerber files. Gerber files are generated from PCB CAD system and sent to PCB manufacturers as basis for the manufacturing process. The different layers of the PCB are separated into different files. gerbv can load all files at the same time, though it can not show them at the same time. You have to browse through the different layers with the radio buttons on the right side.
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