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dependency bumps.
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Changes include:
* Updated to use qt3
* New functions
* New language translations
* New fonts added
* Many bug fixes
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Gnucap 0.33 release notes (01/12/2003)
This is a bug fix and compatibility release.
0.32 was not widely distributed due to password problems and a heavy
work load, so the release notes are repeated after the current ones.
New features:
1. Add inductance probes, like capacitor.
Bug fixes:
1. Fix xprobe duplicate default arg bug - shows in g++3.2.
2. Fix bug that sometimes caused a crash when changing a model after
analysis.
3. Fix bug that caused an assert to fail (debug build) after removing
a probe from an element.
4. Fix a dumb typo hack bug ddHAS_READLINE. Now history and command
line editing really works. It was working, but somehow the hack
slipped into the release code.
=================================================================
Gnucap 0.32 release notes (09/30/2002)
New features:
1. Series resistance in the diode. It took 5 minutes to do,
so it is embarrasing that it wasn't done before.
2. History and command line editing, using Gnu Readline. Thanks to
Simon Hoffe for sending me the patch.
3. More parameters in the BJT model. This gives it better
compatibility with commercial simulators. These parameters are beyond
Spice 3f5.
4. "M" parameter in diode, BJT and MOS devices. M is the number of
parallel devices. Some commercial simulators have this.
Changes that may or may not be improvements.
1. The definition of the transient option "UIC" has changed. It is
now Spice compatible, which means to not attempt to do any solution or
consistency check. Just apply the values, assuming anything that
isn't specified is 0. The old behavior was to attempt a solution
while holding the IC values.
Bug fixes:
1. voltage sync bug. It still doesn't fix the MOS 2 convergence
problem.
2. Fix memory leak in POLY components.
3. Fix bug in Fourier that sometimes causes overrun (crash) and time
sync errors.
4. Modelgen: fix bug in list parsing.
5. Some changes to eliminate warnings when compiling with g++ 3.1.
6. Use Euler differentiation on first step, because trap used a value
that cannot be known then. Usually, this doesn't make much
difference, but there are a few cases where the error can get
magnified and trigger trapezoidal ringing, leading to a totally bogus
result. It most cases, you could hide it with small enough steps.
These cases should work with default settings now.
7. Fix bug that sometimes caused incorrect handling of initial
conditions (UIC),
8. Fix bug that caused continuing a transient analysis to give
incorrect results.
Significant internal changes:
1. The inductor uses all of the same support functions as the
capacitor, including "integrate", which is now correctly called
"differentiate".
2. Most of the code is in place for named nodes. It mostly works and
can be turned on with the option "namednodes". It is off by default
because it is not complete. Most likely, it will be finished in the
next release.
Some things that are still partially implemented:
1. BSIM models, charge effects, "alpha0" parameter. (computed then
ignored)
2. Configure still doesn't handle everything.
3. The model compiler still requires too much raw coding.
4. Named nodes. If you set the option "namednodes", it will support
named nodes, but some things don't work, so it is off by default.
5. The preliminary IBIS code is now included. For now, it is a
standalone executable, that reads an IBIS file and generates a
netlist. The netlist requires some editing to use, and is not fully
compatible anyway. It is included in hopes of recruiting help in
finishing the project.
Bugs (nothing new, but needs repeating):
1. The transmission line initial conditions are not propagated until
the transient analysis runs.
2. An occasional bogus calculation in MOSFETS occurs when a device is
reversed. This sometimes causes nonconvergence.
3. The "modify" command with multiple arguments seems to take only the
first one. It used to work, but is broken in this release. I am not
sure when it broke.
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This is an emacs major mode for linking verilog code with simulation results
and the Dinotrace waveform viewer.
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rather
make all packages that use linux emulation include bsd.pkg.mk as the
last files just like any normal package.
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From the NEWS file:
* Changes in Dinotrace 9.1i 03/07/2003
*** Display values with appropriate leading 0s. [Dan McMahill]
*** Fix 0 extension of verilog values. [Dominik Strasser, Bill Welch]
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Transcalc is an analysis and synthesis tool for calculating the
electrical and physical properties of different kinds of RF and
microwave transmission lines.
Transcalc was somewhat inspired by the functionality of Agilent
Technologies' commercial program linecalc. Transcalc aspires to be
more functional in the long run and well-documented with appropriate
references to formulas that are used. Transcalc is built using the
GIMP toolkit (GTK) for its GUI interface.
For each type of transmission line, using dialog boxes, you can enter
values for the various parameters, and either calculate its electrical
properties (analyze), or use the given electrical requirements to
sythesize physical parameters of the required transmission line.
Available transmission lines (this list will expand with subsequent
releases):
* microstrip
* rectangular waveguide
* coax
* coupled microstrip
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* You cannot compile with backend anymore, switch is removed. In last
release this caused compilation error due to bit rot.
* Drawing of arcs is a constant headache. Mark Whitis found another
case that I had missed out. Clockwise arcs all of a sudden started
to be drawn as counter-clockwise.
* Arcs with very small angle differences could either be a complete
circle or a very small part of an arc. Calculating the angles with
integers wasn't sufficient, anyhow. They are now doubles all the way.
* Aperture macro primitive 1 was a _filled_ circle.
* Image rotate used to cause warnings that it wasn't implemented. Now
if the file has an image rotate on zero degrees there is no warning
(yes I've seen it).
* Dan McMahill discovered that if you tried to swap with an unused layer
gerbv segfaulted.
* Peter Monta submitted patch for incremental coordinates.
* No traces of Guile left...
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triggered a compiler error. This package now builds and seems to run
on NetBSD-1.6/alpha
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Makefiles simply need to use this value often, for better or for
worse.
(2) Create a new variable FIX_RPATH that lists variables that should
be cleansed of -R or -rpath values if ${_USE_RPATH} is "no". By
default, FIX_RPATH contains LIBS, X11_LDFLAGS, and LDFLAGS, and
additional variables may be appended from package Makefiles.
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been caused by moving to the new guile.
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Quick summary of changes:
- works with guile-1.6.3 now
- Norwegian/Danish/German character fixes
- PNG output now has some of the objects appearing to have the right thickness.
- added Russian translation
- bug fix in postscript output
- non-applicable menu choices are now greyed out
- fixed PADS netlist output bug
- added several components to library
- added multisheet refdes renumber utility
- several other bug fixes.
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portable. Bump PKGREVISION accordingly.
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The previous version was extremely out of date and the distfile is no
longer available.
Many, many changes since the last packaged version. New 'tuner' feature
added. New models added. Several bug fixes too numerous to list.
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are not properly parsed. Bump pkgrev.
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in recent bulk builds.
Release covered-20021214 made. This release is a bug fix release. See list below
for details. Bugs that lead to infinite looping in the score command and segmentation
faults should now be cleared up. Please let me know if there are any other bugs that
need to be addressed before first stable release. Development documentation updated
to match changes in files. Regression suite has been updated quite a bit from last
time. There are now over 125 diagnostics in the regression suite (my goal was to
write about 100 before first stable release).
- Segmentation fault fixes in report command
- Parser can now handle all net types (not just wire). Diagnostics added to regression
suite to verify their proper handling.
- Parser updated to handle net declaration assignments (e.g., wire a = b & c;).
Diagnostics added to verify proper handling.
- Added human-understandable error messages in parser to help identify file and
line number along with a quasi-helpful error message description.
- When parser error is found, Covered exits after parsing phase without continuing
to write CDD file.
- Fixed bug where a multi-bit select expression existed in a module that was
instantiated more than once. Assertion error fired in this case.
- Updated regression suite for VCS testing.
- Fixed bug where parameters were used in modules that were instantiated more than
once.
- Fixed bug that dealt with parameters (see param6.1.v for test case).
- Fixed bug where a delay statement was the last statement in a statement block used
by Covered. Added diagnostics to verify correct behavior.
- Fixed infinite loop problem with db_add_statement function.
- Fixed infinite loop problem with statement_set_stop function.
- Fixed bug with parsing order. When an instance is found for a module that has
already been parsed, the instance was incorrectly being handled. Bug replicated
with instance6.v diagnostic.
- Fixed output of edge-triggered events to add @(...) around the expression (they
were easily confused with other code that could exist on the same line).
- Fixed bug in parser to not allow module to be parsed more than once.
- Fixed bug that lead to an assertion error (see instance6.1.v for test case).
- Fixing bug with calculating list and concatenation lengths when MBIT_SEL
expressions were included.
- Changed Covered's handling of -y directories. Before, all files in these directories
were fed into the parser to look for missing modules. Now, when a module is needed,
the module name is used to find the matching filename in the -y list (basically,
the -y option works like the -y option in Icarus Verilog and VCS). This fix really
streamlined the parsing phase and fixed several bugs.
- Memory declarations are now properly ignored (produced segmentation fault previously).
- Fixed report command to display all lines and expressions in order according to
their line number (the problem is REALLY fixed now).
- Removed hierarchical references from being scored.
All in all, you should notice a huge improvement in the parsing speed, syntax errors are
reported better, more Verilog syntax should be handled properly, the score command will
run a bit faster than before, and the reports should be a bit easier to read. Segmentation
faults and assertion errors should become lesser in number (if not gone altogether?).
I am feeling pretty confident that we are getting close to a stable release as I have
been able to generate a CDD file for a chip that is millions of gates in size (CDD file
was created in the range of 30 - 45 seconds!) Keep the bug reports coming. I have some
things to work on for next release already.
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This is the first packaged (in pkgsrc) snapshot after the verilog-0.7
release.
This snapshot adds preliminary support for real variables to the language
to the features already found in verilog-0.7.
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Many improvements such as support for mixed dielectric systems and several
bitmap generators for common structures to allow quick application of the
tool. Several bug fixes as well. Voltages outside a shield are set to zero
which fixes a reported result in older versions. Many other improvemnts
and bug fixes are listed in the ChangeLog in the distfile.
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have it be automatically included by bsd.pkg.mk if USE_PKGINSTALL is set
to "YES". This enforces the requirement that bsd.pkg.install.mk be
included at the end of a package Makefile. Idea suggested by Julio M.
Merino Vidal <jmmv at menta.net>.
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handled by gnome-libs.
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second time.
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Packages using Guile now all depend on guile14. These packages are
expected to be made depend on newer Guile (1.6.x) when updated in the
future.
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Approved by wiz.
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has been a soname change. Pointed out by fredb.
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Huberts latest bulk-build.
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package and library major bumps therein.
Also match dependency in corresponding buildlink2.mk's for the same reason.
Mmmm, binary packages.
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From pino@dohd.org in PR pkg/19437.
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This release represents many bug fixes, expanded language coverage,
greatly enhanced xilinx fpga synthesis and several performance enhancements.
The complete list is rather long.
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