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2017-02-06Recursive bump for harfbuzz's new graphite2 dependency.wiz10-18/+20
2017-01-28Updated cad/py-simpy to 3.0.10mef3-46/+10
2017-01-28Updated cad/py-gds to 1.1.1mef2-7/+7
2017-01-24Updated cad/py-gds to 1.1mef3-8/+9
2017-01-21Update to pcb-4.0.0dmcmahill7-55/+115
2017-01-20Enable ocefhajny1-1/+2
2017-01-20Import OCE 0.18 as cad/oce, based on wip/oce.fhajny18-0/+13577
2017-01-19Convert all occurrences (353 by my count) ofagc1-3/+3
2017-01-07distfile has vanished. prevent timeout. update MASTER_SITES.zafer1-2/+2
2017-01-063.16.4 (2017/01/04)plunky3-40/+180
2017-01-01Revbump after boost updateadam3-4/+6
2017-01-01Updated cad/klayout to 0.24.9mef3-10/+13
2017-01-01Updated cad/gtkwave to 3.3.79mef2-7/+7
2016-12-22Don't use non-int values for scancodes. Bump revision.joerg3-3/+24
2016-12-20Correction of PKGNAME, GDS2-3.33 to p5-gds2-3.33mef1-1/+2
2016-12-17Updated cad/eagle to 7.7.0mef3-15/+12
2016-12-16Update to version 3.16.0 (released 2016/12/14)plunky9-213/+802
2016-12-16# OpenSCAD 2015.03plunky2-9/+8
2016-12-16Update to patch version 2.1.3plunky2-8/+7
2016-12-10Updated cad/gtkwave to 3.3.78mef2-7/+7
2016-11-25Upgrade USE_LANGUAGES=ada to use lang/gcc5-aux instead of lang/gcc-auxmarino1-1/+2
2016-11-20Restrict a few very memory hungry files to -O1.joerg2-1/+20
2016-10-21distinfo was wrong or distfile updated with the same name ?mef1-5/+5
2016-10-17Updated cad/gtkwave to 3.3.77mef2-7/+7
2016-10-13verilog is no longerjnemeth1-2/+1
2016-10-09Add patch from John D. Baker in PR 51509 to fix 32-bit build.dholland2-1/+18
2016-10-09Add cad/veriwellkamil1-1/+2
2016-10-09Import veriwell-2.8.7 as cad/veriwellkamil4-0/+36
2016-10-09Update MyHDL from 0.8.1 to 0.9.0kamil10-73/+106
2016-10-08cad/verilog has been renamed to cad/iverilogkamil8-186/+0
2016-10-08Switch from cad/verilog to cad/iverilogkamil1-2/+2
2016-10-08Switch from cad/verilog to cad/iverilogkamil1-2/+3
2016-10-08Add cad/iverilog (will replace cad/verilog)kamil1-1/+2
2016-10-08Import iverilog (Icarus Verilog) 10.1.1 as cad/iverilogkamil8-0/+182
2016-10-08Update cad/verilog (icarus verilog) from 0.9.7 to 10.1.1kamil6-135/+42
2016-10-08Update cad/covered from 0.4.7 to 0.7.10kamil5-123/+156
2016-10-08Drop conflict with nonexistent covered-currentkamil1-3/+1
2016-10-08Detach the cad/verilog-current dependencykamil1-3/+3
2016-10-08Drop covered-currentkamil6-273/+0
2016-10-08Detach cad/covered-currentkamil1-2/+1
2016-10-08Remove verilog-currentkamil8-183/+0
2016-10-08Detach cad/verilog-currentkamil1-2/+1
2016-10-07Revbump post boost updateadam3-4/+6
2016-09-25add GCC_REQD+= 4.7 as the package uses -std=c++11 flagplunky1-1/+4
2016-09-25add gettext to USE_TOOLSplunky1-2/+2
2016-09-22Remove redundent/unnecessary .include lines, and PYDISTUTILSPKG= yes, thanks...mef1-5/+1
2016-09-21Fix reversed assignement, pointed out by he@ (thanks !)bouyer3-6/+6
2016-09-20Remove url2pkg marker.wiz1-2/+1
2016-09-19 - Converting PLIST to ${EGG_INFODIR}. Also add/convert .include lang/python/...mef2-8/+11
2016-09-16use -delete for POSIX complianceplunky1-2/+2
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