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LLVM 15.0.4
Changes to the LLVM IR
LLVM now uses opaque pointers. This means that different pointer types like i8*, i32* or void()** are now represented as a single ptr type. See the linked document for migration instructions.
Renamed llvm.experimental.vector.extract intrinsic to llvm.vector.extract.
Renamed llvm.experimental.vector.insert intrinsic to llvm.vector.insert.
The constant expression variants of the following instructions have been removed:
extractvalue
insertvalue
udiv
sdiv
urem
srem
fadd
fsub
fmul
fdiv
frem
Added the support for fmax and fmin in atomicrmw instruction. The comparison is expected to match the behavior of llvm.maxnum.* and llvm.minnum.* respectively.
callbr instructions no longer use blockaddress arguments for labels. Instead, label constraints starting with ! refer directly to entries in the callbr indirect destination list.
Changes to building LLVM
Omitting CMAKE_BUILD_TYPE when using a single configuration generator is now an error. You now have to pass -DCMAKE_BUILD_TYPE=<type> in order to configure LLVM. This is done to help new users of LLVM select the correct type: since building LLVM in Debug mode is very resource intensive, we want to make sure that new users make the choice that lines up with their usage. We have also improved documentation around this setting that should help new users. You can find this documentation here.
Changes to Loop Optimizations
Loop interchange legality and cost model improvements
Changes to the AMDGPU Backend
8 and 16-bit atomic loads and stores are now supported
Changes to the ARM Backend
Added support for the Armv9-A, Armv9.1-A and Armv9.2-A architectures.
Added support for the Armv8.1-M PACBTI-M extension.
Added support for the Armv9-A, Armv9.1-A and Armv9.2-A architectures.
Added support for the Armv8.1-M PACBTI-M extension.
Removed the deprecation of ARMv8-A T32 Complex IT blocks. No deprecation warnings will be generated and -mrestrict-it is now always off by default. Previously it was on by default for Armv8 and off for all other architecture versions.
Added a pass to workaround Cortex-A57 Erratum 1742098 and Cortex-A72 Erratum 1655431. This is enabled by default when targeting either CPU.
Implemented generation of Windows SEH unwind information.
Switched the MinGW target to use SEH instead of DWARF for unwind information.
Added support for the Cortex-M85 CPU.
Added support for a new -mframe-chain=(none|aapcs|aapcs+leaf) command-line option, which controls the generation of AAPCS-compliant Frame Records.
Changes to the DirectX Backend
DirectX has been added as an experimental target. Specify -DLLVM_EXPERIMENTAL_TARGETS_TO_BUILD=DirectX in your CMake configuration to enable it. The target is not packaged in pre-built binaries.
The DirectX backend supports the dxil architecture which is based on LLVM 3.6 IR encoded as bitcode and is the format used for DirectX GPU Shader programs.
Changes to the PowerPC Backend
Common PowerPC improvements: * Add a new post instruction selection pass to generate CTR loops. * Add SSE4 and BMI compatible intrinsics implementation. * Supported 16-byte lock free atomics on PowerPC8 and up. * Supported atomic load/store for pointer types. * Supported stack size larger than 2G * Add __builtin_min/__builtin_max/__abs builtins. * Code generation improvements for splat load/vector shuffle/mulli, etc. * Emit VSX instructions for vector loads and stores regardless of alignment. * The mcpu=future has its own ISA now (FutureISA). * Added the ppc-set-dscr option to set the Data Stream Control Register (DSCR). * Bug fixes.
AIX improvements: * Supported 64 bit XCOFF for integrated-as path. * Supported X86-compatible vector intrinsics. * Program code csect default alignment now is 32-byte. * Supported auxiliary header in integrated-as path. * Improved alias symbol handling.
Changes to the RISC-V Backend
A RISCVRedundantCopyElimination pass was added to remove unnecessary zero copies.
A RISC-V specific CodeGenPrepare pass was added.
The machine outliner was enabled by default for RISC-V at -Oz. Additionally, the newly introduced RISCVMakeCompressible pass will make modify instructions prior to emission at -Oz in order to increase opportunities for the compression with the RISC-V C extension.
Various bug fixes and improvements to code generation for the RISC-V vector extensions.
Various improvements were made to RISC-V specific optimisation passes such as RISCVSExtWRemoval and RISCVMergeBaseOffset.
llc now computes the target ABI based on the target architecture using the same logic as Clang if not explicit ABI is given.
generic is now recognized as a valid CPU name and is mapped to generic-rv32 or generic-rv64 depending on the target triple.
Support for the experimental Zvfh extension was added, enabling half-precision floating point in vectors.
Support for the Zihintpause (Pause Hint) extension.
Assembler and disassembler support for the Zfinx and Zdinx (float / double in integer register) extensions.
Assembler and disassembler support for the Zicbom, Zicboz, and Zicbop cache management operation extensions.
Support for the Zmmul extension (a subextension of the M extension, adding multiplication instructions only).
Assembler and disassembler support for the hypervisor extension and for the Sinval supervisor memory-management extension.
Changes to the X86 Backend
Support half type on SSE2 and above targets following X86 psABI.
Support rdpru instruction on Zen2 and above targets.
During this release, half type has an ABI breaking change to provide the support for the ABI of _Float16 type on SSE2 and above following X86 psABI. (D107082)
The change may affect the current use of half includes (but is not limited to):
Frontends generating half type in function passing and/or returning arguments.
Downstream runtimes providing any half conversion builtins assuming the old ABI.
Projects built with LLVM 15.0 but using early versions of compiler-rt.
When you find failures with half type, check the calling conversion of the code and switch it to the new ABI.
Changes to the LLVM tools
(Experimental) llvm-symbolizer now has --filter-markup to filter Symbolizer Markup into human-readable form.
llvm-objcopy has removed support for the legacy zlib-gnu format.
llvm-objcopy now allows --set-section-flags src=... --rename-section src=tst. --add-section=.foo1=... --rename-section=.foo1=.foo2 now adds .foo1 instead of .foo2.
New features supported on AIX for llvm-ar:
AIX big-format archive write operation (D123949)
A new object mode option, -X , to specify the type of object file llvm-ar should operate upon (D127864)
Read global symbols of AIX big archive (D124865)
New options supported for llvm-nm:
-X, to specify the type of object file that llvm-nm should examine (D118193)
--export-symbols, to create a list of symbols to export (D112735)
The LLVM gold plugin now ignores bitcode from the .llvmbc section of ELF files when doing LTO. https://github.com/llvm/llvm-project/issues/47216
llvm-objcopy now supports 32 bit XCOFF.
llvm-objdump: improved assembly printing for XCOFF.
llc now parses code-model attribute from input file.
Changes to LLDB
The “memory region” command now has a “–all” option to list all memory regions (including unmapped ranges). This is the equivalent of using address 0 then repeating the command until all regions have been listed.
Added “–show-tags” option to the “memory find” command. This is off by default. When enabled, if the target value is found in tagged memory, the tags for that memory will be shown inline with the memory contents.
Various memory related parts of LLDB have been updated to handle non-address bits (such as AArch64 pointer signatures):
“memory read”, “memory write” and “memory find” can now be used with addresses with non-address bits.
All the read and write memory methods on SBProccess and SBTarget can be used with addreses with non-address bits.
When printing a pointer expression, LLDB can now dereference the result even if it has non-address bits.
The memory cache now ignores non-address bits when looking up memory locations. This prevents us reading locations multiple times, or not writing out new values if the addresses have different non-address bits.
LLDB now supports reading memory tags from AArch64 Linux core files.
LLDB now supports the gnu debuglink section for reading debug information from a separate file on Windows
LLDB now allows selecting the C++ ABI to use on Windows (between Itanium, used for MingW, and MSVC) via the plugin.object-file.pe-coff.abi setting. In Windows builds of LLDB, this defaults to the style used for LLVM’s default target.
Other Changes
The code for the LLVM Visual Studio integration has been removed. This had been obsolete and abandoned since Visual Studio started including an integration by default in 2019.
Added the unwinder, personality, and helper functions for exception handling on AIX. (D100132) (D100504)
PGO on AIX: A new implementation that requires linker support (__start_SECTION/__stop_SECTION symbols) available on AIX 7.2 TL5 SP4 and AIX 7.3 TL0 SP2.
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Updated in wip by @wiz and myself.
14.0.6
-This release is a bug-fix release and is API and ABI compatible with 14.0.0.
This release fixes a bug that was introduced in 14.0.5.
This will likely be the last 14.0.x release.
14.0.5
-This release is a bug-fix release and is API and ABI compatible with 14.0.0.
Note that we have adopted a new release schedule for the project, so there
will be a new bug-fix release (14.0.x) every 2 weeks.
14.0.5 is the last planned release, but we may do a 14.0.6 release if there
are critical issues found in 14.0.5.
14.0.4
-This release is a bug-fix release and is API and ABI compatible with 14.0.0.
14.0.0
Changes to the LLVM IR
Using the legacy pass manager for the optimization pipeline is deprecated
and will be removed after LLVM 14. In the meantime, only minimal effort will
be made to maintain the legacy pass manager for the optimization pipeline.
Max allowed integer type was reduced from 2^24-1 bits to 2^23 bits.
Max allowed alignment was increased from 2^29 to 2^32.
Changes to building LLVM
Building LLVM with Visual Studio now requires version 2019 or later.
Changes to the AArch64 Backend
Added support for the Armv9-A, Armv9.1-A and Armv9.2-A architectures.
The compiler now recognises the “tune-cpu” function attribute to support
the use of the -mtune frontend flag. This allows certain scheduling features
and optimisations to be enabled independently of the architecture.
If the “tune-cpu” attribute is absent it tunes according to the
“target-cpu”.
Fixed relocations against temporary symbols (e.g. in jump tables and
constant pools) in large COFF object files.
Auto-vectorization now targets SVE by default when available.
Changes to the ARM Backend
Added support for the Armv9-A, Armv9.1-A and Armv9.2-A architectures.
Added support for the Armv8.1-M PACBTI-M extension.
Changed the assembly comment string for MSVC targets to @ (consistent with
the MinGW and ELF targets), freeing up ; to be used as statement separator.
Changes to the PowerPC Target
Linux improvements:
Provided a number of builtins for compatibility with the XL compiler.
Allow MMA builtin types in pre-P10 compilation units.
Add support for Return Oriented Programming (ROP) protection for 32 bit.
Refactored code to use more inclusive language.
Switched to LLD as the default linker for pre-built Linux binaries.
Enabled IEEE quad long double on Linux via PPC_LINUX_DEFAULT_IEEELONGDOUBLE
in cmake config.
Added __ibm128 type to represent IBM double-double format, also
available as __attribute__((mode(IF))).
-mfloat128 can now be used in Linux subtargets with VSX enabled.
Added quadword atomic load/store support in codegen; not enabled by default.
Codegen improvements for splat load, byval parameter, stack lowering, etc.
Implemented P10 instruction scheduling model.
Implemented P10 instruction fusion pairs.
Improved handling of #pragma clang loop unroll_and_jam.
Various bug fixes.
AIX Support/improvements:
Variadic (ellipsis) functions with C complex types are now supported.
Added toc-data support for AIX 64-bit.
Added toc-data support for read-only globals.
Updated default target on AIX from pwr4 to pwr7.
AIX 64-bit code generation now uses fast-isel for O0.
Added DWARF support for 32-bit XCOFF.
Changes to the RISC-V Target
Codegen improvements for RV64 around the selection of addw/subw/mulw/slliw
instructions and removal of redundant sext.w instructions (using the new
RISCVSExtWRemoval pass).
The various RISC-V vector extensions were updated to version 1.0 and are no
longer experimental.
The Zba, Zbb, Zbc, and Zbs bit-manipulation extensions were updated to
version 1.0 and are no longer experimental.
Added MC layer support for the ratified scalar cryptography extensions.
The Zfh and Zfhmin extensions for half-precision floating point were updated
to version 1.0 and are no longer experimental.
Added support for the .insn directive.
Various improvements to immediate materialisation, including when
bit-manipulation extensions are enabled. Additionally, the constant pool is
now used for large integers.
Added support for constrained FP intrinsics for scalar types.
Added support for CSRs introduced in the Sscofpmf, Smstateen, and Sstc
extensions.
The experimental ‘Zbproposedc’ extension was removed, as was the ‘B’
extension (including all bit-manipulation sub-extensions). Individual ‘Zb*’
extensions should be used instead.
Changes to the X86 Target
Support for AVX512-FP16 instructions has been added.
Removed incomplete support for Intel MPX. (D111517)
Changes to the AMDGPU Target
Changes to the Windows Target
Changed how the .pdata sections refer to the code they’re describing, to
avoid conflicting unwind info if weak symbols are overridden.
Fixed code generation for calling support routines for converting 128 bit
integers from/to floats on x86_64.
The preferred path separator form (backslashes or forward slashes) can be
configured in Windows builds of LLVM now, with the
LLVM_WINDOWS_PREFER_FORWARD_SLASH CMake option. This defaults to true in
MinGW builds of LLVM.
Set proper COFF symbol types for function aliases (e.g. for Itanium C++
constructors), making sure that GNU ld exports all of them correctly as
functions, not data, when linking a DLL.
Handling of temporary files on more uncommon file systems (network mounts,
ramdisks) on Windows is fixed now (which previously either errored out or
left stray files behind).
Changes to the C API
LLVMSetInstDebugLocation has been deprecated in favor of the more general
LLVMAddMetadataToInst.
Fixed building LLVM-C.dll for i386 targets with MSVC, which had been broken
since the LLVM 8.0.0 release.
Changes to the LLVM tools
llvm-cov: -name-allowlist is now accepted in addition to -name-whitelist.
-name-whitelist is marked as deprecated and to be removed in future
releases.
llvm-ar now supports --thin for creating a thin archive. The modifier T has
a different meaning in some ar implementations. (D116979)
llvm-ar now supports reading big archives for XCOFF. (D111889)
llvm-nm now demangles Rust symbols. (D111937)
llvm-objcopy’s ELF port now avoids reordering section headers to preserve
st_shndx fields of dynamic symbols. (D107653)
llvm-objcopy now supports --update-section for ELF and Mach-O. (D112116)
(D117281)
llvm-objcopy now supports --subsystem for PE/COFF. (D116556)
llvm-objcopy now supports mips64le relocations for ELF. (D115635)
llvm-objcopy --rename-section now renames relocation sections together with
their targets. (D110352)
llvm-objdump --symbolize-operands now supports PowerPC. (D114492)
llvm-objdump -p now dumps PE header. (D113356)
llvm-objdump -R now supports ELF position-dependent executables. (D110595)
llvm-objdump -T now prints symbol versions. (D108097)
llvm-readobj: Improved printing of symbols in Windows unwind data.
llvm-readobj now supports --elf-output-style=JSON for JSON output and
--pretty-print for pretty printing of this output. (D114225)
llvm-readobj now supports several dump styles (--needed-libs, --relocs,
--syms) for XCOFF.
llvm-symbolizer now supports –debuginfod. (D113717)
llvm-cov now accepts “allowlist” spelling for -name-allowlist.
llvm-nm now supports XCOFF object files.
Added --needed-libs, aux header, and symbols support in llvm-readobj.
Added --symbolize-operands support in llvm-objdump.
Tools that read archive files now support reading AIX big format archive
files.
Added dump section support in obj2yaml.
Added yaml2obj support for 64-bit XCOFF.
Changes to LLDB
A change in Clang’s type printing has changed the way LLDB names array types
(from int [N] to int[N]) - LLDB pretty printer type name matching code may
need to be updated to handle this.
The following commands now ignore non-address bits (e.g. AArch64 pointer
signatures) in address arguments. In addition, non-address bits will not be
shown in the output of the commands.
memory find
memory read
memory region (see below)
memory tag read
memory tag write
The memory region command and GetMemoryRegionInfo API method now ignore
non-address bits in the address parameter. This also means that on systems
with non-address bits the last (usually unmapped) memory region will not
extend to 0xF…F. Instead it will end at the end of the mappable range that
the virtual address size allows.
The memory read command has a new option --show-tags. Use this option to
show memory tags beside the contents of tagged memory ranges.
Fixed continuing from breakpoints and singlestepping on Windows on ARM/ARM64.
LLDB has been included in Windows on ARM64 binary release with Python
support disabled.
Changes to BOLT
BOLT project is added to the LLVM monorepo. BOLT is a post-link optimizer
developed to speed up large applications. Build and usage instructions are
given in README.
Additional Information
A wide variety of additional information is available on the LLVM web page, in
particular in the documentation section. The web page also contains versions of
the API documentation which is up-to-date with the Git version of the source
code. You can access versions of these documents specific to this release by
going into the llvm/docs/ directory in the LLVM tree.
If you have any questions or comments about LLVM, please feel free to contact
us via the mailing lists.
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PKGSRC_LLVM_PTHREADLIB. LLVM insists on 64-bit atomics, and
on NetBSD/powerpc we don't have that natively, so have to rely
on -latomic from gcc. This library is linked with -lpthread, so
the cmake logic to detect whether -lpthread is included in the C
library says "yes", leading to later breakage when clang is being
built. On NetBSD, set PKGSRC_LLVM_PTHREADLIB to -lpthread.
OK'ed by wiz@,
bump PKGREVISION.
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12.0.1:
Non-comprehensive list of changes in this release
The ConstantPropagation pass was removed. Users should use the InstSimplify pass instead.
Changes to the LLVM IR
Added the byref attribute to better represent argument passing for the amdgpu_kernel calling convention.
Added type parameter to the sret attribute to continue work on removing pointer element types.
The llvm.experimental.vector.reduce family of intrinsics have been renamed to drop the “experimental” from the name, reflecting their now fully supported status in the IR.
Changes to building LLVM
The internal llvm-build Python script and the associated LLVMBuild.txt files used to describe the LLVM component structure have been removed and replaced by a pure CMake approach, where each component stores extra properties in the created targets. These properties are processed once all components are defined to resolve library dependencies and produce the header expected by llvm-config.
Changes to TableGen
The new “TableGen Programmer’s Reference” replaces the “TableGen Language Introduction” and “TableGen Language Reference” documents.
The syntax for specifying an integer range in a range list has changed. The old syntax used a hyphen in the range (e.g., {0-9}). The new syntax uses the “…” range punctuation (e.g., {0...9}). The hyphen syntax is deprecated.
Changes to the AArch64 Backend
Lots of improvements to generation of Windows unwind data; the unwind data is optimized and written in packed form where possible, reducing the size of unwind data (pdata and xdata sections) by around 60% compared with LLVM 11. The generation of prologs/epilogs is tweaked when targeting Windows, to increase the chances of being able to use the packed unwind info format.
Support for creating Windows unwind data using .seh_* assembler directives.
Produce proper assembly output for the Windows target, including :lo12: relocation specifiers, to allow the assembly output to actually be assembled.
Changed the assembly comment string for MSVC targets to // (consistent with the MinGW and ELF targets), freeing up ; to be used as statement separator.
Changes to the ARM Backend
Changes to the MIPS Target
Changes to the PowerPC Target
Optimization:
Made improvements to loop unroll-and-jam including fix to respect user provided #pragma unroll-and-jam for loops on targets other than ARM.
Improved PartialInliner allowing it to handle code regions in a switch statements.
Improved PGO support on AIX by building and linking with compiler-rt profile library.
Add support for Epilogue Vectorization and enabled it by default.
CodeGen:
POWER10 support * Implementation of PC Relative addressing in LLD including the associated
linker optimizations.
Add support for the new matrix multiplication (MMA) instructions to Clang and LLVM.
Implementation of Power10 builtins.
Scheduling enhancements * Add a new algorithm to cluster more loads/stores if the DAG is not too
complicated.
Enable the PowerPC scheduling heuristic for Power10.
Target dependent passes tuning * Enhance LoopStrengthReduce/PPCLoopInstrFormPrep pass for PowerPC,
especially for P10 intrinsics.
Enhance machine combiner pass to reduce register pressure for PowerPC.
Improve MachineSink to do more sinking based on register pressure and alias analysis.
General improvements * Complete the constrained floating point operations support. * Improve the llvm-exegesis support. * Improve the stack clash protection to probe the gap between stackptr and
realigned stackptr.
Improve the IEEE long double support for Power8.
Enable MemorySSA for LoopSink.
Enhance LLVM debugging functionality via options such as -print-changed and -print-before-changed.
Add builtins for Power9 (i.e. darn, xvtdiv, xvtsqrt etc).
Add options to disable all or part of LoopIdiomRecognizePass.
Add support for printing the DDG in DOT form allowing for visual inspection of the Data Dependence Graph.
Remove the QPX support.
Significant number of bug fixes including all the fixes necessary to achieve a clean test run for Julia.
AIX Support:
Compiler-rt support * Add support for building compiler-rt for AIX and 32-bit Power targets. * Made compiler-rt the default rtlib for AIX.
General Improvements * Enable the AIX extended AltiVec ABI under option -mabi=vec-extabi. * Add partial C99 complex type support. * Implemente traceback table for functions (encodes vector information, emits exception handling).
Implemente code generation for C++ dynamic initialization and finalization. of non-local variables for use with the -bcdtors option of the AIX linker.
Add new option -mignore-xcoff-visibility.
Enable explicit sections on AIX.
Enable -f[no-]data-sections on AIX and set -fdata-sections to be the default on AIX.
Enable -f[no-]function-sections.
Add support for relocation generation using the large code model.
Add pragma align natural and sorted out pragma pack stack effect.
Changes to the X86 Target
The ‘mpx’ feature was removed from the backend. It had been removed from clang frontend in 10.0. Mention of the ‘mpx’ feature in an IR file will print a message to stderr, but IR should still compile.
Support for -march=alderlake, -march=sapphirerapids, -march=znver3 and -march=x86-64-v[234] has been added.
The assembler now has support for {disp32} and {disp8} pseudo prefixes for controlling displacement size for memory operands and jump displacements. The assembler also supports the .d32 and .d8 mnemonic suffixes to do the same.
A new function attribute “tune-cpu” has been added to support -mtune like gcc. This allows microarchitectural optimizations to be applied independent from the “target-cpu” attribute or TargetMachine CPU which will be used to select Instruction Set. If the attribute is not present, the tune CPU will follow the target CPU.
Support for HRESET instructions has been added.
Support for UINTR instructions has been added.
Support for AVXVNNI instructions has been added.
Changes to the AMDGPU Target
The new byref attribute is now the preferred method for representing aggregate kernel arguments.
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8.0.0:
Non-comprehensive list of changes in this release
* The llvm-cov tool can now export lcov trace files using the -format=lcov option of the export command.
* The add_llvm_loadable_module CMake macro has been removed. The add_llvm_library macro with the MODULE argument now provides the same functionality. See Writing an LLVM Pass.
* For MinGW, references to data variables that might need to be imported from a dll are accessed via a stub, to allow the linker to convert it to a dllimport if needed.
* Added support for labels as offsets in .reloc directive.
* Support for precise identification of X86 instructions with memory operands, by using debug information. This supports profile-driven cache prefetching. It is enabled with the -x86-discriminate-memops LLVM Flag.
* Support for profile-driven software cache prefetching on X86. This is part of a larger system, consisting of: an offline cache prefetches recommender, AutoFDO tooling, and LLVM. In this system, a binary compiled with -x86-discriminate-memops is run under the observation of the recommender. The recommender identifies certain memory access instructions by their binary file address, and recommends a prefetch of a specific type (NTA, T0, etc) be performed at a specified fixed offset from such an instruction’s memory operand. Next, this information needs to be converted to the AutoFDO syntax and the resulting profile may be passed back to the compiler with the LLVM flag -prefetch-hints-file, together with the exact same set of compilation parameters used for the original binary. More information is available in the RFC.
* Windows support for libFuzzer (x86_64).
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6.0.1:
Non-comprehensive list of changes in this release
Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper.
The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use.
The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget.
The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost.
Significantly improved quality of CodeView debug info for Windows.
Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer).
Changes to the LLVM IR
----------------------
The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort.
Changes to the AArch64 Target
-----------------------------
Enabled the new GlobalISel instruction selection framework by default at -O0.
Changes to the ARM Target
-------------------------
Support for enabling SjLj exception handling on platforms where it isn’t the default.
Changes to the Hexagon Target
-----------------------------
The Hexagon backend now supports V65 ISA.
The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version.
The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future.
The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled.
Changes to the MIPS Target
--------------------------
Fixed numerous bugs:
fpowi on MIPS64 giving incorrect results when used with a negative integer.
Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash.
Fixed a conversion bug when using the DSP ASE.
Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used.
Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions.
Fixed a crash when using a type of unknown size with gp relative addressing.
Corrected the j macro for microMIPS.
Corrected the encoding of movep for microMIPS32r6.
Fixed an issue with the usage of insert instructions having an invalid set of operands.
Fixed an issue where TLS symbols were not marked as such.
Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores.
Corrected the ELF headers when using the DSP ASE.
New features:
The long branch pass now generates some R6 specific instructions when targeting MIPSR6.
The delay slot filler now performs more branch conversions if delay slots cannot be filled.
The MIPS MT ASE is now fully supported.
Added support for the lapc pseudo instruction.
Improved the selection of multiple instructions (dext, nmadd, nmsub).
Further improved microMIPS codesize reduction.
Deprecation notices:
microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed.
Changes to the SystemZ Target
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During this release the SystemZ target has:
Added support for 128-bit atomic operations.
Added support for the “o” constraint for inline asm statements.
Changes to the X86 Target
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During this release the X86 target has:
Added support for enabling SjLj exception handling on platforms where it isn’t the default.
Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI.
Added support for Intel Icelake CPU.
Fixed some X87 codegen bugs.
Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs.
Improved scheduler model for AMD Jaguar CPUs.
Improved llvm-mc’s disassembler for some EVEX encoded instructions.
Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions.
Improved codegen for memory comparisons
Improved codegen for i32 vector multiplies
Improved codegen for scalar integer absolute values
Improved codegen for vector integer rotations (XOP and AVX512)
Improved codegen of data being transferred between GPRs and K-registers.
Improved codegen for vector truncations.
Improved folding of address computations into gather/scatter instructions.
Gained initial support recognizing variable shuffles from vector element extracts and inserts.
Improved documentation for SSE/AVX intrinsics in intrin.h header files.
Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
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5.0.0:
Non-comprehensive list of changes in this release
* LLVM’s WeakVH has been renamed to WeakTrackingVH and a new WeakVH has been introduced. The new WeakVH nulls itself out on deletion, but does not track values across RAUW.
* A new library named BinaryFormat has been created which holds a collection of code which previously lived in Support. This includes the file_magic structure and identify_magic functions, as well as all the structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file formats.
* The tool llvm-pdbdump has been renamed llvm-pdbutil to better reflect its nature as a general purpose PDB manipulation / diagnostics tool that does more than just dumping contents.
* The BBVectorize pass has been removed. It was fully replaced and no longer used back in 2014 but we didn’t get around to removing it. Now it is gone. The SLP vectorizer is the suggested non-loop vectorization pass.
* A new tool opt-viewer.py has been added to visualize optimization remarks in HTML. The tool processes the YAML files produced by clang with the -fsave-optimization-record option.
* A new CMake macro LLVM_REVERSE_ITERATION has been added. If enabled, all supported unordered LLVM containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by iteration of unordered containers. Currently, it supports reverse iteration of SmallPtrSet and DenseMap.
* A new tool llvm-dlltool has been added to create short import libraries from GNU style definition files. The tool utilizes the PE COFF SPEC Import Library Format and PE COFF Auxiliary Weak Externals Format to achieve compatibility with LLD and MSVC LINK.
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under NetBSD. Bump PKGREVISION
Rust language 1.20.0 uses these options and Rust build system uses it
as '-l tinfo' and our wrapper does not handle this.
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