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@comment $NetBSD: PLIST,v 1.5 2006/05/04 16:58:05 drochner Exp $
${PYSITELIB}/myhdl/_Cosimulation.py
${PYSITELIB}/myhdl/_Cosimulation.pyc
${PYSITELIB}/myhdl/_Cosimulation.pyo
${PYSITELIB}/myhdl/_Signal.py
${PYSITELIB}/myhdl/_Signal.pyc
${PYSITELIB}/myhdl/_Signal.pyo
${PYSITELIB}/myhdl/_Simulation.py
${PYSITELIB}/myhdl/_Simulation.pyc
${PYSITELIB}/myhdl/_Simulation.pyo
${PYSITELIB}/myhdl/_Waiter.py
${PYSITELIB}/myhdl/_Waiter.pyc
${PYSITELIB}/myhdl/_Waiter.pyo
${PYSITELIB}/myhdl/__init__.py
${PYSITELIB}/myhdl/__init__.pyc
${PYSITELIB}/myhdl/__init__.pyo
${PYSITELIB}/myhdl/_always.py
${PYSITELIB}/myhdl/_always.pyc
${PYSITELIB}/myhdl/_always.pyo
${PYSITELIB}/myhdl/_always_comb.py
${PYSITELIB}/myhdl/_always_comb.pyc
${PYSITELIB}/myhdl/_always_comb.pyo
${PYSITELIB}/myhdl/_bin.py
${PYSITELIB}/myhdl/_bin.pyc
${PYSITELIB}/myhdl/_bin.pyo
${PYSITELIB}/myhdl/_cell_deref.py
${PYSITELIB}/myhdl/_cell_deref.pyc
${PYSITELIB}/myhdl/_cell_deref.pyo
${PYSITELIB}/myhdl/_concat.py
${PYSITELIB}/myhdl/_concat.pyc
${PYSITELIB}/myhdl/_concat.pyo
${PYSITELIB}/myhdl/_delay.py
${PYSITELIB}/myhdl/_delay.pyc
${PYSITELIB}/myhdl/_delay.pyo
${PYSITELIB}/myhdl/_enum.py
${PYSITELIB}/myhdl/_enum.pyc
${PYSITELIB}/myhdl/_enum.pyo
${PYSITELIB}/myhdl/_extractHierarchy.py
${PYSITELIB}/myhdl/_extractHierarchy.pyc
${PYSITELIB}/myhdl/_extractHierarchy.pyo
${PYSITELIB}/myhdl/_instance.py
${PYSITELIB}/myhdl/_instance.pyc
${PYSITELIB}/myhdl/_instance.pyo
${PYSITELIB}/myhdl/_intbv.py
${PYSITELIB}/myhdl/_intbv.pyc
${PYSITELIB}/myhdl/_intbv.pyo
${PYSITELIB}/myhdl/_isGenSeq.py
${PYSITELIB}/myhdl/_isGenSeq.pyc
${PYSITELIB}/myhdl/_isGenSeq.pyo
${PYSITELIB}/myhdl/_join.py
${PYSITELIB}/myhdl/_join.pyc
${PYSITELIB}/myhdl/_join.pyo
${PYSITELIB}/myhdl/_misc.py
${PYSITELIB}/myhdl/_misc.pyc
${PYSITELIB}/myhdl/_misc.pyo
${PYSITELIB}/myhdl/_simulator.py
${PYSITELIB}/myhdl/_simulator.pyc
${PYSITELIB}/myhdl/_simulator.pyo
${PYSITELIB}/myhdl/_toVerilog/__init__.py
${PYSITELIB}/myhdl/_toVerilog/__init__.pyc
${PYSITELIB}/myhdl/_toVerilog/__init__.pyo
${PYSITELIB}/myhdl/_toVerilog/_analyze.py
${PYSITELIB}/myhdl/_toVerilog/_analyze.pyc
${PYSITELIB}/myhdl/_toVerilog/_analyze.pyo
${PYSITELIB}/myhdl/_toVerilog/_convert.py
${PYSITELIB}/myhdl/_toVerilog/_convert.pyc
${PYSITELIB}/myhdl/_toVerilog/_convert.pyo
${PYSITELIB}/myhdl/_traceSignals.py
${PYSITELIB}/myhdl/_traceSignals.pyc
${PYSITELIB}/myhdl/_traceSignals.pyo
${PYSITELIB}/myhdl/_unparse.py
${PYSITELIB}/myhdl/_unparse.pyc
${PYSITELIB}/myhdl/_unparse.pyo
${PYSITELIB}/myhdl/_util.py
${PYSITELIB}/myhdl/_util.pyc
${PYSITELIB}/myhdl/_util.pyo
@dirrm ${PYSITELIB}/myhdl/_toVerilog
@dirrm ${PYSITELIB}/myhdl
|
