summaryrefslogtreecommitdiff
path: root/cad/verilog
ModeNameSize
-rw-r--r--DESCR753logplain
-rw-r--r--Makefile820logplain
-rw-r--r--PLIST614logplain
-rw-r--r--distinfo231logplain
d---------patches36logplain
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-02 19:38:38 +0000