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$NetBSD: patch-ad,v 1.2 2002/08/27 03:00:13 dmcmahill Exp $
Add Verilog and Verilog-A
--- ../lgrindef.orig Tue Aug 4 09:01:00 1998
+++ ../lgrindef Mon Aug 26 22:54:31 2002
@@ -685,4 +685,75 @@
tk_popup tkwait toplevel trace unknown unset update uplevel upvar while winfo wm:
+# verilog. Written by Dan McMahill <dmcmahill@netbsd.org>
+Verilog:\
+ :pb=\dmodule\d?\p:np=\)\d;:bb=begin\d:be=end\d:\
+ :cb=/*:ce=*/:sb=":se=\e":\
+ :tl:ab=//:ae=$:id=_$`:\
+ :tb=%%:te=%%:mb=%\$:me=\$%:vb=%\|:ve=\|%:\
+ :kw=always and assign attribute begin buf bufif0 bufif1 case casex \
+ casez cmos deassign default defparam disable edge else end endattribute \
+ endcase endfunction endmodule endprimitive endspecify \
+ endtable endtask event for force forever fork function highz0 highz1 if initial \
+ inout input integer join large macromodule medium module nand negedge nmos nor \
+ not notif0 notif1 or output parameter pmos posedge primitive pull0 pull1 \
+ pulldown pullup rcmos real realtime reg release repeat rnmos rpmos rtran \
+ rtranif0 rtranif1 scalared signed small specify specparam strength strong0 \
+ strong1 supply0 supply1 table task time tran tranif0 tranif1 tri tri0 tri1 \
+ triand trior trireg unsigned vectored wait wand weak0 weak1 while wire wor \
+ xnor xor\
+ $bitstoreal $countdrivers $display $fclose $fdisplay $finish $fmonitor \
+ $fopen $fstrobe $fwrite $getpattern $history $incsave $input $itor $key \
+ $list $log $monitor $monitoroff $monitoron $nokey $time \
+ `accelerate `autoexpand_vectornets `celldefine `default_nettype `define \
+ `else `endcelldefine `endif `endprotect `endprotected `expand_vectornets \
+ `ifdef `include `noaccelerate `noexpand_vectornets `noremove_gatenames \
+ `nounconnected_drive `protect `protected `remove_gatenames `remove_netnames \
+ `resetall `timescale `unconnected_drive:
+
+# VerilogA. Written by Dan McMahill <dmcmahill@netbsd.org>
+#
+# the keywords were from appendix E of
+# the Affirma Verilog-A Language Reference, Dec. 1999
+#
+# the ` compiler directives were from page 11-2 of
+# the Affirma Verilog-A Language Reference, Dec. 1999
+#
+# the $ simulator functions were from chapter 9
+# the Affirma Verilog-A Language Reference, Dec. 1999
+VerilogA:\
+ :pb=\dmodule\d?\p:np=\)\d;:bb=begin\d:be=end\d:\
+ :cb=/*:ce=*/:sb=":se=\e":\
+ :tl:ab=//:ae=$:id=_$`:\
+ :tb=%%:te=%%:mb=%\$:me=\$%:vb=%\|:ve=\|%:\
+ :kw=abs abstol access acos ac_stim always analog analysis and asin \
+ asinh assign atan atan2 atanh begin bound_step branch buf bufif0 \
+ bufif1 case casex \
+ casez cmos cos cosh cross ddt ddt_nature deassign default defparam \
+ disable discipline discontinuity edge else \
+ end enddiscipline \
+ endcase endfunction endmodule endnature endprimitive endspecify \
+ endtable endtask event exclude exp final_step flicker_noise flow for \
+ force forever fork from function generate ground highz0 highz1 hypot \
+ idt idtmod idt_nature if ifnone inf initial initial_step\
+ inout input integer join laplace_nd laplace_np laplace_zd laplace_zp \
+ large last_crossing ln log macromodule max medium min module nand \
+ nature negedge nmos noise_table nor \
+ not notif0 notif1 or output parameter pmos posedge potential pow \
+ primitive pull0 pull1 \
+ pulldown pullup rcmos real realtime reg release repeat rnmos rpmos rtran \
+ rtranif0 rtranif1 scalared sin sinh slew small specify specparam sqrt \
+ strong0 \
+ strong1 supply0 supply1 table taan tanh task temperature time timer \
+ tran tranif0 tranif1 transition tri tri0 tri1 \
+ triand trior trireg units vectored vt wait wand weak0 weak1 while \
+ white_noise wire wor \
+ xnor xor zi_nd zi_np zi_nd zi_zp \
+ $realtime $temperature $vt $random $dist_uniform $dist_normal \
+ $dist_exponential $dist_poisson $dist_chi_square $dist_t $dist_erlang \
+ $limexp \
+ $strobe $display $pwr $fopen $fstrobe $fdisplay $fclose \
+ $finish $stop \
+ `define `undef `ifdef `include `timescale `resetall `default_nodetype:
+
# JL - Added visbasic 6 Aug 1996. Note: this is not complete!
@@ -748,4 +819,6 @@
:pro=prolog:\
:m=matlab:\
+ :v=verilog:\
+ :va=veriloga:\
:f=f77:F=f77:for=f77:
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