Imported Upstream version 4.2-build2006upstream/4.2-build2006upstream

14 files changed, 15813 insertions, 0 deletions

diff --git a/kernel/drv/oss_envy24/.config b/kernel/drv/oss_envy24/.config
new file mode 100644
index 0000000..5280084
--- /dev/null
+++ b/kernel/drv/oss_envy24/.config
@@ -0,0 +1 @@
+platform=i86pc
diff --git a/kernel/drv/oss_envy24/.devices b/kernel/drv/oss_envy24/.devices
new file mode 100644
index 0000000..cc44831
--- /dev/null
+++ b/kernel/drv/oss_envy24/.devices
@@ -0,0 +1,13 @@
+oss_envy24	pci1412,1712	Generic ENVY24 based device
+oss_envy24	pcs1412,d630	M Audio Delta 1010
+oss_envy24	pcs1412,d631	M Audio Delta DiO 2496
+oss_envy24	pcs1412,d632	M Audio Delta 66
+oss_envy24	pcs1412,d633	M Audio Delta 44
+oss_envy24	pcs1412,d634	M Audio Audiophile 2496
+oss_envy24	pcs1412,d635	M Audio Delta TDIF
+oss_envy24	pcs1412,d638	M Audio Delta 410
+oss_envy24	pcs1412,d63b	M Audio Delta 1010LT
+oss_envy24	pcs153b,1115	Terratec EWS88MT
+oss_envy24	pcs153b,112b	Terratec EWS88D
+oss_envy24	pcs153b,1130	Terratec EWX 24/96
+oss_envy24	pcs153b,1138	Terratec DMX 6Fire
diff --git a/kernel/drv/oss_envy24/.name b/kernel/drv/oss_envy24/.name
new file mode 100644
index 0000000..d9991f3
--- /dev/null
+++ b/kernel/drv/oss_envy24/.name
@@ -0,0 +1 @@
+VIA Envy24 (ICE1712) sound chipset
diff --git a/kernel/drv/oss_envy24/.params b/kernel/drv/oss_envy24/.params
new file mode 100644
index 0000000..d98c9f8
--- /dev/null
+++ b/kernel/drv/oss_envy24/.params
@@ -0,0 +1,80 @@
+int envy24_skipdevs = 2;
+/*
+ * envy24_skipdevs: By default OSS creates an audio device file for each
+ * stereo pair. However it's possible to change OSS to create a device file
+ * for each input/output channel. See also the envy24_force_mono option
+ * if you want to set the card to mono-only mode.
+ * Values: 1 to 8. Default is 2 (stereo mode).
+ *
+ * Note that the application(s) using the device files can request any number
+ * of channels regardless of the envy24_skipdevs option.
+ */
+int envy24_force_mono = 0;
+/*
+ * envy24_force_mono: Forces all device files to work only in mono mode
+ * (to be used together with envy24_skipdevs=1). This option is necessary
+ * with some software packages that otherwise open the devices in stereo mode.
+ * There is no need to use this option with properly implemented applications.
+ * Values: 0 (default) any number of channels can be used, 1 means that
+ * the device files will only be available in mono mode.
+ *
+ * Note that even envy24_force_mono=1 the application can request and get
+ * stereo. In this way both channel signals will be identical.
+ */
+int envy24_swapdevs = 0;
+/*
+ * envy24_swapdevs: By default OSS will create the output device files before
+ * the recording ones. Some applications may expect input devices to be before 
+ * the output ones.
+ * Values: 0=outputs before inputs (default), 1=inputs before outputs.
+ */
+int envy24_devmask = 65535;
+/*
+ * envy24_devmask: Selects the device files to be created. By default OSS
+ * will create all available device files. However in some systems it may
+ * be necessary to conserve device numbers.
+ *
+ * Values: The envy24_devmask number is the SUM of the following values:
+ * 1  - Create primary (analog/ADAT/TDIF) outputs
+ * 2  - Create primary (analog/ADAT/TDIF) inputs
+ * 4  - Create S/PDIF outputs
+ * 8  - Create S/PDIF inputs
+ * 16 - Create monitor input device
+ * 32 - Create the "raw" input and output devices.
+ * 
+ * For example envy24_devmask=12 (4+8) creates only the S/PDIF devices.
+ * To enable all possible (current or future) device files set envy24_devmask
+ * to 65535 (default).
+ */
+int envy24_realencoder_hack = 0;
+/*
+ * envy24_realencoder_hack: Older versions of realencoder expect a mixer device
+ * for each audio device file. This option makes OSS to create dummy micers to
+ * make realencoder happy.
+ * Values: 0=normal (default), 1=create dmmy mixers.
+ */
+int envy24_gain_sliders = 0;
+/*
+ * envy24_gain_sliders: By default OSS will create the gain controls as
+ * selection controls (+4 dB / CONSUMER / -10 dB) which is ideal for
+ * professional environments. However home users may prefer having volume
+ * sliders instead.
+ * Values: 0=level selectors (default), 1=volume sliders.
+ */
+int envy24_nfrags = 16;
+/*
+ * envy24_nfrags: For normal operation this setting must be 16.
+ */
+int envy24_mixerstyle = 1;
+/*
+ * envy24_mixerstyle: Defines layout of the peak meter and monitor mixer
+ * sections in the control panel.
+ * NOTE! The envy24_skipdevs parameter must be set to 2. Otherwise the
+ *       traditional mixer style will be used regardless of the value of
+ *       this parameter.
+ * Possible values:
+ * 1=Traditional mixer with separate peak meter and monitor gain sections
+ *   (default).
+ * 2=Alternative style with peak meters and monitor gain sliders grouped
+ *   together (separate output and input sections).
+ */
diff --git a/kernel/drv/oss_envy24/envy24.h b/kernel/drv/oss_envy24/envy24.h
new file mode 100644
index 0000000..dceac89
--- /dev/null
+++ b/kernel/drv/oss_envy24/envy24.h
@@ -0,0 +1,279 @@
+/*
+ * Purpose: Common definitions for the Envy24 driver
+ */
+/*
+ *
+ * This file is part of Open Sound System.
+ *
+ * Copyright (C) 4Front Technologies 1996-2008.
+ *
+ * This this source file is released under GPL v2 license (no other versions).
+ * See the COPYING file included in the main directory of this source
+ * distribution for the license terms and conditions.
+ *
+ */
+#include "uart401.h"
+
+#define DEV_BUFSIZE		(64*1024)	/* Buffer size per channel */
+
+#define HW_PLAYBUFFSIZE	(10*2048)
+#define HW_RECBUFFSIZE	(12*2048)
+#define HW_ALLOCSIZE	(24*1024)	/* Must be bigger or equal than HW_PLAYBUFFSIZE and HW_RECBUFFSIZE */
+
+typedef struct envy24_auxdrv envy24_auxdrv_t;
+
+typedef struct
+{
+  unsigned int svid;
+  char *product;
+  int nr_outs, nr_ins;		/* # of analog channels */
+  int flags;
+#define MF_MAUDIO		0x00000001	/* Made by M Audio */
+#define MF_MIDI1		0x00000002	/* Has MIDI 1 port */
+#define MF_SPDIF		0x00000004	/* Has S/PDIF */
+#define MF_AKMCODEC		0x00000008	/* Has AKM codecs */
+#define MF_WCLOCK		0x00000010	/* Has World clock input */
+#define MF_SPDSELECT		0x00000020	/* Optical+coax S/PDIF */
+#define MF_EWS88		0x00000040	/* Terratec EWS88MT */
+#define MF_AP			0x00000080	/* M Audio Audiophile family */
+#define MF_MIDI2		0x00000100	/* Has MIDI 2 port */
+#define MF_EWX2496		0x00000200	/* Terratec EWX 24/96 */
+#define MF_CONSUMER		0x00000400	/* Force consumer AC97 codec detection */
+#define MF_HOONTECH		0x00000800
+#define MF_D410			0x00001000	/* Delta 410 */
+#define MF_MEEPROM		0x00002000	/* M Audio EEPROM interface */
+#define MF_AC97			0x00004000	/* Consumer AC97 codec */
+  envy24_auxdrv_t *auxdrv;
+  unsigned char *eeprom_data;
+}
+card_spec;
+
+#define ICENSEMBLE_VENDOR_ID	0x1412
+#define ICENSEMBLE_ENVY24_ID	0x1712
+
+#define AKM_A 0x40
+#define AKM_B 0x80
+
+#ifdef USE_LICENSING
+extern int options_data;
+#endif
+
+#define MAX_ODEV 10
+#define MAX_IDEV 12
+
+#ifdef DO_RIAA
+typedef struct
+{
+  int32_t x1, x2, x3;
+  int32_t y1, y2, y3;
+}
+riaa_t;
+#endif
+
+typedef struct
+{
+  int flags;
+#define PORTC_SPDOUT	0x00000001
+#define PORTC_SPDIN	0x00000002
+  int dev;
+  int chnum;
+  int direction;
+#define DIR_INPUT	ADEV_NOOUTPUT
+#define DIR_OUTPUT	ADEV_NOINPUT
+  int open_mode;
+
+  char name[16];
+
+  int bits, channels;
+  volatile int is_active;
+  volatile int trigger_bits;
+  int pcm_qlen;
+  int riaa_filter;
+#ifdef DO_RIAA
+  riaa_t riaa_parms[12];
+#endif
+}
+envy24_portc;
+
+/*
+ * Hoontech specific structure
+ */
+typedef union
+{
+  struct
+  {
+    unsigned int box:2;
+    unsigned int darear:1;
+    unsigned int id0:2;
+    unsigned int clock0:1;
+    unsigned int res0:2;
+
+    unsigned int ch1:1;
+    unsigned int ch2:1;
+    unsigned int ch3:1;
+    unsigned int id1:2;
+    unsigned int clock1:1;
+    unsigned int res1:2;
+
+    unsigned int ch4:1;
+    unsigned int midiin:1;
+    unsigned int midi1:1;
+    unsigned int id2:2;
+    unsigned int clock2:1;
+    unsigned int res2:2;
+
+    unsigned int midi2:1;
+    unsigned int mute:1;
+    unsigned int insel:1;
+    unsigned int id3:2;
+    unsigned int clock3:1;
+    unsigned int res3:2;
+  }
+  b;
+
+  struct
+  {
+    unsigned int b0:8;
+    unsigned int b1:8;
+    unsigned int b2:8;
+    unsigned int b3:8;
+  }
+  w;
+
+  unsigned int dwVal;
+
+}
+ADSP;
+
+#define _adsp devc->adsp
+/*****************/
+
+typedef struct envy24d_portc
+{
+  int audio_dev;
+  int open_mode;
+  int channels;
+  int direction;
+  int trigger_bits;
+}
+envy24d_portc;
+
+typedef struct
+{
+  oss_device_t *osdev;
+  oss_mutex_t mutex;
+  int mpu1_attached, mpu2_attached;
+  oss_native_word ccs_base, mt_base;
+  int irq;
+  card_spec *model_data;
+  envy24_auxdrv_t *auxdrv;
+  int skipdevs;			/* envy24_skipdevs option */
+
+  unsigned char eeprom[32];
+
+/*
+ * MT mixer
+ */
+
+  int mixer_dev;
+
+/*
+ * Consumer (AC97) mixer
+ */
+
+  ac97_devc ac97devc;
+  int consumer_mixer_dev;
+  int consumer_ac97_present;
+
+  int nr_outdevs, nr_indevs;
+  int curr_outch, curr_inch;
+  int inportmask, outportmask;
+  envy24_portc play_portc[MAX_ODEV];
+  envy24_portc rec_portc[MAX_IDEV];
+  envy24d_portc direct_portc_in, direct_portc_out;
+  int direct_audio_opened;
+
+  int rec_bufsize, play_bufsize;
+
+  unsigned char *playbuf, *recbuf;
+  int playbuffsize, recbuffsize;
+  oss_native_word playbuf_phys, recbuf_phys;
+  oss_dma_handle_t playbuf_dma_handle, recbuf_dma_handle;
+  int hw_rfragsize, hw_pfragsize, hw_fragsamples, hw_nfrags;
+  volatile int hw_playfrag, hw_recfrag;
+  volatile int active_inputs, active_outputs;
+  volatile int open_inputs, open_outputs;
+  volatile int playback_started, recording_started;
+  volatile int playback_prepared, recording_prepared;
+  int speed, pending_speed_sel, speedbits;
+  int syncsource;
+  int gpio_tmp;
+#define SYNC_INTERNAL 	0
+#define SYNC_SPDIF		1
+#define SYNC_WCLOCK		2
+
+  int play_channel_mask, rec_channel_mask;
+  int nr_play_channels, nr_rec_channels;
+  int writeahead;
+
+  int use_src;
+  int ratelock;
+
+/* Spdif parameters */
+  int spdif_pro_mode;
+  unsigned char spdif_cbits[24];
+  int sync_locked;
+  int ac3_mode;
+
+  short akm_gains[0xff];
+  ADSP adsp;			/* Hoontech only */
+  uart401_devc uart401devc1;
+  uart401_devc uart401devc2;
+
+  int first_dev;
+}
+envy24_devc;
+
+struct envy24_auxdrv
+{
+  void (*card_init) (envy24_devc * devc);
+  int (*mixer_init) (envy24_devc * devc, int dev, int group);
+  void (*spdif_init) (envy24_devc * devc);
+  void (*spdif_set) (envy24_devc * devc, int ctrl0);
+  int (*spdif_ioctl) (envy24_devc * devc, int dev, unsigned int cmd,
+		      ioctl_arg arg);
+  int (*spdif_read_reg) (envy24_devc * devc, int reg);
+  void (*spdif_write_reg) (envy24_devc * devc, int reg, int val);
+  void (*set_rate) (envy24_devc * devc);
+  int (*get_locked_status) (envy24_devc * devc);
+  int (*spdif_mixer_init) (envy24_devc * devc, int dev, int group);
+  void (*card_uninit) (envy24_devc * devc);
+};
+
+struct speed_sel
+{
+  int speed, speedbits;
+};
+
+/* extern struct speed_sel speed_tab[]; */
+
+void envy24d_install (envy24_devc * devc);
+void envy24d_playintr (envy24_devc * devc);
+void envy24d_recintr (envy24_devc * devc);
+void envy24_prepare_play_engine (envy24_devc * devc);
+void envy24_launch_play_engine (envy24_devc * devc);
+void envy24_stop_playback (envy24_devc * devc);
+void envy24_start_recording (envy24_devc * devc);
+void envy24_launch_recording (envy24_devc * devc);
+void envy24_stop_recording (envy24_devc * devc);
+
+void envy24_write_cci (envy24_devc * devc, int pos, int data);
+int envy24_read_cci (envy24_devc * devc, int pos);
+extern int cs8427_spdif_ioctl (envy24_devc * devc, int dev, unsigned int cmd,
+			       ioctl_arg arg);
+extern void init_cs8427_spdif (envy24_devc * devc);
+extern int cs8427_spdif_mixer_init (envy24_devc * devc, int dev, int group);
+void WriteGPIObit (envy24_devc * devc, int sel, int what);
+int ReadGPIObit (envy24_devc * devc, int sel);
+void write_cs8427_spdif (envy24_devc * devc, int d);
+extern void envy24_set_enum_mask (int dev, int ctl, oss_native_word mask);
diff --git a/kernel/drv/oss_envy24/envy24_1010lt.c b/kernel/drv/oss_envy24/envy24_1010lt.c
new file mode 100644
index 0000000..5d31891
--- /dev/null
+++ b/kernel/drv/oss_envy24/envy24_1010lt.c
@@ -0,0 +1,582 @@
+/*
+ * Purpose: Card specific routines for M Audio Delta 1010LT
+ */
+/*
+ *
+ * This file is part of Open Sound System.
+ *
+ * Copyright (C) 4Front Technologies 1996-2008.
+ *
+ * This this source file is released under GPL v2 license (no other versions).
+ * See the COPYING file included in the main directory of this source
+ * distribution for the license terms and conditions.
+ *
+ */
+
+#include "oss_config.h"
+#include <ac97.h>
+#include "envy24.h"
+
+#define CH_STEREO	0x80
+
+/* SPI chip select codes */
+#define CS8_CS 0x4
+#define CDC_CS 0x0
+#define NONE_CS 0x7
+
+#define SPI_CLK 1
+#define SPI_DIN 2
+#define SPI_DOUT 3
+#define WCLOCK_ENABLE 7
+
+#define CS8_ADDR 0x20		/* Chip SPI/I2C address */
+#define CS8_RD 0x01
+#define CS8_WR 0x00
+
+#define BIT0		0x01
+#define BIT1		0x02
+#define BIT2		0x04
+#define BIT3		0x08
+#define BIT4		0x10
+#define BIT5		0x20
+#define BIT6		0x40
+#define BIT7		0x80
+
+#if 0
+# define PRT_STATUS(v) outb(v&0xff, 0x378)
+#else
+# define PRT_STATUS(v)
+#endif
+
+/* -----	DEFINITION OF GPIOs     ----- */
+
+#define	FPGA_PROGRAM_L		7	/* FPGA program control select line (active low) */
+#define FPGA_CLK		1	/* FPGA program clock */
+#define EXT_REG_CLK		0	/* Was GPIO Fast mode (debug) */
+#define FPGA_D0			3	/* FPGA program data */
+
+#define LATCH_EN_L		4	/* Strobe for external latch (active low) */
+#define FPGA_MUTE		5
+
+#define FPGA_INIT_STATE	0xFC	/* Init state for extern register to allow */
+				/* FPGA initialization. */
+
+#define FPGA_MASTER		5
+
+extern int envy24_gain_sliders;
+extern int envy24_virtualout;
+extern int envy24_zerolatency;	/* Testing in progress */
+
+static void
+SPI_select (envy24_devc * devc, int sel)
+{
+  int tmp;
+
+  tmp = envy24_read_cci (devc, 0x20);
+  tmp &= ~0x70;
+  tmp |= (sel & 0x7) << 4;
+  envy24_write_cci (devc, 0x20, tmp);
+}
+
+static void
+write_d1010lt_codec (envy24_devc * devc, int sel, int bRegister,
+		     unsigned char bData)
+{
+  int bMask;
+
+  WriteGPIObit (devc, SPI_DOUT, 0);
+  WriteGPIObit (devc, SPI_CLK, 1);
+
+  SPI_select (devc, sel);
+  oss_udelay (1);
+  bRegister = (bRegister & 0x0F) | 0xA0;	/* Add I2C address field. */
+
+  /* Assert the CODEC chip select and wait at least 150 nS. */
+  /* */
+
+  /* Write the register address byte. */
+  /* */
+  for (bMask = 0x80; bMask; bMask = (bMask >> 1) & 0x7F)
+    {
+      /* Drop SPI clock low. */
+      WriteGPIObit (devc, SPI_CLK, 0);
+
+      /* Write current data bit. */
+      if (bMask & bRegister)
+	WriteGPIObit (devc, SPI_DOUT, 1);
+      else
+	WriteGPIObit (devc, SPI_DOUT, 0);
+
+      /* Raise SPI clock to "clock data in". */
+      WriteGPIObit (devc, SPI_CLK, 1);
+    }
+
+
+  /* Write the data byte. */
+  /* */
+  for (bMask = 0x80; bMask; bMask = (bMask >> 1) & 0x7F)
+    {
+      /* Drop SPI clock low. */
+      WriteGPIObit (devc, SPI_CLK, 0);
+
+      /* Write current data bit. */
+      if (bMask & bData)
+	WriteGPIObit (devc, SPI_DOUT, 1);
+      else
+	WriteGPIObit (devc, SPI_DOUT, 0);
+
+      /* Raise SPI clock to "clock data in". */
+      WriteGPIObit (devc, SPI_CLK, 1);
+    }
+
+  /* De-assert chip select. */
+  /* */
+
+  SPI_select (devc, NONE_CS);
+}
+
+static void
+d1010lt_card_init (envy24_devc * devc)
+{
+  int i;
+
+  SPI_select (devc, NONE_CS);
+
+  for (i = 0; i < 4; i++)
+    {
+      write_d1010lt_codec (devc, i, 0, 0x07);
+      write_d1010lt_codec (devc, i, 1, 0x03);
+      write_d1010lt_codec (devc, i, 2, 0x60);
+      write_d1010lt_codec (devc, i, 3, 0x19);
+      write_d1010lt_codec (devc, i, 4, 0x7f);
+      write_d1010lt_codec (devc, i, 5, 0x7f);
+      write_d1010lt_codec (devc, i, 6, 0x7f);
+      write_d1010lt_codec (devc, i, 7, 0x7f);
+    }
+
+}
+
+static int
+envy24_set_d1010lt (int dev, int ctrl, unsigned int cmd, int value)
+{
+  envy24_devc *devc = mixer_devs[dev]->devc;
+  int codec, level;
+  static unsigned char levels[] = { 0x7f, 0x8c, 0x98 };
+
+  if (ctrl >= 0xff)
+    return OSS_EINVAL;
+
+  if (cmd == SNDCTL_MIX_READ)
+    {
+      return devc->akm_gains[ctrl];
+    }
+  else if (cmd == SNDCTL_MIX_WRITE)
+    {
+      codec = (ctrl & 0x7) / 2;
+      if (envy24_gain_sliders)
+	{
+	  level = value & 0xff;
+	  if (level < 0)
+	    level = 0;
+	  if (level > 144)
+	    level = 144;
+	}
+      else
+	{
+	  if (value < 0 || value > 2)
+	    value = 0;
+	  level = levels[value];
+	}
+
+      switch (ctrl & 0x89)	/* IN/OUT, LEFT/RIGHT, Gang switches */
+	{
+	case 0x00:		/* Left output channel only */
+	  write_d1010lt_codec (devc, codec, 6, level);
+	  break;
+
+	case 0x01:		/* Right output channel only */
+	  write_d1010lt_codec (devc, codec, 7, level);
+	  break;
+
+	case 0x80:		/* Both output channels */
+	  write_d1010lt_codec (devc, codec, 6, level);
+	  write_d1010lt_codec (devc, codec, 7, level);
+	  break;
+
+	case 0x08:		/* Left input channel only */
+	  write_d1010lt_codec (devc, codec, 4, level);
+	  break;
+
+	case 0x09:		/* Right input channel only */
+	  write_d1010lt_codec (devc, codec, 5, level);
+	  break;
+
+	case 0x88:		/* Both input channels */
+	  write_d1010lt_codec (devc, codec, 4, level);
+	  write_d1010lt_codec (devc, codec, 5, level);
+	  break;
+	}
+
+      return devc->akm_gains[ctrl] = value;
+    }
+  return OSS_EINVAL;
+}
+
+
+static int
+d1010lt_mix_init (envy24_devc * devc, int dev, int group)
+{
+  int i, mask = devc->outportmask, err, skip;
+  int typ = MIXT_ENUM, range = 3;
+  char tmp[64];
+
+  if ((group = mixer_ext_create_group (dev, 0, "ENVY24_GAIN")) < 0)
+    return group;
+
+  skip = devc->skipdevs;
+  if (skip != 2)
+    skip = 1;
+
+  if (envy24_gain_sliders)
+    {
+      typ = MIXT_MONOSLIDER;
+      range = 144;
+
+      for (i = 0; i < 0xff; i++)
+	devc->akm_gains[i] = 0x7f;
+    }
+  else
+    for (i = 0; i < 0xff; i++)
+      devc->akm_gains[i] = 0;
+
+  for (i = 0; i < 8; i += skip)
+    {
+
+      if (!(mask & (1 << i)))
+	continue;		/* Not present */
+
+      if (devc->skipdevs == 2)
+	{
+	  if (i == 8)
+	    strcpy (tmp, "ENVY24_SPDOUT");
+	  else
+	    sprintf (tmp, "ENVY24_OUT%d/%d", i + 1, i + 2);
+
+	  if ((err = mixer_ext_create_control (dev, group,
+					       i | CH_STEREO,
+					       envy24_set_d1010lt, typ, tmp,
+					       range,
+					       MIXF_MAINVOL |
+					       MIXF_READABLE |
+					       MIXF_WRITEABLE)) < 0)
+	    return err;
+	}
+      else
+	{
+	  if (i == 8)
+	    strcpy (tmp, "ENVY24_SPDOUTL");
+	  else if (i == 9)
+	    strcpy (tmp, "ENVY24_SPDOUTR");
+	  else
+	    sprintf (tmp, "ENVY24_OUT%d", i + 1);
+
+	  if ((err = mixer_ext_create_control (dev, group,
+					       i, envy24_set_d1010lt,
+					       typ,
+					       tmp, range,
+					       MIXF_MAINVOL |
+					       MIXF_READABLE |
+					       MIXF_WRITEABLE)) < 0)
+	    return err;
+	}
+    }
+
+  mask = devc->inportmask;
+  for (i = 0; i < 8; i += skip)
+    {
+
+      if (!(mask & (1 << i)))
+	continue;		/* Not present */
+
+      if (devc->skipdevs == 2)
+	{
+	  if (i == 8)
+	    strcpy (tmp, "ENVY24_SPDIN");
+	  else
+	    sprintf (tmp, "ENVY24_IN%d/%d", i + 1, i + 2);
+
+	  if ((err = mixer_ext_create_control (dev, group,
+					       (8 + i) | CH_STEREO,
+					       envy24_set_d1010lt, typ, tmp,
+					       range,
+					       MIXF_RECVOL |
+					       MIXF_READABLE |
+					       MIXF_WRITEABLE)) < 0)
+	    return err;
+	}
+      else
+	{
+	  if (i == 8)
+	    strcpy (tmp, "ENVY24_SPDINL");
+	  else if (i == 9)
+	    strcpy (tmp, "ENVY24_SPDINR");
+	  else
+	    sprintf (tmp, "ENVY24_IN%d", i + 1);
+
+	  if ((err = mixer_ext_create_control (dev, group,
+					       8 + i, envy24_set_d1010lt,
+					       typ,
+					       tmp, range,
+					       MIXF_RECVOL |
+					       MIXF_READABLE |
+					       MIXF_WRITEABLE)) < 0)
+	    return err;
+	}
+    }
+
+  return 0;
+}
+
+static void
+write_d1010lt_spdif_reg (envy24_devc * devc, int bRegister, int bData)
+{
+  unsigned char bMask;
+  unsigned char bSPI;
+
+  /* Assert the CODEC chip select and wait at least 150 nS. */
+  /* */
+  SPI_select (devc, CS8_CS);
+
+  /* Write the SPI address/cmd byte. */
+  /* */
+  bSPI = CS8_ADDR | CS8_WR;
+  /* */
+  for (bMask = 0x80; bMask; bMask = (bMask >> 1) & 0x7F)
+    {
+      /* Drop SPI clock low. */
+      WriteGPIObit (devc, SPI_CLK, 0);
+
+      /* Write current data bit. */
+      if (bMask & bSPI)
+	WriteGPIObit (devc, SPI_DOUT, 1);
+      else
+	WriteGPIObit (devc, SPI_DOUT, 0);
+
+      /* Raise SPI clock to "clock data in". */
+      WriteGPIObit (devc, SPI_CLK, 1);
+    }
+
+  /* Write the address (MAP) byte. */
+  /* */
+  for (bMask = 0x80; bMask; bMask = (bMask >> 1) & 0x7F)
+    {
+      /* Drop SPI clock low. */
+      WriteGPIObit (devc, SPI_CLK, 0);
+
+      /* Write current data bit. */
+      if (bMask & bRegister)
+	WriteGPIObit (devc, SPI_DOUT, 1);
+      else
+	WriteGPIObit (devc, SPI_DOUT, 0);
+
+      /* Raise SPI clock to "clock data in". */
+      WriteGPIObit (devc, SPI_CLK, 1);
+    }
+
+
+  /* Write the data byte. */
+  /* */
+  for (bMask = 0x80; bMask; bMask = (bMask >> 1) & 0x7F)
+    {
+      /* Drop SPI clock low. */
+      WriteGPIObit (devc, SPI_CLK, 0);
+
+      /* Write current data bit. */
+      if (bMask & bData)
+	WriteGPIObit (devc, SPI_DOUT, 1);
+      else
+	WriteGPIObit (devc, SPI_DOUT, 0);
+
+      /* Raise SPI clock to "clock data in". */
+      WriteGPIObit (devc, SPI_CLK, 1);
+    }
+
+  /* De-assert chip select. */
+  /* */
+  SPI_select (devc, NONE_CS);
+}
+
+static int
+read_d1010lt_spdif_reg (envy24_devc * devc, int reg)
+{
+  unsigned char bMask;
+  unsigned char bRet = 0;
+  unsigned char bSPI;
+
+
+	/****** WRITE MAP ADDRESS FIRST ******/
+
+  /* Drop the chip select low. */
+  /* Wait at least 150 nS. */
+  /* */
+  SPI_select (devc, CS8_CS);
+
+  /* Write the SPI address/cmd byte. */
+  /* */
+  bSPI = CS8_ADDR + CS8_WR;	/* SPI address field plus WRITE operation. */
+  /* */
+  for (bMask = 0x80; bMask; bMask = (bMask >> 1) & 0x7F)
+    {
+      /* Drop clock (GPIO5) low. */
+      WriteGPIObit (devc, SPI_CLK, 0);
+
+      /* Write current data bit. */
+      if (bMask & bSPI)
+	WriteGPIObit (devc, SPI_DOUT, 1);
+      else
+	WriteGPIObit (devc, SPI_DOUT, 0);
+
+      /* Raise clock (GPIO5). */
+      WriteGPIObit (devc, SPI_CLK, 1);
+    }
+
+
+  /* Write the address (MAP) byte. */
+  /* */
+  for (bMask = 0x80; bMask; bMask = (bMask >> 1) & 0x7F)
+    {
+      /* Drop clock (GPIO5) low. */
+      WriteGPIObit (devc, SPI_CLK, 0);
+
+      /* Write current data bit. */
+      if (bMask & reg)
+	WriteGPIObit (devc, SPI_DOUT, 1);
+      else
+	WriteGPIObit (devc, SPI_DOUT, 0);
+
+      /* Raise clock (GPIO5). */
+      WriteGPIObit (devc, SPI_CLK, 1);
+    }
+
+  /* De-assert chip select(s). */
+  /* */
+  SPI_select (devc, NONE_CS);
+
+
+	/****** NOW READ THE DATA ******/
+
+  /* Drop the chip select low. */
+  /* Wait at least 150 nS. */
+  /* */
+  SPI_select (devc, CS8_CS);
+
+
+  /* Write the SPI address/cmd byte. */
+  /* */
+  bSPI = CS8_ADDR + CS8_RD;	/* SPI address field plus READ operation. */
+  /* */
+  for (bMask = 0x80; bMask; bMask = (bMask >> 1) & 0x7F)
+    {
+      /* Drop clock (GPIO5) low. */
+      WriteGPIObit (devc, SPI_CLK, 0);
+
+      /* Write current data bit. */
+      if (bMask & bSPI)
+	WriteGPIObit (devc, SPI_DOUT, 1);
+      else
+	WriteGPIObit (devc, SPI_DOUT, 0);
+
+      /* Raise clock (GPIO5). */
+      WriteGPIObit (devc, SPI_CLK, 1);
+    }
+
+
+  /* Read the data byte. */
+  /* */
+  bRet = 0;
+  /* */
+  for (bMask = 0x80; bMask; bMask = (bMask >> 1) & 0x7F)
+    {
+      /* Drop clock low. */
+      WriteGPIObit (devc, SPI_CLK, 0);
+
+      /* Read current data bit. */
+      if (ReadGPIObit (devc, SPI_DIN))
+	bRet |= bMask;
+
+      /* Raise clock. */
+      WriteGPIObit (devc, SPI_CLK, 1);
+    }
+
+
+  /* De-assert chip selects. */
+  /* */
+  SPI_select (devc, NONE_CS);
+
+  /* Return value. */
+
+  return bRet;
+}
+
+static void
+set_d1010lt_speed (envy24_devc * devc)
+{
+  int tmp;
+
+  tmp = devc->speedbits;
+
+  switch (devc->syncsource)
+    {
+    case SYNC_INTERNAL:
+      OUTB (devc->osdev, tmp, devc->mt_base + 0x01);
+      WriteGPIObit (devc, WCLOCK_ENABLE, 0);
+      write_d1010lt_spdif_reg (devc, 4,
+			       read_d1010lt_spdif_reg (devc, 4) & (~BIT0));
+      break;
+
+    case SYNC_SPDIF:
+      tmp |= 0x10;
+      OUTB (devc->osdev, tmp, devc->mt_base + 0x01);
+      WriteGPIObit (devc, WCLOCK_ENABLE, 0);
+      write_d1010lt_spdif_reg (devc, 4,
+			       read_d1010lt_spdif_reg (devc, 4) | BIT0);
+      break;
+
+    case SYNC_WCLOCK:
+      tmp |= 0x10;
+      OUTB (devc->osdev, tmp, devc->mt_base + 0x01);
+      WriteGPIObit (devc, WCLOCK_ENABLE, 1);
+      write_d1010lt_spdif_reg (devc, 4,
+			       read_d1010lt_spdif_reg (devc, 4) & (~BIT0));
+      if (devc->model_data->svid == 0xd63014ff)
+        {
+	  /*
+	   * 1010 rev E only
+	   * don't aks me why, but it seems to work
+	   */
+	  WriteGPIObit (devc, 6, 0);
+	  WriteGPIObit (devc, WCLOCK_ENABLE, 1);
+        }
+      break;
+    }
+}
+
+static int
+d1010lt_get_locked_status (envy24_devc * devc)
+{
+  /* TODO */
+  return 1;
+}
+
+envy24_auxdrv_t d1010lt_auxdrv = {
+  d1010lt_card_init,
+  d1010lt_mix_init,
+  init_cs8427_spdif,
+  write_cs8427_spdif,
+  cs8427_spdif_ioctl,
+  read_d1010lt_spdif_reg,
+  write_d1010lt_spdif_reg,
+  set_d1010lt_speed,
+  d1010lt_get_locked_status,
+  cs8427_spdif_mixer_init
+};
diff --git a/kernel/drv/oss_envy24/envy24_6fire.c b/kernel/drv/oss_envy24/envy24_6fire.c
new file mode 100644
index 0000000..469ceab
--- /dev/null
+++ b/kernel/drv/oss_envy24/envy24_6fire.c
@@ -0,0 +1,781 @@
+/*
+ * Purpose: Card specific routines for Terratec DMX6fire.
+ */
+/*
+ *
+ * This file is part of Open Sound System.
+ *
+ * Copyright (C) 4Front Technologies 1996-2008.
+ *
+ * This this source file is released under GPL v2 license (no other versions).
+ * See the COPYING file included in the main directory of this source
+ * distribution for the license terms and conditions.
+ *
+ */
+
+#include "oss_config.h"
+#include "ac97.h"
+#include "envy24.h"
+
+#if 0
+# define PRT_STATUS(v) outb(v&0xff, 0x378)
+#else
+# define PRT_STATUS(v)
+#endif
+
+#define DEFAULT_FRONTBOX_SETUP	0xfd
+
+extern int envy24_gain_sliders;
+extern int envy24_virtualout;
+
+#define EWX_DIG_ADDR 0x24	/* IIC address of digital traceiver chip of 6fire */
+
+/*=============================================================================
+  Function    : IIC_GetSDA
+-------------------------------------------------------------------------------
+  Description : 
+  Returns     : unsigned char  -> 
+  Parameters  : unsigned long dwPortAddr -> 
+-------------------------------------------------------------------------------
+  Notes       : 
+=============================================================================*/
+static unsigned char
+IIC_GetSDA (envy24_devc * devc)
+{
+
+  unsigned char bReg, bSDA;
+
+  /* FMB TEST: RW line */
+  /* set write mask */
+  bReg = ~(0x08);		/* writeable */
+  envy24_write_cci (devc, 0x21, bReg);
+
+  /* set RW line LOW */
+  bReg = 0;			/* writeable */
+  envy24_write_cci (devc, 0x20, bReg);
+
+  /* Set direction: SDA to input and SCL to output */
+  bReg = envy24_read_cci (devc, 0x22);
+  bReg |= 0x20;			/* SCL output = 1 */
+  bReg &= ~0x10;		/* SDA input  = 0 */
+  envy24_write_cci (devc, 0x22, bReg);
+
+  /* Get SDA line state */
+  bSDA = envy24_read_cci (devc, 0x20);
+
+
+  /* set RW line HIGH */
+  bReg = 0x08;			/* writeable */
+  envy24_write_cci (devc, 0x20, bReg);
+
+  return 1;
+  /* return ((bSDA & 0x10) == 0x10); */
+
+}
+
+/*=============================================================================
+  Function    : IIC_SetIic
+-------------------------------------------------------------------------------
+  Description : 
+  Returns     : void  -> 
+  Parameters  : unsigned int dwPortAddr -> 
+              : unsigned char fSDA -> 
+              : unsigned char fSCL -> 
+-------------------------------------------------------------------------------
+  Notes       : 
+=============================================================================*/
+static void
+IIC_SetIic (envy24_devc * devc, unsigned char fSDA, unsigned char fSCL)
+{
+  unsigned char bReg;
+
+  /* Set direction: SDA and SCL to output */
+  bReg = envy24_read_cci (devc, 0x22);
+  bReg |= (0x20 | 0x10);	/* 1 -> output */
+  envy24_write_cci (devc, 0x22, bReg);
+
+  /* set write mask */
+  bReg = ~(0x20 | 0x10);	/* writeable */
+  envy24_write_cci (devc, 0x21, bReg);
+
+  /* Set line state */
+  /* FMB TEST: RW line */
+  bReg = 0x08;
+  if (fSDA)
+    bReg += 0x10;
+  if (fSCL)
+    bReg += 0x20;
+  envy24_write_cci (devc, 0x20, bReg);
+
+}
+
+/*=============================================================================
+  Function    : IIC_Start
+-------------------------------------------------------------------------------
+  Description : 
+  Returns     : void  -> 
+  Parameters  : unsigned int dwPortAddr -> 
+-------------------------------------------------------------------------------
+  Notes       : 
+=============================================================================*/
+/*__inline  */
+static void
+IIC_Start (envy24_devc * devc)
+{
+  /* falling edge of SDA while SCL is HIGH */
+  IIC_SetIic (devc, 1, 1);
+  oss_udelay (30);
+  IIC_SetIic (devc, 0, 1);
+}
+
+/*=============================================================================
+  Function    : IIC_Stop  
+-------------------------------------------------------------------------------
+  Description : 
+  Returns     : void -> 
+  Parameters  : unsigned int dwPortAddr -> 
+-------------------------------------------------------------------------------
+  Notes       : 
+=============================================================================*/
+/*__inline  */
+
+static void
+IIC_Stop (envy24_devc * devc)
+{
+  /* rising edge of SDA while SCL is HIGH */
+  IIC_SetIic (devc, 0, 1);
+  IIC_SetIic (devc, 1, 1);
+}
+
+
+/*=============================================================================
+  Function    : IIC_SendByte
+-------------------------------------------------------------------------------
+  Description : 
+  Returns     : unsigned char -> 
+  Parameters  : unsigned int dwPortAddr -> 
+              : unsigned char bByte -> 
+-------------------------------------------------------------------------------
+  Notes       : 
+=============================================================================*/
+/*__inline  */
+static unsigned char
+IIC_SendByte (envy24_devc * devc, unsigned char bByte)
+{
+  unsigned char bDataBit, bAck;
+  int i;
+
+  for (i = 7; i >= 0; i--)	/* send byte (MSB first) */
+    {
+      bDataBit = (bByte >> i) & 0x01;
+
+      IIC_SetIic (devc, bDataBit, 0);
+      IIC_SetIic (devc, bDataBit, 1);
+      IIC_SetIic (devc, bDataBit, 0);
+    }				/* end for i */
+
+  IIC_SetIic (devc, 1, 0);
+
+  /* Get acknowledge */
+  IIC_SetIic (devc, 1, 1);
+  bAck = IIC_GetSDA (devc);
+  /* FMB this is a start condition but never mind */
+  IIC_SetIic (devc, 0, 0);
+#if 0
+  if (bAck)
+    cmn_err (CE_CONT, "SendByte failed %02x\n", bByte);
+  else
+    cmn_err (CE_CONT, "SendByte OK %02x\n", bByte);
+#endif
+  return 1;
+  /* return (!bAck); *//* bAck = 0 --> success */
+}
+
+#if 0
+/*=============================================================================
+  Function    : IIC_WriteByte
+-------------------------------------------------------------------------------
+  Description : 
+  Returns     : unsigned char  -> 
+  Parameters  : unsigned int dwPortAddr -> 
+              : unsigned char bIicAddress -> 
+              : unsigned char bByte -> 
+-------------------------------------------------------------------------------
+  Notes       : 
+=============================================================================*/
+static unsigned char
+IIC_WriteByte (envy24_devc * devc, unsigned char bIicAddress,
+	       unsigned char bByte)
+{
+  IIC_Start (devc);
+
+  /* send IIC address and data byte */
+  if (!IIC_SendByte (devc, bIicAddress))
+    {
+      cmn_err (CE_CONT, "IIC_SendByte 1 failed\n");
+      goto FAILED;
+    }
+  if (!IIC_SendByte (devc, bByte))
+    {
+      cmn_err (CE_CONT, "IIC_SendByte 2 failed\n");
+      goto FAILED;
+    }
+
+  IIC_Stop (devc);
+  return 1;
+
+FAILED:
+  IIC_Stop (devc);
+  return 0;
+}
+#endif
+
+static unsigned char
+IIC_WriteWord (envy24_devc * devc, unsigned char bIicAddress,
+	       unsigned char reg, unsigned char bByte)
+{
+  IIC_Start (devc);
+
+  /* send IIC address and data byte */
+  if (!IIC_SendByte (devc, bIicAddress))
+    {
+      cmn_err (CE_CONT, "IIC_SendByte 1 failed\n");
+      goto FAILED;
+    }
+  if (!IIC_SendByte (devc, reg))
+    {
+      cmn_err (CE_CONT, "IIC_SendByte 2 failed\n");
+      goto FAILED;
+    }
+  if (!IIC_SendByte (devc, bByte))
+    {
+      cmn_err (CE_CONT, "IIC_SendByte 3 failed\n");
+      goto FAILED;
+    }
+
+  IIC_Stop (devc);
+  return 1;
+
+FAILED:
+  IIC_Stop (devc);
+  return 0;
+}
+
+static void
+FrontboxControl (envy24_devc * devc, int b)
+{
+  IIC_WriteWord (devc, 0x40, 0x01, b);	/* Output register */
+  devc->gpio_tmp = b;
+}
+
+static int
+HW_AK4525_SetChipSelect (envy24_devc * devc, unsigned char bCsMask)
+{
+  unsigned char b;
+  /* check validity */
+  if (bCsMask > 0x07)
+    {
+      cmn_err (CE_CONT, "Invalid bCsMask %02x\n", bCsMask);
+      return 0;			/* invalid  */
+    }
+
+  envy24_write_cci (devc, 0x21, 0x00);
+  envy24_write_cci (devc, 0x22, 0xff);
+  b = envy24_read_cci (devc, 0x20);
+  b &= ~0x07;
+
+  b |= bCsMask & 0x07;
+
+  envy24_write_cci (devc, 0x20, b);
+
+  return 1;
+}
+
+#define HW_AK4525_SetLines IIC_SetIic
+
+/*=============================================================================
+    FUNCTION:   HW_AK4525_WriteRegister 
+-------------------------------------------------------------------------------
+	PURPOSE:    
+    PARAMETERS: unsigned int port      - port address for IIC port
+                unsigned char bCsMask   - CoDec bitmask (bits 0..3)
+		                  or 0xFF for all codecs together
+		unsigned char bRegIdx   - offset to desired register
+                unsigned char bReg      - new register value
+	RETURNS:    
+-------------------------------------------------------------------------------
+	NOTES:      The Chip Selects must have been set prior to this call
+				PCF8574_CODEC_IIC_ADDRESS    
+
+	+-----------------------------------------------------------------+
+	| B15 B14 B13 B12 B11 B10 B09 B08|B07 B06 B05 B04 B03 B02 B01 B00 |
+	+--------+---+-------------------+--------------------------------+
+	| C1  C0 |R/W|A4  A3  A2  A1  A0 |D7  D6  D5  D4  D3  D2  D1  D0  |
+	| 1   0  |1  |        <= 7       |           data                 |
+	+--------+---+-------------------+--------------------------------+
+
+=============================================================================*/
+static unsigned char
+HW_AK4525_WriteRegister (envy24_devc * devc, unsigned char bCsMask,
+			 unsigned char bRegIdx, unsigned char bRegData)
+{
+
+  unsigned short wCmd;
+  unsigned char i;
+  unsigned char fData;
+
+  /* format buffer */
+  wCmd = 0xA000 +		/* chip address + R/W */
+    (((unsigned short) bRegIdx) << 8) +	/* register address */
+    bRegData;
+
+  HW_AK4525_SetLines (devc, 0, 0);
+
+  /* start write cycle */
+  if (!HW_AK4525_SetChipSelect (devc, bCsMask))
+    {
+      cmn_err (CE_CONT, "HW_AK4525_SetChipSelect failed\n");
+      return 0;			/* = CS to LOW -> data latched */
+    }
+
+
+  for (i = 0; i < 16; i++)
+    {
+      fData = (wCmd & 0x8000) ? 1 : 0;
+      HW_AK4525_SetLines (devc, fData, 0);
+      HW_AK4525_SetLines (devc, fData, 1);	/* data is clocked in on rising edge of CCLK */
+      HW_AK4525_SetLines (devc, fData, 0);
+      wCmd <<= 1;
+    }
+
+  /* leave data line HIGH (= default for IIC) */
+  HW_AK4525_SetLines (devc, fData, 0);	/* data is clocked in on rising edge of CCLK */
+
+  /* end write cycle */
+  if (!HW_AK4525_SetChipSelect (devc, 0x00))
+    {
+      cmn_err (CE_CONT, "HW_AK4525_SetChipSelect 2 failed\n");
+      return 0;			/* = all CS to HIGH -> CS to default */
+    }
+
+  /* default */
+  HW_AK4525_SetLines (devc, 1, 1);	/* data is clocked in on rising edge of CCLK */
+
+  return 1;
+}
+
+
+/* Register offsets */
+enum
+{
+  AK4525_REG_POWER,
+  AK4525_REG_RESET,
+  AK4525_REG_FORMAT,
+  AK4525_REG_DEEMPHASIS,
+  AK4525_REG_LEFT_INPUT,
+  AK4525_REG_RIGHT_INPUT,
+  AK4525_REG_LEFT_OUTPUT,
+  AK4525_REG_RIGHT_OUTPUT
+};
+
+
+/*=============================================================================
+  Function    : HW_AK4525_Reset
+-------------------------------------------------------------------------------
+  Description : 
+  Returns     : unsigned char 
+  Parameters  : PCUST_HW_INSTANCE_DATA  devc - 
+                int nCodecIdx -> 0..3 index of Codec ,-1 -> all
+-------------------------------------------------------------------------------
+  Notes       : 
+=============================================================================*/
+static unsigned char
+HW_AK4525_Reset (envy24_devc * devc, int nCodecIdx)
+{
+  unsigned char bCodecMask = 0;
+  if (nCodecIdx == -1)
+    bCodecMask = 0x07;
+  else
+    bCodecMask = 0x01 << (nCodecIdx);
+
+  if (!HW_AK4525_WriteRegister (devc, bCodecMask,	/* 0x0F -> set mode for all codecs */
+				AK4525_REG_RESET, 0x00))	/* DACs,ADCs -> reset */
+    {
+      cmn_err (CE_CONT, "REG_RESET failed\n");
+      return 0;
+    }
+
+  if (!HW_AK4525_WriteRegister (devc, bCodecMask,	/* 0x0F -> set mode for all codecs */
+				AK4525_REG_FORMAT, 0x60))	/* IIS, 256 fsn, normal speed */
+    return 0;
+
+  if (!HW_AK4525_WriteRegister (devc, bCodecMask,	/* 0x0F -> set mode for all codecs */
+				AK4525_REG_RESET, 0x03))	/* DACs,ADCs -> normal operation */
+    return 0;
+
+  if (!HW_AK4525_WriteRegister (devc, bCodecMask,	/* 0x0F -> set mode for all codecs */
+				AK4525_REG_POWER, 0x07))	/* power on */
+    return 0;
+
+  if (!HW_AK4525_WriteRegister (devc, bCodecMask,	/* soft mute timeout --> short */
+				AK4525_REG_DEEMPHASIS, 0x19))
+    return 0;
+
+  if (!HW_AK4525_WriteRegister (devc,
+				bCodecMask, AK4525_REG_LEFT_INPUT, 0x7f))
+    return 0;
+
+  if (!HW_AK4525_WriteRegister (devc,
+				bCodecMask, AK4525_REG_RIGHT_INPUT, 0x7f))
+    return 0;
+
+  if (!HW_AK4525_WriteRegister (devc,
+				bCodecMask, AK4525_REG_LEFT_OUTPUT, 0x7f))
+    return 0;
+
+  if (!HW_AK4525_WriteRegister (devc,
+				bCodecMask, AK4525_REG_RIGHT_OUTPUT, 0x7f))
+    return 0;
+
+  return 1;
+}
+
+static void
+set_dmx6fire_speed (envy24_devc * devc)
+{
+  unsigned char tmp;
+
+  tmp = devc->speedbits;
+  if (devc->syncsource != SYNC_INTERNAL)
+    {
+      tmp |= 0x10;		/* S/PDIF input clock select */
+      if (devc->model_data->flags & MF_WCLOCK)	/* Has world clock too */
+	{
+	  int cmd = envy24_read_cci (devc, 0x20);
+	  cmd |= 0x10;		/* S/PDIF */
+	  if (devc->syncsource == SYNC_WCLOCK)
+	    cmd &= ~0x10;	/* World clock */
+	  envy24_write_cci (devc, 0x20, cmd);
+	}
+    }
+  OUTB (devc->osdev, tmp, devc->mt_base + 0x01);
+}
+
+#if 0
+/*
+ * S/PDIF register access doesn't work so this feature is not enabled.
+ */
+
+#define EWX_CLK 0x20
+#define EWX_DTA 0x10
+
+static void
+dmx6fire_iic_write_byte (envy24_devc * devc, unsigned char data,
+			 unsigned char save)
+{
+  int i;
+  unsigned char gpio;
+
+  for (i = 0; i < 8; i++)
+    {
+      int fData = (data & 0x80) ? 1 : 0;
+
+      gpio = 0x08;
+      if (fData)
+	gpio |= EWX_DTA;	/* DATA */
+      envy24_write_cci (devc, 0x20, gpio | save);
+      envy24_write_cci (devc, 0x20, gpio | EWX_CLK | save);	/*  Clock pulse */
+      envy24_write_cci (devc, 0x20, gpio | save);
+
+      data <<= 1;
+    }
+
+  envy24_write_cci (devc, 0x20, EWX_DTA | save);
+  envy24_write_cci (devc, 0x20, EWX_DTA | EWX_CLK | save);	/*  Clock pulse  (ACK) */
+  envy24_write_cci (devc, 0x20, EWX_DTA | save);
+}
+
+static unsigned char
+dmx6fire_iic_read_byte (envy24_devc * devc, unsigned char save)
+{
+  int i;
+  unsigned char data = 0;
+  int b;
+
+  PRT_STATUS (0x01);
+  save |= EWX_DTA;
+  envy24_write_cci (devc, 0x20, save);
+  oss_udelay (10);
+#if 1
+  save &= ~8;			/* R/W bit */
+  envy24_write_cci (devc, 0x22, ~EWX_DTA);	/* GPIO direction */
+  envy24_write_cci (devc, 0x21, EWX_DTA);	/* GPIO write mask */
+#endif
+
+  for (i = 0; i < 8; i++)
+    {
+
+      envy24_write_cci (devc, 0x20, EWX_CLK | save);	/*  Clock pulse */
+      b = envy24_read_cci (devc, 0x20);
+      if (b & EWX_DTA)
+	data |= 0x80;
+      envy24_write_cci (devc, 0x20, save);
+
+      data >>= 1;
+    }
+
+  envy24_write_cci (devc, 0x22, 0xff);	/* GPIO direction */
+  envy24_write_cci (devc, 0x21, 0x00);	/* GPIO write mask */
+  envy24_write_cci (devc, 0x20, (save & ~EWX_DTA) | 0x08);	/* Low for the ACK bit */
+  envy24_write_cci (devc, 0x20, (save & ~EWX_DTA) | 0x08 | EWX_CLK);	/* Clock for the ACK bit */
+  envy24_write_cci (devc, 0x20, save | 0x08);
+  oss_udelay (10);
+  return data;
+}
+
+#if 0
+static void
+dmx6fire_iic_write (envy24_devc * devc, int addr,
+		    unsigned char bRegIdx, unsigned char bRegData)
+{
+  unsigned char save;
+
+  /* start write cycle */
+  envy24_write_cci (devc, 0x22, 0xff);	/* GPIO direction */
+  envy24_write_cci (devc, 0x21, 0x00);	/* GPIO write mask */
+
+  save = (envy24_read_cci (devc, 0x20) & ~(EWX_CLK | EWX_DTA)) | 0x08	/* R/W bit */
+    ;
+  /* Send start */
+  envy24_write_cci (devc, 0x20, save | EWX_CLK | EWX_DTA);
+  envy24_write_cci (devc, 0x20, save | EWX_CLK);
+  envy24_write_cci (devc, 0x20, save);
+
+  dmx6fire_iic_write_byte (devc, addr, save);
+  dmx6fire_iic_write_byte (devc, bRegIdx, save);
+  dmx6fire_iic_write_byte (devc, bRegData, save);
+
+  /* Send stop */
+  envy24_write_cci (devc, 0x20, save);
+  envy24_write_cci (devc, 0x20, save | EWX_CLK);
+  envy24_write_cci (devc, 0x20, save | EWX_CLK | EWX_DTA);
+}
+#endif
+
+static unsigned char
+dmx6fire_iic_read (envy24_devc * devc, int addr, unsigned char bRegIdx)
+{
+  unsigned char save, data;
+
+  /* dmx6fire_iic_write(devc, addr, bRegIdx, 0x55); */
+  PRT_STATUS (0x80);
+
+  envy24_write_cci (devc, 0x22, 0xff);	/* GPIO direction */
+  envy24_write_cci (devc, 0x21, 0x00);	/* GPIO write mask */
+
+  save = (envy24_read_cci (devc, 0x20) & ~(EWX_DTA | EWX_CLK)) | 0x08	/* R/W bit */
+    ;
+  PRT_STATUS (0x02);
+  /* Send start */
+  envy24_write_cci (devc, 0x20, save | EWX_CLK | EWX_DTA);
+  envy24_write_cci (devc, 0x20, save | EWX_CLK);
+  envy24_write_cci (devc, 0x20, save);
+
+  dmx6fire_iic_write_byte (devc, addr | 0x01, save);
+  data = dmx6fire_iic_read_byte (devc, save);
+
+  /* Send stop */
+  envy24_write_cci (devc, 0x20, save);
+  envy24_write_cci (devc, 0x20, save | EWX_CLK);
+  envy24_write_cci (devc, 0x20, save | EWX_CLK | EWX_DTA);
+  PRT_STATUS (0x00);
+  return data;
+}
+
+static int
+read_dmx6fire_spdif_reg (envy24_devc * devc, int bRegister)
+/*
+*****************************************************************************
+*  Reads a byte from a specific CS8427 register.
+****************************************************************************/
+{
+
+  unsigned char ret;
+  ret = dmx6fire_iic_read (devc, EWX_DIG_ADDR, bRegister);
+
+  return ret;
+}
+
+static void
+write_dmx6fire_spdif_reg (envy24_devc * devc, int bRegister, int bData)
+{
+
+  /*dmx6fire_iic_write(devc, EWX_DIG_ADDR, bRegister, bData); */
+  IIC_WriteWord (devc, EWX_DIG_ADDR, bRegister, bData);
+}
+#else
+static int
+read_dmx6fire_spdif_reg (envy24_devc * devc, int bRegister)
+{
+  return 0;
+}
+
+static void
+write_dmx6fire_spdif_reg (envy24_devc * devc, int bRegister, int bData)
+{
+}
+#endif
+
+static void
+dmx6fire_card_init (envy24_devc * devc)
+{
+  envy24_write_cci (devc, 0x20, 0xff);
+  envy24_write_cci (devc, 0x21, 0x00);
+  envy24_write_cci (devc, 0x22, 0xff);
+  envy24_write_cci (devc, 0x20, 0xff);
+  HW_AK4525_SetChipSelect (devc, 0x00);
+#if 1
+
+  IIC_WriteWord (devc, 0x40, 0x02, 0x00);	/* Polarity register */
+  IIC_WriteWord (devc, 0x40, 0x03, 0x00);	/* Direction register */
+
+  FrontboxControl (devc, DEFAULT_FRONTBOX_SETUP);	/* Set default values */
+
+  if (!HW_AK4525_Reset (devc, -1))
+    cmn_err (CE_CONT, "Envy24: DMX6fire reset failed\n");;
+#endif
+
+}
+
+static int
+dmx6fire_mixer_set (int dev, int ctrl, unsigned int cmd, int value)
+{
+  envy24_devc *devc = mixer_devs[dev]->devc;
+
+  if (cmd == SNDCTL_MIX_READ)
+    switch (ctrl)
+      {
+      case 1:
+	if (devc->skipdevs == 2)
+	  return devc->rec_portc[2].riaa_filter;
+	else
+	  return devc->rec_portc[4].riaa_filter;
+	break;
+
+      }
+
+  if (cmd == SNDCTL_MIX_WRITE)
+    switch (ctrl)
+      {
+      case 1:
+	if (devc->skipdevs == 2)
+	  return devc->rec_portc[2].riaa_filter = !!value;
+	else
+	  return devc->rec_portc[4].riaa_filter = !!value;
+	break;
+
+      }
+
+  return OSS_EINVAL;
+}
+
+static int
+dmx6fire_mix_init (envy24_devc * devc, int dev, int group)
+{
+  int err;
+#if 0
+  int i, mask = devc->outportmask, skip, codec, ports;
+  int range = 3;
+  int typ = MIXT_ENUM;
+  if ((group = mixer_ext_create_group (dev, 0, "ENVY24_GAIN")) < 0)
+    return group;
+
+  skip = devc->skipdevs;
+  if (skip != 2)
+    skip = 1;
+
+  if (envy24_gain_sliders)
+    {
+      typ = MIXT_MONOSLIDER;
+      range = 164;
+
+      for (i = 0; i < 0xff; i++)
+	devc->akm_gains[i] = 0x7f;
+    }
+  else
+    for (i = 0; i < 0xff; i++)
+      devc->akm_gains[i] = 0;
+
+  for (i = 0; i < 8; i += skip)
+    {
+      char tmp[32];
+
+      if (!(mask & (1 << i)))
+	continue;		/* Not present */
+
+      if (devc->skipdevs == 2)
+	{
+	  if (i == 8)
+	    strcpy (tmp, "ENVY24_SPDOUT");
+	  else
+	    sprintf (tmp, "ENVY24_OUT%d/%d", i + 1, i + 2);
+
+	  codec = (i > 1) ? AKM_B : AKM_A;
+	  ports = 0x0c;		/* Both output ports */
+	  if ((err = mixer_ext_create_control (dev, group,
+					       codec | ports, envy24_set_tdif,
+					       typ,
+					       tmp, range,
+					       MIXF_MAINVOL |
+					       MIXF_READABLE |
+					       MIXF_WRITEABLE)) < 0)
+	    return err;
+	}
+      else
+	{
+	  if (i == 8)
+	    strcpy (tmp, "ENVY24_SPDOUTL");
+	  else if (i == 9)
+	    strcpy (tmp, "ENVY24_SPDOUTR");
+	  else
+	    sprintf (tmp, "ENVY24_OUT%d", i + 1);
+
+	  codec = (i > 1) ? AKM_B : AKM_A;
+	  ports = (i & 1) ? 0x08 : 0x04;
+	  if ((err = mixer_ext_create_control (dev, group,
+					       codec | ports, envy24_set_tdif,
+					       typ,
+					       tmp, range,
+					       MIXF_MAINVOL |
+					       MIXF_READABLE |
+					       MIXF_WRITEABLE)) < 0)
+	    return err;
+	}
+    }
+#endif
+
+  if ((group = mixer_ext_create_group (dev, 0, "ENVY24_6FIRE")) < 0)
+    return group;
+
+  if ((err = mixer_ext_create_control (dev, group,
+				       1, dmx6fire_mixer_set,
+				       MIXT_ONOFF,
+				       "6FIRE_RIAA", 2,
+				       MIXF_READABLE | MIXF_WRITEABLE)) < 0)
+    return err;
+
+  return 0;
+}
+
+envy24_auxdrv_t dmx6fire_auxdrv = {
+  dmx6fire_card_init,
+  dmx6fire_mix_init,
+  init_cs8427_spdif,
+  write_cs8427_spdif,
+  NULL,
+  read_dmx6fire_spdif_reg,
+  write_dmx6fire_spdif_reg,
+  set_dmx6fire_speed,
+  NULL,
+  cs8427_spdif_mixer_init
+};
diff --git a/kernel/drv/oss_envy24/envy24_default.c b/kernel/drv/oss_envy24/envy24_default.c
new file mode 100644
index 0000000..21baa45
--- /dev/null
+++ b/kernel/drv/oss_envy24/envy24_default.c
@@ -0,0 +1,2384 @@
+/*
+ * Purpose: Card specific routines for several Envy24 based cards.
+ */
+/*
+ *
+ * This file is part of Open Sound System.
+ *
+ * Copyright (C) 4Front Technologies 1996-2008.
+ *
+ * This this source file is released under GPL v2 license (no other versions).
+ * See the COPYING file included in the main directory of this source
+ * distribution for the license terms and conditions.
+ *
+ */
+
+#include "oss_config.h"
+#include "ac97.h"
+#include "envy24.h"
+
+#if 0
+# define PRT_STATUS(v) outb(v&0xff, 0x378)
+#else
+# define PRT_STATUS(v)
+#endif
+
+extern int envy24_gain_sliders;
+extern int envy24_virtualout;
+extern int envy24_zerolatency;	/* Testing in progress */
+
+#define EWX_DIG_ADDR 0x20	/* IIC address of digital traceiver chip of EWX2496 */
+
+/*
+ * Playback engine management
+ */
+
+static void
+write_spdif (envy24_devc * devc, int d)
+{
+  int i, cmd;
+
+  cmd = envy24_read_cci (devc, 0x20);
+  for (i = 7; i >= 0; i--)
+    {
+      cmd &= ~0x04;
+      envy24_write_cci (devc, 0x20, cmd);
+      oss_udelay (1);
+      if (d & (1 << i))
+	cmd |= 0x08;
+      else
+	cmd &= ~0x08;
+      cmd |= 0x04;
+      envy24_write_cci (devc, 0x20, cmd);
+      oss_udelay (1);
+    }
+  cmd &= ~0x04;
+  envy24_write_cci (devc, 0x20, cmd);
+}
+
+static void
+write_codec (envy24_devc * devc, int codec, int addr, int data)
+{
+  unsigned char cmd;
+  int i;
+  int tmp;
+  cmd = envy24_read_cci (devc, 0x20);
+  cmd &= ~codec;
+  envy24_write_cci (devc, 0x20, cmd);
+  oss_udelay (1);
+  addr &= 0x07;
+  tmp = 0xa000 | (addr << 8) | data;
+  for (i = 15; i >= 0; i--)
+    {
+      cmd &= ~0x30;
+      if (tmp & (1 << i))
+	cmd |= 0x10;
+      envy24_write_cci (devc, 0x20, cmd);
+      oss_udelay (1);
+      cmd |= 0x20;
+      envy24_write_cci (devc, 0x20, cmd);
+      oss_udelay (1);
+    }
+  cmd |= codec;
+  envy24_write_cci (devc, 0x20, cmd);
+  oss_udelay (1);
+}
+
+#define CDC_CLK 1		/* Clock input to the CODEC's, rising edge clocks data. */
+#define CDC_DIN 2		/* Data input to Envy from the CODEC. */
+#define CDC_DOUT 3		/* Data output from Envy to the CODEC. */
+#define DIG_CS 4		/* Chip select (0=select) for the SPDIF tx/rx. */
+#define CDC_CS 5		/* Chip select (0=select) for the CODEC. */
+#define D410_MUTE	7	/* Delta 410 codec mute */
+#define CS_ASSERT 0		/* Asserted chip select (selects are inverted). */
+#define CS_RELEASE 1		/* Idle chip select (selects are inverted). */
+
+
+#define CS8_CLK CDC_CLK
+#define CS8_DIN CDC_DIN
+#define CS8_DOUT CDC_DOUT
+#define CS8_CS DIG_CS
+#define CS_1 CS_ASSERT
+#define CS_0 CS_RELEASE
+#define CS8_ADDR 0x20		/* Chip SPI/I2C address */
+#define CS8_RD 0x01
+#define CS8_WR 0x00
+
+#define EWX_DIG_CS				0
+#define EWX_CDC_CLK				5
+#define EWX_CDC_DOUT			4
+#define EWX_CDC_DIN 			EWX_CDC_DOUT
+#define EWX_IIC_WRITE			3
+#define CX_ASSERT 0		/* Asserted chip select (selects are inverted). */
+#define CX_RELEASE 1		/* Idle chip select (selects are inverted). */
+
+void
+WriteGPIObit (envy24_devc * devc, int sel, int what)
+{
+  unsigned char gpio;
+
+  gpio = envy24_read_cci (devc, 0x20);
+  gpio &= ~(1 << sel);
+  gpio |= (what << sel);
+  envy24_write_cci (devc, 0x20, gpio);
+}
+
+int
+ReadGPIObit (envy24_devc * devc, int sel)
+{
+  unsigned char gpio;
+
+  gpio = envy24_read_cci (devc, 0x20);
+  return !!(gpio & (1 << sel));
+}
+
+static void
+write_ap_codec (envy24_devc * devc, int bRegister, unsigned char bData)
+/*
+
+*****************************************************************************
+*  Writes a byte to a specific register of the Delta-AP CODEC.
+*  Register must be (0..15).
+****************************************************************************/
+{
+  unsigned char bMask;
+
+  if (devc->model_data->flags & MF_D410)
+    bRegister = (bRegister & 0x0F) | 0x20;	/* Add I2C address field. */
+  else
+    bRegister = (bRegister & 0x0F) | 0xA0;	/* Add I2C address field. */
+
+  /* Assert the CODEC chip select and wait at least 150 nS. */
+  /* */
+  WriteGPIObit (devc, CDC_CS, CS_ASSERT);
+  WriteGPIObit (devc, DIG_CS, CS_RELEASE);
+
+  /* Write the register address byte. */
+  /* */
+  for (bMask = 0x80; bMask; bMask = (bMask >> 1) & 0x7F)
+    {
+      /* Drop SPI clock low. */
+      WriteGPIObit (devc, CDC_CLK, 0);
+
+      /* Write current data bit. */
+      if (bMask & bRegister)
+	WriteGPIObit (devc, CDC_DOUT, 1);
+      else
+	WriteGPIObit (devc, CDC_DOUT, 0);
+
+      /* Raise SPI clock to "clock data in". */
+      WriteGPIObit (devc, CDC_CLK, 1);
+    }
+
+
+  /* Write the data byte. */
+  /* */
+  for (bMask = 0x80; bMask; bMask = (bMask >> 1) & 0x7F)
+    {
+      /* Drop SPI clock low. */
+      WriteGPIObit (devc, CDC_CLK, 0);
+
+      /* Write current data bit. */
+      if (bMask & bData)
+	WriteGPIObit (devc, CDC_DOUT, 1);
+      else
+	WriteGPIObit (devc, CDC_DOUT, 0);
+
+      /* Raise SPI clock to "clock data in". */
+      WriteGPIObit (devc, CDC_CLK, 1);
+    }
+
+  /* De-assert chip select. */
+  /* */
+  WriteGPIObit (devc, CDC_CS, CS_RELEASE);
+}
+static int
+read_ap_spdif_reg (envy24_devc * devc, int bRegister)
+/*
+*****************************************************************************
+*  Reads a byte from a specific CS8427 register.
+****************************************************************************/
+{
+  unsigned char bMask;
+  unsigned char bRet = 0;
+  unsigned char bSPI;
+
+	/****** WRITE MAP ADDRESS FIRST ******/
+
+  /* Drop the chip select low. */
+  /* Wait at least 150 nS. */
+  /* */
+  WriteGPIObit (devc, DIG_CS, CS_ASSERT);
+
+  /* Write the SPI address/cmd byte. */
+  /* */
+  bSPI = CS8_ADDR + CS8_WR;	/* SPI address field plus WRITE operation. */
+  /* */
+  for (bMask = 0x80; bMask; bMask = (bMask >> 1) & 0x7F)
+    {
+      /* Drop clock (GPIO5) low. */
+      WriteGPIObit (devc, CDC_CLK, 0);
+
+      /* Write current data bit. */
+      if (bMask & bSPI)
+	WriteGPIObit (devc, CDC_DOUT, 1);
+      else
+	WriteGPIObit (devc, CDC_DOUT, 0);
+
+      /* Raise clock (GPIO5). */
+      WriteGPIObit (devc, CDC_CLK, 1);
+    }
+
+
+  /* Write the address (MAP) byte. */
+  /* */
+  for (bMask = 0x80; bMask; bMask = (bMask >> 1) & 0x7F)
+    {
+      /* Drop clock (GPIO5) low. */
+      WriteGPIObit (devc, CDC_CLK, 0);
+
+      /* Write current data bit. */
+      if (bMask & bRegister)
+	WriteGPIObit (devc, CDC_DOUT, 1);
+      else
+	WriteGPIObit (devc, CDC_DOUT, 0);
+
+      /* Raise clock (GPIO5). */
+      WriteGPIObit (devc, CDC_CLK, 1);
+    }
+
+  /* De-assert chip select(s). */
+  /* */
+  WriteGPIObit (devc, DIG_CS, CS_RELEASE);
+
+
+	/****** NOW READ THE DATA ******/
+
+  /* Drop the chip select low. */
+  /* Wait at least 150 nS. */
+  /* */
+  WriteGPIObit (devc, DIG_CS, CS_ASSERT);
+
+
+  /* Write the SPI address/cmd byte. */
+  /* */
+  bSPI = CS8_ADDR + CS8_RD;	/* SPI address field plus READ operation. */
+  /* */
+  for (bMask = 0x80; bMask; bMask = (bMask >> 1) & 0x7F)
+    {
+      /* Drop clock (GPIO5) low. */
+      WriteGPIObit (devc, CDC_CLK, 0);
+
+      /* Write current data bit. */
+      if (bMask & bSPI)
+	WriteGPIObit (devc, CDC_DOUT, 1);
+      else
+	WriteGPIObit (devc, CDC_DOUT, 0);
+
+      /* Raise clock (GPIO5). */
+      WriteGPIObit (devc, CDC_CLK, 1);
+    }
+
+
+  /* Read the data byte. */
+  /* */
+  bRet = 0;
+  /* */
+  for (bMask = 0x80; bMask; bMask = (bMask >> 1) & 0x7F)
+    {
+      /* Drop clock low. */
+      WriteGPIObit (devc, CDC_CLK, 0);
+
+      /* Read current data bit. */
+      if (ReadGPIObit (devc, CDC_DIN))
+	bRet |= bMask;
+
+      /* Raise clock. */
+      WriteGPIObit (devc, CDC_CLK, 1);
+    }
+
+
+  /* De-assert chip selects. */
+  /* */
+  WriteGPIObit (devc, DIG_CS, CS_RELEASE);
+
+  /* Return value. */
+
+  return bRet;
+}
+
+static unsigned char
+ewx2496_iic_read (envy24_devc * devc, int addr, unsigned char bRegIdx);
+
+static int
+read_ewx2496_spdif_reg (envy24_devc * devc, int bRegister)
+/*
+*****************************************************************************
+*  Reads a byte from a specific CS8427 register.
+****************************************************************************/
+{
+  unsigned char ret;
+
+  ret = ewx2496_iic_read (devc, EWX_DIG_ADDR, bRegister);
+
+  return ret;
+}
+
+#define read_cs8427_spdif_reg(d, r) devc->model_data->auxdrv->spdif_read_reg(d, r)
+
+static void
+write_ap_spdif_reg (envy24_devc * devc, int bRegister, int bData)
+/*
+*****************************************************************************
+*  Writes a byte to a specific register of the Delta-AP S/PDIF chip.
+*  Register must be (0..55).
+****************************************************************************/
+{
+  unsigned char bMask;
+  unsigned char bSPI;
+
+  /* Assert the CODEC chip select and wait at least 150 nS. */
+  /* */
+  WriteGPIObit (devc, CDC_CS, CS_0);
+  WriteGPIObit (devc, CS8_CS, CS_1);
+
+  /* Write the SPI address/cmd byte. */
+  /* */
+  bSPI = CS8_ADDR | CS8_WR;
+  /* */
+  for (bMask = 0x80; bMask; bMask = (bMask >> 1) & 0x7F)
+    {
+      /* Drop SPI clock low. */
+      WriteGPIObit (devc, CS8_CLK, 0);
+
+      /* Write current data bit. */
+      if (bMask & bSPI)
+	WriteGPIObit (devc, CS8_DOUT, 1);
+      else
+	WriteGPIObit (devc, CS8_DOUT, 0);
+
+      /* Raise SPI clock to "clock data in". */
+      WriteGPIObit (devc, CS8_CLK, 1);
+    }
+
+  /* Write the address (MAP) byte. */
+  /* */
+  for (bMask = 0x80; bMask; bMask = (bMask >> 1) & 0x7F)
+    {
+      /* Drop SPI clock low. */
+      WriteGPIObit (devc, CS8_CLK, 0);
+
+      /* Write current data bit. */
+      if (bMask & bRegister)
+	WriteGPIObit (devc, CS8_DOUT, 1);
+      else
+	WriteGPIObit (devc, CS8_DOUT, 0);
+
+      /* Raise SPI clock to "clock data in". */
+      WriteGPIObit (devc, CS8_CLK, 1);
+    }
+
+
+  /* Write the data byte. */
+  /* */
+  for (bMask = 0x80; bMask; bMask = (bMask >> 1) & 0x7F)
+    {
+      /* Drop SPI clock low. */
+      WriteGPIObit (devc, CS8_CLK, 0);
+
+      /* Write current data bit. */
+      if (bMask & bData)
+	WriteGPIObit (devc, CS8_DOUT, 1);
+      else
+	WriteGPIObit (devc, CS8_DOUT, 0);
+
+      /* Raise SPI clock to "clock data in". */
+      WriteGPIObit (devc, CS8_CLK, 1);
+    }
+
+  /* De-assert chip select. */
+  /* */
+  WriteGPIObit (devc, CS8_CS, CS_0);
+}
+
+static void
+ewx2496_iic_write (envy24_devc * devc, int addr,
+		   unsigned char bRegIdx, unsigned char bRegData);
+
+static void
+write_ewx2496_spdif_reg (envy24_devc * devc, int bRegister, int bData)
+{
+  ewx2496_iic_write (devc, EWX_DIG_ADDR, bRegister, bData);
+
+}
+
+#define write_cs8427_spdif_reg(d, r, b) devc->model_data->auxdrv->spdif_write_reg(d, r, b)
+
+#define BIT0		0x01
+#define BIT1		0x02
+#define BIT2		0x04
+#define BIT3		0x08
+#define BIT4		0x10
+#define BIT5		0x20
+#define BIT6		0x40
+#define BIT7		0x80
+
+static void
+lock_cs8427_spdif (envy24_devc * devc)
+{
+  write_cs8427_spdif_reg (devc, 18, read_cs8427_spdif_reg (devc, 18) & ~BIT5);
+  write_cs8427_spdif_reg (devc, 18, read_cs8427_spdif_reg (devc, 18) | BIT2);
+}
+
+static void
+unlock_cs8427_spdif (envy24_devc * devc)
+{
+  write_cs8427_spdif_reg (devc, 18, read_cs8427_spdif_reg (devc, 18) & ~BIT2);
+}
+
+static unsigned char
+bitswap (unsigned char bIn)
+/*
+*****************************************************************************
+*  Endian reversing routine.
+****************************************************************************/
+{
+  unsigned char bOut = 0;
+  unsigned char bImask = 0x01;
+  unsigned char bOmask = 0x80;
+
+  while (bImask)
+    {
+      if (bIn & bImask)
+	bOut |= bOmask;
+      bImask = bImask << 1;
+      bOmask = (bOmask >> 1) & 0x7F;
+    }
+
+  return bOut;
+}
+
+
+static unsigned char
+ReadCsByte (envy24_devc * devc, unsigned char bByteNum)
+/*
+*****************************************************************************
+*  Reads a byte from Channel Status block buffer in CS8427.
+*
+*  bByteNum is in the range (0..23)
+*
+*  This routine assumes that CS8427 register 18 bit 5 is cleared so that the
+*  CS buffer is windowed, and that register 18 bit 2 is set so that CS output
+*  transfers are currently disabled.
+****************************************************************************/
+{
+  unsigned char bTemp;
+
+  /* CS block window starts at reg #32... */
+  bTemp = read_cs8427_spdif_reg (devc, bByteNum + 32);
+
+  /* CS block access is reverse endian. */
+  return bitswap (bTemp);
+}
+
+static void
+WriteCsByte (envy24_devc * devc, unsigned char bByteNum, unsigned char bData)
+/*
+*****************************************************************************
+*  Writes a byte to Channel Status block buffer in CS8427.
+*
+*  bByteNum is in the range (0..23)
+*
+*  This routine assumes that CS8427 register 18 bit 5 is cleared so that the
+*  CS buffer is windowed, and that register 18 bit 2 is set so that CS output
+*  transfers are currently disabled.
+****************************************************************************/
+{
+  /* CS block access is reverse endian. */
+  bData = bitswap (bData);
+
+  /* CS Window starts at reg #32... */
+  write_cs8427_spdif_reg (devc, bByteNum + 32, bData);
+}
+
+void
+InitConsumerModeCS (envy24_devc * devc)
+{
+  int i;
+
+  /* Set CS8427 registers 32-55 to window CS block, and disable CS output. */
+  lock_cs8427_spdif (devc);
+
+  /* Zero all the general CS bits. */
+  /* */
+  for (i = 0; i < 24; i++)
+    WriteCsByte (devc, i, 0x00);
+  /* */
+  /* Consumer (usually SPDIF or AC3) mode static bit settings. */
+  /* */
+  WriteCsByte (devc, 0, 0x00);	/* Consumer format (bit0 = 0). */
+  WriteCsByte (devc, 1, 0x02);	/* Category = PCM encoder/decoder. */
+
+  unlock_cs8427_spdif (devc);
+}
+
+void
+init_cs8427_spdif (envy24_devc * devc)
+{
+  int tmp;
+
+  /* Select iunternal sync */
+  write_cs8427_spdif_reg (devc, 4, read_cs8427_spdif_reg (devc, 4) & (~BIT0));
+/*
+*****************************************************************************
+*  Initializes core (mainly static) registers of the CS8427.
+*  Returns 1 if initialization OK, otherwise 0.
+****************************************************************************/
+  /* Assumes Envy24 GPIO's have been initialized.  They should be just fine */
+  /* in the Windows driver as they are initialized from EEPROM info. */
+
+  /* Verify device ID register.  Must be 0x71. */
+  if ((tmp = read_cs8427_spdif_reg (devc, 127)) != 0x71 && tmp != 0)
+    {
+      cmn_err (CE_CONT, "Envy24: Unrecognized S/PDIF chip ID %02x\n",
+	       read_cs8427_spdif_reg (devc, 127));
+      cmn_err (CE_CONT,
+	       "        Hardware stalled. Please reboot and try again.\n");
+      return;
+    }
+
+  /* Turn off RUN bit while making changes to configuration. */
+  write_cs8427_spdif_reg (devc, 4, read_cs8427_spdif_reg (devc, 4) & (~BIT6));
+
+  /* RMCK default function, set Validity, disable mutes, TCBL=output. */
+  write_cs8427_spdif_reg (devc, 1, 0x01);	/* validity* is BIT6. */
+
+  /* Hold last valid audio sample, RMCK=256*Fs, normal stereo operation. */
+  write_cs8427_spdif_reg (devc, 2, 0x00);
+  /* Output drivers normal operation, Tx <== serial audio port, */
+  /* Rx ==> serial audio port. */
+  write_cs8427_spdif_reg (devc, 3, 0x0C);
+
+  /* RUN off, OMCK=256xFs, output time base = OMCK, input time base = */
+  /* recovered input clock, recovered input clock source is Envy24. */
+  write_cs8427_spdif_reg (devc, 4, 0x00);
+
+  /* Serial audio input port data format = I2S. */
+  write_cs8427_spdif_reg (devc, 5, BIT2 | BIT0);	/* SIDEL=1, SILRPOL=1. */
+
+  /* Serial audio output port data format = I2S. */
+  write_cs8427_spdif_reg (devc, 6, BIT2 | BIT0);	/* SODEL=1, SOLRPOL=1. */
+
+  /* Turn off CS8427 interrupt stuff that we don't implement in our hardware. */
+  write_cs8427_spdif_reg (devc, 9, 0x00);
+  write_cs8427_spdif_reg (devc, 10, 0x00);
+  write_cs8427_spdif_reg (devc, 11, 0x00);
+  write_cs8427_spdif_reg (devc, 12, 0x00);
+  write_cs8427_spdif_reg (devc, 13, 0x00);
+  write_cs8427_spdif_reg (devc, 14, 0x00);
+
+  /* Unmask the input PLL lock, V, confidence, biphase, parity status bits. */
+  write_cs8427_spdif_reg (devc, 17,
+			  (unsigned char) BIT4 | BIT3 | BIT2 | BIT1 | BIT0);
+
+  /* Registers 32-55 window to CS buffer. */
+  /* Inhibit D->E transfers from overwriting first 5 bytes of CS data. */
+  /* Inhibit D->E transfers (all) of CS data. */
+  /* Allow E->F transfers of CS data. */
+  /* One-byte mode: both A/B channels get same written CS data. */
+  /* A channel info is output to chip's EMPH* pin. */
+  /* */
+  write_cs8427_spdif_reg (devc, 18, 0x18);
+
+  /* Use internal buffer to transmit User (U) data.    */
+  /* Chip's U pin is an output. */
+  /* Transmit all 0's for user data. */
+  /* */
+  write_cs8427_spdif_reg (devc, 19, 0x10);
+
+  /* Turn on chip's RUN bit, rock and roll! */
+  /* */
+  write_cs8427_spdif_reg (devc, 4, read_cs8427_spdif_reg (devc, 4) | BIT6);
+  InitConsumerModeCS (devc);
+
+}
+
+#if 0
+static void
+WriteCsField (envy24_devc * devc, unsigned char bByteNum,
+	      unsigned short bMask, unsigned short bBits)
+/*
+*****************************************************************************
+*  Writes a specific field within the Channel Status block buffer.
+*		bByteNum is CS byte number to access (0..23).
+*		bMask is the field to be written (set bits define field).
+*		bBits is the value to write into that field.
+*
+*  Assumes: Reg 18 Bit 5 is cleared so CS buffer is accessible.
+*			Reg 18 Bit 2 is set so E->F buffer transfer is stopped.
+****************************************************************************/
+{
+  /* Get current reg value. */
+  unsigned char bTemp = ReadCsByte (devc, bByteNum);
+
+  /* Clear field to be written. */
+  bTemp &= ~(bMask);
+
+  /* Set new values. */
+  WriteCsByte (devc, bByteNum, (unsigned char) (bTemp | (bBits & bMask)));
+}
+#endif
+
+/*ARGSUSED*/ 
+void
+write_cs8427_spdif (envy24_devc * devc, int d)
+{
+  int i;
+
+  if (devc->syncsource == SYNC_INTERNAL)
+    {
+      write_cs8427_spdif_reg (devc, 4,
+			      read_cs8427_spdif_reg (devc, 4) & ~BIT0);
+    }
+  else
+    {
+      write_cs8427_spdif_reg (devc, 4,
+			      read_cs8427_spdif_reg (devc, 4) | BIT0);
+    }
+
+  lock_cs8427_spdif (devc);
+  for (i = 0; i < 24; i++)
+    {
+      WriteCsByte (devc, i, devc->spdif_cbits[i]);
+    }
+  unlock_cs8427_spdif (devc);
+}
+
+/*
+ * Terratec stuff
+ */
+
+/*=============================================================================
+  Function    : IIC_GetSDA
+-------------------------------------------------------------------------------
+  Description : 
+  Returns     : unsigned char  -> 
+  Parameters  : unsigned long dwPortAddr -> 
+-------------------------------------------------------------------------------
+  Notes       : 
+=============================================================================*/
+/*ARGSUSED*/ 
+static unsigned char
+IIC_GetSDA (envy24_devc * devc, unsigned long dwPortAddr)
+{
+
+  unsigned char bReg, bSDA;
+
+  /* FMB TEST: RW line */
+  /* set write mask */
+  bReg = ~(0x08);		/* writeable */
+  envy24_write_cci (devc, 0x21, bReg);
+
+  /* set RW line LOW */
+  bReg = 0;			/* writeable */
+  envy24_write_cci (devc, 0x20, bReg);
+
+  /* Set direction: SDA to input and SCL to output */
+  bReg = envy24_read_cci (devc, 0x22);
+  bReg |= 0x20;			/* SCL output = 1 */
+  bReg &= ~0x10;		/* SDA input  = 0 */
+  envy24_write_cci (devc, 0x22, bReg);
+
+  /* Get SDA line state */
+  bSDA = envy24_read_cci (devc, 0x20);
+
+
+  /* set RW line HIGH */
+  bReg = 0x08;			/* writeable */
+  envy24_write_cci (devc, 0x20, bReg);
+
+  return 1;
+  /* return ((bSDA & 0x10) == 0x10); */
+
+}
+
+/*=============================================================================
+  Function    : IIC_SetIic
+-------------------------------------------------------------------------------
+  Description : 
+  Returns     : void  -> 
+  Parameters  : unsigned int dwPortAddr -> 
+              : unsigned char fSDA -> 
+              : unsigned char fSCL -> 
+-------------------------------------------------------------------------------
+  Notes       : 
+=============================================================================*/
+/*ARGSUSED*/ 
+static void
+IIC_SetIic (envy24_devc * devc, unsigned int dwPortAddr, unsigned char fSDA,
+	    unsigned char fSCL)
+{
+  unsigned char bReg;
+
+  /* Set direction: SDA and SCL to output */
+  bReg = envy24_read_cci (devc, 0x22);
+  bReg |= (0x20 | 0x10);	/* 1 -> output */
+  envy24_write_cci (devc, 0x22, bReg);
+
+  /* set write mask */
+  bReg = ~(0x20 | 0x10);	/* writeable */
+  envy24_write_cci (devc, 0x21, bReg);
+
+  /* Set line state */
+  /* FMB TEST: RW line */
+  bReg = 0x08;
+/*	bReg = 0; */
+  if (fSDA)
+    bReg += 0x10;
+  if (fSCL)
+    bReg += 0x20;
+  envy24_write_cci (devc, 0x20, bReg);
+
+}
+
+/*=============================================================================
+  Function    : IIC_Start
+-------------------------------------------------------------------------------
+  Description : 
+  Returns     : void  -> 
+  Parameters  : unsigned int dwPortAddr -> 
+-------------------------------------------------------------------------------
+  Notes       : 
+=============================================================================*/
+/*__inline  */
+static void
+IIC_Start (envy24_devc * devc, unsigned int dwPortAddr)
+{
+  /* falling edge of SDA while SCL is HIGH */
+  IIC_SetIic (devc, dwPortAddr, 1, 1);
+  IIC_SetIic (devc, dwPortAddr, 0, 1);
+}
+
+/*=============================================================================
+  Function    : IIC_Stop  
+-------------------------------------------------------------------------------
+  Description : 
+  Returns     : void -> 
+  Parameters  : unsigned int dwPortAddr -> 
+-------------------------------------------------------------------------------
+  Notes       : 
+=============================================================================*/
+/*__inline  */
+
+static void
+IIC_Stop (envy24_devc * devc, unsigned int dwPortAddr)
+{
+  /* rising edge of SDA while SCL is HIGH */
+  IIC_SetIic (devc, dwPortAddr, 0, 1);
+  IIC_SetIic (devc, dwPortAddr, 1, 1);
+}
+
+
+/*=============================================================================
+  Function    : IIC_SendByte
+-------------------------------------------------------------------------------
+  Description : 
+  Returns     : unsigned char -> 
+  Parameters  : unsigned int dwPortAddr -> 
+              : unsigned char bByte -> 
+-------------------------------------------------------------------------------
+  Notes       : 
+=============================================================================*/
+/*__inline  */
+static unsigned char
+IIC_SendByte (envy24_devc * devc, unsigned int dwPortAddr,
+	      unsigned char bByte)
+{
+  unsigned char bDataBit, bAck;
+  int i;
+
+  for (i = 7; i >= 0; i--)	/* send byte (MSB first) */
+    {
+      bDataBit = (bByte >> i) & 0x01;
+
+      IIC_SetIic (devc, dwPortAddr, bDataBit, 0);
+      IIC_SetIic (devc, dwPortAddr, bDataBit, 1);
+    }				/* end for i */
+
+  IIC_SetIic (devc, dwPortAddr, 1, 0);
+
+  /* Get acknowledge */
+  IIC_SetIic (devc, dwPortAddr, 1, 1);
+  bAck = IIC_GetSDA (devc, dwPortAddr);
+  /* FMB this is a start condition but never mind */
+  IIC_SetIic (devc, dwPortAddr, 0, 0);
+  return 1;
+  /* return (!bAck); *//* bAck = 0 --> success */
+}
+
+/*=============================================================================
+  Function    : IIC_WriteByte
+-------------------------------------------------------------------------------
+  Description : 
+  Returns     : unsigned char  -> 
+  Parameters  : unsigned int dwPortAddr -> 
+              : unsigned char bIicAddress -> 
+              : unsigned char bByte -> 
+-------------------------------------------------------------------------------
+  Notes       : 
+=============================================================================*/
+static unsigned char
+IIC_WriteByte (envy24_devc * devc, int dwPortAddr, unsigned char bIicAddress,
+	       unsigned char bByte)
+{
+  IIC_Start (devc, dwPortAddr);
+
+  /* send IIC address and data byte */
+  if (!IIC_SendByte (devc, dwPortAddr, bIicAddress))
+    {
+      cmn_err (CE_CONT, "IIC_SendByte 1 failed\n");
+      goto FAILED;
+    }
+  if (!IIC_SendByte (devc, dwPortAddr, bByte))
+    {
+      cmn_err (CE_CONT, "IIC_SendByte 2 failed\n");
+      goto FAILED;
+    }
+
+  IIC_Stop (devc, dwPortAddr);
+  return 1;
+
+FAILED:
+  IIC_Stop (devc, dwPortAddr);
+  return 0;
+}
+
+/*=============================================================================
+    FUNCTION:  HW_AK4525_SetChipSelect
+-------------------------------------------------------------------------------
+	PURPOSE:    
+    PARAMETERS: PDEVICE_EXTENSION pDevExt - contains the port address 
+	                                        and the OUT_SEL state
+                unsigned char bCsMask	- AK4525 CS Mask: 1 means selected
+	RETURNS:    int 
+-------------------------------------------------------------------------------
+	NOTES:       - We use the fact that the parameter bCsMask has the same layout
+	               as the IIC command byte we have to send to the PCF8574
+	               (wrong polarity, however)
+				-  We also have to care that we don't change the output switch
+				   setting. We remember the value in the Device Extension
+				-  It is important that the CODECS are deselected (CS to HIGH)
+				   after sue. Otherwise some IIC functions might accidentally
+				   change our CODEC registers!!!
+=============================================================================*/
+static unsigned char
+HW_AK4525_SetChipSelect (envy24_devc * devc, unsigned char bCsMask)
+{
+  unsigned char bDataByte;
+  /* check validity */
+  if (bCsMask > 0x0F)
+    {
+      cmn_err (CE_CONT, "Invalid bCsMask %02x\n", bCsMask);
+      return 0;			/* invalid  */
+    }
+
+  /* Format data byte */
+  bDataByte = (~bCsMask) & 0x0F;
+  /* FMB PCF8574 HIGH means -10dbV,  */
+  /*     OutputLevelSwitch is 1 for +4dbU */
+  /* if (!pDevExt->Ews88mt.OutputLevelSwitch) */
+  /*  bDataByte += 0x40; */
+
+  /* Set Chip select to LOW for selected Codecs (via IIC) */
+  if (!IIC_WriteByte (devc, devc->ccs_base, 0x48, bDataByte))
+    {
+      cmn_err (CE_CONT, "IIC_WriteByte failed\n");
+      return 0;
+    }
+
+  return 1;
+}
+
+#define HW_AK4525_SetLines IIC_SetIic
+
+/*=============================================================================
+    FUNCTION:   HW_AK4525_WriteRegister 
+-------------------------------------------------------------------------------
+	PURPOSE:    
+    PARAMETERS: unsigned int port      - port address for IIC port
+                unsigned char bCsMask   - CoDec bitmask (bits 0..3)
+		                  or 0xFF for all codecs together
+		unsigned char bRegIdx   - offset to desired register
+                unsigned char bReg      - new register value
+	RETURNS:    
+-------------------------------------------------------------------------------
+	NOTES:      The Chip Selects must have been set prior to this call
+				PCF8574_CODEC_IIC_ADDRESS    
+
+	+-----------------------------------------------------------------+
+	| B15 B14 B13 B12 B11 B10 B09 B08|B07 B06 B05 B04 B03 B02 B01 B00 |
+	+--------+---+-------------------+--------------------------------+
+	| C1  C0 |R/W|A4  A3  A2  A1  A0 |D7  D6  D5  D4  D3  D2  D1  D0  |
+	| 1   0  |1  |        <= 7       |           data                 |
+	+--------+---+-------------------+--------------------------------+
+
+=============================================================================*/
+static unsigned char
+HW_AK4525_WriteRegister (envy24_devc * devc, unsigned char bCsMask,
+			 unsigned char bRegIdx, unsigned char bRegData)
+{
+
+  unsigned short wCmd;
+  unsigned char i;
+  unsigned int port = devc->ccs_base;
+  unsigned char fData;
+
+  /* format buffer */
+  wCmd = 0xA000 +		/* chip address + R/W */
+    (((unsigned short) bRegIdx) << 8) +	/* register address */
+    bRegData;
+
+  /* start write cycle */
+  if (!HW_AK4525_SetChipSelect (devc, bCsMask))
+    {
+      cmn_err (CE_CONT, "HW_AK4525_SetChipSelect failed\n");
+      return 0;			/* = CS to LOW -> data latched */
+    }
+
+
+  for (i = 0; i < 16; i++)
+    {
+      fData = (wCmd & 0x8000) ? 1 : 0;
+      HW_AK4525_SetLines (devc, port, fData, 0);
+      HW_AK4525_SetLines (devc, port, fData, 1);	/* data is clocked in on rising edge of CCLK */
+      wCmd <<= 1;
+    }
+
+  /* leave data line HIGH (= default for IIC) */
+  HW_AK4525_SetLines (devc, port, fData, 0);	/* data is clocked in on rising edge of CCLK */
+
+  /* end write cycle */
+  if (!HW_AK4525_SetChipSelect (devc, 0x00))
+    {
+      cmn_err (CE_CONT, "HW_AK4525_SetChipSelect 2 failed\n");
+      return 0;			/* = all CS to HIGH -> CS to default */
+    }
+
+  /* default */
+  HW_AK4525_SetLines (devc, port, 1, 1);	/* data is clocked in on rising edge of CCLK */
+
+  return 1;
+}
+
+#define EWX_CLK 0x20
+#define EWX_DTA 0x10
+
+static void
+ewx2496_iic_write_byte (envy24_devc * devc, unsigned char data,
+			unsigned char save)
+{
+  int i;
+  unsigned char gpio;
+
+  for (i = 0; i < 8; i++)
+    {
+      int fData = (data & 0x80) ? 1 : 0;
+
+      gpio = 0x08;
+      if (fData)
+	gpio |= EWX_DTA;	/* DATA */
+      envy24_write_cci (devc, 0x20, gpio | save);
+      envy24_write_cci (devc, 0x20, gpio | EWX_CLK | save);	/*  Clock pulse */
+      envy24_write_cci (devc, 0x20, gpio | save);
+
+      data <<= 1;
+    }
+
+  envy24_write_cci (devc, 0x20, EWX_DTA | save);
+  oss_udelay (3);
+  envy24_write_cci (devc, 0x20, EWX_DTA | EWX_CLK | save);	/*  Clock pulse  (ACK) */
+  oss_udelay (1);
+  envy24_write_cci (devc, 0x20, EWX_DTA | save);
+  oss_udelay (1);
+}
+
+static unsigned char
+ewx2496_iic_read_byte (envy24_devc * devc, unsigned char save)
+{
+  int i;
+  unsigned char data = 0;
+  int b;
+
+  PRT_STATUS (0x01);
+  save |= EWX_DTA;
+  envy24_write_cci (devc, 0x20, save);
+  oss_udelay (10);
+#if 0
+  save &= ~8;			/* R/W bit */
+  envy24_write_cci (devc, 0x22, ~EWX_DTA);	/* GPIO direction */
+  envy24_write_cci (devc, 0x21, EWX_DTA);	/* GPIO write mask */
+#endif
+
+  for (i = 0; i < 8; i++)
+    {
+
+      envy24_write_cci (devc, 0x20, EWX_CLK | save);	/*  Clock pulse */
+      b = envy24_read_cci (devc, 0x20);
+      if (b & EWX_DTA)
+	data |= 0x80;
+      envy24_write_cci (devc, 0x20, save);
+
+      data >>= 1;
+    }
+
+  envy24_write_cci (devc, 0x22, 0xff);	/* GPIO direction */
+  envy24_write_cci (devc, 0x21, 0x00);	/* GPIO write mask */
+  envy24_write_cci (devc, 0x20, (save & ~EWX_DTA) | 0x08);	/* Low for the ACK bit */
+  envy24_write_cci (devc, 0x20, (save & ~EWX_DTA) | 0x08 | EWX_CLK);	/* Clock for the ACK bit */
+  envy24_write_cci (devc, 0x20, save | 0x08);
+  oss_udelay (10);
+  return data;
+}
+
+static void
+ewx2496_iic_write (envy24_devc * devc, int addr,
+		   unsigned char bRegIdx, unsigned char bRegData)
+{
+  unsigned char save;
+
+  /* start write cycle */
+  envy24_write_cci (devc, 0x22, 0xff);	/* GPIO direction */
+  envy24_write_cci (devc, 0x21, 0x00);	/* GPIO write mask */
+
+  save = (envy24_read_cci (devc, 0x20) & ~(EWX_CLK | EWX_DTA)) | 0x08	/* R/W bit */
+    ;
+  /* Send start */
+  oss_udelay (1);
+  envy24_write_cci (devc, 0x20, save | EWX_CLK | EWX_DTA);
+  oss_udelay (1);
+  envy24_write_cci (devc, 0x20, save | EWX_CLK);
+  oss_udelay (1);
+  envy24_write_cci (devc, 0x20, save);
+  oss_udelay (1);
+
+  ewx2496_iic_write_byte (devc, addr, save);
+  ewx2496_iic_write_byte (devc, bRegIdx, save);
+  ewx2496_iic_write_byte (devc, bRegData, save);
+
+  /* Send stop */
+  oss_udelay (1);
+  envy24_write_cci (devc, 0x20, save);
+  oss_udelay (1);
+  envy24_write_cci (devc, 0x20, save | EWX_CLK);
+  oss_udelay (1);
+  envy24_write_cci (devc, 0x20, save | EWX_CLK | EWX_DTA);
+}
+
+static unsigned char
+ewx2496_iic_read (envy24_devc * devc, int addr, unsigned char bRegIdx)
+{
+  unsigned char save, data;
+
+  /* ewx2496_iic_write(devc, addr, bRegIdx, 0x55); */
+  PRT_STATUS (0x80);
+
+  envy24_write_cci (devc, 0x22, 0xff);	/* GPIO direction */
+  envy24_write_cci (devc, 0x21, 0x00);	/* GPIO write mask */
+
+  save = (envy24_read_cci (devc, 0x20) & ~(EWX_DTA | EWX_CLK)) | 0x08	/* R/W bit */
+    ;
+  PRT_STATUS (0x02);
+  /* Send start */
+  oss_udelay (1);
+  envy24_write_cci (devc, 0x20, save | EWX_CLK | EWX_DTA);
+  oss_udelay (1);
+  envy24_write_cci (devc, 0x20, save | EWX_CLK);
+  oss_udelay (1);
+  envy24_write_cci (devc, 0x20, save);
+  oss_udelay (1);
+
+  ewx2496_iic_write_byte (devc, addr | 0x01, save);
+  oss_udelay (10);
+  data = ewx2496_iic_read_byte (devc, save);
+
+  /* Send stop */
+  oss_udelay (1);
+  envy24_write_cci (devc, 0x20, save);
+  oss_udelay (1);
+  envy24_write_cci (devc, 0x20, save | EWX_CLK);
+  oss_udelay (1);
+  envy24_write_cci (devc, 0x20, save | EWX_CLK | EWX_DTA);
+  oss_udelay (1);
+  PRT_STATUS (0x00);
+  return data;
+}
+
+static unsigned char
+write_ewx2496_codec (envy24_devc * devc,
+		     unsigned char bRegIdx, unsigned char bRegData)
+{
+
+  unsigned short wCmd;
+  unsigned char i;
+  unsigned char fData;
+  unsigned char gpio, save;
+
+  /* format buffer */
+  wCmd = 0xA000 +		/* chip address + R/W */
+    (((unsigned short) bRegIdx) << 8) +	/* register address */
+    bRegData;
+
+  /* start write cycle */
+  envy24_write_cci (devc, 0x22, 0xff);	/* GPIO direction */
+  envy24_write_cci (devc, 0x21, 0x00);	/* GPIO write mask */
+
+  save = envy24_read_cci (devc, 0x20) & ~0x39;
+  envy24_write_cci (devc, 0x20, save | 0x09);	/* CS inactive */
+  oss_udelay (200);
+  envy24_write_cci (devc, 0x20, 0x08);	/* CS active */
+  oss_udelay (200);
+
+  gpio = 0x08;
+
+  for (i = 0; i < 16; i++)
+    {
+      fData = (wCmd & 0x8000) ? 1 : 0;
+
+      gpio = 0x08;
+      if (fData)
+	gpio |= 0x10;		/* DATA */
+      envy24_write_cci (devc, 0x20, gpio | save);
+      oss_udelay (20);
+      envy24_write_cci (devc, 0x20, gpio | 0x20 | save);	/*  Clock pulse */
+      oss_udelay (200);
+      envy24_write_cci (devc, 0x20, gpio | save);
+
+      wCmd <<= 1;
+    }
+
+  oss_udelay (50);
+  envy24_write_cci (devc, 0x20, 0x01);	/* CS inactive */
+  oss_udelay (20);
+
+  return 1;
+}
+
+/* Register offsets */
+enum
+{
+  AK4525_REG_POWER,
+  AK4525_REG_RESET,
+  AK4525_REG_FORMAT,
+  AK4525_REG_DEEMPHASIS,
+  AK4525_REG_LEFT_INPUT,
+  AK4525_REG_RIGHT_INPUT,
+  AK4525_REG_LEFT_OUTPUT,
+  AK4525_REG_RIGHT_OUTPUT
+};
+
+
+/*=============================================================================
+  Function    : HW_AK4525_Reset
+-------------------------------------------------------------------------------
+  Description : 
+  Returns     : unsigned char 
+  Parameters  : PCUST_HW_INSTANCE_DATA  devc - 
+                int nCodecIdx -> 0..3 index of Codec ,-1 -> all
+-------------------------------------------------------------------------------
+  Notes       : 
+=============================================================================*/
+static unsigned char
+HW_AK4525_Reset (envy24_devc * devc, int nCodecIdx)
+{
+  unsigned char bCodecMask = 0;
+  if (nCodecIdx == -1)
+    bCodecMask = 0x0F;
+  else
+    bCodecMask = 0x01 << (nCodecIdx);
+
+  if (!HW_AK4525_WriteRegister (devc, bCodecMask,	/* 0x0F -> set mode for all codecs */
+				AK4525_REG_RESET, 0x00))	/* DACs,ADCs -> reset */
+    {
+      cmn_err (CE_CONT, "REG_RESET failed\n");
+      return 0;
+    }
+
+  if (!HW_AK4525_WriteRegister (devc, bCodecMask,	/* 0x0F -> set mode for all codecs */
+				AK4525_REG_FORMAT, 0x60))	/* IIS, 256 fsn, normal speed */
+    return 0;
+
+  if (!HW_AK4525_WriteRegister (devc, bCodecMask,	/* 0x0F -> set mode for all codecs */
+				AK4525_REG_RESET, 0x03))	/* DACs,ADCs -> normal operation */
+    return 0;
+
+  if (!HW_AK4525_WriteRegister (devc, bCodecMask,	/* 0x0F -> set mode for all codecs */
+				AK4525_REG_POWER, 0x07))	/* power on */
+    return 0;
+
+  if (!HW_AK4525_WriteRegister (devc, bCodecMask,	/* soft mute timeout --> short */
+				AK4525_REG_DEEMPHASIS, 0x19))
+    return 0;
+
+  if (!HW_AK4525_WriteRegister (devc,
+				bCodecMask, AK4525_REG_LEFT_INPUT, 0x7f))
+    return 0;
+
+  if (!HW_AK4525_WriteRegister (devc,
+				bCodecMask, AK4525_REG_RIGHT_INPUT, 0x7f))
+    return 0;
+
+  if (!HW_AK4525_WriteRegister (devc,
+				bCodecMask, AK4525_REG_LEFT_OUTPUT, 0x7f))
+    return 0;
+
+  if (!HW_AK4525_WriteRegister (devc,
+				bCodecMask, AK4525_REG_RIGHT_OUTPUT, 0x7f))
+    return 0;
+
+  return 1;
+}
+
+unsigned char
+ewx2496_AK4525_Reset (envy24_devc * devc, int nCodecIdx)
+{
+  unsigned char bCodecMask = 0;
+  if (nCodecIdx == -1)
+    bCodecMask = 0x0F;
+  else
+    bCodecMask = 0x01 << (nCodecIdx);
+  envy24_write_cci (devc, 0x20, 0x03);	/* Default value */
+
+  if (!write_ewx2496_codec (devc, AK4525_REG_RESET, 0x00))	/* DACs,ADCs -> reset */
+    {
+      cmn_err (CE_CONT, "REG_RESET failed\n");
+      return 0;
+    }
+
+  if (!write_ewx2496_codec (devc, AK4525_REG_FORMAT, 0x60))	/* IIS, 256 fsn, normal speed */
+    return 0;
+
+  if (!write_ewx2496_codec (devc, AK4525_REG_RESET, 0x03))	/* DACs,ADCs -> normal operation */
+    return 0;
+
+  if (!write_ewx2496_codec (devc, AK4525_REG_POWER, 0x07))	/* power on */
+    return 0;
+
+  if (!write_ewx2496_codec (devc, AK4525_REG_DEEMPHASIS, 0x19))
+    return 0;
+
+  if (!write_ewx2496_codec (devc, AK4525_REG_LEFT_INPUT, 0x7f))
+    return 0;
+
+  if (!write_ewx2496_codec (devc, AK4525_REG_RIGHT_INPUT, 0x7f))
+    return 0;
+
+  if (!write_ewx2496_codec (devc, AK4525_REG_LEFT_OUTPUT, 0x7f))
+    return 0;
+
+  if (!write_ewx2496_codec (devc, AK4525_REG_RIGHT_OUTPUT, 0x7f))
+    return 0;
+
+  return 1;
+}
+
+static void
+ews88_init_codecs (envy24_devc * devc)
+{
+  if (!HW_AK4525_Reset (devc, -1))
+    cmn_err (CE_CONT, "Envy24: EWS88MT reset failed\n");;
+}
+
+static void
+ewx2496_init_codecs (envy24_devc * devc)
+{
+  if (!ewx2496_AK4525_Reset (devc, -1))
+    cmn_err (CE_CONT, "Envy24: EWS88MT reset failed\n");;
+}
+
+static int
+envy24_set_akm (int dev, int ctrl, unsigned int cmd, int value)
+{
+  envy24_devc *devc = mixer_devs[dev]->devc;
+  int codec, level, i;
+  static unsigned char levels[] = { 0x7f, 0x8c, 0x98 };
+
+  if (ctrl >= 0xff)
+    return OSS_EINVAL;
+
+  if (cmd == SNDCTL_MIX_READ)
+    {
+      if (envy24_gain_sliders)
+	return devc->akm_gains[ctrl];
+      return devc->akm_gains[ctrl];
+    }
+  else if (cmd == SNDCTL_MIX_WRITE)
+    {
+
+      if (envy24_gain_sliders)
+	level = value & 0xff;
+      else
+	{
+	  if (value > 2)
+	    return OSS_EINVAL;
+	  level = levels[value];
+	}
+
+      codec = ctrl & 0xf0;
+
+      for (i = 0; i < 4; i++)
+	{
+	  if (!(ctrl & (1 << i)))
+	    continue;
+
+	  write_codec (devc, codec, 4 + i, level);
+	}
+      return devc->akm_gains[ctrl] = value;
+    }
+  return OSS_EINVAL;
+}
+
+static int
+envy24_set_ap (int dev, int ctrl, unsigned int cmd, int value)
+{
+  envy24_devc *devc = mixer_devs[dev]->devc;
+  int level;
+  static unsigned char levels[] = { 0x60, 0x6f, 0x7f };
+
+  if (ctrl >= 0xff)
+    return OSS_EINVAL;
+
+  if (cmd == SNDCTL_MIX_READ)
+    {
+      if (envy24_gain_sliders)
+	return devc->akm_gains[ctrl];
+      return devc->akm_gains[ctrl];
+    }
+  else if (cmd == SNDCTL_MIX_WRITE)
+    {
+
+      if (envy24_gain_sliders)
+	level = value & 0xff;
+      else
+	{
+	  if (value > 2)
+	    return OSS_EINVAL;
+	  level = levels[value];
+	}
+
+      write_ap_codec (devc, 4, level);
+      write_ap_codec (devc, 5, level);
+      return devc->akm_gains[ctrl] = value;
+    }
+  return OSS_EINVAL;
+}
+
+static int
+envy24_set_d410 (int dev, int ctrl, unsigned int cmd, int value)
+{
+  envy24_devc *devc = mixer_devs[dev]->devc;
+  int level, n;
+  static unsigned char levels[] = { 0x00, 0x00, 0x0c };
+
+  if (ctrl >= 8)
+    return OSS_EINVAL;
+
+  if (cmd == SNDCTL_MIX_READ)
+    {
+      if (envy24_gain_sliders)
+	return devc->akm_gains[ctrl];
+      return devc->akm_gains[ctrl];
+    }
+  else if (cmd == SNDCTL_MIX_WRITE)
+    {
+
+      if (envy24_gain_sliders)
+	level = 255 - value * 2;
+      else
+	{
+	  if (value > 2)
+	    return OSS_EINVAL;
+	  level = levels[value];
+	}
+
+      if (ctrl < 6)
+	n = ctrl + 2;
+      else
+	n = ctrl + 5;
+      write_ap_codec (devc, n, level);
+      if (devc->skipdevs == 2)
+	write_ap_codec (devc, n + 1, level);
+      return devc->akm_gains[ctrl] = value;
+    }
+  return OSS_EINVAL;
+}
+
+static unsigned char
+write_ewx2496_codec (envy24_devc * devc,
+		     unsigned char bRegIdx, unsigned char bRegData);
+
+static int
+envy24_set_ewx2496 (int dev, int ctrl, unsigned int cmd, int value)
+{
+  envy24_devc *devc = mixer_devs[dev]->devc;
+  int level;
+  static unsigned char levels[] = { 0x60, 0x6f, 0x7f };
+
+  if (ctrl >= 0xff)
+    return OSS_EINVAL;
+
+  if (cmd == SNDCTL_MIX_READ)
+    {
+      if (envy24_gain_sliders)
+	return devc->akm_gains[ctrl];
+      return devc->akm_gains[ctrl];
+    }
+  else if (cmd == SNDCTL_MIX_WRITE)
+    {
+
+      if (envy24_gain_sliders)
+	level = value & 0xff;
+      else
+	{
+	  if (value > 2)
+	    return OSS_EINVAL;
+	  level = levels[value];
+	}
+
+      write_ewx2496_codec (devc, 6, level);
+      write_ewx2496_codec (devc, 7, level);
+      return devc->akm_gains[ctrl] = value;
+    }
+  return OSS_EINVAL;
+}
+
+static unsigned char
+HW_AK4525_WriteRegister (envy24_devc * devc, unsigned char bCsMask,
+			 unsigned char bRegIdx, unsigned char bRegData);
+
+static int
+envy24_set_ews88 (int dev, int ctrl, unsigned int cmd, int value)
+{
+  envy24_devc *devc = mixer_devs[dev]->devc;
+  int codec, level, i;
+  static unsigned char levels[] = { 0x7f, 0x8c, 0x98 };
+
+  if (ctrl >= 0xff)
+    return OSS_EINVAL;
+
+  if (cmd == SNDCTL_MIX_READ)
+    {
+      if (envy24_gain_sliders)
+	return devc->akm_gains[ctrl];
+      return devc->akm_gains[ctrl];
+    }
+  else if (cmd == SNDCTL_MIX_WRITE)
+    {
+
+      if (envy24_gain_sliders)
+	level = value & 0xff;
+      else
+	{
+	  if (value > 2)
+	    return OSS_EINVAL;
+	  level = levels[value];
+	}
+
+      codec = ctrl & 0xf0;
+
+      for (i = 0; i < 4; i++)
+	{
+	  if (!(ctrl & (1 << i)))
+	    continue;
+
+	  if (!HW_AK4525_WriteRegister (devc, codec >> 4, 4 + i, level))
+	    return OSS_EIO;
+	}
+      return devc->akm_gains[ctrl] = value;
+    }
+  return OSS_EINVAL;
+}
+
+/*ARGSUSED*/ 
+static int
+create_akm_mixer (int dev, envy24_devc * devc, int root)
+{
+  int i, mask = devc->outportmask, group, err, skip, codec, ports;
+  int typ = MIXT_ENUM, range = 3;
+  char tmp[64];
+
+  if ((group = mixer_ext_create_group (dev, 0, "ENVY24_GAIN")) < 0)
+    return group;
+
+  skip = devc->skipdevs;
+  if (skip != 2)
+    skip = 1;
+
+  if (envy24_gain_sliders)
+    {
+      typ = MIXT_MONOSLIDER;
+      range = 144;
+
+      for (i = 0; i < 0xff; i++)
+	devc->akm_gains[i] = 0x7f;
+    }
+  else
+    for (i = 0; i < 0xff; i++)
+      devc->akm_gains[i] = 0;
+
+  for (i = 0; i < 8; i += skip)
+    {
+
+      if (!(mask & (1 << i)))
+	continue;		/* Not present */
+
+      if (devc->skipdevs == 2)
+	{
+	  if (i == 8)
+	    strcpy (tmp, "ENVY24_SPDOUT");
+	  else
+	    sprintf (tmp, "ENVY24_OUT%d/%d", i + 1, i + 2);
+
+	  codec = (i > 1) ? AKM_B : AKM_A;
+	  ports = 0x0c;		/* Both output ports */
+	  if ((err = mixer_ext_create_control (dev, group,
+					       codec | ports, envy24_set_akm,
+					       typ,
+					       tmp, range,
+					       MIXF_MAINVOL |
+					       MIXF_READABLE |
+					       MIXF_WRITEABLE)) < 0)
+	    return err;
+	}
+      else
+	{
+	  if (i == 8)
+	    strcpy (tmp, "ENVY24_SPDOUTL");
+	  else if (i == 9)
+	    strcpy (tmp, "ENVY24_SPDOUTR");
+	  else
+	    sprintf (tmp, "ENVY24_OUT%d", i + 1);
+
+	  codec = (i > 1) ? AKM_B : AKM_A;
+	  ports = (i & 1) ? 0x08 : 0x04;
+	  if ((err = mixer_ext_create_control (dev, group,
+					       codec | ports, envy24_set_akm,
+					       typ,
+					       tmp, range,
+					       MIXF_MAINVOL |
+					       MIXF_READABLE |
+					       MIXF_WRITEABLE)) < 0)
+	    return err;
+	}
+    }
+
+  mask = devc->inportmask;
+  for (i = 0; i < 8; i += skip)
+    {
+
+      if (!(mask & (1 << i)))
+	continue;		/* Not present */
+
+      if (devc->skipdevs == 2)
+	{
+	  if (i == 8)
+	    strcpy (tmp, "ENVY24_SPDIN");
+	  else
+	    sprintf (tmp, "ENVY24_IN%d/%d", i + 1, i + 2);
+
+	  codec = (i > 1) ? AKM_B : AKM_A;
+	  ports = 0x03;		/* Both output ports */
+	  if ((err = mixer_ext_create_control (dev, group,
+					       codec | ports, envy24_set_akm,
+					       typ,
+					       tmp, range,
+					       MIXF_RECVOL |
+					       MIXF_READABLE |
+					       MIXF_WRITEABLE)) < 0)
+	    return err;
+	}
+      else
+	{
+	  if (i == 8)
+	    strcpy (tmp, "ENVY24_SPDINL");
+	  else if (i == 9)
+	    strcpy (tmp, "ENVY24_SPDINR");
+	  else
+	    sprintf (tmp, "ENVY24_IN%d", i + 1);
+
+	  codec = (i > 1) ? AKM_B : AKM_A;
+	  ports = (i & 1) ? 0x02 : 0x01;
+	  if ((err = mixer_ext_create_control (dev, group,
+					       codec | ports, envy24_set_akm,
+					       typ,
+					       tmp, range,
+					       MIXF_RECVOL |
+					       MIXF_READABLE |
+					       MIXF_WRITEABLE)) < 0)
+	    return err;
+	}
+    }
+
+  return 0;
+}
+
+/*ARGSUSED*/ 
+static int
+create_ap_mixer (int dev, envy24_devc * devc, int root)
+{
+  int i, mask = devc->outportmask, group, err, skip, codec, ports;
+  int typ = MIXT_ENUM, range = 3;
+  char tmp[64];
+
+  if ((group = mixer_ext_create_group (dev, 0, "ENVY24_GAIN")) < 0)
+    return group;
+
+  skip = devc->skipdevs;
+  if (skip != 2)
+    skip = 1;
+
+  if (envy24_gain_sliders)
+    {
+      typ = MIXT_MONOSLIDER;
+      range = 164;
+
+      for (i = 0; i < 0xff; i++)
+	devc->akm_gains[i] = 0x7f;
+    }
+  else
+    for (i = 0; i < 0xff; i++)
+      devc->akm_gains[i] = 0;
+
+  for (i = 0; i < 8; i += skip)
+    {
+
+      if (!(mask & (1 << i)))
+	continue;		/* Not present */
+
+      if (devc->skipdevs == 2)
+	{
+	  if (i == 8)
+	    strcpy (tmp, "ENVY24_SPDOUT");
+	  else
+	    sprintf (tmp, "ENVY24_OUT%d/%d", i + 1, i + 2);
+
+	  codec = (i > 1) ? AKM_B : AKM_A;
+	  ports = 0x0c;		/* Both output ports */
+	  if ((err = mixer_ext_create_control (dev, group,
+					       codec | ports, envy24_set_ap,
+					       typ,
+					       tmp, range,
+					       MIXF_MAINVOL |
+					       MIXF_READABLE |
+					       MIXF_WRITEABLE)) < 0)
+	    return err;
+	}
+      else
+	{
+	  if (i == 8)
+	    strcpy (tmp, "ENVY24_SPDOUTL");
+	  else if (i == 9)
+	    strcpy (tmp, "ENVY24_SPDOUTR");
+	  else
+	    sprintf (tmp, "ENVY24_OUT%d", i + 1);
+
+	  codec = (i > 1) ? AKM_B : AKM_A;
+	  ports = (i & 1) ? 0x08 : 0x04;
+	  if ((err = mixer_ext_create_control (dev, group,
+					       codec | ports, envy24_set_ap,
+					       typ,
+					       tmp, range,
+					       MIXF_MAINVOL |
+					       MIXF_READABLE |
+					       MIXF_WRITEABLE)) < 0)
+	    return err;
+	}
+    }
+
+  return 0;
+}
+
+/*ARGSUSED*/ 
+static int
+create_d410_mixer (int dev, envy24_devc * devc, int root)
+{
+  int i, mask = devc->outportmask, group, err, skip;
+  int typ = MIXT_ENUM, range = 3;
+  int enum_mask = 0xffffff;
+  char tmp[64];
+
+  if ((group = mixer_ext_create_group (dev, 0, "ENVY24_GAIN")) < 0)
+    return group;
+
+  skip = devc->skipdevs;
+  if (skip != 2)
+    skip = 1;
+
+  if (envy24_gain_sliders)
+    {
+      typ = MIXT_MONOSLIDER;
+      range = 127;
+
+      for (i = 0; i < 0xff; i++)
+	devc->akm_gains[i] = 127;
+    }
+  else
+    {
+      for (i = 0; i < 0xff; i++)
+	devc->akm_gains[i] = 1;
+      enum_mask = 0x6;
+    }
+
+  for (i = 0; i < 8; i += skip)
+    {
+
+      if (!(mask & (1 << i)))
+	continue;		/* Not present */
+
+      if (devc->skipdevs == 2)
+	{
+	  if (i == 8)
+	    strcpy (tmp, "ENVY24_SPDOUT");
+	  else
+	    sprintf (tmp, "ENVY24_OUT%d/%d", i + 1, i + 2);
+
+	  if ((err = mixer_ext_create_control (dev, group,
+					       i, envy24_set_d410,
+					       typ,
+					       tmp, range,
+					       MIXF_MAINVOL |
+					       MIXF_READABLE |
+					       MIXF_WRITEABLE)) < 0)
+	    return err;
+	}
+      else
+	{
+	  if (i == 8)
+	    strcpy (tmp, "ENVY24_SPDOUTL");
+	  else if (i == 9)
+	    strcpy (tmp, "ENVY24_SPDOUTR");
+	  else
+	    sprintf (tmp, "ENVY24_OUT%d", i + 1);
+
+	  if ((err = mixer_ext_create_control (dev, group,
+					       i, envy24_set_d410,
+					       typ,
+					       tmp, range,
+					       MIXF_MAINVOL |
+					       MIXF_READABLE |
+					       MIXF_WRITEABLE)) < 0)
+	    return err;
+	}
+      envy24_set_enum_mask (dev, err, enum_mask);
+    }
+
+  return 0;
+}
+
+/*ARGSUSED*/ 
+static int
+create_ewx2496_mixer (int dev, envy24_devc * devc, int root)
+{
+  int i, mask = devc->outportmask, group, err, skip, codec, ports;
+  int typ = MIXT_ENUM, range = 3;
+  char tmp[64];
+
+  if ((group = mixer_ext_create_group (dev, 0, "ENVY24_GAIN")) < 0)
+    return group;
+
+  skip = devc->skipdevs;
+  if (skip != 2)
+    skip = 1;
+
+  if (envy24_gain_sliders)
+    {
+      typ = MIXT_MONOSLIDER;
+      range = 164;
+
+      for (i = 0; i < 0xff; i++)
+	devc->akm_gains[i] = 0x7f;
+    }
+  else
+    for (i = 0; i < 0xff; i++)
+      devc->akm_gains[i] = 0;
+
+  for (i = 0; i < 8; i += skip)
+    {
+
+      if (!(mask & (1 << i)))
+	continue;		/* Not present */
+
+      if (devc->skipdevs == 2)
+	{
+	  if (i == 8)
+	    strcpy (tmp, "ENVY24_SPDOUT");
+	  else
+	    sprintf (tmp, "ENVY24_OUT%d/%d", i + 1, i + 2);
+
+	  codec = (i > 1) ? AKM_B : AKM_A;
+	  ports = 0x0c;		/* Both output ports */
+	  if ((err = mixer_ext_create_control (dev, group,
+					       codec | ports,
+					       envy24_set_ewx2496, typ, tmp,
+					       range,
+					       MIXF_MAINVOL |
+					       MIXF_READABLE |
+					       MIXF_WRITEABLE)) < 0)
+	    return err;
+	}
+      else
+	{
+	  if (i == 8)
+	    strcpy (tmp, "ENVY24_SPDOUTL");
+	  else if (i == 9)
+	    strcpy (tmp, "ENVY24_SPDOUTR");
+	  else
+	    sprintf (tmp, "ENVY24_OUT%d", i + 1);
+
+	  codec = (i > 1) ? AKM_B : AKM_A;
+	  ports = (i & 1) ? 0x08 : 0x04;
+	  if ((err = mixer_ext_create_control (dev, group,
+					       codec | ports,
+					       envy24_set_ewx2496, typ, tmp,
+					       range,
+					       MIXF_MAINVOL |
+					       MIXF_READABLE |
+					       MIXF_WRITEABLE)) < 0)
+	    return err;
+	}
+    }
+
+  return 0;
+}
+
+/*ARGSUSED*/ 
+static int
+create_ews88_mixer (int dev, envy24_devc * devc, int root)
+{
+  int i, mask = devc->outportmask, group, err, skip, codec, ports;
+  int typ = MIXT_ENUM, range = 3;
+  char tmp[64];
+
+  if ((group = mixer_ext_create_group (dev, 0, "ENVY24_GAIN")) < 0)
+    return group;
+
+  skip = devc->skipdevs;
+  if (skip != 2)
+    skip = 1;
+
+  if (envy24_gain_sliders)
+    {
+      typ = MIXT_MONOSLIDER;
+      range = 164;
+
+      for (i = 0; i < 0xff; i++)
+	devc->akm_gains[i] = 0x7f;
+    }
+  else
+    for (i = 0; i < 0xff; i++)
+      devc->akm_gains[i] = 0;
+
+  for (i = 0; i < 8; i += skip)
+    {
+
+      if (!(mask & (1 << i)))
+	continue;		/* Not present */
+
+      if (devc->skipdevs == 2)
+	{
+	  if (i == 8)
+	    strcpy (tmp, "ENVY24_SPDOUT");
+	  else
+	    sprintf (tmp, "ENVY24_OUT%d/%d", i + 1, i + 2);
+
+	  codec = 0x10 << (i / 2);
+	  ports = 0x0c;		/* Both output ports */
+	  if ((err = mixer_ext_create_control (dev, group,
+					       codec | ports,
+					       envy24_set_ews88, typ, tmp,
+					       range,
+					       MIXF_MAINVOL |
+					       MIXF_READABLE |
+					       MIXF_WRITEABLE)) < 0)
+	    return err;
+	}
+      else
+	{
+	  if (i == 8)
+	    strcpy (tmp, "ENVY24_SPDOUTL");
+	  else if (i == 9)
+	    strcpy (tmp, "ENVY24_SPDOUTR");
+	  else
+	    sprintf (tmp, "ENVY24_OUT%d", i + 1);
+
+	  codec = 0x10 << (i / 2);
+	  ports = (i & 1) ? 0x08 : 0x04;
+	  if ((err = mixer_ext_create_control (dev, group,
+					       codec | ports,
+					       envy24_set_ews88, typ, tmp,
+					       range,
+					       MIXF_MAINVOL |
+					       MIXF_READABLE |
+					       MIXF_WRITEABLE)) < 0)
+	    return err;
+	}
+    }
+
+  mask = devc->inportmask;
+  for (i = 0; i < 8; i += skip)
+    {
+
+      if (!(mask & (1 << i)))
+	continue;		/* Not present */
+
+      if (devc->skipdevs == 2)
+	{
+	  if (i == 8)
+	    strcpy (tmp, "ENVY24_SPDIN");
+	  else
+	    sprintf (tmp, "ENVY24_IN%d/%d", i + 1, i + 2);
+
+	  codec = 0x10 << (i / 2);
+	  ports = 0x03;		/* Both output ports */
+	  if ((err = mixer_ext_create_control (dev, group,
+					       codec | ports,
+					       envy24_set_ews88, typ, tmp,
+					       range,
+					       MIXF_RECVOL |
+					       MIXF_READABLE |
+					       MIXF_WRITEABLE)) < 0)
+	    return err;
+	}
+      else
+	{
+	  if (i == 8)
+	    strcpy (tmp, "ENVY24_SPDINL");
+	  else if (i == 9)
+	    strcpy (tmp, "ENVY24_SPDINR");
+	  else
+	    sprintf (tmp, "ENVY24_IN%d", i + 1);
+
+	  codec = 0x10 << (i / 2);
+	  ports = (i & 1) ? 0x02 : 0x01;
+	  if ((err = mixer_ext_create_control (dev, group,
+					       codec | ports,
+					       envy24_set_ews88, typ, tmp,
+					       range,
+					       MIXF_RECVOL |
+					       MIXF_READABLE |
+					       MIXF_WRITEABLE)) < 0)
+	    return err;
+	}
+    }
+
+  return 0;
+}
+
+/*
+ * Hoontech DSP24 family
+ */
+
+
+typedef union
+{
+  struct
+  {
+    unsigned int data:5;
+    unsigned int clock:1;
+    unsigned int res0:2;
+  }
+  b;
+
+  unsigned int dwVal;
+}
+CLBYTE;
+
+#define HOONTECH_CLOCK	0x20
+
+static void
+hoontech_write_gpio (envy24_devc * devc, unsigned char data)
+{
+  envy24_write_cci (devc, 0x22, 0xff);	/* GPIO direction */
+  envy24_write_cci (devc, 0x21, 0xc0);	/* GPIO write mask */
+
+  envy24_write_cci (devc, 0x20, data | HOONTECH_CLOCK);	/* GPIO data */
+  envy24_write_cci (devc, 0x20, data & ~HOONTECH_CLOCK);	/* GPIO data */
+  envy24_write_cci (devc, 0x20, data | HOONTECH_CLOCK);	/* GPIO data */
+}
+
+static void
+hoontech_init (envy24_devc * devc)
+{
+  devc->adsp.b.box = 0;
+  devc->adsp.b.darear = 0;
+  devc->adsp.b.id0 = 0;
+  devc->adsp.b.clock0 = 1;
+  devc->adsp.b.res0 = 0x0;
+
+  devc->adsp.b.ch1 = 0x01;
+  devc->adsp.b.ch2 = 0x01;
+  devc->adsp.b.ch3 = 0x01;
+  devc->adsp.b.id1 = 1;
+  devc->adsp.b.clock1 = 1;
+  devc->adsp.b.res1 = 0x0;
+
+  devc->adsp.b.ch4 = 0x01;
+  devc->adsp.b.midiin = 0x01;
+  devc->adsp.b.midi1 = 0x0;
+  devc->adsp.b.id2 = 2;
+  devc->adsp.b.clock2 = 1;
+  devc->adsp.b.res2 = 0x0;
+
+  devc->adsp.b.midi2 = 0x0;
+  devc->adsp.b.mute = 0x0;
+  devc->adsp.b.insel = 0x1;
+  devc->adsp.b.id3 = 3;
+  devc->adsp.b.clock3 = 1;
+  devc->adsp.b.res3 = 0x0;
+
+  hoontech_write_gpio (devc, devc->adsp.w.b0);
+  hoontech_write_gpio (devc, devc->adsp.w.b1);
+  hoontech_write_gpio (devc, devc->adsp.w.b2);
+  hoontech_write_gpio (devc, devc->adsp.w.b3);
+}
+
+/**************************************************/
+
+static void
+default_card_init (envy24_devc * devc)
+{
+
+  if (devc->model_data->flags & MF_AKMCODEC)
+    {
+      write_codec (devc, AKM_A | AKM_B, 0, 0x07);
+      write_codec (devc, AKM_A | AKM_B, 1, 0x03);
+      write_codec (devc, AKM_A | AKM_B, 2, 0x60);
+      write_codec (devc, AKM_A | AKM_B, 3, 0x19);
+      write_codec (devc, AKM_A | AKM_B, 4, 0x7f);
+      write_codec (devc, AKM_A | AKM_B, 5, 0x7f);
+      write_codec (devc, AKM_A | AKM_B, 6, 0x7f);
+      write_codec (devc, AKM_A | AKM_B, 7, 0x7f);
+    }
+
+  if (devc->model_data->flags & MF_AP)
+    {				/* Init the AK4528 codec of Audiophile 2496 */
+      write_ap_codec (devc, 0, 0x07);
+      write_ap_codec (devc, 1, 0x00);
+      write_ap_codec (devc, 2, 0x60);
+      write_ap_codec (devc, 3, 0x0d);
+      write_ap_codec (devc, 4, 0x7f);
+      write_ap_codec (devc, 1, 0x03);
+      write_ap_codec (devc, 5, 0x7f);
+    }
+
+  if (devc->model_data->flags & MF_D410)
+    {				/* Init the AK4529 codec of Delta 410 */
+      OUTB (devc->osdev,
+	    INB (devc->osdev, devc->mt_base + 0x02) & ~0x04,
+	    devc->mt_base + 0x02);
+
+      write_ap_codec (devc, 0x00, 0x0c);
+      write_ap_codec (devc, 0x01, 0x02);
+      write_ap_codec (devc, 0x02, 0x00);
+      write_ap_codec (devc, 0x03, 0x00);
+      write_ap_codec (devc, 0x04, 0x00);
+      write_ap_codec (devc, 0x05, 0x00);
+      write_ap_codec (devc, 0x06, 0x00);
+      write_ap_codec (devc, 0x07, 0x00);
+      write_ap_codec (devc, 0x0b, 0x00);
+      write_ap_codec (devc, 0x0c, 0x00);
+      write_ap_codec (devc, 0x08, 0x15);
+      write_ap_codec (devc, 0x0a, 0x3f);
+    }
+
+  if (devc->model_data->flags & MF_EWS88)
+    ews88_init_codecs (devc);
+
+  if (devc->model_data->flags & MF_EWX2496)
+    ewx2496_init_codecs (devc);
+
+  if (devc->model_data->flags & MF_HOONTECH)
+    hoontech_init (devc);
+}
+
+static int
+default_mix_init (envy24_devc * devc, int dev, int group)
+{
+  int err;
+
+  if (devc->model_data->flags & MF_AKMCODEC)
+    {
+      if ((err = create_akm_mixer (dev, devc, group)) < 0)
+	return err;
+    }
+  else if (devc->model_data->flags & MF_AP)
+    {
+      if ((err = create_ap_mixer (dev, devc, group)) < 0)
+	return err;
+    }
+  else if (devc->model_data->flags & MF_D410)
+    {
+      if ((err = create_d410_mixer (dev, devc, group)) < 0)
+	return err;
+    }
+  else if (devc->model_data->flags & MF_EWS88)
+    {
+      if ((err = create_ews88_mixer (dev, devc, group)) < 0)
+	return err;
+    }
+  else if (devc->model_data->flags & MF_EWX2496)
+    {
+      if ((err = create_ewx2496_mixer (dev, devc, group)) < 0)
+	return err;
+    }
+  return 0;
+}
+
+/*ARGSUSED*/ 
+int
+cs8427_spdif_ioctl (envy24_devc * devc, int dev, unsigned int cmd,
+		    ioctl_arg arg)
+{
+  oss_digital_control *ctrl = (oss_digital_control *) arg;
+
+  if (arg == NULL)
+    return OSS_EINVAL;
+
+  switch (cmd)
+    {
+    case SNDCTL_DSP_READCTL:
+      {
+	int i, rq;
+	unsigned char status;
+
+	rq = ctrl->valid;
+	memset (ctrl, 0, sizeof (*ctrl));
+
+	ctrl->caps = DIG_CBITIN_FULL | DIG_CBITOUT_FULL;
+
+	if (rq & VAL_CBITIN)
+	  {
+	    for (i = 0; i < 24; i++)
+	      ctrl->cbitin[i] = ReadCsByte (devc, i);
+	    ctrl->valid |= VAL_CBITIN;
+	  }
+
+	if (rq & VAL_CBITOUT)
+	  {
+	    for (i = 0; i < 24; i++)
+	      ctrl->cbitin[i] = devc->spdif_cbits[i];
+	    ctrl->valid |= VAL_CBITOUT;
+	  }
+
+
+	if (rq & VAL_ISTATUS)
+	  {
+	    ctrl->valid |= VAL_ISTATUS;
+	    status = read_cs8427_spdif_reg (devc, 15);
+	    if (status & 0x04)
+	      ctrl->in_data = IND_DATA;
+	    else
+	      ctrl->in_data = IND_AUDIO;
+
+	    status = read_cs8427_spdif_reg (devc, 16);
+	    if (status & 0x40)
+	      ctrl->in_errors |= INERR_QCODE_CRC;
+	    if (status & 0x20)
+	      ctrl->in_errors |= INERR_CRC;
+
+	    if (status & 0x10)
+	      ctrl->in_locked = LOCK_UNLOCKED;
+	    else
+	      ctrl->in_locked = LOCK_LOCKED;
+
+	    if (status & 0x08)
+	      ctrl->in_vbit = VBIT_ON;
+	    else
+	      ctrl->in_vbit = VBIT_OFF;
+
+	    if (status & 0x04)
+	      ctrl->in_quality = IN_QUAL_POOR;
+	    else
+	      ctrl->in_quality = IN_QUAL_GOOD;
+
+	    if (status & 0x02)
+	      ctrl->in_errors |= INERR_BIPHASE;
+
+	    if (status & 0x01)
+	      ctrl->in_errors |= INERR_PARITY;
+
+#if 1
+	    /* TODO: Better handling required */
+	    write_cs8427_spdif_reg (devc, 18, 0x00);
+#endif
+	  }
+      }
+      return 0;
+      break;
+
+    case SNDCTL_DSP_WRITECTL:
+      {
+	int i, rq;
+
+	rq = ctrl->valid;
+	memset (ctrl, 0, sizeof (*ctrl));
+
+	ctrl->caps = DIG_CBITOUT_FULL;
+
+	if (rq & VAL_CBITOUT)
+	  {
+	    for (i = 0; i < 24; i++)
+	      devc->spdif_cbits[i] = ctrl->cbitout[i];
+	    ctrl->valid |= VAL_CBITOUT;
+
+	    lock_cs8427_spdif (devc);
+	    for (i = 0; i < 24; i++)
+	      {
+		WriteCsByte (devc, i, devc->spdif_cbits[i]);
+	      }
+	    unlock_cs8427_spdif (devc);
+	  }
+      }
+      return 0;
+      break;
+
+    default:;
+    }
+  return OSS_EINVAL;
+}
+
+static int
+set_spdif_control (int dev, int ctrl, unsigned int cmd, int value)
+{
+  envy24_devc *devc = mixer_devs[dev]->devc;
+
+  if (cmd == SNDCTL_MIX_READ)
+    {
+      switch (ctrl)
+	{
+	case 1:
+	  return devc->spdif_pro_mode;
+	  break;
+	}
+
+      return OSS_EIO;
+    }
+
+  if (cmd == SNDCTL_MIX_WRITE)
+    {
+      switch (ctrl)
+	{
+	case 1:
+	  return devc->spdif_pro_mode = !!value;
+	  break;
+	}
+
+      return OSS_EIO;
+    }
+
+  return OSS_EIO;
+}
+
+/*ARGSUSED*/ 
+int
+cs8427_spdif_mixer_init (envy24_devc * devc, int dev, int group)
+{
+  int err;
+
+  if ((group = mixer_ext_create_group (dev, 0, "ENVY24_SPDIF")) < 0)
+    return group;
+
+  if ((err = mixer_ext_create_control (dev, group,
+				       1, set_spdif_control,
+				       MIXT_ENUM,
+				       "SPDIF_MODE", 2,
+				       MIXF_READABLE | MIXF_WRITEABLE)) < 0)
+    return err;
+
+  return 0;
+}
+
+static void
+set_ap_speed (envy24_devc * devc)
+{
+  unsigned char gpio, tmp;
+
+  tmp = devc->speedbits;
+  if (devc->syncsource != SYNC_INTERNAL)
+    {
+      tmp |= 0x10;		/* S/PDIF input clock select */
+      if (devc->model_data->flags & MF_WCLOCK)	/* Has world clock too */
+	{
+	  int cmd = envy24_read_cci (devc, 0x20);
+	  cmd |= 0x10;		/* S/PDIF */
+	  if (devc->syncsource == SYNC_WCLOCK)
+	    cmd &= ~0x10;	/* World clock */
+	  envy24_write_cci (devc, 0x20, cmd);
+	}
+    }
+  OUTB (devc->osdev, tmp, devc->mt_base + 0x01);
+
+  if (devc->speed > 48000)
+    {
+      write_ap_codec (devc, 0x01, 0x00);
+      gpio = envy24_read_cci (devc, 0x20);
+      gpio |= 0x01;		/* Turn DFS ON */
+      envy24_write_cci (devc, 0x20, gpio);
+      write_ap_codec (devc, 0x02, 0x65);
+      write_ap_codec (devc, 0x01, 0x03);
+    }
+  else
+    {
+      write_ap_codec (devc, 0x01, 0x00);
+      gpio = envy24_read_cci (devc, 0x20);
+      gpio &= ~0x01;		/* Turn DFS OFF */
+      envy24_write_cci (devc, 0x20, gpio);
+      write_ap_codec (devc, 0x02, 0x60);
+      write_ap_codec (devc, 0x01, 0x03);
+    }
+}
+
+envy24_auxdrv_t default_auxdrv = {
+  default_card_init,
+  default_mix_init,
+  NULL,
+  write_spdif
+};
+
+envy24_auxdrv_t ap2496_auxdrv = {
+  default_card_init,
+  default_mix_init,
+  init_cs8427_spdif,
+  write_cs8427_spdif,
+  cs8427_spdif_ioctl,
+  read_ap_spdif_reg,
+  write_ap_spdif_reg,
+  set_ap_speed,
+  NULL,
+  cs8427_spdif_mixer_init
+};
+
+envy24_auxdrv_t d410_auxdrv = {
+  default_card_init,
+  default_mix_init,
+  init_cs8427_spdif,
+  write_cs8427_spdif,
+  cs8427_spdif_ioctl,
+  read_ap_spdif_reg,
+  write_ap_spdif_reg,
+  NULL,
+  NULL,
+  cs8427_spdif_mixer_init
+};
+
+envy24_auxdrv_t ewx2496_auxdrv = {
+  default_card_init,
+  default_mix_init,
+  init_cs8427_spdif,
+  write_cs8427_spdif,
+  NULL,
+  read_ewx2496_spdif_reg,
+  write_ewx2496_spdif_reg,
+  NULL,
+  NULL,
+  cs8427_spdif_mixer_init
+};
diff --git a/kernel/drv/oss_envy24/envy24_direct.c b/kernel/drv/oss_envy24/envy24_direct.c
new file mode 100644
index 0000000..9448c6c
--- /dev/null
+++ b/kernel/drv/oss_envy24/envy24_direct.c
@@ -0,0 +1,415 @@
+/*
+ * Purpose: Direct 24 bit multich driver for Envy24.
+ *
+ * This driver implements the all inputs and all outputs audio devices for
+ * envy24. Unlike the ordinary driver this one doesn't use additional buffering.
+ */
+/*
+ *
+ * This file is part of Open Sound System.
+ *
+ * Copyright (C) 4Front Technologies 1996-2008.
+ *
+ * This this source file is released under GPL v2 license (no other versions).
+ * See the COPYING file included in the main directory of this source
+ * distribution for the license terms and conditions.
+ *
+ */
+
+#include "oss_config.h"
+#include "ac97.h"
+
+#ifdef USE_LICENSING
+#include "private/licensing/licensing.h"
+#endif
+
+#include "envy24.h"
+
+#define OUTCH_NAMES "CH1/2 CH3/4 CH5/6 CH7/8 digital"
+#define INCH_NAMES "CH1/2 CH3/4 CH5/6 CH7/8 digital monitor_mix"
+
+/*
+ * Audio routines
+ */
+extern int envy24_audio_set_rate (int dev, int arg);
+int envy24d_get_buffer_pointer (int dev, dmap_t * dmap, int direction);
+
+void
+envy24d_playintr (envy24_devc * devc)
+{
+  oss_audio_outputintr (devc->direct_portc_out.audio_dev, 0);
+}
+
+void
+envy24d_recintr (envy24_devc * devc)
+{
+  oss_audio_inputintr (devc->direct_portc_in.audio_dev, 0);
+}
+
+/*ARGSUSED*/ 
+static short
+envy24d_audio_set_channels (int dev, short arg)
+{
+  envy24d_portc *portc = audio_engines[dev]->portc;
+  return portc->channels;
+}
+
+/*ARGSUSED*/ 
+static unsigned int
+envy24d_audio_set_format (int dev, unsigned int arg)
+{
+  return AFMT_S32_LE;
+}
+
+/*ARGSUSED*/ 
+static int
+envy24d_audio_ioctl (int dev, unsigned int cmd, ioctl_arg arg)
+{
+  return OSS_EINVAL;
+}
+
+static void envy24d_audio_trigger (int dev, int state);
+
+static void
+envy24d_audio_reset (int dev)
+{
+  envy24d_audio_trigger (dev, 0);
+}
+
+/*ARGSUSED*/ 
+static int
+envy24d_audio_open (int dev, int mode, int open_flags)
+{
+  envy24_devc *devc = audio_engines[dev]->devc;
+  envy24d_portc *portc = audio_engines[dev]->portc;
+  oss_native_word flags;
+
+  if (!(mode & portc->direction))
+    return OSS_EINVAL;
+
+  MUTEX_ENTER_IRQDISABLE (devc->mutex, flags);
+
+  if (portc->open_mode != 0 || (devc->direct_audio_opened & mode))
+    {
+      MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+      return OSS_EBUSY;
+    }
+
+  if (mode == OPEN_WRITE && (devc->play_channel_mask != 0))
+    {
+      MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+      return OSS_EBUSY;
+    }
+
+  if (mode == OPEN_READ && (devc->rec_channel_mask != 0))
+    {
+      MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+      return OSS_EBUSY;
+    }
+
+  portc->open_mode = mode;
+  devc->direct_audio_opened |= mode;
+  MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+
+  return 0;
+}
+
+static void
+envy24d_audio_close (int dev, int mode)
+{
+  envy24_devc *devc = audio_engines[dev]->devc;
+  envy24d_portc *portc = audio_engines[dev]->portc;
+  oss_native_word flags;
+
+  MUTEX_ENTER_IRQDISABLE (devc->mutex, flags);
+  portc->open_mode = 0;
+  devc->direct_audio_opened &= ~mode;
+  MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+}
+
+/*ARGSUSED*/ 
+static void
+envy24d_audio_output_block (int dev, oss_native_word buf, int count,
+			    int fragsize, int intrflag)
+{
+}
+
+/*ARGSUSED*/ 
+static void
+envy24d_audio_start_input (int dev, oss_native_word buf, int count,
+			   int fragsize, int intrflag)
+{
+}
+
+static void
+envy24d_audio_trigger (int dev, int state)
+{
+  envy24_devc *devc = audio_engines[dev]->devc;
+  envy24d_portc *portc = audio_engines[dev]->portc;
+  int changed;
+  oss_native_word flags;
+
+  MUTEX_ENTER_IRQDISABLE (devc->mutex, flags);
+  changed = state ^ portc->trigger_bits;
+
+  if (portc->direction == OPEN_WRITE && (changed & PCM_ENABLE_OUTPUT))
+    {
+      if (state & PCM_ENABLE_OUTPUT)
+	{
+#ifdef DO_TIMINGS
+	  oss_do_timing ("Envy24d: Trigger start output");
+#endif
+	  portc->trigger_bits = state;
+	  envy24_launch_play_engine (devc);
+	}
+      else
+	{
+#ifdef DO_TIMINGS
+	  oss_do_timing ("Envy24d: Trigger stop output");
+#endif
+	  portc->trigger_bits = state;
+	  envy24_stop_playback (devc);
+	}
+    }
+
+  if (portc->direction == OPEN_READ && (changed & PCM_ENABLE_INPUT))
+    {
+      if (state & PCM_ENABLE_INPUT)
+	{
+#ifdef DO_TIMINGS
+	  oss_do_timing ("Envy24d: Trigger start input");
+#endif
+	  portc->trigger_bits = state;
+	  envy24_launch_recording (devc);
+	}
+      else
+	{
+#ifdef DO_TIMINGS
+	  oss_do_timing ("Envy24d: Trigger stop input");
+#endif
+	  portc->trigger_bits = state;
+	  envy24_stop_recording (devc);
+	}
+    }
+  MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+}
+
+/*ARGSUSED*/ 
+static int
+envy24d_audio_prepare_for_input (int dev, int bsize, int bcount)
+{
+  envy24_devc *devc = audio_engines[dev]->devc;
+  envy24_start_recording (devc);
+  return 0;
+}
+
+/*ARGSUSED*/ 
+static int
+envy24d_audio_prepare_for_output (int dev, int bsize, int bcount)
+{
+  envy24_devc *devc = audio_engines[dev]->devc;
+
+  envy24_prepare_play_engine (devc);
+  return 0;
+}
+
+static int
+envy24d_alloc_buffer (int dev, dmap_t * dmap, int direction)
+{
+  envy24_devc *devc = audio_engines[dev]->devc;
+
+  if (direction == OPEN_WRITE)
+    {
+      if (devc->playbuf == NULL)
+	{
+	  cmn_err (CE_CONT, "Envy24: No playback DMA buffer available\n");
+	  return OSS_ENOSPC;
+	}
+
+      dmap->dmabuf = devc->playbuf;
+      dmap->buffsize = devc->playbuffsize;
+      dmap->dmabuf_phys = devc->playbuf_phys;
+      return 0;
+    }
+
+  if (direction == OPEN_READ)
+    {
+      if (devc->recbuf == NULL)
+	{
+	  cmn_err (CE_CONT, "Envy24: No recording DMA buffer available\n");
+	  return OSS_ENOSPC;
+	}
+
+      dmap->dmabuf = devc->recbuf;
+      dmap->buffsize = devc->recbuffsize;
+      dmap->dmabuf_phys = devc->recbuf_phys;
+      return 0;
+    }
+
+  return OSS_EIO;
+}
+
+/*ARGSUSED*/ 
+static int
+envy24d_free_buffer (int dev, dmap_t * dmap, int direction)
+{
+  dmap->dmabuf = NULL;
+  dmap->dmabuf_phys = 0;
+  dmap->buffsize = 0;
+  return 0;
+}
+
+int
+envy24d_get_buffer_pointer (int dev, dmap_t * dmap, int direction)
+{
+
+  envy24_devc *devc = audio_engines[dev]->devc;
+  int pos;
+
+  if (direction == PCM_ENABLE_OUTPUT)
+    {
+      pos = INW (devc->osdev, devc->mt_base + 0x14);
+      pos = (pos + 1) * 4;
+      pos = dmap->bytes_in_use - pos;
+
+      return pos;
+    }
+
+  if (direction == PCM_ENABLE_INPUT)
+    {
+      pos = INW (devc->osdev, devc->mt_base + 0x24);
+      pos = (pos + 1) * 4;
+      pos = dmap->bytes_in_use - pos;
+
+      return pos;
+    }
+
+  return OSS_EIO;
+}
+
+/*ARGSUSED*/ 
+static int
+envy24d_check_input (int dev)
+{
+  cmn_err (CE_WARN, "Envy24d: Input timed out.\n");
+  return OSS_EIO;
+}
+
+/*ARGSUSED*/ 
+static int
+envy24d_check_output (int dev)
+{
+  cmn_err (CE_WARN, "Envy24d: Output timed out (%d)\n", GET_JIFFIES ());
+  return OSS_EIO;
+}
+
+static const audiodrv_t envy24d_audio_driver = {
+  envy24d_audio_open,
+  envy24d_audio_close,
+  envy24d_audio_output_block,
+  envy24d_audio_start_input,
+  envy24d_audio_ioctl,
+  envy24d_audio_prepare_for_input,
+  envy24d_audio_prepare_for_output,
+  envy24d_audio_reset,
+  NULL,
+  NULL,
+  NULL,
+  NULL,
+  envy24d_audio_trigger,
+  envy24_audio_set_rate,
+  envy24d_audio_set_format,
+  envy24d_audio_set_channels,
+  NULL,
+  NULL,
+  envy24d_check_input,
+  envy24d_check_output,
+  envy24d_alloc_buffer,
+  envy24d_free_buffer,
+  NULL,
+  NULL,
+  envy24d_get_buffer_pointer
+};
+
+void
+envy24d_install (envy24_devc * devc)
+{
+
+  int adev, out_dev, in_dev;
+  char tmpname[128];
+  envy24d_portc *portc;
+
+  /*
+   * Output device
+   */
+  sprintf (tmpname, "%s (all outputs)", devc->model_data->product);
+
+  if ((out_dev = adev = oss_install_audiodev_with_devname (OSS_AUDIO_DRIVER_VERSION,
+				    devc->osdev,
+				    devc->osdev,
+				    tmpname,
+				    &envy24d_audio_driver,
+				    sizeof (audiodrv_t),
+				    ADEV_NOVIRTUAL | ADEV_NOINPUT | ADEV_COLD
+				    | ADEV_SPECIAL | ADEV_32BITONLY,
+				    AFMT_S32_LE, devc, -1,
+				    "10ch_out")) >= 0)
+    {
+      portc = &devc->direct_portc_out;
+      audio_engines[adev]->portc = portc;
+      audio_engines[adev]->rate_source = devc->first_dev;
+      audio_engines[adev]->caps |= DSP_CH_MULTI;
+      audio_engines[adev]->min_channels = 10;
+      audio_engines[adev]->max_channels = 10;
+      audio_engines[adev]->outch_names = OUTCH_NAMES;
+      audio_engines[adev]->min_block = devc->hw_pfragsize;
+      audio_engines[adev]->max_block = devc->hw_pfragsize;
+      audio_engines[adev]->min_rate = 8000;
+      audio_engines[adev]->max_rate = 96000;
+
+      audio_engines[adev]->mixer_dev = devc->mixer_dev;
+      devc->direct_audio_opened = 0;
+      portc->open_mode = 0;
+      portc->audio_dev = adev;
+      portc->channels = 10;
+      portc->direction = OPEN_WRITE;
+      audio_engines[adev]->port_number = 0;	/* First output channel */
+    }
+
+  /*
+   * Input device
+   */
+  sprintf (tmpname, "%s (all inputs)", devc->model_data->product);
+
+  if ((adev = in_dev = oss_install_audiodev_with_devname (OSS_AUDIO_DRIVER_VERSION,
+				    devc->osdev,
+				    devc->osdev,
+				    tmpname,
+				    &envy24d_audio_driver,
+				    sizeof (audiodrv_t),
+				    ADEV_NOVIRTUAL | ADEV_NOOUTPUT | ADEV_COLD
+				    | ADEV_SPECIAL | ADEV_32BITONLY,
+				    AFMT_S32_LE, devc, -1,
+				    "12ch_in")) >= 0)
+    {
+      portc = &devc->direct_portc_in;
+      audio_engines[adev]->portc = portc;
+      audio_engines[adev]->rate_source = devc->first_dev;
+      audio_engines[adev]->caps |= DSP_CH_MULTI;
+      audio_engines[adev]->min_channels = 12;
+      audio_engines[adev]->max_channels = 12;
+      audio_engines[adev]->inch_names = INCH_NAMES;
+      audio_engines[adev]->min_rate = 8000;
+      audio_engines[adev]->max_rate = 96000;
+
+      audio_engines[adev]->mixer_dev = devc->mixer_dev;
+      devc->direct_audio_opened = 0;
+      portc->open_mode = 0;
+      portc->audio_dev = adev;
+      audio_engines[adev]->min_block = devc->hw_pfragsize;
+      audio_engines[adev]->max_block = devc->hw_pfragsize;
+      portc->channels = 12;
+      portc->direction = OPEN_READ;
+      audio_engines[adev]->port_number = 10;	/* First input channel */
+    }
+}
diff --git a/kernel/drv/oss_envy24/envy24_ews88d.c b/kernel/drv/oss_envy24/envy24_ews88d.c
new file mode 100644
index 0000000..c68be60
--- /dev/null
+++ b/kernel/drv/oss_envy24/envy24_ews88d.c
@@ -0,0 +1,377 @@
+/*
+ * Purpose: Card specific routines for Terratec EWS88D.
+ */
+/*
+ *
+ * This file is part of Open Sound System.
+ *
+ * Copyright (C) 4Front Technologies 1996-2008.
+ *
+ * This this source file is released under GPL v2 license (no other versions).
+ * See the COPYING file included in the main directory of this source
+ * distribution for the license terms and conditions.
+ *
+ */
+
+#include "oss_config.h"
+#include "ac97.h"
+#include "envy24.h"
+
+#if 0
+# define PRT_STATUS(v) outb(v&0xff, 0x378)
+#else
+# define PRT_STATUS(v)
+#endif
+
+/* PCF8575 pin assignment  (default 0xffff) */
+#define PCF_SPDIN_SELECT	0x0001	/* 0=optical 1=coax */
+#define PCF_OPTOUT		0x0002	/* 0=SPDIF 1=ADAT */
+#define PCF_CLOCKSRC		0x0004	/* 0=ADAT 1=SPDIF */
+#define PCF_ADATEN		0x0008	/* 0=ADAT disabled 1=ADAT enabled */
+#define PCF_ADATLOOP_		0x0010	/* 0=ADAT in->out loop, 1=no loop */
+#define PCF_CS8414_ERF_		0x0020	/* Inverted CS8414 ERF */
+#define PCF_SPDIF_ERR		0x0040	/* OR'ed from CS8414 E0..E2 */
+#define PCF_ADAT_ERROR		0x0080	/* ADAT error input */
+
+extern int envy24_gain_sliders;
+extern int envy24_virtualout;
+extern int envy24_zerolatency;	/* Testing in progress */
+/*
+ * Terratec stuff
+ */
+
+/*=============================================================================
+  Function    : IIC_GetSDA
+-------------------------------------------------------------------------------
+  Description : 
+  Returns     : unsigned char  -> 
+  Parameters  : unsigned long dwPortAddr -> 
+-------------------------------------------------------------------------------
+  Notes       : 
+=============================================================================*/
+static __inline__ unsigned char
+IIC_GetSDA (envy24_devc * devc, unsigned long dwPortAddr)
+{
+
+  unsigned char bReg, bSDA;
+
+  /* FMB TEST: RW line */
+  /* set write mask */
+  bReg = ~(0x08);		/* writeable */
+  envy24_write_cci (devc, 0x21, bReg);
+
+  /* set RW line LOW */
+  bReg = 0;			/* writeable */
+  envy24_write_cci (devc, 0x20, bReg);
+
+  /* Set direction: SDA to input and SCL to output */
+  bReg = envy24_read_cci (devc, 0x22);
+  bReg |= 0x20;			/* SCL output = 1 */
+  bReg &= ~0x10;		/* SDA input  = 0 */
+  envy24_write_cci (devc, 0x22, bReg);
+
+  /* Get SDA line state */
+  bSDA = envy24_read_cci (devc, 0x20);
+
+  /* set RW line HIGH */
+  bReg = 0x08;			/* writeable */
+  envy24_write_cci (devc, 0x20, bReg);
+
+  return 1;
+  /* return ((bSDA & 0x10) == 0x10); */
+
+}
+
+/*=============================================================================
+  Function    : IIC_SetIic
+-------------------------------------------------------------------------------
+  Description : 
+  Returns     : void  -> 
+  Parameters  : unsigned int dwPortAddr -> 
+              : unsigned char fSDA -> 
+              : unsigned char fSCL -> 
+-------------------------------------------------------------------------------
+  Notes       : 
+=============================================================================*/
+static __inline__ void
+IIC_SetIic (envy24_devc * devc, unsigned int dwPortAddr, unsigned char fSDA,
+	    unsigned char fSCL)
+{
+  unsigned char bReg;
+
+  /* Set direction: SDA and SCL to output */
+  bReg = envy24_read_cci (devc, 0x22);
+  bReg |= (0x20 | 0x10);	/* 1 -> output */
+  envy24_write_cci (devc, 0x22, bReg);
+
+  /* set write mask */
+  bReg = ~(0x20 | 0x10);	/* writeable */
+  envy24_write_cci (devc, 0x21, bReg);
+
+  /* Set line state */
+  /* FMB TEST: RW line */
+  bReg = 0x08;
+/*	bReg = 0; */
+  if (fSDA)
+    bReg += 0x10;
+  if (fSCL)
+    bReg += 0x20;
+  envy24_write_cci (devc, 0x20, bReg);
+
+}
+
+/*=============================================================================
+  Function    : IIC_Start
+-------------------------------------------------------------------------------
+  Description : 
+  Returns     : void  -> 
+  Parameters  : unsigned int dwPortAddr -> 
+-------------------------------------------------------------------------------
+  Notes       : 
+=============================================================================*/
+static __inline__ void
+IIC_Start (envy24_devc * devc, unsigned int dwPortAddr)
+{
+  /* falling edge of SDA while SCL is HIGH */
+  IIC_SetIic (devc, dwPortAddr, 1, 1);
+  IIC_SetIic (devc, dwPortAddr, 0, 1);
+}
+
+/*=============================================================================
+  Function    : IIC_Stop  
+-------------------------------------------------------------------------------
+  Description : 
+  Returns     : void -> 
+  Parameters  : unsigned int dwPortAddr -> 
+-------------------------------------------------------------------------------
+  Notes       : 
+=============================================================================*/
+static __inline__ void
+IIC_Stop (envy24_devc * devc, unsigned int dwPortAddr)
+{
+  /* rising edge of SDA while SCL is HIGH */
+  IIC_SetIic (devc, dwPortAddr, 0, 1);
+  IIC_SetIic (devc, dwPortAddr, 1, 1);
+}
+
+
+/*=============================================================================
+  Function    : IIC_SendByte
+-------------------------------------------------------------------------------
+  Description : 
+  Returns     : unsigned char -> 
+  Parameters  : unsigned int dwPortAddr -> 
+              : unsigned char bByte -> 
+-------------------------------------------------------------------------------
+  Notes       : 
+=============================================================================*/
+/*__inline  */
+static unsigned char
+IIC_SendByte (envy24_devc * devc, unsigned int dwPortAddr,
+	      unsigned char bByte)
+{
+  unsigned char bDataBit, bAck;
+  int i;
+
+  for (i = 7; i >= 0; i--)	/* send byte (MSB first) */
+    {
+      bDataBit = (bByte >> i) & 0x01;
+
+      IIC_SetIic (devc, dwPortAddr, bDataBit, 0);
+      IIC_SetIic (devc, dwPortAddr, bDataBit, 1);
+    }				/* end for i */
+
+  IIC_SetIic (devc, dwPortAddr, 1, 0);
+
+  /* Get acknowledge */
+  IIC_SetIic (devc, dwPortAddr, 1, 1);
+  bAck = IIC_GetSDA (devc, dwPortAddr);
+  /* FMB this is a start condition but never mind */
+  IIC_SetIic (devc, dwPortAddr, 0, 0);
+  return 1;
+  /* return (!bAck); *//* bAck = 0 --> success */
+}
+
+static unsigned char
+IIC_WriteWord (envy24_devc * devc, int dwPortAddr, unsigned char bIicAddress,
+	       unsigned short bByte)
+{
+  IIC_Start (devc, dwPortAddr);
+
+  /* send IIC address and data byte */
+  if (!IIC_SendByte (devc, dwPortAddr, bIicAddress))
+    {
+      cmn_err (CE_CONT, "IIC_SendByte 1 failed\n");
+      goto FAILED;
+    }
+  if (!IIC_SendByte (devc, dwPortAddr, bByte & 0xff))
+    {
+      cmn_err (CE_CONT, "IIC_SendByte 3 failed\n");
+      goto FAILED;
+    }
+  if (!IIC_SendByte (devc, dwPortAddr, (bByte >> 8) & 0xff))
+    {
+      cmn_err (CE_CONT, "IIC_SendByte 2 failed\n");
+      goto FAILED;
+    }
+
+  IIC_Stop (devc, dwPortAddr);
+  return 1;
+
+FAILED:
+  IIC_Stop (devc, dwPortAddr);
+  return 0;
+}
+
+static void
+ews88d_set_pcf8575 (envy24_devc * devc, unsigned short d)
+{
+  if (!IIC_WriteWord (devc, devc->ccs_base, 0x40, d))
+    {
+      cmn_err (CE_CONT, "IIC_WriteWord failed\n");
+    }
+  devc->gpio_tmp = d;
+}
+
+static void
+ews88d_card_init (envy24_devc * devc)
+{
+  ews88d_set_pcf8575 (devc, 0xffff);
+}
+
+static void
+set_ews88d_speed (envy24_devc * devc)
+{
+  int tmp;
+
+  tmp = devc->speedbits;
+
+  switch (devc->syncsource)
+    {
+    case SYNC_INTERNAL:
+      OUTB (devc->osdev, tmp, devc->mt_base + 0x01);
+      break;
+
+    case SYNC_SPDIF:
+      tmp |= 0x10;
+      OUTB (devc->osdev, tmp, devc->mt_base + 0x01);
+      devc->gpio_tmp &= ~PCF_CLOCKSRC;
+      ews88d_set_pcf8575 (devc, devc->gpio_tmp);
+      break;
+
+    case SYNC_WCLOCK:
+      tmp |= 0x10;
+      OUTB (devc->osdev, tmp, devc->mt_base + 0x01);
+      devc->gpio_tmp |= PCF_CLOCKSRC;
+      ews88d_set_pcf8575 (devc, devc->gpio_tmp);
+      break;
+    }
+
+  if (devc->speed > 48000)
+    {
+      devc->gpio_tmp &= ~PCF_ADATEN;
+      ews88d_set_pcf8575 (devc, devc->gpio_tmp);
+    }
+  else
+    {
+      devc->gpio_tmp |= PCF_ADATEN;
+      ews88d_set_pcf8575 (devc, devc->gpio_tmp);
+    }
+}
+
+static int
+ews88d_mixer_set (int dev, int ctrl, unsigned int cmd, int value)
+{
+  envy24_devc *devc = mixer_devs[dev]->devc;
+
+  if (cmd == SNDCTL_MIX_READ)
+    switch (ctrl)
+      {
+      case 1:
+	return !!(devc->gpio_tmp & PCF_SPDIN_SELECT);
+	break;
+
+      case 2:
+	return !!(devc->gpio_tmp & PCF_OPTOUT);
+	break;
+
+      case 3:
+	return !(devc->gpio_tmp & PCF_ADATLOOP_);
+	break;
+      }
+
+  if (cmd == SNDCTL_MIX_WRITE)
+    switch (ctrl)
+      {
+      case 1:
+	devc->gpio_tmp &= ~PCF_SPDIN_SELECT;
+	if (value)
+	  devc->gpio_tmp |= PCF_SPDIN_SELECT;
+	ews88d_set_pcf8575 (devc, devc->gpio_tmp);
+	return !!(devc->gpio_tmp & PCF_SPDIN_SELECT);
+	break;
+
+      case 2:
+	devc->gpio_tmp &= ~PCF_OPTOUT;
+	if (value)
+	  devc->gpio_tmp |= PCF_OPTOUT;
+	ews88d_set_pcf8575 (devc, devc->gpio_tmp);
+	return !!(devc->gpio_tmp & PCF_OPTOUT);
+	break;
+
+      case 3:
+	devc->gpio_tmp &= ~PCF_ADATLOOP_;
+	if (!value)
+	  devc->gpio_tmp |= PCF_ADATLOOP_;
+	ews88d_set_pcf8575 (devc, devc->gpio_tmp);
+	return !(devc->gpio_tmp & PCF_ADATLOOP_);
+	break;
+      }
+
+  return OSS_EINVAL;
+}
+
+static int
+ews88d_mix_init (envy24_devc * devc, int dev, int group)
+{
+  int err;
+
+  if ((group = mixer_ext_create_group (dev, 0, "ENVY24_EWS88D")) < 0)
+    return group;
+
+  if ((err = mixer_ext_create_control (dev, group,
+				       1, ews88d_mixer_set,
+				       MIXT_ENUM,
+				       "EWS88D_SPDIN", 2,
+				       MIXF_READABLE | MIXF_WRITEABLE)) < 0)
+    return err;
+
+  if ((err = mixer_ext_create_control (dev, group,
+				       2, ews88d_mixer_set,
+				       MIXT_ENUM,
+				       "EWS88D_OPTOUT", 2,
+				       MIXF_READABLE | MIXF_WRITEABLE)) < 0)
+    return err;
+
+  if ((err = mixer_ext_create_control (dev, group,
+				       3, ews88d_mixer_set,
+				       MIXT_ONOFF,
+				       "EWS88D_ADATLOOP", 2,
+				       MIXF_READABLE | MIXF_WRITEABLE)) < 0)
+    return err;
+
+  return 0;
+}
+
+envy24_auxdrv_t ews88d_auxdrv = {
+  ews88d_card_init,
+  ews88d_mix_init,
+  NULL,
+  NULL,
+  NULL,
+  NULL,
+  NULL,
+  set_ews88d_speed,
+  NULL,
+  cs8427_spdif_mixer_init
+};
diff --git a/kernel/drv/oss_envy24/envy24_tdif.c b/kernel/drv/oss_envy24/envy24_tdif.c
new file mode 100644
index 0000000..4f247fd
--- /dev/null
+++ b/kernel/drv/oss_envy24/envy24_tdif.c
@@ -0,0 +1,687 @@
+/*
+ * Purpose: Card specific routines for M Audio Delta TDIF
+ */
+/*
+ *
+ * This file is part of Open Sound System.
+ *
+ * Copyright (C) 4Front Technologies 1996-2008.
+ *
+ * This this source file is released under GPL v2 license (no other versions).
+ * See the COPYING file included in the main directory of this source
+ * distribution for the license terms and conditions.
+ *
+ */
+
+#include "oss_config.h"
+#include "ac97.h"
+#include "envy24.h"
+#include "envy24_tdif.h"
+
+#define CDC_CLK 1		/* Clock input to the CODEC's, rising edge clocks data. */
+#define CDC_DIN 2		/* Data input to Envy from the CODEC. */
+#define CDC_DOUT 3		/* Data output from Envy to the CODEC. */
+#define CS8_CS 2		/* Chip select (0=select) for the SPDIF tx/rx. */
+#define CDC_CS 3		/* Chip select (0=select) for the CODEC. */
+#define CS_ASSERT 0		/* Asserted chip select (selects are inverted). */
+#define CS_RELEASE 1		/* Idle chip select (selects are inverted). */
+
+
+#define BIT0		0x01
+#define BIT1		0x02
+#define BIT2		0x04
+#define BIT3		0x08
+#define BIT4		0x10
+#define BIT5		0x20
+#define BIT6		0x40
+#define BIT7		0x80
+
+#define CS8_CLK CDC_CLK
+#define CS8_DIN CDC_DIN
+#define CS8_DOUT CDC_DOUT
+#define CS_TRUE CS_ASSERT
+#define CS_FALSE CS_RELEASE
+#define CS8_ADDR 0x20		/* Chip SPI/I2C address */
+#define CS8_RD 0x01
+#define CS8_WR 0x00
+
+#if 0
+# define PRT_STATUS(v) outb(v&0xff, 0x378)
+#else
+# define PRT_STATUS(v)
+#endif
+
+/* -----	DEFINITION OF GPIOs     ----- */
+
+#define	FPGA_PROGRAM_L		7	/* FPGA program control select line (active low) */
+#define FPGA_CLK		1	/* FPGA program clock */
+#define EXT_REG_CLK		0	/* Was GPIO Fast mode (debug) */
+#define FPGA_D0			3	/* FPGA program data */
+
+#define LATCH_EN_L		4	/* Strobe for external latch (active low) */
+#define FPGA_MUTE		5
+
+#define FPGA_INIT_STATE	0xFC	/* Init state for extern register to allow */
+				/* FPGA initialization. */
+
+#define FPGA_MASTER		5
+
+extern int envy24_gain_sliders;
+extern int envy24_virtualout;
+extern int envy24_zerolatency;	/* Testing in progress */
+
+static void
+WriteExternReg (envy24_devc * devc, unsigned char bData)
+/* Initialize external register by serially shifting the data out */
+/* and then strobe the external latch. */
+{
+  int i;
+
+  devc->gpio_tmp = bData;
+
+  WriteGPIObit (devc, LATCH_EN_L, 0);	/* DISABLE External Latch */
+
+  /* FPGA clock to low */
+  WriteGPIObit (devc, EXT_REG_CLK, 0);
+
+  for (i = 0; i < 8; i++)
+    {
+      /* Present data */
+      WriteGPIObit (devc, FPGA_D0, !!(bData & 0x80));
+      /* clock data in */
+      WriteGPIObit (devc, EXT_REG_CLK, 1);
+      WriteGPIObit (devc, EXT_REG_CLK, 0);
+      /* next bit */
+      bData = bData << 1;
+    }
+
+  WriteGPIObit (devc, LATCH_EN_L, 1);	/* STROBE External Latch */
+  WriteGPIObit (devc, LATCH_EN_L, 0);	/* DISABLE External Latch */
+}
+
+static void
+WriteExternRegBit (envy24_devc * devc, int bit, int value)
+{
+  devc->gpio_tmp &= ~(1 << bit);
+  if (value)
+    devc->gpio_tmp |= (1 << bit);
+  WriteExternReg (devc, devc->gpio_tmp);
+}
+
+static void
+tdif_pause (int n)
+/*
+*****************************************************************************
+*  Programmable pause.
+****************************************************************************/
+{
+  static int d;
+  int i;
+
+  for (i = 0; i < n; i++)
+    for (d = 1000L; d--;);
+}
+
+/****************************************************************************/
+
+
+static void
+TDIF_InitFPGA (envy24_devc * devc)
+/*
+*****************************************************************************
+*  Initialize FPGA
+*  wInst = PCI slot code of specific board.
+*  Hardware = Spartan II FPGA (XC2S50-5TQ144)
+****************************************************************************/
+{
+  int bReadByte;
+  int i, j;
+
+#if 0
+  if (envy24_read_cci (devc, 0x20) & 0x40)
+    {
+      DDB (cmn_err (CE_CONT, "envy24: FPGA is already up and running\n"));
+      return;
+    }
+#endif
+
+  cmn_err (CE_CONT, "Envy24: Loading FPGA - please wait\n");
+
+  /*Init external register */
+  WriteGPIObit (devc, FPGA_PROGRAM_L, 1);	/*DISABLE FPGA Programming */
+  WriteGPIObit (devc, LATCH_EN_L, 0);	/*DISABLE External Latch */
+
+  bReadByte = FPGA_INIT_STATE;
+
+  WriteExternReg (devc, bReadByte);
+
+  /*Pull PROGRAM# pin LOW to start loading configuration data */
+  WriteGPIObit (devc, FPGA_PROGRAM_L, 0);
+  tdif_pause (10);
+  WriteGPIObit (devc, FPGA_PROGRAM_L, 1);
+
+  for (j = 0; j < sizeof (fpga_code); j++)
+    {
+      bReadByte = fpga_code[j];
+      for (i = 0; i < 8; i++)
+	{
+	  /*FPGA clock to low */
+	  WriteGPIObit (devc, FPGA_CLK, 0);
+	  /*Present data */
+	  WriteGPIObit (devc, FPGA_D0, !!(bReadByte & 0x80));
+	  /*clock data in */
+	  WriteGPIObit (devc, FPGA_CLK, 1);
+
+	  /*next bit */
+	  bReadByte = bReadByte << 1;
+	}
+
+    }
+
+  /*Some clocks to start FPGA */
+  for (i = 0; i < 64; i++)
+    {
+      /*FPGA clock to low */
+      WriteGPIObit (devc, FPGA_CLK, 0);
+      /*clock data in */
+      WriteGPIObit (devc, FPGA_CLK, 1);
+    }
+
+  if (!(envy24_read_cci (devc, 0x20) & 0x40))
+    cmn_err (CE_CONT, "Envy24: FPGA failed to initialize\n");
+  else
+    DDB (cmn_err (CE_CONT, "FPGA is up and running\n"));
+
+  oss_udelay (10);
+  WriteExternRegBit (devc, FPGA_MUTE, 1);	/* Keep it still muted */
+
+}
+
+static void
+write_tdif_codec (envy24_devc * devc, int bRegister, unsigned char bData)
+/*
+
+*****************************************************************************
+*  Writes a byte to a specific register of the Delta-AP CODEC.
+*  Register must be (0..15).
+****************************************************************************/
+{
+  unsigned char bMask;
+
+  bRegister = (bRegister & 0x0F) | 0xA0;	/* Add I2C address field. */
+
+  /* Assert the CODEC chip select and wait at least 150 nS. */
+  /* */
+  WriteExternRegBit (devc, CDC_CS, CS_TRUE);
+
+  /* Write the register address byte. */
+  /* */
+  for (bMask = 0x80; bMask; bMask = (bMask >> 1) & 0x7F)
+    {
+      /* Drop SPI clock low. */
+      WriteGPIObit (devc, CDC_CLK, 0);
+
+      /* Write current data bit. */
+      if (bMask & bRegister)
+	WriteGPIObit (devc, CDC_DOUT, 1);
+      else
+	WriteGPIObit (devc, CDC_DOUT, 0);
+
+      /* Raise SPI clock to "clock data in". */
+      WriteGPIObit (devc, CDC_CLK, 1);
+    }
+
+
+  /* Write the data byte. */
+  /* */
+  for (bMask = 0x80; bMask; bMask = (bMask >> 1) & 0x7F)
+    {
+      /* Drop SPI clock low. */
+      WriteGPIObit (devc, CDC_CLK, 0);
+
+      /* Write current data bit. */
+      if (bMask & bData)
+	WriteGPIObit (devc, CDC_DOUT, 1);
+      else
+	WriteGPIObit (devc, CDC_DOUT, 0);
+
+      /* Raise SPI clock to "clock data in". */
+      WriteGPIObit (devc, CDC_CLK, 1);
+    }
+
+  /* De-assert chip select. */
+  /* */
+  WriteExternRegBit (devc, CDC_CS, CS_FALSE);
+}
+
+static void write_tdif_spdif_reg (envy24_devc * devc, int bRegister,
+				  int bData);
+static int read_tdif_spdif_reg (envy24_devc * devc, int bRegister);
+
+static void
+tdif_card_init (envy24_devc * devc)
+{
+  WriteExternReg (devc, 0xfc);
+  TDIF_InitFPGA (devc);
+  write_tdif_spdif_reg (devc, 4, read_tdif_spdif_reg (devc, 4) & (~BIT0));
+  WriteGPIObit (devc, FPGA_MASTER, 1);
+  WriteExternRegBit (devc, 4, 1);	/* Disable TDIF master PLL */
+  WriteExternRegBit (devc, 6, 0);	/* Don't route PLL master clock to Envy24. */
+
+  write_tdif_codec (devc, 0, 0x07);
+  write_tdif_codec (devc, 1, 0x00);
+  write_tdif_codec (devc, 2, 0x60);
+  write_tdif_codec (devc, 3, 0x0d);
+  write_tdif_codec (devc, 4, 0x7f);
+  write_tdif_codec (devc, 1, 0x03);
+  write_tdif_codec (devc, 5, 0x7f);
+}
+
+static void
+tdif_card_uninit (envy24_devc * devc)
+{
+  WriteGPIObit (devc, FPGA_PROGRAM_L, 1);	/*DISABLE FPGA Programming */
+  WriteGPIObit (devc, LATCH_EN_L, 0);	/*DISABLE External Latch */
+  WriteGPIObit (devc, FPGA_PROGRAM_L, 0);
+}
+
+static int
+envy24_set_tdif (int dev, int ctrl, unsigned int cmd, int value)
+{
+  envy24_devc *devc = mixer_devs[dev]->devc;
+  int level;
+  static unsigned char levels[] = { 0x60, 0x6f, 0x7f };
+
+  if (ctrl >= 0xff)
+    return OSS_EINVAL;
+
+  if (cmd == SNDCTL_MIX_READ)
+    {
+      if (envy24_gain_sliders)
+	return devc->akm_gains[ctrl];
+      return devc->akm_gains[ctrl];
+    }
+  else if (cmd == SNDCTL_MIX_WRITE)
+    {
+
+      if (envy24_gain_sliders)
+	level = value & 0xff;
+      else
+	{
+	  if (value > 2)
+	    return OSS_EINVAL;
+	  level = levels[value];
+	}
+
+      write_tdif_codec (devc, 4, level);
+      write_tdif_codec (devc, 5, level);
+      return devc->akm_gains[ctrl] = value;
+    }
+  return OSS_EINVAL;
+}
+
+
+static int
+tdif_mix_init (envy24_devc * devc, int dev, int group)
+{
+  int i, mask = devc->outportmask, err, skip, codec, ports;
+  int typ = MIXT_ENUM, range = 3;
+  char tmp[64];
+
+  if ((group = mixer_ext_create_group (dev, 0, "ENVY24_GAIN")) < 0)
+    return group;
+
+  skip = devc->skipdevs;
+  if (skip != 2)
+    skip = 1;
+
+  if (envy24_gain_sliders)
+    {
+      typ = MIXT_MONOSLIDER;
+      range = 164;
+
+      for (i = 0; i < 0xff; i++)
+	devc->akm_gains[i] = 0x7f;
+    }
+  else
+    for (i = 0; i < 0xff; i++)
+      devc->akm_gains[i] = 0;
+
+  for (i = 0; i < 8; i += skip)
+    {
+
+      if (!(mask & (1 << i)))
+	continue;		/* Not present */
+
+      if (devc->skipdevs == 2)
+	{
+	  if (i == 8)
+	    strcpy (tmp, "ENVY24_SPDOUT");
+	  else
+	    sprintf (tmp, "ENVY24_OUT%d/%d", i + 1, i + 2);
+
+	  codec = (i > 1) ? AKM_B : AKM_A;
+	  ports = 0x0c;		/* Both output ports */
+	  if ((err = mixer_ext_create_control (dev, group,
+					       codec | ports, envy24_set_tdif,
+					       typ,
+					       tmp, range,
+					       MIXF_MAINVOL |
+					       MIXF_READABLE |
+					       MIXF_WRITEABLE)) < 0)
+	    return err;
+	}
+      else
+	{
+	  if (i == 8)
+	    strcpy (tmp, "ENVY24_SPDOUTL");
+	  else if (i == 9)
+	    strcpy (tmp, "ENVY24_SPDOUTR");
+	  else
+	    sprintf (tmp, "ENVY24_OUT%d", i + 1);
+
+	  codec = (i > 1) ? AKM_B : AKM_A;
+	  ports = (i & 1) ? 0x08 : 0x04;
+	  if ((err = mixer_ext_create_control (dev, group,
+					       codec | ports, envy24_set_tdif,
+					       typ,
+					       tmp, range,
+					       MIXF_MAINVOL |
+					       MIXF_READABLE |
+					       MIXF_WRITEABLE)) < 0)
+	    return err;
+	}
+    }
+
+  return 0;
+}
+
+static void
+set_tdif_speed (envy24_devc * devc)
+{
+  int tmp;
+
+  WriteExternRegBit (devc, FPGA_MUTE, 1);	/* Mute FPGA */
+  /* Set the TDIF sampling rate */
+  devc->gpio_tmp &= ~0x03;
+  switch (devc->speed)
+    {
+    case 32000:
+      devc->gpio_tmp |= 0x01;
+      break;
+    case 44100:
+      devc->gpio_tmp |= 0x02;
+      break;
+    case 48000:
+      devc->gpio_tmp |= 0x01;
+      break;
+    default:
+      devc->gpio_tmp |= 0x01;
+      break;
+    }
+  WriteExternReg (devc, devc->gpio_tmp);
+
+  tmp = devc->speedbits;
+
+  switch (devc->syncsource)
+    {
+    case SYNC_INTERNAL:
+      OUTB (devc->osdev, tmp, devc->mt_base + 0x01);
+      WriteGPIObit (devc, FPGA_MASTER, 1);
+      write_tdif_spdif_reg (devc, 4, read_tdif_spdif_reg (devc, 4) & (~BIT0));
+      WriteExternRegBit (devc, 4, 1);	/* Disable TDIF master PLL */
+      WriteExternRegBit (devc, 6, 0);	/* Don't route PLL master clock to Envy24. */
+      break;
+
+    case SYNC_SPDIF:
+      tmp |= 0x10;
+      OUTB (devc->osdev, tmp, devc->mt_base + 0x01);
+      WriteGPIObit (devc, FPGA_MASTER, 1);
+      write_tdif_spdif_reg (devc, 4, read_tdif_spdif_reg (devc, 4) | BIT0);
+      WriteExternRegBit (devc, 6, 1);	/* Do route PLL master clock to Envy24. */
+      WriteExternRegBit (devc, 4, 1);	/* Disable TDIF master PLL */
+      break;
+
+    case SYNC_WCLOCK:
+      tmp |= 0x10;
+      OUTB (devc->osdev, tmp, devc->mt_base + 0x01);
+      write_tdif_spdif_reg (devc, 4, read_tdif_spdif_reg (devc, 4) & (~BIT0));
+      WriteExternRegBit (devc, 4, 0);	/* Enable TDIF master PLL */
+      WriteExternRegBit (devc, 6, 1);	/* Do route PLL master clock to Envy24. */
+      WriteGPIObit (devc, FPGA_MASTER, 0);
+      break;
+    }
+
+  if (devc->speed > 48000)
+    {
+      write_tdif_codec (devc, 0x01, 0x00);
+      write_tdif_codec (devc, 0x02, 0x65);
+      write_tdif_codec (devc, 0x01, 0x03);
+    }
+  else
+    {
+      write_tdif_codec (devc, 0x01, 0x00);
+      write_tdif_codec (devc, 0x02, 0x60);
+      write_tdif_codec (devc, 0x01, 0x03);
+    }
+  WriteExternRegBit (devc, FPGA_MUTE, 0);	/* Unmute */
+}
+
+static void
+write_tdif_spdif_reg (envy24_devc * devc, int bRegister, int bData)
+{
+  unsigned char bMask;
+  unsigned char bSPI;
+
+  /* Assert the CODEC chip select and wait at least 150 nS. */
+  /* */
+  WriteExternRegBit (devc, CS8_CS, CS_TRUE);
+
+  /* Write the SPI address/cmd byte. */
+  /* */
+  bSPI = CS8_ADDR | CS8_WR;
+  /* */
+  for (bMask = 0x80; bMask; bMask = (bMask >> 1) & 0x7F)
+    {
+      /* Drop SPI clock low. */
+      WriteGPIObit (devc, CS8_CLK, 0);
+
+      /* Write current data bit. */
+      if (bMask & bSPI)
+	WriteGPIObit (devc, CS8_DOUT, 1);
+      else
+	WriteGPIObit (devc, CS8_DOUT, 0);
+
+      /* Raise SPI clock to "clock data in". */
+      WriteGPIObit (devc, CS8_CLK, 1);
+    }
+
+  /* Write the address (MAP) byte. */
+  /* */
+  for (bMask = 0x80; bMask; bMask = (bMask >> 1) & 0x7F)
+    {
+      /* Drop SPI clock low. */
+      WriteGPIObit (devc, CS8_CLK, 0);
+
+      /* Write current data bit. */
+      if (bMask & bRegister)
+	WriteGPIObit (devc, CS8_DOUT, 1);
+      else
+	WriteGPIObit (devc, CS8_DOUT, 0);
+
+      /* Raise SPI clock to "clock data in". */
+      WriteGPIObit (devc, CS8_CLK, 1);
+    }
+
+
+  /* Write the data byte. */
+  /* */
+  for (bMask = 0x80; bMask; bMask = (bMask >> 1) & 0x7F)
+    {
+      /* Drop SPI clock low. */
+      WriteGPIObit (devc, CS8_CLK, 0);
+
+      /* Write current data bit. */
+      if (bMask & bData)
+	WriteGPIObit (devc, CS8_DOUT, 1);
+      else
+	WriteGPIObit (devc, CS8_DOUT, 0);
+
+      /* Raise SPI clock to "clock data in". */
+      WriteGPIObit (devc, CS8_CLK, 1);
+    }
+
+  /* De-assert chip select. */
+  /* */
+  WriteExternRegBit (devc, CS8_CS, CS_FALSE);
+}
+
+static int
+read_tdif_spdif_reg (envy24_devc * devc, int reg)
+{
+  unsigned char bMask;
+  unsigned char bRet = 0;
+  unsigned char bSPI;
+
+
+	/****** WRITE MAP ADDRESS FIRST ******/
+
+  /* Drop the chip select low. */
+  /* Wait at least 150 nS. */
+  /* */
+  WriteExternRegBit (devc, CS8_CS, CS_TRUE);
+
+  /* Write the SPI address/cmd byte. */
+  /* */
+  bSPI = CS8_ADDR + CS8_WR;	/* SPI address field plus WRITE operation. */
+  /* */
+  for (bMask = 0x80; bMask; bMask = (bMask >> 1) & 0x7F)
+    {
+      /* Drop clock (GPIO5) low. */
+      WriteGPIObit (devc, CDC_CLK, 0);
+
+      /* Write current data bit. */
+      if (bMask & bSPI)
+	WriteGPIObit (devc, CDC_DOUT, 1);
+      else
+	WriteGPIObit (devc, CDC_DOUT, 0);
+
+      /* Raise clock (GPIO5). */
+      WriteGPIObit (devc, CDC_CLK, 1);
+    }
+
+
+  /* Write the address (MAP) byte. */
+  /* */
+  for (bMask = 0x80; bMask; bMask = (bMask >> 1) & 0x7F)
+    {
+      /* Drop clock (GPIO5) low. */
+      WriteGPIObit (devc, CDC_CLK, 0);
+
+      /* Write current data bit. */
+      if (bMask & reg)
+	WriteGPIObit (devc, CDC_DOUT, 1);
+      else
+	WriteGPIObit (devc, CDC_DOUT, 0);
+
+      /* Raise clock (GPIO5). */
+      WriteGPIObit (devc, CDC_CLK, 1);
+    }
+
+  /* De-assert chip select(s). */
+  /* */
+  WriteExternRegBit (devc, CS8_CS, CS_FALSE);
+
+
+	/****** NOW READ THE DATA ******/
+
+  /* Drop the chip select low. */
+  /* Wait at least 150 nS. */
+  /* */
+  WriteExternRegBit (devc, CS8_CS, CS_TRUE);
+
+
+  /* Write the SPI address/cmd byte. */
+  /* */
+  bSPI = CS8_ADDR + CS8_RD;	/* SPI address field plus READ operation. */
+  /* */
+  for (bMask = 0x80; bMask; bMask = (bMask >> 1) & 0x7F)
+    {
+      /* Drop clock (GPIO5) low. */
+      WriteGPIObit (devc, CDC_CLK, 0);
+
+      /* Write current data bit. */
+      if (bMask & bSPI)
+	WriteGPIObit (devc, CDC_DOUT, 1);
+      else
+	WriteGPIObit (devc, CDC_DOUT, 0);
+
+      /* Raise clock (GPIO5). */
+      WriteGPIObit (devc, CDC_CLK, 1);
+    }
+
+
+  /* Read the data byte. */
+  /* */
+  bRet = 0;
+  /* */
+  for (bMask = 0x80; bMask; bMask = (bMask >> 1) & 0x7F)
+    {
+      /* Drop clock low. */
+      WriteGPIObit (devc, CDC_CLK, 0);
+
+      /* Read current data bit. */
+      if (ReadGPIObit (devc, CDC_DIN))
+	bRet |= bMask;
+
+      /* Raise clock. */
+      WriteGPIObit (devc, CDC_CLK, 1);
+    }
+
+
+  /* De-assert chip selects. */
+  /* */
+  WriteExternRegBit (devc, CS8_CS, CS_FALSE);
+
+  /* Return value. */
+
+  return bRet;
+}
+
+static int
+tdif_get_locked_status (envy24_devc * devc)
+{
+  switch (devc->syncsource)
+    {
+    case SYNC_INTERNAL:
+      return 1;
+      break;
+
+    case SYNC_SPDIF:
+      return !(read_tdif_spdif_reg (devc, 16) & 0x17);
+      break;
+
+    case SYNC_WCLOCK:
+      /* The SPI input pin shows the TDIF locked status */
+      if (envy24_read_cci (devc, 0x20) & (1 << 2))
+	return 1;
+      return 0;
+      break;
+    }
+
+  return 1;
+}
+
+envy24_auxdrv_t tdif_auxdrv = {
+  tdif_card_init,
+  tdif_mix_init,
+  init_cs8427_spdif,
+  write_cs8427_spdif,
+  cs8427_spdif_ioctl,
+  read_tdif_spdif_reg,
+  write_tdif_spdif_reg,
+  set_tdif_speed,
+  tdif_get_locked_status,
+  cs8427_spdif_mixer_init,
+  tdif_card_uninit
+};
diff --git a/kernel/drv/oss_envy24/envy24_tdif.h b/kernel/drv/oss_envy24/envy24_tdif.h
new file mode 100644
index 0000000..8fd1f9f
--- /dev/null
+++ b/kernel/drv/oss_envy24/envy24_tdif.h
@@ -0,0 +1,5836 @@
+/*
+ * Purpose: FPGA firmware for M-Audio Delta TDIF
+ */
+static unsigned char fpga_code[] = {
+  0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x00, 0x00,
+  0x01, 0x61, 0x00, 0x0b, 0x74, 0x64, 0x69, 0x66, 0x5f, 0x31, 0x2e, 0x6e,
+  0x63, 0x64, 0x00, 0x62, 0x00, 0x0a, 0x32, 0x73, 0x35, 0x30, 0x74, 0x71,
+  0x31, 0x34, 0x34, 0x00, 0x63, 0x00, 0x0b, 0x32, 0x30, 0x30, 0x31, 0x2f,
+  0x30, 0x31, 0x2f, 0x32, 0x30, 0x00, 0x64, 0x00, 0x09, 0x30, 0x31, 0x3a,
+  0x33, 0x38, 0x3a, 0x30, 0x38, 0x00, 0x65, 0x00, 0x01, 0x11, 0x0c, 0xff,
+  0xff, 0xff, 0xff, 0xaa, 0x99, 0x55, 0x66, 0x30, 0x00, 0x80, 0x01, 0x00,
+  0x00, 0x00, 0x07, 0x30, 0x01, 0x60, 0x01, 0x00, 0x00, 0x00, 0x0b, 0x30,
+  0x01, 0x20, 0x01, 0x00, 0x80, 0x3f, 0x2d, 0x30, 0x00, 0xc0, 0x01, 0x00,
+  0x00, 0x00, 0x00, 0x30, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x09, 0x30,
+  0x00, 0x20, 0x01, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x80, 0x01, 0x00,
+  0x00, 0x00, 0x01, 0x30, 0x00, 0x40, 0x00, 0x50, 0x00, 0x3e, 0x04, 0x00,
+  0x12, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x14, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x12, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x04, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x04, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x04, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
+  0x12, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
+  0x00, 0x00, 0x80, 0x00, 0x20, 0x00, 0x28, 0x00, 0x12, 0x00, 0x02, 0x80,
+  0x01, 0x80, 0x00, 0x70, 0x00, 0x1c, 0x00, 0x02, 0x80, 0x00, 0xa0, 0x00,
+  0x28, 0x3f, 0xd4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0,
+  0x05, 0xfc, 0x00, 0xff, 0x00, 0x3f, 0xc0, 0x0f, 0xf0, 0x03, 0xfc, 0x00,
+  0xff, 0x00, 0x3f, 0xc0, 0x0f, 0xf0, 0x03, 0x7c, 0x00, 0xff, 0x00, 0x3f,
+  0xc0, 0x0f, 0xe0, 0x03, 0xf4, 0x02, 0xc7, 0x00, 0x3f, 0xc0, 0x2c, 0xf1,
+  0x03, 0x30, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0,
+  0x10, 0xec, 0x00, 0xbb, 0x00, 0x2e, 0xc0, 0x09, 0xb0, 0x02, 0xec, 0x00,
+  0xbb, 0x00, 0x2e, 0xc0, 0x0b, 0xb0, 0x02, 0xec, 0x00, 0xbb, 0x00, 0x2e,
+  0xc0, 0x0b, 0x90, 0x02, 0xe4, 0x20, 0x8b, 0x00, 0x2f, 0xd0, 0x08, 0xb0,
+  0x02, 0x30, 0x04, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8,
+  0x05, 0xcc, 0x00, 0xb3, 0x00, 0x2c, 0xc0, 0x0b, 0x30, 0x02, 0xcc, 0x00,
+  0xb3, 0x00, 0x2c, 0xc0, 0x0b, 0x30, 0x02, 0xcc, 0x00, 0xb3, 0x00, 0x2c,
+  0xc0, 0x0b, 0x38, 0x02, 0xe4, 0x80, 0x83, 0x00, 0x2c, 0x44, 0x28, 0x32,
+  0x02, 0x32, 0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0,
+  0x15, 0xac, 0x00, 0xbb, 0x00, 0x2e, 0xc0, 0x09, 0xb0, 0x02, 0xec, 0x00,
+  0xbb, 0x00, 0x2e, 0xc0, 0x0b, 0xb0, 0x02, 0xec, 0x00, 0xbb, 0x00, 0x2e,
+  0xc0, 0x0b, 0x98, 0x02, 0xe4, 0x10, 0x8b, 0x00, 0x2e, 0x40, 0x28, 0x30,
+  0x02, 0x30, 0x04, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
+  0x15, 0xec, 0x00, 0x7b, 0x00, 0x3e, 0xc0, 0x0f, 0xb0, 0x03, 0xec, 0x00,
+  0xfb, 0x00, 0x3e, 0xc0, 0x0f, 0xb0, 0x03, 0xec, 0x00, 0xfb, 0x00, 0x3e,
+  0xc0, 0x0f, 0xb8, 0x03, 0xc4, 0x00, 0xcb, 0x00, 0x3f, 0xe0, 0x0c, 0xb0,
+  0x03, 0x10, 0x04, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0,
+  0x01, 0xbc, 0x00, 0xff, 0x00, 0x3f, 0xc0, 0x0d, 0xf0, 0x03, 0xfc, 0x00,
+  0xff, 0x00, 0x3f, 0xc0, 0x0f, 0xf0, 0x03, 0xfc, 0x00, 0xff, 0x00, 0x3f,
+  0xc0, 0x0f, 0xd0, 0x03, 0xf5, 0x00, 0xff, 0x00, 0x3e, 0xc8, 0x0f, 0xf0,
+  0x03, 0xf8, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
+  0x10, 0xac, 0x00, 0xfb, 0x00, 0x3e, 0xc0, 0x0f, 0xb0, 0x03, 0xec, 0x00,
+  0xfb, 0x00, 0x3e, 0xc0, 0x0f, 0xb0, 0x03, 0xec, 0x00, 0xfb, 0x00, 0x32,
+  0xc0, 0x0f, 0xb0, 0x03, 0xe4, 0x40, 0xfb, 0x00, 0x3a, 0x40, 0x0e, 0xb0,
+  0x03, 0x90, 0x04, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8,
+  0x05, 0x2c, 0x00, 0xbb, 0x00, 0x2e, 0xc0, 0x0b, 0xb0, 0x02, 0xec, 0x00,
+  0xbb, 0x00, 0x2e, 0xc0, 0x0b, 0xb0, 0x02, 0xec, 0x00, 0xbb, 0x00, 0x22,
+  0xc0, 0x0b, 0x90, 0x02, 0xe4, 0x00, 0xbf, 0x08, 0x21, 0x40, 0x08, 0xb8,
+  0x02, 0x32, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0,
+  0x05, 0x4c, 0x00, 0xb3, 0x00, 0x2c, 0xc0, 0x0b, 0x30, 0x02, 0xcc, 0x00,
+  0xb3, 0x00, 0x2c, 0xc0, 0x0b, 0x30, 0x02, 0xcc, 0x00, 0xb3, 0x00, 0xa0,
+  0xc0, 0x0b, 0x10, 0x02, 0xc7, 0x20, 0xb3, 0x80, 0x28, 0x40, 0x0a, 0x38,
+  0x02, 0xb8, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0,
+  0x01, 0x1e, 0x00, 0xb7, 0x80, 0x2d, 0xe0, 0x0b, 0x78, 0x02, 0xde, 0x00,
+  0xb7, 0x80, 0x2d, 0xe0, 0x0b, 0x78, 0x02, 0xde, 0x00, 0xb7, 0x80, 0x21,
+  0xe0, 0x0b, 0x5c, 0x02, 0xde, 0x00, 0xb7, 0x82, 0x21, 0x60, 0x08, 0x7c,
+  0x02, 0x38, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48,
+  0x08, 0x0c, 0x00, 0xf3, 0x00, 0x3c, 0xc0, 0x0f, 0x30, 0x03, 0xcc, 0x00,
+  0xf3, 0x00, 0x3c, 0xc0, 0x0f, 0x30, 0x03, 0xcc, 0x00, 0xfb, 0x00, 0x30,
+  0xc0, 0x0f, 0x10, 0x03, 0xc4, 0x00, 0xf3, 0x00, 0x18, 0xc0, 0x0e, 0xb0,
+  0x83, 0x92, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
+  0x1d, 0xbc, 0x00, 0xff, 0x00, 0x3f, 0xc0, 0x0f, 0xf0, 0x03, 0xfc, 0x00,
+  0xff, 0x00, 0x3f, 0xc0, 0x0f, 0xf0, 0x03, 0xfc, 0x00, 0xff, 0x00, 0x3f,
+  0xc0, 0x0f, 0xd0, 0x03, 0xfc, 0x00, 0xff, 0x00, 0x3f, 0xc2, 0x2f, 0xf0,
+  0x03, 0xd0, 0x06, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8,
+  0x05, 0xec, 0x00, 0xfb, 0x00, 0x3e, 0xc0, 0x0f, 0xb0, 0x03, 0xec, 0x00,
+  0xfb, 0x00, 0x3e, 0xc0, 0x0f, 0xb0, 0x03, 0xec, 0x00, 0xfb, 0x00, 0x3e,
+  0xc0, 0x0f, 0x90, 0x03, 0xe4, 0x00, 0xfb, 0x10, 0x30, 0x48, 0x0c, 0xb0,
+  0x63, 0xea, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8,
+  0x11, 0x9c, 0x00, 0xb7, 0x00, 0x2d, 0xc0, 0x0b, 0x70, 0x02, 0xdc, 0x00,
+  0xb7, 0x00, 0x2d, 0xc0, 0x0b, 0x70, 0x02, 0xdc, 0x00, 0xb7, 0x00, 0x2d,
+  0xc0, 0x0b, 0x50, 0x02, 0xdc, 0x00, 0xb7, 0x00, 0x21, 0x62, 0x28, 0x70,
+  0x02, 0xf2, 0x04, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0,
+  0x00, 0x9e, 0x00, 0xb7, 0x80, 0x2d, 0xe0, 0x0b, 0x78, 0x02, 0xde, 0x00,
+  0xb7, 0x80, 0x2d, 0xe0, 0x0b, 0x78, 0x02, 0xde, 0x00, 0xb7, 0x80, 0x2d,
+  0xe0, 0x0b, 0x58, 0x02, 0xd6, 0x00, 0xb3, 0x80, 0x21, 0xe0, 0x08, 0x78,
+  0x02, 0xf0, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48,
+  0x14, 0xcc, 0x00, 0xb3, 0x00, 0x2c, 0xc0, 0x0b, 0x30, 0x02, 0xcc, 0x00,
+  0xb3, 0x00, 0x2c, 0xc0, 0x0b, 0x30, 0x02, 0xcc, 0x00, 0xb3, 0x00, 0x2c,
+  0xc0, 0x0b, 0x10, 0x02, 0xcc, 0x00, 0xb3, 0x00, 0xa0, 0xc0, 0x08, 0x30,
+  0x02, 0xd2, 0x04, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe8,
+  0x15, 0xa8, 0x00, 0xfa, 0x00, 0x3e, 0x80, 0x0f, 0xa0, 0x03, 0xe8, 0x00,
+  0xfa, 0x00, 0x3e, 0x80, 0x0f, 0xa0, 0x03, 0xe8, 0x00, 0xfa, 0x00, 0x3e,
+  0x80, 0x0f, 0x60, 0x03, 0xe8, 0x00, 0xfa, 0x00, 0x32, 0x80, 0x0c, 0xa0,
+  0x23, 0xfa, 0x04, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48,
+  0x00, 0xe0, 0x00, 0xf8, 0x00, 0x3e, 0x00, 0x0f, 0x80, 0x03, 0xe0, 0x00,
+  0xf8, 0x00, 0x3e, 0x00, 0x0f, 0x80, 0x03, 0xe0, 0x00, 0xf8, 0x00, 0x3e,
+  0x00, 0x0f, 0x88, 0x03, 0xe0, 0x00, 0xf8, 0x00, 0x3c, 0x00, 0x0f, 0x84,
+  0x03, 0xd2, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
+  0x10, 0xe4, 0x00, 0xf9, 0x00, 0x3e, 0x40, 0x0f, 0x90, 0x03, 0xe4, 0x00,
+  0xf9, 0x00, 0x3e, 0x40, 0x0f, 0x90, 0x03, 0xe4, 0x00, 0xf9, 0x00, 0x3e,
+  0x40, 0x0f, 0x90, 0x03, 0x24, 0x00, 0xf9, 0x00, 0x32, 0x40, 0x0e, 0x90,
+  0x03, 0x82, 0x04, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
+  0x04, 0x64, 0x00, 0xb9, 0x00, 0x2e, 0x40, 0x0b, 0x90, 0x02, 0xe4, 0x00,
+  0xb9, 0x00, 0x2e, 0x40, 0x0b, 0x90, 0x02, 0xe4, 0x00, 0xb9, 0x00, 0x2e,
+  0x40, 0x0b, 0x98, 0x02, 0x24, 0x00, 0xb1, 0x40, 0xa2, 0x40, 0x08, 0x96,
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+  0x40, 0x0f, 0x90, 0x03, 0xe4, 0x00, 0xf9, 0x00, 0x3e, 0x40, 0x0c, 0x18,
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+  0x60, 0x0b, 0x90, 0x02, 0xe4, 0x00, 0xb9, 0x00, 0x2e, 0x40, 0x28, 0x92,
+  0x02, 0x06, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
+  0x04, 0x04, 0x00, 0xb1, 0x00, 0x2c, 0x40, 0x0b, 0x10, 0x02, 0xc4, 0x00,
+  0xb1, 0x00, 0x2c, 0x40, 0x0b, 0x10, 0x02, 0xc4, 0x00, 0xb1, 0x28, 0x2c,
+  0x40, 0x0b, 0x12, 0x02, 0xc4, 0x00, 0xb1, 0x00, 0x2c, 0x4a, 0x08, 0x12,
+  0x82, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb8,
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+  0xf8, 0x00, 0x3e, 0x00, 0x0f, 0x80, 0x03, 0xe0, 0x00, 0xf8, 0x20, 0x3e,
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+  0x40, 0x0f, 0xd1, 0x03, 0xe4, 0x00, 0xf9, 0x28, 0x3e, 0x4a, 0x0f, 0xd2,
+  0x83, 0xe6, 0x06, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x98,
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+  0xb3, 0x00, 0x2c, 0xc0, 0x0b, 0x30, 0x02, 0xcc, 0x00, 0xb3, 0x00, 0x2c,
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+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
diff --git a/kernel/drv/oss_envy24/oss_envy24.c b/kernel/drv/oss_envy24/oss_envy24.c
new file mode 100644
index 0000000..b3b82bd
--- /dev/null
+++ b/kernel/drv/oss_envy24/oss_envy24.c
@@ -0,0 +1,4043 @@
+/*
+ * Purpose: Driver for IC Ensemble ENVY24 based audio cards.
+ *
+ * The audio input and output devices implemented by this driver use additional
+ * layer of buffering for channel re-interleaving. The device itself uses
+ * 10/12 channel interleaved 32 bit format in hardware level. The
+ * re-interleaving engine splits these multi channel devices to several
+ * "stereo" devices.
+ */
+/*
+ *
+ * This file is part of Open Sound System.
+ *
+ * Copyright (C) 4Front Technologies 1996-2008.
+ *
+ * This this source file is released under GPL v2 license (no other versions).
+ * See the COPYING file included in the main directory of this source
+ * distribution for the license terms and conditions.
+ *
+ */
+
+#include "oss_envy24_cfg.h"
+#include <ac97.h>
+#include <oss_pci.h>
+
+#include "envy24.h"
+
+extern int envy24_skipdevs;
+extern int envy24_force_mono;
+extern int envy24_gain_sliders;
+int envy24_virtualout = 0;	/* This used to be an config option */
+
+extern int envy24_devmask;
+#define DMASK_ANALOGOUT		1
+#define DMASK_ANALOGIN		2
+#define DMASK_SPDIFOUT		4
+#define DMASK_SPDIFIN		8
+#define DMASK_MONITORIN	       16
+#define DMASK_RAWDEVS	       32
+
+extern envy24_auxdrv_t default_auxdrv;
+extern envy24_auxdrv_t ap2496_auxdrv;
+extern envy24_auxdrv_t d410_auxdrv;
+extern envy24_auxdrv_t d1010lt_auxdrv;
+extern envy24_auxdrv_t tdif_auxdrv;
+extern envy24_auxdrv_t ewx2496_auxdrv;
+extern envy24_auxdrv_t ews88d_auxdrv;
+extern envy24_auxdrv_t dmx6fire_auxdrv;
+
+static card_spec models[] = {
+  {0xd6301412, "M Audio Delta 1010", 8, 8,
+   MF_MAUDIO | MF_MIDI1 | MF_SPDIF | MF_WCLOCK | MF_MEEPROM},
+  {0xd6311412, "M Audio Delta DiO 2496", 2, 0,
+   MF_MAUDIO | MF_SPDIF | MF_SPDSELECT | MF_MEEPROM},
+  {0xd6321412, "M Audio Delta 66", 4, 4,
+   MF_MAUDIO | MF_SPDIF | MF_AKMCODEC | MF_MEEPROM},
+  {0xd6331412, "M Audio Delta 44", 4, 4,
+   MF_MAUDIO | MF_AKMCODEC | MF_MEEPROM},
+  {0xd6341412, "M Audio Audiophile 2496", 2, 2,
+   MF_AP | MF_SPDIF | MF_MIDI1 | MF_MEEPROM, &ap2496_auxdrv},
+  {0xd6381412, "M Audio Delta 410", 8, 2, MF_D410 | MF_SPDIF | MF_MEEPROM,
+   &d410_auxdrv},
+
+  /* Delta 1010 rev E is based on 1010LT instead of the original 1010 design */
+  {0xd63014ff, "M Audio Delta 1010 rev E", 8, 8,
+   MF_MIDI1 | MF_SPDIF | MF_MEEPROM | MF_WCLOCK, &d1010lt_auxdrv},
+  
+  {0xd63b1412, "M Audio Delta 1010LT", 8, 8,
+   MF_MIDI1 | MF_SPDIF | MF_MEEPROM | MF_WCLOCK, &d1010lt_auxdrv},
+  {0xd6351412, "M Audio Delta TDIF", 8, 8, MF_SPDIF | MF_MEEPROM | MF_WCLOCK,
+   &tdif_auxdrv},
+  {0x1115153b, "Terratec EWS88MT", 8, 8,
+   MF_MIDI1 | MF_SPDIF | MF_EWS88 | MF_AC97},
+  {0x112b153b, "Terratec EWS88D", 8, 8,
+   MF_MIDI1 | MF_MIDI2 | MF_SPDIF | MF_AC97 | MF_WCLOCK, &ews88d_auxdrv},
+  {0x1130153b, "Terratec EWX 24/96", 2, 2, MF_SPDIF | MF_EWX2496,
+   &ewx2496_auxdrv},
+  {0x1138153b, "Terratec DMX6fire 24/96", 6, 6,
+   MF_MIDI1 | MF_MIDI2 | MF_SPDIF, &dmx6fire_auxdrv},
+  {0x17121412, "Generic Envy24 based card", 8, 8,
+   MF_SPDIF | MF_MIDI1 | MF_CONSUMER | MF_HOONTECH},
+  {0}
+};
+
+static struct speed_sel speed_tab[] = {
+  {
+   8000, 0x06}
+  ,
+  {
+   9600, 0x03}
+  ,
+  {
+   11025, 0x0a}
+  ,
+  {
+   12000, 0x02}
+  ,
+  {
+   16000, 0x05}
+  ,
+  {
+   22050, 0x09}
+  ,
+  {
+   24000, 0x01}
+  ,
+  {
+   32000, 0x04}
+  ,
+  {
+   44100, 0x08}
+  ,
+  {
+   48000, 0x00}
+  ,
+  /* {64000, 0x0f}, doesn't work */
+  {
+   88200, 0x0b}
+  ,
+  {
+   96000, 0x07}
+  ,
+  {
+   -1, 0x10}
+  ,
+};
+
+int
+envy24_read_cci (envy24_devc * devc, int pos)
+{
+  OUTB (devc->osdev, pos, devc->ccs_base + 0x03);
+  return INB (devc->osdev, devc->ccs_base + 0x04);
+}
+
+void
+envy24_write_cci (envy24_devc * devc, int pos, int data)
+{
+  OUTB (devc->osdev, pos, devc->ccs_base + 0x03);
+  OUTB (devc->osdev, data, devc->ccs_base + 0x04);
+}
+
+static int
+eeprom_read (envy24_devc * devc, int pos)
+{
+  int i, status;
+
+  for (i = 0; i < 0x10000; i++)
+    {
+      status = INB (devc->osdev, devc->ccs_base + 0x13);
+      if (!(status & 1))
+	break;
+
+    }
+
+  OUTB (devc->osdev, 0xa0, devc->ccs_base + 0x10);	/* EEPROM read */
+  OUTB (devc->osdev, pos, devc->ccs_base + 0x11);	/* Offset */
+
+  for (i = 0; i < 2000; i++)
+    {
+      status = INB (devc->osdev, devc->ccs_base + 0x13);
+      if (!(status & 1))
+	break;
+
+    }
+
+  oss_udelay (1);
+  return INB (devc->osdev, devc->ccs_base + 0x12);
+}
+
+static int
+load_eeprom (envy24_devc * devc, int subid)
+{
+  int status, i, check;
+
+  status = INB (devc->osdev, devc->ccs_base + 0x13);
+
+  if (!(status & 0x80))
+    return 0;			/* No EEPROM */
+
+  for (i = 0; i < 32; i++)
+    {
+      devc->eeprom[i] = eeprom_read (devc, i);
+      devc->eeprom[i] = eeprom_read (devc, i);
+    }
+  DDB (cmn_err (CE_CONT, "EEPROM="));
+  for (i = 0; i < 10; i++)
+    DDB (cmn_err (CE_CONT, "0x%02x, ", devc->eeprom[i]));
+  DDB (cmn_err (CE_CONT, "\n"));
+
+  check = 0;
+  for (i = 0; i < 4; i++)
+    {
+      check <<= 8;
+      check |= devc->eeprom[i];
+    }
+
+  if (check != subid)
+    cmn_err (CE_CONT,
+	     "Envy24 WARNING: Possible EEPROM read error %08x != %08x\n",
+	     check, subid);
+
+  return 1;
+}
+
+static void
+handle_playdev (envy24_devc * devc, envy24_portc * portc, int this_frag)
+{
+  int sample, nsamples, nbytes, ch;
+  dmap_t *dmap = audio_engines[portc->dev]->dmap_out;
+
+  if (!(portc->trigger_bits & PCM_ENABLE_OUTPUT) && devc->playback_started)
+    return;
+
+  nsamples = devc->hw_fragsamples;	/* Number of 32 bit samples */
+
+  nbytes = nsamples * portc->channels;
+
+  if (audio_engines[portc->dev]->dmap_out->flags & DMAP_POST)
+    {
+      if (portc->pcm_qlen > 0)
+	portc->pcm_qlen--;
+    }
+  else
+    {
+      if (portc->pcm_qlen < devc->writeahead)
+	portc->pcm_qlen++;
+    }
+
+  if (portc->bits & (AFMT_S16_LE | AFMT_S16_BE | AFMT_AC3))
+    nbytes *= 2;
+  else if (portc->
+	   bits & (AFMT_S32_LE | AFMT_S32_BE | AFMT_S24_LE | AFMT_S24_BE))
+    nbytes *= 4;
+
+  if (nbytes != dmap->fragment_size)
+    return;			/* Fragment size mismatch */
+
+  switch (portc->bits)
+    {
+    case AFMT_U8:
+      {
+	unsigned char *ip;
+	int *op;
+
+	ip = audio_engines[portc->dev]->dmap_out->dmabuf;
+	ip += (dmap_get_qhead (dmap) * dmap->fragment_size);
+	op = (int *) (devc->playbuf + devc->hw_pfragsize * this_frag);
+	VMEM_CHECK (ip, nsamples * sizeof (*ip));
+	VMEM_CHECK (op, nsamples * sizeof (*op));
+
+	for (sample = 0; sample < nsamples; sample++)
+	  {
+	    int *p = &op[sample * 10 + portc->chnum];
+
+	    for (ch = 0; ch < portc->channels; ch++)
+	      {
+		*p++ = (*ip++ ^ 0x80) << 24;
+	      }
+	  }
+      }
+      break;
+
+    case AFMT_AC3:
+    case AFMT_S16_LE:
+      {
+	short *ip;
+	int *op;
+#ifdef DO_TIMINGS
+	oss_timing_printf ("Envy24: Copy out %d, %d",
+		   dmap_get_qhead (dmap) * dmap->fragment_size, nbytes);
+#endif
+
+	ip = (short *) (dmap->dmabuf +
+			(dmap_get_qhead (dmap) * dmap->fragment_size));
+	op = (int *) (devc->playbuf + devc->hw_pfragsize * this_frag);
+	VMEM_CHECK (ip, nsamples * sizeof (*ip));
+	VMEM_CHECK (op, nsamples * sizeof (*op));
+
+	for (sample = 0; sample < nsamples; sample++)
+	  {
+	    int *p = &op[sample * 10 + portc->chnum];
+
+	    for (ch = 0; ch < portc->channels; ch++)
+	      {
+		*p++ = *ip++ << 16;
+	      }
+	  }
+      }
+      break;
+
+    case AFMT_S16_BE:
+      {
+	short *ip;
+	int *op;
+
+	ip = (short *) (audio_engines[portc->dev]->dmap_out->dmabuf +
+			(dmap_get_qhead (dmap) * dmap->fragment_size));
+	op = (int *) (devc->playbuf + devc->hw_pfragsize * this_frag);
+	VMEM_CHECK (ip, nsamples * sizeof (*ip));
+	VMEM_CHECK (op, nsamples * sizeof (*op));
+
+	for (sample = 0; sample < nsamples; sample++)
+	  {
+	    int *p = &op[sample * 10 + portc->chnum];
+
+	    for (ch = 0; ch < portc->channels; ch++)
+	      {
+		short s = (short) (((*(unsigned short *) ip & 0xff) << 8) |
+				   ((*(unsigned short *) ip & 0xff00) >>
+				    8));
+		ip++;
+		*p++ = s << 16;
+	      }
+	  }
+      }
+      break;
+
+    case AFMT_S24_LE:
+      {
+	int *ip;
+	int *op;
+
+	ip = (int *) (audio_engines[portc->dev]->dmap_out->dmabuf +
+		      (dmap_get_qhead (dmap) * dmap->fragment_size));
+	op = (int *) (devc->playbuf + devc->hw_pfragsize * this_frag);
+	VMEM_CHECK (ip, nsamples * sizeof (*ip));
+	VMEM_CHECK (op, nsamples * sizeof (*op));
+
+	for (sample = 0; sample < nsamples; sample++)
+	  {
+	    int *p = &op[sample * 10 + portc->chnum];
+
+	    for (ch = 0; ch < portc->channels; ch++)
+	      {
+		*p++ = *ip++ << 8;
+	      }
+	  }
+      }
+      break;
+
+    case AFMT_S32_LE:
+      {
+	int *ip;
+	int *op;
+
+	ip = (int *) (audio_engines[portc->dev]->dmap_out->dmabuf +
+		      (dmap_get_qhead (dmap) * dmap->fragment_size));
+	op = (int *) (devc->playbuf + devc->hw_pfragsize * this_frag);
+	VMEM_CHECK (ip, nsamples * sizeof (*ip));
+	VMEM_CHECK (op, nsamples * sizeof (*op));
+
+	for (sample = 0; sample < nsamples; sample++)
+	  {
+	    int *p = &op[sample * 10 + portc->chnum];
+
+	    for (ch = 0; ch < portc->channels; ch++)
+	      {
+		*p++ = *ip++;
+	      }
+	  }
+      }
+      break;
+    }
+
+  oss_audio_outputintr (portc->dev, 1);
+}
+
+#ifdef DO_RIAA
+static __inline__ int32_t
+_riaa_sat31 (register int32_t a, register int32_t b)
+{
+  register int64_t v = (((int64_t) a) * b) + (1 << 30);
+  return (int32_t) (v >> 31);
+}
+#endif
+
+static void
+handle_recdev (envy24_devc * devc, envy24_portc * portc)
+{
+  int sample, nsamples, nbytes, ch;
+  dmap_t *dmap = audio_engines[portc->dev]->dmap_in;
+
+  if (portc->trigger_bits == 0 && devc->recording_started)
+    return;
+
+  nsamples = devc->hw_fragsamples;	/* Number of 32 bit samples */
+
+  nbytes = nsamples * portc->channels;
+
+  if (portc->bits & (AFMT_S16_LE | AFMT_S16_BE | AFMT_AC3))
+    nbytes *= 2;
+  else if (portc->bits & (AFMT_S32_LE | AFMT_S24_LE))
+    nbytes *= 4;
+
+  if (nbytes != dmap->fragment_size)
+    {
+      return;			/* Fragment size mismatch */
+    }
+
+  switch (portc->bits)
+    {
+    case AFMT_U8:
+      {
+	unsigned char *ip;
+	int *op;
+
+	ip = audio_engines[portc->dev]->dmap_in->dmabuf;
+	ip += (dmap_get_qtail (dmap) * dmap->fragment_size);
+	op = (int *) (devc->recbuf + devc->hw_rfragsize * devc->hw_recfrag);
+	VMEM_CHECK (ip, nsamples * sizeof (*ip));
+	VMEM_CHECK (op, nsamples * sizeof (*op));
+
+	for (sample = 0; sample < nsamples; sample++)
+	  {
+	    int *p = &op[sample * 12 + portc->chnum];
+
+	    for (ch = 0; ch < portc->channels; ch++)
+	      {
+		*ip++ = ((*p++) >> 24) ^ 0x80;
+	      }
+	  }
+      }
+      break;
+
+    case AFMT_S16_LE:
+#ifdef DO_RIAA
+      if (portc->riaa_filter)
+	{
+	  /* RIAA filtered version */
+	  short *ip;
+	  int *op;
+
+	  ip = (short *) (audio_engines[portc->dev]->dmap_in->dmabuf +
+			  (dmap_get_qtail (dmap) * dmap->fragment_size));
+	  op = (int *) (devc->recbuf + devc->hw_rfragsize * devc->hw_recfrag);
+
+	  VMEM_CHECK (ip, nsamples * sizeof (*ip));
+	  VMEM_CHECK (op, nsamples * sizeof (*op));
+
+	  for (ch = 0; ch < portc->channels; ch++)
+	    {
+	      int *p = &op[portc->chnum + ch];
+	      short *p2 = &ip[ch];
+	      riaa_t *ff = &portc->riaa_parms[ch];
+
+	      int32_t x1 = ff->x1, x2 = ff->x2, x3 = ff->x3,
+		y1 = ff->y1, y2 = ff->y2, y3 = ff->y3, x0, y0;
+
+	      for (sample = 0; sample < nsamples; sample++)
+		{
+		  int tmp = *p;
+		  p += 12;
+
+		  x0 = _riaa_sat31 (tmp, 0x4C30C30C);
+
+		  y0 = _riaa_sat31 (x0, 0xF38FB92F) +
+		    _riaa_sat31 (x1, 0xF2492994) +
+		    _riaa_sat31 (x2, 0x1AB82385) +
+		    _riaa_sat31 (x3, 0x023FB0F8) +
+		    (_riaa_sat31 (y1, 0x574DB88C) << 1) +
+		    _riaa_sat31 (y2, 0xF650F27D) +
+		    _riaa_sat31 (y3, 0xDACB84B9);
+
+		  x3 = x2;
+		  x2 = x1;
+		  x1 = x0;
+		  y3 = y2;
+		  y2 = y1;
+		  y1 = y0;
+
+		  tmp = -y0;
+
+		  *p2 = tmp >> 16;
+		  p2 += portc->channels;
+		}
+
+	      ff->x1 = x1;
+	      ff->x2 = x2;
+	      ff->x3 = x3;
+	      ff->y1 = y1;
+	      ff->y2 = y2;
+	      ff->y3 = y3;
+	    }
+	  /* RIAA filtered version */
+	}
+      else
+#endif
+	{
+	  short *ip;
+	  int *op;
+
+	  ip = (short *) (audio_engines[portc->dev]->dmap_in->dmabuf +
+			  (dmap_get_qtail (dmap) * dmap->fragment_size));
+	  op = (int *) (devc->recbuf + devc->hw_rfragsize * devc->hw_recfrag);
+
+	  VMEM_CHECK (ip, nsamples * sizeof (*ip));
+	  VMEM_CHECK (op, nsamples * sizeof (*op));
+	  for (sample = 0; sample < nsamples; sample++)
+	    {
+	      int *p = &op[sample * 12 + portc->chnum];
+
+	      for (ch = 0; ch < portc->channels; ch++)
+		{
+		  *ip++ = (*p++) >> 16;
+		}
+	    }
+	}
+      break;
+
+    case AFMT_S32_LE:
+      {
+	int *ip;
+	int *op;
+
+	ip = (int *) (audio_engines[portc->dev]->dmap_in->dmabuf +
+		      (dmap_get_qtail (dmap) * dmap->fragment_size));
+	op = (int *) (devc->recbuf + devc->hw_rfragsize * devc->hw_recfrag);
+
+	VMEM_CHECK (ip, nsamples * sizeof (*ip));
+	VMEM_CHECK (op, nsamples * sizeof (*op));
+	for (sample = 0; sample < nsamples; sample++)
+	  {
+	    int *p = &op[sample * 12 + portc->chnum];
+
+	    for (ch = 0; ch < portc->channels; ch++)
+	      {
+		*ip++ = *p++;
+	      }
+	  }
+      }
+      break;
+
+    case AFMT_S24_LE:
+      {
+	int *ip;
+	int *op;
+
+	ip = (int *) (audio_engines[portc->dev]->dmap_in->dmabuf +
+		      (dmap_get_qtail (dmap) * dmap->fragment_size));
+	op = (int *) (devc->recbuf + devc->hw_rfragsize * devc->hw_recfrag);
+
+	VMEM_CHECK (ip, nsamples * sizeof (*ip));
+	VMEM_CHECK (op, nsamples * sizeof (*op));
+	for (sample = 0; sample < nsamples; sample++)
+	  {
+	    int *p = &op[sample * 12 + portc->chnum];
+
+	    for (ch = 0; ch < portc->channels; ch++)
+	      {
+		*ip++ = *p++ >> 8;
+	      }
+	  }
+      }
+      break;
+    }
+
+  oss_audio_inputintr (portc->dev, 0);
+}
+
+static void
+tank_playback_data (envy24_devc * devc)
+{
+  int i, nc = devc->nr_outdevs;
+  envy24_portc *portc;
+  unsigned char *p;
+
+  p = devc->playbuf + devc->hw_playfrag * devc->hw_pfragsize;
+  VMEM_CHECK (p, devc->hw_pfragsize);
+  memset (p, 0, devc->hw_pfragsize);	/* Cleanup the fragment */
+
+  for (i = 0; i < nc; i++)
+    {
+      portc = &devc->play_portc[i];
+
+      if (!portc->open_mode)	/* Not opened */
+	continue;
+      handle_playdev (devc, portc, devc->hw_playfrag);
+    }
+
+  devc->hw_playfrag = (devc->hw_playfrag + 1) % devc->hw_nfrags;
+}
+
+static void
+handle_recording (envy24_devc * devc)
+{
+  int i;
+  envy24_portc *portc;
+  /* oss_native_word flags; */
+
+  /*
+   * TODO: Fix mutexes and move the inputintr/outputintr calls outside the
+   * mutex block.
+   */
+  /* MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); */
+  for (i = 0; i < devc->nr_indevs; i++)
+    {
+      portc = &devc->rec_portc[i];
+
+      if (!portc->open_mode)	/* Not opened */
+	continue;
+      handle_recdev (devc, portc);
+    }
+
+  devc->hw_recfrag = (devc->hw_recfrag + 1) % devc->hw_nfrags;
+  /* MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); */
+}
+
+extern int envy24d_get_buffer_pointer (int dev, dmap_t * dmap, int direction);
+
+static void
+mt_audio_intr (envy24_devc * devc)
+{
+  int status;
+
+#ifdef DO_TIMINGS
+  oss_timing_enter (DF_INTERRUPT);
+  oss_do_timing2 (DFLAG_PROFILE, "Envy24_audio_intr");
+#endif
+  status = INB (devc->osdev, devc->mt_base + 0x00);
+  if (devc->playback_started && (status & 0x01))	/* Playback interrupt */
+    {
+/* cmn_err(CE_CONT, "%d\n", GET_JIFFIES()); */
+      if (devc->direct_audio_opened & OPEN_WRITE)
+	{
+	  envy24d_playintr (devc);
+	}
+      else
+	{
+	  int ptr, qlen, i;
+
+	  ptr = INW (devc->osdev, devc->mt_base + 0x14);
+	  ptr = (devc->playbuffsize - ((ptr + 1) * 4)) / devc->hw_pfragsize;
+
+	  /* Find the number of current fragments in the hardware level buffer */
+	  qlen = 0;
+	  i = devc->hw_playfrag;
+
+	  while (qlen < 15 && i != ptr)
+	    {
+	      qlen++;
+	      i = (i + 1) % devc->hw_nfrags;
+	    }
+
+	  if (qlen != devc->writeahead)
+	    {
+	      tank_playback_data (devc);
+	    }
+
+	  if (devc->hw_playfrag == ptr)	/* Out of sync */
+	    {
+	      tank_playback_data (devc);	/* Try to catch the hardware pointer */
+	    }
+
+
+	  tank_playback_data (devc);
+	}
+    }
+
+  if (devc->recording_started && (status & 0x02))	/* Record interrupt */
+    {
+      if (devc->direct_audio_opened & OPEN_READ)
+	envy24d_recintr (devc);
+      else
+	handle_recording (devc);
+    }
+
+  OUTB (devc->osdev, status, devc->mt_base + 0x00);
+#ifdef DO_TIMINGS
+  oss_timing_leave (DF_INTERRUPT);
+  oss_do_timing2 (DFLAG_PROFILE, "Envy24_audio_intr done");
+#endif
+}
+
+static int
+envy24intr (oss_device_t * osdev)
+{
+  int status;
+  envy24_devc *devc;
+
+  devc = osdev->devc;
+
+  status = INB (devc->osdev, devc->ccs_base + 0x02);
+  if (status == 0)
+    return 0;
+
+  if (status & 0x80)		/* MIDI UART 1 */
+    if (devc->model_data->flags & MF_MIDI1)
+      uart401_irq (&devc->uart401devc1);
+
+  if (status & 0x20)		/* MIDI UART 2 */
+    if (devc->model_data->flags & MF_MIDI2)
+      uart401_irq (&devc->uart401devc2);
+
+  if (status & 0x10)
+    {
+/*cmn_err(CE_CONT, "%d/%d.", GET_JIFFIES(), envy24d_get_buffer_pointer(11, audio_engines[11]->dmap_out, DMODE_OUTPUT)); */
+      mt_audio_intr (devc);
+    }
+
+  OUTB (devc->osdev, status, devc->ccs_base + 0x02);	/* ACK */
+
+  return 1;
+}
+
+static void envy24_setup_pro_speed (envy24_devc * devc);
+static void envy24_setup_consumer_speed (envy24_devc * devc);
+
+void
+envy24_prepare_play_engine (envy24_devc * devc)
+{
+  int tmp, fragsize, buffsize;
+
+  if (devc->playback_prepared)
+    return;
+
+  /* Set S/PDIF sample rate indication */
+
+  if (devc->spdif_cbits[0] & 0x01)
+    envy24_setup_pro_speed (devc);
+  else
+    envy24_setup_consumer_speed (devc);
+
+  if (devc->model_data->flags & MF_SPDIF)
+    {
+      tmp = 0x80;
+
+      if (devc->ac3_mode)
+	tmp |= 0x40;		/* Audio mode off */
+
+      switch (devc->speed)
+	{
+	case 48000:
+	  tmp |= 0x01;
+	  break;
+	case 44100:
+	  tmp |= 0x02;
+	  break;
+	case 32000:
+	  tmp |= 0x03;
+	  break;
+	}
+
+      if (devc->model_data->auxdrv->spdif_set)
+	devc->model_data->auxdrv->spdif_set (devc, tmp);
+
+    }
+
+  if (devc->model_data->auxdrv->set_rate)
+    devc->model_data->auxdrv->set_rate (devc);
+  else
+    {
+      tmp = devc->speedbits;
+      if (devc->syncsource != SYNC_INTERNAL)
+	{
+	  tmp |= 0x10;		/* S/PDIF input clock select */
+	  if (devc->model_data->flags & MF_WCLOCK)	/* Has world clock too */
+	    {
+	      int cmd = envy24_read_cci (devc, 0x20);
+	      cmd |= 0x10;	/* S/PDIF */
+	      if (devc->syncsource == SYNC_WCLOCK)
+		cmd &= ~0x10;	/* World clock */
+	      envy24_write_cci (devc, 0x20, cmd);
+	    }
+	}
+      OUTB (devc->osdev, tmp, devc->mt_base + 0x01);
+    }
+
+  fragsize = devc->hw_pfragsize;
+  buffsize = devc->playbuffsize / 4 - 1;
+
+  PMEM_CHECK (devc->playbuf_phys, devc->playbuffsize);
+
+  OUTL (devc->osdev, devc->playbuf_phys, devc->mt_base + 0x10);	/* Base */
+  OUTW (devc->osdev, buffsize, devc->mt_base + 0x14);	/* Count */
+  OUTL (devc->osdev, devc->playbuf_phys, devc->mt_base + 0x10);	/* Base */
+  OUTW (devc->osdev, buffsize, devc->mt_base + 0x14);	/* Count */
+  OUTL (devc->osdev, devc->playbuf_phys, devc->mt_base + 0x10);	/* Base */
+  OUTW (devc->osdev, fragsize / 4 - 1, devc->mt_base + 0x16);	/* Interrupt rate */
+  OUTL (devc->osdev, devc->playbuf_phys, devc->mt_base + 0x10);	/* Base */
+
+  devc->playback_prepared = 1;
+  mixer_devs[devc->mixer_dev]->modify_counter++;
+}
+
+void
+envy24_launch_play_engine (envy24_devc * devc)
+{
+  /* Unmask playback interrupts */
+  OUTB (devc->osdev,
+	INB (devc->osdev, devc->mt_base + 0x00) & ~0x40,
+	devc->mt_base + 0x00);
+  OUTB (devc->osdev, INB (devc->osdev, devc->mt_base + 0x00) & ~0x40,
+	devc->mt_base + 0x00);
+  /* Kick it */
+  OUTB (devc->osdev, INB (devc->osdev, devc->mt_base + 0x18) | 0x01,
+	devc->mt_base + 0x18);
+  devc->playback_started = 1;
+
+  if (devc->model_data->auxdrv->set_rate)
+    devc->model_data->auxdrv->set_rate (devc);
+}
+
+static void
+start_playback (envy24_devc * devc)
+{
+  devc->hw_playfrag = 0;
+
+#ifdef DO_TIMINGS
+  oss_do_timing ("Envy24: Start playback");
+#endif
+  tank_playback_data (devc);
+  tank_playback_data (devc);
+  if (devc->writeahead == 2)
+    tank_playback_data (devc);
+
+  envy24_prepare_play_engine (devc);
+  envy24_launch_play_engine (devc);
+}
+
+void
+envy24_stop_playback (envy24_devc * devc)
+{
+#ifdef DO_TIMINGS
+  oss_do_timing ("Envy24: Stop playback");
+#endif
+  memset (devc->playbuf, 0, devc->playbuffsize);
+  /*
+   * Give the engine time to eat some silent samples 
+   * This makes the corresponding digital mixer inputs to drop to 0
+   * which decreases noise in the monitor outputs.
+   */
+  OUTB (devc->osdev, INB (devc->osdev, devc->mt_base + 0x18) & ~0x01,
+	devc->mt_base + 0x18);
+  OUTB (devc->osdev, INB (devc->osdev, devc->mt_base + 0x18) & ~0x01,
+	devc->mt_base + 0x18);
+
+  /* Mask playback interrupts */
+  OUTB (devc->osdev,
+	INB (devc->osdev, devc->mt_base + 0x00) | 0x40, devc->mt_base + 0x00);
+  devc->playback_started = 0;
+  devc->playback_prepared = 0;
+}
+
+void
+envy24_start_recording (envy24_devc * devc)
+{
+  int tmp;
+
+  devc->hw_recfrag = 0;
+  OUTB (devc->osdev, INB (devc->osdev, devc->mt_base + 0x18) & ~0x04,
+	devc->mt_base + 0x18);
+  OUTB (devc->osdev, INB (devc->osdev, devc->mt_base + 0x18) & ~0x04,
+	devc->mt_base + 0x18);
+  oss_udelay (20);
+
+  if (devc->model_data->flags & MF_SPDIF)
+    {
+      tmp = 0x80;
+
+      switch (devc->speed)
+	{
+	case 48000:
+	  tmp |= 0x01;
+	  break;
+	case 44100:
+	  tmp |= 0x02;
+	  break;
+	case 32000:
+	  tmp |= 0x03;
+	  break;
+	}
+
+      if (devc->model_data->auxdrv->spdif_set)
+	devc->model_data->auxdrv->spdif_set (devc, tmp);
+
+    }
+
+  tmp = devc->speedbits;
+  if (devc->syncsource != SYNC_INTERNAL)
+    {
+      tmp |= 0x10;		/* S/PDIF input clock select */
+      if (devc->model_data->flags & MF_WCLOCK)	/* Has world clock too */
+	{
+	  int cmd = envy24_read_cci (devc, 0x20);
+	  cmd |= 0x10;		/* S/PDIF */
+	  if (devc->syncsource == SYNC_WCLOCK)
+	    cmd &= ~0x10;	/* World clock */
+	  envy24_write_cci (devc, 0x20, cmd);
+	}
+    }
+
+  OUTB (devc->osdev, tmp, devc->mt_base + 0x01);
+
+  if (devc->model_data->auxdrv->set_rate)
+    devc->model_data->auxdrv->set_rate (devc);
+
+  PMEM_CHECK (devc->recbuf_phys, devc->recbuffsize);
+
+  OUTL (devc->osdev, devc->recbuf_phys, devc->mt_base + 0x20);	/* Base */
+  oss_udelay (20);
+  OUTL (devc->osdev, devc->recbuf_phys, devc->mt_base + 0x20);	/* Base */
+  oss_udelay (20);
+  OUTW (devc->osdev, devc->recbuffsize / 4 - 1, devc->mt_base + 0x24);	/* Count */
+  OUTL (devc->osdev, devc->recbuf_phys, devc->mt_base + 0x20);	/* Base */
+  oss_udelay (60);
+  OUTW (devc->osdev, devc->hw_rfragsize / 4 - 1, devc->mt_base + 0x26);	/* Interrupt rate */
+
+  oss_udelay (60);
+}
+
+void
+envy24_launch_recording (envy24_devc * devc)
+{
+
+#if 1
+  /* Unmask recording interrupts */
+  OUTB (devc->osdev,
+	INB (devc->osdev, devc->mt_base + 0x00) & ~0x80,
+	devc->mt_base + 0x00);
+
+#endif
+  /* Kick it */
+  OUTB (devc->osdev, INB (devc->osdev, devc->mt_base + 0x18) | 0x04,
+	devc->mt_base + 0x18);
+  devc->recording_started = 1;
+  mixer_devs[devc->mixer_dev]->modify_counter++;
+
+}
+
+void
+envy24_stop_recording (envy24_devc * devc)
+{
+  OUTB (devc->osdev, INB (devc->osdev, devc->mt_base + 0x18) & ~0x04,
+	devc->mt_base + 0x18);
+  OUTB (devc->osdev, INB (devc->osdev, devc->mt_base + 0x18) & ~0x04,
+	devc->mt_base + 0x18);
+
+  /* Mask recording interrupts */
+  OUTB (devc->osdev,
+	INB (devc->osdev, devc->mt_base + 0x00) | 0x80, devc->mt_base + 0x00);
+  devc->recording_started = 0;
+  memset (devc->recbuf, 0, devc->recbuffsize);
+}
+
+/*
+ * Audio entrypoint routines
+ */
+
+int
+envy24_audio_set_rate (int dev, int arg)
+{
+  envy24_devc *devc = audio_engines[dev]->devc;
+#if 1
+  int i = 0, ix = -1, df, best = 0x7fffffff;
+  oss_native_word flags;
+
+  if (arg <= 0)
+    return devc->speed;
+
+  MUTEX_ENTER_IRQDISABLE (devc->mutex, flags);
+  if (devc->recording_started || devc->playback_started)
+    {
+      DDB (cmn_err (CE_CONT,
+		    "Requested sampling rate(1) on device %d was %d, got %d\n",
+		    dev, arg, devc->speed));
+      MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+      return devc->speed;
+    }
+
+  if ((devc->open_inputs + devc->open_outputs) > 1)
+    {
+      DDB (cmn_err (CE_CONT,
+		    "Requested sampling rate(2) on device %d was %d, got %d\n",
+		    dev, arg, devc->speed));
+      MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+      return devc->speed;
+    }
+
+  if (devc->ratelock)
+    {
+      DDB (cmn_err (CE_CONT,
+		    "Requested sampling rate(3) on device %d was %d, got %d\n",
+		    dev, arg, devc->speed));
+      MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+      return devc->speed;
+    }
+
+/* This is the only open device file so change the speed */
+
+  i = 0;
+
+  while (speed_tab[i].speed != -1)
+    {
+      df = arg - speed_tab[i].speed;
+      if (df < 0)
+	df = -df;
+
+      if (df < best)
+	{
+	  best = df;
+	  ix = i;
+	  if (df == 0)
+	    break;
+	}
+
+      i++;
+    }
+
+  if (ix == -1)			/* No matching rate */
+    {
+      DDB (cmn_err (CE_CONT,
+		    "Requested sampling rate(4) on device %d was %d, got %d\n",
+		    dev, arg, devc->speed));
+      MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+      return devc->speed;
+    }
+
+  devc->speed = speed_tab[ix].speed;
+  devc->speedbits = speed_tab[ix].speedbits;
+#endif
+  if (devc->speed != arg)
+    {
+      DDB (cmn_err (CE_CONT,
+		    "Requested sampling rate(5) on device %d was %d, got %d\n",
+		    dev, arg, devc->speed));
+      MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+      return devc->speed;
+    }
+  DDB (cmn_err (CE_CONT, "Sampling rate set to %d\n", devc->speed));
+  MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+  return devc->speed;
+}
+
+static void
+update_fragments (envy24_portc * portc)
+{
+  int nsamples, nbytes, dev = portc->dev;
+  envy24_devc *devc = audio_engines[dev]->devc;
+
+  nsamples = devc->hw_fragsamples;	/* Number of 32 bit samples */
+
+  nbytes = nsamples * portc->channels;
+
+  if (portc->bits & (AFMT_S16_LE | AFMT_S16_BE | AFMT_AC3))
+    {
+      nbytes *= 2;
+    }
+  else if (portc->bits & (AFMT_S32_LE | AFMT_S24_LE))
+    nbytes *= 4;
+
+  audio_engines[dev]->min_block = nbytes;
+  audio_engines[dev]->max_block = nbytes;
+}
+
+static short
+envy24_audio_set_channels (int dev, short arg)
+{
+  envy24_portc *portc = audio_engines[dev]->portc;
+  envy24_devc *devc = audio_engines[dev]->devc;
+  int i, nc = devc->nr_play_channels;
+  oss_native_word flags;
+
+  if (envy24_virtualout)
+    nc = 10;
+
+  if (arg <= portc->channels)
+    return portc->channels;
+
+  /* Force mono->stereo conversion if in skip=2 mode */
+  if (devc->skipdevs == 2 && arg < 2)
+    arg = 2;
+
+  if (envy24_force_mono)
+    arg = 1;
+
+  if (portc->direction == DIR_INPUT)
+    {
+      if ((portc->chnum + arg) > devc->nr_rec_channels)
+	return portc->channels;
+      MUTEX_ENTER_IRQDISABLE (devc->mutex, flags);
+      for (i = portc->channels; i < arg; i++)
+	if (devc->rec_channel_mask & (1 << (portc->chnum + i)))
+	  {
+	    MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+	    return portc->channels;
+	  }
+      for (i = portc->channels; i < arg; i++)
+	devc->rec_channel_mask |= (1 << (portc->chnum + i));
+      MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+    }
+  else
+    {
+      if ((portc->chnum + arg) > nc)
+	return portc->channels;
+      MUTEX_ENTER_IRQDISABLE (devc->mutex, flags);
+      for (i = portc->channels; i < arg; i++)
+	if (devc->play_channel_mask & (1 << (portc->chnum + i)))
+	  {
+	    MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+	    return portc->channels;
+	  }
+      for (i = portc->channels; i < arg; i++)
+	devc->play_channel_mask |= (1 << (portc->chnum + i));
+      MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+    }
+
+  portc->channels = arg;
+  update_fragments (portc);
+
+  return portc->channels;
+}
+
+static unsigned int
+envy24_audio_set_format (int dev, unsigned int arg)
+{
+  envy24_portc *portc = audio_engines[dev]->portc;
+
+  if (arg == 0)
+    return portc->bits;
+
+  if (!(arg & audio_engines[dev]->oformat_mask))
+    return portc->bits = AFMT_S16_LE;
+
+  portc->bits = arg;
+
+  if (arg == AFMT_AC3)
+    {
+      envy24_audio_set_channels (dev, 2);
+    }
+
+  update_fragments (portc);
+
+  return portc->bits;
+}
+
+static int
+envy24_audio_ioctl (int dev, unsigned int cmd, ioctl_arg arg)
+{
+  envy24_devc *devc = audio_engines[dev]->devc;
+  envy24_portc *portc = audio_engines[dev]->portc;
+  oss_native_word flags;
+  int rt;
+
+  if (arg == NULL)
+    return OSS_EINVAL;
+
+  switch (cmd)
+    {
+    case SNDCTL_DSP_GET_RECSRC:
+    case SNDCTL_DSP_SET_RECSRC:
+    case SNDCTL_DSP_GET_PLAYTGT:
+    case SNDCTL_DSP_SET_PLAYTGT:
+      return *arg = 0;
+      break;
+
+    case SNDCTL_DSP_GET_RECSRC_NAMES:
+      return oss_encode_enum ((oss_mixer_enuminfo *) arg, portc->name, 0);
+      break;
+
+    case SNDCTL_DSP_GET_PLAYTGT_NAMES:
+      return oss_encode_enum ((oss_mixer_enuminfo *) arg, portc->name, 0);
+      break;
+
+    case SNDCTL_DSP_GET_CHNORDER:
+      *(oss_uint64_t *) arg = CHNORDER_UNDEF;
+      return 0;
+    }
+
+  if (devc->model_data->auxdrv->spdif_ioctl == NULL)
+    return OSS_EINVAL;
+
+  MUTEX_ENTER_IRQDISABLE (devc->mutex, flags);
+  rt = devc->model_data->auxdrv->spdif_ioctl (devc, dev, cmd, arg);
+  MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+  return rt;
+}
+
+static void envy24_audio_trigger (int dev, int state);
+
+static void
+envy24_audio_reset (int dev)
+{
+#ifdef DO_TIMINGS
+  oss_do_timing ("Envy24: Reset audio");
+#endif
+  envy24_audio_trigger (dev, 0);
+}
+
+#define WriteCsByte(devc, b, v) (devc)->spdif_cbits[b]=(v)
+#define ReadCsByte(devc, b) (devc)->spdif_cbits[b]
+
+static __inline__ void
+WriteCsField (envy24_devc * devc, unsigned char bByteNum,
+	      unsigned short bMask, unsigned short bBits)
+{
+  /* Get current reg value. */
+  unsigned char bTemp = ReadCsByte (devc, bByteNum);
+
+  /* Clear field to be written. */
+  bTemp &= ~(bMask);
+
+  /* Set new values. */
+  WriteCsByte (devc, bByteNum, (unsigned char) (bTemp | (bBits & bMask)));
+}
+
+static void
+envy24_setup_pro_speed (envy24_devc * devc)
+{
+
+  switch (devc->speed)
+    {
+    case 32000:
+      WriteCsField (devc, 0, 0xc0, 0xc0);
+      break;
+
+    case 44100:
+      WriteCsField (devc, 0, 0xc0, 0x40);
+      break;
+
+    case 48000:
+      WriteCsField (devc, 0, 0xc0, 0x80);
+      break;
+
+    default:
+      WriteCsField (devc, 0, 0xc0, 0x00);
+      break;
+    }
+}
+
+static void
+setup_pro_mode (envy24_devc * devc)
+{
+  devc->spdif_cbits[0] |= 0x01;	/* Pro mode */
+  devc->spdif_cbits[2] |= 0x2c;	/* 24-bit data word */
+
+  envy24_setup_pro_speed (devc);
+}
+
+static void
+envy24_setup_consumer_speed (envy24_devc * devc)
+{
+
+  /*
+   * Set the sampling rate indication
+   */
+  if (devc->ac3_mode)
+    WriteCsField (devc, 0, 0x02, 0x02);	/* 1:1 = 1 */
+  else
+    WriteCsField (devc, 0, 0x02, 0x00);	/* 1:1 = 0 */
+
+  switch (devc->speed)
+    {
+    case 22050L:
+      WriteCsField (devc, 0, 0xC0, 0x00);	/* 7:6 = 00 */
+      WriteCsField (devc, 3, 0x0F, 0x00);	/* 3:0 = 0000 */
+      WriteCsField (devc, 4, 0x0F, 0x09);	/* 3:0 = 1001 */
+      break;
+    case 32000L:
+      WriteCsField (devc, 0, 0xC0, 0xC0);	/* 7:6 = 11 */
+      WriteCsField (devc, 3, 0x0F, 0x03);	/* 3:0 = 0011 */
+      WriteCsField (devc, 4, 0x0F, 0x00);	/* 3:0 = 0000 */
+      break;
+    case 44100L:
+      WriteCsField (devc, 0, 0xC0, 0x40);	/* 7:6 = 01 */
+      WriteCsField (devc, 3, 0x0F, 0x00);	/* 3:0 = 0000 */
+      WriteCsField (devc, 4, 0x0F, 0x00);	/* 3:0 = 0000 */
+      break;
+    case 48000L:
+      WriteCsField (devc, 0, 0xC0, 0x80);	/* 7:6 = 10 */
+      WriteCsField (devc, 3, 0x0F, 0x02);	/* 3:0 = 0010 */
+      WriteCsField (devc, 4, 0x0F, 0x00);	/* 3:0 = 0000 */
+      break;
+    case 88200L:
+      WriteCsField (devc, 0, 0xC0, 0x00);	/* 7:6 = 00 */
+      WriteCsField (devc, 3, 0x0F, 0x00);	/* 3:0 = 0000 */
+      WriteCsField (devc, 4, 0x0F, 0x05);	/* 3:0 = 0101 */
+      break;
+    case 96000L:
+      WriteCsField (devc, 0, 0xC0, 0x00);	/* 7:6 = 00 */
+      WriteCsField (devc, 3, 0x0F, 0x00);	/* 3:0 = 0000 */
+      WriteCsField (devc, 4, 0x0F, 0x04);	/* 3:0 = 0100 */
+      break;
+    default:
+      WriteCsField (devc, 0, 0xC0, 0x00);	/* 7:6 = 00 */
+      WriteCsField (devc, 3, 0x0F, 0x00);	/* 3:0 = 0000 */
+      WriteCsField (devc, 4, 0x0F, 0x00);	/* 3:0 = 0000 */
+      break;
+    }
+}
+
+static void
+setup_consumer_mode (envy24_devc * devc)
+{
+  WriteCsByte (devc, 0, ReadCsByte (devc, 0) & ~(0x02));	/* Set audio mode */
+  WriteCsByte (devc, 0, ReadCsByte (devc, 0) & ~(0x38));	/* Set no emphasis */
+
+  WriteCsByte (devc, 0, ReadCsByte (devc, 0) & ~(0x04));	/* Set "original" */
+  WriteCsByte (devc, 1, ReadCsByte (devc, 1) | (0x80));	/* Set "original" */
+
+  envy24_setup_consumer_speed (devc);
+}
+
+static void
+setup_spdif_control (envy24_devc * devc)
+{
+/*  unsigned char *cbits; */
+
+  memset (devc->spdif_cbits, 0, sizeof (devc->spdif_cbits));
+
+/*  cbits = devc->spdif_cbits; */
+
+  if (devc->spdif_pro_mode)
+    {
+      setup_pro_mode (devc);
+    }
+  else
+    {
+      setup_consumer_mode (devc);
+    }
+}
+
+/*ARGSUSED*/ 
+static int
+envy24_audio_open (int dev, int mode, int open_flags)
+{
+  envy24_portc *portc = audio_engines[dev]->portc;
+  envy24_devc *devc = audio_engines[dev]->devc;
+  oss_native_word flags;
+
+  mode |= ADEV_NOVIRTUAL;
+
+  if (devc->playbuf == NULL || devc->recbuf == NULL)
+    {
+      cmn_err (CE_WARN, "No DMA buffer\n");
+      return OSS_ENOSPC;
+    }
+
+  MUTEX_ENTER_IRQDISABLE (devc->mutex, flags);
+  if (portc->open_mode != 0 || devc->direct_audio_opened != 0)
+    {
+      MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+      return OSS_EBUSY;
+    }
+
+  if (portc->direction == DIR_INPUT)
+    {
+      if (devc->rec_channel_mask & (1 << portc->chnum))
+	{
+	  MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+	  return OSS_EBUSY;
+	}
+      devc->rec_channel_mask |= (1 << portc->chnum);
+    }
+  else
+    {
+      if (devc->play_channel_mask & (1 << portc->chnum))
+	{
+	  MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+	  return OSS_EBUSY;
+	}
+      devc->play_channel_mask |= (1 << portc->chnum);
+    }
+
+  portc->open_mode = mode;
+  portc->channels = 1;
+  if (devc->skipdevs == 2)
+    portc->channels = 2;
+  portc->pcm_qlen = 0;
+  if (portc->direction == DIR_INPUT)
+    {
+      if (devc->open_inputs++ == 0 && devc->open_outputs == 0)
+	{
+	  devc->speed = speed_tab[devc->pending_speed_sel].speed;
+	  devc->speedbits = speed_tab[devc->pending_speed_sel].speedbits;
+	}
+    }
+  else
+    {
+      if (devc->open_inputs == 0 && devc->open_outputs++ == 0)
+	{
+	  if (portc->flags & PORTC_SPDOUT)
+	    {
+	      setup_spdif_control (devc);
+	    }
+
+	  devc->speed = speed_tab[devc->pending_speed_sel].speed;
+	  devc->speedbits = speed_tab[devc->pending_speed_sel].speedbits;
+	}
+    }
+#if 1
+  if (devc->use_src)
+    {
+      /* SRC stuff */
+      audio_engines[dev]->flags |= ADEV_FIXEDRATE;
+      audio_engines[dev]->fixed_rate = devc->speed;
+      audio_engines[dev]->min_rate = devc->speed;
+      audio_engines[dev]->max_rate = devc->speed;
+    }
+  else
+    {
+      audio_engines[dev]->flags &= ~ADEV_FIXEDRATE;
+      audio_engines[dev]->fixed_rate = 0;
+      audio_engines[dev]->min_rate = 8000;
+      audio_engines[dev]->max_rate = 96000;
+    }
+#endif
+  MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+
+  return 0;
+}
+
+/*ARGSUSED*/ 
+static void
+envy24_audio_close (int dev, int mode)
+{
+  envy24_devc *devc = audio_engines[dev]->devc;
+  envy24_portc *portc = audio_engines[dev]->portc;
+  oss_native_word flags;
+
+  int i;
+
+  envy24_audio_reset (dev);
+
+  MUTEX_ENTER_IRQDISABLE (devc->mutex, flags);
+  portc->open_mode = 0;
+  if (portc->flags & PORTC_SPDOUT)
+    devc->ac3_mode = 0;
+  if (portc->direction == DIR_INPUT)
+    {
+      devc->open_inputs--;
+      for (i = 0; i < portc->channels; i++)
+	devc->rec_channel_mask &= ~(1 << (portc->chnum + i));
+    }
+  else
+    {
+      devc->open_outputs--;
+      for (i = 0; i < portc->channels; i++)
+	devc->play_channel_mask &= ~(1 << (portc->chnum + i));
+    }
+  MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+}
+
+/*ARGSUSED*/ 
+static void
+envy24_audio_output_block (int dev, oss_native_word buf, int count,
+			   int fragsize, int intrflag)
+{
+}
+
+/*ARGSUSED*/ 
+static void
+envy24_audio_start_input (int dev, oss_native_word buf, int count,
+			  int fragsize, int intrflag)
+{
+}
+
+static int
+envy24_sync_control (int dev, int event, int mode)
+{
+  envy24_devc *devc = audio_engines[dev]->devc;
+  envy24_portc *portc = audio_engines[dev]->portc;
+
+  if (event == SYNC_PREPARE)
+    {
+      if (mode & PCM_ENABLE_OUTPUT)
+	{
+	  if (!devc->playback_prepared)
+	    devc->hw_playfrag = 0;
+	  handle_playdev (devc, portc, devc->hw_playfrag);
+	  handle_playdev (devc, portc, devc->hw_playfrag + 1);
+	  if (devc->writeahead == 2)
+	    handle_playdev (devc, portc, devc->hw_playfrag + 2);
+	  envy24_prepare_play_engine (devc);
+	  portc->trigger_bits |= PCM_ENABLE_OUTPUT;
+	}
+
+      if (mode & PCM_ENABLE_INPUT)
+	{
+	  if (devc->active_inputs == 0)
+	    {
+	      envy24_start_recording (devc);
+	    }
+	  portc->trigger_bits |= PCM_ENABLE_INPUT;
+	}
+      return 0;
+    }
+
+  if (event == SYNC_TRIGGER)
+    {
+      if (mode & PCM_ENABLE_OUTPUT)
+	{
+	  envy24_prepare_play_engine (devc);	/* Just to make sure */
+	  devc->hw_playfrag = 1 + devc->writeahead;
+	  if (devc->active_outputs++ == 0)
+	    envy24_launch_play_engine (devc);
+	}
+
+      if (mode & PCM_ENABLE_INPUT)
+	{
+	  if (devc->active_inputs++ == 0)
+	    {
+	      devc->hw_recfrag = 0;
+	      envy24_launch_recording (devc);
+	    }
+	}
+      return 0;
+    }
+
+  return OSS_EIO;
+}
+
+static void
+envy24_audio_trigger (int dev, int state)
+{
+  int changed;
+  oss_native_word flags;
+
+  envy24_portc *portc = audio_engines[dev]->portc;
+  envy24_devc *devc = audio_engines[dev]->devc;
+
+  MUTEX_ENTER_IRQDISABLE (devc->mutex, flags);
+  changed = state ^ portc->trigger_bits;
+
+  if (portc->direction == DIR_OUTPUT && (changed & PCM_ENABLE_OUTPUT))
+    {
+      if (state & PCM_ENABLE_OUTPUT)
+	{
+#ifdef DO_TIMINGS
+	  oss_do_timing ("Envy24: Trigger start output");
+#endif
+	  portc->trigger_bits = state;
+	  if (devc->active_outputs++ == 0)
+	    start_playback (devc);
+	}
+      else
+	{
+#ifdef DO_TIMINGS
+	  oss_do_timing ("Envy24: Trigger stop output");
+#endif
+	  portc->trigger_bits = state;
+	  if (--devc->active_outputs == 0)
+	    envy24_stop_playback (devc);
+	}
+    }
+
+  if (portc->direction == DIR_INPUT && (changed & PCM_ENABLE_INPUT))
+    {
+      if (state & PCM_ENABLE_INPUT)
+	{
+	  portc->trigger_bits = state;
+	  if (devc->active_inputs++ == 0)
+	    {
+	      envy24_start_recording (devc);
+	      envy24_launch_recording (devc);
+	    }
+	}
+      else
+	{
+	  if (--devc->active_inputs == 0)
+	    envy24_stop_recording (devc);
+	  portc->trigger_bits = state;
+	}
+    }
+
+  portc->trigger_bits = state;
+  MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+}
+
+/*ARGSUSED*/ 
+static int
+envy24_audio_prepare_for_input (int dev, int bsize, int bcount)
+{
+  int nsamples, nbytes;
+
+  envy24_portc *portc = audio_engines[dev]->portc;
+  envy24_devc *devc = audio_engines[dev]->devc;
+  oss_native_word flags;
+
+  if (audio_engines[dev]->flags & ADEV_NOINPUT)
+    return OSS_EACCES;
+
+  nsamples = devc->hw_fragsamples;	/* Number of 32 bit samples */
+
+  nbytes = nsamples * portc->channels;
+
+  MUTEX_ENTER_IRQDISABLE (devc->mutex, flags);
+#ifdef DO_RIAA
+  memset (portc->riaa_parms, 0, sizeof (portc->riaa_parms));
+  if (portc->riaa_filter)
+    cmn_err (CE_CONT, "oss: RIAA filter activated for /dev/dsp%d\n", dev);
+#endif
+
+  if (portc->bits & (AFMT_S16_LE | AFMT_S16_BE | AFMT_AC3))
+    {
+      nbytes *= 2;
+    }
+  else if (portc->bits & (AFMT_S32_LE | AFMT_S24_LE))
+    nbytes *= 4;
+
+  if (nbytes != bsize)
+    {
+      dmap_p dmap = audio_engines[dev]->dmap_in;
+      dmap->fragment_size = bsize = nbytes;
+      dmap->bytes_in_use = dmap->fragment_size * dmap->nfrags;
+      if (dmap->bytes_in_use > dmap->buffsize)
+	{
+	  dmap->nfrags = dmap->buffsize / dmap->fragment_size;
+	  dmap->bytes_in_use = dmap->nfrags * dmap->fragment_size;
+	}
+    }
+  MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+  return 0;
+}
+
+/*ARGSUSED*/ 
+static int
+envy24_audio_prepare_for_output (int dev, int bsize, int bcount)
+{
+  int nsamples, nbytes;
+  oss_native_word flags;
+
+  envy24_portc *portc = audio_engines[dev]->portc;
+  envy24_devc *devc = audio_engines[dev]->devc;
+
+  if (audio_engines[dev]->flags & ADEV_NOOUTPUT)
+    return OSS_EACCES;
+
+  nsamples = devc->hw_fragsamples;	/* Number of 32 bit samples */
+
+  nbytes = nsamples * portc->channels;
+
+  if (portc->flags & PORTC_SPDOUT)
+    if (portc->bits == AFMT_AC3)
+      devc->ac3_mode = 1;
+
+  if (portc->bits & (AFMT_S16_LE | AFMT_S16_BE | AFMT_AC3))
+    {
+      nbytes *= 2;
+    }
+  else if (portc->bits & (AFMT_S32_LE | AFMT_S32_BE))
+    nbytes *= 4;
+
+  MUTEX_ENTER_IRQDISABLE (devc->mutex, flags);
+  if (nbytes != bsize)
+    {
+      dmap_p dmap = audio_engines[dev]->dmap_out;
+      cmn_err (CE_CONT, "Fragment size mismatch: hw=%d, sw=%d\n",
+	       nbytes, bsize);
+      cmn_err (CE_NOTE,
+	       "Application bug detected. Fix ioctl() calling order\n");
+
+      oss_audio_set_error (dev, E_PLAY,
+			   OSSERR (1012, "Wrong ioctl call order"), 0);
+      /*
+       * Errordesc: The envy24 driver requires that number of channels, sample format and
+       * sampling rate are set before calling any ioctl call that may lock
+       * the fragment size prematurely. In such case the driver cannot change the
+       * fragment size to value that is suitable for the device.
+       *
+       * Please use the recommended ioctl call order defined in
+       * http://manuals.opensound.com/developer/callorder.html.
+       */
+      dmap->fragment_size = bsize = nbytes;
+      dmap->bytes_in_use = dmap->fragment_size * dmap->nfrags;
+      if (dmap->bytes_in_use > dmap->buffsize)
+	{
+	  dmap->nfrags = dmap->buffsize / dmap->fragment_size;
+	  dmap->bytes_in_use = dmap->nfrags * dmap->fragment_size;
+	}
+
+      MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+      return OSS_EIO;
+    }
+  MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+  return 0;
+}
+
+/*ARGSUSED*/ 
+static int
+envy24_alloc_buffer (int dev, dmap_t * dmap, int direction)
+{
+  envy24_devc *devc = audio_engines[dev]->devc;
+
+  if (dmap->dmabuf != NULL)
+    return 0;
+
+#if 0
+/*
+ * Ignore the direction parameter since it's missleading. Instead use the
+ * ADEV_NOINPUT/ADEV_NOOUTPUT flag.
+ */
+
+  if (audio_engines[dev]->flags & ADEV_NOINPUT)
+    direction = OPEN_WRITE;
+  else
+    direction = OPEN_READ;
+#endif
+
+  dmap->buffsize = devc->skipdevs * DEV_BUFSIZE;
+  dmap->dmabuf_phys = 0;
+  dmap->dmabuf = KERNEL_MALLOC (dmap->buffsize);
+
+  if (dmap->dmabuf == NULL)
+    {
+      cmn_err (CE_WARN, "Failed to allocate a DMA buffer\n");
+      return OSS_ENOSPC;
+    }
+  memset (dmap->dmabuf, 0, dmap->buffsize);
+  return 0;
+}
+
+/*ARGSUSED*/ 
+static int
+envy24_free_buffer (int dev, dmap_t * dmap, int direction)
+{
+  if (dmap->dmabuf == NULL)
+    return 0;
+#if 1
+  KERNEL_FREE (dmap->dmabuf);
+#endif
+  dmap->dmabuf = NULL;
+  return 0;
+}
+
+static int
+envy24_check_input (int dev)
+{
+  envy24_devc *devc = audio_engines[dev]->devc;
+
+  if (!devc->recording_started)
+    return 0;
+
+  cmn_err (CE_NOTE, "Input timed out.\n");
+  return OSS_EIO;
+}
+
+static int
+envy24_check_output (int dev)
+{
+  envy24_devc *devc = audio_engines[dev]->devc;
+
+  if (!devc->playback_started)
+    return 0;
+
+  cmn_err (CE_NOTE, "Output timed out\n");
+  return OSS_EIO;
+}
+
+static int
+envy24_local_qlen (int dev)
+{
+  envy24_portc *portc = audio_engines[dev]->portc;
+
+  return portc->pcm_qlen * audio_engines[dev]->dmap_out->fragment_size;
+}
+
+static const audiodrv_t envy24_audio_driver = {
+  envy24_audio_open,
+  envy24_audio_close,
+  envy24_audio_output_block,
+  envy24_audio_start_input,
+  envy24_audio_ioctl,
+  envy24_audio_prepare_for_input,
+  envy24_audio_prepare_for_output,
+  envy24_audio_reset,
+  envy24_local_qlen,
+  NULL,
+  NULL,
+  NULL,
+  envy24_audio_trigger,
+  envy24_audio_set_rate,
+  envy24_audio_set_format,
+  envy24_audio_set_channels,
+  NULL,
+  NULL,
+  envy24_check_input,
+  envy24_check_output,
+  envy24_alloc_buffer,
+  envy24_free_buffer,
+  NULL,
+  NULL,
+  NULL,				/* envy24_get_buffer_pointer */
+  NULL,				/* calibrate_speed */
+  envy24_sync_control
+};
+
+/*ARGSUSED*/ 
+static int
+envy24_mixer_ioctl (int dev, int audiodev, unsigned int cmd, ioctl_arg arg)
+{
+  extern int envy24_realencoder_hack;
+
+  if (!envy24_realencoder_hack)
+    {
+      if (cmd == SOUND_MIXER_READ_DEVMASK ||
+	  cmd == SOUND_MIXER_READ_RECMASK || cmd == SOUND_MIXER_READ_RECSRC ||
+	  cmd == SOUND_MIXER_READ_STEREODEVS)
+	return *arg = 0;
+    }
+
+  if (cmd == SOUND_MIXER_READ_DEVMASK ||
+      cmd == SOUND_MIXER_READ_RECMASK || cmd == SOUND_MIXER_READ_RECSRC ||
+      cmd == SOUND_MIXER_READ_STEREODEVS)
+    return *arg =
+      SOUND_MASK_LINE | SOUND_MASK_PCM | SOUND_MASK_MIC |
+      SOUND_MASK_VOLUME | SOUND_MASK_CD;
+
+  if (cmd == SOUND_MIXER_READ_VOLUME || cmd == SOUND_MIXER_READ_PCM ||
+      cmd == SOUND_MIXER_READ_LINE || cmd == SOUND_MIXER_READ_MIC ||
+      cmd == SOUND_MIXER_READ_CD || cmd == MIXER_READ (SOUND_MIXER_DIGITAL1))
+    return *arg = 100 | (100 << 8);
+  if (cmd == SOUND_MIXER_WRITE_VOLUME || cmd == SOUND_MIXER_WRITE_PCM ||
+      cmd == SOUND_MIXER_WRITE_LINE || cmd == SOUND_MIXER_READ_MIC ||
+      cmd == SOUND_MIXER_WRITE_CD ||
+      cmd == MIXER_WRITE (SOUND_MIXER_DIGITAL1))
+    return *arg = 100 | (100 << 8);
+  if (cmd == SOUND_MIXER_READ_CAPS)
+    return *arg = SOUND_CAP_EXCL_INPUT;
+  if (cmd == SOUND_MIXER_PRIVATE1)
+    return *arg = 0;
+  return OSS_EINVAL;
+}
+
+static int
+envy24_set_control (int dev, int ctrl, unsigned int cmd, int value)
+{
+  envy24_devc *devc = mixer_devs[dev]->devc;
+
+  if (cmd == SNDCTL_MIX_READ)
+    switch (ctrl)
+      {
+      case 1:
+	return devc->pending_speed_sel;
+	break;
+
+      case 2:
+	return devc->syncsource;
+	break;
+
+      case 3:
+	return devc->use_src;
+	break;
+
+      case 4:
+	{
+	  int tmp = envy24_read_cci (devc, 0x20);
+	  return !!(tmp & 0x10);
+	}
+	break;
+
+      case 5:
+	return devc->ratelock;
+	break;
+
+      case 6:
+	return devc->speed;
+	break;
+
+      case 7:
+	return devc->sync_locked =
+	  devc->model_data->auxdrv->get_locked_status (devc);
+
+      default:
+	return OSS_EIO;
+      }
+
+  if (cmd == SNDCTL_MIX_WRITE)
+    switch (ctrl)
+      {
+      case 1:
+	if (value < 0 || value > 12)
+	  return OSS_EIO;
+
+	if (value != devc->pending_speed_sel)
+	  {
+	    if (devc->open_inputs == 0 && devc->open_outputs == 0)	/* IDDLE */
+	      OUTB (devc->osdev, value, devc->mt_base + 0x01);	/* Make the change now */
+	  }
+
+	return devc->pending_speed_sel = value;
+	break;
+
+      case 2:
+	if (value < 0 || value > 2)
+	  return OSS_EIO;
+	return devc->syncsource = value;
+	break;
+
+      case 3:
+	return devc->use_src = value;
+	break;
+
+      case 4:
+	{
+	  int tmp = envy24_read_cci (devc, 0x20) & ~0x10;
+	  if (value)
+	    tmp |= 0x10;	/* Optical */
+	  envy24_write_cci (devc, 0x20, tmp);
+	  return !!(tmp & 0x10);
+	}
+	break;
+
+      case 5:
+	return devc->ratelock = value;
+	break;
+
+      case 6:
+	return devc->speed;
+	break;
+
+      case 7:
+	return devc->sync_locked =
+	  devc->model_data->auxdrv->get_locked_status (devc);
+	break;
+
+      default:
+	return OSS_EIO;
+      }
+
+  return OSS_EINVAL;
+}
+
+static int
+read_mon (envy24_devc * devc, int ch, int is_right)
+{
+  int tmp;
+
+  if (ch >= 20)
+    return 0;
+
+  OUTB (devc->osdev, ch, devc->mt_base + 0x3a);
+  tmp = INW (devc->osdev, devc->mt_base + 0x38);
+
+  if (is_right)
+    tmp >>= 8;
+  tmp &= 0x7f;
+  if (tmp > 0x60)		/* Mute? */
+    return 0;
+
+  tmp = (tmp * 15) / 10;
+  return 144 - tmp;
+}
+
+static int
+mon_scale (int v)
+{
+  if (v == 0)
+    return 0x7f;		/* Mute */
+
+  v = 144 - v;
+
+  v = (10 * v) / 15;
+  if (v > 0x60)
+    v = 0x7f;
+  return v;
+}
+
+static void
+mon_set (envy24_devc * devc, int ch, int left, int right)
+{
+
+  left = mon_scale (left);
+  right = mon_scale (right);
+
+  OUTB (devc->osdev, 1, devc->mt_base + 0x3b);	/* Volume change rate */
+  OUTB (devc->osdev, ch, devc->mt_base + 0x3a);
+  OUTW (devc->osdev, left | (right << 8), devc->mt_base + 0x38);
+}
+
+static int
+read_peak (envy24_devc * devc, int ch)
+{
+  int tmp;
+
+  if (ch >= 22)
+    return 0;
+
+  OUTB (devc->osdev, ch, devc->mt_base + 0x3e);
+  tmp = INB (devc->osdev, devc->mt_base + 0x3f);
+
+  return tmp;
+}
+
+/*ARGSUSED*/
+static int
+envy24_get_peak (int dev, int ctrl, unsigned int cmd, int value)
+{
+  static const unsigned char peak_cnv[256] = {
+    0, 18, 29, 36, 42, 47, 51, 54, 57, 60, 62, 65, 67, 69, 71, 72,
+    74, 75, 77, 78, 79, 81, 82, 83, 84, 85, 86, 87, 88, 89, 89, 90,
+    91, 92, 93, 93, 94, 95, 95, 96, 97, 97, 98, 99, 99, 100, 100, 101,
+    101, 102, 102, 103, 103, 104, 104, 105, 105, 106, 106, 107, 107, 108, 108,
+    108,
+    109, 109, 110, 110, 110, 111, 111, 111, 112, 112, 113, 113, 113, 114, 114,
+    114,
+    115, 115, 115, 115, 116, 116, 116, 117, 117, 117, 118, 118, 118, 118, 119,
+    119,
+    119, 119, 120, 120, 120, 121, 121, 121, 121, 122, 122, 122, 122, 122, 123,
+    123,
+    123, 123, 124, 124, 124, 124, 125, 125, 125, 125, 125, 126, 126, 126, 126,
+    126,
+    127, 127, 127, 127, 127, 128, 128, 128, 128, 128, 129, 129, 129, 129, 129,
+    130,
+    130, 130, 130, 130, 130, 131, 131, 131, 131, 131, 131, 132, 132, 132, 132,
+    132,
+    132, 133, 133, 133, 133, 133, 133, 134, 134, 134, 134, 134, 134, 134, 135,
+    135,
+    135, 135, 135, 135, 135, 136, 136, 136, 136, 136, 136, 136, 137, 137, 137,
+    137,
+    137, 137, 137, 138, 138, 138, 138, 138, 138, 138, 138, 139, 139, 139, 139,
+    139,
+    139, 139, 139, 140, 140, 140, 140, 140, 140, 140, 140, 141, 141, 141, 141,
+    141,
+    141, 141, 141, 141, 142, 142, 142, 142, 142, 142, 142, 142, 142, 143, 143,
+    143,
+    143, 143, 143, 143, 143, 143, 144, 144, 144, 144, 144, 144, 144, 144, 144,
+    144,
+  };
+
+  envy24_devc *devc = mixer_devs[dev]->devc;
+
+  int i, orign, n = -1, left = 0, right = 0;
+
+  for (i = 0; i < 12 && n == -1; i++)
+    if (ctrl & (1 << i))
+      n = i;
+
+  if (n == -1)
+    return OSS_EINVAL;
+
+  orign = n;
+  if (ctrl & 0x80000000)
+    n += 10;			/* Recording stream */
+
+  if (cmd == SNDCTL_MIX_READ)
+    {
+      left = read_peak (devc, n);
+      if (ctrl & (1 << (orign + 1)))	/* Stereo mode? */
+	right = read_peak (devc, n + 1);
+      else
+	right = left;
+
+      left = peak_cnv[left];
+      right = peak_cnv[right];
+      return left | (right << 8);
+    }
+
+  return OSS_EINVAL;
+}
+
+static int
+envy24_set_mon (int dev, int ctrl, unsigned int cmd, int value)
+{
+  envy24_devc *devc = mixer_devs[dev]->devc;
+
+  int i, orign, n = -1, left = 0, right = 0;
+
+  for (i = 0; i < 10 && n == -1; i++)
+    if (ctrl & (1 << i))
+      n = i;
+
+  if (n == -1)
+    return OSS_EINVAL;
+
+  orign = n;
+  if (ctrl & 0x80000000)
+    n += 10;			/* Recording stream */
+
+  if (cmd == SNDCTL_MIX_READ)
+    {
+      left = read_mon (devc, n, 0) * 10;
+      if (ctrl & (1 << (orign + 1)))	/* Stereo mode? */
+	right = read_mon (devc, n + 1, 1) * 10;
+      else
+	right = read_mon (devc, n, 1) * 10;
+
+      return left | (right << 16);
+    }
+  else if (cmd == SNDCTL_MIX_WRITE)
+    {
+      left = value & 0xffff;
+      right = (value >> 16) & 0xffff;
+
+      if (right > 1440)
+	right = 1440;
+      if (left > 1440)
+	left = 1440;
+
+      if (ctrl & (1 << (orign + 1)))	/* Stereo mode? */
+	{
+	  mon_set (devc, n, left / 10, 0);
+	  mon_set (devc, n + 1, 0, right / 10);
+	}
+      else
+	{
+	  mon_set (devc, n, left / 10, right / 10);
+	}
+      return left | (right << 16);
+    }
+  return OSS_EINVAL;
+}
+
+static int
+get_loopback (envy24_devc * devc, int ch)
+{
+  int tmp;
+
+  tmp = INL (devc->osdev, devc->mt_base + 0x34);
+  return (tmp >> (4 * ch)) & 0x07;
+}
+
+static int
+get_spdif_loopback (envy24_devc * devc, int ch)
+{
+  int tmp;
+
+  tmp = INL (devc->osdev, devc->mt_base + 0x34);
+  return (tmp >> ((4 * ch) + 3)) & 0x01;
+}
+
+static void
+set_loopback (envy24_devc * devc, int ch, int val)
+{
+  int tmp = INL (devc->osdev, devc->mt_base + 0x34);
+  tmp &= ~(0x07 << (4 * ch));
+  tmp |= (val & 0x07) << (4 * ch);
+  OUTL (devc->osdev, tmp, devc->mt_base + 0x34);
+}
+
+static void
+set_spdif_loopback (envy24_devc * devc, int ch, int val)
+{
+  int tmp = INL (devc->osdev, devc->mt_base + 0x34);
+  tmp &= ~(0x08 << (4 * ch));
+  tmp |= (val & 0x01) << ((4 * ch) + 3);
+  OUTL (devc->osdev, tmp, devc->mt_base + 0x34);
+}
+
+static int
+envy24_set_outrout (int dev, int ctrl, unsigned int cmd, int value)
+{
+  envy24_devc *devc = mixer_devs[dev]->devc;
+  int tmp, i;
+
+  if (cmd == SNDCTL_MIX_READ)
+    {
+      tmp = INW (devc->osdev, devc->mt_base + 0x30);
+
+      for (i = 0; i < 8; i++)
+	if (ctrl & (1 << i))
+	  {
+	    tmp = (tmp >> (2 * i)) & 0x03;
+	    switch (tmp)
+	      {
+	      case 0:		/* DMA */
+		return 0;
+		break;
+
+	      case 1:		/* Monitor */
+		return 1;
+		break;
+
+	      case 2:		/* Analog input loopback */
+		return 2 + get_loopback (devc, i);
+		break;
+
+	      case 3:		/* S/PDIF input loopback */
+		return 10 + get_spdif_loopback (devc, i);
+		break;
+	      }
+	  }
+
+      return OSS_EINVAL;
+    }
+  else if (cmd == SNDCTL_MIX_WRITE)
+    {
+      tmp = INW (devc->osdev, devc->mt_base + 0x30);
+      for (i = 0; i < 8; i++)
+	if (ctrl & (1 << i))
+	  {
+	    int ch;
+	    ch = i / 2;
+	    if (i & 1)
+	      ch += 4;
+
+	    tmp &= ~(0x03 << (ch * 2));	/* Cleanup */
+
+	    if (value == 0)	/* DMA */
+	      continue;
+
+	    if (value == 1)	/* Monitor */
+	      {
+		tmp |= 1 << (ch * 2);
+		continue;
+	      }
+
+	    if (value < 10)	/* Analog inputs */
+	      {
+		tmp |= 2 << (ch * 2);
+		set_loopback (devc, i, value - 2);
+		continue;
+	      }
+
+	    tmp |= 3 << (ch * 2);
+	    set_spdif_loopback (devc, i, value - 10);
+	  }
+
+      OUTW (devc->osdev, tmp, devc->mt_base + 0x30);
+      return value;
+    }
+  return OSS_EINVAL;
+}
+
+static int
+envy24_set_stereo_outrout (int dev, int ctrl, unsigned int cmd, int value)
+{
+  envy24_devc *devc = mixer_devs[dev]->devc;
+  int tmp, i;
+
+  if (cmd == SNDCTL_MIX_READ)
+    {
+      tmp = INW (devc->osdev, devc->mt_base + 0x30);
+
+      for (i = 0; i < 8; i++)
+	if (ctrl & (1 << i))
+	  {
+	    int ch;
+	    ch = i / 2;
+	    if (i & 1)
+	      ch += 4;
+	    tmp = (tmp >> (2 * ch)) & 0x03;
+	    switch (tmp)
+	      {
+	      case 0:		/* DMA */
+		return 0;
+		break;
+
+	      case 1:		/* Monitor */
+		return 1;
+		break;
+
+	      case 2:		/* Analog input loopback */
+		return 2 + get_loopback (devc, i) / 2;
+		break;
+
+	      case 3:		/* S/PDIF input loopback */
+		return 6;
+		break;
+	      }
+	  }
+
+      return OSS_EINVAL;
+    }
+  else if (cmd == SNDCTL_MIX_WRITE)
+    {
+      tmp = INW (devc->osdev, devc->mt_base + 0x30);
+      for (i = 0; i < 8; i++)
+	if (ctrl & (1 << i))
+	  {
+	    int ch;
+	    ch = i / 2;
+	    if (i & 1)
+	      ch += 4;
+
+	    tmp &= ~(0x03 << (ch * 2));	/* Cleanup */
+
+	    if (value == 0)	/* DMA */
+	      {
+		continue;
+	      }
+
+	    if (value == 1)	/* Monitor */
+	      {
+		tmp |= 1 << (ch * 2);
+		continue;
+	      }
+
+	    if (value < 6)	/* Analog inputs */
+	      {
+		tmp |= 2 << (ch * 2);
+		set_loopback (devc, i, (value - 2) * 2 + (i & 1));
+		continue;
+	      }
+
+	    tmp |= 3 << (ch * 2);	/* S/PDIF */
+	    set_spdif_loopback (devc, i, (value - 10) + (i & 1));
+	    continue;
+	  }
+
+      OUTW (devc->osdev, tmp, devc->mt_base + 0x30);
+      return value;
+    }
+  return OSS_EINVAL;
+}
+
+static int
+read_spdif_stereo (envy24_devc * devc)
+{
+  int tmp;
+  tmp = INL (devc->osdev, devc->mt_base + 0x32);
+
+/*
+ * Look only at the left channel. Assume the same settings on right.
+ */
+
+  switch (tmp & 0x03)
+    {
+    case 0:			/* From DMA */
+      return 0;
+      break;
+
+    case 1:			/* From digital mixer */
+      return 1;
+      break;
+
+    case 2:			/* Analog input # loopback */
+      return 2 + ((tmp >> 9) & 0x03);
+      break;
+
+    case 3:			/* S/PDIF input loopback */
+      return 6;
+      break;
+    }
+
+  return 0;
+}
+
+static int
+read_spdif_mono (envy24_devc * devc, int ch)
+{
+  int tmp, v;
+  tmp = INL (devc->osdev, devc->mt_base + 0x32);
+
+  if (ch == 0)			/* Left channel ? */
+    v = (tmp) & 0x03;
+  else
+    v = (tmp >> 2) & 0x03;
+
+  switch (v)
+    {
+    case 0:			/* DMA */
+      return 0;
+      break;
+
+    case 1:			/* Monitor */
+      return 1;
+      break;
+
+    case 2:			/* Analog input */
+      if (ch == 0)		/* Left or right */
+	v = (tmp >> 8) & 0x07;
+      else
+	v = (tmp >> 12) & 0x07;
+
+      return 2 + v;
+      break;
+
+    case 3:
+      if (ch == 0)		/* Left or right */
+	v = (tmp >> 11) & 0x01;
+      else
+	v = (tmp >> 15) & 0x01;
+      return 10 + v;
+      break;
+
+    }
+
+  return 0;
+}
+
+static int
+write_spdif_mono (envy24_devc * devc, int ch, int val)
+{
+  int tmp = 0, v;
+  tmp = INW (devc->osdev, devc->mt_base + 0x32);
+
+  if (val == 0)			/* DMA */
+    {
+      if (ch == 0)		/* Left */
+	tmp &= ~0x0003;
+      else
+	tmp &= ~0x000c;
+      goto do_ne;
+    }
+
+  if (val == 1)			/* Monitor */
+    {
+      if (ch == 0)		/* Left */
+	{
+	  tmp &= ~0x0003;
+	  tmp |= 0x0001;
+	}
+      else
+	{
+	  tmp &= ~0x000c;
+	  tmp |= 0x0004;
+	}
+      goto do_ne;
+    }
+
+  if (val < 10)			/* Analog inputs */
+    {
+      v = (val - 2) & 0x07;
+
+      if (ch == 0)		/* Left */
+	{
+	  tmp &= ~(0x0003 | (0x07 << 8));
+	  tmp |= 0x02 | (v << 8);
+	}
+      else
+	{
+	  tmp &= ~(0x000c | (0x07 << 12));
+	  tmp |= 0x08 | (v << 12);
+	}
+      goto do_ne;
+    }
+
+  /* Else S/PDIF */
+
+  if (ch == 0)			/* Left */
+    {
+      tmp &= ~(1 << 11);
+      tmp |= 0x0003;
+
+      if (val == 11)
+	tmp |= 1 << 11;
+    }
+  else
+    {
+      tmp &= ~(1 << 15);
+      tmp |= 0x000c;
+
+      if (val == 11)
+	tmp |= 1 << 15;
+    }
+
+do_ne:
+  OUTW (devc->osdev, tmp, devc->mt_base + 0x32);
+  return val;
+}
+
+static int
+write_spdif_stereo (envy24_devc * devc, int val)
+{
+  int tmp = 0, v;
+
+  if (val == 0)			/* DMA */
+    {
+      tmp = 0x0000;
+      goto do_ne;
+    }
+
+  if (val == 1)			/* Monitor */
+    {
+      tmp = 0x0005;
+      goto do_ne;
+    }
+
+  if (val < 6)			/* Analog inputs */
+    {
+      tmp = 0x000a;
+
+      v = (val - 2) * 2;
+      tmp |= (v << 8);
+      tmp |= ((v + 1) << 12);
+      goto do_ne;
+    }
+
+  /* Else S/PDIF */
+
+  tmp = 0x800f;
+
+do_ne:
+  OUTW (devc->osdev, tmp, devc->mt_base + 0x32);
+  return val;
+}
+
+static int
+envy24_set_spdifrout (int dev, int ctrl, unsigned int cmd, int value)
+{
+  envy24_devc *devc = mixer_devs[dev]->devc;
+
+  if (cmd == SNDCTL_MIX_READ)
+    {
+      if (ctrl == 3)
+	return read_spdif_stereo (devc);
+      else
+	return read_spdif_mono (devc, ctrl - 1);
+    }
+  else if (cmd == SNDCTL_MIX_WRITE)
+    {
+      if (ctrl == 3)
+	return write_spdif_stereo (devc, value);
+      else
+	return write_spdif_mono (devc, ctrl - 1, value);
+    }
+  return OSS_EINVAL;
+}
+
+/*ARGSUSED*/ 
+static int
+create_output_mixer (int dev, envy24_devc * devc, int root)
+{
+  int i, mask = devc->outportmask, group, err, num, skip;
+  char tmp[64];
+
+  int nc = devc->nr_play_channels;
+
+  if (envy24_virtualout)
+    {
+      mask = 0;
+      nc = 10;
+      for (i = 0; i < nc; i++)
+	mask |= (1 << i);
+    }
+
+  if ((group = mixer_ext_create_group (dev, 0, "ENVY24_OUTPUT")) < 0)
+    return group;
+
+  skip = devc->skipdevs;
+  if (skip != 2)
+    skip = 1;
+
+  for (i = 0; i < nc; i += skip)
+    {
+
+      num = 1 << i;
+      if (!(mask & num))
+	continue;		/* Not present */
+
+      sprintf (tmp, "@pcm%d", devc->play_portc[i / 2].dev);
+
+      num |= 1 << (i + 1);
+      if ((err = mixer_ext_create_control (dev, group,
+					   num, envy24_set_mon,
+					   MIXT_STEREOSLIDER16,
+					   tmp, 1440,
+					   MIXF_MONVOL |
+					   MIXF_READABLE |
+					   MIXF_WRITEABLE | MIXF_CENTIBEL)) <
+	  0)
+	return err;
+      if ((err = mixer_ext_create_control (dev, group,
+					   num, envy24_get_peak,
+					   MIXT_STEREOPEAK,
+					   "-", 144,
+					   MIXF_READABLE | MIXF_DECIBEL)) < 0)
+	return err;
+    }
+
+  return 0;
+}
+
+/*ARGSUSED*/ 
+static int
+create_input_mixer (int dev, envy24_devc * devc, int root)
+{
+  int i, mask = devc->inportmask, group, err, num, skip;
+  char tmp[64];
+
+  if ((group = mixer_ext_create_group (dev, 0, "ENVY24_INPUT")) < 0)
+    return group;
+
+  skip = devc->skipdevs;
+  if (skip != 2)
+    skip = 1;
+
+  for (i = 0; i < devc->nr_rec_channels && i < 10; i += skip)
+    {
+
+      num = (1 << i);
+      if (!(mask & num))
+	continue;		/* Not present */
+
+      num |= 0x80000000;	/* Input flag */
+
+      if (i == 8)
+	strcpy (tmp, "ENVY24_SPDIN");
+      else
+	sprintf (tmp, "ENVY24_IN%d/%d", i + 1, i + 2);
+
+      num |= (1 << (i + 1));
+
+      if ((err = mixer_ext_create_control (dev, group,
+					   num, envy24_set_mon,
+					   MIXT_STEREOSLIDER16,
+					   tmp, 1440,
+					   MIXF_MONVOL |
+					   MIXF_READABLE |
+					   MIXF_WRITEABLE | MIXF_CENTIBEL)) <
+	  0)
+	return err;
+
+      if ((err = mixer_ext_create_control (dev, group,
+					   num, envy24_get_peak,
+					   MIXT_STEREOPEAK,
+					   "-", 144,
+					   MIXF_READABLE | MIXF_DECIBEL)) < 0)
+	return err;
+    }
+
+  num = (1 << 11);
+
+  if ((err = mixer_ext_create_control (dev, group,
+				       num, envy24_get_peak,
+				       MIXT_STEREOPEAK,
+				       "MONITOR", 144,
+				       MIXF_READABLE | MIXF_DECIBEL)) < 0)
+    return err;
+  return 0;
+}
+
+/*ARGSUSED*/ 
+static int
+create_mon_mixer (int dev, envy24_devc * devc, int root)
+{
+  int i, mask = devc->outportmask, group, err, num, skip;
+  char tmp[64];
+
+  int nc = devc->nr_play_channels;
+
+  if (envy24_virtualout)
+    {
+      mask = 0;
+      nc = 10;
+      for (i = 0; i < nc; i++)
+	mask |= (1 << i);
+    }
+
+  if ((group = mixer_ext_create_group (dev, 0, "ENVY24_MON")) < 0)
+    return group;
+
+  skip = devc->skipdevs;
+  if (skip != 2)
+    skip = 1;
+
+  for (i = 0; i < nc; i += skip)
+    {
+
+      num = 1 << i;
+      if (!(mask & num))
+	continue;		/* Not present */
+
+      if (devc->skipdevs == 2)
+	{
+	  if (i == 8)
+	    strcpy (tmp, "ENVY24_SPDOUT");
+	  else
+	    sprintf (tmp, "ENVY24_OUT%d/%d", i + 1, i + 2);
+
+	  num |= 1 << (i + 1);
+	  if ((err = mixer_ext_create_control (dev, group,
+					       num, envy24_set_mon,
+					       MIXT_STEREOSLIDER16,
+					       tmp, 1440,
+					       MIXF_MONVOL |
+					       MIXF_READABLE |
+					       MIXF_WRITEABLE |
+					       MIXF_CENTIBEL)) < 0)
+	    return err;
+	}
+      else
+	{
+	  if (i == 8)
+	    strcpy (tmp, "ENVY24_SPDOUTL");
+	  else if (i == 9)
+	    strcpy (tmp, "ENVY24_SPDOUTR");
+	  else
+	    sprintf (tmp, "ENVY24_OUT%d", i + 1);
+	  if ((err = mixer_ext_create_control (dev, group,
+					       num, envy24_set_mon,
+					       MIXT_STEREOSLIDER16,
+					       tmp, 1440,
+					       MIXF_MONVOL |
+					       MIXF_READABLE |
+					       MIXF_WRITEABLE |
+					       MIXF_CENTIBEL)) < 0)
+	    return err;
+	}
+    }
+
+  mask = devc->inportmask;
+  for (i = 0; i < devc->nr_rec_channels && i < 10; i += skip)
+    {
+
+      num = 1 << i;
+      if (!(mask & num))
+	continue;		/* Not present */
+
+      num |= 0x80000000;	/* Input flag */
+
+      if (devc->skipdevs == 2)
+	{
+	  if (i == 8)
+	    strcpy (tmp, "ENVY24_SPDIN");
+	  else
+	    sprintf (tmp, "ENVY24_IN%d/%d", i + 1, i + 2);
+
+	  num |= 1 << (i + 1);
+	  if ((err = mixer_ext_create_control (dev, group,
+					       num, envy24_set_mon,
+					       MIXT_STEREOSLIDER16,
+					       tmp, 1440,
+					       MIXF_MONVOL |
+					       MIXF_READABLE |
+					       MIXF_WRITEABLE |
+					       MIXF_CENTIBEL)) < 0)
+	    return err;
+	}
+      else
+	{
+	  if (i == 8)
+	    strcpy (tmp, "ENVY24_SPDINL");
+	  else if (i == 9)
+	    strcpy (tmp, "ENVY24_SPDINR");
+	  else
+	    sprintf (tmp, "ENVY24_IN%d", i + 1);
+
+	  if ((err = mixer_ext_create_control (dev, group,
+					       num, envy24_set_mon,
+					       MIXT_STEREOSLIDER16,
+					       tmp, 1440,
+					       MIXF_MONVOL |
+					       MIXF_READABLE |
+					       MIXF_WRITEABLE |
+					       MIXF_CENTIBEL)) < 0)
+	    return err;
+	}
+    }
+
+  return 0;
+}
+
+/*ARGSUSED*/ 
+static int
+create_peak_mixer (int dev, envy24_devc * devc, int root)
+{
+  int i, mask = devc->outportmask, group, err, num, skip;
+  int nc = devc->nr_play_channels;
+  char tmp[64];
+
+  if ((group = mixer_ext_create_group (dev, 0, "ENVY24_PEAK")) < 0)
+    return group;
+
+  skip = 2;
+
+  for (i = 0; i < nc; i += skip)
+    {
+
+      num = 1 << i;
+      if (!(mask & num))
+	continue;		/* Not present */
+
+      {
+	if (i == 8)
+	  strcpy (tmp, "ENVY24_SPDOUT");
+	else
+	  sprintf (tmp, "ENVY24_OUT%d/%d", i + 1, i + 2);
+
+	num |= 1 << (i + 1);
+	if ((err = mixer_ext_create_control (dev, group,
+					     num, envy24_get_peak,
+					     MIXT_STEREOPEAK,
+					     tmp, 144,
+					     MIXF_READABLE | MIXF_DECIBEL)) <
+	    0)
+	  return err;
+      }
+    }
+
+  mask = devc->inportmask;
+  for (i = 0; i < devc->nr_rec_channels; i += skip)
+    {
+
+      num = 1 << i;
+      if (!(mask & num))
+	continue;		/* Not present */
+
+      num |= 0x80000000;	/* Input flag */
+
+      {
+	if (i == 8)
+	  strcpy (tmp, "ENVY24_SPDIN");
+	else if (i == 10)
+	  strcpy (tmp, "ENVY24_MAIN");
+	else
+	  sprintf (tmp, "ENVY24_IN%d/%d", i + 1, i + 2);
+
+	num |= 1 << (i + 1);
+	if ((err = mixer_ext_create_control (dev, group,
+					     num, envy24_get_peak,
+					     MIXT_STEREOPEAK,
+					     tmp, 144,
+					     MIXF_READABLE | MIXF_DECIBEL)) <
+	    0)
+	  return err;
+      }
+    }
+
+  return 0;
+}
+
+void
+envy24_set_enum_mask (int dev, int ctl, oss_native_word mask)
+{
+  oss_mixext *ext;
+  int i;
+
+  ext = mixer_find_ext (dev, ctl);
+
+  if (ext == NULL)
+    {
+      cmn_err (CE_WARN, "Cannot locate the mixer extension\n");
+      return;
+    }
+
+  memset (ext->enum_present, 0, sizeof (ext->enum_present));
+
+  for (i = 0; i < 32; i++)
+    if (mask & (1 << i))
+      ext->enum_present[i / 8] |= (1 << (i % 8));
+}
+
+/*ARGSUSED*/ 
+static int
+create_rout_mixer (int dev, envy24_devc * devc, int root)
+{
+  int i, mask = devc->outportmask, group, err, skip, num, chnum;
+  char tmp[64];
+
+  if ((group =
+       mixer_ext_create_group_flags (dev, 0, "ENVY24_ROUTE", MIXF_FLAT)) < 0)
+    return group;
+
+  skip = devc->skipdevs;
+  if (skip != 2)
+    skip = 1;
+
+  for (i = 0; i < 8; i += skip)
+    {
+
+      num = 1 << i;
+      if (!(mask & num))
+	continue;		/* Not present */
+
+      if (devc->skipdevs == 2)
+	{
+	  oss_native_word tmpmask = 0x00000001;
+	  int j;
+
+	  if (i < 2)
+	    tmpmask |= 0x00000002;
+	  for (j = 0; j < 8; j++)
+	    if (mask & (1 << j))
+	      tmpmask |= 1 << ((j / 2) + 2);
+	  if (devc->model_data->flags & MF_SPDIF)
+	    tmpmask |= 0x00000040;
+
+	  sprintf (tmp, "ENVY24_OUT%d/%d", i + 1, i + 2);
+	  chnum = i;
+	  num = (1 << chnum) | (1 << (chnum + 1));
+	  if ((err = mixer_ext_create_control (dev, group,
+					       num, envy24_set_stereo_outrout,
+					       MIXT_ENUM,
+					       tmp, 7,
+					       MIXF_READABLE |
+					       MIXF_WRITEABLE)) < 0)
+	    return err;
+	  envy24_set_enum_mask (dev, err, tmpmask);
+	}
+      else
+	{
+	  oss_native_word tmpmask = 0x00000001;
+	  int j;
+
+	  sprintf (tmp, "ENVY24_OUT%d", i + 1);
+	  chnum = i;
+	  num = 1 << chnum;
+
+	  if (i < 2)
+	    tmpmask |= (1 << 1);
+	  for (j = 0; j < 8; j++)
+	    if (mask & (1 << j))
+	      tmpmask |= 1 << (j + 2);
+	  if (devc->model_data->flags & MF_SPDIF)
+	    tmpmask |= (3 << 10);
+
+	  if ((err = mixer_ext_create_control (dev, group,
+					       num, envy24_set_outrout,
+					       MIXT_ENUM,
+					       tmp, 12,
+					       MIXF_READABLE |
+					       MIXF_WRITEABLE)) < 0)
+	    return err;
+	  envy24_set_enum_mask (dev, err, tmpmask);
+	}
+    }
+
+  mask = devc->inportmask;
+
+  if (devc->model_data->flags & MF_SPDIF)
+    {
+      if (devc->skipdevs == 2)
+	{
+	  oss_native_word tmpmask = 0x00000043;
+	  int j;
+	  for (j = 0; j < 8; j++)
+	    if (mask & (1 << j))
+	      tmpmask |= (1 << ((j / 2) + 2));
+
+	  if ((err = mixer_ext_create_control (dev, group,
+					       3, envy24_set_spdifrout,
+					       MIXT_ENUM,
+					       "ENVY24_SPDIF", 7,
+					       MIXF_READABLE |
+					       MIXF_WRITEABLE)) < 0)
+	    return err;
+	  envy24_set_enum_mask (dev, err, tmpmask);
+	}
+      else
+	{
+	  oss_native_word tmpmask = 0x00000c03;
+	  int j;
+	  for (j = 0; j < 8; j++)
+	    if (mask & (1 << j))
+	      tmpmask |= (1 << (j + 2));
+
+	  if ((err = mixer_ext_create_control (dev, group,
+					       1, envy24_set_spdifrout,
+					       MIXT_ENUM,
+					       "ENVY24_SPDIFL", 12,
+					       MIXF_READABLE |
+					       MIXF_WRITEABLE)) < 0)
+	    return err;
+	  envy24_set_enum_mask (dev, err, tmpmask);
+
+	  if ((err = mixer_ext_create_control (dev, group,
+					       2, envy24_set_spdifrout,
+					       MIXT_ENUM,
+					       "ENVY24_SPDIFR", 12,
+					       MIXF_READABLE |
+					       MIXF_WRITEABLE)) < 0)
+	    return err;
+	  envy24_set_enum_mask (dev, err, tmpmask);
+	}
+    }
+
+#if 0
+  for (i = 0; i < devc->nr_rec_channels && i < 10; i += skip)
+    {
+
+      num = 1 << i;
+      if (!(mask & num))
+	continue;		/* Not present */
+
+      num |= 0x80000000;	/* Input flag */
+
+      if (devc->skipdevs == 2)
+	{
+	  sprintf (tmp, "ENVY24_IN%d/%d", i + 1, i + 2);
+	  num |= 1 << (i + 1);
+	  if ((err = mixer_ext_create_control (dev, group,
+					       num, envy24_set_mon,
+					       MIXT_STEREOSLIDER16,
+					       tmp, 1440,
+					       MIXF_READABLE |
+					       MIXF_WRITEABLE |
+					       MIXF_CENTIBEL)) < 0)
+	    return err;
+	}
+      else
+	{
+	  sprintf (tmp, "ENVY24_IN%d", i + 1);
+	  if ((err = mixer_ext_create_control (dev, group,
+					       num, envy24_set_mon,
+					       MIXT_STEREOSLIDER16,
+					       tmp, 1440,
+					       MIXF_READABLE |
+					       MIXF_WRITEABLE |
+					       MIXF_CENTIBEL)) < 0)
+	    return err;
+	}
+    }
+#endif
+
+  return 0;
+}
+
+static int
+envy24_mix_init (int dev)
+{
+  envy24_devc *devc = mixer_devs[dev]->devc;
+  int group, err, ctl;
+  int n;
+
+  extern int envy24_mixerstyle;
+
+  if ((group = mixer_ext_create_group (dev, 0, "ENVY24")) < 0)
+    return group;
+
+  if (envy24_skipdevs == 2)
+    switch (envy24_mixerstyle)
+      {
+      case 2:
+	/* New style input and output mixer sections */
+	if ((err = create_output_mixer (dev, devc, group)) < 0)
+	  return err;
+	if ((err = create_input_mixer (dev, devc, group)) < 0)
+	  return err;
+	break;
+
+      default:
+	/* Traditional mixer (peak meters and montor gains separated) */
+	if ((err = create_peak_mixer (dev, devc, group)) < 0)
+	  return err;
+	if ((err = create_mon_mixer (dev, devc, group)) < 0)
+	  return err;
+	break;
+      }
+
+  if ((err = create_rout_mixer (dev, devc, group)) < 0)
+    return err;
+
+  if (devc->model_data->auxdrv->mixer_init)
+    if ((err = devc->model_data->auxdrv->mixer_init (devc, dev, group)) < 0)
+      return err;
+
+  if ((err = mixer_ext_create_control (dev, group,
+				       1, envy24_set_control,
+				       MIXT_ENUM,
+				       "ENVY24_RATE", 12,
+				       MIXF_READABLE | MIXF_WRITEABLE)) < 0)
+    return err;
+  mixer_ext_set_strings (dev, err, 
+   "8000 9600 11025 12000 16000 22050 24000 32000 44100 48000 88200 96000", 0);
+
+  if (devc->model_data->flags & (MF_SPDIF | MF_WCLOCK))
+    {
+      n = 2;
+      if (devc->model_data->flags & MF_WCLOCK)
+	n = 3;
+      if ((err = mixer_ext_create_control (dev, group,
+					   2, envy24_set_control,
+					   MIXT_ENUM,
+					   "ENVY24_SYNC", n,
+					   MIXF_READABLE | MIXF_WRITEABLE)) <
+	  0)
+	return err;
+    }
+
+  if (devc->model_data->flags & MF_SPDSELECT)
+    {
+      if ((err = mixer_ext_create_control (dev, group,
+					   4, envy24_set_control,
+					   MIXT_ENUM,
+					   "ENVY24_SPDIN", 2,
+					   MIXF_READABLE | MIXF_WRITEABLE)) <
+	  0)
+	return err;
+    }
+
+#if 0
+/* Always on */
+  if ((err = mixer_ext_create_control (dev, group,
+				       3, envy24_set_control,
+				       MIXT_ONOFF,
+				       "ENVY24_SRC", 2,
+				       MIXF_READABLE | MIXF_WRITEABLE)) < 0)
+    return err;
+#endif
+
+  if ((err = mixer_ext_create_control (dev, group,
+				       5, envy24_set_control,
+				       MIXT_ONOFF,
+				       "ENVY24_RATELOCK", 2,
+				       MIXF_READABLE | MIXF_WRITEABLE)) < 0)
+    return err;
+
+  if ((ctl = mixer_ext_create_control (dev, group,
+				       6, envy24_set_control,
+				       MIXT_VALUE,
+				       "ENVY24_ACTRATE", 96000,
+				       MIXF_READABLE)) < 0)
+    return ctl;
+  mixer_ext_set_description(dev, ctl, "Sample rate currently used by the device");
+
+#if 1
+  if (devc->model_data->auxdrv->get_locked_status)
+    {
+      devc->sync_locked = devc->model_data->auxdrv->get_locked_status (devc);
+
+      if ((err = mixer_ext_create_control (dev, group,
+					   7, envy24_set_control,
+					   MIXT_ONOFF,
+					   "ENVY24_LOCKED", 1,
+					   MIXF_READABLE)) < 0)
+	return err;
+    }
+#endif
+
+  if (devc->model_data->auxdrv->spdif_mixer_init)
+    if ((err =
+	 devc->model_data->auxdrv->spdif_mixer_init (devc, dev, group)) < 0)
+      return err;
+  return 0;
+}
+
+static mixer_driver_t envy24_mixer_driver = {
+  envy24_mixer_ioctl
+};
+
+static int
+install_adev (envy24_devc * devc, char *name, int flags, int skip,
+	      int portc_flags, char *port_id, char *devfile_name)
+{
+  int dev, i;
+  adev_p adev;
+  int fmts = 0, last;
+  extern int envy24_realencoder_hack;
+
+  if (portc_flags & PORTC_SPDOUT)
+    fmts |= AFMT_AC3;
+
+  if ((dev = oss_install_audiodev_with_devname (OSS_AUDIO_DRIVER_VERSION,
+				   devc->osdev,
+				   devc->osdev,
+				   name,
+				   &envy24_audio_driver,
+				   sizeof (audiodrv_t),
+				   ADEV_AUTOMODE | ADEV_NOMMAP |
+				   flags | ADEV_NOVIRTUAL,
+				   fmts | AFMT_S16_LE | AFMT_S32_LE |
+				   AFMT_S24_LE, devc, -1,
+				   devfile_name)) < 0)
+    {
+      dev = -1;
+      return 0;
+    }
+  else
+    {
+      envy24_portc *portc;
+      adev = audio_engines[dev];
+
+      if (devc->first_dev == -1)
+	devc->first_dev = dev;
+      for (i = 0; speed_tab[i].speed != -1; i++)
+	adev->rates[adev->nrates++] = speed_tab[i].speed;
+
+      adev->vmix_flags = 0;
+
+      if (flags == DIR_OUTPUT)
+	{
+	  last = 10;
+	  audio_engines[dev]->port_number = devc->curr_outch;
+	  audio_engines[dev]->min_rate = 8000;
+	  audio_engines[dev]->max_rate = 96000;
+	  portc = &devc->play_portc[devc->nr_outdevs++];
+	  portc->chnum = devc->curr_outch;
+	  strncpy (portc->name, port_id, sizeof (portc->name) - 1);
+	  portc->name[sizeof (portc->name) - 1] = 0;
+	  devc->curr_outch += skip;
+	  if (portc_flags & PORTC_SPDOUT)
+	    audio_engines[dev]->caps |= PCM_CAP_DIGITALOUT;
+	  if (portc_flags & PORTC_SPDIN)
+	    audio_engines[dev]->caps |= PCM_CAP_DIGITALIN;
+
+	}
+      else
+	{
+	  last = 12;
+	  portc = &devc->rec_portc[devc->nr_indevs++];
+	  audio_engines[dev]->port_number = devc->curr_inch + 10;
+	  portc->chnum = devc->curr_inch;
+	  strncpy (portc->name, port_id, sizeof (portc->name) - 1);
+	  portc->name[sizeof (portc->name) - 1] = 0;
+	  devc->curr_inch += skip;
+#ifdef DO_RIAA
+	  portc->riaa_filter = 0;
+#endif
+	}
+
+      portc->flags = portc_flags;
+      audio_engines[dev]->devc = devc;
+      audio_engines[dev]->portc = portc;
+      audio_engines[dev]->rate_source = devc->first_dev;
+
+      switch (skip)
+	{
+	case 1:
+	  audio_engines[dev]->caps |= DSP_CH_MONO;
+	  audio_engines[dev]->min_channels = 1;
+	  audio_engines[dev]->max_channels =
+	    (envy24_force_mono) ? 1 : last - portc->chnum;
+	  break;
+
+	case 2:
+	  audio_engines[dev]->caps |= DSP_CH_STEREO;
+	  audio_engines[dev]->min_channels = 1;
+	  audio_engines[dev]->max_channels = last - portc->chnum;
+	  break;
+
+	default:
+	  audio_engines[dev]->caps |= DSP_CH_MULTI;
+	  audio_engines[dev]->min_channels = 1;
+	  audio_engines[dev]->max_channels = last - portc->chnum;
+	}
+
+      audio_engines[dev]->mixer_dev = devc->mixer_dev;
+      portc->dev = dev;
+      portc->open_mode = 0;
+      portc->is_active = 0;
+      portc->direction = flags;
+      portc->trigger_bits = 0;
+
+      if (envy24_realencoder_hack && flags == DIR_INPUT
+	  && devc->nr_indevs > 1)
+	if (oss_install_mixer (OSS_MIXER_DRIVER_VERSION,
+			       devc->osdev,
+			       devc->osdev,
+			       "Dummy mixer",
+			       &envy24_mixer_driver,
+			       sizeof (mixer_driver_t), devc) >= 0)
+	  {
+	    mixer_devs[devc->mixer_dev]->priority = -1;	/* Don't use as the default mixer */
+	  }
+    }
+
+  return 1;
+}
+
+static int
+install_output_devices (envy24_devc * devc, int mask)
+{
+  char tmp[512], id[32];
+  int i, nc, portc_flags = 0;
+
+  char *lr = "", *kind;
+
+  nc = devc->nr_play_channels = MAX_ODEV;
+  devc->nr_rec_channels = MAX_IDEV;
+
+  if (devc->skipdevs < 1)
+    devc->skipdevs = 1;
+
+  for (i = 0; i < nc; i += devc->skipdevs)
+    {
+      char *devfile_name = "";
+
+      if (devc->skipdevs != 2)
+	lr = (i & 1) ? "R" : "L";
+      kind = "";
+
+      if (!(mask & (1 << devc->curr_outch)))
+	kind = "(virtual) ";
+
+      switch (devc->curr_outch)
+	{
+	case 8:
+	case 9:
+	  portc_flags = PORTC_SPDOUT;
+	  sprintf (tmp, "%s %sS/PDIF out %s", devc->model_data->product, kind,
+		   lr);
+	  sprintf (id, "SPDIF%s", lr);
+	  devfile_name = "spdout";
+	  break;
+
+	default:
+	  if (devc->skipdevs > 1)
+	    {
+	      sprintf (tmp, "%s %sout%d/%d", devc->model_data->product, kind,
+		       i + 1, i + devc->skipdevs);
+	      sprintf (id, "OUT%d/%d", i + 1, i + devc->skipdevs);
+	    }
+	  else
+	    {
+	      sprintf (tmp, "%s %sout%d", devc->model_data->product, kind,
+		       i + 1);
+	      sprintf (id, "OUT%d", i + 1);
+	    }
+	}
+
+      if (mask & (1 << devc->curr_outch))
+	install_adev (devc, tmp, ADEV_NOINPUT, devc->skipdevs, portc_flags,
+		      id, devfile_name);
+      else
+	devc->curr_outch += devc->skipdevs;
+    }
+
+  return 1;
+}
+
+/*ARGSUSED*/ 
+static int
+install_virtual_output_devices (envy24_devc * devc, int mask)
+{
+#if 0
+  char tmp[512];
+  int i, nc;
+
+  char *lr = "";
+  nc = devc->nr_play_channels = MAX_ODEV;
+  devc->nr_rec_channels = MAX_IDEV;
+
+  if (envy24_virtualout)
+    {
+      nc = 10;
+    }
+
+  if (devc->skipdevs < 1)
+    devc->skipdevs = 1;
+
+  for (i = 0; i < nc; i += devc->skipdevs)
+    {
+
+      if (devc->skipdevs != 2)
+	lr = (i & 1) ? "R" : "L";
+
+      switch (devc->curr_outch)
+	{
+	case 8:
+	case 9:
+	  sprintf (tmp, "%s virtual out %s", devc->model_data->product, lr);
+	  break;
+
+	default:
+	  if (devc->skipdevs > 1)
+	    sprintf (tmp, "%s virtual out%d/%d", devc->model_data->product,
+		     i + 1, i + devc->skipdevs);
+	  else
+	    sprintf (tmp, "%s virtual out%d", devc->model_data->product,
+		     i + 1);
+	}
+
+      if (!(mask & (1 << devc->curr_outch)))	/* Not done yet */
+	install_adev (devc, tmp, ADEV_NOINPUT, devc->skipdevs, 0, "virtual", ""); // TODO: Find better device file name
+      else
+	devc->curr_outch += devc->skipdevs;
+    }
+#endif
+  return 1;
+}
+
+static int
+install_input_devices (envy24_devc * devc, int mask)
+{
+  char tmp[512], id[32];
+  int i, portc_flags = 0;
+
+  char *lr = "";
+
+  devc->nr_play_channels = MAX_ODEV;
+  devc->nr_rec_channels = MAX_IDEV;
+
+  if (devc->skipdevs < 1)
+    devc->skipdevs = 1;
+
+  for (i = 0; i < devc->nr_rec_channels; i += devc->skipdevs)
+    {
+      char *devfile_name = "";
+
+      if (devc->skipdevs != 2)
+	lr = (i & 1) ? "R" : "L";
+
+      switch (devc->curr_inch)
+	{
+	case 8:
+	case 9:
+	  portc_flags = PORTC_SPDIN;
+	  sprintf (tmp, "%s S/PDIF in %s", devc->model_data->product, lr);
+	  sprintf (id, "SPDIF%s", lr);
+	  devfile_name = "spdin";
+	  break;
+
+	case 10:
+	case 11:
+	  sprintf (tmp, "%s input from mon. mixer %s",
+		   devc->model_data->product, lr);
+	  sprintf (id, "MON%s", lr);
+	  devfile_name = "mon";
+	  break;
+
+	default:
+	  if (devc->skipdevs > 1)
+	    {
+	      sprintf (tmp, "%s in%d/%d", devc->model_data->product, i + 1,
+		       i + devc->skipdevs);
+	      sprintf (id, "IN%d/%d", i + 1, i + devc->skipdevs);
+	    }
+	  else
+	    {
+	      sprintf (tmp, "%s in%d", devc->model_data->product, i + 1);
+	      sprintf (id, "IN%d", i + 1);
+	    }
+	}
+
+      if (mask & (1 << devc->curr_inch))
+	install_adev (devc, tmp, ADEV_NOOUTPUT, devc->skipdevs, portc_flags,
+		      id, devfile_name);
+      else
+	devc->curr_inch += devc->skipdevs;
+    }
+
+  OUTL (devc->osdev, 0x00224466, devc->mt_base + 0x34);	/* 1 to 1 input routing */
+
+  return 1;
+}
+
+static int
+install_audio_devices (envy24_devc * devc)
+{
+  extern int envy24_swapdevs;
+  int maskout, maskin, i;
+#define setmask(m, b) m|=(1<<(b))
+
+  maskout = maskin = 0;
+
+  if (envy24_devmask == 0)
+    envy24_devmask = 65535;
+
+  if (envy24_devmask & DMASK_MONITORIN)
+    {
+      setmask (maskin, 10);	/* Monitor input left */
+      setmask (maskin, 11);	/* Monitor input right */
+    }
+
+  if (devc->model_data->flags & MF_SPDIF)
+    {
+      if (envy24_devmask & DMASK_SPDIFIN)
+	{
+	  setmask (maskin, 8);	/* S/PDIF left */
+	  setmask (maskin, 9);	/* S/PDIF right */
+	}
+
+      if (envy24_devmask & DMASK_SPDIFOUT)
+	{
+	  setmask (maskout, 8);	/* S/PDIF left */
+	  setmask (maskout, 9);	/* S/PDIF right */
+	}
+      if (devc->model_data->auxdrv->spdif_set)
+	devc->model_data->auxdrv->spdif_set (devc, 0x20);
+    }
+
+  if (envy24_devmask & DMASK_ANALOGOUT)
+    for (i = 0; i < devc->model_data->nr_outs; i++)
+      setmask (maskout, i);
+
+  if (envy24_devmask & DMASK_ANALOGIN)
+    for (i = 0; i < devc->model_data->nr_ins; i++)
+      setmask (maskin, i);
+
+  devc->inportmask = maskin;
+  devc->outportmask = maskout;
+
+  if (envy24_swapdevs)
+    {
+      install_input_devices (devc, maskin);
+      install_output_devices (devc, maskout);
+      install_virtual_output_devices (devc, maskout);
+    }
+  else
+    {
+      install_output_devices (devc, maskout);
+      install_input_devices (devc, maskin);
+      install_virtual_output_devices (devc, maskout);
+    }
+
+  for (i = 0; i < 10; i += devc->skipdevs)
+    {
+      int num = 1 << i;
+      if (devc->skipdevs == 2)
+	num |= 1 << (i + 1);
+
+      if (maskout & num)
+	envy24_set_mon (devc->mixer_dev, num, SNDCTL_MIX_WRITE,
+			1340 | (1340 << 16));
+      if (maskin & num)
+	envy24_set_mon (devc->mixer_dev, 0x80000000 | num, SNDCTL_MIX_WRITE,
+			1340 | (1340 << 16));
+    }
+
+  if (envy24_devmask & DMASK_RAWDEVS)
+    envy24d_install (devc);
+  return 1;
+}
+
+static int
+ac97_read (void *devc_, int reg)
+{
+  envy24_devc *devc = devc_;
+  int i, status;
+
+  OUTB (devc->osdev, reg, devc->ccs_base + 0x08);
+  OUTB (devc->osdev, reg, devc->ccs_base + 0x08);
+  OUTB (devc->osdev, reg, devc->ccs_base + 0x08);
+  OUTB (devc->osdev, 0x10, devc->ccs_base + 0x09);
+
+  for (i = 0; i < 1000; i++)
+    {
+      status = INB (devc->osdev, devc->ccs_base + 0x09);
+      if (!(status & 0x10))
+	{
+	  status = INW (devc->osdev, devc->ccs_base + 0x0a);
+	  return status;
+	}
+    }
+
+  return 0xffff;
+}
+
+static int
+ac97_writereg (void *devc_, int reg, int data)
+{
+  envy24_devc *devc = devc_;
+  int i, status;
+
+  OUTB (devc->osdev, reg, devc->ccs_base + 0x08);
+  OUTB (devc->osdev, reg, devc->ccs_base + 0x08);
+  OUTB (devc->osdev, reg, devc->ccs_base + 0x08);
+  OUTB (devc->osdev, 0x20, devc->ccs_base + 0x09);
+
+  for (i = 0; i < 1000; i++)
+    {
+      status = INB (devc->osdev, devc->ccs_base + 0x09);
+      if (!(status & 0x20))
+	{
+	  OUTW (devc->osdev, data & 0xffff, devc->ccs_base + 0x0a);
+	  return 1;
+	}
+    }
+
+  return 0;
+}
+
+static int
+ac97_write (void *devc, int reg, int data)
+{
+  int ret;
+
+  ac97_writereg (devc, reg, data);
+  ac97_writereg (devc, reg, data);
+  ret = ac97_writereg (devc, reg, data);
+  return ret;
+}
+
+static void
+install_consumer_devices (envy24_devc * devc)
+{
+#if 1
+  int i, status;
+
+  OUTB (devc->osdev, 0x80, devc->ccs_base + 0x09);	/* Cold reset mixer */
+  oss_udelay (200);
+  OUTB (devc->osdev, 0x00, devc->ccs_base + 0x09);	/* Release reset */
+  oss_udelay (200);
+
+  for (i = 0; i < 1000; i++)
+    {
+      status = INB (devc->osdev, devc->ccs_base + 0x09);
+
+      if (status & 0x80)
+	break;
+
+      oss_udelay (1000);
+    }
+
+  if (i >= 1000)
+    {
+    }
+#endif
+
+  devc->consumer_mixer_dev =
+    ac97_install (&devc->ac97devc, "Envy24 consumer mixer", ac97_read,
+		  ac97_write, devc, devc->osdev);
+
+  /* Route monitor output to consumer AC97 */
+  OUTB (devc->osdev, 0x01, devc->mt_base + 0x3c);
+
+  /* Set consumer volumes to full */
+  envy24_write_cci (devc, 3, 0);
+  envy24_write_cci (devc, 4, 0);
+}
+
+static int
+maudio_load_eeprom (envy24_devc * devc)
+{
+  int status;
+
+  status = INB (devc->osdev, devc->ccs_base + 0x13);
+
+  if (!(status & 0x80))
+    return 0;			/* No EEPROM */
+
+  envy24_write_cci (devc, 0x22, devc->eeprom[0xc]);	/* GPIO direction */
+  envy24_write_cci (devc, 0x21, devc->eeprom[0xa]);	/* GPIO write mask */
+  envy24_write_cci (devc, 0x20, devc->eeprom[0xb]);	/* GPIO data */
+
+  return 1;
+}
+
+
+static int
+envy24_init (envy24_devc * devc)
+{
+  extern int envy24_nfrags;
+  oss_native_word phaddr;
+  int err;
+
+  /* Disable all interrupts */
+  OUTB (devc->osdev, 0xff, devc->ccs_base + 0x01);
+  OUTB (devc->osdev, 0xff, devc->mt_base + 0x00);
+
+  if ((err = oss_register_interrupts (devc->osdev, 0, envy24intr, NULL)) < 0)
+    {
+      cmn_err (CE_WARN, "Can't register interrupt handler, err=%d\n", err);
+      return 0;
+    }
+
+  if (envy24_skipdevs < 1)
+    envy24_skipdevs = 1;
+  if (envy24_skipdevs > 2)
+    envy24_skipdevs = 2;
+
+  devc->skipdevs = envy24_skipdevs;
+
+  if (envy24_skipdevs != 1)
+    envy24_force_mono = 0;
+
+  if (devc->model_data->flags & MF_MIDI1)
+    {
+      char name[128];
+      oss_native_word flags;
+      sprintf (name, "%s #1", devc->model_data->product);
+
+      MUTEX_ENTER (devc->mutex, flags);
+      uart401_init (&devc->uart401devc1, devc->osdev, devc->ccs_base + 0x0c,
+		    name);
+      MUTEX_EXIT (devc->mutex, flags);
+
+      /* Enable UART1 interrupts */
+      OUTB (devc->osdev,
+	    INB (devc->osdev, devc->ccs_base + 0x01) & ~0x80,
+	    devc->ccs_base + 0x01);
+    }
+
+  if (devc->model_data->flags & MF_MIDI2)
+    {
+      char name[128];
+      oss_native_word flags;
+      sprintf (name, "%s #2", devc->model_data->product);
+
+      MUTEX_ENTER (devc->mutex, flags);
+      uart401_init (&devc->uart401devc2, devc->osdev, devc->ccs_base + 0x1c,
+		    name);
+      MUTEX_EXIT (devc->mutex, flags);
+      /* Enable UART2 interrupts */
+      OUTB (devc->osdev,
+	    INB (devc->osdev, devc->ccs_base + 0x01) & ~0x20,
+	    devc->ccs_base + 0x01);
+    }
+
+  devc->speedbits = 0;
+  devc->speed = 48000;
+  devc->pending_speed_sel = 9;
+
+  if (devc->model_data->flags & (MF_MEEPROM))
+    maudio_load_eeprom (devc);
+
+  if (devc->model_data->auxdrv->card_init)
+    devc->model_data->auxdrv->card_init (devc);
+  if (devc->model_data->auxdrv->spdif_init)
+    devc->model_data->auxdrv->spdif_init (devc);
+
+  if ((devc->mixer_dev = oss_install_mixer (OSS_MIXER_DRIVER_VERSION,
+					    devc->osdev,
+					    devc->osdev,
+					    devc->model_data->product,
+					    &envy24_mixer_driver,
+					    sizeof (mixer_driver_t),
+					    devc)) >= 0)
+    {
+      int n = 50;
+
+      if (devc->skipdevs == 1)
+	n += 30;
+      mixer_ext_set_init_fn (devc->mixer_dev, envy24_mix_init, n);
+    }
+
+  if (envy24_nfrags != 2 && envy24_nfrags != 4 && envy24_nfrags != 8 &&
+      envy24_nfrags != 16 && envy24_nfrags != 32 && envy24_nfrags != 64)
+    envy24_nfrags = 16;
+
+  devc->playbuffsize = HW_PLAYBUFFSIZE;
+  devc->recbuffsize = HW_RECBUFFSIZE;
+
+  devc->hw_nfrags = envy24_nfrags;
+  devc->hw_pfragsize = devc->playbuffsize / devc->hw_nfrags;
+  devc->hw_rfragsize = devc->recbuffsize / devc->hw_nfrags;
+  devc->hw_fragsamples = devc->hw_pfragsize / 40;	/* # of 32 bit samples/fragment/channel */
+
+  if (devc->hw_pfragsize % 40)
+    cmn_err (CE_WARN, "Error! Bad per channel fragment size\n");
+  devc->hw_playfrag = 0;
+  devc->hw_recfrag = 0;
+
+  devc->playbuf =
+    CONTIG_MALLOC (devc->osdev, HW_ALLOCSIZE, MEMLIMIT_28BITS, &phaddr, devc->playbuf_dma_handle);
+  if (devc->playbuf == NULL)
+    {
+      cmn_err (CE_WARN, "Failed to allocate %d bytes of DMA buffer\n",
+	       HW_ALLOCSIZE);
+      return 0;
+    }
+
+  devc->playbuf_phys = phaddr;
+  if ((devc->playbuf_phys + HW_ALLOCSIZE) >= (256 * 1024 * 1024))
+    {
+      cmn_err (CE_WARN, "Got DMA buffer beyond address 256M.\n");
+      cmn_err (CE_CONT, "Reboot and try again\n");
+      return 1;
+    }
+
+  OUTL (devc->osdev, devc->playbuf_phys, devc->mt_base + 0x10);	/* Play base */
+
+  devc->recbuf =
+    CONTIG_MALLOC (devc->osdev, HW_ALLOCSIZE, MEMLIMIT_28BITS, &phaddr, devc->recbuf_dma_handle);
+  if (devc->recbuf == NULL)
+    {
+      cmn_err (CE_WARN, "Failed to allocate %d bytes of DMA buffer\n",
+	       HW_ALLOCSIZE);
+      return 0;
+    }
+
+  devc->recbuf_phys = phaddr;
+  if ((devc->recbuf_phys + HW_ALLOCSIZE) >= (256 * 1024 * 1024))
+    {
+      cmn_err (CE_WARN, "Got DMA buffer beyond address 256M.\n");
+      cmn_err (CE_CONT, "Reboot and try again\n");
+      return 1;
+    }
+
+  OUTL (devc->osdev, devc->recbuf_phys, devc->mt_base + 0x20);	/* Rec base */
+
+  devc->playback_started = 0;
+  devc->recording_started = 0;
+  devc->playback_prepared = 0;
+  devc->recording_prepared = 0;
+  devc->writeahead = 1;
+#ifdef __VXWORKS__
+  devc->ratelock = 0;
+#else
+  devc->ratelock = 1;
+#endif
+  memset (devc->playbuf, 0, HW_ALLOCSIZE);
+  memset (devc->recbuf, 0, HW_ALLOCSIZE);
+
+  install_audio_devices (devc);
+
+  if (devc->consumer_ac97_present || (devc->model_data->flags & MF_CONSUMER))
+    install_consumer_devices (devc);
+  /* Enable professional rec/play interrupts */
+  OUTB (devc->osdev,
+	INB (devc->osdev, devc->ccs_base + 0x01) & ~0x10,
+	devc->ccs_base + 0x01);
+
+  setup_spdif_control (devc);
+
+  if (devc->model_data->auxdrv->spdif_set)
+    devc->model_data->auxdrv->spdif_set (devc, 0x20);
+
+#if 1
+  /* Make sure everything is initialized */
+  envy24_prepare_play_engine (devc);
+  envy24_launch_play_engine (devc);
+  oss_udelay (10000);
+  envy24_stop_playback (devc);
+#endif
+
+#if 0
+  {
+    char line[200], *s = line;
+    *line = 0;
+
+    for (i = 0; i < 0x20; i++)
+      {
+	if (!(i % 16))
+	  {
+	    if (*line != 0)
+	      cmn_err (CE_CONT, "%s\n", line);
+
+	    s = line;
+	    sprintf (s, "CCS%02x: ", i);
+	    s = line + strlen (line);
+	  }
+	sprintf (s, "%02x ", INB (devc->osdev, devc->ccs_base + i));
+	s = line + strlen (line);
+      }
+    *line = 0;
+
+    for (i = 0; i < 0x40; i++)
+      {
+	if (!(i % 16))
+	  {
+	    if (*line != 0)
+	      cmn_err (CE_CONT, "%s\n", line);
+
+	    s = line;
+	    sprintf (s, "MT%02x: ", i);
+	    s = line + strlen (line);
+	  }
+	sprintf (s, "%02x ", INB (devc->osdev, devc->mt_base + i));
+	s = line + strlen (line);
+      }
+
+    cmn_err (CE_CONT, "%s\n", line);
+  }
+#endif
+
+  return 1;
+}
+
+int
+oss_envy24_attach (oss_device_t * osdev)
+{
+  envy24_devc *devc;
+  static int status;
+  unsigned char pci_irq_line;
+  unsigned short pci_command, vendor, device;
+  unsigned int subvendor;
+  unsigned int pci_ioaddr, pci_ioaddr3;
+  int i;
+
+  char *name = "Generic ENVY24";
+
+  DDB (cmn_err (CE_CONT, "Entered Envy24 probe routine\n"));
+
+  if ((devc = PMALLOC (osdev, sizeof (*devc))) == NULL)
+    {
+      cmn_err (CE_WARN, "Out of memory\n");
+      return 0;
+    }
+
+  devc->osdev = osdev;
+  osdev->devc = devc;
+
+  pci_read_config_word (osdev, PCI_VENDOR_ID, &vendor);
+  pci_read_config_word (osdev, PCI_DEVICE_ID, &device);
+
+  if (vendor != ICENSEMBLE_VENDOR_ID || device != ICENSEMBLE_ENVY24_ID)
+    return 0;
+
+  pci_read_config_dword (osdev, PCI_BASE_ADDRESS_0, &pci_ioaddr);
+  DDB (cmn_err (CE_CONT, "Device found at I/O %x\n", pci_ioaddr));
+  pci_read_config_dword (osdev, PCI_BASE_ADDRESS_3, &pci_ioaddr3);
+
+  devc->active_inputs = 0;
+  devc->active_outputs = 0;
+  devc->sync_locked = 1;
+  devc->first_dev = -1;
+
+  pci_read_config_word (osdev, PCI_COMMAND, &pci_command);
+  pci_read_config_irq (osdev, PCI_INTERRUPT_LINE, &pci_irq_line);
+  pci_read_config_dword (osdev, 0x2c, &subvendor);
+  devc->ccs_base = MAP_PCI_IOADDR (devc->osdev, 0, pci_ioaddr) & ~0x3;
+  DDB (cmn_err (CE_CONT, "CCS base %x/%lx\n", pci_ioaddr, devc->ccs_base));
+
+  devc->mt_base = MAP_PCI_IOADDR (devc->osdev, 3, pci_ioaddr3) & ~0x3;
+  DDB (cmn_err (CE_CONT, "MT base %x/%lx\n", pci_ioaddr3, devc->mt_base));
+
+  pci_command |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
+  pci_write_config_word (osdev, PCI_COMMAND, pci_command);
+
+
+  /* Reset the chip */
+  OUTB (devc->osdev, 0x81, devc->ccs_base + 0x00);
+  oss_udelay (200);
+  /* Release reset */
+  OUTB (devc->osdev, 0x01, devc->ccs_base + 0x00);
+  oss_udelay (200);
+
+  devc->nr_outdevs = devc->nr_indevs = 0;
+  devc->curr_outch = devc->curr_inch = 0;
+  devc->playbuffsize = 0;
+  devc->recbuffsize = 0;
+  devc->playbuf = devc->recbuf = NULL;
+
+  status = INB (devc->osdev, devc->ccs_base + 0x13);
+  if (status & 0x80)		/* EEPROM present */
+    {
+      static char resol_tab[] = { 16, 18, 20, 24 };
+      unsigned char tmpbyte;
+
+      load_eeprom (devc, subvendor);
+
+      /* Fix bit 0x80 of EEPROM location 0x07. */
+      pci_read_config_byte (osdev, 0x61, &tmpbyte);
+      tmpbyte &= 0x80;
+      devc->eeprom[0x07] &= ~0x80;
+      devc->eeprom[0x07] |= tmpbyte;
+
+#if 1
+      devc->eeprom[0x07] |= 0x80;
+#endif
+
+      pci_write_config_byte (osdev, 0x60, devc->eeprom[0x06]);
+      pci_write_config_byte (osdev, 0x61, devc->eeprom[0x07]);
+      pci_write_config_byte (osdev, 0x62, devc->eeprom[0x08]);
+      pci_write_config_byte (osdev, 0x63, devc->eeprom[0x09]);
+
+#if 1
+      if (devc->eeprom[0x06] & 0x20)
+	DDB (cmn_err (CE_CONT, "Two MPU401 UARTs present.\n"));
+      if (devc->eeprom[0x06] & 0x10)
+	{
+	  DDB (cmn_err (CE_CONT, "Consumer AC97 not present.\n"));
+	}
+      else
+	{
+	  DDB (cmn_err (CE_CONT, "Consumer AC97 present.\n"));
+	}
+      DDB (cmn_err (CE_CONT, "%d stereo ADC(s) available\n",
+		    ((devc->eeprom[0x06] >> 2) & 0x03) + 1));
+      DDB (cmn_err (CE_CONT, "%d stereo DAC(s) available\n",
+		    ((devc->eeprom[0x06] >> 0) & 0x03) + 1));
+
+      DDB (cmn_err (CE_CONT, "MT converter type %s\n",
+		    (devc->eeprom[0x07] & 0x80) ? "I2S" : "AC97"));
+
+      if (devc->eeprom[0x08] & 0x80)
+	{
+	  DDB (cmn_err (CE_CONT, "Has I2S volume control and mute\n"));
+	}
+      else
+	{
+	  DDB (cmn_err (CE_CONT, "No I2S volume control and mute\n"));
+	}
+      if (devc->eeprom[0x08] & 0x20)
+	DDB (cmn_err (CE_CONT, "Has 96kHz support\n"));
+
+      DDB (cmn_err (CE_CONT, "Converter resolution %d bits\n",
+		    resol_tab[(devc->eeprom[0x08] >> 4) & 0x03]));
+
+      if (devc->eeprom[0x09] & 0x02)
+	DDB (cmn_err (CE_CONT, "Has S/PDIF in support\n"));
+      if (devc->eeprom[0x09] & 0x01)
+	DDB (cmn_err (CE_CONT, "Has S/PDIF out support\n"));
+
+#endif
+
+      if (subvendor == 0xd6301412)	/* Delta 1010 */
+      if (devc->eeprom[0xc] == 0x7b)	/* Looks like Delta 1010 rev E */
+	 subvendor = 0xd63014ff;	/* Delta 1010E */
+
+
+#if 1
+      if (!(devc->eeprom[0x07] & 0x80))
+	{
+	  cmn_err (CE_WARN, "Cards with AC97 codecs are not supported\n");
+	  return 0;
+	}
+#endif
+    }
+
+  i = 0;
+  while (models[i].svid != 0)
+    {
+      if (models[i].svid == subvendor)
+	{
+	  name = models[i].product;
+	  devc->model_data = &models[i];
+	  if (devc->model_data->auxdrv == NULL)
+	    devc->model_data->auxdrv = &default_auxdrv;
+	  DDB (cmn_err (CE_CONT, "Card id '%s'\n", name));
+
+	  break;
+	}
+
+      i++;
+    }
+
+  if (devc->model_data->flags & MF_AC97)
+    devc->consumer_ac97_present = 1;
+
+  if (models[i].svid == 0)
+    {
+      cmn_err (CE_NOTE, "Unknown device ID (%08x).\n", subvendor);
+      cmn_err (CE_NOTE, "This card is not supported (yet).\n");
+      return 0;
+    }
+
+  MUTEX_INIT (osdev, devc->mutex, MH_DRV);
+  oss_register_device (osdev, name);
+  devc->irq = pci_irq_line;
+  return envy24_init (devc);	/* Detected */
+}
+
+
+int
+oss_envy24_detach (oss_device_t * osdev)
+{
+  envy24_devc *devc;
+
+  devc = osdev->devc;
+
+  if (oss_disable_device (osdev) < 0)
+    return 0;
+
+  /* Disable all interrupts */
+  OUTB (devc->osdev, 0xff, devc->ccs_base + 0x01);
+
+  /* Stop playback */
+  OUTB (devc->osdev, INB (devc->osdev, devc->mt_base + 0x18) & ~0x01,
+	devc->mt_base + 0x18);
+  oss_udelay (100);
+  OUTB (devc->osdev, INB (devc->osdev, devc->mt_base + 0x18) & ~0x01,
+	devc->mt_base + 0x18);
+
+  /* Stop recording */
+  OUTB (devc->osdev, INB (devc->osdev, devc->mt_base + 0x18) & ~0x04,
+	devc->mt_base + 0x18);
+  oss_udelay (100);
+  OUTB (devc->osdev, INB (devc->osdev, devc->mt_base + 0x18) & ~0x04,
+	devc->mt_base + 0x18);
+
+  if (devc->model_data->flags & MF_MIDI1)
+    uart401_disable (&devc->uart401devc1);
+  if (devc->model_data->flags & MF_MIDI2)
+    uart401_disable (&devc->uart401devc2);
+
+  oss_unregister_interrupts (osdev);
+  MUTEX_CLEANUP (devc->mutex);
+  UNMAP_PCI_IOADDR (devc->osdev, 0);
+  UNMAP_PCI_IOADDR (devc->osdev, 3);
+
+  if (devc->playbuf != NULL)
+    CONTIG_FREE (devc->osdev, devc->playbuf, HW_ALLOCSIZE, devc->playbuf_dma_handle);
+
+  if (devc->recbuf != NULL)
+    CONTIG_FREE (devc->osdev, devc->recbuf, HW_ALLOCSIZE, devc->recbuf_dma_handle);
+  devc->playbuf = devc->recbuf = NULL;
+
+  oss_unregister_device (osdev);
+  return 1;
+}
diff --git a/kernel/drv/oss_envy24/oss_envy24.man b/kernel/drv/oss_envy24/oss_envy24.man
new file mode 100644
index 0000000..d9943a9
--- /dev/null
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+NAME
+oss_envy24 - ICE Envy24 audio device driver.
+
+DESCRIPTION
+Open Sound System driver for Envy24 based audio cards such as the
+M-Audio Delta Series, Terratec EWS88 Series, Hoontech DSP24.
+
+ ENVY24 device characteristics:
+
+o 8/16 bit playback/record
+o mono/stereo/4ch/5.1ch/7.1ch playback
+o mono/sterero recording 
+o 8KHz to 192Khz sample rate.
+
+ ENVY24 AUDIO DEVICES
+
+	Audio devices:
+	0: M Audio Delta 1010 out1/2
+	1: M Audio Delta 1010 out3/4
+	2: M Audio Delta 1010 out5/6
+	3: M Audio Delta 1010 out7/8
+	4: M Audio Delta 1010 S/PDIF out
+	5: M Audio Delta 1010 in1/2
+	6: M Audio Delta 1010 in3/4
+	7: M Audio Delta 1010 in5/6
+	8: M Audio Delta 1010 in7/8
+	9: M Audio Delta 1010 S/PDIF in
+	10: M Audio Delta 1010 input from mon. mixer
+	11: M Audio Delta 1010 (all outputs)
+	12: M Audio Delta 1010 (all inputs)
+
+	Synth devices:
+
+	Midi devices:
+	0: M Audio Delta 1010
+
+	Timers:
+	0: System clock
+
+	Mixers:
+	0: M Audio Delta 1010
+
+
+The actual /dev/dsp# numbers may be different on your system. Check the right
+ones by looking at the output procuced by "ossinfo -a" command. With the
+above configuration you can use /dev/dsp0 to /dev/dsp4 for playback of stereo
+streams. If you play mono files the signal will be output only from the left
+channel. /dev/dsp0 to /dev/dsp3 are connected to the analog outputs while
+/dev/dsp4 is the S/PDIF output. 
+
+The /dev/dsp5 to /dev/dsp10 device files can be used for recording. /dev/dsp5
+to /dev/dsp8 are the analog inputs. /dev/dsp11 and /dev/dsp12 are raw 
+input/output device files. They will be described in detail in the "Raw I/O
+devices" section below.
+
+It's also possible to make OSS to create individual device files for every
+channel this creates twice as many device files than the default setting. To
+do this just append envy24_skipdevs=1 to the oss_envy24.conf file. This is useful
+only if you are working on mono rather than stereo signals. However please
+note that setting envy24_skipdevs=1 does _NOT_ lock the device files to one 
+channel mode, the application can still set them to stereo or multi channel 
+mode if it likes.
+
+It is possible to set all device files to mono only mode by setting 
+envy24_skipdevs=1 and envy24_force_mono=1. However this mode disables stereo 
+and multi channel usage for all devices so in general it should not be used.
+ 
+By default the driver will create output devices before the input ones. By 
+setting envy24_swapdevs=1 in oss_envy24.conf you can ask OSS to create the device
+files in opposite order i.e. input device files before the output ones. This
+may be useful when using RealProducer.
+
+As a workaround to a bug in RealProducer you also need to create some dummy
+mixer devices by defining envy24_realencoder_hack=1 in oss_envy24.conf. Without
+these extra mixer devices RealProducer will not be able to access other than 
+the first input device.
+
+
+ DEVICE MANAGEMENT
+
+By default OSS creates a large number of device files for each envy24 card. 
+This may be a problem when multiple cards need to be used in the same system. 
+Adding the envy24_devmask option to oss_envy24.conf should help
+in most cases because it removes the devices that are actually not needed in 
+the system.
+
+The envy24_devmask number is the SUM of the following values:
+
+	1: Create primary (analog/ADAT/TDIF) outputs.
+	2: Create primary (analog/ADAT/TDIF) inputs.
+	4: Create S/PDIF outputs.
+	8: Create S/PDIF inputs.
+	16: Create monitor input device.
+	32: Create the raw input and output devices.
+
+For example envy24_devmask=12 (4+8) creates only the S/PDIF devices.
+To enable all possible (current or future) device files set envy24_devmask
+to 65535 (default).
+
+If possible make your application to open the right device file 
+(/dev/dsp0 to /dev/dsp10) explicitly. It's also possible to use the 
+default devicefile (/dev/dsp) since OSS now supports automatic device
+allocation (it opens the first available input or output devicefile 
+depending on the open mode).
+
+The channel allocation mechanism between device files is very flexible.
+Even there is a device file for every stereo pair (or a mono channel) 
+it's possible to use any of the device file to access multiple channels.
+For example an application can open /dev/dsp0 and set the number of 
+channels to 10. In this way the application can play all 10 channels 
+(or any number between 1 and 10) simultaneously (the samples will be 
+interleaved).
+
+There is simple automatic syncstart feature when using multiple 
+applications at the same time. Playback will not start before all 
+currently open devices files have started the playback operation. 
+The same mechanism works for recording (recording and playback 
+operations are fully independent).
+
+The Envy24 driver supports 8, 16 and 24/32 bit sample formats.
+
+
+ SAMPLING RATE
+
+Envy24 based cards are multi channel devices and all the channels share the
+same sampling rate. For this reason the sampling rate is normally locked to the
+value selected using ossmix. However OSS supports some other methods for
+changing the sampling rate. There are four ways to change the sampling rate.
+
+  BASIC METHOD:
+
+Since all input and output channels of Envy24 work at the same sampling rate
+it's not possible for the applications to select the rate themselves. Instead
+the sampling rate is always locked to the currently selected rate. This rate
+selection can be changed using the ossmix program shipped with OSS.
+
+For example:
+
+	ossmix envy24.rate 48000
+
+sets the sampling rate to 48000 Hz (default). The possible alternatives are 
+- 8000
+- 9600
+- 11025
+- 12000
+- 16000
+- 22050
+- 24000
+- 32000
+- 44100
+- 48000
+- 88200 
+- 96000
+
+When using S/PDIF inputs/outputs only the sampling rates 32000, 44100, 48000, 88200 or 96000 should be used.
+
+  EXTERNAL SYNC
+It's possible to lock the sampling rate to the S/PDIF or world clock inputs
+by setting the envy24.sync setting in ossmix to SPDIF or WCLOCK. However
+the envy24.rate setting should be set manually to match the rate being used
+(there is no autodetection for that).
+
+  NONLOCKED METHOD
+It's also possible to turn the envy24.ratelock setting to OFF using ossmix.
+After that the first application that opens the device can change the sampling
+rate. However great care should be taken that this application gets the
+recording/playback process fully started before any of the other
+applications open their devices. Otherwise all devices will be locked to 8Khz.
+Also keep in mind that subsequent applications will be forced to use the
+sampling rate set by the first one.
+
+  SOFTWARE SRC
+OSS contains a very high quality software based sample rate converter.
+It can be enabled by setting envy24.src to ON using ossmix.
+
+After that OSS can do on-fly sample rate conversions between the actual
+"hardware" sampling rate and the sampling rates used by the applications. In
+this way every application may use different sampling rate. However there are
+some drawbacks in this method:
+
+o The hardware rate needs to be 44100, 48000 or 96000 Hz.
+o The software SRC algorithm consumes some CPU time (1% to 20% per audio 
+channel depending on the CPU speed and sampling rates). For this reason this 
+method may be useless in multi channel use with anything else but the fastest
+high end CPUs.
+o Only mono and stereo (1 or 2 channel) streams are supported.
+o The SRC algorithm does cause minor artifacts to the sound (SNR is around 60 dB).
+
+
+ RAW IO DEVICES
+
+These device files provide an alternative way to access Envy24 based devices.
+With these devices it's possible to bypass the dual buffering required by the 
+"normal" input-output device files described above. This means that also the 
+mmap() feature is available and that the latencies caused by dual buffering 
+are gone. So these device files work much like "ordinary" soundcards. However
+due to multi channel professional nature of the Envy24 chip there are some very
+fundamental differences. This means that these device files can only be used 
+with applications that are aware of them.
+
+The differences from normal audio device files are:
+
+1. The sample format will always be 32 bit msb aligned (AFMT_S32_LE). Trying to
+use any other sample format will cause unexpected results.
+2. Number of channels is fixed and cannot be changed. The output device has 
+always 10 channels (0 to 7 are analog outputs and 8 to 9 are the digital 
+outputs). This assignment will be used even with cards that don't support 
+digital (or analog) outputs at all. If the actual hardware being used has 
+less channels the unused ones will be discarded (however they will be fed to 
+the on board monitor mixer).
+
+The input device is fixed to 12 channels. Channels 0 to 7 are analog inputs.
+Channels 8 to 9 are digital inputs. Channels 10 and 11 are for the result 
+signal from the on board monitor mixer.
+
+
+ DIGITAL MONITOR MIXER
+
+All Envy24 based cards have a built in monitor mixer. It can be used to mix 
+allinput and output signals together. The result can be recorded from the 
+"input from mon mixer" device (device 10 in the /dev/sndstat example above).
+The monitor mix signal can also be routed to any of the outputs (including 
+S/PDIF and the "consumer" AC97 output of Terratec EWS88MT/D and any other card
+that support s it).
+
+The settings in the gain.* group of ossmix are used to change the levels of all
+inputs and outputs in the digital monitor mixer. The possible values are 
+between 0 (minimum) and 144 (maximum).
+
+OSS permits using all 10 possible output channels of the monitor mixer even 
+with cards that have less physical outputs. These "virtual" outputs are only 
+sent to the monitor mixer and their signal is only present in the monitor mixer
+output. To enable these "virtual" channels set the envy24_virtualout parameter 
+to 1 in oss_envy24.conf. This option has no effect with Delta1010, EWS88MT and
+other cards that have 10 "real" outputs.
+
+
+ SYNC SOURCE
+
+On cards with S/PDIF and/or World Clock inputs it's possible to select the
+sync source using
+
+        ossmix envy24.sync
+
+The possible choices are:
+
+o INTERNAL: Use the internal sampling rate as defined by envy24.rate
+o SPDIF: Use the S/PDIF input as the clock source. The envy24.rate setting 
+must be set manually to match the actual input sampling rate.
+o WCLOCK: Like SPDIF but uses the world clock input signal (Delta 1010 only).
+
+
+ OUTPUT ROUTINGS
+
+Output routing of output ports can be changed by changing the route.* settings
+using ossmix. The possible choices are:
+
+o DMA: Playback from the associated /dev/dsp# device.
+o MONITOR: Output of the digital mixer (only out1/2 and S/PDIF).
+o IN1/2 to IN9/10 or IN1 to IN10: Loopback from the analog inputs
+o SPDIFL or SPDIFR or SPDIF: Loopback from the S/PDIF input.
+
+
+ PEAK METERS
+
+Envy24 based cards have peak meters for the input and output ports of the
+digital monitor mixer. ossmix can show these values under the peak.* group
+(these settings are read only). The values are between 0 (minimum) and 255
+(maximum). At this moment the only applications that supports these peak meters
+are ossmix and ossxmix.
+
+
+ AUDIO LATENCY
+
+IDE disk and CD-ROM drives may cause some interrupt latency problems which
+may cause dropouts in recording/playback with Envy24 based cards. For this
+reason ensure that DMA is turned on for the disk drive.
+
+Another method to solve the dropout problems is making the fragment size used
+by the driver longer. This can be done by adding envy24_nfrags=N to the
+oss_envy24.conf file. By default N is 16. Values 2, 4 or 8 make the fragments
+longer which should cure the dropout problems. However this may cause
+latency problems with some applications. Values 32 and 64 decrease the
+latencies but may cause dropouts with IDE.
+
+
+OPTIONS
+
+o envy24_skipdevs: It's also possible to make OSS to create individual device 
+files for every channel. This creates twice as many device files than the 
+default setting.  
+Values: 1, 0 Default: 0
+
+o envy24_swapdevs: By default the driver will create output devices before the
+input ones. You can force the input devices to be configured before output 
+devices.
+Values: 1, 0 Default: 0
+
+o envy24_realencoder_hack: RealProducer wants to see a mixer device in 
+/dev/mixer. This option allows you to define a dummy /dev/mixer mixer device.
+Envy24 Mixer device doesn't provide any consumer level soundcard compatibility
+so this dummy mixer fools RealProducer into thinking it's running on a consumer
+soundcard like SB Pro or SBLive.
+Values: 1, 0 Default: 0
+
+o envy24_gain_sliders: With some devices it's possible to change the gain 
+controllers to be continuous sliders instead of just enumerated ones.
+Values: 1, 0 Default: 0
+
+o envy24_nfrags: To solve the dropout problems make the fragment size used by
+the driver longer. By default is 16. Values 2, 4 or 8 make the fragments longer
+which should cure the dropout problems. However this may cause latency problems
+with some applications. Values 32 and 64 decrease the latencies but may cause
+dropouts with IDE drives.
+Values: 2-64 Default: 16
+
+o envy24_virtualout: OSS permits using all 10 possible output channels of the
+monitor mixer even with cards that have less physical outputs. These "virtual"
+outputs are only sent to the monitor mixer and their signal is only present in
+the monitor mixer output. This has no effect for Delta1010 or Terratec EWS88MT.
+Values: 1, 0 Default: 0
+
+o envy24_force_mono: It is possible to set all device files to mono only mode
+by setting envy24_skipdevs=1 and envy24_force_mono=1. However this mode 
+disables stereo and multi channel usage for all devices so in general it should
+not be used.
+Values: 1, 0 Default: 0
+
+FILES
+CONFIGFILEPATH/oss_envy24.conf Device configuration file
+
+AUTHOR
+4Front Technologies
+