diff options
Diffstat (limited to 'attic')
68 files changed, 34060 insertions, 0 deletions
diff --git a/attic/.nomake b/attic/.nomake new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/attic/.nomake diff --git a/attic/README b/attic/README new file mode 100644 index 0000000..fb53ad5 --- /dev/null +++ b/attic/README @@ -0,0 +1,7 @@ +The attic/drv directory contains drivers that are no longer maintained and/or +supported. If necessary they can be compiled by doing the following operation +in the OSS (source) directory before running the ./configre script: + + ln -s attic/drv/<the_driver_I_need> kernel/drv/ + + diff --git a/attic/drv/oss_allegro/.config b/attic/drv/oss_allegro/.config new file mode 100644 index 0000000..5280084 --- /dev/null +++ b/attic/drv/oss_allegro/.config @@ -0,0 +1 @@ +platform=i86pc diff --git a/attic/drv/oss_allegro/.devices b/attic/drv/oss_allegro/.devices new file mode 100644 index 0000000..f8be458 --- /dev/null +++ b/attic/drv/oss_allegro/.devices @@ -0,0 +1,5 @@ +oss_allegro pci125d,1988 ESS Allegro ES1988 +oss_allegro pci125d,1990 ESS Canyon 3D ES1990 +oss_allegro pci125d,1992 ESS Canyon 3D-2 ES1992 +oss_allegro pci125d,1998 ESS Maestro3 ES1998 +oss_allegro pci125d,199a ESS Maestro3 ES199A diff --git a/attic/drv/oss_allegro/.name b/attic/drv/oss_allegro/.name new file mode 100644 index 0000000..78da1ff --- /dev/null +++ b/attic/drv/oss_allegro/.name @@ -0,0 +1 @@ +ESS Allegro (ES1988) chipset diff --git a/attic/drv/oss_allegro/.params b/attic/drv/oss_allegro/.params new file mode 100644 index 0000000..f77ef89 --- /dev/null +++ b/attic/drv/oss_allegro/.params @@ -0,0 +1,12 @@ +int allegro_amp=0; +/* + * Allegro Amp is needed for ESS 198X AC97 codecs + * Values: 1=Enable 0=Disable Default: 0 + */ + +int allegro_mpu_ioaddr=0; +/* + * Allegro MPU 401 UART I/O Base + * Values: 0x300, 0x320, 0x33, 0x340 Default: 0 + */ + diff --git a/attic/drv/oss_allegro/400m_src.dat b/attic/drv/oss_allegro/400m_src.dat new file mode 100644 index 0000000..f9d5d0e --- /dev/null +++ b/attic/drv/oss_allegro/400m_src.dat @@ -0,0 +1,33 @@ +0xBF80, 0x101E, 0x906E, 0x006E, 0x8B88, 0x6980, 0xEF88, 0x906F, 0x0D6F, 0x6900, 0xEB08, 0x0412,
+0xBC20, 0x696E, 0xB801, 0x906E, 0x7980, 0x0403, 0xB90E, 0x8807, 0xBE43, 0xBF01, 0xBE47, 0xBE41,
+0x7A80, 0x002A, 0xBE40, 0x3029, 0xEFCC, 0xBE41, 0x7A80, 0x0028, 0xBE40, 0x3028, 0xEFCC, 0x6907,
+0xE308, 0x042A, 0x6909, 0x902C, 0x7980, 0x042C, 0x690D, 0x902C, 0x1009, 0x881A, 0x100A, 0xBA01,
+0x881B, 0x100D, 0x881C, 0x100E, 0xBA01, 0x881D, 0xBF80, 0x00ED, 0x881E, 0x050C, 0x0124, 0xB904,
+0x9027, 0x6918, 0xE308, 0x04B3, 0x902D, 0x6913, 0xBFA0, 0x7598, 0xF704, 0xAE2D, 0x00FF, 0x8B8D,
+0x6919, 0xE308, 0x0463, 0x691A, 0xE308, 0x0456, 0xB907, 0x8809, 0xBEC6, 0x0453, 0x10A9, 0x90AD,
+0x7980, 0x047C, 0xB903, 0x8809, 0xBEC6, 0x0460, 0x1889, 0x6C22, 0x90AD, 0x10A9, 0x6E23, 0x6C22,
+0x90AD, 0x7980, 0x047C, 0x101A, 0xE308, 0x046F, 0xB903, 0x8809, 0xBEC6, 0x046C, 0x10A9, 0x90A0,
+0x90AD, 0x7980, 0x047C, 0xB901, 0x8809, 0xBEC6, 0x047B, 0x1889, 0x6C22, 0x90A0, 0x90AD, 0x10A9,
+0x6E23, 0x6C22, 0x90A0, 0x90AD, 0x692D, 0xE308, 0x049C, 0x0124, 0xB703, 0xB902, 0x8818, 0x8B89,
+0x022C, 0x108A, 0x7C04, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99A0,
+0x108A, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99AF, 0x7B99, 0x0484,
+0x0124, 0x060F, 0x101B, 0x2013, 0x901B, 0xBFA0, 0x7FFF, 0xE344, 0x04AC, 0x901B, 0x8B89, 0x7A80,
+0x051A, 0x6927, 0xBA01, 0x9027, 0x7A80, 0x0523, 0x6927, 0xE308, 0x049E, 0x7980, 0x050F, 0x0624,
+0x1026, 0x2013, 0x9026, 0xBFA0, 0x7FFF, 0xE304, 0x04C0, 0x8B8D, 0x7A80, 0x051A, 0x7980, 0x04B4,
+0x9026, 0x1013, 0x3026, 0x901B, 0x8B8D, 0x7A80, 0x051A, 0x7A80, 0x0523, 0x1027, 0xBA01, 0x9027,
+0xE308, 0x04B4, 0x0124, 0x060F, 0x8B89, 0x691A, 0xE308, 0x04EA, 0x6919, 0xE388, 0x04E0, 0xB903,
+0x8809, 0xBEC6, 0x04DD, 0x1FA0, 0x2FAE, 0x98A9, 0x7980, 0x050F, 0xB901, 0x8818, 0xB907, 0x8809,
+0xBEC6, 0x04E7, 0x10EE, 0x90A9, 0x7980, 0x050F, 0x6919, 0xE308, 0x04FE, 0xB903, 0x8809, 0xBE46,
+0xBEC6, 0x04FA, 0x17A0, 0xBE1E, 0x1FAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0xBE47,
+0x7980, 0x050F, 0xB901, 0x8809, 0xBEC6, 0x050E, 0x16A0, 0x26A0, 0xBFB7, 0xFF00, 0xBE1E, 0x1EA0,
+0x2EAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0x850C, 0x860F, 0x6907, 0xE388, 0x0516,
+0x0D07, 0x8510, 0xBE59, 0x881E, 0xBE4A, 0xEF00, 0x101E, 0x901C, 0x101F, 0x901D, 0x10A0, 0x901E,
+0x10A0, 0x901F, 0xEF00, 0x101E, 0x301C, 0x9020, 0x731B, 0x5420, 0xBE03, 0x9825, 0x1025, 0x201C,
+0x9025, 0x7325, 0x5414, 0xBE03, 0x8B8E, 0x9880, 0x692F, 0xE388, 0x0539, 0xBE59, 0xBB07, 0x6180,
+0x9880, 0x8BA0, 0x101F, 0x301D, 0x9021, 0x731B, 0x5421, 0xBE03, 0x982E, 0x102E, 0x201D, 0x902E,
+0x732E, 0x5415, 0xBE03, 0x9880, 0x692F, 0xE388, 0x054F, 0xBE59, 0xBB07, 0x6180, 0x9880, 0x8BA0,
+0x6918, 0xEF08, 0x7325, 0x5416, 0xBE03, 0x98A0, 0x732E, 0x5417, 0xBE03, 0x98A0, 0xEF00, 0x8BA0,
+0xBEC6, 0x056B, 0xBE59, 0xBB04, 0xAA90, 0xBE04, 0xBE1E, 0x99E0, 0x8BE0, 0x69A0, 0x90D0, 0x69A0,
+0x90D0, 0x081F, 0xB805, 0x881F, 0x8B90, 0x69A0, 0x90D0, 0x69A0, 0x9090, 0x8BD0, 0x8BD8, 0xBE1F,
+0xEF00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
diff --git a/attic/drv/oss_allegro/500m_src.dat b/attic/drv/oss_allegro/500m_src.dat new file mode 100644 index 0000000..c7ba59e --- /dev/null +++ b/attic/drv/oss_allegro/500m_src.dat @@ -0,0 +1,33 @@ +0xBF80, 0x101E, 0x906E, 0x006E, 0x8B88, 0x6980, 0xEF88, 0x906F, 0x0D6F, 0x6900, 0xEB08, 0x0512,
+0xBC20, 0x696E, 0xB801, 0x906E, 0x7980, 0x0503, 0xB90E, 0x8807, 0xBE43, 0xBF01, 0xBE47, 0xBE41,
+0x7A80, 0x002A, 0xBE40, 0x3029, 0xEFCC, 0xBE41, 0x7A80, 0x0028, 0xBE40, 0x3028, 0xEFCC, 0x6907,
+0xE308, 0x052A, 0x6909, 0x902C, 0x7980, 0x052C, 0x690D, 0x902C, 0x1009, 0x881A, 0x100A, 0xBA01,
+0x881B, 0x100D, 0x881C, 0x100E, 0xBA01, 0x881D, 0xBF80, 0x00ED, 0x881E, 0x050C, 0x0124, 0xB904,
+0x9027, 0x6918, 0xE308, 0x05B3, 0x902D, 0x6913, 0xBFA0, 0x7598, 0xF704, 0xAE2D, 0x00FF, 0x8B8D,
+0x6919, 0xE308, 0x0563, 0x691A, 0xE308, 0x0556, 0xB907, 0x8809, 0xBEC6, 0x0553, 0x10A9, 0x90AD,
+0x7980, 0x057C, 0xB903, 0x8809, 0xBEC6, 0x0560, 0x1889, 0x6C22, 0x90AD, 0x10A9, 0x6E23, 0x6C22,
+0x90AD, 0x7980, 0x057C, 0x101A, 0xE308, 0x056F, 0xB903, 0x8809, 0xBEC6, 0x056C, 0x10A9, 0x90A0,
+0x90AD, 0x7980, 0x057C, 0xB901, 0x8809, 0xBEC6, 0x057B, 0x1889, 0x6C22, 0x90A0, 0x90AD, 0x10A9,
+0x6E23, 0x6C22, 0x90A0, 0x90AD, 0x692D, 0xE308, 0x059C, 0x0124, 0xB703, 0xB902, 0x8818, 0x8B89,
+0x022C, 0x108A, 0x7C04, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x065B, 0x692A, 0x8809, 0x8B89, 0x99A0,
+0x108A, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x065B, 0x692A, 0x8809, 0x8B89, 0x99AF, 0x7B99, 0x0584,
+0x0124, 0x060F, 0x101B, 0x2013, 0x901B, 0xBFA0, 0x7FFF, 0xE344, 0x05AC, 0x901B, 0x8B89, 0x7A80,
+0x061A, 0x6927, 0xBA01, 0x9027, 0x7A80, 0x0623, 0x6927, 0xE308, 0x059E, 0x7980, 0x060F, 0x0624,
+0x1026, 0x2013, 0x9026, 0xBFA0, 0x7FFF, 0xE304, 0x05C0, 0x8B8D, 0x7A80, 0x061A, 0x7980, 0x05B4,
+0x9026, 0x1013, 0x3026, 0x901B, 0x8B8D, 0x7A80, 0x061A, 0x7A80, 0x0623, 0x1027, 0xBA01, 0x9027,
+0xE308, 0x05B4, 0x0124, 0x060F, 0x8B89, 0x691A, 0xE308, 0x05EA, 0x6919, 0xE388, 0x05E0, 0xB903,
+0x8809, 0xBEC6, 0x05DD, 0x1FA0, 0x2FAE, 0x98A9, 0x7980, 0x060F, 0xB901, 0x8818, 0xB907, 0x8809,
+0xBEC6, 0x05E7, 0x10EE, 0x90A9, 0x7980, 0x060F, 0x6919, 0xE308, 0x05FE, 0xB903, 0x8809, 0xBE46,
+0xBEC6, 0x05FA, 0x17A0, 0xBE1E, 0x1FAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0xBE47,
+0x7980, 0x060F, 0xB901, 0x8809, 0xBEC6, 0x060E, 0x16A0, 0x26A0, 0xBFB7, 0xFF00, 0xBE1E, 0x1EA0,
+0x2EAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0x850C, 0x860F, 0x6907, 0xE388, 0x0616,
+0x0D07, 0x8510, 0xBE59, 0x881E, 0xBE4A, 0xEF00, 0x101E, 0x901C, 0x101F, 0x901D, 0x10A0, 0x901E,
+0x10A0, 0x901F, 0xEF00, 0x101E, 0x301C, 0x9020, 0x731B, 0x5420, 0xBE03, 0x9825, 0x1025, 0x201C,
+0x9025, 0x7325, 0x5414, 0xBE03, 0x8B8E, 0x9880, 0x692F, 0xE388, 0x0639, 0xBE59, 0xBB07, 0x6180,
+0x9880, 0x8BA0, 0x101F, 0x301D, 0x9021, 0x731B, 0x5421, 0xBE03, 0x982E, 0x102E, 0x201D, 0x902E,
+0x732E, 0x5415, 0xBE03, 0x9880, 0x692F, 0xE388, 0x064F, 0xBE59, 0xBB07, 0x6180, 0x9880, 0x8BA0,
+0x6918, 0xEF08, 0x7325, 0x5416, 0xBE03, 0x98A0, 0x732E, 0x5417, 0xBE03, 0x98A0, 0xEF00, 0x8BA0,
+0xBEC6, 0x066B, 0xBE59, 0xBB04, 0xAA90, 0xBE04, 0xBE1E, 0x99E0, 0x8BE0, 0x69A0, 0x90D0, 0x69A0,
+0x90D0, 0x081F, 0xB805, 0x881F, 0x8B90, 0x69A0, 0x90D0, 0x69A0, 0x9090, 0x8BD0, 0x8BD8, 0xBE1F,
+0xEF00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
diff --git a/attic/drv/oss_allegro/600m_src.dat b/attic/drv/oss_allegro/600m_src.dat new file mode 100644 index 0000000..953eb20 --- /dev/null +++ b/attic/drv/oss_allegro/600m_src.dat @@ -0,0 +1,33 @@ +0xBF80, 0x101E, 0x906E, 0x006E, 0x8B88, 0x6980, 0xEF88, 0x906F, 0x0D6F, 0x6900, 0xEB08, 0x0612,
+0xBC20, 0x696E, 0xB801, 0x906E, 0x7980, 0x0603, 0xB90E, 0x8807, 0xBE43, 0xBF01, 0xBE47, 0xBE41,
+0x7A80, 0x002A, 0xBE40, 0x3029, 0xEFCC, 0xBE41, 0x7A80, 0x0028, 0xBE40, 0x3028, 0xEFCC, 0x6907,
+0xE308, 0x062A, 0x6909, 0x902C, 0x7980, 0x062C, 0x690D, 0x902C, 0x1009, 0x881A, 0x100A, 0xBA01,
+0x881B, 0x100D, 0x881C, 0x100E, 0xBA01, 0x881D, 0xBF80, 0x00ED, 0x881E, 0x050C, 0x0124, 0xB904,
+0x9027, 0x6918, 0xE308, 0x06B3, 0x902D, 0x6913, 0xBFA0, 0x7598, 0xF704, 0xAE2D, 0x00FF, 0x8B8D,
+0x6919, 0xE308, 0x0663, 0x691A, 0xE308, 0x0656, 0xB907, 0x8809, 0xBEC6, 0x0653, 0x10A9, 0x90AD,
+0x7980, 0x067C, 0xB903, 0x8809, 0xBEC6, 0x0660, 0x1889, 0x6C22, 0x90AD, 0x10A9, 0x6E23, 0x6C22,
+0x90AD, 0x7980, 0x067C, 0x101A, 0xE308, 0x066F, 0xB903, 0x8809, 0xBEC6, 0x066C, 0x10A9, 0x90A0,
+0x90AD, 0x7980, 0x067C, 0xB901, 0x8809, 0xBEC6, 0x067B, 0x1889, 0x6C22, 0x90A0, 0x90AD, 0x10A9,
+0x6E23, 0x6C22, 0x90A0, 0x90AD, 0x692D, 0xE308, 0x069C, 0x0124, 0xB703, 0xB902, 0x8818, 0x8B89,
+0x022C, 0x108A, 0x7C04, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x075B, 0x692A, 0x8809, 0x8B89, 0x99A0,
+0x108A, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x075B, 0x692A, 0x8809, 0x8B89, 0x99AF, 0x7B99, 0x0684,
+0x0124, 0x060F, 0x101B, 0x2013, 0x901B, 0xBFA0, 0x7FFF, 0xE344, 0x06AC, 0x901B, 0x8B89, 0x7A80,
+0x071A, 0x6927, 0xBA01, 0x9027, 0x7A80, 0x0723, 0x6927, 0xE308, 0x069E, 0x7980, 0x070F, 0x0624,
+0x1026, 0x2013, 0x9026, 0xBFA0, 0x7FFF, 0xE304, 0x06C0, 0x8B8D, 0x7A80, 0x071A, 0x7980, 0x06B4,
+0x9026, 0x1013, 0x3026, 0x901B, 0x8B8D, 0x7A80, 0x071A, 0x7A80, 0x0723, 0x1027, 0xBA01, 0x9027,
+0xE308, 0x06B4, 0x0124, 0x060F, 0x8B89, 0x691A, 0xE308, 0x06EA, 0x6919, 0xE388, 0x06E0, 0xB903,
+0x8809, 0xBEC6, 0x06DD, 0x1FA0, 0x2FAE, 0x98A9, 0x7980, 0x070F, 0xB901, 0x8818, 0xB907, 0x8809,
+0xBEC6, 0x06E7, 0x10EE, 0x90A9, 0x7980, 0x070F, 0x6919, 0xE308, 0x06FE, 0xB903, 0x8809, 0xBE46,
+0xBEC6, 0x06FA, 0x17A0, 0xBE1E, 0x1FAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0xBE47,
+0x7980, 0x070F, 0xB901, 0x8809, 0xBEC6, 0x070E, 0x16A0, 0x26A0, 0xBFB7, 0xFF00, 0xBE1E, 0x1EA0,
+0x2EAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0x850C, 0x860F, 0x6907, 0xE388, 0x0716,
+0x0D07, 0x8510, 0xBE59, 0x881E, 0xBE4A, 0xEF00, 0x101E, 0x901C, 0x101F, 0x901D, 0x10A0, 0x901E,
+0x10A0, 0x901F, 0xEF00, 0x101E, 0x301C, 0x9020, 0x731B, 0x5420, 0xBE03, 0x9825, 0x1025, 0x201C,
+0x9025, 0x7325, 0x5414, 0xBE03, 0x8B8E, 0x9880, 0x692F, 0xE388, 0x0739, 0xBE59, 0xBB07, 0x6180,
+0x9880, 0x8BA0, 0x101F, 0x301D, 0x9021, 0x731B, 0x5421, 0xBE03, 0x982E, 0x102E, 0x201D, 0x902E,
+0x732E, 0x5415, 0xBE03, 0x9880, 0x692F, 0xE388, 0x074F, 0xBE59, 0xBB07, 0x6180, 0x9880, 0x8BA0,
+0x6918, 0xEF08, 0x7325, 0x5416, 0xBE03, 0x98A0, 0x732E, 0x5417, 0xBE03, 0x98A0, 0xEF00, 0x8BA0,
+0xBEC6, 0x076B, 0xBE59, 0xBB04, 0xAA90, 0xBE04, 0xBE1E, 0x99E0, 0x8BE0, 0x69A0, 0x90D0, 0x69A0,
+0x90D0, 0x081F, 0xB805, 0x881F, 0x8B90, 0x69A0, 0x90D0, 0x69A0, 0x9090, 0x8BD0, 0x8BD8, 0xBE1F,
+0xEF00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
diff --git a/attic/drv/oss_allegro/800m_src.dat b/attic/drv/oss_allegro/800m_src.dat new file mode 100644 index 0000000..d309079 --- /dev/null +++ b/attic/drv/oss_allegro/800m_src.dat @@ -0,0 +1,33 @@ +0xBF80, 0x101E, 0x906E, 0x006E, 0x8B88, 0x6980, 0xEF88, 0x906F, 0x0D6F, 0x6900, 0xEB08, 0x0812,
+0xBC20, 0x696E, 0xB801, 0x906E, 0x7980, 0x0803, 0xB90E, 0x8807, 0xBE43, 0xBF01, 0xBE47, 0xBE41,
+0x7A80, 0x002A, 0xBE40, 0x3029, 0xEFCC, 0xBE41, 0x7A80, 0x0028, 0xBE40, 0x3028, 0xEFCC, 0x6907,
+0xE308, 0x082A, 0x6909, 0x902C, 0x7980, 0x082C, 0x690D, 0x902C, 0x1009, 0x881A, 0x100A, 0xBA01,
+0x881B, 0x100D, 0x881C, 0x100E, 0xBA01, 0x881D, 0xBF80, 0x00ED, 0x881E, 0x050C, 0x0124, 0xB904,
+0x9027, 0x6918, 0xE308, 0x08B3, 0x902D, 0x6913, 0xBFA0, 0x7598, 0xF704, 0xAE2D, 0x00FF, 0x8B8D,
+0x6919, 0xE308, 0x0863, 0x691A, 0xE308, 0x0856, 0xB907, 0x8809, 0xBEC6, 0x0853, 0x10A9, 0x90AD,
+0x7980, 0x087C, 0xB903, 0x8809, 0xBEC6, 0x0860, 0x1889, 0x6C22, 0x90AD, 0x10A9, 0x6E23, 0x6C22,
+0x90AD, 0x7980, 0x087C, 0x101A, 0xE308, 0x086F, 0xB903, 0x8809, 0xBEC6, 0x086C, 0x10A9, 0x90A0,
+0x90AD, 0x7980, 0x087C, 0xB901, 0x8809, 0xBEC6, 0x087B, 0x1889, 0x6C22, 0x90A0, 0x90AD, 0x10A9,
+0x6E23, 0x6C22, 0x90A0, 0x90AD, 0x692D, 0xE308, 0x089C, 0x0124, 0xB703, 0xB902, 0x8818, 0x8B89,
+0x022C, 0x108A, 0x7C04, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x095B, 0x692A, 0x8809, 0x8B89, 0x99A0,
+0x108A, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x095B, 0x692A, 0x8809, 0x8B89, 0x99AF, 0x7B99, 0x0884,
+0x0124, 0x060F, 0x101B, 0x2013, 0x901B, 0xBFA0, 0x7FFF, 0xE344, 0x08AC, 0x901B, 0x8B89, 0x7A80,
+0x091A, 0x6927, 0xBA01, 0x9027, 0x7A80, 0x0923, 0x6927, 0xE308, 0x089E, 0x7980, 0x090F, 0x0624,
+0x1026, 0x2013, 0x9026, 0xBFA0, 0x7FFF, 0xE304, 0x08C0, 0x8B8D, 0x7A80, 0x091A, 0x7980, 0x08B4,
+0x9026, 0x1013, 0x3026, 0x901B, 0x8B8D, 0x7A80, 0x091A, 0x7A80, 0x0923, 0x1027, 0xBA01, 0x9027,
+0xE308, 0x08B4, 0x0124, 0x060F, 0x8B89, 0x691A, 0xE308, 0x08EA, 0x6919, 0xE388, 0x08E0, 0xB903,
+0x8809, 0xBEC6, 0x08DD, 0x1FA0, 0x2FAE, 0x98A9, 0x7980, 0x090F, 0xB901, 0x8818, 0xB907, 0x8809,
+0xBEC6, 0x08E7, 0x10EE, 0x90A9, 0x7980, 0x090F, 0x6919, 0xE308, 0x08FE, 0xB903, 0x8809, 0xBE46,
+0xBEC6, 0x08FA, 0x17A0, 0xBE1E, 0x1FAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0xBE47,
+0x7980, 0x090F, 0xB901, 0x8809, 0xBEC6, 0x090E, 0x16A0, 0x26A0, 0xBFB7, 0xFF00, 0xBE1E, 0x1EA0,
+0x2EAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0x850C, 0x860F, 0x6907, 0xE388, 0x0916,
+0x0D07, 0x8510, 0xBE59, 0x881E, 0xBE4A, 0xEF00, 0x101E, 0x901C, 0x101F, 0x901D, 0x10A0, 0x901E,
+0x10A0, 0x901F, 0xEF00, 0x101E, 0x301C, 0x9020, 0x731B, 0x5420, 0xBE03, 0x9825, 0x1025, 0x201C,
+0x9025, 0x7325, 0x5414, 0xBE03, 0x8B8E, 0x9880, 0x692F, 0xE388, 0x0939, 0xBE59, 0xBB07, 0x6180,
+0x9880, 0x8BA0, 0x101F, 0x301D, 0x9021, 0x731B, 0x5421, 0xBE03, 0x982E, 0x102E, 0x201D, 0x902E,
+0x732E, 0x5415, 0xBE03, 0x9880, 0x692F, 0xE388, 0x094F, 0xBE59, 0xBB07, 0x6180, 0x9880, 0x8BA0,
+0x6918, 0xEF08, 0x7325, 0x5416, 0xBE03, 0x98A0, 0x732E, 0x5417, 0xBE03, 0x98A0, 0xEF00, 0x8BA0,
+0xBEC6, 0x096B, 0xBE59, 0xBB04, 0xAA90, 0xBE04, 0xBE1E, 0x99E0, 0x8BE0, 0x69A0, 0x90D0, 0x69A0,
+0x90D0, 0x081F, 0xB805, 0x881F, 0x8B90, 0x69A0, 0x90D0, 0x69A0, 0x9090, 0x8BD0, 0x8BD8, 0xBE1F,
+0xEF00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
diff --git a/attic/drv/oss_allegro/900m_src.dat b/attic/drv/oss_allegro/900m_src.dat new file mode 100644 index 0000000..a9cdf6a --- /dev/null +++ b/attic/drv/oss_allegro/900m_src.dat @@ -0,0 +1,33 @@ +0xBF80, 0x101E, 0x906E, 0x006E, 0x8B88, 0x6980, 0xEF88, 0x906F, 0x0D6F, 0x6900, 0xEB08, 0x0912,
+0xBC20, 0x696E, 0xB801, 0x906E, 0x7980, 0x0903, 0xB90E, 0x8807, 0xBE43, 0xBF01, 0xBE47, 0xBE41,
+0x7A80, 0x002A, 0xBE40, 0x3029, 0xEFCC, 0xBE41, 0x7A80, 0x0028, 0xBE40, 0x3028, 0xEFCC, 0x6907,
+0xE308, 0x092A, 0x6909, 0x902C, 0x7980, 0x092C, 0x690D, 0x902C, 0x1009, 0x881A, 0x100A, 0xBA01,
+0x881B, 0x100D, 0x881C, 0x100E, 0xBA01, 0x881D, 0xBF80, 0x00ED, 0x881E, 0x050C, 0x0124, 0xB904,
+0x9027, 0x6918, 0xE308, 0x09B3, 0x902D, 0x6913, 0xBFA0, 0x7598, 0xF704, 0xAE2D, 0x00FF, 0x8B8D,
+0x6919, 0xE308, 0x0963, 0x691A, 0xE308, 0x0956, 0xB907, 0x8809, 0xBEC6, 0x0953, 0x10A9, 0x90AD,
+0x7980, 0x097C, 0xB903, 0x8809, 0xBEC6, 0x0960, 0x1889, 0x6C22, 0x90AD, 0x10A9, 0x6E23, 0x6C22,
+0x90AD, 0x7980, 0x097C, 0x101A, 0xE308, 0x096F, 0xB903, 0x8809, 0xBEC6, 0x096C, 0x10A9, 0x90A0,
+0x90AD, 0x7980, 0x097C, 0xB901, 0x8809, 0xBEC6, 0x097B, 0x1889, 0x6C22, 0x90A0, 0x90AD, 0x10A9,
+0x6E23, 0x6C22, 0x90A0, 0x90AD, 0x692D, 0xE308, 0x099C, 0x0124, 0xB703, 0xB902, 0x8818, 0x8B89,
+0x022C, 0x108A, 0x7C04, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x0A5B, 0x692A, 0x8809, 0x8B89, 0x99A0,
+0x108A, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x0A5B, 0x692A, 0x8809, 0x8B89, 0x99AF, 0x7B99, 0x0984,
+0x0124, 0x060F, 0x101B, 0x2013, 0x901B, 0xBFA0, 0x7FFF, 0xE344, 0x09AC, 0x901B, 0x8B89, 0x7A80,
+0x0A1A, 0x6927, 0xBA01, 0x9027, 0x7A80, 0x0A23, 0x6927, 0xE308, 0x099E, 0x7980, 0x0A0F, 0x0624,
+0x1026, 0x2013, 0x9026, 0xBFA0, 0x7FFF, 0xE304, 0x09C0, 0x8B8D, 0x7A80, 0x0A1A, 0x7980, 0x09B4,
+0x9026, 0x1013, 0x3026, 0x901B, 0x8B8D, 0x7A80, 0x0A1A, 0x7A80, 0x0A23, 0x1027, 0xBA01, 0x9027,
+0xE308, 0x09B4, 0x0124, 0x060F, 0x8B89, 0x691A, 0xE308, 0x09EA, 0x6919, 0xE388, 0x09E0, 0xB903,
+0x8809, 0xBEC6, 0x09DD, 0x1FA0, 0x2FAE, 0x98A9, 0x7980, 0x0A0F, 0xB901, 0x8818, 0xB907, 0x8809,
+0xBEC6, 0x09E7, 0x10EE, 0x90A9, 0x7980, 0x0A0F, 0x6919, 0xE308, 0x09FE, 0xB903, 0x8809, 0xBE46,
+0xBEC6, 0x09FA, 0x17A0, 0xBE1E, 0x1FAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0xBE47,
+0x7980, 0x0A0F, 0xB901, 0x8809, 0xBEC6, 0x0A0E, 0x16A0, 0x26A0, 0xBFB7, 0xFF00, 0xBE1E, 0x1EA0,
+0x2EAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0x850C, 0x860F, 0x6907, 0xE388, 0x0A16,
+0x0D07, 0x8510, 0xBE59, 0x881E, 0xBE4A, 0xEF00, 0x101E, 0x901C, 0x101F, 0x901D, 0x10A0, 0x901E,
+0x10A0, 0x901F, 0xEF00, 0x101E, 0x301C, 0x9020, 0x731B, 0x5420, 0xBE03, 0x9825, 0x1025, 0x201C,
+0x9025, 0x7325, 0x5414, 0xBE03, 0x8B8E, 0x9880, 0x692F, 0xE388, 0x0A39, 0xBE59, 0xBB07, 0x6180,
+0x9880, 0x8BA0, 0x101F, 0x301D, 0x9021, 0x731B, 0x5421, 0xBE03, 0x982E, 0x102E, 0x201D, 0x902E,
+0x732E, 0x5415, 0xBE03, 0x9880, 0x692F, 0xE388, 0x0A4F, 0xBE59, 0xBB07, 0x6180, 0x9880, 0x8BA0,
+0x6918, 0xEF08, 0x7325, 0x5416, 0xBE03, 0x98A0, 0x732E, 0x5417, 0xBE03, 0x98A0, 0xEF00, 0x8BA0,
+0xBEC6, 0x0A6B, 0xBE59, 0xBB04, 0xAA90, 0xBE04, 0xBE1E, 0x99E0, 0x8BE0, 0x69A0, 0x90D0, 0x69A0,
+0x90D0, 0x081F, 0xB805, 0x881F, 0x8B90, 0x69A0, 0x90D0, 0x69A0, 0x9090, 0x8BD0, 0x8BD8, 0xBE1F,
+0xEF00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
diff --git a/attic/drv/oss_allegro/a00m_src.dat b/attic/drv/oss_allegro/a00m_src.dat new file mode 100644 index 0000000..6b6c419 --- /dev/null +++ b/attic/drv/oss_allegro/a00m_src.dat @@ -0,0 +1,33 @@ +0xBF80, 0x101E, 0x906E, 0x006E, 0x8B88, 0x6980, 0xEF88, 0x906F, 0x0D6F, 0x6900, 0xEB08, 0x0A12,
+0xBC20, 0x696E, 0xB801, 0x906E, 0x7980, 0x0A03, 0xB90E, 0x8807, 0xBE43, 0xBF01, 0xBE47, 0xBE41,
+0x7A80, 0x002A, 0xBE40, 0x3029, 0xEFCC, 0xBE41, 0x7A80, 0x0028, 0xBE40, 0x3028, 0xEFCC, 0x6907,
+0xE308, 0x0A2A, 0x6909, 0x902C, 0x7980, 0x0A2C, 0x690D, 0x902C, 0x1009, 0x881A, 0x100A, 0xBA01,
+0x881B, 0x100D, 0x881C, 0x100E, 0xBA01, 0x881D, 0xBF80, 0x00ED, 0x881E, 0x050C, 0x0124, 0xB904,
+0x9027, 0x6918, 0xE308, 0x0AB3, 0x902D, 0x6913, 0xBFA0, 0x7598, 0xF704, 0xAE2D, 0x00FF, 0x8B8D,
+0x6919, 0xE308, 0x0A63, 0x691A, 0xE308, 0x0A56, 0xB907, 0x8809, 0xBEC6, 0x0A53, 0x10A9, 0x90AD,
+0x7980, 0x0A7C, 0xB903, 0x8809, 0xBEC6, 0x0A60, 0x1889, 0x6C22, 0x90AD, 0x10A9, 0x6E23, 0x6C22,
+0x90AD, 0x7980, 0x0A7C, 0x101A, 0xE308, 0x0A6F, 0xB903, 0x8809, 0xBEC6, 0x0A6C, 0x10A9, 0x90A0,
+0x90AD, 0x7980, 0x0A7C, 0xB901, 0x8809, 0xBEC6, 0x0A7B, 0x1889, 0x6C22, 0x90A0, 0x90AD, 0x10A9,
+0x6E23, 0x6C22, 0x90A0, 0x90AD, 0x692D, 0xE308, 0x0A9C, 0x0124, 0xB703, 0xB902, 0x8818, 0x8B89,
+0x022C, 0x108A, 0x7C04, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x0B5B, 0x692A, 0x8809, 0x8B89, 0x99A0,
+0x108A, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x0B5B, 0x692A, 0x8809, 0x8B89, 0x99AF, 0x7B99, 0x0A84,
+0x0124, 0x060F, 0x101B, 0x2013, 0x901B, 0xBFA0, 0x7FFF, 0xE344, 0x0AAC, 0x901B, 0x8B89, 0x7A80,
+0x0B1A, 0x6927, 0xBA01, 0x9027, 0x7A80, 0x0B23, 0x6927, 0xE308, 0x0A9E, 0x7980, 0x0B0F, 0x0624,
+0x1026, 0x2013, 0x9026, 0xBFA0, 0x7FFF, 0xE304, 0x0AC0, 0x8B8D, 0x7A80, 0x0B1A, 0x7980, 0x0AB4,
+0x9026, 0x1013, 0x3026, 0x901B, 0x8B8D, 0x7A80, 0x0B1A, 0x7A80, 0x0B23, 0x1027, 0xBA01, 0x9027,
+0xE308, 0x0AB4, 0x0124, 0x060F, 0x8B89, 0x691A, 0xE308, 0x0AEA, 0x6919, 0xE388, 0x0AE0, 0xB903,
+0x8809, 0xBEC6, 0x0ADD, 0x1FA0, 0x2FAE, 0x98A9, 0x7980, 0x0B0F, 0xB901, 0x8818, 0xB907, 0x8809,
+0xBEC6, 0x0AE7, 0x10EE, 0x90A9, 0x7980, 0x0B0F, 0x6919, 0xE308, 0x0AFE, 0xB903, 0x8809, 0xBE46,
+0xBEC6, 0x0AFA, 0x17A0, 0xBE1E, 0x1FAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0xBE47,
+0x7980, 0x0B0F, 0xB901, 0x8809, 0xBEC6, 0x0B0E, 0x16A0, 0x26A0, 0xBFB7, 0xFF00, 0xBE1E, 0x1EA0,
+0x2EAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0x850C, 0x860F, 0x6907, 0xE388, 0x0B16,
+0x0D07, 0x8510, 0xBE59, 0x881E, 0xBE4A, 0xEF00, 0x101E, 0x901C, 0x101F, 0x901D, 0x10A0, 0x901E,
+0x10A0, 0x901F, 0xEF00, 0x101E, 0x301C, 0x9020, 0x731B, 0x5420, 0xBE03, 0x9825, 0x1025, 0x201C,
+0x9025, 0x7325, 0x5414, 0xBE03, 0x8B8E, 0x9880, 0x692F, 0xE388, 0x0B39, 0xBE59, 0xBB07, 0x6180,
+0x9880, 0x8BA0, 0x101F, 0x301D, 0x9021, 0x731B, 0x5421, 0xBE03, 0x982E, 0x102E, 0x201D, 0x902E,
+0x732E, 0x5415, 0xBE03, 0x9880, 0x692F, 0xE388, 0x0B4F, 0xBE59, 0xBB07, 0x6180, 0x9880, 0x8BA0,
+0x6918, 0xEF08, 0x7325, 0x5416, 0xBE03, 0x98A0, 0x732E, 0x5417, 0xBE03, 0x98A0, 0xEF00, 0x8BA0,
+0xBEC6, 0x0B6B, 0xBE59, 0xBB04, 0xAA90, 0xBE04, 0xBE1E, 0x99E0, 0x8BE0, 0x69A0, 0x90D0, 0x69A0,
+0x90D0, 0x081F, 0xB805, 0x881F, 0x8B90, 0x69A0, 0x90D0, 0x69A0, 0x9090, 0x8BD0, 0x8BD8, 0xBE1F,
+0xEF00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
diff --git a/attic/drv/oss_allegro/a80m_src.dat b/attic/drv/oss_allegro/a80m_src.dat new file mode 100644 index 0000000..f175036 --- /dev/null +++ b/attic/drv/oss_allegro/a80m_src.dat @@ -0,0 +1,33 @@ +0xBF80, 0x101E, 0x906E, 0x006E, 0x8B88, 0x6980, 0xEF88, 0x906F, 0x0D6F, 0x6900, 0xEB08, 0x0A92,
+0xBC20, 0x696E, 0xB801, 0x906E, 0x7980, 0x0A83, 0xB90E, 0x8807, 0xBE43, 0xBF01, 0xBE47, 0xBE41,
+0x7A80, 0x002A, 0xBE40, 0x3029, 0xEFCC, 0xBE41, 0x7A80, 0x0028, 0xBE40, 0x3028, 0xEFCC, 0x6907,
+0xE308, 0x0AAA, 0x6909, 0x902C, 0x7980, 0x0AAC, 0x690D, 0x902C, 0x1009, 0x881A, 0x100A, 0xBA01,
+0x881B, 0x100D, 0x881C, 0x100E, 0xBA01, 0x881D, 0xBF80, 0x00ED, 0x881E, 0x050C, 0x0124, 0xB904,
+0x9027, 0x6918, 0xE308, 0x0B33, 0x902D, 0x6913, 0xBFA0, 0x7598, 0xF704, 0xAE2D, 0x00FF, 0x8B8D,
+0x6919, 0xE308, 0x0AE3, 0x691A, 0xE308, 0x0AD6, 0xB907, 0x8809, 0xBEC6, 0x0AD3, 0x10A9, 0x90AD,
+0x7980, 0x0AFC, 0xB903, 0x8809, 0xBEC6, 0x0AE0, 0x1889, 0x6C22, 0x90AD, 0x10A9, 0x6E23, 0x6C22,
+0x90AD, 0x7980, 0x0AFC, 0x101A, 0xE308, 0x0AEF, 0xB903, 0x8809, 0xBEC6, 0x0AEC, 0x10A9, 0x90A0,
+0x90AD, 0x7980, 0x0AFC, 0xB901, 0x8809, 0xBEC6, 0x0AFB, 0x1889, 0x6C22, 0x90A0, 0x90AD, 0x10A9,
+0x6E23, 0x6C22, 0x90A0, 0x90AD, 0x692D, 0xE308, 0x0B1C, 0x0124, 0xB703, 0xB902, 0x8818, 0x8B89,
+0x022C, 0x108A, 0x7C04, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x0BDB, 0x692A, 0x8809, 0x8B89, 0x99A0,
+0x108A, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x0BDB, 0x692A, 0x8809, 0x8B89, 0x99AF, 0x7B99, 0x0B04,
+0x0124, 0x060F, 0x101B, 0x2013, 0x901B, 0xBFA0, 0x7FFF, 0xE344, 0x0B2C, 0x901B, 0x8B89, 0x7A80,
+0x0B9A, 0x6927, 0xBA01, 0x9027, 0x7A80, 0x0BA3, 0x6927, 0xE308, 0x0B1E, 0x7980, 0x0B8F, 0x0624,
+0x1026, 0x2013, 0x9026, 0xBFA0, 0x7FFF, 0xE304, 0x0B40, 0x8B8D, 0x7A80, 0x0B9A, 0x7980, 0x0B34,
+0x9026, 0x1013, 0x3026, 0x901B, 0x8B8D, 0x7A80, 0x0B9A, 0x7A80, 0x0BA3, 0x1027, 0xBA01, 0x9027,
+0xE308, 0x0B34, 0x0124, 0x060F, 0x8B89, 0x691A, 0xE308, 0x0B6A, 0x6919, 0xE388, 0x0B60, 0xB903,
+0x8809, 0xBEC6, 0x0B5D, 0x1FA0, 0x2FAE, 0x98A9, 0x7980, 0x0B8F, 0xB901, 0x8818, 0xB907, 0x8809,
+0xBEC6, 0x0B67, 0x10EE, 0x90A9, 0x7980, 0x0B8F, 0x6919, 0xE308, 0x0B7E, 0xB903, 0x8809, 0xBE46,
+0xBEC6, 0x0B7A, 0x17A0, 0xBE1E, 0x1FAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0xBE47,
+0x7980, 0x0B8F, 0xB901, 0x8809, 0xBEC6, 0x0B8E, 0x16A0, 0x26A0, 0xBFB7, 0xFF00, 0xBE1E, 0x1EA0,
+0x2EAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0x850C, 0x860F, 0x6907, 0xE388, 0x0B96,
+0x0D07, 0x8510, 0xBE59, 0x881E, 0xBE4A, 0xEF00, 0x101E, 0x901C, 0x101F, 0x901D, 0x10A0, 0x901E,
+0x10A0, 0x901F, 0xEF00, 0x101E, 0x301C, 0x9020, 0x731B, 0x5420, 0xBE03, 0x9825, 0x1025, 0x201C,
+0x9025, 0x7325, 0x5414, 0xBE03, 0x8B8E, 0x9880, 0x692F, 0xE388, 0x0BB9, 0xBE59, 0xBB07, 0x6180,
+0x9880, 0x8BA0, 0x101F, 0x301D, 0x9021, 0x731B, 0x5421, 0xBE03, 0x982E, 0x102E, 0x201D, 0x902E,
+0x732E, 0x5415, 0xBE03, 0x9880, 0x692F, 0xE388, 0x0BCF, 0xBE59, 0xBB07, 0x6180, 0x9880, 0x8BA0,
+0x6918, 0xEF08, 0x7325, 0x5416, 0xBE03, 0x98A0, 0x732E, 0x5417, 0xBE03, 0x98A0, 0xEF00, 0x8BA0,
+0xBEC6, 0x0BEB, 0xBE59, 0xBB04, 0xAA90, 0xBE04, 0xBE1E, 0x99E0, 0x8BE0, 0x69A0, 0x90D0, 0x69A0,
+0x90D0, 0x081F, 0xB805, 0x881F, 0x8B90, 0x69A0, 0x90D0, 0x69A0, 0x9090, 0x8BD0, 0x8BD8, 0xBE1F,
+0xEF00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
diff --git a/attic/drv/oss_allegro/allegro_code.h b/attic/drv/oss_allegro/allegro_code.h new file mode 100644 index 0000000..e2e9613 --- /dev/null +++ b/attic/drv/oss_allegro/allegro_code.h @@ -0,0 +1,1508 @@ + +/****************************************************************************** + * * + * (C) 1997-1999 ESS Technology, Inc. * + * * + * This source code, its compiled object code, and its associated data sets * + * are copyright (C) 1997-1999 ESS Technology, Inc. This source code and its * + * associated data sets are trade secrets of ESS Technology, Inc. * + * * + ******************************************************************************/ + +/*--------------------------------------------------------------------------- + * Copyright (C) 1997-1999, ESS Technology, Inc. + *--------------------------------------------------------------------------- + * FILENAME: kernelbn.c v1.01 + *--------------------------------------------------------------------------- + * DESCRIPTION: DSP binaries + *--------------------------------------------------------------------------- + * AUTHOR: Henry Tang / Hong Kim / Alger Yeung/Don Kim + *--------------------------------------------------------------------------- + * HISTORY: + * 09/25/97 HT Created. + * 01/20/97 PJCC (CRL) modified to include Sensaura 3D positional & + * speaker virtualization + * 05/05/99 AY cleanup for NT modem drivers + * 05/18/99 AY add cpythru for 400/500/600/800 + * 05/24/99 AY add cpythru for 4C0/680 + *--------------------------------------------------------------------------- + */ + + +/* */ +/* Kernel */ +/* */ + +WORD gawKernelVectCode[] = { +#include "kernel.dat" +}; + +KERNEL_BIN gsKernelVectCode = { + gawKernelVectCode, + sizeof (gawKernelVectCode) +}; + +/* */ +/* Memory Check Kernel */ +/* */ + +WORD gawMemChkVectCode[] = { +#include "memchk.dat" +}; + +KERNEL_BIN gsMemChkVectCode = { + gawMemChkVectCode, + sizeof (gawMemChkVectCode) +}; + + +/* */ +/* Copy Through */ +/* */ + +WORD gawCpyThruDataXXXX[] = { + 0x0000 +}; + +WORD gawCpyThruVect0400[] = { + 0x7980, 0x0400, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawCpyThruCode0400[] = { + 0 /*#include "400cpyth.dat" */ +}; + +WORD gawCpyThruVect04C0[] = { + 0x7980, 0x04C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawCpyThruCode04C0[] = { + 0 /*#include "4C0cpyth.dat" */ +}; + +WORD gawCpyThruVect0500[] = { + 0x7980, 0x0500, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawCpyThruCode0500[] = { + 0 /*#include "500cpyth.dat" */ +}; + +WORD gawCpyThruVect0600[] = { + 0x7980, 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawCpyThruCode0600[] = { + 0 /*#include "600cpyth.dat" */ +}; + + +WORD gawCpyThruVect0680[] = { + 0x7980, 0x0680, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawCpyThruCode0680[] = { + 0 /*#include "680cpyth.dat" */ +}; + +WORD gawCpyThruVect0800[] = { + 0x7980, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawCpyThruCode0800[] = { + 0 /*#include "800cpyth.dat" */ +}; + +CLIENT_BIN gasCpyThruVectCode[] = { + { + 0x0400, + gawCpyThruVect0400, + gawCpyThruCode0400, + gawCpyThruDataXXXX, + sizeof (gawCpyThruVect0400), + sizeof (gawCpyThruCode0400), + sizeof (gawCpyThruDataXXXX)} + , + { + 0x04C0, + gawCpyThruVect04C0, + gawCpyThruCode04C0, + gawCpyThruDataXXXX, + sizeof (gawCpyThruVect04C0), + sizeof (gawCpyThruCode04C0), + sizeof (gawCpyThruDataXXXX)} + , + { + 0x0500, + gawCpyThruVect0500, + gawCpyThruCode0500, + gawCpyThruDataXXXX, + sizeof (gawCpyThruVect0500), + sizeof (gawCpyThruCode0500), + sizeof (gawCpyThruDataXXXX)} + , + { + 0x0600, + gawCpyThruVect0600, + gawCpyThruCode0600, + gawCpyThruDataXXXX, + sizeof (gawCpyThruVect0600), + sizeof (gawCpyThruCode0600), + sizeof (gawCpyThruDataXXXX)} + , + { + 0x0680, + gawCpyThruVect0680, + gawCpyThruCode0680, + gawCpyThruDataXXXX, + sizeof (gawCpyThruVect0680), + sizeof (gawCpyThruCode0680), + sizeof (gawCpyThruDataXXXX)} + , + { + 0x0800, + gawCpyThruVect0800, + gawCpyThruCode0800, + gawCpyThruDataXXXX, + sizeof (gawCpyThruVect0800), + sizeof (gawCpyThruCode0800), + sizeof (gawCpyThruDataXXXX)} + , + { + 0, NULL, NULL, NULL, 0, 0, 0} +}; + +/* */ +/* Modem */ +/* */ + +WORD gawModemData[] = { + /* M3 HSP client data area starts at 0x1100 */ + /* 80H words at 1100H */ + + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + + /* 80H words at 1180H */ + + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + +#ifdef NT_MODEL + /* 80H words at 1200H */ + + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + + /* 80H words at 1280H */ + + 0 /*#include "modemntd.dat" */ +#else + /* 80H words at 1200H */ + + 0 /*#include "modemd.dat" */ +#endif +}; + +WORD gawModemVect400[] = { + 0x7980, 0x0400, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +#ifdef NT_MODEL + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x7980, 0x0449, +#else + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x7980, 0x0449, +#endif + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000 +}; + +WORD gawModemVect800[] = { + 0x7980, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +#ifdef NT_MODEL + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x7980, 0x0849, +#else + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x7980, 0x0849, +#endif + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000 +}; + +WORD gawModemCode400[] = { +#ifdef NT_MODEL + 0 /*#include "modemnt4.dat" */ +#else + 0 /*#include "400modem.dat" */ +#endif +}; + +WORD gawModemCode800[] = { +#ifdef NT_MODEL + 0 /*#include "modemnt8.dat" */ +#else + 0 /*#include "800modem.dat" */ +#endif +}; + +CLIENT_BIN gasModemVectCode[] = { + { + 0x0400, + gawModemVect400, + gawModemCode400, + gawModemData, + sizeof (gawModemVect400), + sizeof (gawModemCode400), + sizeof (gawModemData)} + , + { + 0x0800, + gawModemVect800, + gawModemCode800, + gawModemData, + sizeof (gawModemVect800), + sizeof (gawModemCode800), + sizeof (gawModemData)} + , + { + 0, NULL, NULL, NULL, 0, 0, 0} +}; + + +/* */ +/* Positional 3D */ +/* */ +/* Note: Data image contains 25 words (first 22 are CDATA_HEADER + */ +/* kernel spare, next 3 are dpaddr, control_enabled and current_count */ +/* for Pos3d) */ +/* */ + +WORD gawPos3DDataXXXX[] = { + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000 +}; + +WORD gawPos3DVect0400[] = { + 0x7980, 0x0400, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000 +}; + +WORD gawPos3DCode0400[] = { + 0 /*#include "4pos3d.dat" */ +}; + +WORD gawPos3DVect0800[] = { + 0x7980, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000 +}; + +WORD gawPos3DCode0800[] = { + 0 /*#include "8pos3d.dat" */ +}; + +CLIENT_BIN gasPos3DVectCode[] = { + { + 0x0400, + gawPos3DVect0400, + gawPos3DCode0400, + gawPos3DDataXXXX, + sizeof (gawPos3DVect0400), + sizeof (gawPos3DCode0400), + sizeof (gawPos3DDataXXXX)} + , + { + 0x0800, + gawPos3DVect0800, + gawPos3DCode0800, + gawPos3DDataXXXX, + sizeof (gawPos3DVect0800), + sizeof (gawPos3DCode0800), + sizeof (gawPos3DDataXXXX)} + , + { + 0, NULL, NULL, NULL, 0, 0, 0} +}; + +/* */ +/* Speaker Virtualization */ +/* */ + +WORD gawSpkVirtDataXXXX[] = { + 0x0000 +}; + +WORD gawSpkVirtVect0400[] = { + 0x7980, 0x0400, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000 +}; + +WORD gawSpkVirtCode0400[] = { + 0 /*#include "4vmax.dat" */ +}; + +WORD gawSpkVirtVect0800[] = { + 0x7980, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000 +}; + +WORD gawSpkVirtCode0800[] = { + 0 /*#include "8vmax.dat" */ +}; + +CLIENT_BIN gasSpkVirtVectCode[] = { + { + 0x0400, + gawSpkVirtVect0400, + gawSpkVirtCode0400, + gawSpkVirtDataXXXX, + sizeof (gawSpkVirtVect0400), + sizeof (gawSpkVirtCode0400), + sizeof (gawSpkVirtDataXXXX)} + , + { + 0x0800, + gawSpkVirtVect0800, + gawSpkVirtCode0800, + gawSpkVirtDataXXXX, + sizeof (gawSpkVirtVect0800), + sizeof (gawSpkVirtCode0800), + sizeof (gawSpkVirtDataXXXX)} + , + { + 0, NULL, NULL, NULL, 0, 0, 0} +}; + +/* */ +/* CRL Speaker Virtualization */ +/* */ + +WORD gawSpkVirtDataXXXX_CRL[] = { + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000 +}; + +WORD gawSpkVirtVect0400_CRL[] = { + 0x7980, 0x0400, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000 +}; + +WORD gawSpkVirtCode0400_CRL[] = { + 0 /*#include "4spkvirt.dat" */ +}; + +WORD gawSpkVirtVect0800_CRL[] = { + 0x7980, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000 +}; + +WORD gawSpkVirtCode0800_CRL[] = { + 0 /*#include "8spkvirt.dat" */ +}; + +CLIENT_BIN gasSpkVirtVectCode_CRL[] = { + { + 0x0400, + gawSpkVirtVect0400_CRL, + gawSpkVirtCode0400_CRL, + gawSpkVirtDataXXXX_CRL, + sizeof (gawSpkVirtVect0400_CRL), + sizeof (gawSpkVirtCode0400_CRL), + sizeof (gawSpkVirtDataXXXX_CRL)} + , + { + 0x0800, + gawSpkVirtVect0800_CRL, + gawSpkVirtCode0800_CRL, + gawSpkVirtDataXXXX_CRL, + sizeof (gawSpkVirtVect0800_CRL), + sizeof (gawSpkVirtCode0800_CRL), + sizeof (gawSpkVirtDataXXXX_CRL)} + , + { + 0, NULL, NULL, NULL, 0, 0, 0} +}; + +/* */ +/* Sample Rate Conversion */ +/* */ + +WORD gawSRCDataXXXX[] = { + 0x0000 +}; + + +WORD gawSRCVect0400[] = { + 0x7980, 0x0400, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawSRCCode0400[] = { + 0 /*#include "400src36.dat" */ +}; + +WORD gawSRCVect0500[] = { + 0x7980, 0x0500, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawSRCCode0500[] = { + 0 /*#include "500src36.dat" */ +}; + +WORD gawSRCVect0600[] = { + 0x7980, 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawSRCCode0600[] = { + 0 /*#include "600src36.dat" */ +}; + +WORD gawSRCVect0800[] = { + 0x7980, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawSRCCode0800[] = { + 0 /*#include "800src36.dat" */ +}; + +CLIENT_BIN gasSRCVectCode[] = { + { + 0x0400, + gawSRCVect0400, + gawSRCCode0400, + gawSRCDataXXXX, + sizeof (gawSRCVect0400), + sizeof (gawSRCCode0400), + sizeof (gawSRCDataXXXX)} + , + { + 0x0500, + gawSRCVect0500, + gawSRCCode0500, + gawSRCDataXXXX, + sizeof (gawSRCVect0500), + sizeof (gawSRCCode0500), + sizeof (gawSRCDataXXXX)} + , + { + 0x0600, + gawSRCVect0600, + gawSRCCode0600, + gawSRCDataXXXX, + sizeof (gawSRCVect0600), + sizeof (gawSRCCode0600), + sizeof (gawSRCDataXXXX)} + , + { + 0x0800, + gawSRCVect0800, + gawSRCCode0800, + gawSRCDataXXXX, + sizeof (gawSRCVect0800), + sizeof (gawSRCCode0800), + sizeof (gawSRCDataXXXX)} + , + { + 0, NULL, NULL, NULL, 0, 0, 0} +}; + +/* */ +/* MINI Sample Rate Conversion */ +/* */ + +WORD gawMINISRCDataXXXX[] = { + 0x0000 +}; + +WORD gawMINISRCVect0400[] = { + 0x7980, 0x0400, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawMINISRCCode0400[] = { +#include "400m_src.dat" +}; + +WORD gawMINISRCVect0500[] = { + 0x7980, 0x0500, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawMINISRCCode0500[] = { +#include "500m_src.dat" +}; + +WORD gawMINISRCVect0600[] = { + 0x7980, 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawMINISRCCode0600[] = { +#include "600m_src.dat" +}; + +WORD gawMINISRCVect0800[] = { + 0x7980, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawMINISRCCode0800[] = { +#include "800m_src.dat" +}; + + +WORD gawMINISRCVect0900[] = { + 0x7980, 0x0900, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawMINISRCCode0900[] = { +#include "900m_src.dat" +}; + + +WORD gawMINISRCVect0A00[] = { + 0x7980, 0x0A00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawMINISRCCode0A00[] = { +#include "a00m_src.dat" +}; + +WORD gawMINISRCVect0A80[] = { + 0x7980, 0x0A80, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawMINISRCCode0A80[] = { +#include "a80m_src.dat" +}; + +CLIENT_BIN gasMINISRCVectCode[] = { + { + 0x0400, + gawMINISRCVect0400, + gawMINISRCCode0400, + gawMINISRCDataXXXX, + sizeof (gawMINISRCVect0400), + sizeof (gawMINISRCCode0400), + sizeof (gawMINISRCDataXXXX)} + , + { + 0x0500, + gawMINISRCVect0500, + gawMINISRCCode0500, + gawMINISRCDataXXXX, + sizeof (gawMINISRCVect0500), + sizeof (gawMINISRCCode0500), + sizeof (gawMINISRCDataXXXX)} + , + { + 0x0600, + gawMINISRCVect0600, + gawMINISRCCode0600, + gawMINISRCDataXXXX, + sizeof (gawMINISRCVect0600), + sizeof (gawMINISRCCode0600), + sizeof (gawMINISRCDataXXXX)} + , + { + 0x0800, + gawMINISRCVect0800, + gawMINISRCCode0800, + gawMINISRCDataXXXX, + sizeof (gawMINISRCVect0800), + sizeof (gawMINISRCCode0800), + sizeof (gawMINISRCDataXXXX)} + , + { + 0x0900, + gawMINISRCVect0900, + gawMINISRCCode0900, + gawMINISRCDataXXXX, + sizeof (gawMINISRCVect0900), + sizeof (gawMINISRCCode0900), + sizeof (gawMINISRCDataXXXX)} + , + { + 0x0A00, + gawMINISRCVect0A00, + gawMINISRCCode0A00, + gawMINISRCDataXXXX, + sizeof (gawMINISRCVect0A00), + sizeof (gawMINISRCCode0A00), + sizeof (gawMINISRCDataXXXX)} + , + { + 0x0A80, + gawMINISRCVect0A80, + gawMINISRCCode0A80, + gawMINISRCDataXXXX, + sizeof (gawMINISRCVect0A80), + sizeof (gawMINISRCCode0A80), + sizeof (gawMINISRCDataXXXX)} + , + { + 0, NULL, NULL, NULL, 0, 0, 0} +}; + +/* */ +/* SPDIF */ +/* */ + +WORD gawSPDIFDataXXXX[] = { + 0x0000 +}; + +WORD gawSPDIFVect0400[] = { + 0x7980, 0x0400, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawSPDIFCode0400[] = { + 0 /*#include "400spdif.dat" */ +}; + +WORD gawSPDIFVect0500[] = { + 0x7980, 0x0500, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawSPDIFCode0500[] = { + 0 /*#include "500spdif.dat" */ +}; + +WORD gawSPDIFVect0600[] = { + 0x7980, 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawSPDIFCode0600[] = { + 0 /*#include "600spdif.dat" */ +}; + +WORD gawSPDIFVect0700[] = { + 0x7980, 0x0700, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawSPDIFCode0700[] = { + 0 /*#include "700spdif.dat" */ +}; + +WORD gawSPDIFVect0800[] = { + 0x7980, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawSPDIFCode0800[] = { + 0 /*#include "800spdif.dat" */ +}; + +WORD gawSPDIFVect0900[] = { + 0x7980, 0x0900, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawSPDIFCode0900[] = { + 0 /*#include "900spdif.dat" */ +}; + +WORD gawSPDIFVect0A00[] = { + 0x7980, 0x0A00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawSPDIFCode0A00[] = { + 0 /*#include "A00spdif.dat" */ +}; + +CLIENT_BIN gasSPDIFVectCode[] = { + { + 0x0400, + gawSPDIFVect0400, + gawSPDIFCode0400, + gawSPDIFDataXXXX, + sizeof (gawSPDIFVect0400), + sizeof (gawSPDIFCode0400), + sizeof (gawSPDIFDataXXXX)} + , + { + 0x0500, + gawSPDIFVect0500, + gawSPDIFCode0500, + gawSPDIFDataXXXX, + sizeof (gawSPDIFVect0500), + sizeof (gawSPDIFCode0500), + sizeof (gawSPDIFDataXXXX)} + , + { + 0x0600, + gawSPDIFVect0600, + gawSPDIFCode0600, + gawSPDIFDataXXXX, + sizeof (gawSPDIFVect0600), + sizeof (gawSPDIFCode0600), + sizeof (gawSPDIFDataXXXX)} + , + { + 0x0700, + gawSPDIFVect0700, + gawSPDIFCode0700, + gawSPDIFDataXXXX, + sizeof (gawSPDIFVect0700), + sizeof (gawSPDIFCode0700), + sizeof (gawSPDIFDataXXXX)} + , + { + 0x0800, + gawSPDIFVect0800, + gawSPDIFCode0800, + gawSPDIFDataXXXX, + sizeof (gawSPDIFVect0800), + sizeof (gawSPDIFCode0800), + sizeof (gawSPDIFDataXXXX)} + , + { + 0x0900, + gawSPDIFVect0900, + gawSPDIFCode0900, + gawSPDIFDataXXXX, + sizeof (gawSPDIFVect0900), + sizeof (gawSPDIFCode0900), + sizeof (gawSPDIFDataXXXX)} + , + { + 0x0A00, + gawSPDIFVect0A00, + gawSPDIFCode0A00, + gawSPDIFDataXXXX, + sizeof (gawSPDIFVect0A00), + sizeof (gawSPDIFCode0A00), + sizeof (gawSPDIFDataXXXX)} + , + { + 0, NULL, NULL, NULL, 0, 0, 0} +}; + + +#ifndef NT_MODEL +/* */ +/* FM client is a special case */ +/* */ +/* Note: If FM .dat images without passthru support are used */ +/* PASSTHRU_SIZE can be set to zero. */ +/* */ + +#define PASSTHRU_SIZE 256 + +#if 0 +WORD gawFMData[1024 + PASSTHRU_SIZE] = { +#include "fm_d1000.dat" +}; + +WORD gawFMData2[] = { +#include "fm_d2000.dat" +}; + +WORD gawFMVectCode[256 + PASSTHRU_SIZE] = { +#include "fm_c0000.dat" +}; + +WORD gawFMCode[1024] = { +#include "fm_c0800.dat" +}; + +FMCLIENT_BIN gsFMVectCode = { + 0x0800, + 0x2000, + gawFMVectCode, + gawFMCode, + gawFMData, + gawFMData2, + sizeof (gawFMVectCode), + sizeof (gawFMCode), + sizeof (gawFMData), + sizeof (gawFMData2) +}; +#endif +#endif + +WORD MIXER_TASK_NUMBER = 0; + +/*--------------------------------------------------------------------------- */ +/* End of File: kernelbn.h */ +/*--------------------------------------------------------------------------- */ + +/****************************************************************************** + * * + * (C) 1997-1999 ESS Technology, Inc. * + * * + ******************************************************************************/ +PCLIENT_BIN kBinStructAddress (PHWI phwi, DWORD dwClient, DWORD dwSearchKey); + +/* */ +/* Client info */ +/* */ + +HWI ghwi = { + + 0, + 0, + 0, + 0, + + 0, + + 0, 0, + + 0, + + /* client table */ + + { + { + gasCpyThruVectCode, + 0, + MAX_INSTANCE_CPYTHRU, + KDATA_INSTANCE0_CPYTHRU, + 0, + 0, + 0} + , + + { + gasModemVectCode, + 0, + MAX_INSTANCE_MODEM, + KDATA_INSTANCE0_MODEM, + 0, + 0, + 0} + , + + { + gasPos3DVectCode, + 0, + MAX_INSTANCE_POS3D, + KDATA_INSTANCE0_POS3D, + 0, + 0, + 0} + , + + { + gasSpkVirtVectCode, + 0, + MAX_INSTANCE_SPKVIRT, + KDATA_INSTANCE0_SPKVIRT, + 0, + 0, + 0} + , + + { + gasSpkVirtVectCode_CRL, + 0, + MAX_INSTANCE_SPKVIRT, + KDATA_INSTANCE0_SPKVIRT, + 0, + 0, + 0} + , + + { + gasSRCVectCode, + 0, + MAX_INSTANCE_SRC, + KDATA_INSTANCE0_SRC, + 0, + 0, + 0} + , + + { + gasMINISRCVectCode, + 0, + MAX_INSTANCE_MINISRC, + KDATA_INSTANCE0_MINISRC, + 0, + 0, + 0} + , + + { + gasSPDIFVectCode, + 0, + MAX_INSTANCE_SPDIF, + KDATA_INSTANCE0_SPDIF, + 0, + 0, + 0} + + } + , + +#if (F_FREE || (F_END != -1)) +#error Assumption about storage flags failed. +#endif + + /* task resource list */ + + { + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + + (WORD) F_END} + , + + /* Copy Through resource list */ + + { + F_FREE, F_FREE, /* AY reduce to 2 for SPDIF IN */ + + (WORD) F_END} + , + + /* Modem resource list */ + + { + F_FREE, + + (WORD) F_END} + , + + /* Positional 3D resource list */ + + { + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, + + (WORD) F_END} + , + + /* Speaker Virtualization resource list */ + + { + F_FREE, + + (WORD) F_END} + , + + /* Sample Rate Conversion resource list */ + + { + F_FREE, F_FREE, + + (WORD) F_END} + , + + /* MINI Sample Rate Conversion resource list */ + + { + F_FREE, F_FREE, + F_FREE, F_FREE, + + (WORD) F_END} + , + + /* SPDIF resource list */ + + { + F_FREE, + + (WORD) F_END} + , + + /* DMA resource list */ + + { + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, + + (WORD) F_END} + , + + /* ADC1 resource list */ + + { + F_FREE, + + (WORD) F_END} + , + + /* ADC2 resource list */ + + { + F_FREE, + + (WORD) F_END} + , + + /* CD resource list */ + { + F_FREE, + + (WORD) F_END} + , + + /* MIC resource list */ + + { + F_FREE, + + (WORD) F_END} + , + + /* I2S resource list */ + + { + F_FREE, + + (WORD) F_END} + , + + /* CHI resource list */ + + { + F_FREE, + + (WORD) F_END} + , + + + /* SPDIF IN resource list */ + + { + F_FREE, + + (WORD) F_END} + , + + /* MIXER resource list */ + { + F_FREE, F_FREE, + F_FREE, F_FREE, + F_FREE, F_FREE, + F_FREE, F_FREE, + F_FREE, F_FREE, + + (WORD) F_END} + , + + /*AY */ + /* FMIXER resource list */ + { + F_FREE, + + (WORD) F_END} + , + + /* RMIXER resource list */ + { + F_FREE, + + (WORD) F_END} + , + + /* DSP code memory map */ + + 0, 0, 0, 0, + + 0, 0, 0, 0, + + { + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + + (BYTE) F_END} + , + + /* DSP data memory map */ + + { + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + + (BYTE) F_END} + , + + /* DSP vector list */ + + { + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE} + +}; + +/* */ +/* Memory map images */ +/* */ + +#if (NUM_UNITS_KERNEL_CODE != 16) +#error Assumption about kernel code size failed. +#endif + + +BYTE gabRevBCodeMemoryMapImage[] = { + F_USED, F_USED, F_USED, F_USED, /* 0000 - 03FF */ + F_USED, F_USED, F_USED, F_USED, + F_USED, F_USED, F_USED, F_USED, + F_USED, F_USED, F_USED, F_USED, + + F_FREE, F_FREE, F_FREE, F_FREE, /* 0400 - 07FF */ + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + + F_FREE, F_FREE, F_FREE, F_FREE, /* 0800 - 0BFF */ + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + + (BYTE) F_END +}; + + +#if (NUM_UNITS_KERNEL_DATA != 2) +#error Assumption about kernel data size failed. +#endif +#if (KDATA_BASE_ADDR != 0x1000) +#error Assumption about kernel data memory location failed. +#endif + + +BYTE gabRevBDataMemoryMapImage[] = { + F_USED, F_USED, F_FREE, F_FREE, /* 1000 - 17FF */ + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + + F_FREE, F_FREE, F_FREE, F_FREE, /* 1800 - 1BFF */ + F_FREE, F_FREE, F_FREE, F_FREE, + + F_USED, F_USED, F_USED, F_USED, /* 1C00 - 1FFF */ + F_USED, F_USED, F_USED, F_USED, + + F_USED, F_USED, F_USED, F_USED, /* 2000 - 27FF */ + F_USED, F_USED, F_USED, F_USED, + F_USED, F_USED, F_USED, F_USED, + F_USED, F_USED, F_USED, F_USED, + + F_USED, F_USED, F_USED, F_USED, /* 2800 - 2BFF */ + F_USED, F_USED, F_USED, F_USED, + + (BYTE) F_END +}; diff --git a/attic/drv/oss_allegro/allegro_util.inc b/attic/drv/oss_allegro/allegro_util.inc new file mode 100644 index 0000000..253508d --- /dev/null +++ b/attic/drv/oss_allegro/allegro_util.inc @@ -0,0 +1,1295 @@ +/* + * allegro_util.inc -- ESS Technology allegro audio driver. + * + * Copyright (C) 1992-2000 Don Kim (don.kim@esstech.com) + * + */ + +#define DOCKF_DOCKED 0x00000001 /* Default Un-Docked */ +#define DOCKF_DEST_CODEC2 0x00000008 /* Tells VxD CODEC2 active */ +#define HW_INIT_SET_ACTIVE_ACRW 0x00000003 /* Sets the active AC Read/Write */ +#define HW_INIT_SET_ACTIVE_ACINTF 0x00000004 /* ... AC Intf (Local or Remote) */ + +VOID CodecReset (void); +void Set2Use36Mhz (void); +void HWMGR_EnableRemoteCodec (allegro_devc * devc, BOOLEAN enable); + +#ifdef later +VOID CloseModem (); +#endif +extern PHWI gphwi; +extern oss_device_t *allegro_osdev; + +#define CODEC_TYPE_AC97 1 +#define CODEC_TYPE_ESS 2 + +#define DSP33MHZ 0 +#define DSP36MHZ 1 +#define DSP49MHZ 2 + +static unsigned char bChipType; +static unsigned char fRemoteCodec; +static unsigned char bCodec; +static unsigned char gbHwVolEnabled = TRUE; +static unsigned char bEapdSupportMode; +static unsigned int wEapdGPOPolarity_Port; +static unsigned char bEnable4Speaker; +BOOL IsAC3Format = FALSE; +BOOL g4Speaker = FALSE; + +/* + * DOCK + */ +static WORD gwDockVal; +UCHAR bEnableDockDetect = TRUE; +UCHAR bDockingDetectGPIPort = 0; /* TODO: What is the right value */ +static WORD wDockedMask; +static WORD wDockedValue; +UCHAR bMonoOutputSelect = 0; +static WORD gwDefaultMonoOutVol; +int bHwVolCtrlMode = -1; +static ULONG ulCodec; +#define NEC_VENDOR_ID3 0x80F11033 +void HwRelease (allegro_devc * devc); +#define WriteLego HWMGR_WriteCodecData +PCLIENT_INST pClient_SPDIFIN = NULL; +BOOL fSPDIFOUT = FALSE; + + +#if 0 +void +dDbgOut (char *sz, ...) +{ + char buf[256]; + va_list va; + va_start (va, sz); + vsprintf (buf, sz, va); + va_end (va); + printk (buf); + printk ("\n"); +} +#endif + +void +HwSetSystemParameter (allegro_devc * devc, DWORD dwValue) +{ + switch (dwValue >> 16) + { + case HW_INIT_SET_ACTIVE_ACRW: /*3 */ + { + dprintf1 (("ACRW %x", dwValue & DOCKF_DEST_CODEC2)); + + /* + * Set the active AC out direction + */ + if ((WORD) dwValue & DOCKF_DEST_CODEC2) /* In/Out AC2 */ + HWMGR_EnableRemoteCodec (devc, TRUE); + else + HWMGR_EnableRemoteCodec (devc, FALSE); + } + break; + + case HW_INIT_SET_ACTIVE_ACINTF: /*4 */ + { + WORD wTmp; + + dprintf1 (("ACINTF %x", dwValue)); + if (!(dwValue & DOCKF_DOCKED)) /* Nothing there */ + { + /* CODEC DAC I/F set to local only */ + wTmp = inpw (devc->osdev, devc->base + 0x3a); + wTmp &= 0xFFF3; /* [3:2] = "00" */ + outpw (devc->osdev, devc->base + 0x3a, wTmp); + + /* CODEC ADC I/F set to local only */ + wTmp = inpw (devc->osdev, devc->base + 0x3c); + wTmp &= 0xFFF3; /* [3:2] = "00" */ + outpw (devc->osdev, devc->base + 0x3c, wTmp); + } + else + { /* DOCKED */ + /* CODEC DAC I/F set to local + remote */ + wTmp = inpw (devc->osdev, devc->base + 0x3a); + wTmp &= 0xFFF3; + wTmp |= 0x000C; /* [3:2] = "11" */ + outpw (devc->osdev, devc->base + 0x3a, wTmp); + + /* CODEC ADC I/F set to remote AC2 (or both??) */ + wTmp = inpw (devc->osdev, devc->base + 0x3c); + wTmp &= 0xFFF3; + wTmp |= 0x000C; /* [3:2] = "11" */ + outpw (devc->osdev, devc->base + 0x3c, wTmp); + } + } + break; + } +} + +VOID +PCIWrite (allegro_devc * devc, WORD address, ULONG value) +{ + + pci_write_config_dword (devc->osdev, address, value); + +} + +ULONG +PCIRead (allegro_devc * devc, WORD address) +{ + unsigned int dw; + pci_read_config_dword (devc->osdev, address, &dw); + return dw; +} + +#ifdef DEBUGINTERFACE +void +dumpreg (WORD programid, WORD index, WORD value, WORD * out) +{ + ULONG dwData; + + switch (programid) + { + case 1: /* aggr */ + *out = inpw (devc->osdev, devc->base + index); + break; + + case 2: /* aggw */ + outpw (devc->osdev, devc->base + index, value); + break; + + case 3: /* legor */ + HWMGR_ReadCodecData (devc, devc->osdev, index, out); + break; + + case 4: /* legow */ + HWMGR_WriteCodecData (devc, (UCHAR) index, value); + break; + + case 5: /* pciar */ + index &= ~0x1; /* make sure it's even address */ + dwData = PCIRead (devcv, index & ~0x3); + if ((index % 4) == 0) + *out = (WORD) dwData; + else + *out = (WORD) (dwData >> 16); + break; + + case 6: /* pciaw */ + index &= ~0x1; /* make sure it's even address */ + dwData = PCIRead (devc, index & ~0x3); + if ((index % 4) == 0) + { + dwData &= ~0xffff; + dwData |= value; + } + else + { + dwData &= 0xffff; + dwData |= (value << 16); + } + PCIWrite (devc, (index & ~0x3), dwData); + break; + } +} +#endif /* DEBUGINTERFACE */ + +void +DelayMillisec (int millisec) +{ + int count; + + millisec = millisec * 1000 / 50; + for (count = 0; count < millisec; count++) + KeStallExecutionProcessor (50); +} /* DelayMillisec */ + +/* -------------------------------------------------------------------------- */ + +UCHAR +HWMGR_ReadDataByte (allegro_devc * devc, UCHAR Index) +{ + return READ_PORT_UCHAR (devc->osdev, devc->base + Index); +} /* HWMGR_ReadDataByte */ + + +USHORT +HWMGR_ReadDataWord (allegro_devc * devc, UCHAR Index) +{ + return READ_PORT_USHORT (devc->osdev, devc->base + Index); +} /* HWMGR_ReadDataWord */ + + +void +HWMGR_WriteDataByte (allegro_devc * devc, UCHAR Index, UCHAR Value) +{ + WRITE_PORT_UCHAR (devc->osdev, devc->base + Index, Value); +} /* HWMGR_WriteDataByte */ + + +void +HWMGR_WriteDataWord (allegro_devc * devc, UCHAR Index, USHORT Value) +{ + WRITE_PORT_USHORT (devc->osdev, devc->base + Index, Value); +} /* HWMGR_WriteDataWord */ + + +void +HWMGR_RestoreACLink (allegro_devc * devc) +{ + int i; + USHORT wDataCodec; + USHORT wDataIn; + USHORT wDataOut; + USHORT wControl = HWMGR_ReadDataWord (devc, RING_BUS_CTRL_A); + + HWMGR_WriteDataWord (devc, RING_BUS_CTRL_A, (USHORT) (wControl & + ~SERIAL_AC_LINK_ENABLE)); + KeStallExecutionProcessor (50); + HWMGR_WriteDataWord (devc, RING_BUS_CTRL_A, wControl); + + wDataCodec = HWMGR_ReadDataWord (devc, RING_BUS_CTRL_B); + wDataIn = HWMGR_ReadDataWord (devc, SDO_IN_DEST_CTRL); + wDataOut = HWMGR_ReadDataWord (devc, SDO_OUT_DEST_CTRL); + + HWMGR_WriteDataWord (devc, SDO_OUT_DEST_CTRL, (USHORT) (wDataOut & + ~COMMAND_ADDR_OUT)); + HWMGR_WriteDataWord (devc, SDO_IN_DEST_CTRL, (USHORT) (wDataIn & + ~STATUS_ADDR_IN)); + HWMGR_WriteDataWord (devc, RING_BUS_CTRL_B, (USHORT) (wDataCodec & + ~SECOND_CODEC_ID_MASK)); + + /* power down DAC to resynchronize after AC-link change */ + HWMGR_WriteDataWord (devc, CODEC_DATA, AC97_PR1); + HWMGR_WriteDataByte (devc, CODEC_COMMAND, AC97_POWER_DOWN_CTRL); + for (i = 0; i < 1000; i++) + if (!(HWMGR_ReadDataByte (devc, CODEC_STATUS) & CODEC_BUSY_B)) + break; + KeStallExecutionProcessor (1); + HWMGR_WriteDataWord (devc, CODEC_DATA, 0); + HWMGR_WriteDataByte (devc, CODEC_COMMAND, AC97_POWER_DOWN_CTRL); + for (i = 0; i < 1000; i++) + if (!(HWMGR_ReadDataByte (devc, CODEC_STATUS) & CODEC_BUSY_B)) + break; + HWMGR_WriteDataWord (devc, RING_BUS_CTRL_B, wDataCodec); + HWMGR_WriteDataWord (devc, SDO_IN_DEST_CTRL, wDataIn); + HWMGR_WriteDataWord (devc, SDO_OUT_DEST_CTRL, wDataOut); +} /* HWMGR_RestoreACLink */ + +BOOLEAN +HWMGR_ReadCodecData (allegro_devc * devc, UCHAR Index, PUSHORT Value) +{ + int i; + + *Value = 0; + HWMGR_WriteDataByte (devc, CODEC_COMMAND, (UCHAR) (CODEC_READ_B | Index)); + for (i = 0; i < 1000; i++) + { + if (!(HWMGR_ReadDataByte (devc, CODEC_STATUS) & CODEC_BUSY_B)) + { + *Value = HWMGR_ReadDataWord (devc, CODEC_DATA); + return TRUE; + } + } + if (CODEC_TYPE_ESS == bCodec) + HWMGR_RestoreACLink (devc); + + return FALSE; +} /* HWMGR_ReadCodecData */ + + +BOOLEAN +HWMGR_WriteCodecData (allegro_devc * devc, UCHAR Index, USHORT Value) +{ + int i; + + HWMGR_WriteDataWord (devc, CODEC_DATA, Value); + HWMGR_WriteDataByte (devc, CODEC_COMMAND, Index); + for (i = 0; i < 1000; i++) + { + if (!(HWMGR_ReadDataByte (devc, CODEC_STATUS) & CODEC_BUSY_B)) + { + return TRUE; + } + } + if (CODEC_TYPE_ESS == bCodec) + HWMGR_RestoreACLink (devc); + return FALSE; +} /* HWMGR_WriteCodecData */ + +void +HWMGR_EnableExternalAmp (allegro_devc * devc, BOOLEAN enable) +{ + USHORT wDirection; + USHORT wGPO; + USHORT wGPO2; + USHORT wPolarity; + USHORT wPolarity2; + + /* + * by default, setup for reference board + */ + if (bEapdSupportMode == 0) + { + bEapdSupportMode = 1; + if (bChipType >= M3_1998) + wEapdGPOPolarity_Port = 0x1100; + else + { + wEapdGPOPolarity_Port = 0x1800; + if (bChipType == 2) + wEapdGPOPolarity_Port = 0x1c00; + if (bEnable4Speaker) + wEapdGPOPolarity_Port = 0x1600; + } + } + + dprintf3 (("Mode=%x PPort=%x", bEapdSupportMode, wEapdGPOPolarity_Port)); + wGPO2 = wPolarity2 = 0; + switch (bEapdSupportMode) + { + case 0: + break; + case 2: + wGPO2 = wEapdGPOPolarity_Port & 0x0F; + wPolarity2 = wEapdGPOPolarity_Port >> 4 & 0x0F; + if (enable) + wPolarity2 = !wPolarity2; + wPolarity2 = wPolarity2 << wGPO2; + wGPO2 = 1 << wGPO2; + wGPO = wEapdGPOPolarity_Port >> 8 & 0x0F; + wPolarity = wEapdGPOPolarity_Port >> 12; + if (enable) + wPolarity = !wPolarity; + wPolarity = wPolarity << wGPO; + wGPO = 1 << wGPO; + wGPO |= wGPO2; + wPolarity |= wPolarity2; + HWMGR_WriteDataWord (devc, GPIO_MASK, (USHORT) ~ wGPO); + wDirection = HWMGR_ReadDataWord (devc, GPIO_DIRECTION) | wGPO; + HWMGR_WriteDataWord (devc, GPIO_DIRECTION, wDirection); + HWMGR_WriteDataWord (devc, GPIO_DATA, (USHORT) (GPO_SECONDARY_AC97 | + GPO_PRIMARY_AC97 | + wPolarity)); + HWMGR_WriteDataWord (devc, GPIO_MASK, 0xFFFF); + break; + + case 1: + wGPO = wEapdGPOPolarity_Port >> 8 & 0x0F; + wPolarity = wEapdGPOPolarity_Port >> 12; + if (enable) + wPolarity = !wPolarity; + wPolarity = wPolarity << wGPO; + wGPO = 1 << wGPO; + wGPO |= wGPO2; + wPolarity |= wPolarity2; + HWMGR_WriteDataWord (devc, GPIO_MASK, (USHORT) ~ wGPO); + wDirection = HWMGR_ReadDataWord (devc, GPIO_DIRECTION) | wGPO; + HWMGR_WriteDataWord (devc, GPIO_DIRECTION, wDirection); + HWMGR_WriteDataWord (devc, GPIO_DATA, (USHORT) (GPO_SECONDARY_AC97 | + GPO_PRIMARY_AC97 | + wPolarity)); + HWMGR_WriteDataWord (devc, GPIO_MASK, 0xFFFF); + break; + } +} /* HWMGR_EnableExternalAmp */ + + +void +HWMGR_EnableRemoteCodec (allegro_devc * devc, BOOLEAN enable) +{ + USHORT wData; + +/* This function MUST be in a non-paged segment */ +/* PAGED_CODE(); */ + if (enable == fRemoteCodec) + return; + fRemoteCodec = enable; + if (enable) + { + + /* enable remote codec */ + wData = HWMGR_ReadDataWord (devc, RING_BUS_CTRL_B); + wData = (wData & ~SECOND_CODEC_ID_MASK) | 1; + HWMGR_WriteDataWord (devc, RING_BUS_CTRL_B, wData); + wData = HWMGR_ReadDataWord (devc, SDO_OUT_DEST_CTRL); + wData = (wData & ~COMMAND_ADDR_OUT) | 1; + HWMGR_WriteDataWord (devc, SDO_OUT_DEST_CTRL, wData); + wData = HWMGR_ReadDataWord (devc, SDO_IN_DEST_CTRL); + wData = (wData & ~STATUS_ADDR_IN) | 1; + HWMGR_WriteDataWord (devc, SDO_IN_DEST_CTRL, wData); + } + else + { + + /* disable remote codec */ + wData = HWMGR_ReadDataWord (devc, RING_BUS_CTRL_B); + wData = wData & ~SECOND_CODEC_ID_MASK; + HWMGR_WriteDataWord (devc, RING_BUS_CTRL_B, wData); + wData = HWMGR_ReadDataWord (devc, SDO_OUT_DEST_CTRL); + wData = wData & ~COMMAND_ADDR_OUT; + HWMGR_WriteDataWord (devc, SDO_OUT_DEST_CTRL, wData); + wData = HWMGR_ReadDataWord (devc, SDO_IN_DEST_CTRL); + wData = wData & ~STATUS_ADDR_IN; + HWMGR_WriteDataWord (devc, SDO_IN_DEST_CTRL, wData); + } +} /* HWMGR_EnableRemoteCodec */ + +#define AKM_CODEC 0x414B4D +#define TRA_CODEC 0x545241 +#define ESS_CODEC 0x458383 +#define STAC9721_CODEC 0x838476 +#define STAC9721_REV_C 0x09 +#define STAC9721_REV_D 0x44 + +BOOLEAN +HWMGR_ReadVendorId (allegro_devc * devc, OUT PULONG pulData, OUT PBYTE pbRev) +{ + USHORT wData; + + *pulData = 0; + if (HWMGR_ReadCodecData (devc, AC97_VENDOR_ID1, &wData)) + { + *pulData = (ULONG) wData << 16; + if (HWMGR_ReadCodecData (devc, AC97_VENDOR_ID2, &wData)) + { + *pulData |= wData; + *pbRev = (UCHAR) * pulData; + *pulData >>= 8; + return TRUE; + } + *pulData = 0; + } + return FALSE; +} /* HWMGR_ReadVendorId */ + +void +HWMGR_ResetCodec (allegro_devc * devc) +{ + ULONG ulData; + USHORT wData; + USHORT wDirection; + int delay_count; + int reset_count; + int wait_count; + int DoReset = TRUE; + BYTE bSaveCodec; + BYTE bRev; + + delay_count = reset_count = wait_count = 0; + wDirection = HWMGR_ReadDataWord (devc, GPIO_DIRECTION); + + /* not sure if this applies for Allegro-1/Maestro-3 */ + if (PCIRead (devc, PCI_USER_CONFIG) & EXT_PCI_MASTER_ENABLE) + { + + /* GPIO4 = output */ + wDirection |= 0x10; + } + + HWMGR_EnableRemoteCodec (devc, FALSE); + + /* set bCodec to undefined so that ReadCodecData will not try to restore */ + /* AC-link */ + bSaveCodec = bCodec; + bCodec = 0; + + /* If we can read codec, skip codec reset to avoid pop sound. */ + /* HP Omnibook M3 does not setup AC-link correctly */ + HWMGR_WriteDataWord (devc, RING_BUS_CTRL_A, IO_SRAM_ENABLE); + + /* delay at least 20 us if disabling AC-link */ + KeStallExecutionProcessor (20); + HWMGR_WriteDataWord (devc, RING_BUS_CTRL_A, + IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE); + KeStallExecutionProcessor (1); + if (HWMGR_ReadVendorId (devc, &ulData, &bRev)) + { + + dprintf1 (("codec1 id = %x", ulData)); + /* do not need to reset */ + DoReset = FALSE; + } + if (ulData != 0 && ulData != 0xFFFFFF) + { + ulCodec = ulData; + bCodec = CODEC_TYPE_AC97; + if (TRA_CODEC == ulCodec) + { + + /* fix for tritech 2.0a codec */ + HWMGR_WriteCodecData (devc, 0x2A, 0x0001); + HWMGR_WriteCodecData (devc, 0x2C, 0x0000); + HWMGR_WriteCodecData (devc, 0x2C, 0xFFFF); + } + else if (ESS_CODEC == ulCodec) + { + bCodec = CODEC_TYPE_ESS; + } + } + else + { + if (bChipType >= M3_1998) + bCodec = CODEC_TYPE_AC97; + else + bCodec = CODEC_TYPE_ESS; + } + if (bSaveCodec) + { + bCodec = bSaveCodec; + } + + dprintf1 (("reset codec1 bCodec=%d DoReset=%d", bCodec, DoReset)); + /* reset primary codec */ + if (DoReset) + { + + /* regular AC97 codec */ + if (bChipType >= M3_1998) + { + delay_count = 20; +#if CRYSTAL_CODEC_FIX + if (!ulCodec || CRY_CODEC == ulCodec) + { + wait_count = 500; + } + else + { + wait_count = 20; + } +#else + wait_count = 20; +#endif + } + else + { + delay_count = 50; + + /* delay 800 ms!? */ + wait_count = 800; + } + reset_count = 0; + + RESET_CODEC: + + HWMGR_WriteDataWord (devc, RING_BUS_CTRL_A, IO_SRAM_ENABLE); + + /* delay at least 20 us if disabling AC-link */ + KeStallExecutionProcessor (20); + + /* write GPO0 */ + HWMGR_WriteDataWord (devc, GPIO_DIRECTION, + wDirection & ~GPO_PRIMARY_AC97); + HWMGR_WriteDataWord (devc, GPIO_MASK, (USHORT) ~ GPO_PRIMARY_AC97); + HWMGR_WriteDataWord (devc, GPIO_DATA, 0x000); + wDirection |= GPO_PRIMARY_AC97; + HWMGR_WriteDataWord (devc, GPIO_DIRECTION, wDirection); + + /* delay 20 ms */ + DelayMillisec (delay_count); + HWMGR_WriteDataWord (devc, GPIO_DATA, GPO_PRIMARY_AC97); + KeStallExecutionProcessor (5); + HWMGR_WriteDataWord (devc, RING_BUS_CTRL_A, + IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE); + HWMGR_WriteDataWord (devc, GPIO_MASK, 0xFFFF); + + /* wait for codec to be ready */ + DelayMillisec (wait_count); + +#if defined( AC97_RESETFIX ) + /* If unable to read from Codec, perform special reset */ + if (!HWMGR_ReadCodecData (devc, AC97_VENDOR_ID1, &wData)) + { + /* Save Serial Link Configuration */ + HWMGR_ReadDataWord (devc, RING_BUS_CTRL_A, &wRingBusReg); + + /* Disable Serial AC Link and Cold Reset Codec */ + HWMGR_WriteDataWord (devc, RING_BUS_CTRL_A, _AC_SDFS_ENABLE); + + /* Delay 20mS */ + for (count = 0; count < 400; count++) + KeStallExecutionProcessor (50); + + /* Enable AC Serial Link */ + HWMGR_WriteDataWord (devc, RING_BUG_CTRL_A, wRingBusReg); + + if (!HWMGR_ReadCodecData (devc, AC97_VENDOR_ID1, &wData)) + { + /* Disable Serial AC Link and Cold Reset Codec */ + HWMGR_WriteDataWord (devc, RING_BUS_CTRL_A, _AC_SDFS_ENABLE); + + /* Warm Reset Codec */ + HWMGR_WriteDataByte (devc, CODEC_COMMAND, 0x00); + /* Delay 20mS */ + for (count = 0; count < 400; count++) + KeStallExecutionProcessor (50); + + /* Enable AC Serial Link */ + HWMGR_WriteDataWord (devc, RING_BUG_CTRL_A, wRingBusReg); + + /* Set AC97 PR4 26h[12] */ + HWMGR_ReadCodecData (devc, AC97_POWER_DOWN_CTRL, &wData); + HWMGR_WriteCodecData (devc, AC97_POWER_DOWN_CTRL, + wData | AC97_PR4); + + /* Warm Reset Codec */ + HWMGR_WriteDataByte (devc, CODEC_COMMAND, 0x00); + /* Delay 20mS */ + for (count = 0; count < 400; count++) + KeStallExecutionProcessor (50); + } + } +#endif + + if (!bCodec) + { + if (HWMGR_ReadVendorId (devc, &ulData, &bRev)) + { + if (ulData != 0 && ulData != 0xFFFFFF) + { + ulCodec = ulData; + bCodec = CODEC_TYPE_AC97; + if (TRA_CODEC == ulCodec) + { + + /* fix for tritech 2.0a codec */ + HWMGR_WriteCodecData (devc, 0x2A, 0x0001); + HWMGR_WriteCodecData (devc, 0x2C, 0x0000); + HWMGR_WriteCodecData (devc, 0x2C, 0xFFFF); + } + else if (ESS_CODEC == ulCodec) + { + bCodec = CODEC_TYPE_ESS; + } + } + } + else + { + if (++reset_count < 20) + { + delay_count += 10; + wait_count += 100; + goto RESET_CODEC; + } + } + if (!bCodec) + { + if (bChipType >= M3_1998) + bCodec = CODEC_TYPE_AC97; + else + bCodec = CODEC_TYPE_ESS; + } + } + } + else if ((wDirection & GPO_PRIMARY_AC97) == 0) + { + HWMGR_WriteDataWord (devc, GPIO_MASK, (USHORT) ~ GPO_PRIMARY_AC97); + HWMGR_WriteDataWord (devc, GPIO_DATA, GPO_PRIMARY_AC97); + wDirection |= GPO_PRIMARY_AC97; + HWMGR_WriteDataWord (devc, GPIO_DIRECTION, wDirection); + HWMGR_WriteDataWord (devc, GPIO_MASK, 0xFFFF); + } + + dprintf1 (("Codec:%d\n", bCodec)); + + if (CODEC_TYPE_ESS == bCodec) + { + if (HWMGR_ReadCodecData (devc, AC97_CLOCK_DELAY, &wData)) + { + wData &= ~(AC97_CLOCK_DELAY_SEL << AC97_ADC_CDS_SHIFT); + wData |= 18 << AC97_ADC_CDS_SHIFT; + HWMGR_WriteCodecData (devc, AC97_CLOCK_DELAY, wData); + } + else + { + if (++reset_count < 20) + { + delay_count += 10; + wait_count += 100; + goto RESET_CODEC; + } + } + } + + if (gwDockVal) + { + HWMGR_EnableRemoteCodec (devc, TRUE); + + wData = HWMGR_ReadDataWord (devc, RING_BUS_CTRL_B); + wData &= ~(SECOND_AC_ENABLE | SECOND_CODEC_ID_MASK); + HWMGR_WriteDataWord (devc, RING_BUS_CTRL_B, + (USHORT) (wData | SECOND_AC_ENABLE | 1)); + + /* If we can read codec, skip codec reset to avoid pop sound. */ + DoReset = TRUE; + if (HWMGR_ReadVendorId (devc, &ulData, &bRev)) + { + + dprintf1 (("Read:%x,%x\n", ulData, bRev)); + + /* do not need to reset */ + DoReset = FALSE; + } + + /* reset secondary codec */ + if (DoReset) + { + HWMGR_WriteDataWord (devc, RING_BUS_CTRL_A, IO_SRAM_ENABLE); + + /* delay at least 20 us if disabling AC-link */ + KeStallExecutionProcessor (20); + + /* write GPO3 */ + HWMGR_WriteDataWord (devc, GPIO_DIRECTION, + wDirection & ~GPO_SECONDARY_AC97); + HWMGR_WriteDataWord (devc, GPIO_MASK, + (USHORT) ~ GPO_SECONDARY_AC97); + HWMGR_WriteDataWord (devc, GPIO_DATA, 0x000); + wDirection |= GPO_SECONDARY_AC97; + HWMGR_WriteDataWord (devc, GPIO_DIRECTION, wDirection); + + /* delay 20 ms */ + DelayMillisec (20); + HWMGR_WriteDataWord (devc, GPIO_DATA, GPO_SECONDARY_AC97); + + /* delay 20 ms */ + DelayMillisec (20); + HWMGR_WriteDataWord (devc, GPIO_MASK, 0xFFFF); + + HWMGR_WriteDataWord (devc, RING_BUS_CTRL_A, + IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE); + KeStallExecutionProcessor (1); + + /* read vendor id */ + (void) HWMGR_ReadVendorId (devc, &ulData, &bRev); + + dprintf1 (("Reset:%x,%x\n", ulData, bRev)); + } + else if ((wDirection & GPO_SECONDARY_AC97) == 0) + { + HWMGR_WriteDataWord (devc, GPIO_MASK, + (USHORT) ~ GPO_SECONDARY_AC97); + HWMGR_WriteDataWord (devc, GPIO_DATA, GPO_SECONDARY_AC97); + wDirection |= GPO_SECONDARY_AC97; + HWMGR_WriteDataWord (devc, GPIO_DIRECTION, wDirection); + HWMGR_WriteDataWord (devc, GPIO_MASK, 0xFFFF); + } + if (ulData != 0 && ulData != 0xFFFFFF) + { + if (TRA_CODEC == ulData) + { + + /* fix for tritech 2.0a codec */ + HWMGR_WriteCodecData (devc, 0x2A, 0x0001); + HWMGR_WriteCodecData (devc, 0x2C, 0x0000); + HWMGR_WriteCodecData (devc, 0x2C, 0xFFFF); + } + else if (STAC9721_CODEC == ulData) + { + USHORT wStatus; + + if (!HWMGR_ReadCodecData + (devc, AC97_POWER_DOWN_CTRL, &wStatus) || 0 == wStatus) + { + HWMGR_WriteCodecData (devc, 0x76, 0xABBA); + if (STAC9721_REV_D == bRev) + { + HWMGR_WriteCodecData (devc, 0x78, 0x2002); + KeStallExecutionProcessor (20); + HWMGR_WriteCodecData (devc, 0x78, 0x2802); + } + else + { + HWMGR_WriteCodecData (devc, 0x78, 0x3002); + KeStallExecutionProcessor (20); + HWMGR_WriteCodecData (devc, 0x78, 0x3802); + } + } + } + } + HWMGR_EnableRemoteCodec (devc, FALSE); + + HWMGR_WriteDataWord (devc, RING_BUS_CTRL_B, wData); + } +} /* HWMGR_ResetCodec */ + +#if 0 +#define DSP33MHZ 0 +#define DSP36MHZ 1 +#define DSP49MHZ 2 +#endif + + +UCHAR bGray_Code[32] = { + 0x00, 0x01, 0x03, 0x02, 0x07, 0x06, 0x04, 0x05, + 0x0F, 0x0E, 0x0C, 0x0D, 0x08, 0x09, 0x0B, 0x0A, + 0x1F, 0x1E, 0x1C, 0x1D, 0x18, 0x19, 0x1B, 0x1A, + 0x10, 0x11, 0x13, 0x12, 0x17, 0x16, 0x14, 0x15 +}; + +void +HWMGR_SetClockSpeed (allegro_devc * devc, UCHAR speed) +{ + ULONG ulData; + int choice; + int mode; + UCHAR bModeValue[8]; + UCHAR bData; + UCHAR bDelta; + + HWMGR_WriteDataByte (devc, ASSP_CONTROL_B, RESET_ASSP); + + ulData = PCIRead (devc, PCI_ALLEGRO_CONFIG); + ulData &= ~INT_CLK_SELECT; + ulData &= ~(CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2); + PCIWrite (devc, PCI_ALLEGRO_CONFIG, ulData); + + if (DSP36MHZ == speed) + { + ulData = PCIRead (devc, PCI_USER_CONFIG); + ulData &= ~IN_CLK_12MHZ_SELECT; + PCIWrite (devc, PCI_USER_CONFIG, ulData); + + for (mode = 0; mode < 4; mode++) + { + ulData |= INT_CLK_MULT_RESET; + PCIWrite (devc, PCI_ALLEGRO_CONFIG, ulData); + ulData &= ~CLK_MULT_MODE_SELECT; + ulData |= mode << CLK_MULT_MODE_SHIFT; + PCIWrite (devc, PCI_ALLEGRO_CONFIG, ulData); + ulData &= ~INT_CLK_MULT_RESET; + PCIWrite (devc, PCI_ALLEGRO_CONFIG, ulData); + + READ_PORT_UCHAR (devc->osdev, 0x80); + READ_PORT_UCHAR (devc->osdev, 0x80); + READ_PORT_UCHAR (devc->osdev, 0x80); + READ_PORT_UCHAR (devc->osdev, 0x80); + READ_PORT_UCHAR (devc->osdev, 0x80); + READ_PORT_UCHAR (devc->osdev, 0x80); + READ_PORT_UCHAR (devc->osdev, 0x80); + READ_PORT_UCHAR (devc->osdev, 0x80); + bModeValue[mode] = + bGray_Code[HWMGR_ReadDataWord (devc, CLK_MULT_DATA_PORT) >> 5 + & 0x1F]; + } + ulData |= CLK_MULT_MODE_SELECT_2; + for (mode = 0; mode < 4; mode++) + { + ulData |= INT_CLK_MULT_RESET; + PCIWrite (devc, PCI_ALLEGRO_CONFIG, ulData); + ulData &= ~CLK_MULT_MODE_SELECT; + ulData |= mode << CLK_MULT_MODE_SHIFT; + PCIWrite (devc, PCI_ALLEGRO_CONFIG, ulData); + ulData &= ~INT_CLK_MULT_RESET; + PCIWrite (devc, PCI_ALLEGRO_CONFIG, ulData); + + READ_PORT_UCHAR (devc->osdev, 0x80); + READ_PORT_UCHAR (devc->osdev, 0x80); + READ_PORT_UCHAR (devc->osdev, 0x80); + READ_PORT_UCHAR (devc->osdev, 0x80); + READ_PORT_UCHAR (devc->osdev, 0x80); + READ_PORT_UCHAR (devc->osdev, 0x80); + READ_PORT_UCHAR (devc->osdev, 0x80); + READ_PORT_UCHAR (devc->osdev, 0x80); + bModeValue[mode + 4] = + bGray_Code[HWMGR_ReadDataWord (devc, CLK_MULT_DATA_PORT) >> 5 + & 0x1F]; + } +#define Abs(x) ((x)<0) ? -(x) : (x) + bDelta = Abs (bModeValue[0] - 0x10); + choice = 0; + for (mode = 1; mode < 8; mode++) + { + if (bDelta > Abs (bModeValue[mode] - 0x10)) + { + bDelta = Abs (bModeValue[mode] - 0x10); + choice = mode; + } + } + +#if 0 + _Debug_Printf_Service ("mode:%d\n", choice); +#endif + ulData &= ~(CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2); + if (choice > 3) + { + ulData |= CLK_MULT_MODE_SELECT_2; + choice -= 4; + } + ulData |= INT_CLK_MULT_RESET; + PCIWrite (devc, PCI_ALLEGRO_CONFIG, ulData); + ulData |= choice << CLK_MULT_MODE_SHIFT; + PCIWrite (devc, PCI_ALLEGRO_CONFIG, ulData); + ulData &= ~INT_CLK_MULT_RESET; + PCIWrite (devc, PCI_ALLEGRO_CONFIG, ulData); + + ulData |= INT_CLK_SELECT; + PCIWrite (devc, PCI_ALLEGRO_CONFIG, ulData); + READ_PORT_UCHAR (devc->osdev, 0x80); + READ_PORT_UCHAR (devc->osdev, 0x80); + } + else + { + ulData = PCIRead (devc, PCI_USER_CONFIG); + ulData |= IN_CLK_12MHZ_SELECT; + PCIWrite (devc, PCI_USER_CONFIG, ulData); + } + + bData = HWMGR_ReadDataByte (devc, ASSP_CONTROL_A); + bData &= ~(DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT); + bData |= ASSP_0_WS_ENABLE; + switch (speed) + { + case DSP36MHZ: + bData |= DSP_CLK_36MHZ_SELECT; + break; + case DSP49MHZ: + bData |= ASSP_CLK_49MHZ_SELECT; + break; + } + HWMGR_WriteDataByte (devc, ASSP_CONTROL_A, bData); + + HWMGR_WriteDataByte (devc, ASSP_CONTROL_B, RUN_ASSP); +} /* HWMGR_SetClockSpeed */ + +void +HWMGR_SetM3ClockSpeed (allegro_devc * devc, UCHAR speed) +{ + ULONG ulData; + int choice; + int mode; + UCHAR bModeValue[8]; + UCHAR bData; + UCHAR bDelta; + + HWMGR_WriteDataByte (devc, ASSP_CONTROL_B, RESET_ASSP); + + ulData = PCIRead (devc, PCI_ALLEGRO_CONFIG); + if (DSP33MHZ == speed) + ulData &= ~INT_CLK_SRC_NOT_PCI; + else + ulData |= INT_CLK_SRC_NOT_PCI; + ulData &= ~(INT_CLK_MULT_ENABLE | INT_CLK_SELECT); + ulData &= ~(CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2); + PCIWrite (devc, PCI_ALLEGRO_CONFIG, ulData); + + if (DSP36MHZ == speed) + { + ulData = PCIRead (devc, PCI_USER_CONFIG); + ulData |= IN_CLK_12MHZ_SELECT; + PCIWrite (devc, PCI_USER_CONFIG, ulData); + + for (mode = 0; mode < 4; mode++) + { + ulData &= ~INT_CLK_MULT_ENABLE; + PCIWrite (devc, PCI_ALLEGRO_CONFIG, ulData); + ulData &= ~CLK_MULT_MODE_SELECT; + ulData |= mode << CLK_MULT_MODE_SHIFT; + PCIWrite (devc, PCI_ALLEGRO_CONFIG, ulData); + ulData |= INT_CLK_MULT_ENABLE; + PCIWrite (devc, PCI_ALLEGRO_CONFIG, ulData); + + READ_PORT_UCHAR (devc->osdev, 0x80); + READ_PORT_UCHAR (devc->osdev, 0x80); + READ_PORT_UCHAR (devc->osdev, 0x80); + READ_PORT_UCHAR (devc->osdev, 0x80); + READ_PORT_UCHAR (devc->osdev, 0x80); + READ_PORT_UCHAR (devc->osdev, 0x80); + READ_PORT_UCHAR (devc->osdev, 0x80); + READ_PORT_UCHAR (devc->osdev, 0x80); + bModeValue[mode] = + bGray_Code[HWMGR_ReadDataWord (devc, CLK_MULT_DATA_PORT) >> 5 + & 0x1F]; + } + ulData |= CLK_MULT_MODE_SELECT_2; + for (mode = 0; mode < 4; mode++) + { + ulData &= ~INT_CLK_MULT_ENABLE; + PCIWrite (devc, PCI_ALLEGRO_CONFIG, ulData); + ulData &= ~CLK_MULT_MODE_SELECT; + ulData |= mode << CLK_MULT_MODE_SHIFT; + PCIWrite (devc, PCI_ALLEGRO_CONFIG, ulData); + ulData |= INT_CLK_MULT_ENABLE; + PCIWrite (devc, PCI_ALLEGRO_CONFIG, ulData); + + READ_PORT_UCHAR (devc->osdev, 0x80); + READ_PORT_UCHAR (devc->osdev, 0x80); + READ_PORT_UCHAR (devc->osdev, 0x80); + READ_PORT_UCHAR (devc->osdev, 0x80); + READ_PORT_UCHAR (devc->osdev, 0x80); + READ_PORT_UCHAR (devc->osdev, 0x80); + READ_PORT_UCHAR (devc->osdev, 0x80); + READ_PORT_UCHAR (devc->osdev, 0x80); + bModeValue[mode + 4] = + bGray_Code[HWMGR_ReadDataWord (devc, CLK_MULT_DATA_PORT) >> 5 + & 0x1F]; + } + bDelta = Abs (bModeValue[0] - 0x10); + choice = 0; + for (mode = 1; mode < 8; mode++) + { + if (bDelta > Abs (bModeValue[mode] - 0x10)) + { + bDelta = Abs (bModeValue[mode] - 0x10); + choice = mode; + } + } + +#if 0 + _Debug_Printf_Service ("mode:%d\n", choice); +#endif + ulData &= ~(INT_CLK_MULT_ENABLE | CLK_MULT_MODE_SELECT | + CLK_MULT_MODE_SELECT_2); + if (choice > 3) + { + ulData |= CLK_MULT_MODE_SELECT_2; + choice -= 4; + } + PCIWrite (devc, PCI_ALLEGRO_CONFIG, ulData); + ulData |= choice << CLK_MULT_MODE_SHIFT; + PCIWrite (devc, PCI_ALLEGRO_CONFIG, ulData); + ulData |= INT_CLK_MULT_ENABLE; + PCIWrite (devc, PCI_ALLEGRO_CONFIG, ulData); + } + + bData = HWMGR_ReadDataByte (devc, ASSP_CONTROL_A); + bData &= ~(DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT); + bData |= ASSP_0_WS_ENABLE; + switch (speed) + { + case DSP36MHZ: + bData |= DSP_CLK_36MHZ_SELECT; + break; + case DSP49MHZ: + bData |= ASSP_CLK_49MHZ_SELECT; + break; + } + HWMGR_WriteDataByte (devc, ASSP_CONTROL_A, bData); + + HWMGR_WriteDataByte (devc, ASSP_CONTROL_B, RUN_ASSP); +} /* HWMGR_SetM3ClockSpeed */ + + +BOOLEAN +HWMGR_InitKernel (allegro_devc * devc) +{ + ULONG ulData; + + ulData = PCIRead (devc, PCI_ALLEGRO_CONFIG); + ulData &= REDUCED_DEBOUNCE; + + if (gbHwVolEnabled) + { + ulData |= HV_CTRL_ENABLE; + + if (bHwVolCtrlMode == -1) + { + bHwVolCtrlMode = 0; + if (bChipType < M3_1998) + bHwVolCtrlMode = 1; + } + + if (PCIRead (devc, 0x2c) == NEC_VENDOR_ID3) + { + bHwVolCtrlMode |= (0x80 | 0x40); + } + + if (bHwVolCtrlMode & 0x80) + { + bHwVolCtrlMode &= ~0x80; + ulData |= REDUCED_DEBOUNCE; + } + + if (bHwVolCtrlMode & 0x40) + { + bHwVolCtrlMode &= ~0x40; + PCIWrite (devc, PCI_USER_CONFIG, + PCIRead (devc, PCI_USER_CONFIG) | HV_CTRL_TEST); + } + + dprintf1 (("bHwVolCtrlMode=%x", bHwVolCtrlMode)); + + /* default 53/54 pin */ + switch (bHwVolCtrlMode) + { + + /* 44/45 pin */ + case 0x01: + ulData |= HV_BUTTON_FROM_GD; + break; + +#if 0 + /* M3E */ + case 0x02: + break; + /* M3E */ + case 0x03: + break; + /* M3E */ + case 0x04: + break; +#endif + } + } + + ulData |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING; + PCIWrite (devc, PCI_ALLEGRO_CONFIG, ulData); + + ulData = PCIRead (devc, PCI_USER_CONFIG); + ulData |= MIDI_1_ENABLE; + PCIWrite (devc, PCI_USER_CONFIG, ulData); + + if (bChipType >= M3_1998) + HWMGR_SetM3ClockSpeed (devc, DSP49MHZ); + else + /* new Allegro board only works with external 49 Mhz clock */ + HWMGR_SetClockSpeed (devc, DSP49MHZ); + /*ulDSPConnectIn = KCONNECT_ADC1; */ + + /* initialize the DSP kernel */ + if (kInitKernel (devc, &gphwi, 0x1978, 0x10, devc->base, 0) != + KRETURN_SUCCESS) + return FALSE; + +#ifdef later + InitModem (); +#endif + +#ifdef FIXED_MODEM + { + extern DWORD gdwESModem; + extern DWORD DisableModemClient (VOID); + if (gdwESModem) + { + if (kOpenInstance + (gphwi, CLIENT_MODEM, 0, 0x180 * 2, + &pClient_Modem) != KRETURN_SUCCESS) + return FALSE; + DisableModemClient (); + } + } +#endif + + return TRUE; +} /* HWMGR_InitKernel */ + +/* -------------------------------------------------------------------------- */ + +void +HWMGR_InitSystem (allegro_devc * devc) +{ + WORD wData; + DWORD dwVal; + +#if 0 /* this cause zip sound for Compaq. Code here is for problems for older */ + /* allegro chip, new one does not need this any more. */ + /* prevent AC-link deadlocking */ + HWMGR_WriteDataWord (devc, HOST_INT_CTRL, SOFTWARE_RESET_ENABLE); + KeStallExecutionProcessor (5); + HWMGR_WriteDataWord (devc, HOST_INT_CTRL, 0x0); +#endif + + HWMGR_InitKernel (devc); + + if (bEnableDockDetect) + { + wDockedMask = bDockingDetectGPIPort & 0x0F; + wDockedValue = (bDockingDetectGPIPort >> 4 & 0x0F) << wDockedMask; + wDockedMask = 1 << wDockedMask; + gwDockVal = + (HWMGR_ReadDataWord (devc, GPIO_DATA) & wDockedMask) == wDockedValue; + } + else + { + wDockedMask = wDockedValue = 0; + } + + /* force to set correct codec */ + fRemoteCodec = 0xFF; + + HWMGR_ResetCodec (devc); + + /* allegro codec proble from cold boot so one more resetcodec */ + HWMGR_ResetCodec (devc); + + if (CODEC_TYPE_ESS == bCodec) + { + + /* power down DAC to resynchronize after AC-link change */ + HWMGR_WriteCodecData (devc, AC97_POWER_DOWN_CTRL, AC97_PR1); + KeStallExecutionProcessor (1); + } + + /* codec not reset every time */ + HWMGR_WriteCodecData (devc, AC97_POWER_DOWN_CTRL, 0); + HWMGR_EnableExternalAmp (devc, TRUE); + if (gwDockVal) + { + wData = HWMGR_ReadDataWord (devc, RING_BUS_CTRL_B); + wData |= SECOND_AC_ENABLE; + HWMGR_WriteDataWord (devc, RING_BUS_CTRL_B, wData); + } + + HWMGR_ReadCodecData (devc, AC97_GENERAL_PURPOSE, &wData); + if (bMonoOutputSelect) + { + wData |= 0x300; + + HWMGR_WriteCodecData (devc, AC97_MASTER_MONO_VOL, gwDefaultMonoOutVol); + KeStallExecutionProcessor (100); + HWMGR_WriteCodecData (devc, AC97_MASTER_MONO_VOL, gwDefaultMonoOutVol); + } + else + wData &= ~0x300; + HWMGR_WriteCodecData (devc, AC97_GENERAL_PURPOSE, wData); + + /* fix DAC volume at 0x0808 */ + HWMGR_WriteCodecData (devc, AC97_MASTER_VOL, 0x0404); + HWMGR_WriteCodecData (devc, AC97_PCM_OUT_VOL, 0x0404); + + /* Mute the ADC */ + if (!g4Speaker) + HWMGR_WriteCodecData (devc, AC97_RECORD_GAIN, 0x8000); + + gwDSPConnectIn = KCONNECT_ADC1; + + /* + * Undock it first + */ + dwVal = HW_INIT_SET_ACTIVE_ACINTF; + dwVal <<= 16; + HwSetSystemParameter (devc, dwVal); + + /* + * Setup active I/F + */ + dwVal = HW_INIT_SET_ACTIVE_ACINTF; + dwVal <<= 16; + + HwSetSystemParameter (devc, dwVal); +} /* HWMGR_InitSystem */ + + +void +HwRelease (allegro_devc * devc) +{ +#ifdef later + CloseModem (); +#endif + + kTermKernel (devc, gphwi, devc->base); + + HWMGR_EnableExternalAmp (devc, FALSE); + + /* MUTE THE DAMN THING FIRST */ + WriteLego (devc, 0x02, 0x3F3F); /* LOUT1 Master Attenuation (-1.5dB steps: 0000 = 0dB, 3F3F = -94dB, ) */ + + WriteLego (devc, 0x04, 0x9F1F); /* Headphone */ + WriteLego (devc, 0x06, 0x9F1F); /* MonoOut */ + WriteLego (devc, 0x12, 0x9F1F); /* CD to Mixer Level (80=mute; 00=+12.0dB, 08=0.0dB, 0F = -33dB) */ + WriteLego (devc, 0x16, 0x9F1F); /* AUX to Mixer Level (80=mute; 00=+12.0dB, 08=0.0dB, 0F = -33dB) */ + WriteLego (devc, 0x0E, 0x9F1F); /* Mic to Mixer Level (80=mute; 00=+12.0dB, 08=0.0dB, 0F = -33dB) */ + WriteLego (devc, 0x18, 0x9F1F); /* DAC to Mixer Level (80=mute; 00=+12.0dB, 08=0.0dB, 0F = -33dB) */ + WriteLego (devc, 0x10, 0x9F1F); /* Line in to Mixer Level (80=mute; 00=+12.0dB, 08=0.0dB, 0F = -33dB) */ + WriteLego (devc, 0x1A, 0); /* Rec Gain */ + WriteLego (devc, 0x1C, 0x8F0F); /* Rec Gain */ +} diff --git a/attic/drv/oss_allegro/hardware.h b/attic/drv/oss_allegro/hardware.h new file mode 100644 index 0000000..ffbca31 --- /dev/null +++ b/attic/drv/oss_allegro/hardware.h @@ -0,0 +1,355 @@ +/* + * ESS Technology allegro audio driver. + * + * Copyright (C) 1992-2000 Don Kim (don.kim@esstech.com) + */ +#ifndef __HARDWARE_H +#define __HARDWARE_H + + +#define SUBSYSTEM_VENDOR_ID 0x2C + +/* Allegro PCI configuration registers */ +#define PCI_LEGACY_AUDIO_CTRL 0x40 +#define SOUND_BLASTER_ENABLE 0x00000001 +#define FM_SYNTHESIS_ENABLE 0x00000002 +#define GAME_PORT_ENABLE 0x00000004 +#define MPU401_IO_ENABLE 0x00000008 +#define MPU401_IRQ_ENABLE 0x00000010 +#define ALIAS_10BIT_IO 0x00000020 +#define SB_DMA_MASK 0x000000C0 +#define SB_DMA_0 0x00000040 +#define SB_DMA_1 0x00000040 +#define SB_DMA_R 0x00000080 +#define SB_DMA_3 0x000000C0 +#define SB_IRQ_MASK 0x00000700 +#define SB_IRQ_5 0x00000000 +#define SB_IRQ_7 0x00000100 +#define SB_IRQ_9 0x00000200 +#define SB_IRQ_10 0x00000300 +#define MIDI_IRQ_MASK 0x00003800 +#define SERIAL_IRQ_ENABLE 0x00004000 +#define DISABLE_LEGACY 0x00008000 + +#define PCI_ALLEGRO_CONFIG 0x50 +#define SB_ADDR_240 0x00000004 +#define MPU_ADDR_MASK 0x00000018 +#define MPU_ADDR_330 0x00000000 +#define MPU_ADDR_300 0x00000008 +#define MPU_ADDR_320 0x00000010 +#define MPU_ADDR_340 0x00000018 +#define USE_PCI_TIMING 0x00000040 +#define POSTED_WRITE_ENABLE 0x00000080 +#define DMA_POLICY_MASK 0x00000700 +#define DMA_DDMA 0x00000000 +#define DMA_TDMA 0x00000100 +#define DMA_PCPCI 0x00000200 +#define DMA_WBDMA16 0x00000400 +#define DMA_WBDMA4 0x00000500 +#define DMA_WBDMA2 0x00000600 +#define DMA_WBDMA1 0x00000700 +#define DMA_SAFE_GUARD 0x00000800 +#define HI_PERF_GP_ENABLE 0x00001000 +#define PIC_SNOOP_MODE_0 0x00002000 +#define PIC_SNOOP_MODE_1 0x00004000 +#define SOUNDBLASTER_IRQ_MASK 0x00008000 +#define RING_IN_ENABLE 0x00010000 +#define SPDIF_TEST_MODE 0x00020000 +#define CLK_MULT_MODE_SELECT_2 0x00040000 +#define EEPROM_WRITE_ENABLE 0x00080000 +#define CODEC_DIR_IN 0x00100000 +#define HV_BUTTON_FROM_GD 0x00200000 +#define REDUCED_DEBOUNCE 0x00400000 +#define HV_CTRL_ENABLE 0x00800000 +#define SPDIF_ENABLE 0x01000000 +#define CLK_DIV_SELECT 0x06000000 +#define CLK_DIV_BY_48 0x00000000 +#define CLK_DIV_BY_49 0x02000000 +#define CLK_DIV_BY_50 0x04000000 +#define CLK_DIV_RESERVED 0x06000000 +#define PM_CTRL_ENABLE 0x08000000 +#define CLK_MULT_MODE_SELECT 0x30000000 +#define CLK_MULT_MODE_SHIFT 28 +#define CLK_MULT_MODE_0 0x00000000 +#define CLK_MULT_MODE_1 0x10000000 +#define CLK_MULT_MODE_2 0x20000000 +#define CLK_MULT_MODE_3 0x30000000 +#define INT_CLK_SELECT 0x40000000 +#define INT_CLK_MULT_RESET 0x80000000 + +/* M3 */ +#define INT_CLK_SRC_NOT_PCI 0x00100000 +#define INT_CLK_MULT_ENABLE 0x80000000 + +#define PCI_ACPI_CONTROL 0x54 +#define PCI_ACPI_D0 0x00000000 +#define PCI_ACPI_D1 0xB4F70000 +#define PCI_ACPI_D2 0xB4F7B4F7 + +#define PCI_USER_CONFIG 0x58 +#define EXT_PCI_MASTER_ENABLE 0x00000001 +#define SPDIF_OUT_SELECT 0x00000002 +#define TEST_PIN_DIR_CTRL 0x00000004 +#define AC97_CODEC_TEST 0x00000020 +#define TRI_STATE_BUFFER 0x00000080 +#define IN_CLK_12MHZ_SELECT 0x00000100 +#define MULTI_FUNC_DISABLE 0x00000200 +#define EXT_MASTER_PAIR_SEL 0x00000400 +#define PCI_MASTER_SUPPORT 0x00000800 +#define STOP_CLOCK_ENABLE 0x00001000 +#define EAPD_DRIVE_ENABLE 0x00002000 +#define REQ_TRI_STATE_ENABLE 0x00004000 +#define REQ_LOW_ENABLE 0x00008000 +#define MIDI_1_ENABLE 0x00010000 +#define MIDI_2_ENABLE 0x00020000 +#define SB_AUDIO_SYNC 0x00040000 +#define HV_CTRL_TEST 0x00100000 +#define SOUNDBLASTER_TEST 0x00400000 + +#define PCI_USER_CONFIG_C 0x5C + +#define PCI_DDMA_CTRL 0x60 +#define DDMA_ENABLE 0x00000001 + + +/* Allegro registers */ +#define HOST_INT_CTRL 0x18 +#define SB_INT_ENABLE 0x0001 +#define MPU401_INT_ENABLE 0x0002 +#define ASSP_INT_ENABLE 0x0010 +#define RING_INT_ENABLE 0x0020 +#define HV_INT_ENABLE 0x0040 +#define CLKRUN_GEN_ENABLE 0x0100 +#define HV_CTRL_TO_PME 0x0400 +#define SOFTWARE_RESET_ENABLE 0x8000 + +#define HOST_INT_STATUS 0x1A +#define SB_INT_PENDING 0x01 +#define MPU401_INT_PENDING 0x02 +#define ASSP_INT_PENDING 0x10 +#define RING_INT_PENDING 0x20 +#define HV_INT_PENDING 0x40 + +#define HARDWARE_VOL_CTRL 0x1B +#define SHADOW_MIX_REG_VOICE 0x1C +#define HW_VOL_COUNTER_VOICE 0x1D +#define SHADOW_MIX_REG_MASTER 0x1E +#define HW_VOL_COUNTER_MASTER 0x1F + +#define CODEC_COMMAND 0x30 +#define CODEC_READ_B 0x80 + +#define CODEC_STATUS 0x30 +#define CODEC_BUSY_B 0x01 + +#define CODEC_DATA 0x32 + +/* AC97 registers */ +#define AC97_RESET 0x00 + +#define AC97_VOL_MUTE_B 0x8000 +#define AC97_VOL_M 0x1F +#define AC97_LEFT_VOL_S 8 + +#define AC97_MASTER_VOL 0x02 +#define AC97_LINE_LEVEL_VOL 0x04 +#define AC97_MASTER_MONO_VOL 0x06 +#define AC97_PC_BEEP_VOL 0x0A +#define AC97_PC_BEEP_VOL_M 0x0F +#define AC97_SROUND_MASTER_VOL 0x38 +#define AC97_PC_BEEP_VOL_S 1 + +#define AC97_PHONE_VOL 0x0C +#define AC97_MIC_VOL 0x0E +#define AC97_MIC_20DB_ENABLE 0x40 + +#define AC97_LINEIN_VOL 0x10 +#define AC97_CD_VOL 0x12 +#define AC97_VIDEO_VOL 0x14 +#define AC97_AUX_VOL 0x16 +#define AC97_PCM_OUT_VOL 0x18 +#define AC97_RECORD_SELECT 0x1A +#define AC97_RECORD_MIC 0x00 +#define AC97_RECORD_CD 0x01 +#define AC97_RECORD_VIDEO 0x02 +#define AC97_RECORD_AUX 0x03 +#define AC97_RECORD_MONO_MUX 0x02 +#define AC97_RECORD_DIGITAL 0x03 +#define AC97_RECORD_LINE 0x04 +#define AC97_RECORD_STEREO 0x05 +#define AC97_RECORD_MONO 0x06 +#define AC97_RECORD_PHONE 0x07 + +#define AC97_RECORD_GAIN 0x1C +#define AC97_RECORD_VOL_M 0x0F + +#define AC97_GENERAL_PURPOSE 0x20 +#define AC97_POWER_DOWN_CTRL 0x26 +#define AC97_ADC_READY 0x0001 +#define AC97_DAC_READY 0x0002 +#define AC97_ANALOG_READY 0x0004 +#define AC97_VREF_ON 0x0008 +#define AC97_PR0 0x0100 +#define AC97_PR1 0x0200 +#define AC97_PR2 0x0400 +#define AC97_PR3 0x0800 +#define AC97_PR4 0x1000 + +#define AC97_RESERVED1 0x28 + +#define AC97_VENDOR_TEST 0x5A + +#define AC97_CLOCK_DELAY 0x5C +#define AC97_LINEOUT_MUX_SEL 0x0001 +#define AC97_MONO_MUX_SEL 0x0002 +#define AC97_CLOCK_DELAY_SEL 0x1F +#define AC97_DAC_CDS_SHIFT 6 +#define AC97_ADC_CDS_SHIFT 11 + +#define AC97_MULTI_CHANNEL_SEL 0x74 + +#define AC97_VENDOR_ID1 0x7C +#define AC97_VENDOR_ID2 0x7E + + +#define RING_BUS_CTRL_A 0x36 +#define RAC_PME_ENABLE 0x0100 +#define RAC_SDFS_ENABLE 0x0200 +#define LAC_PME_ENABLE 0x0400 +#define LAC_SDFS_ENABLE 0x0800 +#define SERIAL_AC_LINK_ENABLE 0x1000 +#define IO_SRAM_ENABLE 0x2000 +#define IIS_INPUT_ENABLE 0x8000 + +#define RING_BUS_CTRL_B 0x38 +#define SECOND_CODEC_ID_MASK 0x0003 +#define SPDIF_FUNC_ENABLE 0x0010 +#define SECOND_AC_ENABLE 0x0020 +#define SB_MODULE_INTF_ENABLE 0x0040 +#define SSPE_ENABLE 0x0040 +#define M3I_DOCK_ENABLE 0x0080 + +#define SDO_OUT_DEST_CTRL 0x3A +#define COMMAND_ADDR_OUT 0x0003 +#define PCM_LR_OUT_LOCAL 0x0000 +#define PCM_LR_OUT_REMOTE 0x0004 +#define PCM_LR_OUT_MUTE 0x0008 +#define PCM_LR_OUT_BOTH 0x000C +#define LINE1_DAC_OUT_LOCAL 0x0000 +#define LINE1_DAC_OUT_REMOTE 0x0010 +#define LINE1_DAC_OUT_MUTE 0x0020 +#define LINE1_DAC_OUT_BOTH 0x0030 +#define PCM_CLS_OUT_LOCAL 0x0000 +#define PCM_CLS_OUT_REMOTE 0x0040 +#define PCM_CLS_OUT_MUTE 0x0080 +#define PCM_CLS_OUT_BOTH 0x00C0 +#define PCM_RLF_OUT_LOCAL 0x0000 +#define PCM_RLF_OUT_REMOTE 0x0100 +#define PCM_RLF_OUT_MUTE 0x0200 +#define PCM_RLF_OUT_BOTH 0x0300 +#define LINE2_DAC_OUT_LOCAL 0x0000 +#define LINE2_DAC_OUT_REMOTE 0x0400 +#define LINE2_DAC_OUT_MUTE 0x0800 +#define LINE2_DAC_OUT_BOTH 0x0C00 +#define HANDSET_OUT_LOCAL 0x0000 +#define HANDSET_OUT_REMOTE 0x1000 +#define HANDSET_OUT_MUTE 0x2000 +#define HANDSET_OUT_BOTH 0x3000 +#define IO_CTRL_OUT_LOCAL 0x0000 +#define IO_CTRL_OUT_REMOTE 0x4000 +#define IO_CTRL_OUT_MUTE 0x8000 +#define IO_CTRL_OUT_BOTH 0xC000 + +#define SDO_IN_DEST_CTRL 0x3C +#define STATUS_ADDR_IN 0x0003 +#define PCM_LR_IN_LOCAL 0x0000 +#define PCM_LR_IN_REMOTE 0x0004 +#define PCM_LR_RESERVED 0x0008 +#define PCM_LR_IN_BOTH 0x000C +#define LINE1_ADC_IN_LOCAL 0x0000 +#define LINE1_ADC_IN_REMOTE 0x0010 +#define LINE1_ADC_IN_MUTE 0x0020 +#define MIC_ADC_IN_LOCAL 0x0000 +#define MIC_ADC_IN_REMOTE 0x0040 +#define MIC_ADC_IN_MUTE 0x0080 +#define LINE2_DAC_IN_LOCAL 0x0000 +#define LINE2_DAC_IN_REMOTE 0x0400 +#define LINE2_DAC_IN_MUTE 0x0800 +#define HANDSET_IN_LOCAL 0x0000 +#define HANDSET_IN_REMOTE 0x1000 +#define HANDSET_IN_MUTE 0x2000 +#define IO_STATUS_IN_LOCAL 0x0000 +#define IO_STATUS_IN_REMOTE 0x4000 + +#define SPDIF_IN_CTRL 0x3E +#define SPDIF_IN_ENABLE 0x0001 + +#define GPIO_DATA 0x60 +#define GPIO_DATA_MASK 0x0FFF +#define GPIO_HV_STATUS 0x3000 +#define GPIO_PME_STATUS 0x4000 + +#define GPIO_MASK 0x64 +#define GPIO_DIRECTION 0x68 +#define GPO_PRIMARY_AC97 0x0001 +#define GPI_LINEOUT_SENSE 0x0004 +#define GPO_SECONDARY_AC97 0x0008 +#define GPI_VOL_DOWN 0x0010 +#define GPI_VOL_UP 0x0020 +#define GPI_IIS_CLK 0x0040 +#define GPI_IIS_LRCLK 0x0080 +#define GPI_IIS_DATA 0x0100 +#define GPI_DOCKING_STATUS 0x0100 +#define GPI_HEADPHONE_SENSE 0x0200 +#define GPO_EXT_AMP_SHUTDOWN 0x1000 + +/* M3 */ +#define GPO_M3_EXT_AMP_SHUTDN 0x0002 + +#define ASSP_INDEX_PORT 0x80 +#define ASSP_MEMORY_PORT 0x82 +#define ASSP_DATA_PORT 0x84 + +#define MPU401_DATA_PORT 0x98 +#define MPU401_STATUS_PORT 0x99 + +#define CLK_MULT_DATA_PORT 0x9C + +#define ASSP_CONTROL_A 0xA2 +#define ASSP_0_WS_ENABLE 0x01 +#define ASSP_CTRL_A_RESERVED1 0x02 +#define ASSP_CTRL_A_RESERVED2 0x04 +#define ASSP_CLK_49MHZ_SELECT 0x08 +#define FAST_PLU_ENABLE 0x10 +#define ASSP_CTRL_A_RESERVED3 0x20 +#define DSP_CLK_36MHZ_SELECT 0x40 + +#define ASSP_CONTROL_B 0xA4 +#define RESET_ASSP 0x00 +#define RUN_ASSP 0x01 +#define ENABLE_ASSP_CLOCK 0x00 +#define STOP_ASSP_CLOCK 0x10 +#define RESET_TOGGLE 0x40 + +#define ASSP_CONTROL_C 0xA6 +#define ASSP_HOST_INT_ENABLE 0x01 +#define FM_ADDR_REMAP_DISABLE 0x02 +#define HOST_WRITE_PORT_ENABLE 0x08 + +#define ASSP_HOST_INT_STATUS 0xAC +#define DSP2HOST_REQ_PIORECORD 0x01 +#define DSP2HOST_REQ_I2SRATE 0x02 +#define DSP2HOST_REQ_TIMER 0x04 + +#endif +#define A1_1988 1 +#define A1_1989 2 +#define M3_1998 3 +#define M3_1999 4 +#define M3_199A 5 +#define M3_199B 6 + +#define LOCAL_CODEC 0 +#define REMOTE_CODEC 1 +#define CHANGE_CODEC 0 +#define RESTORE_CODEC 1 diff --git a/attic/drv/oss_allegro/hckernel.h b/attic/drv/oss_allegro/hckernel.h new file mode 100644 index 0000000..fe7a2e7 --- /dev/null +++ b/attic/drv/oss_allegro/hckernel.h @@ -0,0 +1,183 @@ +/* + * ESS Technology allegro audio driver. + * + * Copyright (C) 1992-2000 Don Kim (don.kim@esstech.com) + */ +#ifndef _HCKERNEL_H_ +#define _HCKERNEL_H_ + + + + +#define IIS_APU56 0x38 +#define IIS_APU57 0x39 + +#define DSP_4_CHANNEL 0x08000000 /*AY specify DSP 4 channel */ +#define DSP_6_CHANNEL 0x04000000 /*AY specify DSP 6 channel */ + +#define DSP_MEMORY_INDEX 0x80 +#define DSP_MEMORY_TYPE 0x82 +#define DSP_DATA_MEMORY 0x0003 +#define DSP_CODE_MEMORY 0x0002 +#define DSP_MEMORY_VALUE 0x84 + +#define NOT_READY 0 +#define RUNNING 1 +#define PAUSE 2 +#define STOP 3 + +/*DSPAPU */ +#define DSPAPU_IN_BUF_SIZE 96 /* 32 * 3 BUFFERS */ +#define DSPAPU_OUT_BUF_SIZE 96 /* 32 * 3 BUFFERS */ + +/****************** SRC3 Begin ********************** */ +/* max # of playback/record clients */ + +#define MAXSRCPLAYCLIENT 1 /* ASSUME NO MULTIPLE STREAMS */ +#define MAXSRCRECCLIENT 1 +#define MAXSVCLIENT 1 /* assume 1 for speaker virtualization */ + + +/* value for bDirection */ +#define SRCPLAYBACK TRUE +#define SRCRECORD FALSE + +/*/dwMode */ +#define SRC_PCM_16BIT 0x01 +#define SRC_PCM_8BIT 0x02 +#define SRC_PCM_STEREO 0x04 +#define SRC_PCM_MONO 0x08 + + +/* khs 0302 */ +#define SRC3_PLAYBACK 0 +#define SRC3_RECORD 1 + +#define SRC3_STEREO 0 +#define SRC3_MONO 1 + +#define SRC3_16BIT 0 +#define SRC3_8BIT 1 + +#define SRC3_SR_44100 0 +#define SRC3_SR_32000 1 +#define SRC3_SR_22050 2 +#define SRC3_SR_11025 3 +#define SRC3_SR_8000 4 + +#define DSP_PROGRAM_SIZE 0x15c /* maximum program size */ +#define SRC_PB_FILTER_SIZE 666 /* maximum playback filter size */ + +#define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN +#define SRC3_MODE_OFFSET CDATA_HEADER_LEN + 1 +#define SRC3_WORD_LENGTH_OFFSET CDATA_HEADER_LEN + 2 +#define SRC3_PARAMETER_OFFSET CDATA_HEADER_LEN + 3 +#define SRC3_COEFF_ADDR_OFFSET CDATA_HEADER_LEN + 8 +#define SRC3_FILTAP_ADDR_OFFSET CDATA_HEADER_LEN + 10 +#define SRC3_TEMP_INBUF_ADDR_OFFSET CDATA_HEADER_LEN + 16 +#define SRC3_TEMP_OUTBUF_ADDR_OFFSET CDATA_HEADER_LEN + 17 +#define FOR_FUTURE_USE 10 /* for storing temporary variable in future */ + +/****************** SRC3 End ********************** */ + + +/****************** Speaker Virtualization Begin ********************** */ + + /* specify the sample rate flag = 1 for 44.1K ; 0 for 48K */ + /* default is 0 so it is for 48K */ +#define SPKRVIRT_SR_FLAG CDATA_HEADER_LEN + 1 +#define SPKRVIRT_44K 0X0001 +#define SPKRVIRT_48K 0X0000 + + +/*VMAx Speaker Virtualization */ +#define SPKRVIRT_VARIABLE_LEN 81 /* IN WORD */ +#define SPKRVIRT_IN_BUFFER_OFFSET CDATA_HEADER_LEN + SPKRVIRT_VARIABLE_LEN +#define SPKRVIRT_IN_BUFFER_SIZE (384 * 2) /* BYTE */ + +#define SPKRVIRT_OUT_BUFFER_OFFSET SPKRVIRT_IN_BUFFER_OFFSET + (SPKRVIRT_IN_BUFFER_SIZE / 2) +#define SPKRVIRT_OUT_BUFFER_SIZE (192 * 2) /* BYTE */ + +#define SPKRVIRT_OWN_DATA_SIZE SPKRVIRT_OUT_BUFFER_OFFSET + (SPKRVIRT_OUT_BUFFER_SIZE / 2) + +/*CRL Sensaura */ + +#define CRL_SPKRVIRT_VARIABLE_LEN 237 /* IN WORD */ + +#define CRL_SPKRVIRT_IN_BUFFER_OFFSET CDATA_HEADER_LEN + CRL_SPKRVIRT_VARIABLE_LEN +/*#define CRL_SPKRVIRT_IN_BUFFER_SIZE (384 * 2) // BYTE */ +#define CRL_SPKRVIRT_IN_BUFFER_SIZE (256 * 2) /* BYTE */ + +#define CRL_SPKRVIRT_OUT_BUFFER_OFFSET CRL_SPKRVIRT_IN_BUFFER_OFFSET + (CRL_SPKRVIRT_IN_BUFFER_SIZE / 2) +/*#define CRL_SPKRVIRT_OUT_BUFFER_SIZE (192 * 2) // BYTE */ +#define CRL_SPKRVIRT_OUT_BUFFER_SIZE (128 * 2) /* BYTE */ + +#define CRL_SPKRVIRT_OWN_DATA_SIZE CRL_SPKRVIRT_OUT_BUFFER_OFFSET + (CRL_SPKRVIRT_OUT_BUFFER_SIZE / 2) + +/****************** Speaker Virtualization End ********************** */ + +/* WARNING! WARNING! WARNING! WARNING! WARNING! WARNING! */ +/* */ +/* Do NOT change DSP_STARTTRANSFER_INFO structure without updating hckernel.inc */ +/* */ +/* WARNING! WARNING! WARNING! WARNING! WARNING! WARNING! */ + + +typedef struct sTRANSFER_INFO +{ + PCLIENT_INST pClient_Inst; + DWORD dwAutoRepeat; + DWORD dwHostSrcBufferAddr; + DWORD dwHostSrcBufferLen; + DWORD dwHostDstBufferAddr; + DWORD dwHostDstBufferLen; + DWORD dwDSPInBufferAddr; + DWORD dwDSPInBufferLen; + DWORD dwDSPOutBufferAddr; + DWORD dwDSPOutBufferLen; + DWORD dwDSPInConnection; + DWORD dwDSPOutConnection; + +} +TRANSFER_INFO, *PTRANSFER_INFO; + + +/*similar to kOpenInstance */ +extern WORD __cdecl DSPxxxOpen (DWORD, DWORD, DWORD, PCLIENT_INST *); +/*similar to kCloseInstance */ +extern WORD __cdecl DSPxxxClose (PCLIENT_INST, DWORD); +/*similar to kStartTransfer */ +extern WORD __cdecl DSPStartXfer (PTRANSFER_INFO); +/*similar to kStopTransfer */ +extern WORD __cdecl DSPStopXfer (PCLIENT_INST); +/*similar to kQueryPosition */ +extern WORD __cdecl DSPQueryPosition (PCLIENT_INST, DWORD, PDWORD); +/*similar to kSetInstanceReady */ +extern WORD __cdecl DSPSetInstanceReady (PCLIENT_INST); +/*similar to kSetInstanceNotReady */ +extern WORD __cdecl DSPSetInstanceNotReady (PCLIENT_INST); +/*similar to kPIOInterruptHandler */ +extern WORD __cdecl DSPPIOInterruptHandler (PCLIENT_INST); +extern WORD __cdecl DSPSetTimer (DWORD); +/*similar to kAlterTransfer */ +extern WORD __cdecl DSPAlterTransfer (PCLIENT_INST, DWORD, DWORD, DWORD); + +extern WORD __cdecl DSPUnmaskInt (void); +extern WORD __cdecl DSPMaskInt (void); + +extern WORD __cdecl DSPReadWord (DWORD, DWORD, DWORD); +extern VOID __cdecl DSPWriteWord (DWORD, DWORD, DWORD, WORD); +/*similar to kI2SInterruptHandler */ +extern WORD __cdecl DSPI2SInterruptHandler (PDWORD); + +extern WORD __cdecl DSPOpenPassThru (PPASSTHRU *, DWORD, DWORD); +extern WORD __cdecl DSPClosePassThru (PPASSTHRU); + +extern WORD gwDisable_DSP; +extern DWORD gwDisable_VMAx; +#define VMAX_MAGIC 0x564D4158 +#define CRL_MAGIC 0x43524C + +extern WORD gwDSPConnectIn; /* tell DSP where to grab data from */ +extern WORD gwDSPConnectOut; /* tell DSP where to send data to */ +#endif diff --git a/attic/drv/oss_allegro/id.h b/attic/drv/oss_allegro/id.h new file mode 100644 index 0000000..c61985f --- /dev/null +++ b/attic/drv/oss_allegro/id.h @@ -0,0 +1,48 @@ +/****************************************************************************** + * * + * (C) 1998-1998 ESS Technology, Inc. * + * * + * This source code, its compiled object code, and its associated data sets * + * are copyright (C) 1998-1998 ESS Technology, Inc. This source code and its * + * associated data sets are trade secrets of ESS Technology, Inc. * + * * + ******************************************************************************/ + +/*--------------------------------------------------------------------------- + * Copyright (C) 1998-1998, ESS Technology, Inc. + *--------------------------------------------------------------------------- + * FILENAME: id.h + *--------------------------------------------------------------------------- + * DESCRIPTION: Header file containing Allegro device and revision IDs + *--------------------------------------------------------------------------- + * AUTHOR: Henry Tang + *--------------------------------------------------------------------------- + * HISTORY: + * 04/22/98 HT Created. + *--------------------------------------------------------------------------- + */ + +// +// Device IDs +// + +#define DEVICE_ID_1968 0x1968 +#define DEVICE_ID_1978 0x1978 + +// +// Revision IDs +// + +#define REVISION_ID_1968 0x00 +#define REVISION_ID_1978_REV_A 0x00 +#define REVISION_ID_1978_REV_B 0x10 + +//--------------------------------------------------------------------------- +// End of File: id.h +//--------------------------------------------------------------------------- + +/****************************************************************************** + * * + * (C) 1998-1998 ESS Technology, Inc. * + * * + ******************************************************************************/ diff --git a/attic/drv/oss_allegro/kernel.dat b/attic/drv/oss_allegro/kernel.dat new file mode 100644 index 0000000..f19dd82 --- /dev/null +++ b/attic/drv/oss_allegro/kernel.dat @@ -0,0 +1,80 @@ +0x7980, 0x0030, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x00FB, 0x7980, 0x00DD, 0x7980, 0x03B4,
+0x7980, 0x0332, 0x7980, 0x0287, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
+0x7980, 0x031A, 0x7980, 0x03B4, 0x7980, 0x022F, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
+0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x0063, 0x7980, 0x006B, 0x7980, 0x03B4, 0x7980, 0x03B4,
+0xBF80, 0x2C7C, 0x8806, 0x8804, 0xBE40, 0xBC20, 0xAE09, 0x1000, 0xAE0A, 0x0001, 0x6938, 0xEB08,
+0x0053, 0x695A, 0xEB08, 0x00D6, 0x0009, 0x8B88, 0x6980, 0xE388, 0x0036, 0xBE30, 0xBC20, 0x6909,
+0xB801, 0x9009, 0xBE41, 0xBE41, 0x6928, 0xEB88, 0x0078, 0xBE41, 0xBE40, 0x7980, 0x0038, 0xBE41,
+0xBE41, 0x903A, 0x6938, 0xE308, 0x0056, 0x903A, 0xBE41, 0xBE40, 0xEF00, 0x903A, 0x6939, 0xE308,
+0x005E, 0x903A, 0xEF00, 0x690B, 0x660C, 0xEF8C, 0x690A, 0x660C, 0x620B, 0x6609, 0xEF00, 0x6910,
+0x660F, 0xEF04, 0xE388, 0x0075, 0x690E, 0x660F, 0x6210, 0x660D, 0xEF00, 0x690E, 0x660D, 0xEF00,
+0xAE70, 0x0001, 0xBC20, 0xAE27, 0x0001, 0x6939, 0xEB08, 0x005D, 0x6926, 0xB801, 0x9026, 0x0026,
+0x8B88, 0x6980, 0xE388, 0x00CB, 0x9028, 0x0D28, 0x4211, 0xE100, 0x007A, 0x4711, 0xE100, 0x00A0,
+0x7A80, 0x0063, 0xB811, 0x660A, 0x6209, 0xE304, 0x007A, 0x0C0B, 0x4005, 0x100A, 0xBA01, 0x9012,
+0x0C12, 0x4002, 0x7980, 0x00AF, 0x7A80, 0x006B, 0xBE02, 0x620E, 0x660D, 0xBA10, 0xE344, 0x007A,
+0x0C10, 0x4005, 0x100E, 0xBA01, 0x9012, 0x0C12, 0x4002, 0x1003, 0xBA02, 0x9012, 0x0C12, 0x4000,
+0x1003, 0xE388, 0x00BA, 0x1004, 0x7980, 0x00BC, 0x1004, 0xBA01, 0x9012, 0x0C12, 0x4001, 0x0C05,
+0x4003, 0x0C06, 0x4004, 0x1011, 0xBFB0, 0x01FF, 0x9012, 0x0C12, 0x4006, 0xBC20, 0xEF00, 0xAE26,
+0x1028, 0x6970, 0xBFD0, 0x0001, 0x9070, 0xE388, 0x007A, 0xAE28, 0x0000, 0xEF00, 0xAE70, 0x0300,
+0x0C70, 0xB00C, 0xAE5A, 0x0000, 0xEF00, 0x7A80, 0x038A, 0x697F, 0xB801, 0x907F, 0x0056, 0x8B88,
+0x0CA0, 0xB008, 0xAF71, 0xB000, 0x4E71, 0xE200, 0x00F3, 0xAE56, 0x1057, 0x0056, 0x0CA0, 0xB008,
+0x8056, 0x7980, 0x03A1, 0x0810, 0xBFA0, 0x1059, 0xE304, 0x03A1, 0x8056, 0x7980, 0x03A1, 0x7A80,
+0x038A, 0xBF01, 0xBE43, 0xBE59, 0x907C, 0x6937, 0xE388, 0x010D, 0xBA01, 0xE308, 0x010C, 0xAE71,
+0x0004, 0x0C71, 0x5000, 0x6936, 0x9037, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80, 0xBF0A,
+0x0560, 0xF500, 0xBF0A, 0x0520, 0xB900, 0xBB17, 0x90A0, 0x6917, 0xE388, 0x0148, 0x0D17, 0xE100,
+0x0127, 0xBF0C, 0x0578, 0xBF0D, 0x057C, 0x7980, 0x012B, 0xBF0C, 0x0538, 0xBF0D, 0x053C, 0x6900,
+0xE308, 0x0135, 0x8B8C, 0xBE59, 0xBB07, 0x90A0, 0xBC20, 0x7980, 0x0157, 0x030C, 0x8B8B, 0xB903,
+0x8809, 0xBEC6, 0x013E, 0x69AC, 0x90AB, 0x69AD, 0x90AB, 0x0813, 0x660A, 0xE344, 0x0144, 0x0309,
+0x830C, 0xBC20, 0x7980, 0x0157, 0x6955, 0xE388, 0x0157, 0x7C38, 0xBF0B, 0x0578, 0xF500, 0xBF0B,
+0x0538, 0xB907, 0x8809, 0xBEC6, 0x0156, 0x10AB, 0x90AA, 0x6974, 0xE388, 0x0163, 0xAE72, 0x0540,
+0xF500, 0xAE72, 0x0500, 0xAE61, 0x103B, 0x7A80, 0x02F6, 0x6978, 0xE388, 0x0182, 0x8B8C, 0xBF0C,
+0x0560, 0xE500, 0x7C40, 0x0814, 0xBA20, 0x8812, 0x733D, 0x7A80, 0x0380, 0x733E, 0x7A80, 0x0380,
+0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA2C, 0x8812, 0x733F, 0x7A80, 0x0380, 0x7340,
+0x7A80, 0x0380, 0x6975, 0xE388, 0x018E, 0xAE72, 0x0548, 0xF500, 0xAE72, 0x0508, 0xAE61, 0x1041,
+0x7A80, 0x02F6, 0x6979, 0xE388, 0x01AD, 0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA18,
+0x8812, 0x7343, 0x7A80, 0x0380, 0x7344, 0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40,
+0x0814, 0xBA24, 0x8812, 0x7345, 0x7A80, 0x0380, 0x7346, 0x7A80, 0x0380, 0x6976, 0xE388, 0x01B9,
+0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x1047, 0x7A80, 0x02F6, 0x697A, 0xE388, 0x01D8,
+0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA08, 0x8812, 0x7349, 0x7A80, 0x0380, 0x734A,
+0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA14, 0x8812, 0x734B, 0x7A80,
+0x0380, 0x734C, 0x7A80, 0x0380, 0xBC21, 0xAE1C, 0x1090, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40,
+0x0812, 0xB804, 0x8813, 0x8B8D, 0xBF0D, 0x056C, 0xE500, 0x7C40, 0x0815, 0xB804, 0x8811, 0x7A80,
+0x034A, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40, 0x731F, 0xB903, 0x8809, 0xBEC6, 0x01F9, 0x548A,
+0xBE03, 0x98A0, 0x7320, 0xB903, 0x8809, 0xBEC6, 0x0201, 0x548A, 0xBE03, 0x98A0, 0x1F20, 0x2F1F,
+0x9826, 0xBC20, 0x6935, 0xE388, 0x03A1, 0x6933, 0xB801, 0x9033, 0xBFA0, 0x02EE, 0xE308, 0x03A1,
+0x9033, 0xBF00, 0x6951, 0xE388, 0x021F, 0x7334, 0xBE80, 0x5760, 0xBE03, 0x9F7E, 0xBE59, 0x9034,
+0x697E, 0x0D51, 0x9013, 0xBC20, 0x695C, 0xE388, 0x03A1, 0x735E, 0xBE80, 0x5760, 0xBE03, 0x9F7E,
+0xBE59, 0x905E, 0x697E, 0x0D5C, 0x9013, 0x7980, 0x03A1, 0x7A80, 0x038A, 0xBF01, 0xBE43, 0x6977,
+0xE388, 0x024E, 0xAE61, 0x104D, 0x0061, 0x8B88, 0x6980, 0xE388, 0x024E, 0x9071, 0x0D71, 0x000B,
+0xAFA0, 0x8010, 0xAFA0, 0x8010, 0x0810, 0x660A, 0xE308, 0x0249, 0x0009, 0x0810, 0x660C, 0xE388,
+0x024E, 0x800B, 0xBC20, 0x697B, 0xE388, 0x03A1, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80,
+0xE100, 0x0266, 0x697C, 0xBF90, 0x0560, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0564, 0x9073, 0x0473,
+0x7980, 0x0270, 0x697C, 0xBF90, 0x0520, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0524, 0x9073, 0x0473,
+0x697C, 0xB801, 0x907C, 0xBF0A, 0x10FD, 0x8B8A, 0xAF80, 0x8010, 0x734F, 0x548A, 0xBE03, 0x9880,
+0xBC21, 0x7326, 0x548B, 0xBE03, 0x618B, 0x988C, 0xBE03, 0x6180, 0x9880, 0x7980, 0x03A1, 0x7A80,
+0x038A, 0x0D28, 0x4711, 0xE100, 0x02BE, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388, 0x02B6,
+0xBFA0, 0x0800, 0xE388, 0x02B2, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02A3, 0x6909,
+0x900B, 0x7980, 0x02A5, 0xAF0B, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100, 0x02ED,
+0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x6909, 0x900B, 0x7980, 0x02B8, 0xAF0B, 0x4005,
+0xAF05, 0x4003, 0xAF06, 0x4004, 0x7980, 0x02ED, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388,
+0x02E7, 0xBFA0, 0x0800, 0xE388, 0x02E3, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02D4,
+0x690D, 0x9010, 0x7980, 0x02D6, 0xAF10, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100,
+0x02ED, 0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x690D, 0x9010, 0x7980, 0x02E9, 0xAF10,
+0x4005, 0xAF05, 0x4003, 0xAF06, 0x4004, 0xBC20, 0x6970, 0x9071, 0x7A80, 0x0078, 0x6971, 0x9070,
+0x7980, 0x03A1, 0xBC20, 0x0361, 0x8B8B, 0x6980, 0xEF88, 0x0272, 0x0372, 0x7804, 0x9071, 0x0D71,
+0x8B8A, 0x000B, 0xB903, 0x8809, 0xBEC6, 0x0309, 0x69A8, 0x90AB, 0x69A8, 0x90AA, 0x0810, 0x660A,
+0xE344, 0x030F, 0x0009, 0x0810, 0x660C, 0xE388, 0x0314, 0x800B, 0xBC20, 0x6961, 0xB801, 0x9061,
+0x7980, 0x02F7, 0x7A80, 0x038A, 0x5D35, 0x0001, 0x6934, 0xB801, 0x9034, 0xBF0A, 0x109E, 0x8B8A,
+0xAF80, 0x8014, 0x4880, 0xAE72, 0x0550, 0xF500, 0xAE72, 0x0510, 0xAE61, 0x1051, 0x7A80, 0x02F6,
+0x7980, 0x03A1, 0x7A80, 0x038A, 0x5D35, 0x0002, 0x695E, 0xB801, 0x905E, 0xBF0A, 0x109E, 0x8B8A,
+0xAF80, 0x8014, 0x4780, 0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x105C, 0x7A80, 0x02F6,
+0x7980, 0x03A1, 0x001C, 0x8B88, 0x6980, 0xEF88, 0x901D, 0x0D1D, 0x100F, 0x6610, 0xE38C, 0x0358,
+0x690E, 0x6610, 0x620F, 0x660D, 0xBA0F, 0xE301, 0x037A, 0x0410, 0x8B8A, 0xB903, 0x8809, 0xBEC6,
+0x036C, 0x6A8C, 0x61AA, 0x98AB, 0x6A8C, 0x61AB, 0x98AD, 0x6A8C, 0x61AD, 0x98A9, 0x6A8C, 0x61A9,
+0x98AA, 0x7C04, 0x8B8B, 0x7C04, 0x8B8D, 0x7C04, 0x8B89, 0x7C04, 0x0814, 0x660E, 0xE308, 0x0379,
+0x040D, 0x8410, 0xBC21, 0x691C, 0xB801, 0x901C, 0x7980, 0x034A, 0xB903, 0x8809, 0x8B8A, 0xBEC6,
+0x0388, 0x54AC, 0xBE03, 0x618C, 0x98AA, 0xEF00, 0xBC20, 0xBE46, 0x0809, 0x906B, 0x080A, 0x906C,
+0x080B, 0x906D, 0x081A, 0x9062, 0x081B, 0x9063, 0x081E, 0x9064, 0xBE59, 0x881E, 0x8065, 0x8166,
+0x8267, 0x8368, 0x8469, 0x856A, 0xEF00, 0xBC20, 0x696B, 0x8809, 0x696C, 0x880A, 0x696D, 0x880B,
+0x6962, 0x881A, 0x6963, 0x881B, 0x6964, 0x881E, 0x0065, 0x0166, 0x0267, 0x0368, 0x0469, 0x056A,
+0xBE3A,
diff --git a/attic/drv/oss_allegro/kernel.h b/attic/drv/oss_allegro/kernel.h new file mode 100644 index 0000000..6a6db12 --- /dev/null +++ b/attic/drv/oss_allegro/kernel.h @@ -0,0 +1,1042 @@ +/****************************************************************************** + * * + * (C) 1997-1999 ESS Technology, Inc. * + * * + * This source code, its compiled object code, and its associated data sets * + * are copyright (C) 1997-1999 ESS Technology, Inc. This source code and its * + * associated data sets are trade secrets of ESS Technology, Inc. * + * * + ******************************************************************************/ + +/*--------------------------------------------------------------------------- + * Copyright (C) 1997-1999, ESS Technology, Inc. + *--------------------------------------------------------------------------- + * FILENAME: kernel.h V2.10 08/19/99 + *--------------------------------------------------------------------------- + * DESCRIPTION: Header file for Maestro 3/Allegro host kernel + *--------------------------------------------------------------------------- + * AUTHOR: Henry Tang / Hong Kim /Alger Yeung/Don Kim + *--------------------------------------------------------------------------- + * HISTORY: + * 09/03/97 HT Created. + * 05/21/99 AY SwitchClient flags + * 07/29/99 AY Adding 4-speaker support + * 08/18/99 AY Adding SPDIF IN support + * 08/18/99 AY Adding SPDIF IN support + * 08/18/99 AY Remove PIO and SoundBlaster support + * 08/18/99 AY Reduce Cpythru to 2 instances instead of 4 + * 09/22/99 HK M3I feature + *--------------------------------------------------------------------------- + */ + + +#ifndef __KERNEL_H +#define __KERNEL_H + +/* */ +/* client IDs */ +/* */ +/* FM client is a special case */ +/* */ + +#define CLIENT_CPYTHRU 0 +#define CLIENT_MODEM 1 +#define CLIENT_POS3D 2 +#define CLIENT_SPKVIRT 3 +#define CLIENT_SPKVIRT_CRL 4 +#define CLIENT_SRC 5 +#define CLIENT_MINISRC 6 +#define CLIENT_SPDIF 7 +#define NUMBER_OF_CLIENTS (CLIENT_SPDIF + 1) + +#define CLIENT_FM NUMBER_OF_CLIENTS + +#define MASK_CLIENT_CPYTHRU (1 << CLIENT_CPYTHRU ) +#define MASK_CLIENT_MODEM (1 << CLIENT_MODEM ) +#define MASK_CLIENT_POS3D (1 << CLIENT_POS3D ) +#define MASK_CLIENT_SPKVIRT (1 << CLIENT_SPKVIRT ) +#define MASK_CLIENT_SPKVIRT_CRL (1 << CLIENT_SPKVIRT_CRL) +#define MASK_CLIENT_SRC (1 << CLIENT_SRC ) +#define MASK_CLIENT_MINISRC (1 << CLIENT_MINISRC ) +#define MASK_CLIENT_SPDIF (1 << CLIENT_SPDIF ) + +/* WARNING! DANGER! WARNING! DANGER! WARNING! DANGER! WARNING! DANGER! */ +/* */ +/* If you modify any memory map and/or definitions below be sure to reflect */ +/* the changes in the DSP version found in KERNEL.INC. */ +/* */ +/* WARNING! DANGER! WARNING! DANGER! WARNING! DANGER! WARNING! DANGER! */ + + +/* */ +/* DSP memory map */ +/* */ + +#define REV_A_CODE_MEMORY_BEGIN 0x0000 +#define REV_A_CODE_MEMORY_END 0x0FFF +#define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040 +#define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1) + +#define REV_B_CODE_MEMORY_BEGIN 0x0000 +#define REV_B_CODE_MEMORY_END 0x0BFF +#define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040 +#define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1) + +#if (REV_A_CODE_MEMORY_LENGTH % REV_A_CODE_MEMORY_UNIT_LENGTH) +#error Assumption about code memory unit length failed. +#endif +#if (REV_B_CODE_MEMORY_LENGTH % REV_B_CODE_MEMORY_UNIT_LENGTH) +#error Assumption about code memory unit length failed. +#endif + +#define REV_A_DATA_MEMORY_BEGIN 0x1000 +#define REV_A_DATA_MEMORY_END 0x2FFF +#define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080 +#define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1) + +#define REV_B_DATA_MEMORY_BEGIN 0x1000 +/*#define REV_B_DATA_MEMORY_END 0x23FF */ +#define REV_B_DATA_MEMORY_END 0x2BFF +#define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080 +#define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1) + +#if (REV_A_DATA_MEMORY_LENGTH % REV_A_DATA_MEMORY_UNIT_LENGTH) +#error Assumption about data memory unit length failed. +#endif +#if (REV_B_DATA_MEMORY_LENGTH % REV_B_DATA_MEMORY_UNIT_LENGTH) +#error Assumption about data memory unit length failed. +#endif + +#define CODE_MEMORY_MAP_LENGTH (64 + 1) +#define DATA_MEMORY_MAP_LENGTH (64 + 1) + +#if (CODE_MEMORY_MAP_LENGTH < ((REV_A_CODE_MEMORY_LENGTH / REV_A_CODE_MEMORY_UNIT_LENGTH) + 1)) +#error Code memory map length too short. +#endif +#if (DATA_MEMORY_MAP_LENGTH < ((REV_A_DATA_MEMORY_LENGTH / REV_A_DATA_MEMORY_UNIT_LENGTH) + 1)) +#error Data memory map length too short. +#endif +#if (CODE_MEMORY_MAP_LENGTH < ((REV_B_CODE_MEMORY_LENGTH / REV_B_CODE_MEMORY_UNIT_LENGTH) + 1)) +#error Code memory map length too short. +#endif +#if (DATA_MEMORY_MAP_LENGTH < ((REV_B_DATA_MEMORY_LENGTH / REV_B_DATA_MEMORY_UNIT_LENGTH) + 1)) +#error Data memory map length too short. +#endif + + +/* */ +/* Kernel code memory definition */ +/* */ + +#define KCODE_VECTORS_BEGIN 0x0000 +#define KCODE_VECTORS_END 0x002F +#define KCODE_VECTORS_UNIT_LENGTH 0x0002 +#define KCODE_VECTORS_LENGTH (KCODE_VECTORS_END - KCODE_VECTORS_BEGIN + 1) + + +/* */ +/* Kernel data memory definition */ +/* */ + +#define KDATA_BASE_ADDR 0x1000 +#define KDATA_BASE_ADDR2 0x1080 + +#define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000) +#define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001) +#define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002) +#define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003) +#define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004) +#define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005) +#define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006) +#define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007) +#define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008) + +#define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009) +#define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A) + +#define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B) +#define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C) +#define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D) +#define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E) +#define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F) +#define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010) +#define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011) +#define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012) +#define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013) +#define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014) + +#define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015) +#define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016) + +#define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017) +#define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018) + +#define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019) +#define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A) + +#define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B) +#define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C) +#define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D) + +#define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E) +#define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F) +#define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020) +#define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021) +#define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022) + +#define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023) +#define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024) +#define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025) + +#define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026) +#define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027) +#define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028) + +#define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029) +#define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A) +#define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B) +#define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C) +#define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D) +#define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E) +#define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F) +#define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030) +#define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031) +#define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032) + +#define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033) +#define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034) +#define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035) + +#define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036) +#define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037) + +#define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038) +#define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039) +#define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A) + +#define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B) +#define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C) +#define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D) +#define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E) +#define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F) +#define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040) + +#define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041) +#define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042) +#define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043) +#define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044) +#define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045) +#define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046) + +#define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047) +#define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048) +#define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049) +#define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A) +#define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B) +#define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C) + +#define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D) +#define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E) +#define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F) +#define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050) + +#define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051) +#define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052) + +#define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053) +#define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054) + +#define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055) +#define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056) +#define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057) +#define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058) +#define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059) + +#define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A) +#define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B) + +/*AY SPDIF IN */ +#define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C) +#define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D) +#define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E) + +#define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F) +#define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060) + +#define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061) + +#define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062) +#define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063) +#define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064) +#define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065) +#define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066) +#define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067) +#define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068) +#define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069) +#define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A) +#define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B) +#define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C) +#define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D) + +#define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E) +#define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F) +#define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070) +#define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071) + +#define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072) +#define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073) + +#define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074) +#define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075) +#define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076) +#define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077) + +#define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078) +#define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079) +#define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A) +#define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B) +#define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C) + + +/* */ +/* second segment */ +/* */ + +/* smart mixer buffer */ + +#define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000) +#define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001) +#define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002) +#define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003) +#define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004) +#define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005) +#define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006) +#define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007) +#define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008) +#define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009) +#define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A) +#define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B) +#define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C) +#define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D) +#define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E) +#define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F) + +#define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010) +#define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011) +#define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012) +#define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013) +#define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014) +#define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015) +#define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016) +#define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017) +#define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018) +#define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019) +#define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A) + +#define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B) +#define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C) +#define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D) +#define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E) +#define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F) +#define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020) + +/* AY */ +/* */ +/* 4 speaker support */ +/* */ + +#define KDATA_DAC2_REQUEST (KDATA_BASE_ADDR2 + 0x0021) + +#define KDATA_FMIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0022) +#define KDATA_FMIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x0023) + +#define KDATA_RMIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0024) +#define KDATA_RMIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x0025) + + +#if (REV_A_DATA_MEMORY_UNIT_LENGTH - 0x0080) +#error Assumption about DATA_MEMORY_UNIT_LENGTH size failed. +#endif + + +/* */ +/* Client data memory definition */ +/* */ + +#define CDATA_INSTANCE_READY 0x00 + +#define CDATA_HOST_SRC_ADDRL 0x01 +#define CDATA_HOST_SRC_ADDRH 0x02 +#define CDATA_HOST_SRC_END_PLUS_1L 0x03 +#define CDATA_HOST_SRC_END_PLUS_1H 0x04 +#define CDATA_HOST_SRC_CURRENTL 0x05 +#define CDATA_HOST_SRC_CURRENTH 0x06 + +#define CDATA_IN_BUF_CONNECT 0x07 +#define CDATA_OUT_BUF_CONNECT 0x08 + +#define CDATA_IN_BUF_BEGIN 0x09 +#define CDATA_IN_BUF_END_PLUS_1 0x0A +#define CDATA_IN_BUF_HEAD 0x0B +#define CDATA_IN_BUF_TAIL 0x0C + +#define CDATA_OUT_BUF_BEGIN 0x0D +#define CDATA_OUT_BUF_END_PLUS_1 0x0E +#define CDATA_OUT_BUF_HEAD 0x0F +#define CDATA_OUT_BUF_TAIL 0x10 + +#define CDATA_DMA_CONTROL 0x11 +#define CDATA_RESERVED 0x12 + +#define CDATA_FREQUENCY 0x13 +#define CDATA_LEFT_VOLUME 0x14 +#define CDATA_RIGHT_VOLUME 0x15 +#define CDATA_LEFT_SUR_VOL 0x16 +#define CDATA_RIGHT_SUR_VOL 0x17 + +#define CDATA_HEADER_LEN 0x18 + +/* */ +/* DMA control definition */ +/* */ + +#define DMACONTROL_BLOCK_MASK 0x000F +#define DMAC_BLOCK0_SELECTOR 0x0000 +#define DMAC_BLOCK1_SELECTOR 0x0001 +#define DMAC_BLOCK2_SELECTOR 0x0002 +#define DMAC_BLOCK3_SELECTOR 0x0003 +#define DMAC_BLOCK4_SELECTOR 0x0004 +#define DMAC_BLOCK5_SELECTOR 0x0005 +#define DMAC_BLOCK6_SELECTOR 0x0006 +#define DMAC_BLOCK7_SELECTOR 0x0007 +#define DMAC_BLOCK8_SELECTOR 0x0008 +#define DMAC_BLOCK9_SELECTOR 0x0009 +#define DMAC_BLOCKA_SELECTOR 0x000A +#define DMAC_BLOCKB_SELECTOR 0x000B +#define DMAC_BLOCKC_SELECTOR 0x000C +#define DMAC_BLOCKD_SELECTOR 0x000D +#define DMAC_BLOCKE_SELECTOR 0x000E +#define DMAC_BLOCKF_SELECTOR 0x000F +#define DMACONTROL_PAGE_MASK 0x00F0 +#define DMAC_PAGE0_SELECTOR 0x0030 +#define DMAC_PAGE1_SELECTOR 0x0020 +#define DMAC_PAGE2_SELECTOR 0x0010 +#define DMAC_PAGE3_SELECTOR 0x0000 +#define DMACONTROL_AUTOREPEAT 0x1000 +#define DMACONTROL_STOPPED 0x2000 +#define DMACONTROL_DIRECTION 0x0100 + + +/* */ +/* Direct mixer definition */ +/* */ + +#define DIRECTMIXER_ADC1 0x0001 +#define DIRECTMIXER_ADC2 0x0002 + + +/* */ +/* DSP to Host interrupt request definition */ +/* */ + +#define DSP2HOST_REQ_PIORECORD 0x01 +#define DSP2HOST_REQ_I2SRATE 0x02 +#define DSP2HOST_REQ_TIMER 0x04 + +/* */ +/* memory check code uses this areas */ +/* */ + +#define FLAGADD1 0x1400 /* dsp internal data */ +#define FLAGADD2 0x1800 /* dsp internal data */ +#define FLAGADD3 0x1000 /* dsp internal data */ + + +/* WARNING! DANGER! WARNING! DANGER! WARNING! DANGER! WARNING! DANGER! */ +/* */ +/* If you modify any memory map and/or definitions above be sure to reflect */ +/* the changes in the DSP version found in KERNEL.INC. */ +/* */ +/* WARNING! DANGER! WARNING! DANGER! WARNING! DANGER! WARNING! DANGER! */ + + +#define F_FREE 0x00 +#define F_USED 0x01 +#define F_END -1 + + +/* */ +/* Kernel/client memory allocation */ +/* */ + +#define NUM_UNITS_KERNEL_CODE 16 +#define NUM_UNITS_KERNEL_DATA 2 + +#define NUM_UNITS_KERNEL_CODE_WITH_HSP 16 +#ifdef NT_MODEL +#define NUM_UNITS_KERNEL_DATA_WITH_HSP 5 +#else +#define NUM_UNITS_KERNEL_DATA_WITH_HSP 4 +#endif + +#define NUM_UNITS( BYTES, UNITLEN ) ((((BYTES+1)>>1) + (UNITLEN-1)) / UNITLEN) + + +/* */ +/* Maximum instances */ +/* */ + +#define MAX_TASKS (KDATA_TASK_ENDMARK - KDATA_TASK0) + +#define MAX_INSTANCE_CPYTHRU (KDATA_INSTANCE_CPYTHRU_ENDMARK - KDATA_INSTANCE0_CPYTHRU) +#define MAX_INSTANCE_MODEM (KDATA_INSTANCE_MODEM_ENDMARK - KDATA_INSTANCE0_MODEM) +#define MAX_INSTANCE_POS3D (KDATA_INSTANCE_POS3D_ENDMARK - KDATA_INSTANCE0_POS3D) +#define MAX_INSTANCE_SPKVIRT (KDATA_INSTANCE_SPKVIRT_ENDMARK - KDATA_INSTANCE0_SPKVIRT) +#define MAX_INSTANCE_SRC (KDATA_INSTANCE_SRC_ENDMARK - KDATA_INSTANCE0_SRC) +#define MAX_INSTANCE_MINISRC (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC) +#define MAX_INSTANCE_SPDIF (KDATA_INSTANCE_SPDIF_ENDMARK - KDATA_INSTANCE0_SPDIF) + +#define MAX_VIRTUAL_DMA_CHANNELS (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0) +#define MAX_VIRTUAL_ADC1_CHANNELS (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0) +#define MAX_VIRTUAL_ADC2_CHANNELS (KDATA_ADC2_XFER_ENDMARK - KDATA_ADC2_XFER0) +#define MAX_VIRTUAL_CD_CHANNELS (KDATA_CD_XFER_ENDMARK - KDATA_CD_XFER0) +#define MAX_VIRTUAL_MIC_CHANNELS (KDATA_MIC_XFER_ENDMARK - KDATA_MIC_XFER0) + +#define MAX_VIRTUAL_I2S_CHANNELS (KDATA_I2S_XFER_ENDMARK - KDATA_I2S_XFER0) +#define MAX_VIRTUAL_CHI_CHANNELS (KDATA_CHI_XFER_ENDMARK - KDATA_CHI_XFER0) +#define MAX_VIRTUAL_SOUNDBLASTER_CHANNELS (KDATA_SOUNDBLASTER_XFER_ENDMARK - KDATA_SOUNDBLASTER_XFER0) +#define MAX_VIRTUAL_SPDIFIN_CHANNELS (KDATA_SPDIFIN_XFER_ENDMARK - KDATA_SPDIFIN_XFER0) + +/*AY */ +#define MAX_VIRTUAL_MIXER_CHANNELS (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0) +#define MAX_VIRTUAL_FMIXER_CHANNELS (KDATA_FMIXER_XFER_ENDMARK - KDATA_FMIXER_XFER0) +#define MAX_VIRTUAL_RMIXER_CHANNELS (KDATA_RMIXER_XFER_ENDMARK - KDATA_RMIXER_XFER0) + +/* */ +/* Hardware instance flags */ +/* */ + +#define HWI_FLAG_UNLOADED 0x00000001 +#define HWI_FLAG_I2S_SECONDPASS 0x00000002 +#define HWI_FLAG_FM_LOADED 0x00000004 +#define HWI_FLAG_SUSPENDED 0x00000008 +#define HWI_FLAG_HSP_PRESENT 0x00000010 +#define HWI_FLAG_MEM_CHECK 0x00000020 + +/* */ +/* Client input/output buffer connectivity */ +/* */ + +#define KCONNECT_NONE 0x0000 +#define KCONNECT_DMA 0x0001 +#define KCONNECT_ADC1 0x0002 +#define KCONNECT_ADC2 0x0003 +#define KCONNECT_CD 0x0004 +#define KCONNECT_MIC 0x0005 +#define KCONNECT_I2S 0x0006 +#define KCONNECT_CHI 0x0007 +#define KCONNECT_SOUNDBLASTER 0x0008 +#define KCONNECT_SPDIF 0x0009 +#define KCONNECT_PIO 0x000A +#define KCONNECT_MIXER 0x000B +#define KCONNECT_SPDIFIN 0x000C +#define KCONNECT_FMIXER 0x000D /*AY */ +#define KCONNECT_RMIXER 0x000E /*AY */ +#define KCONNECT_SAME 0x000F +#define NUMBER_OF_CONNECTIONS (KCONNECT_SAME + 1) + +#define MASK_KCONNECT_NONE (1 << KCONNECT_NONE) +#define MASK_KCONNECT_DMA (1 << KCONNECT_DMA) +#define MASK_KCONNECT_ADC1 (1 << KCONNECT_ADC1) +#define MASK_KCONNECT_ADC2 (1 << KCONNECT_ADC2) +#define MASK_KCONNECT_CD (1 << KCONNECT_CD) +#define MASK_KCONNECT_MIC (1 << KCONNECT_MIC) +#define MASK_KCONNECT_I2S (1 << KCONNECT_I2S) +#define MASK_KCONNECT_CHI (1 << KCONNECT_CHI) +#define MASK_KCONNECT_SOUNDBLASTER (1 << KCONNECT_SOUNDBLASTER) +#define MASK_KCONNECT_SPDIF (1 << KCONNECT_SPDIF) +#define MASK_KCONNECT_MIXER (1 << KCONNECT_MIXER) +#define MASK_KCONNECT_SPDIFIN (1 << KCONNECT_SPDIFIN) +#define MASK_KCONNECT_FMIXER (1 << KCONNECT_FMIXER) /*AY */ +#define MASK_KCONNECT_RMIXER (1 << KCONNECT_RMIXER) /*AY */ +#define MASK_KCONNECT_SAME (1 << KCONNECT_SAME) + +/* */ +/* Open/Close flags */ +/* */ + +#define KOPENCLOSE_SYNCHRONOUS 0x0001 + +/* */ +/* Switch client */ +#define KENABLE_CLIENT 0 +#define KDISABLE_CLIENT 1 + + +/* */ +/* DSP timeout */ +/* */ + +#define DSP_TIMEOUT 10000 + + +/* */ +/* DMA transfer alteration flags */ +/* */ + +#define KALTER_AUTOREPEAT 0x0001 +#define KALTER_POSITION 0x0002 + + +/* */ +/* DSP hardware */ +/* */ + +#define DSP_PORT_TIMER_COUNT 0x06 +#define DSP_PORT_MEMORY_INDEX 0x80 +#define DSP_PORT_MEMORY_TYPE 0x82 +#define DSP_PORT_MEMORY_DATA 0x84 +#define DSP_PORT_CONTROL_REG_A 0xA2 +#define DSP_PORT_CONTROL_REG_B 0xA4 +#define DSP_PORT_CONTROL_REG_C 0xA6 + +#define MEMTYPE_INTERNAL_CODE 0x0002 +#define MEMTYPE_INTERNAL_DATA 0x0003 +#define MEMTYPE_MASK 0x0003 + +#define REGB_ENABLE_RESET 0x01 +#define REGB_STOP_CLOCK 0x10 + +#define REGC_DISABLE_FM_MAPPING 0x02 + +#define DP_SHIFT_COUNT 7 + +#define DMA_BLOCK_LENGTH 32 + + +/* */ +/* kernel binary image storage */ +/* */ + +typedef struct tagKERNEL_BIN +{ + + PWORD pwBinCode; + DWORD dwLengthCode; + +} +KERNEL_BIN, *PKERNEL_BIN; + + +/* */ +/* client binary image storage */ +/* */ + +typedef struct tagCLIENT_BIN +{ + + DWORD dwCodeAddress; + + PWORD pwBinVect; + PWORD pwBinCode; + PWORD pwBinData; + + DWORD dwLengthVect; + DWORD dwLengthCode; + DWORD dwLengthData; + +} +CLIENT_BIN, *PCLIENT_BIN; + + +/* */ +/* FM client binary image storage */ +/* */ + +typedef struct tagFMCLIENT_BIN +{ + + DWORD dwCodeAddress; + DWORD dwData2Address; + + PWORD pwBinVect; + PWORD pwBinCode; + PWORD pwBinData; + PWORD pwBinData2; + + DWORD dwLengthVect; + DWORD dwLengthCode; + DWORD dwLengthData; + DWORD dwLengthData2; + +} +FMCLIENT_BIN, *PFMCLIENT_BIN; + + +/* */ +/* client */ +/* */ + +typedef struct tagCLIENT +{ + + /* kernel use only */ + + PCLIENT_BIN pClient_Bin; + DWORD dwReferenceCount; + DWORD dwMaxReference; + DWORD dwInstanceListArea; + DWORD dwDspCodeNumUnits; + PBYTE pbDspCodeMapPtr; + + /* client use */ + + DWORD dwDspCodeClientArea; + +} +CLIENT, *PCLIENT; + + +/* */ +/* client instance */ +/* */ + +typedef struct tagCLIENT_INST +{ + + /* kernel use only */ + + DWORD dwClient; + DWORD dwHostSrcBufferAddr; + DWORD dwHostSrcBufferLen; + DWORD dwHostDstBufferAddr; + DWORD dwHostDstBufferLen; + DWORD dwHostDstCurrent; + DWORD dwDSPOutBufferAddr; + DWORD dwDSPOutBufferLen; + DWORD dwDSPInConnection; + DWORD dwDSPOutConnection; + DWORD dwDspDataNumUnits; + PBYTE pbDspDataMapPtr; + + /* client use */ + + DWORD dwDspDataClientArea; + DWORD dwDspCodeClientArea; + +} +CLIENT_INST, *PCLIENT_INST; + + +/* */ +/* pass through descriptor */ +/* */ + +typedef struct tagPASSTHRU +{ + + DWORD dwDSPInConnection; + DWORD dwDSPOutConnection; + PBYTE pbDspDataMapPtr; + DWORD dwDspDataPassThruArea; + + WORD wLeftVolume; + WORD wRightVolume; + +} +PASSTHRU, *PPASSTHRU; + + +/* */ +/* Hardware instance */ +/* */ + +typedef struct tagHWI +{ + + DWORD dwDeviceID; + DWORD dwRevisionID; + DWORD dwBaseIO; + DWORD dwFlags; + + PWORD pwSuspendBuffer; + + WORD wI2SSampleCount; + WORD wI2STimerCount; + + WORD wDspResetCount; + + /* client table */ + + CLIENT asClientTable[NUMBER_OF_CLIENTS]; + + /* resource lists */ + + WORD awTaskList[MAX_TASKS + 1]; + + WORD awInstanceCpyThruList[MAX_INSTANCE_CPYTHRU + 1]; + WORD awInstanceModemList[MAX_INSTANCE_MODEM + 1]; + WORD awInstancePos3DList[MAX_INSTANCE_POS3D + 1]; + WORD awInstanceSpkVirtList[MAX_INSTANCE_SPKVIRT + 1]; + WORD awInstanceSRCList[MAX_INSTANCE_SRC + 1]; + WORD awInstanceMINISRCList[MAX_INSTANCE_MINISRC + 1]; + WORD awInstanceSPDIFList[MAX_INSTANCE_SPDIF + 1]; + + WORD awVirtualDMAList[MAX_VIRTUAL_DMA_CHANNELS + 1]; + WORD awVirtualADC1List[MAX_VIRTUAL_ADC1_CHANNELS + 1]; + WORD awVirtualADC2List[MAX_VIRTUAL_ADC2_CHANNELS + 1]; + WORD awVirtualCDList[MAX_VIRTUAL_CD_CHANNELS + 1]; + WORD awVirtualMICList[MAX_VIRTUAL_MIC_CHANNELS + 1]; + + WORD awVirtualI2SList[MAX_VIRTUAL_I2S_CHANNELS + 1]; + WORD awVirtualCHIList[MAX_VIRTUAL_CHI_CHANNELS + 1]; + + WORD awVirtualSPDIFINList[MAX_VIRTUAL_SPDIFIN_CHANNELS + 1]; + WORD awVirtualMIXERList[MAX_VIRTUAL_MIXER_CHANNELS + 1]; + + /*AY */ + WORD awVirtualFMIXERList[MAX_VIRTUAL_FMIXER_CHANNELS + 1]; + WORD awVirtualRMIXERList[MAX_VIRTUAL_RMIXER_CHANNELS + 1]; + + /* memory maps */ + + DWORD dwCodeMemoryBegin; + DWORD dwCodeMemoryEnd; + DWORD dwCodeMemoryUnitLength; + DWORD dwCodeMemoryLength; + + DWORD dwDataMemoryBegin; + DWORD dwDataMemoryEnd; + DWORD dwDataMemoryUnitLength; + DWORD dwDataMemoryLength; + + BYTE abCodeMemoryMap[CODE_MEMORY_MAP_LENGTH]; + BYTE abDataMemoryMap[DATA_MEMORY_MAP_LENGTH]; + + /* vector list */ + + WORD awVectorList[KCODE_VECTORS_LENGTH]; + +} +HWI, *PHWI; + + +/* */ +/* function return codes */ +/* */ + +typedef DWORD KRETURN; + +#define KRETURN_SUCCESS 0 +#define KRETURN_ERROR_GENERIC 1 +#define KRETURN_ERROR_BUSY 2 +#define KRETURN_ERROR_UNLOADED 3 + + +/* */ +/* external function prototypes */ +/* */ +#ifdef __cplusplus +extern "C" +{ +#endif + + WORD kDspReadWord (allegro_devc * devc, DWORD dwBaseIO, DWORD dwMemType, + DWORD dwMemAddr); + + VOID kDspWriteWord + (allegro_devc * devc, DWORD dwBaseIO, DWORD dwMemType, DWORD dwMemAddr, + WORD wMemData); + + VOID kDspReadWords + (allegro_devc * devc, DWORD dwBaseIO, + DWORD dwMemType, DWORD dwMemAddr, DWORD dwMemLen, PWORD pwHostAddr); + + VOID kDspWriteWords + (allegro_devc * devc, DWORD dwBaseIO, + DWORD dwMemType, DWORD dwMemAddr, DWORD dwMemLen, PWORD pwHostAddr); + + VOID kDspWriteZeros + (allegro_devc * devc, DWORD dwBaseIO, DWORD dwMemType, DWORD dwMemAddr, + DWORD dwMemLen); + + VOID kPIOInterruptHandler (allegro_devc * devc, PHWI phwi, + PCLIENT_INST pClient_Inst); + + VOID kI2SInterruptHandler (allegro_devc * devc, PHWI phwi, + PDWORD pdwI2SRate); + + KRETURN kQueryPosition + (allegro_devc * devc, PHWI phwi, + PCLIENT_INST pClient_Inst, DWORD dwQueryOutput, PDWORD pdwPosition); + + KRETURN kResetApuBlockCount (allegro_devc * devc, PHWI phwi, + PCLIENT_INST pClient_Inst); + + KRETURN kGetApuBlockCount + (allegro_devc * devc, PHWI phwi, PCLIENT_INST pClient_Inst, + PDWORD pdwBlockCount); + + KRETURN kInitKernel + (allegro_devc * devc, PHWI * pphwi, + DWORD dwDeviceID, DWORD dwRevisionID, DWORD dwBaseIO, DWORD dwFlags); + + KRETURN kDSPMemCheck (allegro_devc * devc, PHWI phwi); + + KRETURN kTermKernel (allegro_devc * devc, PHWI phwi, DWORD dwBaseIO); + + KRETURN kSuspendKernel (allegro_devc * devc, PHWI phwi); + + KRETURN kResumeKernel (allegro_devc * devc, PHWI phwi); + + KRETURN kOpenInstance + (allegro_devc * devc, PHWI phwi, + DWORD dwClient, + DWORD dwFlags, DWORD dwLen, PCLIENT_INST * ppClient_Inst); + + KRETURN kCloseInstance + (allegro_devc * devc, PHWI phwi, PCLIENT_INST pClient_Inst, + DWORD dwFlags); + + KRETURN kSwitchClient (allegro_devc * devc, PHWI phwi, + PCLIENT_INST pClient_Inst, DWORD dwFlags); + + KRETURN kSetInstanceReady (allegro_devc * devc, PHWI phwi, + PCLIENT_INST pClient_Inst); + + KRETURN kSetInstanceNotReady (allegro_devc * devc, PHWI phwi, + PCLIENT_INST pClient_Inst); + + KRETURN kStartTransfer + (allegro_devc * devc, PHWI phwi, + PCLIENT_INST pClient_Inst, + DWORD dwAutoRepeat, + DWORD dwHostSrcBufferAddr, + DWORD dwHostSrcBufferLen, + DWORD dwHostDstBufferAddr, + DWORD dwHostDstBufferLen, + DWORD dwDSPInBufferAddr, + DWORD dwDSPInBufferLen, + DWORD dwDSPOutBufferAddr, + DWORD dwDSPOutBufferLen, + DWORD dwDSPInConnection, DWORD dwDSPOutConnection); + + KRETURN kStopTransfer (allegro_devc * devc, PHWI phwi, + PCLIENT_INST pClient_Inst); + + KRETURN kAlterTransfer + (allegro_devc * devc, PHWI phwi, + PCLIENT_INST pClient_Inst, + DWORD dwFlags, DWORD dwAutoRepeat, DWORD dwPosition); + + KRETURN kSwitchPINConnection + (allegro_devc * devc, PHWI phwi, + PCLIENT_INST pClient_Inst, + DWORD dwDSPInConnection, DWORD dwDSPOutConnection); + + KRETURN kQueryActivity + (allegro_devc * devc, PHWI phwi, PDWORD pdwClientMasks, + PDWORD pdwConnectMasks); + + KRETURN kSetTimer (allegro_devc * devc, PHWI phwi, DWORD dwTimeInterval); + + KRETURN kOpenPassThru + (allegro_devc * devc, PHWI phwi, + PPASSTHRU * ppPassThru, + DWORD dwDSPInConnection, DWORD dwDSPOutConnection); + + KRETURN kClosePassThru (allegro_devc * devc, PHWI phwi, + PPASSTHRU pPassThru); + + KRETURN kSetVolume + (allegro_devc * devc, PHWI phwi, + PCLIENT_INST pClient_Inst, + WORD wLeftVolume, WORD wRightVolume, WORD wBoosterMode); + + KRETURN kSetRearVolume + (allegro_devc * devc, PHWI phwi, + PCLIENT_INST pClient_Inst, WORD wLeftRearVolume, WORD wRightRearVolume); + + KRETURN kSetPassThruVolume + (allegro_devc * devc, PHWI phwi, PPASSTHRU pPassThru, WORD wLeftVolume, + WORD wRightVolume); + + KRETURN kSetPassThruRearVolume + (allegro_devc * devc, PHWI phwi, + PPASSTHRU pPassThru, WORD wLeftRearVolume, WORD wRightRearVolume); + + + KRETURN kSetMasterVolume (allegro_devc * devc, PHWI phwi, WORD wLeftVolume, + WORD wRightVolume); + + + KRETURN kSetFrequency + (allegro_devc * devc, PHWI phwi, PCLIENT_INST pClient_Inst, + WORD wFrequency); + +#ifdef __cplusplus +} +#endif + + +/* */ +/* external data declarations */ +/* */ +extern KERNEL_BIN gsMemChkVectCode; +extern KERNEL_BIN gsKernelVectCode; +extern KERNEL_BIN gsKernelVectCodeWithHSP; + + + +extern CLIENT_BIN gasCpyThruVectCode[]; +extern CLIENT_BIN gasModemVectCode[]; +extern CLIENT_BIN gasPos3DVectCode[]; +extern CLIENT_BIN gasSpkVirtVectCode[]; +extern CLIENT_BIN gasSpkVirtVectCode_CRL[]; +extern CLIENT_BIN gasSRCVectCode[]; +extern CLIENT_BIN gasMINISRCVectCode[]; +extern CLIENT_BIN gasSPDIFVectCode[]; + + +extern FMCLIENT_BIN gsFMVectCode; + +extern WORD MIXER_TASK_NUMBER; + +/* */ +/* critical enter/leave */ +/* */ + +#if defined( DOS_MODEL ) || defined( WDM_MODEL ) +#define CRITENTER +#define CRITLEAVE +#endif + +#if defined( VXD_MODEL ) +#define CRITENTER _asm pushfd \ + _asm cli + +#define CRITLEAVE _asm popfd +#endif + +#ifdef WDM_MODEL +#define KCALL( func ) func +#define KBEGIN( func ) if ( KRETURN_SUCCESS == func ) { +#define KEND() } +#endif + +#ifdef NT_MODEL +#undef NULL +#define NULL 0 +#endif + +#endif + +/*--------------------------------------------------------------------------- */ +/* End of File: kernel.h */ +/*--------------------------------------------------------------------------- */ + +/****************************************************************************** + * * + * (C) 1997-1999 ESS Technology, Inc. * + * * + ******************************************************************************/ diff --git a/attic/drv/oss_allegro/kernel.inc b/attic/drv/oss_allegro/kernel.inc new file mode 100644 index 0000000..5f7c8b5 --- /dev/null +++ b/attic/drv/oss_allegro/kernel.inc @@ -0,0 +1,6225 @@ +/****************************************************************************** + * * + * (C) 1997-1999 ESS Technology, Inc. * + * * + * This source code, its compiled object code, and its associated data sets * + * are copyright (C) 1997-1999 ESS Technology, Inc. * + * * + ******************************************************************************/ + +/*--------------------------------------------------------------------------- + * Copyright (C) 1997-1999, ESS Technology, Inc. + *--------------------------------------------------------------------------- + * FILENAME: kernel.c V2.10 08/19/99 + *--------------------------------------------------------------------------- + * DESCRIPTION: Maestro 3/Allegro1 host kernel + *--------------------------------------------------------------------------- + * AUTHOR: Henry Tang/Hong Kim/Alger Yeung/Don Kim + *--------------------------------------------------------------------------- + * HISTORY: + * 09/03/97 HT Created. + * 04/23/99 AY Use C call for lowest level access (in and out) + * 04/23/99 AY Remove delay since M3/Allegro1 has no delay bug + * 04/23/99 AY Cleanup dead code + * 05/08/99 AY SPDIF support SCMS + * 05/21/99 AY Add SwitchClient API to add/remove client from/to task list + * 05/24/99 AY Enable Cpythru (dwclient=0) to be loaded even though + * its code memory is not available at certain location + * 06/02/99 AY Enable PassThru support for adc1 -> mixer & adc2->mixer + * 07/29/99 AY Adding 4-speaker support + * 08/18/99 AY Adding SPDIF IN support + * 08/18/99 AY Remove PIO and SoundBlaster support + * 08/18/99 AY Reduce Cpythru to 2 instances instead of 4 + * 09/22/99 HK Add M3I Features + *--------------------------------------------------------------------------- + */ + +#define NON_INTEL 1 /* avoid Intel x86 inline assembly instruction */ +/*#define ALLEGRO_DEBUG 1 // KERNEL debug flag */ +/*#define K_DBG 1 // KERNEL debug flag */ + +#ifdef NT_MODEL +#define HEAPZEROINIT 0 +#ifdef DON +#include "../port.h" +#include "kernel.h" +#endif +#endif + +#ifdef NON_INTEL +/*#error ******** No Intel x86 assembly instructions ************* */ +#endif + +PCLIENT_BIN kBinStructAddress (PHWI phwi, DWORD dwClient, DWORD dwSearchKey); + +/* */ +/* Client info */ +/* */ + +HWI ghwi = { + + 0, + 0, + 0, + 0, + + 0, + + 0, 0, + + 0, + + /* client table */ + + { + { + gasCpyThruVectCode, + 0, + MAX_INSTANCE_CPYTHRU, + KDATA_INSTANCE0_CPYTHRU, + 0, + 0, + 0} + , + + { + gasModemVectCode, + 0, + MAX_INSTANCE_MODEM, + KDATA_INSTANCE0_MODEM, + 0, + 0, + 0} + , + + { + gasPos3DVectCode, + 0, + MAX_INSTANCE_POS3D, + KDATA_INSTANCE0_POS3D, + 0, + 0, + 0} + , + + { + gasSpkVirtVectCode, + 0, + MAX_INSTANCE_SPKVIRT, + KDATA_INSTANCE0_SPKVIRT, + 0, + 0, + 0} + , + + { + gasSpkVirtVectCode_CRL, + 0, + MAX_INSTANCE_SPKVIRT, + KDATA_INSTANCE0_SPKVIRT, + 0, + 0, + 0} + , + + { + gasSRCVectCode, + 0, + MAX_INSTANCE_SRC, + KDATA_INSTANCE0_SRC, + 0, + 0, + 0} + , + + { + gasMINISRCVectCode, + 0, + MAX_INSTANCE_MINISRC, + KDATA_INSTANCE0_MINISRC, + 0, + 0, + 0} + , + + { + gasSPDIFVectCode, + 0, + MAX_INSTANCE_SPDIF, + KDATA_INSTANCE0_SPDIF, + 0, + 0, + 0} + + } + , +#if 0 +#if (F_FREE || (F_END != -1)) +#error Assumption about storage flags failed. +#endif +#endif + /* task resource list */ + + { + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + + (WORD) F_END} + , + + /* Copy Through resource list */ + + { + F_FREE, F_FREE, /* AY reduce to 2 for SPDIF IN */ + + (WORD) F_END} + , + + /* Modem resource list */ + + { + F_FREE, + + (WORD) F_END} + , + + /* Positional 3D resource list */ + + { + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, + + (WORD) F_END} + , + + /* Speaker Virtualization resource list */ + + { + F_FREE, + + (WORD) F_END} + , + + /* Sample Rate Conversion resource list */ + + { + F_FREE, F_FREE, + + (WORD) F_END} + , + + /* MINI Sample Rate Conversion resource list */ + + { + F_FREE, F_FREE, + F_FREE, F_FREE, + + (WORD) F_END} + , + + /* SPDIF resource list */ + + { + F_FREE, + + (WORD) F_END} + , + + /* DMA resource list */ + + { + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, + + (WORD) F_END} + , + + /* ADC1 resource list */ + + { + F_FREE, + + (WORD) F_END} + , + + /* ADC2 resource list */ + + { + F_FREE, + + (WORD) F_END} + , + + /* CD resource list */ + { + F_FREE, + + (WORD) F_END} + , + + /* MIC resource list */ + + { + F_FREE, + + (WORD) F_END} + , + + /* I2S resource list */ + + { + F_FREE, + + (WORD) F_END} + , + + /* CHI resource list */ + + { + F_FREE, + + (WORD) F_END} + , + + + /* SPDIF IN resource list */ + + { + F_FREE, + + (WORD) F_END} + , + + /* MIXER resource list */ + { + F_FREE, F_FREE, + F_FREE, F_FREE, + F_FREE, F_FREE, + F_FREE, F_FREE, + F_FREE, F_FREE, + + (WORD) F_END} + , + + /*AY */ + /* FMIXER resource list */ + { + F_FREE, + + (WORD) F_END} + , + + /* RMIXER resource list */ + { + F_FREE, + + (WORD) F_END} + , + + /* DSP code memory map */ + + 0, 0, 0, 0, + + 0, 0, 0, 0, + + { + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + + (BYTE) F_END} + , + + /* DSP data memory map */ + + { + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + + (BYTE) F_END} + , + + /* DSP vector list */ + + { + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE} + +}; + +/* */ +/* Memory map images */ +/* */ +#if 0 +#if (NUM_UNITS_KERNEL_CODE != 16) +#error Assumption about kernel code size failed. +#endif +#endif + +BYTE gabRevBCodeMemoryMapImage[] = { + F_USED, F_USED, F_USED, F_USED, /* 0000 - 03FF */ + F_USED, F_USED, F_USED, F_USED, + F_USED, F_USED, F_USED, F_USED, + F_USED, F_USED, F_USED, F_USED, + + F_FREE, F_FREE, F_FREE, F_FREE, /* 0400 - 07FF */ + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + + F_FREE, F_FREE, F_FREE, F_FREE, /* 0800 - 0BFF */ + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + + (BYTE) F_END +}; + +#if 0 +#if (NUM_UNITS_KERNEL_DATA != 2) +#error Assumption about kernel data size failed. +#endif +#endif + +#if 0 +#if (KDATA_BASE_ADDR != 0x1000) +#error Assumption about kernel data memory location failed. +#endif +#endif + +BYTE gabRevBDataMemoryMapImage[] = { + F_USED, F_USED, F_FREE, F_FREE, /* 1000 - 17FF */ + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + F_FREE, F_FREE, F_FREE, F_FREE, + + F_FREE, F_FREE, F_FREE, F_FREE, /* 1800 - 1BFF */ + F_FREE, F_FREE, F_FREE, F_FREE, + + F_USED, F_USED, F_USED, F_USED, /* 1C00 - 1FFF */ + F_USED, F_USED, F_USED, F_USED, + + F_USED, F_USED, F_USED, F_USED, /* 2000 - 27FF */ + F_USED, F_USED, F_USED, F_USED, + F_USED, F_USED, F_USED, F_USED, + F_USED, F_USED, F_USED, F_USED, + + F_USED, F_USED, F_USED, F_USED, /* 2800 - 2BFF */ + F_USED, F_USED, F_USED, F_USED, + + (BYTE) F_END +}; + + +extern WORD MIXER_TASK_NUMBER; + +#ifdef VXD_MODEL +#pragma VxD_LOCKED_CODE_SEG +#endif + +#if defined( DOS_MODEL ) || defined( NT_MODEL ) +/*-------------------------------------------------------------------------- */ +/* */ +/* PBYTE _HeapAllocate */ +/* */ +/* Description: */ +/* Allocate memory block of specified length. */ +/* */ +/* Parameters: */ +/* DWORD dwLength */ +/* Length in bytes of memory block. */ +/* */ +/* DWORD dwFlags */ +/* Allocation flags. */ +/* */ +/* Return (PBYTE): */ +/* Pointer to allocated memory block. */ +/* */ +/*-------------------------------------------------------------------------- */ + +/*ARGSUSED*/ +PBYTE +_HeapAllocate (DWORD dwLength, DWORD dwFlags) +{ +#ifdef DOS_MODEL + return (PBYTE) malloc (dwLength); +#endif + +#ifdef NT_MODEL + return (PBYTE) KERNEL_MALLOC (dwLength); +#endif + +} /* _HeapAllocate() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* DWORD _HeapFree */ +/* */ +/* Description: */ +/* Deallocate previously allocated memory block. */ +/* */ +/* Parameters: */ +/* PVOID pvBlock, */ +/* Pointer to previously allocated memory block. */ +/* */ +/* DWORD dwFlags */ +/* Allocation flags. */ +/* */ +/* Return (DWORD): */ +/* Non-zero if successful, zero otherwise. */ +/* */ +/*-------------------------------------------------------------------------- */ + +/*ARGSUSED*/ +DWORD +_HeapFree (PVOID pvBlock, DWORD dwFlags) +{ +#ifdef DOS_MODEL + free (pvBlock); +#endif + +#ifdef NT_MODEL + KERNEL_FREE (pvBlock); +#endif + + return 1; + +} /* _HeapFree() */ +#endif + +/*-------------------------------------------------------------------------- */ +/* */ +/* VOID kDelayNMicroseconds */ +/* */ +/* Description: */ +/* Delay specified number of microseconds. */ +/* */ +/* Parameters: */ +/* DWORD dwCount */ +/* Number of microseconds to delay. */ +/* */ +/* Return (VOID): */ +/* */ +/*-------------------------------------------------------------------------- */ + +VOID +kDelayNMicroseconds (DWORD dwCount) +{ + oss_udelay (dwCount); +} /* kDelayNMicroseconds() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* BYTE kInB */ +/* */ +/* Description: */ +/* Do BYTE I/O read. */ +/* */ +/* Parameters: */ +/* DWORD dwPort */ +/* I/O port address. */ +/* */ +/* Return (BYTE): */ +/* Data read from specified address. */ +/* */ +/*-------------------------------------------------------------------------- */ + +/*ARGSUSED*/ +BYTE +kInB (allegro_devc * devc, DWORD dwPort) +{ + BYTE bData; + bData = READ_PORT_UCHAR (devc->osdev, dwPort); + return bData; +} /* kInB() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* VOID kOutB */ +/* */ +/* Description: */ +/* Do BYTE I/O write. */ +/* */ +/* Parameters: */ +/* DWORD dwPort */ +/* I/O port address. */ +/* */ +/* BYTE bData */ +/* I/O port data. */ +/* */ +/* Return (VOID): */ +/* */ +/*-------------------------------------------------------------------------- */ + +/*ARGSUSED*/ +VOID +kOutB (allegro_devc * devc, DWORD dwPort, BYTE bData) +{ + WRITE_PORT_UCHAR (devc->osdev, dwPort, bData); +} /* kOutB() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* WORD kInW */ +/* */ +/* Description: */ +/* Do WORD I/O read. */ +/* */ +/* Parameters: */ +/* DWORD dwPort */ +/* I/O port address. */ +/* */ +/* Return (WORD): */ +/* Data read from specified address. */ +/* */ +/*-------------------------------------------------------------------------- */ + +/*ARGSUSED*/ +WORD +kInW (allegro_devc * devc, DWORD dwPort) +{ + WORD wData; + wData = READ_PORT_USHORT (devc->osdev, dwPort); + return wData; +} /* kInW() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* VOID kOutW */ +/* */ +/* Description: */ +/* Do WORD I/O write. */ +/* */ +/* Parameters: */ +/* DWORD dwPort */ +/* I/O port address. */ +/* */ +/* WORD wData */ +/* I/O port data. */ +/* */ +/* Return (VOID): */ +/* */ +/*-------------------------------------------------------------------------- */ + +/*ARGSUSED*/ +VOID +kOutW (allegro_devc * devc, DWORD dwPort, WORD wData) +{ + WRITE_PORT_USHORT (devc->osdev, dwPort, wData); +} /* kOutW() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* VOID kInsW */ +/* */ +/* Description: */ +/* Do WORD I/O repeat read. */ +/* */ +/* Parameters: */ +/* DWORD dwPort */ +/* I/O port address. */ +/* */ +/* DWORD dwLen */ +/* Number of WORDs to read from specified address. */ +/* */ +/* DWORD dwAddr */ +/* Host memory address to write to. */ +/* */ +/* Return (VOID): */ +/* */ +/*-------------------------------------------------------------------------- */ + +/*ARGSUSED*/ +VOID +kInsW (allegro_devc * devc, DWORD dwPort, DWORD dwLen, DWORD dwAddr) +{ +#ifdef NON_INTEL + DWORD i; + WORD *wptr; +#endif + + if (!dwLen) + return; + +#ifdef DOS_MODEL + +#ifdef NON_INTEL + wptr = (WORD *) dwAddr; + for (i = 0; i < dwLen; ++i) + { + *wptr++ = inpw (devc, (WORD) dwPort); + } /* endfor */ +#else + _asm + { + push di + push es + cld + mov cx, word ptr dwLen + mov dx, word ptr dwPort les di, dwAddr rep insw pop es pop di} +#endif + +#endif + +#if defined( VXD_MODEL ) || defined( WDM_MODEL ) || defined( NT_MODEL ) + +#ifdef NON_INTEL + wptr = (WORD *) dwAddr; + for (i = 0; i < dwLen; ++i) + { + *wptr++ = inpw (devc->osdev, (WORD) dwPort); + } /* endfor */ +#else + _asm + { + push edi + cld mov ecx, dwLen mov edx, dwPort mov edi, dwAddr rep insw pop edi} +#endif + +#endif + +} /* kInsW() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* VOID kOutsW */ +/* */ +/* Description: */ +/* Do WORD I/O repeat write. */ +/* */ +/* Parameters: */ +/* DWORD dwPort */ +/* I/O port address. */ +/* */ +/* DWORD dwLen */ +/* Number of WORDs to write to specified address. */ +/* */ +/* DWORD dwAddr */ +/* Host memory address to read from. */ +/* */ +/* Return (VOID): */ +/* */ +/*-------------------------------------------------------------------------- */ + +/*ARGSUSED*/ +VOID +kOutsW (allegro_devc * devc, DWORD dwPort, DWORD dwLen, DWORD dwAddr) +{ +#ifdef NON_INTEL + DWORD i; + WORD *wptr; +#endif + + if (!dwLen) + return; + + +#ifdef DOS_MODEL +#ifdef NON_INTEL + + wptr = (WORD *) dwAddr; + for (i = 0; i < dwLen; ++i) + { + outpw (devc, (WORD) dwPort, *wptr++); + } /* endfor */ + +#else +/*#pragma message("----Using slow I/O to overcome hardware bug") */ + _asm + { + push si + push ds + cld + mov cx, word ptr dwLen mov dx, word ptr dwPort lds si, dwAddr rep outsw; + xx: + ; + in al, 80 h; + delay !; + in al, 80 h; + in al, 80 h; + in al, 80 h; + in al, 80 h; + in al, 80 h; + in al, 80 h; + in al, 80 h; + ; + lodsw; + get data; + out dx, ax; + write it; + loop xx; + get going ... pop ds pop si} +#endif +#endif + +#if defined( VXD_MODEL ) || defined( WDM_MODEL ) || defined( NT_MODEL ) +#ifdef NON_INTEL + wptr = (WORD *) dwAddr; + for (i = 0; i < dwLen; ++i) + { + outpw (devc->osdev, (WORD) dwPort, *wptr++); + } /* endfor */ +#else + _asm + { + push esi cld mov ecx, dwLen mov edx, dwPort mov esi, dwAddr rep outsw; + xx:; + in al, 80 h; + delay !; + in al, 80 h; + in al, 80 h; + in al, 80 h; + in al, 80 h; + in al, 80 h; + in al, 80 h; + in al, 80 h; + lodsw; + get data; + out dx, ax; + write it; + loop xx; + get going ... pop esi} +#endif +#endif + +} /* kOutsW() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* WORD kDspReadWord */ +/* */ +/* Description: */ +/* Read WORD from DSP memory. */ +/* */ +/* Parameters: */ +/* DWORD dwBaseIO */ +/* Base I/O address of device. */ +/* */ +/* DWORD dwMemType */ +/* Type of memory to read from. */ +/* */ +/* DWORD dwMemAddr */ +/* Memory address to read from. */ +/* */ +/* Return (WORD): */ +/* Data read from specified address. */ +/* */ +/*-------------------------------------------------------------------------- */ + +WORD +kDspReadWord (allegro_devc * devc, DWORD dwBaseIO, DWORD dwMemType, + DWORD dwMemAddr) +{ + WORD wData; + + CRITENTER + /* 10/04/97, per Henry Tsay, write zeros to bits 15-2 of type register */ + kOutW (devc, dwBaseIO + DSP_PORT_MEMORY_TYPE, (WORD) dwMemType); + kOutW (devc, dwBaseIO + DSP_PORT_MEMORY_INDEX, (WORD) dwMemAddr); + wData = kInW (devc, dwBaseIO + DSP_PORT_MEMORY_DATA); + CRITLEAVE return wData; +} /* kDspReadWord() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* VOID kDspWriteWord */ +/* */ +/* Description: */ +/* Write WORD to DSP memory. */ +/* */ +/* Parameters: */ +/* DWORD dwBaseIO */ +/* Base I/O address of device. */ +/* */ +/* DWORD dwMemType */ +/* Type of memory to write to. */ +/* */ +/* DWORD dwMemAddr */ +/* Memory address to write to. */ +/* */ +/* WORD wMemData */ +/* Data to write to specified address. */ +/* */ +/* Return (VOID): */ +/* */ +/*-------------------------------------------------------------------------- */ + +VOID kDspWriteWord + (allegro_devc * devc, DWORD dwBaseIO, DWORD dwMemType, DWORD dwMemAddr, + WORD wMemData) +{ + + CRITENTER + /* 10/04/97, per Henry Tsay, write zeros to bits 15-2 of type register */ + kOutW (devc, dwBaseIO + DSP_PORT_MEMORY_TYPE, (WORD) dwMemType); + kOutW (devc, dwBaseIO + DSP_PORT_MEMORY_INDEX, (WORD) dwMemAddr); + kOutW (devc, dwBaseIO + DSP_PORT_MEMORY_DATA, wMemData); +CRITLEAVE} /* kDspWriteWord() */ + +/*----------------------------------------------------------------------*/ +/* */ +/* VOID kDspReadWords */ +/* */ +/* Description: */ +/* Read WORD block from DSP memory. */ +/* */ +/* Parameters: */ +/* DWORD dwBaseIO */ +/* Base I/O address of device. */ +/* */ +/* DWORD dwMemType */ +/* Type of memory to read from. */ +/* */ +/* DWORD dwMemAddr */ +/* Memory address to read from. */ +/* */ +/* DWORD dwMemLen */ +/* Number of WORDs to read from specified address. */ +/* */ +/* PWORD pwHostAddr */ +/* Host memory address to write to. */ +/* */ +/* Return (VOID): */ +/* */ +/*----------------------------------------------------------------------*/ + +VOID kDspReadWords + (allegro_devc * devc, DWORD dwBaseIO, + DWORD dwMemType, DWORD dwMemAddr, DWORD dwMemLen, PWORD pwHostAddr) +{ + + CRITENTER + /* 10/04/97, per Henry Tsay, write zeros to bits 15-2 of type register */ + kOutW (devc, dwBaseIO + DSP_PORT_MEMORY_TYPE, (WORD) dwMemType); + kOutW (devc, dwBaseIO + DSP_PORT_MEMORY_INDEX, (WORD) dwMemAddr); + kInsW (devc, dwBaseIO + DSP_PORT_MEMORY_DATA, dwMemLen, (DWORD) pwHostAddr); +CRITLEAVE} /* kDspReadWords() */ + + +/*-------------------------------------------------------------------------- */ +/* */ +/* VOID kDspReadLongWords */ +/* */ +/* Description: */ +/* Read WORD block which could be > 0x1000 from DSP memory. */ +/* Since auto-increment mode can cross 4K boundary, 4K block at a time */ +/* */ +/* Parameters: */ +/* DWORD dwBaseIO */ +/* Base I/O address of device. */ +/* */ +/* DWORD dwMemType */ +/* Type of memory to read from. */ +/* */ +/* DWORD dwMemAddr */ +/* Memory address to read from. */ +/* */ +/* DWORD dwMemLen */ +/* Number of WORDs to read from specified address. */ +/* */ +/* PWORD pwHostAddr */ +/* Host memory address to write to. */ +/* */ +/* Return (VOID): */ +/* */ +/*-------------------------------------------------------------------------- */ + +VOID kDspReadLongWords + (allegro_devc * devc, DWORD dwBaseIO, + DWORD dwMemType, DWORD dwMemLongAddr, DWORD dwMemLongLen, PWORD pwHostAddr) +{ + DWORD dwMemLen; + DWORD dwMemBegin; + WORD *pwBuffer; + + /* take care the Data area which could be > 0x1000 in size */ + dwMemLen = dwMemLongLen; + dwMemBegin = dwMemLongAddr; + pwBuffer = pwHostAddr; + + while (dwMemLen > 0) + { + if (dwMemLen >= 0x1000) + { + kDspReadWords (devc, dwBaseIO, dwMemType, dwMemBegin, 0x1000, + pwBuffer); + + dwMemBegin += 0x1000; + dwMemLen -= 0x1000; + pwBuffer = (pwBuffer + 0x1000); + + } + else + { + kDspReadWords (devc, dwBaseIO, dwMemType, dwMemBegin, dwMemLen, + pwBuffer); + + dwMemLen = 0; + + } /* endif */ + } /* endwhile */ +} /* kDspReadLongWords() */ + + +/*-------------------------------------------------------------------------- */ +/* */ +/* VOID kDspWriteWords */ +/* */ +/* Description: */ +/* Write WORD block to DSP memory. */ +/* */ +/* Parameters: */ +/* DWORD dwBaseIO */ +/* Base I/O address of device. */ +/* */ +/* DWORD dwMemType */ +/* Type of memory to write to. */ +/* */ +/* DWORD dwMemAddr */ +/* Memory address to write to. */ +/* */ +/* DWORD dwMemLen */ +/* Number of WORDs to write to specified address. */ +/* */ +/* PWORD pwHostAddr */ +/* Host memory address to read from. */ +/* */ +/* Return (VOID): */ +/* */ +/*-------------------------------------------------------------------------- */ + +VOID kDspWriteWords + (allegro_devc * devc, DWORD dwBaseIO, + DWORD dwMemType, DWORD dwMemAddr, DWORD dwMemLen, PWORD pwHostAddr) +{ + + CRITENTER + /* 10/04/97, per Henry Tsay, write zeros to bits 15-2 of type register */ + kOutW (devc, dwBaseIO + DSP_PORT_MEMORY_TYPE, (WORD) dwMemType); + kOutW (devc, dwBaseIO + DSP_PORT_MEMORY_INDEX, (WORD) dwMemAddr); + kOutsW (devc, dwBaseIO + DSP_PORT_MEMORY_DATA, dwMemLen, + (DWORD) pwHostAddr); +CRITLEAVE} /* kDspWriteWords() */ + + +/*-------------------------------------------------------------------------- */ +/* */ +/* VOID kDspWriteLongWords */ +/* */ +/* Description: */ +/* Write WORD block which could be > 0x1000 from DSP memory. */ +/* Since auto-increment mode can cross 4K boundary, 4K block at a time */ +/* */ +/* Parameters: */ +/* DWORD dwBaseIO */ +/* Base I/O address of device. */ +/* */ +/* DWORD dwMemType */ +/* Type of memory to Write to. */ +/* */ +/* DWORD dwMemAddr */ +/* Memory address to Write to . */ +/* */ +/* DWORD dwMemLen */ +/* Number of WORDs to write to specified address. */ +/* */ +/* PWORD pwHostAddr */ +/* Host memory address to read from. */ +/* */ +/* Return (VOID): */ +/* */ +/*-------------------------------------------------------------------------- */ + +VOID kDspWriteLongWords + (allegro_devc * devc, DWORD dwBaseIO, + DWORD dwMemType, DWORD dwMemLongAddr, DWORD dwMemLongLen, PWORD pwHostAddr) +{ + DWORD dwMemLen; + DWORD dwMemBegin; + WORD *pwBuffer; + + /* take care the Data area which could be > 0x1000 in size */ + dwMemLen = dwMemLongLen; + dwMemBegin = dwMemLongAddr; + pwBuffer = pwHostAddr; + + while (dwMemLen > 0) + { + if (dwMemLen >= 0x1000) + { + kDspWriteWords (devc, dwBaseIO, dwMemType, dwMemBegin, 0x1000, + pwBuffer); + + dwMemBegin += 0x1000; + dwMemLen -= 0x1000; + pwBuffer = (pwBuffer + 0x1000); + + } + else + { + kDspWriteWords (devc, dwBaseIO, + dwMemType, dwMemBegin, dwMemLen, pwBuffer); + + dwMemLen = 0; + + } /* endif */ + } /* endwhile */ +} /* kDspWriteLongWords() */ + + +/*-------------------------------------------------------------------------- */ +/* */ +/* VOID kDspWriteZeros */ +/* */ +/* Description: */ +/* Write zeros to DSP memory. */ +/* */ +/* Parameters: */ +/* DWORD dwBaseIO */ +/* Base I/O address of device. */ +/* */ +/* DWORD dwMemType */ +/* Type of memory to write to. */ +/* */ +/* DWORD dwMemAddr */ +/* Memory address to write to. */ +/* */ +/* DWORD dwMemLen */ +/* Number of WORDs of zero to write to specified address. */ +/* */ +/* Return (VOID): */ +/* */ +/*-------------------------------------------------------------------------- */ + +VOID kDspWriteZeros + (allegro_devc * devc, DWORD dwBaseIO, DWORD dwMemType, DWORD dwMemAddr, + DWORD dwMemLen) +{ + while (dwMemLen--) + { +/*#pragma message("----Using slow I/O to overcome hardware bug") */ +/* kDelayNMicroseconds( 8 ) ; */ + kDspWriteWord (devc, dwBaseIO, dwMemType, dwMemAddr++, 0); + } + +} /* kDspWriteZeros() */ + + +/*-------------------------------------------------------------------------- */ +/* */ +/* KRETURN kQueryPosition */ +/* */ +/* Description: */ +/* Return a client's current stream position. A position equal to 0 */ +/* indicates the first byte in the buffer is being transferred. A */ +/* position equal to dwHostXXXBufferLen-1 indicates the last byte */ +/* in the buffer is being transferred. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* PCLIENT_INST pClient_Inst */ +/* Pointer to client instance */ +/* */ +/* DWORD dwQueryOutput */ +/* TRUE if querying host client output position, FALSE if querying input */ +/* */ +/* PDWORD pdwPosition */ +/* Pointer to DWORD that will contain the byte position */ +/* */ +/* Return (KRETURN): */ +/* KRETURN_SUCCESS if successful, KRETURN_ERROR_XXX otherwise. */ +/* */ +/*-------------------------------------------------------------------------- */ + +KRETURN kQueryPosition + (allegro_devc * devc, PHWI phwi, + PCLIENT_INST pClient_Inst, DWORD dwQueryOutput, PDWORD pdwPosition) +{ + DWORD dwClient = pClient_Inst->dwClient; + WORD wPosition = 0; + WORD wRetry = 10; + WORD wPositionL = 0; + WORD wPositionH = 0; + PWORD pwCur; + + /* */ + /* Fail if the DSP kernel has been unloaded */ + /* */ + + if (phwi->dwFlags & HWI_FLAG_UNLOADED) + return KRETURN_ERROR_UNLOADED; + + /* */ + /* Make sure client and an instance exist... */ + /* */ + + if (dwClient >= NUMBER_OF_CLIENTS) + return KRETURN_ERROR_GENERIC; + + if (!phwi->asClientTable[dwClient].dwReferenceCount) + return KRETURN_ERROR_GENERIC; + + if ((dwQueryOutput && pClient_Inst->dwDSPInConnection == KCONNECT_DMA) || + (!dwQueryOutput && pClient_Inst->dwDSPOutConnection == KCONNECT_DMA)) + { + /* */ + /* if DMA is not active return position 0 */ + /* */ + + pwCur = phwi->awVirtualDMAList; + + while ((*pwCur != F_FREE) && (*pwCur != (WORD) F_END)) + { + if (*pwCur == + (WORD) (pClient_Inst->dwDspDataClientArea >> DP_SHIFT_COUNT)) + { + break; + } + ++pwCur; + } + + if (*pwCur != + (WORD) (pClient_Inst->dwDspDataClientArea >> DP_SHIFT_COUNT)) + { + *pdwPosition = 0; + return KRETURN_SUCCESS; + } + + /* */ + /* Get the position */ + /* */ + + while (wRetry--) + { + /* read high/low word of current position */ + + wPositionH = kDspReadWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + pClient_Inst-> + dwDspDataClientArea + + CDATA_HOST_SRC_CURRENTH); + + wPositionL = kDspReadWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + pClient_Inst-> + dwDspDataClientArea + + CDATA_HOST_SRC_CURRENTL); + + /* if the high word hasn't changed, we've got a meaningful */ + /* current position value */ + + wPosition = kDspReadWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + pClient_Inst-> + dwDspDataClientArea + + CDATA_HOST_SRC_CURRENTH); + + if (wPosition == wPositionH) + break; + } + + /* fail if we couldn't get a meaningful position */ + + if (wPosition != wPositionH) + return KRETURN_ERROR_GENERIC; + + *pdwPosition = MAKELONG (wPositionL, wPositionH) - + (dwQueryOutput ? + pClient_Inst->dwHostSrcBufferAddr : + pClient_Inst->dwHostDstBufferAddr); + } + else if (!dwQueryOutput && pClient_Inst->dwDSPOutConnection == KCONNECT_PIO) + { + /* */ + /* Get the position */ + /* */ + + *pdwPosition = pClient_Inst->dwHostDstCurrent - + pClient_Inst->dwHostDstBufferAddr; + } + else + { + return KRETURN_ERROR_GENERIC; + } + + return KRETURN_SUCCESS; + +} /* kQueryPosition() */ + + +/*-------------------------------------------------------------------------- */ +/* */ +/* BYTE kDspHalt */ +/* */ +/* Description: */ +/* Halt the DSP. */ +/* */ +/* Parameters: */ +/* DWORD dwBaseIO */ +/* Base I/O address of device. */ +/* */ +/* Return (BYTE): */ +/* Contents of reset port. */ +/* */ +/*-------------------------------------------------------------------------- */ + +BYTE +kDspHalt (allegro_devc * devc, DWORD dwBaseIO) +{ + BYTE bData; + bData = kInB (devc, dwBaseIO + DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK; + /* Fix for HP Typhoon Hibernation Problem RJJ 6/17/00 */ + kDelayNMicroseconds (10); + kOutB (devc, dwBaseIO + DSP_PORT_CONTROL_REG_B, + (BYTE) (bData & ~REGB_ENABLE_RESET)); + + return bData; + +} /* kDspHalt() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* VOID kDspReset */ +/* */ +/* Description: */ +/* Reset the DSP and let it run. */ +/* */ +/* Parameters: */ +/* DWORD dwBaseIO */ +/* Base I/O address of device. */ +/* */ +/* BYTE bData */ +/* Contents of reset port. */ +/* */ +/* Return (VOID): */ +/* */ +/*-------------------------------------------------------------------------- */ + +VOID +kDspReset (allegro_devc * devc, DWORD dwBaseIO, BYTE bData) +{ + kOutB (devc, dwBaseIO + DSP_PORT_CONTROL_REG_B, + (BYTE) (bData | REGB_ENABLE_RESET)); + +} /* kDspReset() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* VOID kDisableFMMap */ +/* */ +/* Description: */ +/* Enable/disable FM address mapping. */ +/* */ +/* Parameters: */ +/* DWORD dwBaseIO */ +/* Base I/O address of device. */ +/* */ +/* DWORD dwDisable */ +/* TRUE if disabling FM mapping, FALSE otherwise */ +/* */ +/* Return (VOID): */ +/* */ +/*-------------------------------------------------------------------------- */ + +VOID +kDisableFMMap (allegro_devc * devc, DWORD dwBaseIO, DWORD dwDisable) +{ + BYTE bData; + + bData = + kInB (devc, dwBaseIO + DSP_PORT_CONTROL_REG_C) & ~REGC_DISABLE_FM_MAPPING; + bData |= (dwDisable ? REGC_DISABLE_FM_MAPPING : 0); + kOutB (devc, dwBaseIO + DSP_PORT_CONTROL_REG_C, (BYTE) bData); + +} /* kDisableFMMap() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* VOID kRestartStreams */ +/* */ +/* Description: */ +/* Restart all previously active streams. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* Return (VOID): */ +/* */ +/*-------------------------------------------------------------------------- */ + +VOID +kRestartStreams (allegro_devc * devc, PHWI phwi) +{ + /* */ + /* reset DMA state machine in case it was active during the suspend */ + /* */ + /* If DMA was active, the worst thing that could happen is that we */ + /* will re-transfer the 16 words that were being transfered during */ + /* the suspend. The 16 words are not duplicated in the stream, they */ + /* simply overwrite the exact copy that was previously transfered. */ + /* */ + + if (phwi->awVirtualDMAList[0]) + { + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_DMA_ACTIVE, FALSE); + } + + +} /* kRestartStreams() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* DWORD kStateExists */ +/* */ +/* Description: */ +/* Checks if the specified DSP data memory location is TRUE or FALSE. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* DWORD dwMemAddr */ +/* Memory address to check. */ +/* */ +/* DWORD dwState */ +/* Specified state to check for (TRUE or FALSE) */ +/* */ +/* Return (DWORD): */ +/* TRUE if specified state exists, FALSE otherwise */ +/* */ +/*-------------------------------------------------------------------------- */ + +#define RESET_IF_TIMEOUT + +DWORD +kStateExists (allegro_devc * devc, PHWI phwi, DWORD dwMemAddr, DWORD dwState) +{ +#ifdef RESET_IF_TIMEOUT + DWORD dwResetLoops = 50; +#endif + DWORD dwLoops; + WORD wData; + BYTE bData; + + for (dwLoops = 0;; ++dwLoops) + { + wData = + kDspReadWord (devc, phwi->dwBaseIO, MEMTYPE_INTERNAL_DATA, dwMemAddr); + + if ((dwState && wData) || (!dwState && !wData)) + return TRUE; + + kDelayNMicroseconds (1); + + if (dwLoops == DSP_TIMEOUT) + { +#ifdef RESET_IF_TIMEOUT + + /* */ + /* For some as yet unknown reason, if HSP/DSP modem runs */ + /* concurrently with other DSP clients for a long time, */ + /* the DSP stops executing. Under such conditions a reset */ + /* will resume DSP execution and the clients appear to run */ + /* fine again. Hence we do a reset if we detect the DSP */ + /* kernel is no longer running. */ + /* */ + + if (--dwResetLoops) + { + dwLoops = 0; + continue; + } + + bData = kDspHalt (devc, phwi->dwBaseIO); + + kRestartStreams (devc, phwi); + + kDspReset (devc, phwi->dwBaseIO, bData); + + /* */ + /* Update our DSP reset counter. This is purely for */ + /* diagnostic purposes. */ + /* */ + + if (phwi->wDspResetCount + 1) + ++phwi->wDspResetCount; + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_DSP_RESET_COUNT, phwi->wDspResetCount); +#endif + + return FALSE; + } + } + +} /* kStateExists() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* PBYTE kAllocDspMemory */ +/* */ +/* Description: */ +/* Find and allocate available DSP memory. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* DWORD dwClient */ +/* Client ID */ +/* */ +/* PBYTE pbMemoryMap */ +/* Pointer to memory map. */ +/* */ +/* DWORD dwNumWanted */ +/* Number of contiguous memory units requested. */ +/* */ +/* Return (PBYTE): */ +/* Pointer to starting memory map unit if successful, NULL otherwise */ +/* */ +/*-------------------------------------------------------------------------- */ + +PBYTE kAllocDspMemory + (PHWI phwi, DWORD dwClient, PBYTE pbMemoryMap, DWORD dwNumWanted) +{ + PBYTE pbMemFound = NULL; + PBYTE pbMemFound2 = NULL; + DWORD dwNumFound = (DWORD) - 1; /* maximum 0xFFFF */ + PBYTE pbMemTmp; + DWORD dwNumTmp; + PBYTE pbMemType; + + + if (!dwNumWanted) + return NULL; + + pbMemType = pbMemoryMap; /*AY990524 Data & Code type */ + + /* */ + /* Search for available memory. We want to find the smallest */ + /* chunk of memory that can satisfy the request. This will minimize */ + /* memory fragmentation. */ + /* */ + + for (; *pbMemoryMap != (BYTE) F_END; ++pbMemoryMap) + { + if (*pbMemoryMap == F_USED) + continue; + + pbMemTmp = pbMemoryMap; + dwNumTmp = 1; + + while (*++pbMemoryMap == F_FREE) + ++dwNumTmp; + + if ((dwNumTmp >= dwNumWanted) && (dwNumTmp < dwNumFound)) + { + pbMemFound = pbMemTmp; + dwNumFound = dwNumTmp; + /*AY+ */ + /* */ + /* memory found, check whether it matches with client Code address */ + /* */ + if (pbMemType == (phwi->abCodeMemoryMap)) /* code memory */ + { + DWORD dwCodeArea; + /*LINTED*/ + dwCodeArea = ((pbMemFound - phwi->abCodeMemoryMap) * + phwi->dwCodeMemoryUnitLength) + + phwi->dwCodeMemoryBegin; + + if (!kBinStructAddress (phwi, dwClient, dwCodeArea)) + { + /* no code binary found */ + pbMemoryMap = pbMemTmp; /* continue with next search */ + ++pbMemoryMap; + dwCodeArea = NULL; + pbMemFound = NULL; + dwNumFound = (DWORD) - 1; + + } + else + { + + /* */ + /* At least we found something availble, so remember just in case. */ + /* */ + + pbMemFound2 = pbMemFound; + + } + + } + /*AY- */ + } + --pbMemoryMap; + } + + /* */ + /* If memory found, allocate it. Only allocate as many units that are */ + /* necessary to satisfy the request. If the smallest memory is not */ + /* found, then check whether other memory is available or not because */ + /* just failing is the last thing that kernel would want to do. */ + /* */ + + if (pbMemFound) + { + + pbMemTmp = pbMemFound; + dwNumTmp = dwNumWanted; + + while (dwNumTmp--) + *pbMemTmp++ = F_USED; + + } + else + { + if (pbMemFound2) + { + + pbMemTmp = pbMemFound2; + dwNumTmp = dwNumWanted; + pbMemFound = pbMemFound2; + + while (dwNumTmp--) + *pbMemTmp++ = F_USED; + + } + + } + + return pbMemFound; + +} /* kAllocDspMemory() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* DWORD kDeallocDspMemory */ +/* */ +/* Description: */ +/* Deallocate DSP memory. */ +/* */ +/* Parameters: */ +/* PBYTE pbMemFree */ +/* Pointer to starting memory map unit to free. */ +/* */ +/* DWORD dwNumFree */ +/* Number of contiguous memory units to free. */ +/* */ +/* Return (DWORD): */ +/* TRUE if successful, FALSE otherwise */ +/* */ +/*-------------------------------------------------------------------------- */ + +DWORD +kDeallocDspMemory (PBYTE pbMemFree, DWORD dwNumFree) +{ + + while (dwNumFree--) + *pbMemFree++ = F_FREE; + + return TRUE; + +} /* kDeallocDspMemory() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* DWORD kConnectDirectMixer */ +/* */ +/* Description: */ +/* Connect/Disconnect the specified directly mixed input and output. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* DWORD dwDSPInConnection */ +/* KCONNECT_XXX indicating input connection */ +/* */ +/* DWORD dwDSPOutConnection */ +/* KCONNECT_XXX indicating output connection */ +/* */ +/* DWORD dwConnect */ +/* TRUE if connecting, FALSE otherwise */ +/* */ +/* Return (DWORD): */ +/* TRUE if successful, FALSE otherwise */ +/* */ +/*-------------------------------------------------------------------------- */ + +DWORD kConnectDirectMixer + (allegro_devc * devc, PHWI phwi, + DWORD dwDSPInConnection, DWORD dwDSPOutConnection, DWORD dwConnect) +{ + WORD wAddress = 0; + WORD wData; + + /* */ + /* Get input setting */ + /* */ + + if (dwDSPInConnection == KCONNECT_ADC1) + wData = DIRECTMIXER_ADC1; + else if (dwDSPInConnection == KCONNECT_ADC2) + wData = DIRECTMIXER_ADC2; + else + wData = 0; + + /* */ + /* Get output setting */ + /* */ + + if ((dwDSPOutConnection == KCONNECT_SPDIF) && dwConnect) + { + /* set the DSP SPDIF request flag */ + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_SPDIF_REQUEST, TRUE); + wAddress = KDATA_SPDIF_XFER; + } + + /* */ + /* Write setting */ + /* */ + + if (dwConnect) + { + wData |= + kDspReadWord (devc, phwi->dwBaseIO, MEMTYPE_INTERNAL_DATA, wAddress); + } + else + { + wData ^= + kDspReadWord (devc, phwi->dwBaseIO, MEMTYPE_INTERNAL_DATA, wAddress); + } + + kDspWriteWord (devc, phwi->dwBaseIO, MEMTYPE_INTERNAL_DATA, wAddress, + wData); + +#if 0 +#if (NUMBER_OF_CONNECTIONS != 0x10) +#error Assumption about number of connections failed. +#endif +#endif + + return TRUE; + +} /* kConnectDirectMixer() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* DWORD kAddListEntry */ +/* */ +/* Description: */ +/* Add entry to host and DSP resource lists. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* PWORD pwHostListBegin */ +/* Start address of host resource list. */ +/* */ +/* WORD wDSPListBegin */ +/* Start address of DSP resource list. */ +/* */ +/* WORD wEntryValue */ +/* Value of entry to add. Must not equal F_FREE or F_END! */ +/* */ +/* Return (DWORD): */ +/* TRUE if successful, FALSE otherwise */ +/* */ +/*-------------------------------------------------------------------------- */ + +DWORD kAddListEntry + (allegro_devc * devc, PHWI phwi, PWORD pwHostListBegin, WORD wDSPListBegin, + WORD wEntryValue) +{ + PWORD pwCur = pwHostListBegin; + + /* */ + /* Search for an unused list entry */ + /* */ + + while (*pwCur != (WORD) F_END) + { + if (*pwCur == F_FREE) + { + /* */ + /* Write wEntryValue to both the host list and the DSP list */ + /* */ + + *pwCur = wEntryValue; + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + wDSPListBegin + (pwCur - pwHostListBegin), + wEntryValue); + return TRUE; + } + ++pwCur; + } + + return FALSE; + +} /* kAddListEntry() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* DWORD kRemoveListEntry */ +/* */ +/* Description: */ +/* Remove entry from host and DSP resource lists. Then compact */ +/* the lists if necessary. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* PWORD pwHostListBegin */ +/* Start address of host resource list. */ +/* */ +/* WORD wDSPListBegin */ +/* Start address of DSP resource list. */ +/* */ +/* WORD wEntryValue */ +/* Value of entry to remove. Must not equal F_FREE or F_END! */ +/* */ +/* Return (DWORD): */ +/* TRUE if successful, FALSE otherwise */ +/* */ +/*-------------------------------------------------------------------------- */ + +DWORD kRemoveListEntry + (allegro_devc * devc, PHWI phwi, PWORD pwHostListBegin, WORD wDSPListBegin, + WORD wEntryValue) +{ + PWORD pwCur = pwHostListBegin; + PWORD pwRemove = NULL; + + /* */ + /* Search for the entry containing wEntryValue and for the */ + /* last data entry */ + /* */ + + while ((*pwCur != F_FREE) && (*pwCur != (WORD) F_END)) + { + if (*pwCur == wEntryValue) + { + pwRemove = pwCur; + } + ++pwCur; + } + + /* Point to last data entry */ + + if (pwCur != pwHostListBegin) + { + --pwCur; + } + + /* */ + /* Fail if an entry containing wEntryValue could not be found */ + /* */ + + if (!pwRemove) + return FALSE; + + /* */ + /* OK, we've found our entry to remove and we've got the location */ + /* of the last data entry. When we remove the entry, the void */ + /* that is created is filled by moving the last data entry into */ + /* the void. The last data entry is then deleted. We have to fill */ + /* up the void because list entries are defined to be packed together */ + /* (i.e. no gaps between entries). */ + /* */ + + /* */ + /* If the entry to remove is NOT the same as the last data entry, we */ + /* first overwrite the entry to be removed with the value of the last */ + /* data entry. Then we delete the last data entry. */ + /* */ + /* If the entry to remove is the same as the last data entry, we */ + /* simply delete the last data entry. */ + /* */ + + if (pwRemove != pwCur) + { + *pwRemove = *pwCur; + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + wDSPListBegin + (pwRemove - pwHostListBegin), *pwCur); + } + + /* */ + /* Delete the last data entry */ + /* */ + + *pwCur = NULL; + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + wDSPListBegin + (pwCur - pwHostListBegin), 0); + + return TRUE; + +} /* kRemoveListEntry() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* PWORD kInstanceListAddress */ +/* */ +/* Description: */ +/* Return pointer to requested client instance list. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* DWORD dwClient */ +/* Client ID */ +/* */ +/* Return (PWORD): */ +/* Pointer to client instance list. */ +/* */ +/*-------------------------------------------------------------------------- */ + +PWORD +kInstanceListAddress (PHWI phwi, DWORD dwClient) +{ + switch (dwClient) + { + case CLIENT_CPYTHRU: + return phwi->awInstanceCpyThruList; + + case CLIENT_MODEM: + return phwi->awInstanceModemList; + + case CLIENT_POS3D: + return phwi->awInstancePos3DList; + + case CLIENT_SPKVIRT: + case CLIENT_SPKVIRT_CRL: + return phwi->awInstanceSpkVirtList; + + case CLIENT_SRC: + return phwi->awInstanceSRCList; + + case CLIENT_MINISRC: + return phwi->awInstanceMINISRCList; + + case CLIENT_SPDIF: + return phwi->awInstanceSPDIFList; + + + /* we should never end up here! */ + default: + return NULL; + } +#if 0 +#if (NUMBER_OF_CLIENTS != 8) +#error Assumption about number of clients failed. +#endif +#endif +} /* kInstanceListAddress() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* PWORD kHostXferListAddress */ +/* */ +/* Description: */ +/* Return pointer to requested host transfer list. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* DWORD dwDSPConnection */ +/* KCONNECT_XXX indicating connection */ +/* */ +/* Return (PWORD): */ +/* Pointer to host transfer list. */ +/* */ +/*-------------------------------------------------------------------------- */ + +PWORD +kHostXferListAddress (PHWI phwi, DWORD dwDSPConnection) +{ + switch (dwDSPConnection) + { + case KCONNECT_NONE: + return NULL; + + case KCONNECT_DMA: + return phwi->awVirtualDMAList; + + case KCONNECT_ADC1: + return phwi->awVirtualADC1List; + + case KCONNECT_ADC2: + return phwi->awVirtualADC2List; + + case KCONNECT_CD: + return phwi->awVirtualCDList; + + case KCONNECT_MIC: + return phwi->awVirtualMICList; + + case KCONNECT_I2S: + return phwi->awVirtualI2SList; + + case KCONNECT_CHI: + return phwi->awVirtualCHIList; + + case KCONNECT_SPDIFIN: + return phwi->awVirtualSPDIFINList; + + case KCONNECT_MIXER: + return phwi->awVirtualMIXERList; + + /*AY */ + case KCONNECT_FMIXER: + return phwi->awVirtualFMIXERList; + + case KCONNECT_RMIXER: + return phwi->awVirtualRMIXERList; + + case KCONNECT_SAME: + return NULL; + + /* we should never end up here! */ + default: + return NULL; + } +#if 0 +#if (NUMBER_OF_CONNECTIONS != 0x10) +#error Assumption about number of connections failed. +#endif +#endif +} /* kHostXferListAddress() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* WORD kDSPXferListAddress */ +/* */ +/* Description: */ +/* Return pointer to requested DSP transfer list. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* DWORD dwDSPConnection */ +/* KCONNECT_XXX indicating connection */ +/* */ +/* Return (WORD): */ +/* Pointer to DSP transfer list. */ +/* */ +/*-------------------------------------------------------------------------- */ + +/*ARGSUSED*/ +WORD +kDSPXferListAddress (PHWI phwi, DWORD dwDSPConnection) +{ + switch (dwDSPConnection) + { + case KCONNECT_NONE: + return NULL; + + case KCONNECT_DMA: + return KDATA_DMA_XFER0; + + case KCONNECT_ADC1: + return KDATA_ADC1_XFER0; + + case KCONNECT_ADC2: + return KDATA_ADC2_XFER0; + + case KCONNECT_CD: + return KDATA_CD_XFER0; + + case KCONNECT_MIC: + return KDATA_MIC_XFER0; + + case KCONNECT_I2S: + return KDATA_I2S_XFER0; + + case KCONNECT_CHI: + return KDATA_CHI_XFER0; + + case KCONNECT_SPDIF: + return KDATA_SPDIF_XFER; + + case KCONNECT_SPDIFIN: + return KDATA_SPDIFIN_XFER0; + + case KCONNECT_MIXER: + return KDATA_MIXER_XFER0; + + /*AY */ + case KCONNECT_FMIXER: + return KDATA_FMIXER_XFER0; + + case KCONNECT_RMIXER: + return KDATA_RMIXER_XFER0; + + case KCONNECT_SAME: + return NULL; + + /* we should never end up here! */ + default: + return NULL; + } +#if 0 +#if (NUMBER_OF_CONNECTIONS != 0x10) +#error Assumption about number of connections failed. +#endif +#endif +} /* kDSPXferListAddress() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* DWORD kConnectInputOutput */ +/* */ +/* Description: */ +/* Connect the specified input and output. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* DWORD dwDSPInConnection */ +/* KCONNECT_XXX indicating input connection */ +/* */ +/* DWORD dwDSPOutConnection */ +/* KCONNECT_XXX indicating output connection */ +/* */ +/* DWORD dwDspDataArea */ +/* Address of DSP data area containing connection header */ +/* */ +/* Return (DWORD): */ +/* TRUE if successful, FALSE otherwise */ +/* */ +/*-------------------------------------------------------------------------- */ + +DWORD kConnectInputOutput + (allegro_devc * devc, PHWI phwi, + DWORD dwDSPInConnection, DWORD dwDSPOutConnection, DWORD dwDspDataArea) +{ + /* */ + /* connect the input */ + /* */ + + if ((dwDSPInConnection != KCONNECT_NONE) && + (dwDSPInConnection != KCONNECT_SAME) && + (dwDSPInConnection < NUMBER_OF_CONNECTIONS)) + { + if (!kAddListEntry (devc, phwi, + kHostXferListAddress (phwi, dwDSPInConnection), + kDSPXferListAddress (phwi, dwDSPInConnection), + (WORD) (dwDspDataArea >> DP_SHIFT_COUNT))) + return FALSE; + + if (dwDSPInConnection == KCONNECT_ADC1) + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_ADC1_REQUEST, TRUE); + + + if (dwDSPInConnection == KCONNECT_ADC2) + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_ADC2_REQUEST, TRUE); + + + if (dwDSPInConnection == KCONNECT_CD) + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_CD_REQUEST, TRUE); + + if (dwDSPInConnection == KCONNECT_MIC) + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_MIC_REQUEST, TRUE); + + if (dwDSPInConnection == KCONNECT_I2S) + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_I2S_INT_METER, 0); + + if (dwDSPInConnection == KCONNECT_SPDIFIN) + { + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_SPDIFIN_INT_METER, 0); + + } + + } + else + { + /* */ + /* input buffer is connected to other instance's output buffer */ + /* */ + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + (WORD) (dwDspDataArea) + CDATA_IN_BUF_CONNECT, + (WORD) dwDSPInConnection); + } + + + /* */ + /* connect the output */ + /* */ + + if ((dwDSPOutConnection != KCONNECT_NONE) && + (dwDSPOutConnection != KCONNECT_SAME) && + (dwDSPOutConnection < NUMBER_OF_CONNECTIONS)) + { + if (!kAddListEntry (devc, phwi, + kHostXferListAddress (phwi, dwDSPOutConnection), + kDSPXferListAddress (phwi, dwDSPOutConnection), + (WORD) (dwDspDataArea >> DP_SHIFT_COUNT))) + return FALSE; + + /* */ + /* if mixer, tell the dsp the total number of mixing list */ + /* */ + + if (dwDSPOutConnection == KCONNECT_MIXER) + { + + MIXER_TASK_NUMBER++; + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_MIXER_TASK_NUMBER, MIXER_TASK_NUMBER); + } + } + else + { + /* */ + /* output buffer is connected to other instance's input buffer */ + /* */ + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + (WORD) (dwDspDataArea) + CDATA_OUT_BUF_CONNECT, + (WORD) dwDSPOutConnection); + } + + return TRUE; + +} /* kConnectInputOutput() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* DWORD kDisconnectInputOutput */ +/* */ +/* Description: */ +/* Disconnect the specified input and output. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* DWORD dwDSPInConnection */ +/* KCONNECT_XXX indicating input connection */ +/* */ +/* DWORD dwDSPOutConnection */ +/* KCONNECT_XXX indicating output connection */ +/* */ +/* DWORD dwDspDataArea */ +/* Address of DSP data area containing connection header */ +/* */ +/* Return (DWORD): */ +/* TRUE if successful, FALSE otherwise */ +/* */ +/*-------------------------------------------------------------------------- */ + +DWORD kDisconnectInputOutput + (allegro_devc * devc, PHWI phwi, + DWORD dwDSPInConnection, DWORD dwDSPOutConnection, DWORD dwDspDataArea) +{ + WORD wdata; + + /* */ + /* disconnect the input */ + /* */ + + if ((dwDSPInConnection != KCONNECT_NONE) && + (dwDSPInConnection != KCONNECT_SAME)) + { + + kRemoveListEntry (devc, phwi, + kHostXferListAddress (phwi, dwDSPInConnection), + kDSPXferListAddress (phwi, dwDSPInConnection), + (WORD) (dwDspDataArea >> DP_SHIFT_COUNT)); + + if (dwDSPInConnection == KCONNECT_ADC1) + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_ADC1_REQUEST, FALSE); + + if (dwDSPInConnection == KCONNECT_ADC2) + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_ADC2_REQUEST, FALSE); + + if (dwDSPInConnection == KCONNECT_CD) + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_CD_REQUEST, FALSE); + + if (dwDSPInConnection == KCONNECT_MIC) + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_MIC_REQUEST, FALSE); + + if (dwDSPInConnection == KCONNECT_I2S) + { + wdata = kDspReadWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_I2S_ACTIVE); + + wdata &= ~0x1; + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_I2S_ACTIVE, wdata); + } + + if (dwDSPInConnection == KCONNECT_SPDIFIN) + { + wdata = kDspReadWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_I2S_ACTIVE); + + wdata &= ~0x2; + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_I2S_ACTIVE, wdata); + } + + } + + /* */ + /* disconnect the output */ + /* */ + + if ((dwDSPOutConnection != KCONNECT_NONE) && + (dwDSPOutConnection != KCONNECT_SAME)) + { + kRemoveListEntry (devc, phwi, + kHostXferListAddress (phwi, dwDSPOutConnection), + kDSPXferListAddress (phwi, dwDSPOutConnection), + (WORD) (dwDspDataArea >> DP_SHIFT_COUNT)); + } + + /* */ + /* if mixer, tell the dsp the total number of mixing list */ + /* */ + + if (dwDSPOutConnection == KCONNECT_MIXER) + { + + MIXER_TASK_NUMBER--; + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_MIXER_TASK_NUMBER, MIXER_TASK_NUMBER); + } + + /* */ + /* handle special cases */ + /* */ + + if ((dwDSPInConnection == KCONNECT_DMA) || + (dwDSPOutConnection == KCONNECT_DMA)) + { + /* do DMA synchronization */ + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_DMA_SWITCH, FALSE); + } + + return TRUE; + +} /* kDisconnectInputOutput() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* PCLIENT_BIN kBinStructAddress */ +/* */ +/* Description: */ +/* Return pointer to requested binary image structure. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* DWORD dwClient */ +/* Client ID */ +/* */ +/* DWORD dwSearchKey */ +/* Search key */ +/* */ +/* Return (PCLIENT_BIN): */ +/* Pointer to structure if successful, NULL otherwise */ +/* */ +/*-------------------------------------------------------------------------- */ + +PCLIENT_BIN +kBinStructAddress (PHWI phwi, DWORD dwClient, DWORD dwSearchKey) +{ + PCLIENT_BIN pClient_Bin; + + if (dwClient >= NUMBER_OF_CLIENTS) + return NULL; + + pClient_Bin = phwi->asClientTable[dwClient].pClient_Bin; + + /* */ + /* If search key is NULL, then just return address of first struct */ + /* */ + + if (!dwSearchKey) + return pClient_Bin; + + /* */ + /* Search key is code load address */ + /* */ + + while (pClient_Bin->dwCodeAddress) + { + if (pClient_Bin->dwCodeAddress == dwSearchKey) + { + return pClient_Bin; + } + + ++pClient_Bin; + } + + return NULL; + +} /* kBinStructAddress() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* DWORD kAllocDspVectors */ +/* */ +/* Description: */ +/* Allocate DSP vectors required by client. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* DWORD dwClient */ +/* Client ID */ +/* */ +/* Return (DWORD): */ +/* TRUE if successful, FALSE otherwise */ +/* */ +/*-------------------------------------------------------------------------- */ + +DWORD +kAllocDspVectors (allegro_devc * devc, PHWI phwi, DWORD dwClient) +{ + PCLIENT_BIN pClient_Bin; + DWORD dwAllocate; + DWORD dwIndex; + + /* */ + /* Check if client needs to allocate DSP vectors */ + /* */ + + if (!(pClient_Bin = kBinStructAddress (phwi, dwClient, + phwi->asClientTable[dwClient]. + dwDspCodeClientArea))) + return FALSE; + + dwAllocate = FALSE; + + for (dwIndex = KCODE_VECTORS_UNIT_LENGTH; /* vector 0 reserved */ + dwIndex < KCODE_VECTORS_LENGTH; dwIndex += KCODE_VECTORS_UNIT_LENGTH) + { + if (pClient_Bin->pwBinVect[dwIndex + 0] || + pClient_Bin->pwBinVect[dwIndex + 1]) + { + dwAllocate = TRUE; + + /* fail if the vector is already allocated */ + + if ((phwi->awVectorList[dwIndex + 0] != F_FREE) || + (phwi->awVectorList[dwIndex + 1] != F_FREE)) + return FALSE; + } + } + + if (!dwAllocate) + return TRUE; + + /* */ + /* Make sure DSP kernel is ready to be halted */ + /* */ + + if (!kStateExists (devc, phwi, KDATA_HALT_ACKNOWLEDGE, FALSE)) + return FALSE; + + /* */ + /* halt the DSP kernel and wait for an acknowledgement */ + /* */ + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_HALT_SYNCH_CLIENT, TRUE); + + if (!kStateExists (devc, phwi, KDATA_HALT_ACKNOWLEDGE, TRUE)) + { + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_HALT_SYNCH_CLIENT, FALSE); + + return FALSE; + } + + /* */ + /* DSP kernel has halted, do vector allocation */ + /* */ + /* Note: We halt the DSP in order to safely modify vectors */ + /* */ + + for (dwIndex = KCODE_VECTORS_UNIT_LENGTH; /* vector 0 reserved */ + dwIndex < KCODE_VECTORS_LENGTH; dwIndex += KCODE_VECTORS_UNIT_LENGTH) + { + if (pClient_Bin->pwBinVect[dwIndex + 0] || + pClient_Bin->pwBinVect[dwIndex + 1]) + { + /* save current DSP vector */ + + phwi->awVectorList[dwIndex + 0] = + kDspReadWord (devc, phwi->dwBaseIO, MEMTYPE_INTERNAL_CODE, + dwIndex + 0); + + phwi->awVectorList[dwIndex + 1] = + kDspReadWord (devc, phwi->dwBaseIO, MEMTYPE_INTERNAL_CODE, + dwIndex + 1); + + /* write new DSP vector */ + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_CODE, + dwIndex + 0, pClient_Bin->pwBinVect[dwIndex + 0]); + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_CODE, + dwIndex + 1, pClient_Bin->pwBinVect[dwIndex + 1]); + } + } + + /* */ + /* all done, reset halt request flag to resume DSP kernel execution */ + /* */ + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_HALT_SYNCH_CLIENT, FALSE); + + return TRUE; + +} /* kAllocDspVectors() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* DWORD kDeallocDspVectors */ +/* */ +/* Description: */ +/* Deallocate DSP vectors previously required by client. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* DWORD dwClient */ +/* Client ID */ +/* */ +/* Return (DWORD): */ +/* TRUE if successful, FALSE otherwise */ +/* */ +/*-------------------------------------------------------------------------- */ + +DWORD +kDeallocDspVectors (allegro_devc * devc, PHWI phwi, DWORD dwClient) +{ + PCLIENT_BIN pClient_Bin; + DWORD dwDeallocate; + DWORD dwIndex; + + /* */ + /* Check if client needs to deallocate DSP vectors */ + /* */ + + if (!(pClient_Bin = kBinStructAddress (phwi, dwClient, + phwi->asClientTable[dwClient]. + dwDspCodeClientArea))) + return FALSE; + + dwDeallocate = FALSE; + + for (dwIndex = KCODE_VECTORS_UNIT_LENGTH; /* vector 0 reserved */ + dwIndex < KCODE_VECTORS_LENGTH; dwIndex += KCODE_VECTORS_UNIT_LENGTH) + { + if (pClient_Bin->pwBinVect[dwIndex + 0] || + pClient_Bin->pwBinVect[dwIndex + 1]) + { + dwDeallocate = TRUE; + + /* fail if the vector was not allocated */ + + if ((phwi->awVectorList[dwIndex + 0] == F_FREE) && + (phwi->awVectorList[dwIndex + 1] == F_FREE)) + return FALSE; + } + } + + if (!dwDeallocate) + return TRUE; + + /* */ + /* Make sure DSP kernel is ready to be halted */ + /* */ + + if (!kStateExists (devc, phwi, KDATA_HALT_ACKNOWLEDGE, FALSE)) + return FALSE; + + /* */ + /* halt the DSP kernel and wait for an acknowledgement */ + /* */ + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_HALT_SYNCH_CLIENT, TRUE); + + if (!kStateExists (devc, phwi, KDATA_HALT_ACKNOWLEDGE, TRUE)) + { + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_HALT_SYNCH_CLIENT, FALSE); + + return FALSE; + } + + /* */ + /* DSP kernel has halted, do vector deallocation */ + /* */ + /* Note: We halt the DSP in order to safely modify vectors */ + /* */ + + for (dwIndex = KCODE_VECTORS_UNIT_LENGTH; /* vector 0 reserved */ + dwIndex < KCODE_VECTORS_LENGTH; dwIndex += KCODE_VECTORS_UNIT_LENGTH) + { + if (pClient_Bin->pwBinVect[dwIndex + 0] || + pClient_Bin->pwBinVect[dwIndex + 1]) + { + /* restore original DSP vector */ + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_CODE, + dwIndex + 0, phwi->awVectorList[dwIndex + 0]); + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_CODE, + dwIndex + 1, phwi->awVectorList[dwIndex + 1]); + + /* reset vector list */ + + phwi->awVectorList[dwIndex + 0] = F_FREE; + phwi->awVectorList[dwIndex + 1] = F_FREE; + } + } + + /* */ + /* all done, reset halt request flag to resume DSP kernel execution */ + /* */ + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_HALT_SYNCH_CLIENT, FALSE); + + return TRUE; + +} /* kDeallocDspVectors() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* VOID kLoadKernel */ +/* */ +/* Description: */ +/* Load the kernel into DSP memory. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* DWORD dwBaseIO */ +/* Base I/O address of device. */ +/* */ +/* DWORD dwFlags */ +/* Hardware instance flags. */ +/* */ +/* Return (VOID): */ +/* */ +/*-------------------------------------------------------------------------- */ + +/*ARGSUSED*/ +VOID +kLoadKernel (allegro_devc * devc, PHWI phwi, DWORD dwBaseIO, DWORD dwFlags) +{ + BYTE bData; + + bData = kDspHalt (devc, dwBaseIO); + + kDisableFMMap (devc, dwBaseIO, TRUE); + + /* clear DSP kernel data memory */ + + kDspWriteZeros (devc, dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_BASE_ADDR, + NUM_UNITS_KERNEL_DATA * phwi->dwDataMemoryUnitLength); + + /* clear DSP kernel mixer data memory */ + + kDspWriteZeros (devc, dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_BASE_ADDR2, + NUM_UNITS_KERNEL_DATA * phwi->dwDataMemoryUnitLength); + + + /* initialize current DMA pointer */ + + kDspWriteWord (devc, dwBaseIO, MEMTYPE_INTERNAL_DATA, KDATA_CURRENT_DMA, KDATA_DMA_XFER0); /* khs 121198 */ + + /* initialize SPDIF frame status pointer and array */ + + kDspWriteWord (devc, dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_SPDIF_CURRENT_FRAME, KDATA_SPDIF_FRAME0); + + kDspWriteWord (devc, dwBaseIO, MEMTYPE_INTERNAL_DATA, KDATA_SPDIF_FRAME0, + /* 0x0204 ) ; */ + 0x0100); /*AY990508 CD data and copy prohibited for SCMS */ + + kDspWriteWord (devc, dwBaseIO, MEMTYPE_INTERNAL_DATA, KDATA_SPDIF_FRAME1, 0x0200); /*48K only */ + + /* download kernel to DSP memory */ + { + kDspWriteWords (devc, dwBaseIO, + MEMTYPE_INTERNAL_CODE, + phwi->dwCodeMemoryBegin, + (gsKernelVectCode.dwLengthCode + 1) / 2, + gsKernelVectCode.pwBinCode); + } + + /* indicate that kernel is loaded */ + phwi->dwFlags &= ~HWI_FLAG_UNLOADED; + + /* Set Master Volume to Maximum */ + kSetMasterVolume (devc, phwi, 0x7FFF, 0x7FFF); + + kDspReset (devc, dwBaseIO, bData); + +} /* kLoadKernel() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* KRETURN kInitKernel */ +/* */ +/* Description: */ +/* Initialize the host and DSP kernel. */ +/* */ +/* Parameters: */ +/* PHWI *pphwi */ +/* Pointer to Pointer to hardware instance. */ +/* */ +/* DWORD dwDeviceID */ +/* Device ID. */ +/* */ +/* DWORD dwRevisionID */ +/* Revision ID. */ +/* should always be 0x10 for M3/Allegro1 */ +/* */ +/* DWORD dwBaseIO */ +/* Base I/O address of device. */ +/* */ +/* DWORD dwFlags */ +/* Hardware instance flags. */ +/* should always be 0 since there is no difference for HSP */ +/* */ +/* Return (KRETURN): */ +/* KRETURN_SUCCESS if successful, KRETURN_ERROR_XXX otherwise. */ +/* */ +/*-------------------------------------------------------------------------- */ + +KRETURN kInitKernel + (allegro_devc * devc, PHWI * pphwi, + DWORD dwDeviceID, DWORD dwRevisionID, DWORD dwBaseIO, DWORD dwFlags) +{ + + PHWI phwi; + BYTE *pbSrc; + BYTE *pbDst; + WORD i; + +#ifdef K_DBG + _Debug_Printf_Service ("kInitKernel DID=%X RID=%X IO=%X Flag=%X\n", + dwDeviceID, dwRevisionID, dwBaseIO, dwFlags); +#endif + /* */ + /* Allocate hardware instance buffer, initialize it, and pass */ + /* the buffer address back to the caller */ + /* */ + + if (!(phwi = (PHWI) _HeapAllocate (sizeof (HWI), HEAPZEROINIT))) + return KRETURN_ERROR_GENERIC; + + *phwi = ghwi; + *pphwi = phwi; + + /* */ + /* Initialize the hardware instance */ + /* */ + + phwi->dwDeviceID = dwDeviceID; + phwi->dwRevisionID = dwRevisionID; + phwi->dwBaseIO = dwBaseIO; + phwi->dwFlags = dwFlags; /* should be 0x0 */ + + + /* */ + /* Check and report bad sectors in DSP Memory */ + /* */ +/*aaa */ + /*if (phwi -> dwFlags & HWI_FLAG_MEM_CHECK) { */ + kDSPMemCheck (devc, phwi); + /* return KRETURN_ERROR_GENERIC ; */ + /* } */ + + /* init memory map bounds */ + + { + phwi->dwCodeMemoryBegin = REV_B_CODE_MEMORY_BEGIN; + phwi->dwCodeMemoryEnd = REV_B_CODE_MEMORY_END; + phwi->dwCodeMemoryUnitLength = REV_B_CODE_MEMORY_UNIT_LENGTH; + phwi->dwCodeMemoryLength = REV_B_CODE_MEMORY_LENGTH; + + phwi->dwDataMemoryBegin = REV_B_DATA_MEMORY_BEGIN; + phwi->dwDataMemoryEnd = REV_B_DATA_MEMORY_END; + phwi->dwDataMemoryUnitLength = REV_B_DATA_MEMORY_UNIT_LENGTH; + phwi->dwDataMemoryLength = REV_B_DATA_MEMORY_LENGTH; + + /* transfer memory map images */ + + pbSrc = gabRevBCodeMemoryMapImage; + pbDst = phwi->abCodeMemoryMap; + + while ((*pbDst++ = *pbSrc++) != (BYTE) F_END); + + pbSrc = gabRevBDataMemoryMapImage; + pbDst = phwi->abDataMemoryMap; + + while ((*pbDst++ = *pbSrc++) != (BYTE) F_END); + } + + /* */ + /* Initialize the DSP */ + /* */ + + kLoadKernel (devc, phwi, dwBaseIO, dwFlags); + + + + /* testing : dump memory map to 0x1800 */ + pbDst = phwi->abDataMemoryMap; + + *pbDst++ = F_USED; + *pbDst++ = F_USED; + + pbDst = phwi->abDataMemoryMap; + + for (i = 0; i < 24; i++) + { + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + (DWORD) 0x10c0 + i, (WORD) ((*pbDst++) * 0xFFFF)); + } + + return KRETURN_SUCCESS; + +} /* kInitKernel() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* KRETURN kDSPMemCheck */ +/* */ +/* Description: */ +/* Check the DSP Data memory and update a memory map in host kernel. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* Return (KRETURN): */ +/* KRETURN_SUCCESS if successful, KRETURN_ERROR_XXX otherwise. */ +/* */ +/*-------------------------------------------------------------------------- */ +/*kkk */ +KRETURN +kDSPMemCheck (allegro_devc * devc, PHWI phwi) +{ + BYTE bData; + BYTE bData2; + + WORD wLoop = 0; + WORD wFlag = 0; + WORD wFlag2 = 1; + WORD wFlag3 = 1; + WORD i; + DWORD addr = 0; + + + /* */ + /* begin to check memory */ + /* */ + + /* save the clock speed for restoreing */ + bData2 = kInB (devc, phwi->dwBaseIO + DSP_PORT_CONTROL_REG_A); + + for (wLoop = 0; wLoop < 20; wLoop++) + { + + bData = kDspHalt (devc, phwi->dwBaseIO); + + /* change to 49Mhz for intensive memory test */ + + kOutB (devc, phwi->dwBaseIO + DSP_PORT_CONTROL_REG_A, (BYTE) 0x09); +/* kOutB( phwi -> dwBaseIO + DSP_PORT_CONTROL_REG_C, (BYTE) 0x10 ) ; */ + + + /* clear DSP kernel data memory */ + + kDspWriteZeros (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_BASE_ADDR, REV_B_DATA_MEMORY_LENGTH); + + /* load memory check code */ + + kDspWriteWords (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_CODE, + phwi->dwCodeMemoryBegin, + (gsMemChkVectCode.dwLengthCode + 1) / 2, + gsMemChkVectCode.pwBinCode); + + /* start DSP */ + + + kDspReset (devc, phwi->dwBaseIO, bData); + + for (i = 0; i < 3; i++) + { + + if (i == 0) + addr = FLAGADD1; + if (i == 1) + addr = FLAGADD2; + if (i == 2) + addr = FLAGADD3; + + + /* initialize */ + + kDspWriteWord (devc, phwi->dwBaseIO, MEMTYPE_INTERNAL_DATA, + addr + 9, wFlag); + + kDspWriteWord (devc, phwi->dwBaseIO, MEMTYPE_INTERNAL_DATA, + addr + 5, wFlag2); + + kDspWriteWord (devc, phwi->dwBaseIO, MEMTYPE_INTERNAL_DATA, + addr + 6, wFlag3); + + + /* first 1k check */ + + /*LINTED*/ + while (1) + { + + wFlag = + kDspReadWord (devc, phwi->dwBaseIO, MEMTYPE_INTERNAL_DATA, + addr); + + if (wFlag == 0x0001) /* passed */ + { + + wFlag = 0; + + kDspWriteWord (devc, phwi->dwBaseIO, MEMTYPE_INTERNAL_DATA, + addr, wFlag); + + break; + + } + else if (wFlag == 0x0002) /* found a bad sector */ + { + + wFlag = + kDspReadWord (devc, phwi->dwBaseIO, MEMTYPE_INTERNAL_DATA, + addr + 2); + + /* update memory map */ + gabRevBDataMemoryMapImage[((wFlag - + REV_B_DATA_MEMORY_BEGIN) >> 7)] + = F_USED; + + wFlag = 0; + + kDspWriteWord (devc, phwi->dwBaseIO, MEMTYPE_INTERNAL_DATA, + addr, wFlag); + + kDspWriteWord (devc, phwi->dwBaseIO, MEMTYPE_INTERNAL_DATA, + addr + 5, wFlag2); + } + + } /* while */ + + } /* for(3) */ + + } /* for(100) */ + + + /* */ + /* everything is done, so restore the clock */ + /* */ + + bData = kDspHalt (devc, phwi->dwBaseIO); + + kOutB (devc, phwi->dwBaseIO + DSP_PORT_CONTROL_REG_A, (BYTE) bData2); + + kDspReset (devc, phwi->dwBaseIO, bData); + + + return KRETURN_SUCCESS; + +} + +/*-------------------------------------------------------------------------- */ +/* */ +/* KRETURN kTermKernel */ +/* */ +/* Description: */ +/* Terminate the host and DSP kernel. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* DWORD dwBaseIO */ +/* Base I/O address of device. */ +/* */ +/* Return (KRETURN): */ +/* KRETURN_SUCCESS if successful, KRETURN_ERROR_XXX otherwise. */ +/* */ +/*-------------------------------------------------------------------------- */ + +KRETURN +kTermKernel (allegro_devc * devc, PHWI phwi, DWORD dwBaseIO) +{ + kDspHalt (devc, dwBaseIO); + + _HeapFree (phwi, 0); + + return KRETURN_SUCCESS; + +} /* kTermKernel() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* KRETURN kSuspendKernel */ +/* */ +/* Description: */ +/* Suspend the kernel and save its state. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* Return (KRETURN): */ +/* KRETURN_SUCCESS if successful, KRETURN_ERROR_XXX otherwise. */ +/* */ +/*-------------------------------------------------------------------------- */ + +KRETURN +kSuspendKernel (allegro_devc * devc, PHWI phwi) +{ + /* */ + /* FM is a special case */ + /* */ +#ifdef K_DBG + _Debug_Printf_Service ("kSuspendKernel %X\n", phwi); +#endif + + if (phwi->dwFlags & HWI_FLAG_FM_LOADED) + { + /* */ + /* Allocate host memory */ + /* */ + + if (!(phwi->pwSuspendBuffer = (PWORD) + _HeapAllocate ((phwi->dwCodeMemoryLength + + phwi->dwDataMemoryLength) * 2, HEAPZEROINIT))) + return KRETURN_ERROR_GENERIC; + + /* */ + /* Do memory save */ + /* */ + + kDspReadWords (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_CODE, + phwi->dwCodeMemoryBegin, + phwi->dwCodeMemoryLength, phwi->pwSuspendBuffer); + + kDspReadLongWords (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + phwi->dwDataMemoryBegin, + phwi->dwDataMemoryLength, + phwi->pwSuspendBuffer + phwi->dwCodeMemoryLength); + + /* */ + /* Indicate FM is suspended */ + /* */ + + phwi->dwFlags |= HWI_FLAG_SUSPENDED; + + return KRETURN_SUCCESS; + } + + /* */ + /* Fail if the DSP kernel has been unloaded */ + /* */ + + if (phwi->dwFlags & HWI_FLAG_UNLOADED) + return KRETURN_ERROR_UNLOADED; + + /* */ + /* Allocate host memory */ + /* */ + + if (!(phwi->pwSuspendBuffer = (PWORD) + _HeapAllocate ((phwi->dwCodeMemoryLength + + phwi->dwDataMemoryLength) * 2, HEAPZEROINIT))) + return KRETURN_ERROR_GENERIC; + + /* */ + /* Make sure DSP kernel is ready to be halted */ + /* */ + + if (!kStateExists (devc, phwi, KDATA_HALT_ACKNOWLEDGE, FALSE)) + goto kSuspend_Error; + + /* */ + /* halt the DSP kernel and wait for an acknowledgement */ + /* */ + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_HALT_SYNCH_CLIENT, TRUE); + + if (!kStateExists (devc, phwi, KDATA_HALT_ACKNOWLEDGE, TRUE)) + { + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_HALT_SYNCH_CLIENT, FALSE); + + goto kSuspend_Error; + } + + /* */ + /* DSP kernel has halted, do memory save */ + /* */ + /* Note: We halt the DSP in order to place it in a known state */ + /* */ + + kDspReadWords (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_CODE, + phwi->dwCodeMemoryBegin, + phwi->dwCodeMemoryLength, phwi->pwSuspendBuffer); + + kDspReadLongWords (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + phwi->dwDataMemoryBegin, + phwi->dwDataMemoryLength, + phwi->pwSuspendBuffer + phwi->dwCodeMemoryLength); + + /* */ + /* Kernel was successfully suspended, indicate kernel is unloaded */ + /* */ + + phwi->dwFlags |= (HWI_FLAG_SUSPENDED | HWI_FLAG_UNLOADED); + + return KRETURN_SUCCESS; + +kSuspend_Error: + + /* */ + /* Failure, undo all that was done... */ + /* */ + + if (phwi->pwSuspendBuffer) + { + _HeapFree (phwi->pwSuspendBuffer, 0); + } + + return KRETURN_ERROR_GENERIC; + +} /* kSuspendKernel() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* KRETURN kResumeKernel */ +/* */ +/* Description: */ +/* Resume the kernel and restore its state. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* Return (KRETURN): */ +/* KRETURN_SUCCESS if successful, KRETURN_ERROR_XXX otherwise. */ +/* */ +/*-------------------------------------------------------------------------- */ + +KRETURN +kResumeKernel (allegro_devc * devc, PHWI phwi) +{ + BYTE bData; + +#ifdef K_DBG + _Debug_Printf_Service ("kResumeKernel %X\n", phwi); +#endif + /* */ + /* FM is a special case */ + /* */ + + if (phwi->dwFlags & HWI_FLAG_FM_LOADED) + { + /* */ + /* Fail if FM isn't suspended */ + /* */ + + if (!(phwi->dwFlags & HWI_FLAG_SUSPENDED)) + return KRETURN_ERROR_GENERIC; + + /* */ + /* Do memory restore */ + /* */ + + bData = kDspHalt (devc, phwi->dwBaseIO); + + if (!phwi->pwSuspendBuffer) + return KRETURN_ERROR_GENERIC; + + kDspWriteWords (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_CODE, + phwi->dwCodeMemoryBegin, + phwi->dwCodeMemoryLength, phwi->pwSuspendBuffer); + + kDspWriteLongWords (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + phwi->dwDataMemoryBegin, + phwi->dwDataMemoryLength, + phwi->pwSuspendBuffer + phwi->dwCodeMemoryLength); + + _HeapFree (phwi->pwSuspendBuffer, 0); + + phwi->pwSuspendBuffer = 0; + + kDspReset (devc, phwi->dwBaseIO, bData); + + /* Indicate FM is no longer suspended */ + + phwi->dwFlags &= ~HWI_FLAG_SUSPENDED; + + return KRETURN_SUCCESS; + } + + /* */ + /* Fail if the kernel isn't suspended */ + /* */ + + if (!(phwi->dwFlags & HWI_FLAG_SUSPENDED)) + return KRETURN_ERROR_GENERIC; + + /* */ + /* Do memory restore */ + /* */ + + bData = kDspHalt (devc, phwi->dwBaseIO); + + if (!phwi->pwSuspendBuffer) + return KRETURN_ERROR_GENERIC; + + kDspWriteWords (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_CODE, + phwi->dwCodeMemoryBegin, + phwi->dwCodeMemoryLength, phwi->pwSuspendBuffer); + + kDspWriteLongWords (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + phwi->dwDataMemoryBegin, + phwi->dwDataMemoryLength, + phwi->pwSuspendBuffer + phwi->dwCodeMemoryLength); + + _HeapFree (phwi->pwSuspendBuffer, 0); + + phwi->pwSuspendBuffer = 0; + + kRestartStreams (devc, phwi); + + /* */ + /* all done, reset halt request flag to resume DSP kernel execution */ + /* */ + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_HALT_SYNCH_CLIENT, FALSE); + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_HALT_ACKNOWLEDGE, FALSE); + + kDspReset (devc, phwi->dwBaseIO, bData); + + /* Indicate kernel is loaded */ + + phwi->dwFlags &= ~(HWI_FLAG_SUSPENDED | HWI_FLAG_UNLOADED); + + return KRETURN_SUCCESS; + +} /* kResumeKernel() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* KRETURN kOpenInstance */ +/* */ +/* Description: */ +/* Open a client instance. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* DWORD dwClient */ +/* Client ID */ +/* */ +/* DWORD dwFlags */ +/* KOPENCLOSE_XXX flags indicating open to perform */ +/* */ +/* DWORD dwLen */ +/* Length in bytes of data area of CLIENT_INST (zero allowed) */ +/* */ +/* PCLIENT_INST *ppClient_Inst */ +/* Pointer to PCLIENT_INST that will contain the instance pointer */ +/* */ +/* Return (KRETURN): */ +/* KRETURN_SUCCESS if successful, KRETURN_ERROR_XXX otherwise. */ +/* */ +/*-------------------------------------------------------------------------- */ + +KRETURN kOpenInstance + (allegro_devc * devc, PHWI phwi, + DWORD dwClient, DWORD dwFlags, DWORD dwLen, PCLIENT_INST * ppClient_Inst) +{ + PCLIENT_INST pClient_Inst = NULL; + PCLIENT_BIN pClient_Bin = NULL; + +#ifdef K_DBG + _Debug_Printf_Service ("kOpenInstance %X %X %X %X\n", phwi, + dwClient, dwFlags, dwLen); +#endif + /* */ + /* Fail if the DSP kernel has been unloaded */ + /* */ + + if (phwi->dwFlags & HWI_FLAG_UNLOADED) + return KRETURN_ERROR_UNLOADED; + +#ifndef NT_MODEL + /* */ + /* FM client is a special case */ + /* */ + /* The FM client isn't really a client of the DSP kernel. It requires */ + /* the entire DSP to execute therefore the DSP kernel must be swapped */ + /* out of the DSP before it can run. When FM is closed the DSP kernel */ + /* is reloaded into the DSP. */ + /* */ + + if (dwClient == CLIENT_FM) + { + DWORD dwClientMasks; + DWORD dwConnectMasks; + BYTE bData; + + /* Fail if the DSP kernel is not idle */ + + if (kQueryActivity (devc, phwi, &dwClientMasks, &dwConnectMasks) != + KRETURN_SUCCESS) + return KRETURN_ERROR_GENERIC; + + if (dwClientMasks || dwConnectMasks) + return KRETURN_ERROR_BUSY; + + /* */ + /* Allocate host memory */ + /* */ + + if (!(pClient_Inst = (PCLIENT_INST) + _HeapAllocate (sizeof (CLIENT_INST) + dwLen, HEAPZEROINIT))) + return KRETURN_ERROR_GENERIC; + + pClient_Inst->dwClient = dwClient; + + *ppClient_Inst = pClient_Inst; + + /* download FM client to DSP memory */ + + bData = kDspHalt (devc, phwi->dwBaseIO); + + kDisableFMMap (devc, phwi->dwBaseIO, FALSE); + + kDspWriteWords (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_CODE, + phwi->dwCodeMemoryBegin, + (gsFMVectCode.dwLengthVect + 1) / 2, + gsFMVectCode.pwBinVect); + + kDspWriteWords (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_CODE, + gsFMVectCode.dwCodeAddress, + (gsFMVectCode.dwLengthCode + 1) / 2, + gsFMVectCode.pwBinCode); + + kDspWriteWords (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + phwi->dwDataMemoryBegin, + (gsFMVectCode.dwLengthData + 1) / 2, + gsFMVectCode.pwBinData); + + kDspWriteWords (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + gsFMVectCode.dwData2Address, + (gsFMVectCode.dwLengthData2 + 1) / 2, + gsFMVectCode.pwBinData2); + + kDspReset (devc, phwi->dwBaseIO, bData); + + /* FM client was successfully loaded, indicate kernel is unloaded */ + + phwi->dwFlags |= (HWI_FLAG_FM_LOADED | HWI_FLAG_UNLOADED); + + return KRETURN_SUCCESS; + } +#endif + + /* */ + /* Do open/close synchronization */ + /* */ + /* Generally, an open can safely be done except just after a close. */ + /* The reason a close might cause a problem is that when a client */ + /* requests a close, the host-side may close but the DSP-side */ + /* may be executing AT THAT MOMENT. This means the host-side thinks */ + /* resources that were formally allocated are now free, whereas on */ + /* the DSP-side they actually are still in use. So if an open is done, */ + /* and the open happens to be assigned some of these same resources, a */ + /* resource conflict arises. For example, the executable of the open */ + /* client might get downloaded over the still executing close client, */ + /* likely causing a DSP crash. */ + /* */ + /* One way to overcome this danger is by making sure a client task */ + /* switch has occured SINCE THE CLOSE WAS COMPLETED. A task switch */ + /* covers the following cases: */ + /* */ + /* 1) A DSP-side client is executing just as the kernel closes it. */ + /* A subsequent task switch means this client is no longer running, */ + /* so the close is complete and the freed resources are available. */ + /* */ + /* 2) A DSP-side client is idle when the kernel closes it. A */ + /* subsequent task switch to this client either means the client */ + /* doesn't run at all (client closed) or an instance is not */ + /* processed at all (instance closed). Thus the resources */ + /* previously used by the client or instance are freed. */ + /* */ + + if (!kStateExists (devc, phwi, KDATA_TASK_SWITCH, TRUE)) + return KRETURN_ERROR_BUSY; + + /* */ + /* Make sure client and an available instance exist... */ + /* */ + + if (dwClient >= NUMBER_OF_CLIENTS) + return KRETURN_ERROR_GENERIC; + + if (phwi->asClientTable[dwClient].dwReferenceCount >= + phwi->asClientTable[dwClient].dwMaxReference) + return KRETURN_ERROR_GENERIC; + + /* */ + /* Allocate host memory */ + /* */ + + if (!(pClient_Inst = (PCLIENT_INST) + _HeapAllocate (sizeof (CLIENT_INST) + dwLen, HEAPZEROINIT))) + goto kOpen_Error; + + pClient_Inst->dwClient = dwClient; + pClient_Inst->dwDspDataNumUnits = + NUM_UNITS (dwLen, phwi->dwDataMemoryUnitLength); + + /* */ + /* Allocate DSP data memory */ + /* */ + + if (dwLen) + { + if (!(pClient_Inst->pbDspDataMapPtr = + kAllocDspMemory (phwi, NULL, + phwi->abDataMemoryMap, + pClient_Inst->dwDspDataNumUnits))) + goto kOpen_Error; + + pClient_Inst->dwDspDataClientArea = + /*LINTED*/ + ((pClient_Inst->pbDspDataMapPtr - phwi->abDataMemoryMap) * + phwi->dwDataMemoryUnitLength) + phwi->dwDataMemoryBegin; + + /* clear DSP client data memory */ + + kDspWriteZeros (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + pClient_Inst->dwDspDataClientArea, + pClient_Inst->dwDspDataNumUnits * + phwi->dwDataMemoryUnitLength); + + /* download client data binary */ + + if (!(pClient_Bin = kBinStructAddress (phwi, dwClient, NULL))) + goto kOpen_Error; + + /* make sure allocation size can hold data binary */ + + if (dwLen < pClient_Bin->dwLengthData) + goto kOpen_Error; + + kDspWriteWords (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + pClient_Inst->dwDspDataClientArea, + (pClient_Bin->dwLengthData + 1) / 2, + pClient_Bin->pwBinData); + + /* add instance to instance list */ + if (dwFlags & KOPENCLOSE_SYNCHRONOUS) + /*if ( 0 ) */ + { + DWORD dwReturn; + + /* */ + /* Make sure DSP kernel is ready to be halted */ + /* */ + + if (!kStateExists (devc, phwi, KDATA_HALT_ACKNOWLEDGE, FALSE)) + goto kOpen_Error; + + /* */ + /* halt the DSP kernel and wait for an acknowledgement */ + /* */ + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_HALT_SYNCH_CLIENT, TRUE); + + if (!kStateExists (devc, phwi, KDATA_HALT_ACKNOWLEDGE, TRUE)) + { + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_HALT_SYNCH_CLIENT, FALSE); + + goto kOpen_Error; + } + + /* */ + /* DSP kernel has halted, do open */ + /* */ + /* Note: We halt the DSP in order to synchronize the open */ + /* with the client */ + /* */ + + dwReturn = kAddListEntry (devc, phwi, + kInstanceListAddress (phwi, dwClient), + (WORD) phwi->asClientTable[dwClient]. + dwInstanceListArea, + (WORD) (pClient_Inst-> + dwDspDataClientArea >> + DP_SHIFT_COUNT)); + + /* */ + /* all done, reset halt request flag to resume DSP kernel execution */ + /* */ + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_HALT_SYNCH_CLIENT, FALSE); + + if (!dwReturn) + goto kOpen_Error; + } + else + { + if (!kAddListEntry (devc, phwi, + kInstanceListAddress (phwi, dwClient), + (WORD) phwi->asClientTable[dwClient]. + dwInstanceListArea, + (WORD) (pClient_Inst-> + dwDspDataClientArea >> DP_SHIFT_COUNT))) + goto kOpen_Error; + + } + + + + } + +/*#pragma message("----Assuming individual client code binaries are equal length!") */ + + phwi->asClientTable[dwClient].dwDspCodeNumUnits = + NUM_UNITS (phwi->asClientTable[dwClient].pClient_Bin->dwLengthCode, + phwi->dwCodeMemoryUnitLength); + + /* */ + /* Allocate DSP code memory */ + /* */ + + if (!phwi->asClientTable[dwClient].dwReferenceCount) + { + if (!(phwi->asClientTable[dwClient].pbDspCodeMapPtr = + kAllocDspMemory (phwi, dwClient, + phwi->abCodeMemoryMap, + phwi->asClientTable[dwClient]. + dwDspCodeNumUnits))) + goto kOpen_Error; + + phwi->asClientTable[dwClient].dwDspCodeClientArea = + /*LINTED*/ + ((phwi->asClientTable[dwClient].pbDspCodeMapPtr - + phwi->abCodeMemoryMap) * phwi->dwCodeMemoryUnitLength) + + phwi->dwCodeMemoryBegin; + + pClient_Inst->dwDspCodeClientArea = + phwi->asClientTable[dwClient].dwDspCodeClientArea; + + /* clear DSP client code memory */ + + kDspWriteZeros (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_CODE, + phwi->asClientTable[dwClient].dwDspCodeClientArea, + phwi->asClientTable[dwClient].dwDspCodeNumUnits * + phwi->dwCodeMemoryUnitLength); + + /* download client code binary */ + + if (!(pClient_Bin = kBinStructAddress (phwi, dwClient, + phwi->asClientTable[dwClient]. + dwDspCodeClientArea))) + goto kOpen_Error; + + kDspWriteWords (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_CODE, + phwi->asClientTable[dwClient].dwDspCodeClientArea, + (pClient_Bin->dwLengthCode + 1) / 2, + pClient_Bin->pwBinCode); + + /* allocate DSP vectors */ + + if (!kAllocDspVectors (devc, phwi, dwClient)) + goto kOpen_Error; + + /* add client to task list */ + + if (!kAddListEntry (devc, phwi, + phwi->awTaskList, + KDATA_TASK0, + (WORD) phwi->asClientTable[dwClient]. + dwDspCodeClientArea)) + goto kOpen_Error; + } + else + { + pClient_Inst->dwDspCodeClientArea = + phwi->asClientTable[dwClient].dwDspCodeClientArea; + } + + /* */ + /* Everything worked, increment reference counter */ + /* */ + + ++phwi->asClientTable[dwClient].dwReferenceCount; + + *ppClient_Inst = pClient_Inst; +#ifdef K_DBG + _Debug_Printf_Service ("kOpenInstance OK %X\n", pClient_Inst); +#endif + + return KRETURN_SUCCESS; + +kOpen_Error: + + /* */ + /* Failure, undo all that was done... */ + /* */ + + if (!phwi->asClientTable[dwClient].dwReferenceCount) + { + if (phwi->asClientTable[dwClient].pbDspCodeMapPtr) + { + kDeallocDspVectors (devc, phwi, dwClient); + + kDeallocDspMemory (phwi->asClientTable[dwClient].pbDspCodeMapPtr, + phwi->asClientTable[dwClient].dwDspCodeNumUnits); + phwi->asClientTable[dwClient].pbDspCodeMapPtr = NULL; + } + } + + if (pClient_Inst) + { + if (pClient_Inst->pbDspDataMapPtr) + { + kRemoveListEntry (devc, phwi, + kInstanceListAddress (phwi, dwClient), + (WORD) phwi->asClientTable[dwClient]. + dwInstanceListArea, + (WORD) (pClient_Inst-> + dwDspDataClientArea >> DP_SHIFT_COUNT)); + + kDeallocDspMemory (pClient_Inst->pbDspDataMapPtr, + pClient_Inst->dwDspDataNumUnits); + } + + _HeapFree (pClient_Inst, 0); + } +#ifdef K_DBG + _Debug_Printf_Service ("kOpenInstance Failed\n"); +#endif + + return KRETURN_ERROR_GENERIC; + +} /* kOpenInstance() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* KRETURN kCloseInstance */ +/* */ +/* Description: */ +/* Close a client instance. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* PCLIENT_INST pClient_Inst */ +/* Pointer to client instance */ +/* */ +/* DWORD dwFlags */ +/* KOPENCLOSE_XXX flags indicating close to perform */ +/* */ +/* Return (KRETURN): */ +/* KRETURN_SUCCESS if successful, KRETURN_ERROR_XXX otherwise. */ +/* */ +/*-------------------------------------------------------------------------- */ + +KRETURN +kCloseInstance (allegro_devc * devc, PHWI phwi, PCLIENT_INST pClient_Inst, + DWORD dwFlags) +{ + DWORD dwClient = pClient_Inst->dwClient; + +#ifdef K_DBG + _Debug_Printf_Service ("kCloseInstance %X %X %X\n", phwi, + pClient_Inst, dwFlags); + + +#endif +#ifndef NT_MODEL + /* */ + /* FM client is a special case */ + /* */ + + if (dwClient == CLIENT_FM) + { + /* Fail if the FM client isn't open */ + + if (!(phwi->dwFlags & HWI_FLAG_FM_LOADED)) + return KRETURN_ERROR_GENERIC; + + kLoadKernel (devc, phwi, phwi->dwBaseIO, phwi->dwFlags); + + _HeapFree (pClient_Inst, 0); + + /* Indicate kernel is loaded */ + + phwi->dwFlags &= ~(HWI_FLAG_FM_LOADED | HWI_FLAG_UNLOADED); + + return KRETURN_SUCCESS; + } +#endif + + /* */ + /* Fail if the DSP kernel has been unloaded */ + /* */ + + if (phwi->dwFlags & HWI_FLAG_UNLOADED) + return KRETURN_ERROR_UNLOADED; + + /* */ + /* Do DMA synchronization */ + /* */ + /* (see discussion in kOpenInstance) */ + /* */ + + if (!kStateExists (devc, phwi, KDATA_DMA_SWITCH, TRUE)) + return KRETURN_ERROR_BUSY; + + /* */ + /* Make sure client and an instance exist... */ + /* */ + + if (dwClient >= NUMBER_OF_CLIENTS) + return KRETURN_ERROR_GENERIC; + + if (!phwi->asClientTable[dwClient].dwReferenceCount) + return KRETURN_ERROR_GENERIC; + + /* */ + /* Deallocate memory */ + /* */ + + if (--phwi->asClientTable[dwClient].dwReferenceCount == 0) + { + /* remove client from task list */ + + kRemoveListEntry (devc, phwi, + phwi->awTaskList, + KDATA_TASK0, + (WORD) phwi->asClientTable[dwClient]. + dwDspCodeClientArea); + + if (!phwi->asClientTable[dwClient].pbDspCodeMapPtr) + return KRETURN_ERROR_GENERIC; + + kDeallocDspVectors (devc, phwi, dwClient); + + kDeallocDspMemory (phwi->asClientTable[dwClient].pbDspCodeMapPtr, + phwi->asClientTable[dwClient].dwDspCodeNumUnits); + phwi->asClientTable[dwClient].pbDspCodeMapPtr = NULL; + } + + + if (!pClient_Inst) + return KRETURN_ERROR_GENERIC; + + if (pClient_Inst->pbDspDataMapPtr) + { + if (dwFlags & KOPENCLOSE_SYNCHRONOUS) + /* if ( 0 ) */ + { + /* */ + /* Make sure DSP kernel is ready to be halted */ + /* */ + + if (!kStateExists (devc, phwi, KDATA_HALT_ACKNOWLEDGE, FALSE)) + goto kClose_Error; + + /* */ + /* halt the DSP kernel and wait for an acknowledgement */ + /* */ + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_HALT_SYNCH_CLIENT, TRUE); + + kStateExists (devc, phwi, KDATA_HALT_ACKNOWLEDGE, TRUE); + + kClose_Error: + + /* */ + /* DSP kernel has halted, do close */ + /* */ + /* Note: We halt the DSP in order to synchronize the close */ + /* with the client */ + /* */ + + kRemoveListEntry (devc, phwi, + kInstanceListAddress (phwi, dwClient), + (WORD) phwi->asClientTable[dwClient]. + dwInstanceListArea, + (WORD) (pClient_Inst-> + dwDspDataClientArea >> DP_SHIFT_COUNT)); + + /* */ + /* all done, reset halt request flag to resume DSP kernel execution */ + /* */ + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_HALT_SYNCH_CLIENT, FALSE); + } + else + { + kRemoveListEntry (devc, phwi, + kInstanceListAddress (phwi, dwClient), + (WORD) phwi->asClientTable[dwClient]. + dwInstanceListArea, + (WORD) (pClient_Inst-> + dwDspDataClientArea >> DP_SHIFT_COUNT)); + + } + + kDeallocDspMemory (pClient_Inst->pbDspDataMapPtr, + pClient_Inst->dwDspDataNumUnits); + } + + _HeapFree (pClient_Inst, 0); + + /* */ + /* Do open/close synchronization */ + /* */ + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_TASK_SWITCH, FALSE); + +#ifdef K_DBG + _Debug_Printf_Service ("kCloseInstance OK\n"); +#endif + return KRETURN_SUCCESS; + +} /* kCloseInstance() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* KRETURN kSwitchClient */ +/* */ +/* Description: */ +/* Remove/Add the client from/to the task list. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* PCLIENT_INST pClient_Inst */ +/* Pointer to client instance */ +/* */ +/* DWORD dwFlags */ +/* KENABLE_CLIENT flags adding client back to task list */ +/* KDISABLE_CLIENT flags removing client from task list */ +/* */ +/* Return (KRETURN): */ +/* KRETURN_SUCCESS if successful, KRETURN_ERROR_XXX otherwise. */ +/* */ +/*-------------------------------------------------------------------------- */ + +KRETURN +kSwitchClient (allegro_devc * devc, PHWI phwi, PCLIENT_INST pClient_Inst, + DWORD dwFlags) +{ + DWORD dwClient = pClient_Inst->dwClient; +#ifdef K_DBG + _Debug_Printf_Service ("kSwitchClient %X %X %X\n", phwi, + pClient_Inst, dwFlags); + + + +#endif + /* */ + /* Fail if the DSP kernel has been unloaded */ + /* */ + + if (phwi->dwFlags & HWI_FLAG_UNLOADED) + return KRETURN_ERROR_UNLOADED; + + /* */ + /* Do DMA synchronization */ + /* */ + /* (see discussion in kOpenInstance) */ + /* */ + + if (!kStateExists (devc, phwi, KDATA_DMA_SWITCH, TRUE)) + return KRETURN_ERROR_BUSY; + + /* */ + /* Make sure client and an instance exist... */ + /* */ + + if (dwClient >= NUMBER_OF_CLIENTS) + return KRETURN_ERROR_GENERIC; + + if (phwi->asClientTable[dwClient].dwReferenceCount != 1) + return KRETURN_ERROR_GENERIC; + + if (dwFlags == KDISABLE_CLIENT) + { + /* remove client from task list */ + + kRemoveListEntry (devc, phwi, + phwi->awTaskList, + KDATA_TASK0, + (WORD) phwi->asClientTable[dwClient]. + dwDspCodeClientArea); + + } + else + { + if (dwFlags == KENABLE_CLIENT) + { + /* add client to task list */ + + if (!kAddListEntry (devc, phwi, + phwi->awTaskList, + KDATA_TASK0, + (WORD) phwi->asClientTable[dwClient]. + dwDspCodeClientArea)) + { + return KRETURN_ERROR_GENERIC; + } + + } + else + { + return KRETURN_ERROR_GENERIC; + } /* endif */ + } /* endif */ + +#ifdef K_DBG + _Debug_Printf_Service ("kSwitchClient OK\n"); +#endif + + return KRETURN_SUCCESS; + +} /* kSwitchClient() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* KRETURN kSetInstanceReady */ +/* */ +/* Description: */ +/* Set a client instance to the ready state. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* PCLIENT_INST pClient_Inst */ +/* Pointer to client instance */ +/* */ +/* Return (KRETURN): */ +/* KRETURN_SUCCESS if successful, KRETURN_ERROR_XXX otherwise. */ +/* */ +/*-------------------------------------------------------------------------- */ + +KRETURN +kSetInstanceReady (allegro_devc * devc, PHWI phwi, PCLIENT_INST pClient_Inst) +{ + DWORD dwClient = pClient_Inst->dwClient; + +#ifdef K_DBG + _Debug_Printf_Service ("kSetInstanceReady %X %x\n", phwi, pClient_Inst); +#endif + /* */ + /* Fail if the DSP kernel has been unloaded */ + /* */ + + if (phwi->dwFlags & HWI_FLAG_UNLOADED) + return KRETURN_ERROR_UNLOADED; + + /* */ + /* Make sure client and an instance exist... */ + /* */ + + if (dwClient >= NUMBER_OF_CLIENTS) + return KRETURN_ERROR_GENERIC; + + if (!phwi->asClientTable[dwClient].dwReferenceCount) + return KRETURN_ERROR_GENERIC; + + /* */ + /* Set the instance ready flag */ + /* */ + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + pClient_Inst-> + dwDspDataClientArea + CDATA_INSTANCE_READY, TRUE); + + return KRETURN_SUCCESS; + +} /* kSetInstanceReady() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* KRETURN kSetInstanceNotReady */ +/* */ +/* Description: */ +/* Set a client instance to the not ready state. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* PCLIENT_INST pClient_Inst */ +/* Pointer to client instance */ +/* */ +/* Return (KRETURN): */ +/* KRETURN_SUCCESS if successful, KRETURN_ERROR_XXX otherwise. */ +/* */ +/*-------------------------------------------------------------------------- */ + +KRETURN +kSetInstanceNotReady (allegro_devc * devc, PHWI phwi, + PCLIENT_INST pClient_Inst) +{ + DWORD dwClient = pClient_Inst->dwClient; + +#ifdef K_DBG + _Debug_Printf_Service ("kSetInstanceNotReady %X %x\n", phwi, pClient_Inst); +#endif + /* */ + /* Fail if the DSP kernel has been unloaded */ + /* */ + + if (phwi->dwFlags & HWI_FLAG_UNLOADED) + return KRETURN_ERROR_UNLOADED; + + /* */ + /* Make sure client and an instance exist... */ + /* */ + + if (dwClient >= NUMBER_OF_CLIENTS) + return KRETURN_ERROR_GENERIC; + + if (!phwi->asClientTable[dwClient].dwReferenceCount) + return KRETURN_ERROR_GENERIC; + + /* */ + /* Clear the instance ready flag */ + /* */ + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + pClient_Inst-> + dwDspDataClientArea + CDATA_INSTANCE_READY, FALSE); + + return KRETURN_SUCCESS; + +} /* kSetInstanceNotReady() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* KRETURN kStartTransfer */ +/* */ +/* Description: */ +/* Start data transfer to/from client instance data memory. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* PCLIENT_INST pClient_Inst */ +/* Pointer to client instance */ +/* */ +/* DWORD dwAutoRepeat */ +/* TRUE if auto-repeat buffer, FALSE if one-shot buffer */ +/* */ +/* DWORD dwHostSrcBufferAddr */ +/* Host source buffer physical address */ +/* */ +/* DWORD dwHostSrcBufferLen */ +/* Host source buffer length in bytes */ +/* */ +/* DWORD dwHostDstBufferAddr */ +/* Host destination buffer linear address */ +/* */ +/* DWORD dwHostDstBufferLen */ +/* Host destination buffer length in bytes */ +/* */ +/* DWORD dwDSPInBufferAddr */ +/* DSP input buffer absolute address */ +/* */ +/* DWORD dwDSPInBufferLen */ +/* DSP input buffer length in bytes */ +/* */ +/* DWORD dwDSPOutBufferAddr */ +/* DSP output buffer absolute address */ +/* */ +/* DWORD dwDSPOutBufferLen */ +/* DSP output buffer length in bytes */ +/* */ +/* DWORD dwDSPInConnection */ +/* KCONNECT_XXX indicating input connection */ +/* */ +/* DWORD dwDSPOutConnection */ +/* KCONNECT_XXX indicating output connection */ +/* */ +/* Return (KRETURN): */ +/* KRETURN_SUCCESS if successful, KRETURN_ERROR_XXX otherwise. */ +/* */ +/*-------------------------------------------------------------------------- */ + +KRETURN kStartTransfer + (allegro_devc * devc, PHWI phwi, + PCLIENT_INST pClient_Inst, + DWORD dwAutoRepeat, + DWORD dwHostSrcBufferAddr, + DWORD dwHostSrcBufferLen, + DWORD dwHostDstBufferAddr, + DWORD dwHostDstBufferLen, + DWORD dwDSPInBufferAddr, + DWORD dwDSPInBufferLen, + DWORD dwDSPOutBufferAddr, + DWORD dwDSPOutBufferLen, DWORD dwDSPInConnection, DWORD dwDSPOutConnection) +{ + DWORD dwClient = pClient_Inst->dwClient; + DWORD dwDspDataClientArea = pClient_Inst->dwDspDataClientArea; + +#ifdef K_DBG + _Debug_Printf_Service + ("kStartTransfer %X %X %X %X %X %X %X %X %X %X %X %X %X\n", phwi, + pClient_Inst, dwAutoRepeat, dwHostSrcBufferAddr, dwHostSrcBufferLen, + dwHostDstBufferAddr, dwHostDstBufferLen, dwDSPInBufferAddr, + dwDSPInBufferLen, dwDSPOutBufferAddr, dwDSPOutBufferLen, + dwDSPInConnection, dwDSPOutConnection); + +#endif + /* */ + /* Fail if the DSP kernel has been unloaded */ + /* */ + + if (phwi->dwFlags & HWI_FLAG_UNLOADED) + return KRETURN_ERROR_UNLOADED; + + + if ((dwDSPInConnection == KCONNECT_DMA) || + (dwDSPOutConnection == KCONNECT_DMA)) + { + /* */ + /* Do DMA synchronization */ + /* */ + /* (see discussion in kOpenInstance) */ + /* */ + + if (!kStateExists (devc, phwi, KDATA_DMA_SWITCH, TRUE)) + return KRETURN_ERROR_BUSY; + } + + /* */ + /* Make sure client and an instance exist... */ + /* */ + + if (dwClient >= NUMBER_OF_CLIENTS) + return KRETURN_ERROR_GENERIC; + + if (!phwi->asClientTable[dwClient].dwReferenceCount) + return KRETURN_ERROR_GENERIC; + + /* */ + /* Verify input connection parameters */ + /* */ + + if ((dwDSPInConnection != KCONNECT_NONE) && + (dwDSPInConnection != KCONNECT_SAME)) + { + if (!dwDSPInBufferLen) + return KRETURN_ERROR_GENERIC; + + /* DSP buffer length must be block multiple */ + + if (dwDSPInBufferLen & (DMA_BLOCK_LENGTH - 1)) + return KRETURN_ERROR_GENERIC; + + if (dwDSPInConnection == KCONNECT_DMA) + { + /* host buffer must be DWORD aligned */ + + if (dwHostSrcBufferAddr & (sizeof (DWORD) - 1)) + return KRETURN_ERROR_GENERIC; + + if (!dwHostSrcBufferLen) + return KRETURN_ERROR_GENERIC; + } + } + + /* */ + /* Verify output connection parameters */ + /* */ + + if ((dwDSPOutConnection != KCONNECT_NONE) && + (dwDSPOutConnection != KCONNECT_SAME)) + { + if (!dwDSPOutBufferLen) + return KRETURN_ERROR_GENERIC; + + /* DSP buffer length must be block multiple */ + + if (dwDSPOutBufferLen & (DMA_BLOCK_LENGTH - 1)) + return KRETURN_ERROR_GENERIC; + + if ((dwDSPOutConnection == KCONNECT_DMA) || + (dwDSPOutConnection == KCONNECT_PIO)) + { + /* host buffer must be DWORD aligned */ + + if (dwHostDstBufferAddr & (sizeof (DWORD) - 1)) + return KRETURN_ERROR_GENERIC; + + if (!dwHostDstBufferLen) + return KRETURN_ERROR_GENERIC; + } + } + + pClient_Inst->dwHostSrcBufferAddr = dwHostSrcBufferAddr; + pClient_Inst->dwHostSrcBufferLen = dwHostSrcBufferLen; + pClient_Inst->dwHostDstBufferAddr = dwHostDstBufferAddr; + pClient_Inst->dwHostDstBufferLen = dwHostDstBufferLen; + pClient_Inst->dwHostDstCurrent = dwHostDstBufferAddr; + pClient_Inst->dwDSPOutBufferAddr = dwDSPOutBufferAddr; + pClient_Inst->dwDSPOutBufferLen = dwDSPOutBufferLen; + pClient_Inst->dwDSPInConnection = dwDSPInConnection; + pClient_Inst->dwDSPOutConnection = dwDSPOutConnection; + + /* */ + /* Write parameters to client instance memory */ + /* */ + + if (dwDSPInConnection == KCONNECT_DMA) + { + /* host source */ + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + dwDspDataClientArea + CDATA_HOST_SRC_ADDRL, + LOWORD (dwHostSrcBufferAddr)); + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + dwDspDataClientArea + CDATA_HOST_SRC_ADDRH, + HIWORD (dwHostSrcBufferAddr)); + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + dwDspDataClientArea + CDATA_HOST_SRC_END_PLUS_1L, + LOWORD (dwHostSrcBufferAddr + dwHostSrcBufferLen)); + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + dwDspDataClientArea + CDATA_HOST_SRC_END_PLUS_1H, + HIWORD (dwHostSrcBufferAddr + dwHostSrcBufferLen)); + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + dwDspDataClientArea + CDATA_HOST_SRC_CURRENTL, + LOWORD (dwHostSrcBufferAddr)); + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + dwDspDataClientArea + CDATA_HOST_SRC_CURRENTH, + HIWORD (dwHostSrcBufferAddr)); + } + +/*#pragma message("----Stream loopback not supported!") */ + + else if (dwDSPOutConnection == KCONNECT_DMA) + { + /* host destination */ + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + dwDspDataClientArea + CDATA_HOST_SRC_ADDRL, + LOWORD (dwHostDstBufferAddr)); + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + dwDspDataClientArea + CDATA_HOST_SRC_ADDRH, + HIWORD (dwHostDstBufferAddr)); + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + dwDspDataClientArea + CDATA_HOST_SRC_END_PLUS_1L, + LOWORD (dwHostDstBufferAddr + dwHostDstBufferLen)); + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + dwDspDataClientArea + CDATA_HOST_SRC_END_PLUS_1H, + HIWORD (dwHostDstBufferAddr + dwHostDstBufferLen)); + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + dwDspDataClientArea + CDATA_HOST_SRC_CURRENTL, + LOWORD (dwHostDstBufferAddr)); + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + dwDspDataClientArea + CDATA_HOST_SRC_CURRENTH, + HIWORD (dwHostDstBufferAddr)); + } + + /* DSP input */ + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + dwDspDataClientArea + CDATA_IN_BUF_BEGIN, + (WORD) dwDSPInBufferAddr); + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + dwDspDataClientArea + CDATA_IN_BUF_END_PLUS_1, + (WORD) (dwDSPInBufferAddr + (dwDSPInBufferLen / 2))); + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + dwDspDataClientArea + CDATA_IN_BUF_HEAD, + (WORD) dwDSPInBufferAddr); + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + dwDspDataClientArea + CDATA_IN_BUF_TAIL, + (WORD) dwDSPInBufferAddr); + + /* DSP output */ + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + dwDspDataClientArea + CDATA_OUT_BUF_BEGIN, + (WORD) dwDSPOutBufferAddr); + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + dwDspDataClientArea + CDATA_OUT_BUF_END_PLUS_1, + (WORD) (dwDSPOutBufferAddr + (dwDSPOutBufferLen / 2))); + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + dwDspDataClientArea + CDATA_OUT_BUF_HEAD, + (WORD) dwDSPOutBufferAddr); + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + dwDspDataClientArea + CDATA_OUT_BUF_TAIL, + (WORD) dwDSPOutBufferAddr); + + /* connect the input and output */ + + if (dwDSPInConnection == KCONNECT_DMA) + { + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + dwDspDataClientArea + CDATA_DMA_CONTROL, + (WORD) (dwAutoRepeat ? + (DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + + DMAC_BLOCKF_SELECTOR) : (DMAC_PAGE3_SELECTOR + + DMAC_BLOCKF_SELECTOR))); + } + +/*#pragma message("----Stream loopback not supported!") */ + + /* */ + /* The kernel currently does not support stream loopback. */ + /* Loopback means data is tranfered via DMA from the host to the */ + /* DSP, then the data is transfered via DMA from the DSP back to */ + /* the host. While the data is in DSP memory it is filtered in */ + /* some way. Thus the DSP acts as a hardware accelerator by */ + /* off-loading filter processing from the host processor. */ + /* */ + + else if (dwDSPOutConnection == KCONNECT_DMA) + { + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + dwDspDataClientArea + CDATA_DMA_CONTROL, + (WORD) (dwAutoRepeat ? + (DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT + + DMAC_PAGE3_SELECTOR + + DMAC_BLOCKF_SELECTOR) : (DMACONTROL_DIRECTION + + DMAC_PAGE3_SELECTOR + + DMAC_BLOCKF_SELECTOR))); + } + + if (!kConnectInputOutput (devc, phwi, + dwDSPInConnection, + dwDSPOutConnection, dwDspDataClientArea)) + return KRETURN_ERROR_GENERIC; + +#ifdef K_DBG + _Debug_Printf_Service ("kStartTransfer OK\n"); +#endif + return KRETURN_SUCCESS; + +} /* kStartTransfer() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* KRETURN kStopTransfer */ +/* */ +/* Description: */ +/* Stop data transfer to/from client instance data memory. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* PCLIENT_INST pClient_Inst */ +/* Pointer to client instance */ +/* */ +/* Return (KRETURN): */ +/* KRETURN_SUCCESS if successful, KRETURN_ERROR_XXX otherwise. */ +/* */ +/*-------------------------------------------------------------------------- */ + +KRETURN +kStopTransfer (allegro_devc * devc, PHWI phwi, PCLIENT_INST pClient_Inst) +{ + DWORD dwClient = pClient_Inst->dwClient; + +#ifdef K_DBG + _Debug_Printf_Service ("kStopTransfer %X %X\n", phwi, pClient_Inst); +#endif + /* */ + /* Fail if the DSP kernel has been unloaded */ + /* */ + + if (phwi->dwFlags & HWI_FLAG_UNLOADED) + return KRETURN_ERROR_UNLOADED; + + /* */ + /* Make sure client and an instance exist... */ + /* */ + + if (dwClient >= NUMBER_OF_CLIENTS) + return KRETURN_ERROR_GENERIC; + + if (!phwi->asClientTable[dwClient].dwReferenceCount) + return KRETURN_ERROR_GENERIC; + + /* */ + /* disconnect the input and output */ + /* */ + + if (!kDisconnectInputOutput (devc, phwi, + pClient_Inst->dwDSPInConnection, + pClient_Inst->dwDSPOutConnection, + pClient_Inst->dwDspDataClientArea)) + return KRETURN_ERROR_GENERIC; + +#ifdef K_DBG + _Debug_Printf_Service ("kStopTransfer OK\n"); +#endif + return KRETURN_SUCCESS; + +} /* kStopTransfer() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* KRETURN kAlterTransfer */ +/* */ +/* Description: */ +/* Alter a client's DMA transfer. */ +/* */ +/* When altering a client's current stream position, a position */ +/* equal to 0 indicates the first byte in the buffer. A position */ +/* equal to dwHostXXXBufferLen-1 indicates the last byte in the */ +/* buffer. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* PCLIENT_INST pClient_Inst */ +/* Pointer to client instance */ +/* */ +/* DWORD dwFlags */ +/* KALTER_XXX flags indicating alterations to perform */ +/* */ +/* DWORD dwAutoRepeat */ +/* TRUE if auto-repeat buffer, FALSE if one-shot buffer */ +/* */ +/* DWORD dwPosition */ +/* The byte position to set */ +/* */ +/* Return (KRETURN): */ +/* KRETURN_SUCCESS if successful, KRETURN_ERROR_XXX otherwise. */ +/* */ +/*-------------------------------------------------------------------------- */ + +KRETURN kAlterTransfer + (allegro_devc * devc, PHWI phwi, + PCLIENT_INST pClient_Inst, + DWORD dwFlags, DWORD dwAutoRepeat, DWORD dwPosition) +{ + DWORD dwClient = pClient_Inst->dwClient; + WORD wDmaControl; + +#ifdef K_DBG + _Debug_Printf_Service ("kAlterTransfer %X %X %X %X %X\n", phwi, + pClient_Inst, dwFlags, dwAutoRepeat, dwPosition); +#endif + /* */ + /* Fail if the DSP kernel has been unloaded */ + /* */ + + if (phwi->dwFlags & HWI_FLAG_UNLOADED) + return KRETURN_ERROR_UNLOADED; + + /* */ + /* Make sure client and an instance exist... */ + /* */ + + if (dwClient >= NUMBER_OF_CLIENTS) + return KRETURN_ERROR_GENERIC; + + if (!phwi->asClientTable[dwClient].dwReferenceCount) + return KRETURN_ERROR_GENERIC; + + /* */ + /* Make sure DSP kernel is ready to be halted */ + /* */ + + if (!kStateExists (devc, phwi, KDATA_HALT_ACKNOWLEDGE, FALSE)) + return KRETURN_ERROR_BUSY; + + /* */ + /* halt the DSP kernel and wait for an acknowledgement */ + /* */ + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_HALT_SYNCH_DMA, TRUE); + + if (!kStateExists (devc, phwi, KDATA_HALT_ACKNOWLEDGE, TRUE)) + { + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_HALT_SYNCH_DMA, FALSE); + + return KRETURN_ERROR_BUSY; + } + + /* */ + /* DSP kernel has halted, do DMA alterations */ + /* */ + /* Note: We halt the DSP in order to synchronize the alterations */ + /* with the DMA state machine */ + /* */ + + if (dwFlags & KALTER_AUTOREPEAT) + { + wDmaControl = kDspReadWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + pClient_Inst->dwDspDataClientArea + + CDATA_DMA_CONTROL); + + wDmaControl &= ~(DMACONTROL_STOPPED | DMACONTROL_AUTOREPEAT); + + if (dwAutoRepeat) + wDmaControl |= DMACONTROL_AUTOREPEAT; + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + pClient_Inst->dwDspDataClientArea + CDATA_DMA_CONTROL, + wDmaControl); + } + + if (dwFlags & KALTER_POSITION) + { + /* */ + /* Position alterations are only permitted on playback streams... */ + /* */ + + if (pClient_Inst->dwDSPInConnection == KCONNECT_DMA) + { + dwPosition += pClient_Inst->dwHostSrcBufferAddr; + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + pClient_Inst->dwDspDataClientArea + + CDATA_HOST_SRC_CURRENTL, LOWORD (dwPosition)); + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + pClient_Inst->dwDspDataClientArea + + CDATA_HOST_SRC_CURRENTH, HIWORD (dwPosition)); + } + } + + /* */ + /* all done, reset halt request flag to resume DSP kernel execution */ + /* */ + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_HALT_SYNCH_DMA, FALSE); + + return KRETURN_SUCCESS; + +} /* kAlterTransfer() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* KRETURN kSwitchPINConnection */ +/* */ +/* Description: */ +/* Switch data transfer PIN connection to/from client instance data memory. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* PCLIENT_INST pClient_Inst */ +/* Pointer to client instance */ +/* */ +/* DWORD dwDSPInConnection */ +/* KCONNECT_XXX indicating input connection */ +/* */ +/* DWORD dwDSPOutConnection */ +/* KCONNECT_XXX indicating output connection */ +/* */ +/* Return (KRETURN): */ +/* KRETURN_SUCCESS if successful, KRETURN_ERROR_XXX otherwise. */ +/* */ +/*-------------------------------------------------------------------------- */ + +KRETURN kSwitchPINConnection + (allegro_devc * devc, PHWI phwi, + PCLIENT_INST pClient_Inst, + DWORD dwDSPInConnection, DWORD dwDSPOutConnection) +{ + DWORD dwClient = pClient_Inst->dwClient; + DWORD dwDspDataClientArea = pClient_Inst->dwDspDataClientArea; +#ifdef K_DBG + _Debug_Printf_Service ("kSwitchPINConnection %X %X %X %X \n", + phwi, + pClient_Inst, dwDSPInConnection, dwDSPOutConnection); + +#endif + + /* */ + /* Fail if the DSP kernel has been unloaded */ + /* */ + + if (phwi->dwFlags & HWI_FLAG_UNLOADED) + return KRETURN_ERROR_UNLOADED; + + /* */ + /* Make sure connections are valid... */ + /* */ + + if (dwDSPInConnection >= NUMBER_OF_CONNECTIONS) + return KRETURN_ERROR_GENERIC; + + if (dwDSPOutConnection >= NUMBER_OF_CONNECTIONS) + return KRETURN_ERROR_GENERIC; + + if ((dwDSPInConnection == KCONNECT_DMA) || + (dwDSPOutConnection == KCONNECT_DMA)) + { + /* */ + /* Do DMA synchronization */ + /* */ + /* DMA engine is not switchable at this moment!!! */ + /* */ + + if (!kStateExists (devc, phwi, KDATA_DMA_SWITCH, TRUE)) + return KRETURN_ERROR_BUSY; + } + + /* */ + /* Make sure client and an instance exist... */ + /* */ + + if (dwClient >= NUMBER_OF_CLIENTS) + return KRETURN_ERROR_GENERIC; + + if (!phwi->asClientTable[dwClient].dwReferenceCount) + return KRETURN_ERROR_GENERIC; + + + /* */ + /* disconnect the input and output first */ + /* */ + + if (!kDisconnectInputOutput (devc, phwi, + pClient_Inst->dwDSPInConnection, + pClient_Inst->dwDSPOutConnection, + pClient_Inst->dwDspDataClientArea)) + return KRETURN_ERROR_GENERIC; + + + /* */ + /* update PIN connection */ + /* */ + + if (dwDSPInConnection != KCONNECT_SAME) + pClient_Inst->dwDSPInConnection = dwDSPInConnection; + + if (dwDSPOutConnection != KCONNECT_SAME) + pClient_Inst->dwDSPOutConnection = dwDSPOutConnection; + + + /* */ + /* Finally, connect updated PIN */ + /* */ + + if (!kConnectInputOutput (devc, phwi, + pClient_Inst->dwDSPInConnection, + pClient_Inst->dwDSPOutConnection, + dwDspDataClientArea)) + return KRETURN_ERROR_GENERIC; + + +#ifdef K_DBG + _Debug_Printf_Service ("kSwitchPINConnection OK\n"); +#endif + return KRETURN_SUCCESS; + +} /* kSwitchPINConnection() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* KRETURN kQueryActivity */ +/* */ +/* Description: */ +/* Indicate what clients and/or connections are active */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* PDWORD pdwClientMasks */ +/* Pointer to DWORD that will contain MASK_CLIENT_XXX masks */ +/* */ +/* PDWORD pdwConnectMasks */ +/* Pointer to DWORD that will contain MASK_KCONNECT_XXX masks */ +/* */ +/* Return (KRETURN): */ +/* KRETURN_SUCCESS if successful, KRETURN_ERROR_XXX otherwise. */ +/* */ +/*-------------------------------------------------------------------------- */ + +KRETURN kQueryActivity + (allegro_devc * devc, PHWI phwi, PDWORD pdwClientMasks, + PDWORD pdwConnectMasks) +{ + DWORD dwClient; + +#ifdef K_DBG + _Debug_Printf_Service ("kQueryActivity %X %X %X\n", phwi, + pdwClientMasks, pdwConnectMasks); + + +#endif + /* */ + /* Fail if the DSP kernel has been unloaded */ + /* */ + + if (phwi->dwFlags & HWI_FLAG_UNLOADED) + return KRETURN_ERROR_UNLOADED; + + /* */ + /* Check if any client instance is defined */ + /* */ + + *pdwClientMasks = 0; + + for (dwClient = 0; dwClient < NUMBER_OF_CLIENTS; ++dwClient) + { + if (phwi->asClientTable[dwClient].dwReferenceCount) + { + *pdwClientMasks |= (1 << dwClient); + } + } + + /* */ + /* Check if any connections are defined */ + /* */ + + *pdwConnectMasks = 0; + + if (phwi->awVirtualDMAList[0]) + *pdwConnectMasks |= MASK_KCONNECT_DMA; + + if (phwi->awVirtualADC1List[0]) + *pdwConnectMasks |= MASK_KCONNECT_ADC1; + + if (phwi->awVirtualADC2List[0]) + *pdwConnectMasks |= MASK_KCONNECT_ADC2; + + if (phwi->awVirtualI2SList[0]) + *pdwConnectMasks |= MASK_KCONNECT_I2S; + + if (phwi->awVirtualCHIList[0]) + *pdwConnectMasks |= MASK_KCONNECT_CHI; + + if (kDspReadWord + (devc, phwi->dwBaseIO, MEMTYPE_INTERNAL_DATA, KDATA_SPDIF_XFER)) + *pdwConnectMasks |= MASK_KCONNECT_SPDIF; + + if (phwi->awVirtualMIXERList[0]) + *pdwConnectMasks |= MASK_KCONNECT_MIXER; + +#if 0 +#if (NUMBER_OF_CONNECTIONS != 0x10) +#error Assumption about number of connections failed. +#endif +#endif + + return KRETURN_SUCCESS; + +} /* kQueryActivity() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* KRETURN kSetTimer */ +/* */ +/* Description: */ +/* Set the DSP to Host interrupt time interval */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* DWORD dwTimeInterval */ +/* Number of APU interrupts per DSP to Host interrupt */ +/* */ +/* Return (KRETURN): */ +/* KRETURN_SUCCESS if successful, KRETURN_ERROR_XXX otherwise. */ +/* */ +/*-------------------------------------------------------------------------- */ + +KRETURN +kSetTimer (allegro_devc * devc, PHWI phwi, DWORD dwTimeInterval) +{ +#ifdef K_DBG + _Debug_Printf_Service ("kSetTimer %X %X\n", phwi, dwTimeInterval); +#endif + /* */ + /* Fail if the DSP kernel has been unloaded */ + /* */ + + if (phwi->dwFlags & HWI_FLAG_UNLOADED) + return KRETURN_ERROR_UNLOADED; + + /* */ + /* Check time interval size */ + /* */ + + if (HIWORD (dwTimeInterval)) + return KRETURN_ERROR_GENERIC; + + /* */ + /* Write timer values */ + /* */ + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_TIMER_COUNT_RELOAD, (WORD) dwTimeInterval); + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_TIMER_COUNT_CURRENT, (WORD) dwTimeInterval); + + return KRETURN_SUCCESS; + +} /* kSetTimer() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* KRETURN kOpenPassThru */ +/* */ +/* Description: */ +/* Open a pass through. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* PPASSTHRU *ppPassThru */ +/* Pointer to PPASSTHRU that will contain the pass through pointer */ +/* */ +/* DWORD dwDSPInConnection */ +/* KCONNECT_XXX indicating input connection */ +/* */ +/* DWORD dwDSPOutConnection */ +/* KCONNECT_XXX indicating output connection */ +/* */ +/* Return (KRETURN): */ +/* KRETURN_SUCCESS if successful, KRETURN_ERROR_XXX otherwise. */ +/* */ +/*-------------------------------------------------------------------------- */ + +KRETURN kOpenPassThru + (allegro_devc * devc, PHWI phwi, + PPASSTHRU * ppPassThru, DWORD dwDSPInConnection, DWORD dwDSPOutConnection) +{ + PPASSTHRU pPassThru = NULL; + +#ifdef K_DBG + _Debug_Printf_Service ("kOpenPassThru %X %X <-> %X\n", phwi, + dwDSPInConnection, dwDSPOutConnection); +#endif + /* */ + /* Fail if the DSP kernel has been unloaded */ + /* */ + + if (phwi->dwFlags & HWI_FLAG_UNLOADED) + return KRETURN_ERROR_UNLOADED; + + /* */ + /* Make sure connections are valid... */ + /* */ + + if ((dwDSPInConnection == KCONNECT_NONE) || + (dwDSPInConnection == KCONNECT_SAME) || + (dwDSPInConnection >= NUMBER_OF_CONNECTIONS)) + return KRETURN_ERROR_GENERIC; + + if ((dwDSPOutConnection == KCONNECT_NONE) || + (dwDSPOutConnection == KCONNECT_SAME) || + (dwDSPOutConnection >= NUMBER_OF_CONNECTIONS)) + return KRETURN_ERROR_GENERIC; + + /* */ + /* Do open/close synchronization */ + /* */ + + if (!kStateExists (devc, phwi, KDATA_TASK_SWITCH, TRUE)) + return KRETURN_ERROR_BUSY; + + /* */ + /* Allocate host memory */ + /* */ + + if (!(pPassThru = (PPASSTHRU) + _HeapAllocate (sizeof (PASSTHRU), HEAPZEROINIT))) + return KRETURN_ERROR_GENERIC; + + pPassThru->dwDSPInConnection = dwDSPInConnection; + pPassThru->dwDSPOutConnection = dwDSPOutConnection; + + /* */ + /* Handle directly mixed (i.e. non-buffered) connections */ + /* */ + + if (dwDSPOutConnection == KCONNECT_SPDIF) + { + kConnectDirectMixer (devc, phwi, dwDSPInConnection, dwDSPOutConnection, + TRUE); + } + else + { + if (dwDSPOutConnection == KCONNECT_MIXER) + { + switch (dwDSPInConnection) + { + case KCONNECT_ADC1: + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_ADC1_MIXER_REQUEST, TRUE); + break; + case KCONNECT_ADC2: + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_ADC2_MIXER_REQUEST, TRUE); + break; + + case KCONNECT_CD: + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_CD_MIXER_REQUEST, TRUE); + break; + + case KCONNECT_MIC: + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_MIC_MIXER_REQUEST, TRUE); + break; + + default: + goto kOpen_Error; + } /* endswitch */ + } /* endif */ + + } + + /* */ + /* Everything worked */ + /* */ + + *ppPassThru = pPassThru; + +#ifdef K_DBG + _Debug_Printf_Service ("kOpenPassThru OK %X\n", pPassThru); +#endif + return KRETURN_SUCCESS; + +kOpen_Error: + + /* */ + /* Failure, undo all that was done... */ + /* */ + + if (pPassThru) + { + _HeapFree (pPassThru, 0); + } + +#ifdef K_DBG + _Debug_Printf_Service ("kOpenPassThru Failed\n"); +#endif + return KRETURN_ERROR_GENERIC; + +} /* kOpenPassThru() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* KRETURN kClosePassThru */ +/* */ +/* Description: */ +/* Close a pass through. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* PPASSTHRU pPassThru */ +/* Pointer to pass through */ +/* */ +/* Return (KRETURN): */ +/* KRETURN_SUCCESS if successful, KRETURN_ERROR_XXX otherwise. */ +/* */ +/*-------------------------------------------------------------------------- */ + +KRETURN +kClosePassThru (allegro_devc * devc, PHWI phwi, PPASSTHRU pPassThru) +{ +#ifdef K_DBG + _Debug_Printf_Service ("kClosePassThru %X %X\n", phwi, pPassThru); +#endif + /* */ + /* Fail if the DSP kernel has been unloaded */ + /* */ + + if (phwi->dwFlags & HWI_FLAG_UNLOADED) + return KRETURN_ERROR_UNLOADED; + + /* */ + /* Deallocate memory */ + /* */ + + if (!pPassThru) + return KRETURN_ERROR_GENERIC; + + /* */ + /* Handle directly mixed (i.e. non-buffered) connections */ + /* */ + + if (pPassThru->dwDSPOutConnection == KCONNECT_SPDIF) + { + kConnectDirectMixer (devc, phwi, + pPassThru->dwDSPInConnection, + pPassThru->dwDSPOutConnection, FALSE); + } + else + { + if (pPassThru->dwDSPOutConnection == KCONNECT_MIXER) + { + switch (pPassThru->dwDSPInConnection) + { + case KCONNECT_ADC1: + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_ADC1_MIXER_REQUEST, FALSE); + break; + + case KCONNECT_ADC2: + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_ADC2_MIXER_REQUEST, FALSE); + break; + + case KCONNECT_CD: + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_CD_MIXER_REQUEST, FALSE); + break; + + case KCONNECT_MIC: + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_MIC_MIXER_REQUEST, FALSE); + break; + + } /* endswitch */ + + } /* endif */ + + } + + _HeapFree (pPassThru, 0); + + /* */ + /* Do open/close synchronization */ + /* */ + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_TASK_SWITCH, FALSE); + + return KRETURN_SUCCESS; + +} /* kClosePassThru() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* KRETURN kSetVolume */ +/* */ +/* Description: */ +/* Set a client's current stream left/right Volume. */ +/* Maximum is 0x7FFF and Minimum is 0x0000. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* PCLIENT_INST pClient_Inst */ +/* Pointer to client instance */ +/* */ +/* WORD wLeftVolume */ +/* 16 bit constant for left channel volume */ +/* */ +/* WORD wRightVolume */ +/* 16 bit constant for right channel volume */ +/* */ +/* WORD wBoosterMode */ +/* TRUE activates a broader range of volume setting. */ +/* In this mode, 7FFF represents 18dB gain */ +/* 1000 represents 0dB gain */ +/* 0 represents -Inf gain(mute) */ +/* FALSE supports only an attenuation mode. */ +/* In this mode, 7FFF represents 0dB gain */ +/* 0 represents -Inf gain(mute) */ +/* */ +/* Return (KRETURN): */ +/* KRETURN_SUCCESS if successful, KRETURN_ERROR_XXX otherwise. */ +/* */ +/*-------------------------------------------------------------------------- */ + +KRETURN kSetVolume + (allegro_devc * devc, PHWI phwi, + PCLIENT_INST pClient_Inst, + WORD wLeftVolume, WORD wRightVolume, WORD wBoosterMode) +{ + DWORD dwClient = pClient_Inst->dwClient; + +#if 0 + WORD wCurLVol, wCurRVol, wLTemp, wRTemp; +#endif + +#ifdef K_DBG + _Debug_Printf_Service ("kSetVolume %X %X %X %X\n", + phwi, pClient_Inst, wLeftVolume, wRightVolume); +#endif + /* */ + /* Fail if the DSP kernel has been unloaded */ + /* */ + + if (phwi->dwFlags & HWI_FLAG_UNLOADED) + return KRETURN_ERROR_UNLOADED; + + /* */ + /* Make sure client and an instance exist... */ + /* */ + + if (dwClient >= NUMBER_OF_CLIENTS) + return KRETURN_ERROR_GENERIC; + + if (!phwi->asClientTable[dwClient].dwReferenceCount) + return KRETURN_ERROR_GENERIC; + +#if 0 /* micro step the volume */ + wCurLVol = kDspReadWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + pClient_Inst-> + dwDspDataClientArea + CDATA_LEFT_VOLUME); + + wCurRVol = kDspReadWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + pClient_Inst-> + dwDspDataClientArea + CDATA_RIGHT_VOLUME); + + /* need to do micro steps to avoid zipper noise */ + /* max 7 steps */ + wLTemp = wLeftVolume; + wRTemp = wRightVolume; + + + wCurLVol &= 0xF000; + wCurLVol |= (wLeftVolume & 0x0FFF); + + if (wCurLVol < wLeftVolume) + { + wLeftVolume = wCurLVol; + wCurLVol = wLTemp; + } /* endif */ + + do + { + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + pClient_Inst-> + dwDspDataClientArea + CDATA_LEFT_VOLUME, wCurLVol); + + kDelayNMicroseconds (10); + wCurLVol -= 0x800; + } + while (wCurLVol > wLeftVolume); + + wCurRVol &= 0xF000; + wCurRVol |= (wRightVolume & 0x0FFF); + + if (wCurRVol < wRightVolume) + { + wRightVolume = wCurRVol; + wCurRVol = wRTemp; + } /* endif */ + + do + { + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + pClient_Inst-> + dwDspDataClientArea + CDATA_RIGHT_VOLUME, wCurRVol); + + kDelayNMicroseconds (10); + wCurRVol -= 0x800; + } + while (wCurRVol > wRightVolume); + + wLeftVolume = wLTemp; + wRightVolume = wRTemp; +#endif + /* */ + /* write left/right word of current stream volume */ + /* */ + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + pClient_Inst-> + dwDspDataClientArea + CDATA_LEFT_VOLUME, -wLeftVolume); + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + pClient_Inst-> + dwDspDataClientArea + CDATA_RIGHT_VOLUME, -wRightVolume); + + /* */ + /* tell the client whether this is broader range */ + /* of volume setting or not */ + /* */ + + if (wBoosterMode) + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + pClient_Inst-> + dwDspDataClientArea + CDATA_HEADER_LEN + 23, TRUE); + else + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + pClient_Inst-> + dwDspDataClientArea + CDATA_HEADER_LEN + 23, FALSE); + + + return KRETURN_SUCCESS; + +} /* kSetVolume() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* KRETURN kSetRearVolume */ +/* */ +/* Description: */ +/* Set a client's current stream rear left/rear right Volume. */ +/* Maximum is 0x7FFF and Minimum is 0x0000. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* PCLIENT_INST pClient_Inst */ +/* Pointer to client instance */ +/* */ +/* WORD wLeftRearVolume */ +/* 16 bit constant for rear left channel volume */ +/* */ +/* WORD wRightRearVolume */ +/* 16 bit constant for rear right channel volume */ +/* */ +/* */ +/* Return (KRETURN): */ +/* KRETURN_SUCCESS if successful, KRETURN_ERROR_XXX otherwise. */ +/* */ +/*-------------------------------------------------------------------------- */ + +KRETURN kSetRearVolume + (allegro_devc * devc, PHWI phwi, + PCLIENT_INST pClient_Inst, WORD wLeftRearVolume, WORD wRightRearVolume) +{ + DWORD dwClient = pClient_Inst->dwClient; + + +#ifdef K_DBG + _Debug_Printf_Service ("kSetVolume %X %X %X %X\n", + phwi, + pClient_Inst, wLeftRearVolume, wRightRearVolume); +#endif + /* */ + /* Fail if the DSP kernel has been unloaded */ + /* */ + + if (phwi->dwFlags & HWI_FLAG_UNLOADED) + return KRETURN_ERROR_UNLOADED; + + /* */ + /* Make sure client and an instance exist... */ + /* */ + + if (dwClient >= NUMBER_OF_CLIENTS) + return KRETURN_ERROR_GENERIC; + + if (!phwi->asClientTable[dwClient].dwReferenceCount) + return KRETURN_ERROR_GENERIC; + + /* */ + /* write rear left/rear right word of current stream volume */ + /* */ + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + pClient_Inst-> + dwDspDataClientArea + CDATA_LEFT_SUR_VOL, wLeftRearVolume); + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + pClient_Inst-> + dwDspDataClientArea + CDATA_RIGHT_SUR_VOL, wRightRearVolume); + + return KRETURN_SUCCESS; + +} /* kSetRearVolume() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* KRETURN kSetPassThruVolume */ +/* */ +/* Description: */ +/* Set a passthrough instance volume. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* PPASSTHRU *ppPassThru */ +/* Pointer to PPASSTHRU that will contain the pass through pointer */ +/* */ +/* WORD wLeftVolume */ +/* 16 bit constant for left channel volume */ +/* */ +/* WORD wRightVolume */ +/* 16 bit constant for right channel volume */ +/* */ +/* Return (KRETURN): */ +/* KRETURN_SUCCESS if successful, KRETURN_ERROR_XXX otherwise. */ +/* */ +/*-------------------------------------------------------------------------- */ +KRETURN kSetPassThruVolume + (allegro_devc * devc, PHWI phwi, PPASSTHRU pPassThru, WORD wLeftVolume, + WORD wRightVolume) +{ + /* */ + /* Fail if the DSP kernel has been unloaded */ + /* */ + + if (phwi->dwFlags & HWI_FLAG_UNLOADED) + return KRETURN_ERROR_UNLOADED; + + /* pPassThru -> wLeftVolume = wLeftVolume ; */ + /* pPassThru -> wRightVolume = wRightVolume ; */ + + switch (pPassThru->dwDSPInConnection) + { + case KCONNECT_ADC1: + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_ADC1_LEFT_VOLUME, wLeftVolume); + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_ADC1_RIGHT_VOLUME, wRightVolume); + + break; + + case KCONNECT_ADC2: + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_ADC2_LEFT_VOLUME, wLeftVolume); + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_ADC2_RIGHT_VOLUME, wRightVolume); + + break; + + case KCONNECT_CD: + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_CD_LEFT_VOLUME, wLeftVolume); + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_CD_RIGHT_VOLUME, wRightVolume); + break; + + case KCONNECT_MIC: + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_MIC_VOLUME, wLeftVolume); + + break; + + default: + return KRETURN_ERROR_GENERIC; + } /* endswitch */ + + + return KRETURN_SUCCESS; + +} /* kSetPassThruVolume */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* KRETURN kSetPassThruRearVolume */ +/* */ +/* Description: */ +/* Set a passthrough instance's rear volume. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* PPASSTHRU *ppPassThru */ +/* Pointer to PPASSTHRU that will contain the pass through pointer */ +/* */ +/* WORD wLeftRearVolume */ +/* 16 bit constant for left rear channel volume */ +/* */ +/* WORD wRightRearVolume */ +/* 16 bit constant for right rear channel volume */ +/* */ +/* Return (KRETURN): */ +/* KRETURN_SUCCESS if successful, KRETURN_ERROR_XXX otherwise. */ +/* */ +/*-------------------------------------------------------------------------- */ +KRETURN kSetPassThruRearVolume + (allegro_devc * devc, PHWI phwi, + PPASSTHRU pPassThru, WORD wLeftRearVolume, WORD wRightRearVolume) +{ + /* */ + /* Fail if the DSP kernel has been unloaded */ + /* */ + if (phwi->dwFlags & HWI_FLAG_UNLOADED) + return KRETURN_ERROR_UNLOADED; + + switch (pPassThru->dwDSPInConnection) + { + case KCONNECT_ADC1: + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_ADC1_LEFT_SUR_VOL, wLeftRearVolume); + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_ADC1_RIGHT_SUR_VOL, wRightRearVolume); + + break; + + + case KCONNECT_ADC2: + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_ADC2_LEFT_SUR_VOL, wLeftRearVolume); + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_ADC2_RIGHT_SUR_VOL, wRightRearVolume); + + break; + + case KCONNECT_CD: + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_CD_LEFT_SUR_VOL, wLeftRearVolume); + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_CD_RIGHT_SUR_VOL, wRightRearVolume); + break; + + case KCONNECT_MIC: + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_MIC_SUR_VOL, wLeftRearVolume); + + break; + + default: + return KRETURN_ERROR_GENERIC; + } /* endswitch */ + + + return KRETURN_SUCCESS; + +} /* kSetPassThruRearVolume */ + + +/*-------------------------------------------------------------------------- */ +/* */ +/* KRETURN kSetMasterVolume */ +/* */ +/* Description: */ +/* Set master volume. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* WORD wLeftVolume */ +/* 16 bit constant for left channel volume */ +/* */ +/* WORD wRightVolume */ +/* 16 bit constant for right channel volume */ +/* */ +/* Return (KRETURN): */ +/* KRETURN_SUCCESS if successful, KRETURN_ERROR_XXX otherwise. */ +/* */ +/*-------------------------------------------------------------------------- */ +KRETURN +kSetMasterVolume (allegro_devc * devc, PHWI phwi, WORD wLeftVolume, + WORD wRightVolume) +{ + /* */ + /* Fail if the DSP kernel has been unloaded */ + /* */ + if (phwi->dwFlags & HWI_FLAG_UNLOADED) + return KRETURN_ERROR_UNLOADED; + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_DAC_LEFT_VOLUME, wLeftVolume); + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_DAC_RIGHT_VOLUME, wRightVolume); + + return KRETURN_SUCCESS; + +} /* kSetMasterVolume */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* KRETURN kSetFrequency */ +/* */ +/* Description: */ +/* Set a client's current stream sampling frequency. */ +/* 48khz is corresponding to 0x7FFF */ +/* 0 hz is corresponding to 0x0000 */ +/* The other frequencies are linear mapping between those two */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* PCLIENT_INST pClient_Inst */ +/* Pointer to client instance */ +/* */ +/* WORD wFrequency */ +/* 16 bit constant for sampling frequency */ +/* */ +/* */ +/* Return (KRETURN): */ +/* KRETURN_SUCCESS if successful, KRETURN_ERROR_XXX otherwise. */ +/* */ +/*-------------------------------------------------------------------------- */ + +KRETURN +kSetFrequency (allegro_devc * devc, PHWI phwi, PCLIENT_INST pClient_Inst, + WORD wFrequency) +{ + DWORD dwClient = pClient_Inst->dwClient; +#ifdef K_DBG + _Debug_Printf_Service ("kSetVolume %X %X %X\n", phwi, + pClient_Inst, wFrequency); +#endif + + + /* */ + /* Fail if the DSP kernel has been unloaded */ + /* */ + + if (phwi->dwFlags & HWI_FLAG_UNLOADED) + return KRETURN_ERROR_UNLOADED; + + /* */ + /* Make sure client and an instance exist... */ + /* */ + + if (dwClient >= NUMBER_OF_CLIENTS) + return KRETURN_ERROR_GENERIC; + + if (!phwi->asClientTable[dwClient].dwReferenceCount) + return KRETURN_ERROR_GENERIC; + + /* */ + /* write left/right word of current stream sampling frequency */ + /* */ + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + pClient_Inst-> + dwDspDataClientArea + CDATA_FREQUENCY, wFrequency); + + return KRETURN_SUCCESS; + +} /* kSetFrequency */ + + +/**************************************************************************** */ +/* The following is unique to M2/M2E only */ +/**************************************************************************** */ +#ifdef PIOREC +/*-------------------------------------------------------------------------- */ +/* */ +/* DWORD kCopyLinearToCircular */ +/* */ +/* Description: */ +/* Copy data from a linear DSP output buffer to a potentially */ +/* circular host destination buffer. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* DWORD dwMemAddr */ +/* Memory address to read from. */ +/* */ +/* DWORD dwMemLen */ +/* Number of WORDs to read from specified address. */ +/* */ +/* DWORD dwHostAddr */ +/* Host memory address to write to. */ +/* */ +/* DWORD dwHostBase */ +/* Base address of host buffer. */ +/* */ +/* DWORD dwHostLen */ +/* Length in bytes of host buffer. */ +/* */ +/* Return (DWORD): */ +/* */ +/*-------------------------------------------------------------------------- */ + +DWORD kCopyLinearToCircular + (allegro_devc * devc, PHWI phwi, + DWORD dwMemAddr, + DWORD dwMemLen, DWORD dwHostAddr, DWORD dwHostBase, DWORD dwHostLen) +{ + DWORD dwPreWrapLen; + + /* */ + /* copy DSP buffer data to host buffer */ + /* */ + + if ((dwHostAddr + (dwMemLen * sizeof (WORD))) <= (dwHostBase + dwHostLen)) + { + /* */ + /* host buffer won't wrap, do straight copy */ + /* */ + + kDspReadWords (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + dwMemAddr, dwMemLen, (PWORD) dwHostAddr); + } + else + { + dwPreWrapLen = (dwHostBase + dwHostLen - dwHostAddr) / sizeof (WORD); + + /* */ + /* host buffer will wrap, do pre-wrap copy */ + /* */ + + kDspReadWords (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + dwMemAddr, dwPreWrapLen, (PWORD) dwHostAddr); + + /* */ + /* do post-wrap copy */ + /* */ + + kDspReadWords (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + dwMemAddr + dwPreWrapLen, + dwMemLen - dwPreWrapLen, (PWORD) dwHostBase); + } + + /* */ + /* update current host pointer and check for wrap */ + /* */ + + dwHostAddr += (dwMemLen * sizeof (WORD)); + + if (dwHostAddr >= (dwHostBase + dwHostLen)) + { + dwHostAddr = dwHostBase + (dwHostAddr - (dwHostBase + dwHostLen)); + } + + return dwHostAddr; + +} /* kCopyLinearToCircular() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* VOID kPIOInterruptHandler */ +/* */ +/* Description: */ +/* PIO data available interrupt handler. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* PCLIENT_INST pClient_Inst */ +/* Pointer to client instance */ +/* */ +/* Return (VOID): */ +/* */ +/*-------------------------------------------------------------------------- */ + +VOID +kPIOInterruptHandler (allegro_devc * devc, PHWI phwi, + PCLIENT_INST pClient_Inst) +{ + DWORD dwHostDstBufferAddr = pClient_Inst->dwHostDstBufferAddr; + DWORD dwHostDstBufferLen = pClient_Inst->dwHostDstBufferLen; + DWORD dwHostDstCurrent = pClient_Inst->dwHostDstCurrent; + DWORD dwDSPOutBufferAddr = pClient_Inst->dwDSPOutBufferAddr; + DWORD dwDSPOutBufferLen = pClient_Inst->dwDSPOutBufferLen; + DWORD dwOutBufHead; + DWORD dwOutBufTail; + + /* */ + /* return if PIO recording not active */ + /* */ + + if (!phwi->awVirtualPIOList[0]) + return; + + /* */ + /* read buffer state from DSP */ + /* */ + + dwOutBufHead = kDspReadWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + pClient_Inst->dwDspDataClientArea + + CDATA_OUT_BUF_HEAD); + + dwOutBufTail = kDspReadWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + pClient_Inst->dwDspDataClientArea + + CDATA_OUT_BUF_TAIL); + + /* */ + /* copy DSP buffer data to host buffer */ + /* */ + + if (dwOutBufHead > dwOutBufTail) + { + /* */ + /* DSP buffer data doesn't wrap, do straight copy */ + /* */ + + dwHostDstCurrent = + kCopyLinearToCircular (devc, phwi, + dwOutBufTail, + dwOutBufHead - dwOutBufTail, + dwHostDstCurrent, + dwHostDstBufferAddr, dwHostDstBufferLen); + } + else + { + /* */ + /* DSP buffer data wraps, do pre-wrap copy */ + /* */ + + dwHostDstCurrent = + kCopyLinearToCircular (devc, phwi, + dwOutBufTail, + dwDSPOutBufferAddr + (dwDSPOutBufferLen / 2) + - dwOutBufTail, + dwHostDstCurrent, + dwHostDstBufferAddr, dwHostDstBufferLen); + + /* */ + /* do post-wrap copy */ + /* */ + + dwHostDstCurrent = + kCopyLinearToCircular (devc, phwi, + dwDSPOutBufferAddr, + dwOutBufHead - dwDSPOutBufferAddr, + dwHostDstCurrent, + dwHostDstBufferAddr, dwHostDstBufferLen); + } + + /* */ + /* write updated buffer state to DSP */ + /* */ + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + pClient_Inst->dwDspDataClientArea + CDATA_OUT_BUF_TAIL, + (WORD) dwOutBufHead); + + pClient_Inst->dwHostDstCurrent = dwHostDstCurrent; + +} /* kPIOInterruptHandler() */ +#endif + +#ifdef HOSTI2SFREQCALC /* I2S was calculated in the host */ +#ifdef DOS_MODEL +#pragma message("----kI2SInterruptHandler omitted (causes internal compiler error)") +#else +/*-------------------------------------------------------------------------- */ +/* */ +/* VOID kI2SInterruptHandler */ +/* */ +/* Description: */ +/* I2S data flow impeded interrupt handler. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* PDWORD pdwI2SRate */ +/* Pointer to DWORD that will contain the I2S sample rate or */ +/* -1 if the sample rate should not be changed */ +/* */ +/* Return (VOID): */ +/* */ +/*-------------------------------------------------------------------------- */ + +VOID +kI2SInterruptHandler (allegro_devc * devc, PHWI phwi, PDWORD pdwI2SRate) +{ + WORD wI2SSampleCount; + WORD wI2STimerCount; + WORD wI2SSampleRate; + + /* */ + /* Get current sample count and timer count */ + /* */ + + wI2SSampleCount = kDspReadWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + KDATA_I2S_SAMPLE_COUNT); + + wI2STimerCount = kInW (devc, phwi->dwBaseIO + DSP_PORT_TIMER_COUNT); + + /* */ + /* I2S sample rate determination is a two pass operation. */ + /* On the first pass we zero the activity flag and return -1. */ + /* On the second pass we check if the activity flag is still */ + /* zero. If so, we know the I2S data stream has stopped */ + /* and we return 0 for the sample rate. Otherwise, we use */ + /* the sample count data and do our best to determine the */ + /* sample rate. */ + /* */ + + if (phwi->dwFlags & HWI_FLAG_I2S_SECONDPASS) + { + if (!kDspReadWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_I2S_ACTIVE)) + { + /* */ + /* the I2S stream has stopped */ + /* */ + + *pdwI2SRate = 0; + } + else + { + /* */ + /* the I2S stream is moving */ + /* */ + + wI2SSampleCount -= phwi->wI2SSampleCount; + wI2STimerCount -= phwi->wI2STimerCount; + + /* */ + /* determine sample rate */ + /* */ + /* The timer rate is 48,000 ticks/second, so */ + /* */ + /* samples N samples 48,000 ticks 1 */ + /* ------- = --------- X ------------ X ------- */ + /* second 1 1 second M ticks */ + /* */ + + wI2SSampleRate = (wI2SSampleCount * 48000) / wI2STimerCount; + + if (wI2SSampleRate > (48000 + 44100) / 2) + *pdwI2SRate = 48000; + else if (wI2SSampleRate > (44100 + 32000) / 2) + *pdwI2SRate = 44100; + else if (wI2SSampleRate > (32000 + 22050) / 2) + *pdwI2SRate = 32000; + else + *pdwI2SRate = 22050; + } + + phwi->dwFlags &= ~HWI_FLAG_I2S_SECONDPASS; + } + else + { + /* */ + /* zero the activity flag and advance to the next state */ + /* */ + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, KDATA_I2S_ACTIVE, 0); + + phwi->wI2SSampleCount = wI2SSampleCount; + phwi->wI2STimerCount = wI2STimerCount; + + *pdwI2SRate = (DWORD) - 1; + + phwi->dwFlags |= HWI_FLAG_I2S_SECONDPASS; + } + +} /* kI2SInterruptHandler() */ +#endif +#endif + +#ifdef APUBLOCKCOUNT +/*-------------------------------------------------------------------------- */ +/* */ +/* KRETURN kResetApuBlockCount */ +/* */ +/* Description: */ +/* Reset a client's APU block count field. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* PCLIENT_INST pClient_Inst */ +/* Pointer to client instance */ +/* */ +/* Return (KRETURN): */ +/* KRETURN_SUCCESS if successful, KRETURN_ERROR_XXX otherwise. */ +/* */ +/*-------------------------------------------------------------------------- */ + +KRETURN +kResetApuBlockCount (allegro_devc * devc, PHWI phwi, + PCLIENT_INST pClient_Inst) +{ + DWORD dwClient = pClient_Inst->dwClient; + + /* */ + /* Fail if the DSP kernel has been unloaded */ + /* */ + + if (phwi->dwFlags & HWI_FLAG_UNLOADED) + return KRETURN_ERROR_UNLOADED; + + /* */ + /* Make sure client and an instance exist... */ + /* */ + + if (dwClient >= NUMBER_OF_CLIENTS) + return KRETURN_ERROR_GENERIC; + + if (!phwi->asClientTable[dwClient].dwReferenceCount) + return KRETURN_ERROR_GENERIC; + + /* */ + /* Reset the block count */ + /* */ + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + pClient_Inst-> + dwDspDataClientArea + CDATA_APU_BLOCK_COUNTL, 0); + + kDspWriteWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + pClient_Inst-> + dwDspDataClientArea + CDATA_APU_BLOCK_COUNTH, 0); + + return KRETURN_SUCCESS; + +} /* kResetApuBlockCount() */ + +/*-------------------------------------------------------------------------- */ +/* */ +/* KRETURN kGetApuBlockCount */ +/* */ +/* Description: */ +/* Return a client's current stream position in terms of the number */ +/* of APU blocks transfered. */ +/* */ +/* Parameters: */ +/* PHWI phwi */ +/* Pointer to hardware instance. */ +/* */ +/* PCLIENT_INST pClient_Inst */ +/* Pointer to client instance */ +/* */ +/* PDWORD pdwBlockCount */ +/* Pointer to DWORD that will contain the number of APU blocks */ +/* */ +/* Return (KRETURN): */ +/* KRETURN_SUCCESS if successful, KRETURN_ERROR_XXX otherwise. */ +/* */ +/*-------------------------------------------------------------------------- */ + +KRETURN kGetApuBlockCount + (allegro_devc * devc, PHWI phwi, PCLIENT_INST pClient_Inst, + PDWORD pdwBlockCount) +{ + DWORD dwClient = pClient_Inst->dwClient; + WORD wBlockCount; + WORD wRetry = 10; + WORD wBlockCountL; + WORD wBlockCountH; + + /* */ + /* Fail if the DSP kernel has been unloaded */ + /* */ + + if (phwi->dwFlags & HWI_FLAG_UNLOADED) + return KRETURN_ERROR_UNLOADED; + + /* */ + /* Make sure client and an instance exist... */ + /* */ + + if (dwClient >= NUMBER_OF_CLIENTS) + return KRETURN_ERROR_GENERIC; + + if (!phwi->asClientTable[dwClient].dwReferenceCount) + return KRETURN_ERROR_GENERIC; + + /* */ + /* Get the block count */ + /* */ + + while (wRetry--) + { + /* read high/low word of current block count */ + + wBlockCountH = kDspReadWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + pClient_Inst-> + dwDspDataClientArea + + CDATA_APU_BLOCK_COUNTH); + + wBlockCountL = kDspReadWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + pClient_Inst-> + dwDspDataClientArea + + CDATA_APU_BLOCK_COUNTL); + + /* if the high word hasn't changed, we've got a meaningful */ + /* block count value */ + + wBlockCount = kDspReadWord (devc, phwi->dwBaseIO, + MEMTYPE_INTERNAL_DATA, + pClient_Inst-> + dwDspDataClientArea + + CDATA_APU_BLOCK_COUNTH); + + if (wBlockCount == wBlockCountH) + break; + } + + /* fail if we couldn't get a meaningful block count */ + + if (wBlockCount != wBlockCountH) + return KRETURN_ERROR_GENERIC; + + *pdwBlockCount = MAKELONG (wBlockCountL, wBlockCountH); + + return KRETURN_SUCCESS; + +} /* kGetApuBlockCount() */ + +#endif + +/*--------------------------------------------------------------------------- */ +/* End of File: kernel.c */ +/*--------------------------------------------------------------------------- */ + +/****************************************************************************** + * * + * (C) 1997-1999 ESS Technology, Inc. * + * * + ******************************************************************************/ diff --git a/attic/drv/oss_allegro/kernelbn.inc b/attic/drv/oss_allegro/kernelbn.inc new file mode 100644 index 0000000..10441be --- /dev/null +++ b/attic/drv/oss_allegro/kernelbn.inc @@ -0,0 +1,1107 @@ +/****************************************************************************** + * * + * (C) 1997-1999 ESS Technology, Inc. * + * * + * This source code, its compiled object code, and its associated data sets * + * are copyright (C) 1997-1999 ESS Technology, Inc. * + * * + ******************************************************************************/ + +/*--------------------------------------------------------------------------- + * Copyright (C) 1997-1999, ESS Technology, Inc. + *--------------------------------------------------------------------------- + * FILENAME: kernelbn.c v1.01 + *--------------------------------------------------------------------------- + * DESCRIPTION: DSP binaries + *--------------------------------------------------------------------------- + * AUTHOR: Henry Tang / Hong Kim / Alger Yeung/Don Kim + *--------------------------------------------------------------------------- + * HISTORY: + * 09/25/97 HT Created. + * 01/20/97 PJCC (CRL) modified to include Sensaura 3D positional & + * speaker virtualization + * 05/05/99 AY cleanup for NT modem drivers + * 05/18/99 AY add cpythru for 400/500/600/800 + * 05/24/99 AY add cpythru for 4C0/680 + *--------------------------------------------------------------------------- + */ + +#ifdef NT_MODEL +#ifdef DON +#include "../port.h" +#include "kernel.h" +#endif +#endif + +/* */ +/* Kernel */ +/* */ + +WORD gawKernelVectCode[] = { +#include "kernel.dat" +}; + +KERNEL_BIN gsKernelVectCode = { + gawKernelVectCode, + sizeof (gawKernelVectCode) +}; + +/* */ +/* Memory Check Kernel */ +/* */ + +WORD gawMemChkVectCode[] = { +#include "memchk.dat" +}; + +KERNEL_BIN gsMemChkVectCode = { + gawMemChkVectCode, + sizeof (gawMemChkVectCode) +}; + + +/* */ +/* Copy Through */ +/* */ + +WORD gawCpyThruDataXXXX[] = { + 0x0000 +}; + +WORD gawCpyThruVect0400[] = { + 0x7980, 0x0400, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawCpyThruCode0400[] = { + 0 /*#include "400cpyth.dat" */ +}; + +WORD gawCpyThruVect04C0[] = { + 0x7980, 0x04C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawCpyThruCode04C0[] = { + 0 /*#include "4C0cpyth.dat" */ +}; + +WORD gawCpyThruVect0500[] = { + 0x7980, 0x0500, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawCpyThruCode0500[] = { + 0 /*#include "500cpyth.dat" */ +}; + +WORD gawCpyThruVect0600[] = { + 0x7980, 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawCpyThruCode0600[] = { + 0 /*#include "600cpyth.dat" */ +}; + + +WORD gawCpyThruVect0680[] = { + 0x7980, 0x0680, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawCpyThruCode0680[] = { + 0 /*#include "680cpyth.dat" */ +}; + +WORD gawCpyThruVect0800[] = { + 0x7980, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawCpyThruCode0800[] = { + 0 /*#include "800cpyth.dat" */ +}; + +CLIENT_BIN gasCpyThruVectCode[] = { + { + 0x0400, + gawCpyThruVect0400, + gawCpyThruCode0400, + gawCpyThruDataXXXX, + sizeof (gawCpyThruVect0400), + sizeof (gawCpyThruCode0400), + sizeof (gawCpyThruDataXXXX)} + , + { + 0x04C0, + gawCpyThruVect04C0, + gawCpyThruCode04C0, + gawCpyThruDataXXXX, + sizeof (gawCpyThruVect04C0), + sizeof (gawCpyThruCode04C0), + sizeof (gawCpyThruDataXXXX)} + , + { + 0x0500, + gawCpyThruVect0500, + gawCpyThruCode0500, + gawCpyThruDataXXXX, + sizeof (gawCpyThruVect0500), + sizeof (gawCpyThruCode0500), + sizeof (gawCpyThruDataXXXX)} + , + { + 0x0600, + gawCpyThruVect0600, + gawCpyThruCode0600, + gawCpyThruDataXXXX, + sizeof (gawCpyThruVect0600), + sizeof (gawCpyThruCode0600), + sizeof (gawCpyThruDataXXXX)} + , + { + 0x0680, + gawCpyThruVect0680, + gawCpyThruCode0680, + gawCpyThruDataXXXX, + sizeof (gawCpyThruVect0680), + sizeof (gawCpyThruCode0680), + sizeof (gawCpyThruDataXXXX)} + , + { + 0x0800, + gawCpyThruVect0800, + gawCpyThruCode0800, + gawCpyThruDataXXXX, + sizeof (gawCpyThruVect0800), + sizeof (gawCpyThruCode0800), + sizeof (gawCpyThruDataXXXX)} + , + { + NULL, NULL, NULL, NULL, NULL, NULL, NULL} +}; + +/* */ +/* Modem */ +/* */ + +WORD gawModemData[] = { + /* M3 HSP client data area starts at 0x1100 */ + /* 80H words at 1100H */ + + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + + /* 80H words at 1180H */ + + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + +#ifdef NT_MODEL + /* 80H words at 1200H */ + + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + + /* 80H words at 1280H */ + + 0 /*#include "modemntd.dat" */ +#else + /* 80H words at 1200H */ + + 0 /*#include "modemd.dat" */ +#endif +}; + +WORD gawModemVect400[] = { + 0x7980, 0x0400, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +#ifdef NT_MODEL + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x7980, 0x0449, +#else + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x7980, 0x0449, +#endif + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000 +}; + +WORD gawModemVect800[] = { + 0x7980, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +#ifdef NT_MODEL + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x7980, 0x0849, +#else + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x7980, 0x0849, +#endif + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000 +}; + +WORD gawModemCode400[] = { +#ifdef NT_MODEL + 0 /*#include "modemnt4.dat" */ +#else + 0 /*#include "400modem.dat" */ +#endif +}; + +WORD gawModemCode800[] = { +#ifdef NT_MODEL + 0 /*#include "modemnt8.dat" */ +#else + 0 /*#include "800modem.dat" */ +#endif +}; + +CLIENT_BIN gasModemVectCode[] = { + { + 0x0400, + gawModemVect400, + gawModemCode400, + gawModemData, + sizeof (gawModemVect400), + sizeof (gawModemCode400), + sizeof (gawModemData)} + , + { + 0x0800, + gawModemVect800, + gawModemCode800, + gawModemData, + sizeof (gawModemVect800), + sizeof (gawModemCode800), + sizeof (gawModemData)} + , + { + NULL, NULL, NULL, NULL, NULL, NULL, NULL} +}; + + +/* */ +/* Positional 3D */ +/* */ +/* Note: Data image contains 25 words (first 22 are CDATA_HEADER + */ +/* kernel spare, next 3 are dpaddr, control_enabled and current_count */ +/* for Pos3d) */ +/* */ + +WORD gawPos3DDataXXXX[] = { + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000 +}; + +WORD gawPos3DVect0400[] = { + 0x7980, 0x0400, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000 +}; + +WORD gawPos3DCode0400[] = { + 0 /*#include "4pos3d.dat" */ +}; + +WORD gawPos3DVect0800[] = { + 0x7980, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000 +}; + +WORD gawPos3DCode0800[] = { + 0 /*#include "8pos3d.dat" */ +}; + +CLIENT_BIN gasPos3DVectCode[] = { + { + 0x0400, + gawPos3DVect0400, + gawPos3DCode0400, + gawPos3DDataXXXX, + sizeof (gawPos3DVect0400), + sizeof (gawPos3DCode0400), + sizeof (gawPos3DDataXXXX)} + , + { + 0x0800, + gawPos3DVect0800, + gawPos3DCode0800, + gawPos3DDataXXXX, + sizeof (gawPos3DVect0800), + sizeof (gawPos3DCode0800), + sizeof (gawPos3DDataXXXX)} + , + { + NULL, NULL, NULL, NULL, NULL, NULL, NULL} +}; + +/* */ +/* Speaker Virtualization */ +/* */ + +WORD gawSpkVirtDataXXXX[] = { + 0x0000 +}; + +WORD gawSpkVirtVect0400[] = { + 0x7980, 0x0400, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000 +}; + +WORD gawSpkVirtCode0400[] = { + 0 /*#include "4vmax.dat" */ +}; + +WORD gawSpkVirtVect0800[] = { + 0x7980, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000 +}; + +WORD gawSpkVirtCode0800[] = { + 0 /*#include "8vmax.dat" */ +}; + +CLIENT_BIN gasSpkVirtVectCode[] = { + { + 0x0400, + gawSpkVirtVect0400, + gawSpkVirtCode0400, + gawSpkVirtDataXXXX, + sizeof (gawSpkVirtVect0400), + sizeof (gawSpkVirtCode0400), + sizeof (gawSpkVirtDataXXXX)} + , + { + 0x0800, + gawSpkVirtVect0800, + gawSpkVirtCode0800, + gawSpkVirtDataXXXX, + sizeof (gawSpkVirtVect0800), + sizeof (gawSpkVirtCode0800), + sizeof (gawSpkVirtDataXXXX)} + , + { + NULL, NULL, NULL, NULL, NULL, NULL, NULL} +}; + +/* */ +/* CRL Speaker Virtualization */ +/* */ + +WORD gawSpkVirtDataXXXX_CRL[] = { + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000 +}; + +WORD gawSpkVirtVect0400_CRL[] = { + 0x7980, 0x0400, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000 +}; + +WORD gawSpkVirtCode0400_CRL[] = { + 0 /*#include "4spkvirt.dat" */ +}; + +WORD gawSpkVirtVect0800_CRL[] = { + 0x7980, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000 +}; + +WORD gawSpkVirtCode0800_CRL[] = { + 0 /*#include "8spkvirt.dat" */ +}; + +CLIENT_BIN gasSpkVirtVectCode_CRL[] = { + { + 0x0400, + gawSpkVirtVect0400_CRL, + gawSpkVirtCode0400_CRL, + gawSpkVirtDataXXXX_CRL, + sizeof (gawSpkVirtVect0400_CRL), + sizeof (gawSpkVirtCode0400_CRL), + sizeof (gawSpkVirtDataXXXX_CRL)} + , + { + 0x0800, + gawSpkVirtVect0800_CRL, + gawSpkVirtCode0800_CRL, + gawSpkVirtDataXXXX_CRL, + sizeof (gawSpkVirtVect0800_CRL), + sizeof (gawSpkVirtCode0800_CRL), + sizeof (gawSpkVirtDataXXXX_CRL)} + , + { + NULL, NULL, NULL, NULL, NULL, NULL, NULL} +}; + +/* */ +/* Sample Rate Conversion */ +/* */ + +WORD gawSRCDataXXXX[] = { + 0x0000 +}; + + +WORD gawSRCVect0400[] = { + 0x7980, 0x0400, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawSRCCode0400[] = { + 0 /*#include "400src36.dat" */ +}; + +WORD gawSRCVect0500[] = { + 0x7980, 0x0500, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawSRCCode0500[] = { + 0 /*#include "500src36.dat" */ +}; + +WORD gawSRCVect0600[] = { + 0x7980, 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawSRCCode0600[] = { + 0 /*#include "600src36.dat" */ +}; + +WORD gawSRCVect0800[] = { + 0x7980, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawSRCCode0800[] = { + 0 /*#include "800src36.dat" */ +}; + +CLIENT_BIN gasSRCVectCode[] = { + { + 0x0400, + gawSRCVect0400, + gawSRCCode0400, + gawSRCDataXXXX, + sizeof (gawSRCVect0400), + sizeof (gawSRCCode0400), + sizeof (gawSRCDataXXXX)} + , + { + 0x0500, + gawSRCVect0500, + gawSRCCode0500, + gawSRCDataXXXX, + sizeof (gawSRCVect0500), + sizeof (gawSRCCode0500), + sizeof (gawSRCDataXXXX)} + , + { + 0x0600, + gawSRCVect0600, + gawSRCCode0600, + gawSRCDataXXXX, + sizeof (gawSRCVect0600), + sizeof (gawSRCCode0600), + sizeof (gawSRCDataXXXX)} + , + { + 0x0800, + gawSRCVect0800, + gawSRCCode0800, + gawSRCDataXXXX, + sizeof (gawSRCVect0800), + sizeof (gawSRCCode0800), + sizeof (gawSRCDataXXXX)} + , + { + NULL, NULL, NULL, NULL, NULL, NULL, NULL} +}; + +/* */ +/* MINI Sample Rate Conversion */ +/* */ + +WORD gawMINISRCDataXXXX[] = { + 0x0000 +}; + +WORD gawMINISRCVect0400[] = { + 0x7980, 0x0400, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawMINISRCCode0400[] = { +#include "400m_src.dat" +}; + +WORD gawMINISRCVect0500[] = { + 0x7980, 0x0500, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawMINISRCCode0500[] = { +#include "500m_src.dat" +}; + +WORD gawMINISRCVect0600[] = { + 0x7980, 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawMINISRCCode0600[] = { +#include "600m_src.dat" +}; + +WORD gawMINISRCVect0800[] = { + 0x7980, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawMINISRCCode0800[] = { +#include "800m_src.dat" +}; + + +WORD gawMINISRCVect0900[] = { + 0x7980, 0x0900, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawMINISRCCode0900[] = { +#include "900m_src.dat" +}; + + +WORD gawMINISRCVect0A00[] = { + 0x7980, 0x0A00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawMINISRCCode0A00[] = { +#include "a00m_src.dat" +}; + +WORD gawMINISRCVect0A80[] = { + 0x7980, 0x0A80, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawMINISRCCode0A80[] = { +#include "a80m_src.dat" +}; + +CLIENT_BIN gasMINISRCVectCode[] = { + { + 0x0400, + gawMINISRCVect0400, + gawMINISRCCode0400, + gawMINISRCDataXXXX, + sizeof (gawMINISRCVect0400), + sizeof (gawMINISRCCode0400), + sizeof (gawMINISRCDataXXXX)} + , + { + 0x0500, + gawMINISRCVect0500, + gawMINISRCCode0500, + gawMINISRCDataXXXX, + sizeof (gawMINISRCVect0500), + sizeof (gawMINISRCCode0500), + sizeof (gawMINISRCDataXXXX)} + , + { + 0x0600, + gawMINISRCVect0600, + gawMINISRCCode0600, + gawMINISRCDataXXXX, + sizeof (gawMINISRCVect0600), + sizeof (gawMINISRCCode0600), + sizeof (gawMINISRCDataXXXX)} + , + { + 0x0800, + gawMINISRCVect0800, + gawMINISRCCode0800, + gawMINISRCDataXXXX, + sizeof (gawMINISRCVect0800), + sizeof (gawMINISRCCode0800), + sizeof (gawMINISRCDataXXXX)} + , + { + 0x0900, + gawMINISRCVect0900, + gawMINISRCCode0900, + gawMINISRCDataXXXX, + sizeof (gawMINISRCVect0900), + sizeof (gawMINISRCCode0900), + sizeof (gawMINISRCDataXXXX)} + , + { + 0x0A00, + gawMINISRCVect0A00, + gawMINISRCCode0A00, + gawMINISRCDataXXXX, + sizeof (gawMINISRCVect0A00), + sizeof (gawMINISRCCode0A00), + sizeof (gawMINISRCDataXXXX)} + , + { + 0x0A80, + gawMINISRCVect0A80, + gawMINISRCCode0A80, + gawMINISRCDataXXXX, + sizeof (gawMINISRCVect0A80), + sizeof (gawMINISRCCode0A80), + sizeof (gawMINISRCDataXXXX)} + , + { + NULL, NULL, NULL, NULL, NULL, NULL, NULL} +}; + +/* */ +/* SPDIF */ +/* */ + +WORD gawSPDIFDataXXXX[] = { + 0x0000 +}; + +WORD gawSPDIFVect0400[] = { + 0x7980, 0x0400, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawSPDIFCode0400[] = { + 0 /*#include "400spdif.dat" */ +}; + +WORD gawSPDIFVect0500[] = { + 0x7980, 0x0500, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawSPDIFCode0500[] = { + 0 /*#include "500spdif.dat" */ +}; + +WORD gawSPDIFVect0600[] = { + 0x7980, 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawSPDIFCode0600[] = { + 0 /*#include "600spdif.dat" */ +}; + +WORD gawSPDIFVect0700[] = { + 0x7980, 0x0700, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawSPDIFCode0700[] = { + 0 /*#include "700spdif.dat" */ +}; + +WORD gawSPDIFVect0800[] = { + 0x7980, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawSPDIFCode0800[] = { + 0 /*#include "800spdif.dat" */ +}; + +WORD gawSPDIFVect0900[] = { + 0x7980, 0x0900, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawSPDIFCode0900[] = { + 0 /*#include "900spdif.dat" */ +}; + +WORD gawSPDIFVect0A00[] = { + 0x7980, 0x0A00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, +}; + +WORD gawSPDIFCode0A00[] = { + 0 /*#include "A00spdif.dat" */ +}; + +CLIENT_BIN gasSPDIFVectCode[] = { + { + 0x0400, + gawSPDIFVect0400, + gawSPDIFCode0400, + gawSPDIFDataXXXX, + sizeof (gawSPDIFVect0400), + sizeof (gawSPDIFCode0400), + sizeof (gawSPDIFDataXXXX)} + , + { + 0x0500, + gawSPDIFVect0500, + gawSPDIFCode0500, + gawSPDIFDataXXXX, + sizeof (gawSPDIFVect0500), + sizeof (gawSPDIFCode0500), + sizeof (gawSPDIFDataXXXX)} + , + { + 0x0600, + gawSPDIFVect0600, + gawSPDIFCode0600, + gawSPDIFDataXXXX, + sizeof (gawSPDIFVect0600), + sizeof (gawSPDIFCode0600), + sizeof (gawSPDIFDataXXXX)} + , + { + 0x0700, + gawSPDIFVect0700, + gawSPDIFCode0700, + gawSPDIFDataXXXX, + sizeof (gawSPDIFVect0700), + sizeof (gawSPDIFCode0700), + sizeof (gawSPDIFDataXXXX)} + , + { + 0x0800, + gawSPDIFVect0800, + gawSPDIFCode0800, + gawSPDIFDataXXXX, + sizeof (gawSPDIFVect0800), + sizeof (gawSPDIFCode0800), + sizeof (gawSPDIFDataXXXX)} + , + { + 0x0900, + gawSPDIFVect0900, + gawSPDIFCode0900, + gawSPDIFDataXXXX, + sizeof (gawSPDIFVect0900), + sizeof (gawSPDIFCode0900), + sizeof (gawSPDIFDataXXXX)} + , + { + 0x0A00, + gawSPDIFVect0A00, + gawSPDIFCode0A00, + gawSPDIFDataXXXX, + sizeof (gawSPDIFVect0A00), + sizeof (gawSPDIFCode0A00), + sizeof (gawSPDIFDataXXXX)} + , + { + NULL, NULL, NULL, NULL, NULL, NULL, NULL} +}; + +#if 0 +#ifndef NT_MODEL +/* */ +/* FM client is a special case */ +/* */ +/* Note: If FM .dat images without passthru support are used */ +/* PASSTHRU_SIZE can be set to zero. */ +/* */ + +#define PASSTHRU_SIZE 256 + +WORD gawFMData[1024 + PASSTHRU_SIZE] = { +#include "fm_d1000.dat" +}; + +WORD gawFMData2[] = { +#include "fm_d2000.dat" +}; + +WORD gawFMVectCode[256 + PASSTHRU_SIZE] = { +#include "fm_c0000.dat" +}; + +WORD gawFMCode[1024] = { +#include "fm_c0800.dat" +}; + +FMCLIENT_BIN gsFMVectCode = { + 0x0800, + 0x2000, + gawFMVectCode, + gawFMCode, + gawFMData, + gawFMData2, + sizeof (gawFMVectCode), + sizeof (gawFMCode), + sizeof (gawFMData), + sizeof (gawFMData2) +}; +#endif +#endif +WORD MIXER_TASK_NUMBER = 0; + +/*--------------------------------------------------------------------------- */ +/* End of File: kernelbn.h */ +/*--------------------------------------------------------------------------- */ + +/****************************************************************************** + * * + * (C) 1997-1999 ESS Technology, Inc. * + * * + ******************************************************************************/ diff --git a/attic/drv/oss_allegro/memchk.dat b/attic/drv/oss_allegro/memchk.dat new file mode 100644 index 0000000..1f8d3f6 --- /dev/null +++ b/attic/drv/oss_allegro/memchk.dat @@ -0,0 +1,33 @@ +0x7980, 0x001A, 0x7980, 0x0020, 0x7980, 0x0020, 0x7980, 0x0020, 0x7980, 0x0020, 0x7980, 0x0020,
+0x7980, 0x0020, 0x7980, 0x0020, 0x7980, 0x0020, 0x7980, 0x0020, 0x7980, 0x0020, 0x7980, 0x0020,
+0x7980, 0x0020, 0x0807, 0xBFC0, 0x0024, 0x8807, 0x7980, 0x005C, 0xBE38, 0x7980, 0x0021, 0x8BD0,
+0x0818, 0x9001, 0x0810, 0x9002, 0xBF80, 0xFFFF, 0x9003, 0x1080, 0x9004, 0x7980, 0x0051, 0x8BD0,
+0x0818, 0x9001, 0x0810, 0x9002, 0xBF80, 0x0000, 0x9003, 0x1080, 0x9004, 0x7980, 0x0051, 0x8BD0,
+0x0818, 0x9001, 0x0810, 0x9002, 0xBF80, 0x5555, 0x9003, 0x1080, 0x9004, 0x7980, 0x0051, 0x8BD0,
+0x0818, 0x9001, 0x0810, 0x9002, 0xBF80, 0xAAAA, 0x9003, 0x1080, 0x9004, 0x8BE0, 0xBF80, 0x0000,
+0x9005, 0xBF80, 0x0002, 0x9000, 0x1005, 0xE388, 0x0058, 0xEF00, 0x8B88, 0xBE46, 0xBF80, 0x0001,
+0x8818, 0xBF80, 0x1000, 0x8816, 0x0816, 0xBE1E, 0xBC28, 0xBFA0, 0x1000, 0xE388, 0x0072, 0xBE1F,
+0xBC30, 0xBFA0, 0x1400, 0xE388, 0x0072, 0xBC20, 0x6906, 0xE388, 0x0072, 0x0818, 0xBA01, 0x8811,
+0xBF80, 0x01FF, 0xBE1E, 0x0818, 0xBE0A, 0xE388, 0x0084, 0xBE1D, 0xBE0A, 0xBE1D, 0x7980, 0x007C,
+0xBE1D, 0x8817, 0x0816, 0x8810, 0x8B88, 0x0817, 0x8809, 0xBF80, 0x0000, 0xBFC0, 0xFFFF, 0xBEC6,
+0x0093, 0x8B00, 0x90E0, 0x98E0, 0x8B89, 0x0810, 0xBFA0, 0x03FF, 0x8810, 0x7B90, 0x0088, 0x0818,
+0xBA01, 0x8811, 0x0816, 0x8810, 0x8B88, 0x0817, 0x8809, 0x8B00, 0x8B00, 0xBEC6, 0x00B2, 0x10E0,
+0xBFA0, 0xFFFF, 0xEB08, 0x0023, 0x10E0, 0xBA00, 0xEB08, 0x002F, 0x8B00, 0x8B00, 0x8B00, 0x8B89,
+0x0810, 0xBFA0, 0x03FF, 0x8810, 0x7B90, 0x00A0, 0x0818, 0xBA01, 0x8811, 0x0816, 0x8810, 0x8B88,
+0x0817, 0x8809, 0xBF80, 0x0000, 0xBE82, 0xFFFF, 0xBEC6, 0x00CA, 0x8B00, 0x90E0, 0x98E0, 0x8B89,
+0x0810, 0xBFA0, 0x03FF, 0x8810, 0x7B90, 0x00BF, 0x0818, 0xBA01, 0x8811, 0x0816, 0x8810, 0x8B88,
+0x0817, 0x8809, 0x8B00, 0x8B00, 0xBEC6, 0x00E9, 0x10E0, 0xBA00, 0xEB08, 0x002F, 0x10E0, 0xBFA0,
+0xFFFF, 0xEB08, 0x0023, 0x8B00, 0x8B00, 0x8B00, 0x8B89, 0x0810, 0xBFA0, 0x03FF, 0x8810, 0x7B90,
+0x00D7, 0x0818, 0xBA01, 0x8811, 0x0816, 0x8810, 0x8B88, 0x0817, 0x8809, 0xBF80, 0x5555, 0xBE82,
+0xAAAA, 0xBEC6, 0x0101, 0x8B00, 0x90E0, 0x98E0, 0x8B89, 0x0810, 0xBFA0, 0x03FF, 0x8810, 0x7B90,
+0x00F6, 0x0818, 0xBA01, 0x8811, 0x0816, 0x8810, 0x8B88, 0x0817, 0x8809, 0x8B00, 0x8B00, 0xBEC6,
+0x0121, 0x10E0, 0xBFA0, 0x5555, 0xEB08, 0x003B, 0x10E0, 0xBFA0, 0xAAAA, 0xEB08, 0x0047, 0x8B00,
+0x8B00, 0x8B00, 0x8B89, 0x0810, 0xBFA0, 0x03FF, 0x8810, 0x7B90, 0x010E, 0x0818, 0xBA01, 0x8811,
+0x0816, 0x8810, 0x8B88, 0x0817, 0x8809, 0xBF80, 0xAAAA, 0xBE82, 0x5555, 0xBEC6, 0x0139, 0x8B00,
+0x90E0, 0x98E0, 0x8B89, 0x0810, 0xBFA0, 0x03FF, 0x8810, 0x7B90, 0x012E, 0x0818, 0xBA01, 0x8811,
+0x0816, 0x8810, 0x8B88, 0x0817, 0x8809, 0x8B00, 0x8B00, 0xBEC6, 0x0159, 0x10E0, 0xBFA0, 0xAAAA,
+0xEB08, 0x0047, 0x10E0, 0xBFA0, 0x5555, 0xEB08, 0x003B, 0x8B00, 0x8B00, 0x8B00, 0x8B89, 0x0810,
+0xBFA0, 0x03FF, 0x8810, 0x7B90, 0x0146, 0x1009, 0xE308, 0x016E, 0x0818, 0xBE09, 0xBE1E, 0xBA40,
+0xE304, 0x016E, 0xBE1F, 0x8818, 0x7980, 0x0072, 0xBF80, 0x0001, 0x9000, 0x1000, 0xE308, 0x0171,
+0xBF80, 0x0001, 0x8818, 0x0816, 0xBF90, 0x0400, 0x8816, 0xBFA0, 0x1800, 0xE3CC, 0x0064, 0x7980,
+0x0021,
diff --git a/attic/drv/oss_allegro/oss_allegro.c b/attic/drv/oss_allegro/oss_allegro.c new file mode 100644 index 0000000..150f8e5 --- /dev/null +++ b/attic/drv/oss_allegro/oss_allegro.c @@ -0,0 +1,1081 @@ +/* + * Driver for ALLEGRO PCI audio controller. + */ +/* + * + * This file is part of Open Sound System. + * + * Copyright (C) 4Front Technologies 1996-2008. + * + * This this source file is released under GPL v2 license (no other versions). + * See the COPYING file included in the main directory of this source + * distribution for the license terms and conditions. + * + */ + + +#include "oss_allegro_cfg.h" +#include "oss_pci.h" +#include "ac97.h" +#include "uart401.h" + +#ifndef PAGE_SIZE +#define PAGE_SIZE 4096 +#endif + +#define NT_MODEL + +#define ESSM3_VENDOR_ID 0x125D +#define ESS_1988 0x1988 /* allegro */ +#define ESS_1989 0x1989 /* allegro */ +#define ESS_1990 0x1990 /* Canyon 3D */ +#define ESS_1992 0x1992 /* Canyon 3D-2 */ +#define ESS_1998 0x1998 /* m3 */ +#define ESS_1999 0x1999 /* m3 */ +#define ESS_199A 0x199a /* m3 */ +#define ESS_199B 0x199b /* m3 */ + +#define NT_MODEL +#define MAX_PORTC 2 + +typedef struct allegro_portc +{ + int speed, bits, channels; + int open_mode; + int audio_enabled; + int trigger_bits; + int audiodev; +} +allegro_portc; + +typedef struct allegro_devc +{ + oss_device_t *osdev; + oss_native_word base, mpu_base; + int mpu_attached, fm_attached; + uart401_devc uart401devc; + int irq; + int model; +#define MDL_ESS1988 1 +#define MDL_ESS1989 2 +#define MDL_ESS1990 3 +#define MDL_ESS1992 4 +#define MDL_ESS1998 5 +#define MDL_ESS1999 6 +#define MDL_ESS199A 7 +#define MDL_ESS199B 8 + char *chip_name; + + /* Audio parameters */ + int open_mode; + int audio_initialized; + allegro_portc portc[MAX_PORTC]; + oss_mutex_t mutex; + oss_mutex_t low_mutex; + + /* buffer and device control */ + unsigned char fmt, ctrl; + struct dmabuf + { + void *rawbuf; + unsigned dmasize; + oss_native_word base; /* Offset for ptr */ + } + dma_adc, dma_dac; + + oss_dma_handle_t dma_handle; + + /* Mixer parameters */ + ac97_devc ac97devc; +} +allegro_devc; + +#include "port.h" +#include "hardware.h" +#include "kernel.h" +#include "srcmgr.h" + +PALLEGRO_WAVE *WaveStream = NULL; +extern int allegro_mpu_ioaddr; +extern int allegro_amp; +int debug = 0; + +#define ESS_CFMT_STEREO 0x01 +#define ESS_CFMT_16BIT 0x02 +#define ESS_CFMT_MASK 0x03 +#define ESS_CFMT_ASHIFT 0 +#define ESS_CFMT_CSHIFT 4 + +#define CTRL_DAC_EN 0x40 /* enable DAC */ +#define CTRL_ADC_EN 0x10 /* enable ADC */ + +WORD gwDSPConnectIn = KCONNECT_ADC1; /* Default ADC1 */ + +#include "allegro_util.inc" +#include "srcmgr.inc" +#include "kernel.inc" +#include "kernelbn.inc" + + +unsigned int +GetPosition (allegro_devc * devc, unsigned char Direction) +{ + oss_native_word flags; + unsigned long pos = 0; + + if (!Direction) + WaveStream = &CaptureStream; + else + WaveStream = &PlaybackStream; + + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); + + if (*WaveStream) + pos = SRCMGR_GetPosition (devc, *WaveStream); + + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + return pos; +} + +static int +ac97_write (void *devc_, int addr, int data) +{ + oss_native_word flags; + allegro_devc *devc = devc_; +#if 0 + int i; + + MUTEX_ENTER_IRQDISABLE (devc->low_mutex, flags); + for (i = 0; i < 1000; i++) + if (!(INB (devc->osdev, devc->base + 0x30) & 0x01)) + break; + OUTW (devc->osdev, data & 0xffff, devc->base + 0x32); + oss_udelay (100); + OUTW (devc->osdev, (addr & 0x7f) & ~0x80, devc->base + 0x30); + MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags); +#else + MUTEX_ENTER_IRQDISABLE (devc->low_mutex, flags); + HWMGR_WriteCodecData (devc, (UCHAR) addr, data); + MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags); +#endif + return 0; +} + +static int +ac97_read (void *devc_, int addr) +{ + allegro_devc *devc = devc_; + oss_native_word flags; + unsigned short data; +#if 0 + int i; + int sanity = 10000; + + MUTEX_ENTER_IRQDISABLE (devc->low_mutex, flags); + for (i = 0; i < 100000; i++) + if (!(INB (devc->osdev, devc->base + 0x30) & 0x01)) + break; + OUTW (devc->osdev, addr | 0x80, devc->base + 0x30); + + while (INB (devc->osdev, devc->base + 0x30) & 1) + { + sanity--; + if (!sanity) + { + cmn_err (CE_WARN, "ac97 codec timeout - 0x%x.\n", addr); + MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags); + return 0; + } + } + + data = INW (devc->osdev, devc->base + 0x32); + MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags); +#else + MUTEX_ENTER_IRQDISABLE (devc->low_mutex, flags); + HWMGR_ReadCodecData (devc, (UCHAR) addr, &data); + MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags); +#endif + return data; +} + +void +HwStartDMA (allegro_devc * devc, unsigned char Direction) +{ + if (!Direction) + WaveStream = &CaptureStream; + else + WaveStream = &PlaybackStream; + + SetState (devc, *WaveStream, KSSTATE_RUN); + + DDB (cmn_err (CE_WARN, "Wave%s DMA started\n", !Direction ? "In" : "Out")); +} + + +void +HwStopDMA (allegro_devc * devc, unsigned char Direction) +{ + if (!Direction) + WaveStream = &CaptureStream; + else + WaveStream = &PlaybackStream; + + SetState (devc, *WaveStream, KSSTATE_STOP); + + DDB (cmn_err (CE_WARN, "Wave%s DMA stopped\n", !Direction ? "In" : "Out")); +} + + +void +HwSetWaveFormat (allegro_devc * devc, PWAVE_INFO WaveInfo, + unsigned char Direction) +{ + + if (!Direction) + WaveStream = &CaptureStream; + else + WaveStream = &PlaybackStream; + + SetFormat (devc, *WaveStream, WaveInfo); +} + + +static int +allegrointr (oss_device_t * osdev) +{ + allegro_devc *devc = (allegro_devc *) osdev->devc; + unsigned char bIntStatus; + unsigned char bIntTimer = FALSE; + unsigned int currdac, curradc, n, i; + int serviced = 0; + + bIntStatus = INB (devc->osdev, devc->base + 0x1A); + + if (bIntStatus == 0xff) + return 0; + OUTW (devc->osdev, bIntStatus, devc->base + 0x1A); + if (bIntStatus & ASSP_INT_PENDING) + { + unsigned char status; + serviced = 1; + + status = INB (devc->osdev, (devc->base + ASSP_CONTROL_B)); + if ((status & STOP_ASSP_CLOCK) == 0) + { + status = INB (devc->osdev, (devc->base + ASSP_HOST_INT_STATUS)); + + /* acknowledge other interrupts */ + if (status & DSP2HOST_REQ_TIMER) + { + OUTB (devc->osdev, DSP2HOST_REQ_TIMER, + (devc->base + ASSP_HOST_INT_STATUS)); + bIntTimer = TRUE; + } + } + } + + if (bIntStatus & 0x40) + { + serviced = 1; + OUTB (devc->osdev, 0x40, devc->base + 0x1A); + } + + if (bIntStatus & MPU401_INT_PENDING) + { + serviced = 1; + uart401_irq (&devc->uart401devc); + } + + if (!bIntTimer) + return serviced; + + for (i = 0; i < MAX_PORTC; i++) + { + allegro_portc *portc = &devc->portc[i]; + if (portc->trigger_bits & PCM_ENABLE_OUTPUT) + { + dmap_t *dmapout = audio_engines[portc->audiodev]->dmap_out; + currdac = GetPosition (devc, 1); + currdac /= dmapout->fragment_size; + n = 0; + while (dmap_get_qhead (dmapout) != currdac && n++ < dmapout->nfrags) + oss_audio_outputintr (portc->audiodev, 1); + } + if (portc->trigger_bits & PCM_ENABLE_INPUT) + { + dmap_t *dmapin = audio_engines[portc->audiodev]->dmap_in; + curradc = GetPosition (devc, 0); + curradc /= dmapin->fragment_size; + + n = 0; + while (dmap_get_qtail (dmapin) != curradc && n++ < dmapin->nfrags) + oss_audio_inputintr (portc->audiodev, 0); + } + } + + return serviced; +} + +static int +allegro_audio_set_rate (int dev, int arg) +{ + allegro_portc *portc = audio_engines[dev]->portc; + + if (arg == 0) + return portc->speed; + + if (arg > 48000) + arg = 48000; + if (arg < 5000) + arg = 5000; + portc->speed = arg; + return portc->speed; +} + +static short +allegro_audio_set_channels (int dev, short arg) +{ + allegro_portc *portc = audio_engines[dev]->portc; + + if ((arg != 1) && (arg != 2)) + return portc->channels; + portc->channels = arg; + + return portc->channels; +} + +static unsigned int +allegro_audio_set_format (int dev, unsigned int arg) +{ + allegro_portc *portc = audio_engines[dev]->portc; + + if (arg == 0) + return portc->bits; + + if (!(arg & (AFMT_U8 | AFMT_S16_LE))) + return portc->bits; + portc->bits = arg; + + return portc->bits; +} + +/*ARGSUSED*/ +static int +allegro_audio_ioctl (int dev, unsigned int cmd, ioctl_arg arg) +{ + return OSS_EINVAL; +} + +static void allegro_audio_trigger (int dev, int state); + +static void +allegro_audio_reset (int dev) +{ + allegro_audio_trigger (dev, 0); +} + +static void +allegro_audio_reset_input (int dev) +{ + allegro_portc *portc = audio_engines[dev]->portc; + allegro_audio_trigger (dev, portc->trigger_bits & ~PCM_ENABLE_INPUT); +} + +static void +allegro_audio_reset_output (int dev) +{ + allegro_portc *portc = audio_engines[dev]->portc; + allegro_audio_trigger (dev, portc->trigger_bits & ~PCM_ENABLE_OUTPUT); +} + +/*ARGSUSED*/ +static int +allegro_audio_open (int dev, int mode, int open_flags) +{ + oss_native_word flags; + allegro_portc *portc = audio_engines[dev]->portc; + allegro_devc *devc = audio_engines[dev]->devc; + + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); + if (portc->open_mode) + { + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + return OSS_EBUSY; + } + + if (devc->open_mode & mode) + { + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + return OSS_EBUSY; + } + + devc->open_mode |= mode; + + + portc->open_mode = mode; + portc->audio_enabled &= ~mode; + + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + + return 0; +} + +static void +allegro_audio_close (int dev, int mode) +{ + allegro_portc *portc = audio_engines[dev]->portc; + allegro_devc *devc = audio_engines[dev]->devc; + + allegro_audio_reset (dev); + portc->open_mode = 0; + devc->open_mode &= ~mode; + portc->audio_enabled &= ~mode; +} + +/*ARGSUSED*/ +static void +allegro_audio_output_block (int dev, oss_native_word buf, int count, + int fragsize, int intrflag) +{ + allegro_portc *portc = audio_engines[dev]->portc; + + portc->audio_enabled |= PCM_ENABLE_OUTPUT; + portc->trigger_bits &= ~PCM_ENABLE_OUTPUT; + +} + +/*ARGSUSED*/ +static void +allegro_audio_start_input (int dev, oss_native_word buf, int count, + int fragsize, int intrflag) +{ + allegro_portc *portc = audio_engines[dev]->portc; + + portc->audio_enabled |= PCM_ENABLE_INPUT; + portc->trigger_bits &= ~PCM_ENABLE_INPUT; + +} + +static void +allegro_audio_trigger (int dev, int state) +{ + /*oss_native_word flags; */ + allegro_portc *portc = audio_engines[dev]->portc; + allegro_devc *devc = audio_engines[dev]->devc; + + /* MUTEX_ENTER_IRQDISABLE (devc->low_mutex, flags); */ + if (portc->open_mode & OPEN_WRITE) + { + if (state & PCM_ENABLE_OUTPUT) + { + if ((portc->audio_enabled & PCM_ENABLE_OUTPUT) && + !(portc->trigger_bits & PCM_ENABLE_OUTPUT)) + + { + devc->ctrl |= CTRL_DAC_EN; + HwStartDMA (devc, TRUE); + portc->trigger_bits |= PCM_ENABLE_OUTPUT; + } + } + else + { + if ((portc->audio_enabled & PCM_ENABLE_OUTPUT) && + (portc->trigger_bits & PCM_ENABLE_OUTPUT)) + { + portc->audio_enabled &= ~PCM_ENABLE_OUTPUT; + portc->trigger_bits &= ~PCM_ENABLE_OUTPUT; + devc->ctrl &= ~CTRL_DAC_EN; + HwStopDMA (devc, TRUE); + FreeStream (devc, PlaybackStream); + } + } + } + if (portc->open_mode & OPEN_READ) + { + if (state & PCM_ENABLE_INPUT) + { + if ((portc->audio_enabled & PCM_ENABLE_INPUT) && + !(portc->trigger_bits & PCM_ENABLE_INPUT)) + + { + devc->ctrl |= CTRL_ADC_EN; + HwStartDMA (devc, FALSE); + portc->trigger_bits |= PCM_ENABLE_INPUT; + } + } + else + { + if ((portc->audio_enabled & PCM_ENABLE_INPUT) && + (portc->trigger_bits & PCM_ENABLE_INPUT)) + + { + portc->audio_enabled &= ~PCM_ENABLE_INPUT; + portc->trigger_bits &= ~PCM_ENABLE_INPUT; + devc->ctrl &= ~CTRL_ADC_EN; + HwStopDMA (devc, FALSE); + FreeStream (devc, CaptureStream); + } + } + } + /* MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags); */ +} + +/*ARGSUSED*/ +static int +allegro_audio_prepare_for_input (int dev, int bsize, int bcount) +{ + allegro_devc *devc = audio_engines[dev]->devc; + allegro_portc *portc = audio_engines[dev]->portc; + oss_native_word flags; + WAVE_INFO WaveInfo; + + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); + WaveInfo.BitsPerSample = portc->bits; + WaveInfo.Channels = portc->channels; + WaveInfo.SamplesPerSec = portc->speed; + + HwSetWaveFormat (devc, &WaveInfo, FALSE); + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + + portc->audio_enabled &= ~PCM_ENABLE_INPUT; + portc->trigger_bits &= ~PCM_ENABLE_INPUT; + return 0; +} + +/*ARGSUSED*/ +static int +allegro_audio_prepare_for_output (int dev, int bsize, int bcount) +{ + allegro_devc *devc = audio_engines[dev]->devc; + allegro_portc *portc = audio_engines[dev]->portc; + oss_native_word flags; + WAVE_INFO WaveInfo; + + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); + WaveInfo.BitsPerSample = portc->bits; + WaveInfo.Channels = portc->channels; + WaveInfo.SamplesPerSec = portc->speed; + SRCMGR_SetVolume (devc, PlaybackStream->DspClientInstance, 0x7FFF, 0x7FFF); + + HwSetWaveFormat (devc, &WaveInfo, TRUE); + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + + portc->audio_enabled &= ~PCM_ENABLE_OUTPUT; + portc->trigger_bits &= ~PCM_ENABLE_OUTPUT; + return 0; +} + +static int +allegro_alloc_buffer (int dev, dmap_t * dmap, int direction) +{ + + allegro_devc *devc = audio_engines[dev]->devc; + + if (dmap->dmabuf != NULL) + return 0; + + if (direction == PCM_ENABLE_OUTPUT) + { + dmap->dmabuf = devc->dma_dac.rawbuf; + dmap->dmabuf_phys = devc->dma_dac.base; + dmap->buffsize = devc->dma_dac.dmasize; + } + if (direction == PCM_ENABLE_INPUT) + { + dmap->dmabuf = devc->dma_adc.rawbuf; + dmap->dmabuf_phys = devc->dma_adc.base; + dmap->buffsize = devc->dma_adc.dmasize; + } + return 0; +} + + +/*ARGSUSED*/ +static int +allegro_free_buffer (int dev, dmap_t * dmap, int direction) +{ + if (dmap->dmabuf == NULL) + return 0; + + dmap->dmabuf = NULL; + dmap->dmabuf_phys = 0; + dmap->buffsize = 0; + + return 0; +} + +/*ARGSUSED*/ +static int +allegro_get_buffer_pointer (int dev, dmap_t * dmap, int direction) +{ + allegro_devc *devc = audio_engines[dev]->devc; + oss_native_word flags; + oss_native_word ptr = 0; + + MUTEX_ENTER_IRQDISABLE (devc->low_mutex, flags); + if (direction == PCM_ENABLE_OUTPUT) + { + ptr = GetPosition (devc, 1); + } + if (direction == PCM_ENABLE_INPUT) + { + ptr = GetPosition (devc, 0); + } + MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags); + return ptr; +} + + +static int +alloc_dmabuf (allegro_devc * devc, int direction) +{ + struct dmabuf *db = direction ? &devc->dma_adc : &devc->dma_dac; + unsigned char fmt = 0; + oss_native_word phaddr; + + if (direction) + { + fmt &= ~((ESS_CFMT_STEREO | ESS_CFMT_16BIT) << ESS_CFMT_CSHIFT); + fmt >>= ESS_CFMT_CSHIFT; + + } + else + { + fmt &= ~((ESS_CFMT_STEREO | ESS_CFMT_16BIT) << ESS_CFMT_ASHIFT); + fmt >>= ESS_CFMT_ASHIFT; + } + + if (!db->rawbuf) + { +#define MAX_REJECTED 8 + int rejected = 0; + oss_native_word rejectedPA[MAX_REJECTED]; + oss_native_word PhysicalAddressConstraint = 0xFFFF; + + /* alloc as big a chunk as we can */ + db->dmasize = 16384; + + while (!db->rawbuf) + { + oss_native_word LogicalAddress; + void *rawbuf; + rawbuf = + (void *) CONTIG_MALLOC (devc->osdev, db->dmasize, + MEMLIMIT_32BITS, &phaddr, devc->dma_handle); + + if (!rawbuf) + break; + LogicalAddress = phaddr; + if (((LogicalAddress & ~PhysicalAddressConstraint) == + ((LogicalAddress + 0x4000 - 1) & ~PhysicalAddressConstraint))) + { + db->rawbuf = rawbuf; + } + else + { + if (rejected == MAX_REJECTED) + { + CONTIG_FREE (devc->osdev, rawbuf, db->dmasize, devc->dma_handle); + break; + } + rejectedPA[rejected] = (oss_native_word) rawbuf; + rejected++; + } + } + + while (rejected--) + { + CONTIG_FREE (devc->osdev, (char *) rejectedPA[rejected], + db->dmasize, TODO); + } + + if (!db->rawbuf) + return OSS_ENOMEM; + +#ifdef linux + /* now mark the pages as reserved; otherwise remap_page_range doesn't do what we want */ + oss_reserve_pages ((oss_native_word) db->rawbuf, + (oss_native_word) db->rawbuf + (PAGE_SIZE << 2) - 1); +#endif + } + memset (db->rawbuf, (fmt & ESS_CFMT_16BIT) ? 0 : 0x80, db->dmasize); + db->base = phaddr; + return 0; +} + +static int +free_dmabuf (allegro_devc * devc, unsigned direction) +{ + struct dmabuf *db; + + if (direction) + db = &devc->dma_dac; + else + db = &devc->dma_adc; + + if (db->rawbuf) + { +#ifdef linux + /* undo marking the pages as reserved */ + oss_unreserve_pages ((oss_native_word) db->rawbuf, + (oss_native_word) db->rawbuf + (PAGE_SIZE << 2) - + 1); +#endif + CONTIG_FREE (devc->osdev, db->rawbuf, db->dmasize, TODO); + db->rawbuf = NULL; + return 0; + } + return OSS_EIO; +} + +static audiodrv_t allegro_audio_driver = { + allegro_audio_open, + allegro_audio_close, + allegro_audio_output_block, + allegro_audio_start_input, + allegro_audio_ioctl, + allegro_audio_prepare_for_input, + allegro_audio_prepare_for_output, + allegro_audio_reset, + NULL, + NULL, + allegro_audio_reset_input, + allegro_audio_reset_output, + allegro_audio_trigger, + allegro_audio_set_rate, + allegro_audio_set_format, + allegro_audio_set_channels, + NULL, + NULL, + NULL, + NULL, + allegro_alloc_buffer, + allegro_free_buffer, + NULL, + NULL, + allegro_get_buffer_pointer +}; + +#if 0 +static void +attach_fm (allegro_devc * devc) +{ + if (!opl3_detect (0x388, devc->osdev)) + return; + opl3_init (0x388, devc->osdev); + devc->fm_attached = 1; +} +#endif + +static void +attach_mpu (allegro_devc * devc) +{ + devc->mpu_attached = 1; + uart401_init (&devc->uart401devc, devc->osdev, devc->mpu_base, + "Allegro MIDI UART"); +} + +static int +init_allegro (allegro_devc * devc) +{ + int my_mixer, adev; + int first_dev = 0; + int ret, i; + unsigned short val; + + devc->mpu_attached = devc->fm_attached = 0; + + ret = alloc_dmabuf (devc, 0); + if (ret != 0) + { + cmn_err (CE_WARN, "Couldn't allocate playback memory\n"); + return 1; + } + + ret = alloc_dmabuf (devc, 1); + if (ret != 0) + { + cmn_err (CE_WARN, "Couldn't allocate recording memory\n"); + return 1; + } + + AllocateStream (devc, WAVE_CAPTURE); + AllocateStream (devc, WAVE_PLAYBACK); + +#if 0 + for (i = devc->base + 0x1c; i <= devc->base + 0x1f; i++) + OUTB (devc->osdev, 0x00, i); + OUTB (devc->osdev, 0x40, devc->base + 0x38); + OUTB (devc->osdev, 0x10, devc->base + 0x3e); + OUTB (devc->osdev, 0x44, devc->base + 0x3f); +#endif + + HWMGR_InitSystem (devc); + OUTW (devc->osdev, 0x0012, devc->base + 0x18); + + /* Once enable it, never touch again */ + OUTB (devc->osdev, (INB (devc->osdev, devc->base + 0xA6) | 0x01), + devc->base + 0xA6); + + pci_read_config_word (devc->osdev, PCI_ALLEGRO_CONFIG, &val); + switch (devc->mpu_base) + { + case 0x330: + val |= 0; + break; + case 0x300: + val |= (1 << 3); + break; + case 0x320: + val |= (2 << 3); + break; + case 0x340: + val |= (3 << 3); + break; + } + pci_write_config_word (devc->osdev, PCI_ALLEGRO_CONFIG, val); + +#if 0 + attach_fm (devc); +#endif + + if (devc->mpu_base > 0) + attach_mpu (devc); + + + InitStream (); + + if (allegro_amp) + { + /*initialize the GPIOs....this is hacked using Windows settings */ + OUTB (devc->osdev, 0xff, devc->base + 0x61); + oss_udelay (100); + + OUTB (devc->osdev, 0xff, devc->base + 0x63); + oss_udelay (100); + + OUTB (devc->osdev, 0xff, devc->base + 0x67); + oss_udelay (100); + OUTB (devc->osdev, 0xff, devc->base + 0x69); + } + + my_mixer = ac97_install (&devc->ac97devc, "AC97 Mixer", + ac97_read, ac97_write, devc, devc->osdev); + if (my_mixer < 0) + return 0; + + for (i = 0; i < MAX_PORTC; i++) + { + int caps = ADEV_AUTOMODE; + allegro_portc *portc = &devc->portc[i]; + char tmp_name[256]; + + if (i == 0) + { + strcpy (tmp_name, devc->chip_name); + caps |= ADEV_DUPLEX; + } + else + { + strcpy (tmp_name, devc->chip_name); + caps |= ADEV_DUPLEX | ADEV_SHADOW; + } + + if ((adev = oss_install_audiodev (OSS_AUDIO_DRIVER_VERSION, + devc->osdev, + devc->osdev, + tmp_name, + &allegro_audio_driver, + sizeof (audiodrv_t), + caps, + AFMT_U8 | AFMT_S16_LE, devc, -1)) < 0) + { + adev = -1; + return 0; + } + else + { + if (i == 0) + first_dev = adev; + audio_engines[adev]->portc = portc; + audio_engines[adev]->rate_source = first_dev; + audio_engines[adev]->mixer_dev = my_mixer; + audio_engines[adev]->min_rate = 5000; + audio_engines[adev]->max_rate = 48000; + audio_engines[adev]->caps |= PCM_CAP_FREERATE; + audio_engines[adev]->vmix_flags = VMIX_MULTIFRAG; + portc->open_mode = 0; + portc->audiodev = adev; + portc->audio_enabled = 0; +#ifdef CONFIG_OSS_VMIX + if (i == 0) + vmix_attach_audiodev(devc->osdev, adev, -1, 0); +#endif + } + } + + return 1; +} + +int +oss_allegro_attach (oss_device_t * osdev) +{ + unsigned char pci_irq_line, pci_revision; + unsigned short pci_command, vendor, device; + unsigned int pci_ioaddr; + int err; + allegro_devc *devc; + DDB (cmn_err (CE_WARN, "Entered ALLEGRO ALLEGRO probe routine\n")); + + pci_read_config_word (osdev, PCI_VENDOR_ID, &vendor); + pci_read_config_word (osdev, PCI_DEVICE_ID, &device); + + if (vendor != ESSM3_VENDOR_ID || + (device != ESS_1988 && device != ESS_1989 && device != ESS_1990 && + device != ESS_1992 && device != ESS_1998 && device != ESS_1999 && + device != ESS_199A && device != ESS_199B)) + + return 0; + + pci_read_config_byte (osdev, PCI_REVISION_ID, &pci_revision); + pci_read_config_word (osdev, PCI_COMMAND, &pci_command); + pci_read_config_irq (osdev, PCI_INTERRUPT_LINE, &pci_irq_line); + pci_read_config_dword (osdev, PCI_BASE_ADDRESS_0, &pci_ioaddr); + + DDB (cmn_err (CE_WARN, "ALLEGRO I/O base %04x\n", pci_ioaddr)); + + if (pci_ioaddr == 0) + { + cmn_err (CE_WARN, "I/O address not assigned by BIOS.\n"); + return 0; + } + + if (pci_irq_line == 0) + { + cmn_err (CE_WARN, "IRQ not assigned by BIOS (%d).\n", pci_irq_line); + return 0; + } + + if ((devc = PMALLOC (osdev, sizeof (*devc))) == NULL) + { + cmn_err (CE_WARN, "Out of memory\n"); + return 0; + } + + + devc->osdev = osdev; + osdev->devc = devc; + devc->irq = pci_irq_line; + devc->mpu_base = allegro_mpu_ioaddr; + + devc->base = MAP_PCI_IOADDR (devc->osdev, 0, pci_ioaddr); + /* Remove I/O space marker in bit 0. */ + devc->base &= ~3; + + pci_command |= PCI_COMMAND_MASTER | PCI_COMMAND_IO; + pci_write_config_word (osdev, PCI_COMMAND, pci_command); + + /* Enable Game port/MPU401 */ + pci_read_config_word (osdev, PCI_LEGACY_AUDIO_CTRL, &pci_command); + pci_command = GAME_PORT_ENABLE | MPU401_IO_ENABLE | MPU401_IRQ_ENABLE; + pci_write_config_word (osdev, PCI_LEGACY_AUDIO_CTRL, pci_command); + + switch (device) + { + case ESS_1988: + devc->model = MDL_ESS1998; + devc->chip_name = "ESS Allegro (ESS1998)"; + bChipType = A1_1988; + break; + case ESS_1989: + devc->model = MDL_ESS1989; + devc->chip_name = "ESS Allegro (ESS1989)"; + bChipType = A1_1989; + break; + case ESS_1990: + devc->model = MDL_ESS1990; + devc->chip_name = "ESS Canyon 3D (ESS1990)"; + break; + case ESS_1992: + devc->model = MDL_ESS1992; + devc->chip_name = "ESS Canyon 3D-II (ESS1992)"; + break; + case ESS_1998: + devc->model = MDL_ESS1998; + devc->chip_name = "ESS Maestro3 (ESS1998)"; + bChipType = M3_1998; + break; + case ESS_1999: + devc->model = MDL_ESS1999; + devc->chip_name = "ESS Maestro3 (ESS1999)"; + bChipType = M3_1999; + break; + case ESS_199A: + devc->model = MDL_ESS199A; + devc->chip_name = "ESS Maestro3 (ESS199A)"; + bChipType = M3_199A; + break; + case ESS_199B: + devc->model = MDL_ESS199B; + devc->chip_name = "ESS Maestro3 (ESS199B)"; + bChipType = M3_199B; + break; + + } + + MUTEX_INIT (devc->osdev, devc->mutex, MH_DRV); + MUTEX_INIT (devc->osdev, devc->low_mutex, MH_DRV + 1); + + oss_register_device (osdev, devc->chip_name); + + if ((err = oss_register_interrupts (devc->osdev, 0, allegrointr, NULL)) < 0) + { + cmn_err (CE_WARN, "Can't allocate IRQ%d, err=%d\n", pci_irq_line, err); + return 0; + } + + return init_allegro (devc); /* Detected */ +} + + +int +oss_allegro_detach (oss_device_t * osdev) +{ + allegro_devc *devc = (allegro_devc *) osdev->devc; + int ret; + + if (oss_disable_device (osdev) < 0) + return 0; + + + OUTW (devc->osdev, 0x00, devc->base + 0x18); + + if (devc->mpu_attached) + { + uart401_disable (&devc->uart401devc); + devc->mpu_attached = 0; + } + + oss_unregister_interrupts (devc->osdev); + + ret = free_dmabuf (devc, 0); /* free playback mem */ + if (ret != 0) + { + cmn_err (CE_WARN, "Couldn't free playback memory\n"); + return 0; + } + + ret = free_dmabuf (devc, 1); /* free record mem */ + if (ret != 0) + { + cmn_err (CE_WARN, "Couldn't free record memory\n"); + return 0; + } + + MUTEX_CLEANUP (devc->mutex); + MUTEX_CLEANUP (devc->low_mutex); + UNMAP_PCI_IOADDR (devc->osdev, 0); + + oss_unregister_device (osdev); + return 1; +} diff --git a/attic/drv/oss_allegro/oss_allegro.man b/attic/drv/oss_allegro/oss_allegro.man new file mode 100644 index 0000000..b36bdbd --- /dev/null +++ b/attic/drv/oss_allegro/oss_allegro.man @@ -0,0 +1,25 @@ +NAME +oss_allegro - ESS Allegro/Maestro3 audio driver + +DESCRIPTION +Open Sound System driver for ESS Allegro/Maestro3 sound cards. +Allegro device characteristics: + - 8/16 bit playback/record + - mono/stereo playback/recording + - 8KHz to 48Khz sample rate. + +OPTIONS +o allegro_amp=0|1 +Some ES1988 devices have the ESS19XX ac97 device that needs to be turned on. + + +o allegro_mpu_ioaddr=<xxx> +The ESS allegro device supports the UART401 device (not usually found in +laptop models but only on certain PCI cards). Check the allegro.conf +file (see below) for valid addresses. + +FILES +CONFIGFILEPATH/oss_allegro.conf Device configuration file + +AUTHOR +4Front Technologies diff --git a/attic/drv/oss_allegro/port.h b/attic/drv/oss_allegro/port.h new file mode 100644 index 0000000..78397f4 --- /dev/null +++ b/attic/drv/oss_allegro/port.h @@ -0,0 +1,82 @@ +/* + * ESS Technology allegro audio driver. + * + * Copyright (C) 1992-2000 Don Kim (don.kim@esstech.com) + * + */ +#define VOID void +typedef void *PVOID; +typedef char CHAR; +typedef short SHORT; +typedef long LONG; +//typedef int BOOL; +//typedef unsigned char UCHAR; +typedef unsigned char *PBYTE; +typedef unsigned short *PUSHORT; +#define BYTE UCHAR +#define BOOLEAN UCHAR +typedef unsigned long DWORD; +#define USHORT WORD +typedef unsigned short WORD; +#define ULONG DWORD +#define IN +#define OUT +#ifndef TRUE +#define TRUE 1 +#define FALSE 0 +#endif +typedef unsigned short *PWORD; +typedef unsigned long *PDWORD; +typedef unsigned long *PULONG; + +#define inp(o,a) INB(o, a) +#define inpw(o,a) INW(o, a) +#define outp(o,a,d) OUTB(o, d, a) +#define outpw(o,a,d) OUTW(o, d, a) + +#define CRITENTER + +#define CRITLEAVE + +#define MAKEWORD(a, b) ((WORD)(((BYTE)(a)) | ((WORD)((BYTE)(b))) << 8)) +#define MAKELONG(a, b) ((LONG)(((WORD)(a)) | ((DWORD)((WORD)(b))) << 16)) +#define LOWORD(l) ((WORD)(l)) +#define HIWORD(l) ((WORD)(((DWORD)(l) >> 16) & 0xFFFF)) +#define LOBYTE(w) ((BYTE)(w)) +#define HIBYTE(w) ((BYTE)(((WORD)(w) >> 8) & 0xFF)) + + +#define KeStallExecutionProcessor oss_udelay +#define SoundDelay mdelay + +#define KeAcquireSpinLock(a, b) + +#define KeReleaseSpinLock(a, b) + + +#define READ_PORT_UCHAR( o, a ) INB(o, a) +#define READ_PORT_USHORT( o, a ) INW(o, a) +#define WRITE_PORT_UCHAR( o, a, d ) OUTB(o, d, a) +#define WRITE_PORT_USHORT( o, a, d ) OUTW(o, d, a) + +#define __cdecl + +typedef struct _WAVE_INFO +{ + ULONG SamplesPerSec; + UCHAR BitsPerSample; + UCHAR Channels; +} +WAVE_INFO, *PWAVE_INFO; + +#define KIRQL +#define OldIrql + +#ifdef MDEBUG +extern void dDbgOut (char *sz, ...); +#define dprintf1( _x_ ) if (debug >= 1) dDbgOut _x_ +#define dprintf3( _x_ ) if (debug >= 3) dDbgOut _x_ +#else +#define dprintf1( _x_ ) +#define dprintf3( _x_ ) +#endif diff --git a/attic/drv/oss_allegro/srcmgr.h b/attic/drv/oss_allegro/srcmgr.h new file mode 100644 index 0000000..987dadf --- /dev/null +++ b/attic/drv/oss_allegro/srcmgr.h @@ -0,0 +1,2498 @@ +/* + * ESS Technology allegro audio driver. + * + * Copyright (C) 1992-2000 Don Kim (don.kim@esstech.com) + * + */ +#ifndef __SRCMGR_H +#define __SRCMGR_H + +typedef enum +{ + KSSTATE_STOP, + /*KSSTATE_ACQUIRE, */ + /*KSSTATE_PAUSE, */ + KSSTATE_RUN +} +KSSTATE, *PKSSTATE; + +/* -------------------------------------------------------------------------- */ + +typedef struct +{ + ULONG Physical; + ULONG Length; +} +MBUFFER, *PMBUFFER; + +typedef struct +{ + BYTE WaveType; + BOOLEAN Format16Bit; + BOOLEAN FormatStereo; + BOOLEAN SR_8khzFlag; + KSSTATE State; + ULONG Frequency; + ULONG Length; + PMBUFFER Buffer; + + /* DSP kernel support */ + PCLIENT_INST DspClientInstance; + USHORT wFreqIndex; + USHORT wSRC3VarLen; + ULONG StreamType; + ULONG PositionBeforePaused; +} +ALLEGRO_WAVE, *PALLEGRO_WAVE; + + +#define WAVE_PLAYBACK 0 +#define WAVE_CAPTURE 1 +#define WAVE_MIXER 2 + +extern PALLEGRO_WAVE CaptureStream; +extern PALLEGRO_WAVE PlaybackStream; +extern PALLEGRO_WAVE MidiStream; + + +/*void AllocateStream ( BYTE waveType, PWAVE_INFO waveFormat ); */ +void InitStream (); +void AllocateStream (allegro_devc * devc, BYTE waveType); +void FreeStream (allegro_devc * devc, PALLEGRO_WAVE AllegroWave); +ULONG SRCMGR_GetPosition (allegro_devc * devc, PALLEGRO_WAVE AllegroWave); +void SetFormat (allegro_devc * devc, PALLEGRO_WAVE AllegroWave, + PWAVE_INFO waveFormat); +/*void SetState ( struct ess_state *s, PALLEGRO_WAVE AllegroWave, KSSTATE NewState ); */ +void +SRCMGR_SetVolume (allegro_devc * devc, IN PCLIENT_INST client, IN USHORT left, + IN USHORT right); +void SRCMGR_SetRearVolume (allegro_devc * devc, IN PCLIENT_INST client, + IN USHORT left, IN USHORT right); +void SRCMGR_SetPassThruVolume (allegro_devc * devc, IN PPASSTHRU client, + IN USHORT left, IN USHORT right); +void SRCMGR_SetPassThruRearVolume (allegro_devc * devc, IN PPASSTHRU client, + IN USHORT left, IN USHORT right); +/*#include "src3pbc.h" */ +short SRC3_PB_COEFF_HALF[5][666] = { + + +#if 0 + /* src3.5 44.1 khz */ + {0, -1, 2, -6, 13, -26, 48, -83, 135, -212, 326, -497, 776, -1325, 3084, + 15636, -2172, 1090, -665, 431, -283, 183, -115, 70, -40, 21, -10, 4, -2, 0, + 0, -1, 4, -9, 20, -40, 72, -122, 199, -311, 477, -728, 1142, -1975, 4859, + 14731, -2854, 1472, -906, 588, -386, 250, -157, 94, -54, 28, -14, 6, -2, 0, + 0, -1, 5, -12, 26, -51, 92, -156, 253, -395, 605, -924, 1456, -2555, 6712, + 13518, -3263, 1725, -1069, 696, -456, 294, -184, 111, -63, 33, -16, 7, -2, + 1, 0, -2, 6, -14, 31, -60, 108, -182, 293, -457, 699, -1068, 1692, -3017, + 8574, 12046, -3408, 1842, -1149, 749, -491, 316, -197, 118, -66, 35, -16, + 7, -2, 1, 0, -2, 6, -16, 34, -65, 117, -196, 315, -490, 749, -1147, 1827, + -3315, 10376, 10376, -3315, 1827, -1147, 749, -490, 315, -196, 117, -65, + 34, -16, 6, -2, 0, 1, -2, 7, -16, 35, -66, 118, -197, 316, -491, 749, + -1149, 1842, -3408, 12046, 8574, -3017, 1692, -1068, 699, -457, 293, -182, + 108, -60, 31, -14, 6, -2, 0, 1, -2, 7, -16, 33, -63, 111, -184, 294, -456, + 696, -1069, 1725, -3263, 13518, 6712, -2555, 1456, -924, 605, -395, 253, + -156, 92, -51, 26, -12, 5, -1, 0, 0, -2, 6, -14, 28, -54, 94, -157, 250, + -386, 588, -906, 1472, -2854, 14731, 4859, -1975, 1142, -728, 477, -311, + 199, -122, 72, -40, 20, -9, 4, -1, 0, 0, -2, 4, -10, 21, -40, 70, -115, + 183, -283, 431, -665, 1090, -2172, 15636, 3084, -1325, 776, -497, 326, + -212, 135, -83, 48, -26, 13, -6, 2, -1, 0, 0, -1, 2, -6, 12, -22, 38, -62, + 98, -152, 231, -358, 591, -1215, 16195, 1447, -652, 386, -248, 163, -106, + 67, -41, 24, -13, 6, -3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 16384, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, -3, 6, -13, + 24, -41, 67, -106, 163, -248, 386, -652, 1447, 16195, -1215, 591, -358, + 231, -152, 98, -62, 38, -22, 12, -6, 2, -1, 0}, +#else /* if */ /* src3.6 44.1 khz */ + {0, + -2, + 9, + -30, + 78, + -176, + 364, + -743, + 1859, + 16060, + -1459, + 633, + -312, + 149, + -64, + 23, + -7, + 1, + 0, + -4, + 17, + -54, + 141, + -315, + 647, + -1329, + 3466, + 15404, + -2260, + 1004, + -495, + 235, + -100, + 36, + -10, + 2, + 0, + -5, + 25, + -79, + 202, + -448, + 918, + -1897, + 5200, + 14423, + -2803, + 1269, + -627, + 296, + -125, + 44, + -12, + 2, + 1, + -8, + 33, + -102, + 258, + -566, + 1156, + -2406, + 7004, + 13158, + -3095, + 1425, + -703, + 330, + -137, + 47, + -12, + 2, + 1, + -9, + 40, + -122, + 302, + -658, + 1339, + -2813, + 8814, + 11661, + -3154, + 1473, + -726, + 338, + -139, + 47, + -12, + 2, + 1, + -11, + 45, + -135, + 330, + -714, + 1449, + -3077, + 10563, + 9991, + -3008, + 1422, + -700, + 323, + -131, + 44, + -11, + 1, + 2, + -12, + 48, + -139, + 338, + -724, + 1469, + -3158, + 12182, + 8215, + -2692, + 1285, + -631, + 289, + -116, + 38, + -9, + 1, + 2, + -12, + 47, + -134, + 321, + -684, + 1385, + -3024, + 13609, + 6399, + -2245, + 1081, + -529, + 240, + -95, + 30, + -7, + 1, + 2, + -11, + 42, + -118, + 278, + -589, + 1193, + -2650, + 14784, + 4611, + -1712, + 830, + -405, + 182, + -71, + 22, + -5, + 0, + 2, + -9, + 32, + -90, + 209, + -440, + 891, + -2021, + 15660, + 2913, + -1133, + 553, + -269, + 120, + -46, + 14, + -3, + 0, + 1, + -5, + 18, + -50, + 115, + -241, + 488, + -1135, + 16201, + 1361, + -551, + 270, + -131, + 58, + -22, + 7, + -1, + 0, + -0, + 0, + -0, + 0, + -0, + 0, + -0, + 0, + 16384, + 0, + -0, + 0, + -0, + 0, + -0, + 0, + -0, + 0, + 0, + -1, + 7, + -22, + 58, + -131, + 270, + -551, + 1361, + 16201, + -1135, + 488, + -241, + 115, + -50, + 18, + -5, + 1, + 0, + -3, + 14, + -46, + 120, + -269, + 553, + -1133, + 2913, + 15660, + -2021, + 891, + -440, + 209, + -90, + 32, + -9, + 2, + 0, + -5, + 22, + -71, + 182, + -405, + 830, + -1712, + 4611, + 14784, + -2650, + 1193, + -589, + 278, + -118, + 42, + -11, + 2, + 1, + -7, + 30, + -95, + 240, + -529, + 1081, + -2245, + 6399, + 13609, + -3024, + 1385, + -684, + 321, + -134, + 47, + -12, + 2, + 1, + -9, + 38, + -116, + 289, + -631, + 1285, + -2692, + 8215, + 12182, + -3158, + 1469, + -724, + 338, + -139, + 48, + -12, + 2, + 1, + -11, + 44, + -131, + 323, + -700, + 1422, + -3008, + 9991, + 10563, + -3077, + 1449, + -714, + 330, + -135, + 45, + -11, + 1, + 2, + -12, + 47, + -139, + 338, + -726, + 1473, + -3154, + 11661, + 8814, + -2813, + 1339, + -658, + 302, + -122, + 40, + -9, + 1, + 2, + -12, + 47, + -137, + 330, + -703, + 1425, + -3095, + 13158, + 7004, + -2406, + 1156, + -566, + 258, + -102, + 33, + -8, + 1, + 2, + -12, + 44, + -125, + 296, + -627, + 1269, + -2803, + 14423, + 5200, + -1897, + 918, + -448, + 202, + -79, + 25, + -5, + 0, + 2, + -10, + 36, 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-10, + 42, + -127, + 314, + -681, + 1385, + -2919, + 9407, + 11120, + -3126, + 1466, + -723, + 335, + -137, + 46, + -11, + 1, + 1, + -11, + 46, + -137, + 335, + -723, + 1466, + -3126, + 11120, + 9407, + -2919, + 1385, + -681, + 314, + -127, + 42, + -10, + 1, + 2, + -12, + 48, + -139, + 335, + -717, + 1453, + -3139, + 12682, + 7610, + -2555, + 1224, + -600, + 274, + -109, + 35, + -8, + 1, + 2, + -12, + 46, + -130, + 310, + -658, + 1333, + -2927, + 14031, + 5797, + -2075, + 1002, + -490, + 222, + -87, + 28, + -6, + 1, + 2, + -11, + 39, + -110, + 258, + -545, + 1104, + -2469, + 15111, + 4032, + -1522, + 740, + -360, + 162, + -63, + 19, + -4, + 0, + 1, + -8, + 28, + -78, + 181, + -379, + 768, + -1754, + 15879, + 2377, + -938, + 458, + -222, + 99, + -38, + 11, + -2, + 0, + 1, + -4, + 13, + -34, + 79, + -165, + 334, + -783, + 16303, + 884, + -362, + 178, + -86, + 38, + -14, + 4, + -1, + 0, + 0, + -0, + 2, + -7, + 18, + -42, + 87, + -178, + 430, + 16364, + -405, + 171, + -84, + 40, + -18, + 7, + -2, + 0, + }, + + +#endif +/* 32khz */ + {-1, + 8, + -31, + 85, + -198, + 410, + -788, + 1490, + -3112, + 13478, + 6633, + -2373, + 1202, + -637, + 325, + -151, + 62, + -21, + 5, + -1, + 0, + -0, + 0, + -0, + 0, + -0, + 0, + -0, + 0, + 16384, + 0, + -0, + 0, + -0, + 0, + -0, + 0, + -0, + 0, + -0, + -1, + 5, + -21, + 62, + -151, + 325, + -637, + 1202, + -2373, + 6633, + 13478, + -3112, + 1490, + -788, + 410, + -198, + 85, + -31, + 8, + -1, + }, + +#if 0 /* src3.6 */ +/* 22.05 khz */ + {1, -4, 11, -29, 63, -124, 226, -387, 639, -1039, 1741, -3337, 12626, 7840, + -2805, 1536, -928, 570, -343, 198, -107, 53, -24, 9, -3, 0, 0, -1, 3, -10, + 22, -46, 86, -151, 253, -412, 677, -1192, 2807, 15743, -2023, 987, -579, + 355, -217, 128, -71, 37, -17, 7, -2, 1, 1, -3, 11, -27, 59, -115, 208, + -355, 584, -950, 1600, -3128, 13912, 6117, -2340, 1298, -787, 483, -290, + 167, -90, 44, -19, 7, -2, 0, 0, -1, 5, -15, 34, -69, 128, -224, 375, -611, + 1005, -1790, 4422, 14964, -2693, 1347, -795, 488, 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9537, -3148, + 1699, -1023, 629, -380, 220, -120, 60, -27, 10, -3, 1, 0, 0, 2, -5, 11, + -22, 42, -75, 125, -205, 335, -585, 1320, 16222, -1122, 532, -310, 190, + -116, 69, -39, 20, -10, 4, -1, 0}, +#else /* src3.7 */ + {2, + -12, + 47, + -139, + 338, + -726, + 1473, + -3154, + 11661, + 8814, + -2813, + 1339, + -658, + 302, + -122, + 40, + -9, + 1, + 0, + -2, + 9, + -30, + 78, + -176, + 364, + -743, + 1859, + 16060, + -1459, + 633, + -312, + 149, + -64, + 23, + -7, + 1, + 2, + -12, + 47, + -137, + 330, + -703, + 1425, + -3095, + 13158, + 7004, + -2406, + 1156, + -566, + 258, + -102, + 33, + -8, + 1, + 0, + -4, + 17, + -54, + 141, + -315, + 647, + -1329, + 3466, + 15404, + -2260, + 1004, + -495, + 235, + -100, + 36, + -10, + 2, + 2, + -12, + 44, + -125, + 296, + -627, + 1269, + -2803, + 14423, + 5200, + -1897, + 918, + -448, + 202, + -79, + 25, + -5, + 0, + 0, + -5, + 25, + -79, + 202, + -448, + 918, + -1897, + 5200, + 14423, + -2803, + 1269, + -627, + 296, + -125, + 44, + -12, + 2, + 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-7, 19, -43, 89, -169, 303, -529, 947, -1999, 15740, 2789, -1157, + 629, -360, 204, -110, 55, -25, 10, -3, 1, 0, 0, 0, -1, 3, -11, 31, -73, + 153, -296, 535, -937, 1655, -3280, 12609, 7814, -2740, 1444, -824, 469, + -256, 130, -61, 25, -9, 3, 0, 0, 0, 0, 3, -9, 25, -61, 130, -256, 469, + -824, 1444, -2740, 7814, 12609, -3280, 1655, -937, 535, -296, 153, -73, 31, + -11, 3, -1, 0, 0, 0, 1, -3, 10, -25, 55, -110, 204, -360, 629, -1157, 2789, + 15740, -1999, 947, -529, 303, -169, 89, -43, 19, -7, 2, -1, 0, 0, 0, 1, -4, + 11, -24, 48, -91, 163, -285, 512, -1110, 16221, 1310, -566, 310, -178, 100, + -54, 27, -12, 5, -2, 0, 0, 0, 0, -1, 3, -11, 29, -68, 142, -273, 492, -860, + 1525, -3081, 13900, 6091, -2281, 1216, -695, 395, -214, 109, -50, 21, -7, + 2, 0, 0, 0, -1, 3, -10, 29, -69, 146, -285, 520, -913, 1604, -3082, 9512, + 11129, -3273, 1678, -953, 544, -299, 154, -73, 31, -11, 3, -1, 0, 0, 0, 1, + -5, 15, -38, 83, -164, 304, -537, 938, -1740, 4398, 14957, -2657, 1288, + -724, 414, -231, 121, -58, 25, -10, 3, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 16384, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1, 3, -10, 25, -58, + 121, -231, 414, -724, 1288, -2657, 14957, 4398, -1740, 938, -537, 304, + -164, 83, -38, 15, -5, 1, 0, 0, 0, -1, 3, -11, 31, -73, 154, -299, 544, + -953, 1678, -3273, 11129, 9512, -3082, 1604, -913, 520, -285, 146, -69, 29, + -10, 3, -1, 0, 0, 0, 2, -7, 21, -50, 109, -214, 395, -695, 1216, -2281, + 6091, 13900, -3081, 1525, -860, 492, -273, 142, -68, 29, -11, 3, -1, 0, 0, + 0, 0, -2, 5, -12, 27, -54, 100, -178, 310, -566, 1310, 16221, -1110, 512, + -285, 163, -91, 48, -24, 11, -4, 1, 0, 0}, + + + /* 8khz */ + + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 16384, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, -1, 2, -4, 6, -8, 11, -16, 21, + -28, 36, -47, 60, -76, 95, -118, 146, -181, 223, -277, 345, -438, 571, + -781, 1174, -2219, 15643, 3118, -1397, 882, -629, 477, -373, 297, -240, + 194, -157, 127, -102, 82, -65, 51, -40, 30, -23, 17, -13, 9, -6, 4, -3, 2, + -1, 1, 0, 0, 0, 0, 0, -1, 1, -2, 4, -6, 9, -13, 18, -26, 35, -46, 60, -78, + 100, -126, 159, -198, 245, -302, 373, -462, 576, -728, 944, -1278, 1881, + -3356, 13542, 6759, -2670, 1631, -1147, 862, -672, 535, -430, 348, -282, + 228, -184, 147, -117, 92, -72, 55, -42, 31, -23, 16, -12, 8, -5, 3, -2, 1, + -1, 0, 0, 0, 0, -1, 1, -3, 4, -6, 10, -14, 20, -28, 38, -51, 67, -87, 111, + -140, 176, -220, 273, -337, 416, -515, 641, -807, 1041, -1397, 2018, -3436, + 10417, 10417, -3436, 2018, -1397, 1041, -807, 641, -515, 416, -337, 273, + -220, 176, -140, 111, -87, 67, -51, 38, -28, 20, -14, 10, -6, 4, -3, 1, -1, + 0, 0, 0, 0, -1, 1, -2, 3, -5, 8, -12, 16, -23, 31, -42, 55, -72, 92, -117, + 147, -184, 228, -282, 348, -430, 535, -672, 862, -1147, 1631, -2670, 6759, + 13542, -3356, 1881, -1278, 944, -728, 576, -462, 373, -302, 245, -198, 159, + -126, 100, -78, 60, -46, 35, -26, 18, -13, 9, -6, 4, -2, 1, -1, 0, 0, 0, 0, + 0, 1, -1, 2, -3, 4, -6, 9, -13, 17, -23, 30, -40, 51, -65, 82, -102, 127, + -157, 194, -240, 297, -373, 477, -629, 882, -1397, 3118, 15643, -2219, + 1174, -781, 571, -438, 345, -277, 223, -181, 146, -118, 95, -76, 60, -47, + 36, -28, 21, -16, 11, -8, 6, -4, 2, -1, 1, 0, 0, 0} +}; + +/*#include "src3rec.h" */ +#define REDUCED_FILTER 1 + +#if REDUCED_FILTER +/*short SRC3_REC_COEFF_HALF[4][313] = { */ +short SRC3_REC_COEFF_HALF[5][680] = { +#else /* if */ +short SRC3_REC_COEFF_HALF[4][528] = { +#endif + +#if REDUCED_FILTER + +#if 1 /* Higher Sampling Rate Acuracy for 44.1khz */ + {2, + -11, + 44, + -126, + 288, + -552, + 921, + -1398, + 2184, + 14981, + 395, + -683, + 594, + -412, + 237, + -112, + 42, + -11, + 2, + 0, + 2, + -11, + 43, + -117, + 252, + -450, + 680, + -862, + 812, + 15037, + 1708, + -1221, + 843, + -520, + 278, + -124, + 44, + -11, + 2, + 0, + 2, + -11, + 39, + -101, + 204, + -331, + 421, + -333, + -372, + 14758, + 3185, + -1743, + 1062, + -605, + 303, + -128, + 43, + -10, + 1, + 0, + 1, + -9, + 33, + -80, + 149, + -204, + 163, + 157, + -1340, + 14155, + 4778, + -2211, + 1231, + -656, + 310, + -123, + 38, + -8, + 1, + 0, + 1, + -8, + 25, + -58, + 91, + -79, + -77, + 582, + -2077, + 13254, + 6436, + -2585, + 1332, + -666, + 295, + -108, + 30, + -5, + -0, + 0, + 1, + -6, + 18, + -35, + 35, + 37, + -287, + 922, + -2576, + 12092, + 8100, + -2828, + 1350, + -629, + 256, + -82, + 17, + 0, + -1, + 0, + 1, + -4, + 11, + -13, + -16, + 137, + -455, + 1166, + -2844, + 10715, + 9706, + -2902, + 1273, + -541, + 192, + -46, + -0, + 6, + -3, + 0, + 0, + -2, + 4, + 6, + -59, + 216, + -576, + 1309, + -2898, + 9181, + 11195, + -2779, + 1096, + -404, + 106, + 0, + -20, + 13, + -4, + 1, + 0, + -1, + -2, + 22, + -92, + 272, + -646, + 1354, + -2764, + 7548, + 12505, + -2435, + 819, + -221, + -0, + 53, + -42, + 20, + -6, + 1, + 0, + 0, + -6, + 33, + -114, + 303, + -667, + 1307, + -2473, + 5880, + 13585, + -1858, + 449, + 0, + -120, + 110, + -65, + 28, + -8, + 1, + 1, + -9, + 40, + -126, + 310, + -643, + 1181, + -2063, + 4237, + 14391, + -1043, + -0, + 248, + -247, + 167, + -87, + 35, + -10, + 1, + 0, + 1, + -11, + 44, + -128, + 297, + -580, + 994, + -1573, + 2677, + 14888, + 0, + -506, + 508, + -372, + 221, + -106, + 40, + -11, + 2, + 0, + 2, + -11, + 43, + -121, + 265, + -487, + 763, + -1041, + 1251, + 15056, + 1251, + -1041, + 763, + -487, + 265, + -121, + 43, + -11, + 2, + 0, + 2, + -11, + 40, + -106, + 221, + -372, + 508, + -506, + 0, + 14888, + 2677, + -1573, + 994, + -580, + 297, + -128, + 44, + -11, + 1, + 0, + 1, + -10, + 35, + -87, + 167, + -247, + 248, + -0, + -1043, + 14391, + 4237, + -2063, + 1181, + -643, + 310, + -126, + 40, + -9, + 1, + 0, + 1, + -8, + 28, + -65, + 110, + -120, + 0, + 449, + -1858, + 13585, + 5880, + -2473, + 1307, + -667, + 303, + -114, + 33, + -6, + 0, + 0, + 1, + -6, + 20, + -42, + 53, + -0, + -221, + 819, + -2435, + 12505, + 7548, + -2764, + 1354, + -646, + 272, + -92, + 22, + -2, + -1, + 0, + 1, + -4, + 13, + -20, + 0, + 106, + -404, + 1096, + -2779, + 11195, + 9181, + -2898, + 1309, + -576, + 216, + -59, + 6, + 4, + -2, + 0, + 0, + -3, + 6, + -0, + -46, + 192, + -541, + 1273, + -2902, + 9706, + 10715, + -2844, + 1166, + -455, + 137, + -16, + -13, + 11, + -4, + 1, + 0, + -1, + 0, + 17, + -82, + 256, + -629, + 1350, + -2828, + 8100, + 12092, + -2576, + 922, + -287, + 37, + 35, + -35, + 18, + -6, + 1, + 0, + -0, + -5, + 30, + -108, + 295, + -666, + 1332, + -2585, + 6436, + 13254, + -2077, + 582, + -77, + -79, + 91, + -58, + 25, + -8, + 1, + 1, + -8, + 38, + -123, + 310, + -656, + 1231, + -2211, + 4778, + 14155, + -1340, + 157, + 163, + -204, + 149, + -80, + 33, + -9, + 1, + 0, + 1, + -10, + 43, + -128, + 303, + -605, + 1062, + -1743, + 3185, + 14758, + -372, + -333, + 421, + -331, + 204, + -101, + 39, + -11, + 2, + 0, + 2, + -11, + 44, + -124, + 278, + -520, + 843, + -1221, + 1708, + 15037, + 812, + -862, + 680, + -450, + 252, + -117, + 43, + -11, + 2, + 0, + 2, + -11, + 42, + -112, + 237, + -412, + 594, + -683, + 395, + 14981, + 2184, + -1398, + 921, + -552, + 288, + -126, + 44, + -11, + 2, + 0, + 2, + -10, + 37, + -94, + 186, + -289, + 334, + -164, + -720, + 14592, + 3705, + -1907, + 1125, + -626, + 308, + -128, + 42, + -10, + 1, + 0, + 1, + -9, + 30, + -73, + 129, + -162, + 80, + 307, + -1612, + 13886, + 5327, + -2348, + 1273, + -664, + 308, + -120, + 36, + -7, + 1, + 0, + 1, + -7, + 23, + -50, + 72, + -39, + -151, + 705, + -2269, + 12893, + 6993, + -2683, + 1348, + -659, + 285, + -101, + 26, + -3, + -0, + 0, + 1, + -5, + 15, + -27, + 17, + 73, + -348, + 1015, + -2690, + 11654, + 8645, + -2873, + 1335, + -605, + 237, + -71, + 12, + 2, + -2, + 0, + 0, + -3, + 8, + -6, + -31, + 166, + -501, + 1225, + -2885, + 10219, + 10219, + -2885, + 1225, + -501, + 166, + -31, + -6, + 8, + -3, + 0, + 0, + -2, + 2, + 12, + -71, + 237, + -605, + 1335, + -2873, + 8645, + 11654, + -2690, + 1015, + -348, + 73, + 17, + -27, + 15, + -5, + 1, + 0, + -0, + -3, + 26, + -101, + 285, + -659, + 1348, + -2683, + 6993, + 12893, + -2269, + 705, + -151, + -39, + 72, + -50, + 23, + -7, + 1, + 0, + 1, + -7, + 36, + -120, + 308, + -664, + 1273, + -2348, + 5327, + 13886, + -1612, + 307, + 80, + -162, + 129, + -73, + 30, + -9, + 1, + 1, + -10, + 42, + -128, + 308, + -626, + 1125, + -1907, + 3705, + 14592, + -720, + -164, + 334, + -289, + 186, + -94, + 37, + -10, + 2, + 0, + }, + +#else /* if */ /* Less Acurate for 44.1khz */ + {1, -5, 19, -53, 119, -224, 363, -511, 613, -558, 0, 14844, 2791, -1712, + 1170, -769, 464, -250, 117, -45, 13, -2, 0, 0, 1, -6, 20, -51, 108, -189, + 282, -344, 302, 0, -1091, 14326, 4409, -2226, 1371, -835, 472, -237, 102, + -34, 7, 0, -1, 0, 1, -6, 18, -46, 90, -146, 189, -170, 0, 500, -1942, + 13488, 6103, -2642, 1492, -846, 444, -205, 77, -19, 0, 3, -1, 0, 1, -5, 16, + -38, 69, -97, 93, 0, -274, 916, -2543, 12366, 7811, -2917, 1516, -796, 381, + -153, 42, 0, -9, 6, -2, 0, 1, -4, 13, -29, 46, -48, 0, 154, -505, 1230, + -2895, 11007, 9468, -3012, 1430, -681, 283, -83, 0, 22, -19, 10, -3, 1, 1, + -3, 10, -19, 22, 0, -83, 283, -681, 1430, -3012, 9468, 11007, -2895, 1230, + -505, 154, 0, -48, 46, -29, 13, -4, 1, 0, -2, 6, -9, 0, 42, -153, 381, + -796, 1516, -2917, 7811, 12366, -2543, 916, -274, 0, 93, -97, 69, -38, 16, + -5, 1, 0, -1, 3, 0, -19, 77, -205, 444, -846, 1492, -2642, 6103, 13488, + -1942, 500, 0, -170, 189, -146, 90, -46, 18, -6, 1, 0, -1, 0, 7, -34, 102, + -237, 472, -835, 1371, -2226, 4409, 14326, -1091, 0, 302, -344, 282, -189, + 108, -51, 20, -6, 1, 0, 0, -2, 13, -45, 117, -250, 464, -769, 1170, -1712, + 2791, 14844, 0, -558, 613, -511, 363, -224, 119, -53, 19, -5, 1, 0, -4, 17, + -51, 123, -245, 426, -657, 910, -1142, 1306, 15019, 1306, -1142, 910, -657, + 426, -245, 123, -51, 17, -4, 0, 0}, +#endif + +#else /* if */ /* not reduced 44k filter */ + {0, 1, -2, 4, -7, 11, -16, 20, -21, 16, 0, -31, 81, -152, 245, -358, 482, + -606, 715, -785, 780, -623, 0, 14847, 2849, -1874, 1448, -1135, 869, -637, + 438, -275, 149, -59, 0, 33, -46, 46, -39, 30, -20, 12, -7, 3, -1, 0, 0, 0, + 0, 1, -2, 4, -6, 10, -13, 14, -11, 0, 22, -58, 111, -182, 267, -361, 454, + -531, 569, -539, 390, 0, -1129, 14338, 4482, -2417, 1674, -1210, 862, -585, + 366, -199, 79, 0, -45, 65, -67, 59, -46, 32, -20, 11, -6, 2, -1, 0, 0, 0, + 0, 1, -2, 3, -5, 8, -9, 7, 0, -15, 41, -80, 132, -197, 270, -341, 398, + -423, 392, -272, 0, 569, -2022, 13513, 6183, -2846, 1798, -1205, 793, -490, + 265, -105, 0, 62, -90, 94, -84, 67, -49, 32, -19, 10, -4, 1, 0, 0, 0, 0, 0, + 1, -2, 3, -4, 5, -4, 0, 10, -28, 56, -95, 144, -199, 254, -298, 317, -292, + 198, 0, -365, 1053, -2663, 12407, 7890, -3117, 1804, -1113, 665, -355, 141, + 0, -83, 122, -130, 119, -97, 72, -49, 30, -16, 7, -2, 0, 1, -1, 0, 0, 0, 1, + -1, 2, -3, 3, 0, -6, 18, -38, 66, -103, 145, -187, 222, -238, 219, -147, 0, + 257, -684, 1430, -3051, 11064, 9538, -3196, 1682, -937, 483, -188, 0, 111, + -164, 177, -164, 136, -103, 72, -45, 25, -12, 4, 0, -1, 1, -1, 0, 0, 0, 0, + -1, 1, -1, 0, 4, -12, 25, -45, 72, -103, 136, -164, 177, -164, 111, 0, + -188, 483, -937, 1682, -3196, 9538, 11064, -3051, 1430, -684, 257, 0, -147, + 219, -238, 222, -187, 145, -103, 66, -38, 18, -6, 0, 3, -3, 2, -1, 1, 0, 0, + 0, -1, 1, 0, -2, 7, -16, 30, -49, 72, -97, 119, -130, 122, -83, 0, 141, + -355, 665, -1113, 1804, -3117, 7890, 12407, -2663, 1053, -365, 0, 198, + -292, 317, -298, 254, -199, 144, -95, 56, -28, 10, 0, -4, 5, -4, 3, -2, 1, + 0, 0, 0, 0, 0, 1, -4, 10, -19, 32, -49, 67, -84, 94, -90, 62, 0, -105, 265, + -490, 793, -1205, 1798, -2846, 6183, 13513, -2022, 569, 0, -272, 392, -423, + 398, -341, 270, -197, 132, -80, 41, -15, 0, 7, -9, 8, -5, 3, -2, 1, 0, 0, + 0, 0, -1, 2, -6, 11, -20, 32, -46, 59, -67, 65, -45, 0, 79, -199, 366, + -585, 862, -1210, 1674, -2417, 4482, 14338, -1129, 0, 390, -539, 569, -531, + 454, -361, 267, -182, 111, -58, 22, 0, -11, 14, -13, 10, -6, 4, -2, 1, 0, + 0, 0, 0, -1, 3, -7, 12, -20, 30, -39, 46, -46, 33, 0, -59, 149, -275, 438, + -637, 869, -1135, 1448, -1874, 2849, 14847, 0, -623, 780, -785, 715, -606, + 482, -358, 245, -152, 81, -31, 0, 16, -21, 20, -16, 11, -7, 4, -2, 1, 0, 0, + 0, -1, 4, -7, 12, -19, 26, -31, 32, -23, 0, 43, -110, 205, -328, 477, -643, + 818, -989, 1141, -1261, 1339, 15019, 1339, -1261, 1141, -989, 818, -643, + 477, -328, 205, -110, 43, 0, -23, 32, -31, 26, -19, 12, -7, 4, -1, 0, 0, + 0}, + +#endif +/* 32k */ + {-0, + 0, + 6, + -14, + 0, + 57, + -101, + 0, + 273, + -425, + 0, + 993, + -1582, + 0, + 8985, + 8985, + 0, + -1582, + 993, + 0, + -425, + 273, + 0, + -101, + 57, + 0, + -14, + 6, + 0, + -0, + -1, + 3, + -0, + -20, + 41, + -0, + -132, + 216, + -0, + -526, + 801, + -0, + -2075, + 4422, + 10923, + 4422, + -2075, + -0, + 801, + -526, + -0, + 216, + -132, + -0, + 41, + -20, + -0, + 3, + -1, + -0, + }, + + +/* 22k */ + {0, 0, 1, 2, -3, -7, 6, 19, -7, -42, 0, 80, 26, -134, -87, 199, 205, -262, + -415, 300, 781, -265, -1523, 0, 4395, 7487, 5823, 1291, -1432, -813, 607, + 578, -254, -401, 80, 261, 0, -155, -28, 83, 30, -39, -22, 15, 12, -4, -6, + 1, 2, 0, 0, 0, 0, 0, 1, 2, -2, -7, 3, 18, 0, -39, -13, 71, 48, -112, -119, + 154, 245, -176, -453, 148, 793, 0, -1436, -515, 3612, 7265, 6418, 2035, + -1234, -1065, 445, 685, -136, -443, 0, 272, 51, -153, -58, 77, 46, -33, + -29, 11, 15, -2, -6, 0, 2, 0, 0, 0, 0, 0, 1, 2, -1, -7, 0, 17, 6, -35, -24, + 60, 65, -86, -141, 103, 267, -87, -461, 0, 760, 240, -1278, -928, 2816, + 6904, 6904, 2816, -928, -1278, 240, 760, 0, -461, -87, 267, 103, -141, -86, + 65, 60, -24, -35, 6, 17, 0, -7, -1, 2, 1, 0, 0, 0, 0, 0, 2, 0, -6, -2, 15, + 11, -29, -33, 46, 77, -58, -153, 51, 272, 0, -443, -136, 685, 445, -1065, + -1234, 2035, 6418, 7265, 3612, -515, -1436, 0, 793, 148, -453, -176, 245, + 154, -119, -112, 48, 71, -13, -39, 0, 18, 3, -7, -2, 2, 1, 0, 0, 0, 0, 0, + 2, 1, -6, -4, 12, 15, -22, -39, 30, 83, -28, -155, 0, 261, 80, -401, -254, + 578, 607, -813, -1432, 1291, 5823, 7487, 4395, 0, -1523, -265, 781, 300, + -415, -262, 205, 199, -87, -134, 26, 80, 0, -42, -7, 19, 6, -7, -3, 2, 1, + 0, 0, 0, 0, 2, 1, -4, -6, 9, 17, -14, -41, 15, 84, 0, -148, -47, 235, 150, + -339, -348, 446, 719, -541, -1526, 607, 5141, 7562, 5141, 607, -1526, -541, + 719, 446, -348, -339, 150, 235, -47, -148, 0, 84, 15, -41, -14, 17, 9, -6, + -4, 1, 2, 0, 0, 0}, + +/* 11k */ + {0, -1, -1, -1, 1, 6, 12, 12, 0, -26, -55, -63, -25, 63, 167, 216, 138, -91, + -398, -614, -530, 0, 959, 2135, 3179, 3741, 3624, 2869, 1739, 601, -229, + -603, -566, -296, 0, 182, 211, 135, 30, -43, -64, -46, -16, 6, 13, 10, 4, + 0, -1, -1, 0, 0, 0, 0, -1, -1, 0, 4, 10, 13, 6, -16, -46, -64, -43, 30, + 135, 211, 182, 0, -296, -566, -603, -229, 601, 1739, 2869, 3624, 3741, + 3179, 2135, 959, 0, -530, -614, -398, -91, 138, 216, 167, 63, -25, -63, + -55, -26, 0, 12, 12, 6, 1, -1, -1, -1, 0, 0, -1, -1, -1, 3, 8, 13, 10, -7, + -36, -61, -56, 0, 99, 194, 207, 77, -191, -491, -629, -406, 279, 1343, + 2517, 3434, 3781, 3434, 2517, 1343, 279, -406, -629, -491, -191, 77, 207, + 194, 99, 0, -56, -61, -36, -7, 10, 13, 8, 3, -1, -1, -1, 0, 0}, + + +/* 8k */ + {0, 1, 1, 2, 2, 0, -4, -10, -17, -21, -16, 0, 29, 66, 98, 108, 79, 0, -123, + -263, -375, -401, -287, 0, 457, 1037, 1658, 2211, 2594, 2731, 2594, 2211, + 1658, 1037, 457, 0, -287, -401, -375, -263, -123, 0, 79, 108, 98, 66, 29, + 0, -16, -21, -17, -10, -4, 0, 2, 2, 1, 1, 0, 0} +}; + + +/*#include "minisrc.h" */ +/* warning!! warning!! warning!! warning!! warning!! warning!! warning!!*/ + +/* You really have to watch out "the order of IIR coefficients"!!!!!! */ +/* the order is : b2, b1, b0, -a2, -a1 */ + +/*#define MINISRC_BIQUAD_STAGE 2 */ + +#if 1 +WORD MINISRC_LPF[10] = { + 0X0743, + 0X1104, + 0X0A4C, + 0XF88D, + 0X242C, + + 0X1023, + 0X1AA9, + 0X0B60, + 0XEFDD, + 0X186F +}; + +#else +WORD MINISRC_LPF[10] = { + 0x01B7, + 0XF632, + 0X0BE4, + 0XDC94, + 0X2D03, + + 0X3748, + 0X938D, + 0X5887, + 0XC7F9, + 0X6D75 +}; +#endif +/*#include "msrcsize.h" */ +#ifndef __MSRCSIZE +#define __MSRCSIZE + +#define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 ) +#define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2) +#define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 ) +#define MINISRC_BIQUAD_STAGE 2 +/* M. SRC LPF coefficient could be changed in the DSP code */ +#define MINISRC_COEF_LOC 0X175 + + +#endif + +#endif diff --git a/attic/drv/oss_allegro/srcmgr.inc b/attic/drv/oss_allegro/srcmgr.inc new file mode 100644 index 0000000..c1a3b93 --- /dev/null +++ b/attic/drv/oss_allegro/srcmgr.inc @@ -0,0 +1,1338 @@ +/* + * srcmgr.c -- ESS Technology allegro audio driver. + * + * Copyright (C) 1992-2000 Don Kim (don.kim@esstech.com) + * + */ + +#include "hckernel.h" +static int num_errors = 0; /* Dummy variable used to supress lint warnings. */ + +#define DMAREC + +/*/////////////////////////////////////////////////////////////////////////// */ +/* DSP kernel support */ +/* index 0 - 44.1k; 1 - 32k; 2 - 22.05k; 3 - 11.025k; 4 - 8k */ +/* */ +/*/////////////////////////////////////////////////////////////////////////// */ +WORD gwSRC3_PB_SIZE_OUT[5] = + { 37 * 2 * 2, 6 * 2, 37 * 2 * 2, 26 * 2, 12 * 2 }; +WORD gwSRC3_PB_SIZE_IN[5] = { 34 * 2, 4, 17 * 2, 6, 2 }; +WORD gwSRC3_PB_FILTER_LENGTH[5] = { 666, 60, 666, 338, 360 }; +WORD gwSRC3_PB_FILTER_TAP_SIZE[5] = { 17, 19, 17, 25, 59 }; /* SIZE - 1 */ +WORD gwSRC3_PB_BIG_LOOP_COUNTER[5] = { 11, 1, 5, 2, 0 }; +WORD gwSRC3_PB_SMALL_LOOP_COUNTER[5] = { 0, 0, 1, 3, 4 }; +WORD gwSRC3_IN_BufferSize[5] = + { 2 * 17 * 16, 192 * 2, 2 * 17 * 16, 192 * 2, 192 * 2 }; +WORD gwSRC3_OUT_BufferSize[5] = + { 160 * 4, 160 * 2, 160 * 4, 160 * 2, 160 * 2 }; + +WORD gwSRC3_REC_SIZE_OUT[5] = { 34 * 2, 4, 12, 6, 2 }; +WORD gwSRC3_REC_SIZE_IN[5] = { 37 * 2, 6, 26, 26, 12 }; +WORD gwSRC3_REC_FILTER_LENGTH[5] = { 680, 60, 312, 156, 60 }; +WORD gwSRC3_REC_FILTER_TAP_SIZE[5] = { 19, 29, 51, 51, 59 }; /* SIZE - 1 */ + +/* WORD gwSRC3_REC_BIG_LOOP_COUNTER[5] = { 9, 0, 4, 1, -1 }; */ +WORD gwSRC3_REC_SMALL_LOOP_COUNTER[5] = { 0, 0, 1, 3, 4 }; +WORD gwSRC3_REC_IN_BufferSize[5] = { 37 * 16 * 2, 32 * 6 * 2, 416, 416, 384 }; +WORD gwSRC3_REC_OUT_BufferSize[5] = + { 160 * 4, 160 * 2, 160 * 2, 160 * 2, 160 * 2 }; + +#define PB_DMA_BUFFER_SIZE 0x2400 +#define PLAYBACK_BUFFER_SIZE PB_DMA_BUFFER_SIZE +/*#define WAVE_BUFFER_BLOCK_SIZE (MAXNUM_WAVE_RENDER * PLAYBACK_BUFFER_SIZE) + 0x8000 */ + +#define STREAM_TYPE_DSPSRC 1 /* high quality SRC stream */ +#define STREAM_TYPE_DSPMSRC 2 /* general mini SRC stream */ +#define STREAM_TYPE_NULL (( ULONG ) -1 ) + +BYTE AllocateSRCPlay = FALSE; +BYTE AllocateSRCRec = FALSE; +/* -------------------------------------------------------------------------- */ + +/* khs, for full-dupulex */ +#define MAX_SRC_STREAMS 2 + + +PHWI gphwi = NULL; + +#define _Debug_Printf_Service(x) dprintf3((x)) + +#if 0 +extern PHYSICAL_ADDRESS PPhysicalAddress; +extern PHYSICAL_ADDRESS RPhysicalAddress; +extern ULONG SWTAddress; +#endif + +#define wSPDIFVarLen (CDATA_HEADER_LEN + 10) +#define gwSPDIF_IN_BufferSize 192 +/* -------------------------------------------------------------------------- */ + +#define MAXNUM_WAVE_RENDER 1 +#define MAXNUM_WAVE_CAPTURE 1 +#define MAXNUM_WAVE_MIXER 1 +#define MAXNUM_WAVE_CHANNELS MAXNUM_WAVE_RENDER + MAXNUM_WAVE_CAPTURE + MAXNUM_WAVE_MIXER + + +ALLEGRO_WAVE WaveStreams[MAXNUM_WAVE_CHANNELS] = { {0} }; + +PALLEGRO_WAVE CaptureStream = NULL; +PALLEGRO_WAVE PlaybackStream = NULL; +PALLEGRO_WAVE MidiStream = NULL; + +MBUFFER CaptureBuffer; +MBUFFER RenderBuffer; +MBUFFER MidiBuffer; + +static int StreamsRunning = 0; + +void +InitStream () +{ + int i; + for (i = 0; i < 3; i++) + { + WaveStreams[i].PositionBeforePaused = 0; + WaveStreams[i].DspClientInstance = NULL; + WaveStreams[i].StreamType = STREAM_TYPE_NULL; + WaveStreams[i].State = KSSTATE_STOP; + } + + WaveStreams[0].WaveType = WAVE_PLAYBACK; + WaveStreams[1].WaveType = WAVE_CAPTURE; + WaveStreams[2].WaveType = WAVE_MIXER; + +#if 0 + RenderBuffer.Physical = (ULONG) PPhysicalAddress.LowPart; + RenderBuffer.Length = 0x2000; + WaveStreams[0].Buffer = &RenderBuffer; + WaveStreams[0].Length = RenderBuffer.Length; + + CaptureBuffer.Physical = (ULONG) RPhysicalAddress.LowPart; + CaptureBuffer.Length = 0x4000; + WaveStreams[1].Buffer = &CaptureBuffer; + WaveStreams[1].Length = CaptureBuffer.Length; + + MidiBuffer.Physical = (ULONG) SWTAddress; + MidiBuffer.Length = 3520; + WaveStreams[2].Buffer = &MidiBuffer; + WaveStreams[2].Length = MidiBuffer.Length; + WaveStreams[2].StreamType = STREAM_TYPE_DSPMSRC; +#endif + + PlaybackStream = &WaveStreams[0]; + CaptureStream = &WaveStreams[1]; + MidiStream = &WaveStreams[2]; +} + +/*ARGSUSED*/ +void +AllocateStream (allegro_devc * devc, IN BYTE waveType) +{ + dprintf1 (("AllocateStream %d", waveType)); + WaveStreams[waveType].DspClientInstance = NULL; + WaveStreams[waveType].StreamType = STREAM_TYPE_NULL; + WaveStreams[waveType].State = KSSTATE_STOP; + + /* */ + /* at the request of record, turn off SPDIF out if already on. */ + /* at the end of record, turn on */ +#ifdef later + if ((WAVE_CAPTURE == waveType) && fSPDIFOUT) + HWMGR_Enable_SPDIF (devc, FALSE); +#endif + +/* SetFormat( &WaveStreams[ waveType ], WaveInfo ); */ +} /* AllocateStream */ + +void +FreeStream (allegro_devc * devc, IN PALLEGRO_WAVE AllegroWave) +{ + /* close DSP instance */ + dprintf3 (("FreeStream:%x", AllegroWave->DspClientInstance)); + if (AllegroWave->DspClientInstance) + { + if (kCloseInstance (devc, gphwi, AllegroWave->DspClientInstance, + KOPENCLOSE_SYNCHRONOUS) != KRETURN_SUCCESS) + { + /*_Debug_Printf_Service( "Close Inst!\n" ); */ + dprintf1 (("ERROR: FreeStream kCloseInstance")); + num_errors++; + } + AllegroWave->DspClientInstance = NULL; + } + + if (IsAC3Format) + { + /* */ + /* reset the spdif out data type to PCM */ + HWMGR_WriteDataWord (devc, ASSP_MEMORY_PORT, DSP_DATA_MEMORY); + HWMGR_WriteDataWord (devc, ASSP_INDEX_PORT, KDATA_SPDIF_FRAME0); + HWMGR_WriteDataWord (devc, ASSP_DATA_PORT, 0x100); + } + + if (STREAM_TYPE_DSPSRC == AllegroWave->StreamType) + { + AllocateSRCRec = FALSE; + AllocateSRCPlay = FALSE; + } +} /* FreeStream */ + + +void +SRCMGR_Stop (allegro_devc * devc, IN PALLEGRO_WAVE AllegroWave) +{ + dprintf1 (("SRCMGR_Stop: Client = %x", AllegroWave->DspClientInstance)); + if (AllegroWave->DspClientInstance) + { + + /* stop DMA transfer */ + kStopTransfer (devc, gphwi, AllegroWave->DspClientInstance); + + /* stop the DSP client */ + kSetInstanceNotReady (devc, gphwi, AllegroWave->DspClientInstance); + } +} /* SRCMGR_Stop */ + +void +SRCMGR_StartSPDIFIN (allegro_devc * devc, IN BOOLEAN start) +{ + ULONG FilterLength; + ULONG i; + USHORT wCC_offset; + USHORT wCD_offset; + + if (start) + { + if (pClient_SPDIFIN) + { + kCloseInstance (devc, gphwi, pClient_SPDIFIN, + KOPENCLOSE_SYNCHRONOUS); + pClient_SPDIFIN = NULL; +#if 0 + StreamsRunning--; + if (0 == StreamsRunning) + { + WRITE_PORT_USHORT (devc->osdev, devc->base + HOST_INT_CTRL, + (USHORT) (READ_PORT_USHORT + (devc->osdev, + devc->base + + HOST_INT_CTRL) & + ~CLKRUN_GEN_ENABLE)); + } +#endif + } + kOpenInstance (devc, gphwi, + CLIENT_MINISRC, + 0, + 2 * (MINISRC_TMP_BUFFER_SIZE / 2 + + MINISRC_IN_BUFFER_SIZE / 2 + 1 + + MINISRC_OUT_BUFFER_SIZE / 2 + 1), &pClient_SPDIFIN); + if (pClient_SPDIFIN) + { +#if 0 + StreamsRunning++; + if (1 == StreamsRunning) + { + WRITE_PORT_USHORT (devc->osdev, devc->base + HOST_INT_CTRL, + (USHORT) (READ_PORT_USHORT + (devc->osdev, + devc->base + + HOST_INT_CTRL) | + CLKRUN_GEN_ENABLE)); + } +#endif + wCC_offset = (WORD) (pClient_SPDIFIN->dwDspCodeClientArea); + wCD_offset = (WORD) (pClient_SPDIFIN->dwDspDataClientArea); + + dprintf1 (("success %x %x %x", pClient_SPDIFIN, wCC_offset, + wCD_offset)); + kStartTransfer (devc, gphwi, pClient_SPDIFIN, TRUE, 0L, 0L, 0L, 0L, + (ULONG) (wCD_offset + MINISRC_TMP_BUFFER_SIZE / 2), + (ULONG) (MINISRC_IN_BUFFER_SIZE), + (ULONG) (wCD_offset + MINISRC_TMP_BUFFER_SIZE / 2 + + MINISRC_IN_BUFFER_SIZE / 2 + 1), + (ULONG) (MINISRC_OUT_BUFFER_SIZE), KCONNECT_SPDIFIN, + KCONNECT_MIXER); + + /* ------------------------------------------------------------------------- */ + /* load the coefficient starting at offset of program size in program memory */ + /* ------------------------------------------------------------------------- */ + + /* filter length calculation */ + FilterLength = sizeof (MINISRC_LPF) / 2; + + for (i = 0; i < FilterLength; i++) + { + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_CODE, wCC_offset + MINISRC_COEF_LOC + i, (USHORT) (MINISRC_LPF[i])); /*since it is in sequence. */ + } + + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_CODE, + wCC_offset + MINISRC_COEF_LOC + FilterLength, + 0X8000); + +/*------------------------------------------------------------------------------------------- */ +/* Transfer all parameters into DSP Data memory */ +/* All the change below should be consistent with DSP client --- khs 04/17/98 */ +/*------------------------------------------------------------------------------------------- */ + + /* left Volume */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + CDATA_LEFT_VOLUME, 0X7FFF); + + /* right Volume */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + CDATA_LEFT_VOLUME + 1, 0X7FFF); + + /* DIRECTION */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, wCD_offset + SRC3_DIRECTION_OFFSET, 0 /* playback */ + ); + + /* MODE */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, wCD_offset + SRC3_DIRECTION_OFFSET + 1, 0 /* stereo */ + ); + + /* WORDLEN */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, wCD_offset + SRC3_DIRECTION_OFFSET + 2, 0 /* 16bit */ + ); + + /* FRACTION */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 3, 0X0000); + + /* FIRST_L */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 4, 0); + + /* FIRST_R */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 5, 0); + + /* SECOND_L */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 6, 0); + + /* SECOND_R */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 7, 0); + + /* DELTA_L */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 8, 0); + + /* DELTA_R */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 9, 0); + + /* ROUND */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 10, 0X8000); + + /* HIGHER BYTE MASK */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 11, 0XFF00); + + /* TEMPORARY INPUT BUFFER ADDRESS */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 12, + (WORD) (wCD_offset + 40 + 8)); + + /* TEMP0 */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 13, 0); + + /* C_FRACTION */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 14, 0); + + /* COUNTER */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 15, 0); + + /* NUMIN */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 16, 8); + + /* NUMOUT */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 17, 24); + + /* NUMSTAGE */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 18, + (MINISRC_BIQUAD_STAGE - 1)); + + /* COEF */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 19, + (WORD) (wCC_offset + MINISRC_COEF_LOC)); + + /* FILTERTAP */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 20, 0); + + /* BOOSTER */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 21, 0); + + /* SKIPLPF */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 22, 0xFF); + + + /* set the run-flag to start */ + kSetInstanceReady (devc, gphwi, pClient_SPDIFIN); + } + } + else + { + if (pClient_SPDIFIN) + { + + /* stop DMA transfer */ + kStopTransfer (devc, gphwi, pClient_SPDIFIN); + + /* stop the DSP client */ + kSetInstanceNotReady (devc, gphwi, pClient_SPDIFIN); + + kCloseInstance (devc, gphwi, pClient_SPDIFIN, + KOPENCLOSE_SYNCHRONOUS); + pClient_SPDIFIN = NULL; +#if 0 + StreamsRunning--; + if (0 == StreamsRunning) + { + WRITE_PORT_USHORT (devc->osdev, devc->base + HOST_INT_CTRL, + (USHORT) (READ_PORT_USHORT + (devc->osdev, + devc->base + + HOST_INT_CTRL) & + ~CLKRUN_GEN_ENABLE)); + } +#endif + } + } +} /* SRCMGR_StartSPDIFIN */ + +#define REAL_SHIFT 15 +#define REAL_SCALE ( 1 << REAL_SHIFT ) + +void +SRCMGR_SetFrequency (allegro_devc * devc, IN PALLEGRO_WAVE AllegroWave) +{ + LONG frequency; + + if (AllegroWave->DspClientInstance) + { + frequency = (AllegroWave->Frequency * REAL_SCALE + 24000) / 48000; + if (frequency > 0) + --frequency; + kSetFrequency (devc, gphwi, AllegroWave->DspClientInstance, + (WORD) frequency); + } +} /* SRCMGR_SetFrequency */ + +void +SRCMGR_StartPlay (allegro_devc * devc, IN PALLEGRO_WAVE AllegroWave) +{ + ULONG FilterLength; + ULONG i; + ULONG Length; + ULONG SizeIn; + ULONG SizeOut; + ULONG StartOffset; + USHORT wCC_offset; + USHORT wCD_offset; + + if (AllegroWave->DspClientInstance) + { + + if (!IsAC3Format) + SRCMGR_SetFrequency (devc, AllegroWave); + + wCC_offset = + (WORD) (AllegroWave->DspClientInstance->dwDspCodeClientArea); + wCD_offset = + (WORD) (AllegroWave->DspClientInstance->dwDspDataClientArea); + + Length = devc->dma_dac.dmasize; /*AllegroWave->Buffer->Length; */ + AllegroWave->Length = Length; + + if (!IsAC3Format) + { + StartOffset = 0x20 * 2; + SizeIn = MINISRC_IN_BUFFER_SIZE - StartOffset; + SizeOut = MINISRC_OUT_BUFFER_SIZE + StartOffset; + StartOffset = wCD_offset + MINISRC_TMP_BUFFER_SIZE / 2; + + kStartTransfer (devc, gphwi, AllegroWave->DspClientInstance, TRUE, devc->dma_dac.base, /*AllegroWave->Buffer->Physical, */ + Length, + 0L, + 0L, + StartOffset, + SizeIn, + StartOffset + SizeIn / 2 + 1, + SizeOut, KCONNECT_DMA, KCONNECT_MIXER); + + /* ------------------------------------------------------------------------- */ + /* load the coefficient starting at offset of program size in program memory */ + /* ------------------------------------------------------------------------- */ + + /* filter length calculation */ + FilterLength = sizeof (MINISRC_LPF) / 2; + + for (i = 0; i < FilterLength; i++) + { + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_CODE, wCC_offset + MINISRC_COEF_LOC + i, (USHORT) (MINISRC_LPF[i])); /*since it is in sequence. */ + } + + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_CODE, + wCC_offset + MINISRC_COEF_LOC + FilterLength, + 0X8000); + +/*------------------------------------------------------------------------------------------- */ +/* Transfer all parameters into DSP Data memory */ +/* All the change below should be consistent with DSP client --- khs 04/17/98 */ +/*------------------------------------------------------------------------------------------- */ + + /* left Volume */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + CDATA_LEFT_VOLUME, 0X7FFF); + + /* right Volume */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + CDATA_LEFT_VOLUME + 1, 0X7FFF); + + /* DIRECTION */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, wCD_offset + SRC3_DIRECTION_OFFSET, 0 /* playback */ + ); + + /* MODE */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 1, + (WORD) ! AllegroWave->FormatStereo); + + /* WORDLEN */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 2, + (WORD) ! AllegroWave->Format16Bit); + + /* FRACTION */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 3, 0X0000); + + /* FIRST_L */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 4, 0); + + /* FIRST_R */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 5, 0); + + /* SECOND_L */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 6, 0); + + /* SECOND_R */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 7, 0); + + /* DELTA_L */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 8, 0); + + /* DELTA_R */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 9, 0); + + /* ROUND */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 10, 0X8000); + + /* HIGHER BYTE MASK */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 11, 0XFF00); + + /* TEMPORARY INPUT BUFFER ADDRESS */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 12, + (WORD) (wCD_offset + 40 + 8)); + + /* TEMP0 */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 13, 0); + + /* C_FRACTION */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 14, 0); + + /* COUNTER */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 15, 0); + + /* NUMIN */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 16, 8); + + if (0 < AllegroWave->Frequency && AllegroWave->Frequency < 8000) + { + Length = 48000 * 8 / AllegroWave->Frequency; + + /* add one more for remainder */ + ++Length; + + /* make it even */ + if (Length & 1) + ++Length; + + /* NUMOUT */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 17, + (USHORT) Length * 2); + } + else + /* NUMOUT */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 17, 50 * 2); + + /* NUMSTAGE */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 18, + (MINISRC_BIQUAD_STAGE - 1)); + + /* COEF */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 19, + (WORD) (wCC_offset + MINISRC_COEF_LOC)); + + /* FILTERTAP */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 20, 0); + + /* BOOSTER */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 21, 0); + + /* SKIPLPF */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 22, + (WORD) ((AllegroWave->Frequency > + 45000) ? 0xFF : 0)); + + + if (AllegroWave->PositionBeforePaused) + kAlterTransfer (devc, gphwi, + AllegroWave->DspClientInstance, + KALTER_POSITION, + TRUE, AllegroWave->PositionBeforePaused); + } + else + { + kStartTransfer (devc, gphwi, AllegroWave->DspClientInstance, TRUE, devc->dma_dac.base, /*AllegroWave->Buffer->Physical, */ + Length, + 0L, + 0L, + (ULONG) (wCD_offset + wSPDIFVarLen), + (ULONG) (gwSPDIF_IN_BufferSize), + (DWORD) NULL, 0, KCONNECT_DMA, 0); + + /* only one parameter */ + /* when you close ac3-spdif, you have to put it back with "0x100" */ + HWMGR_WriteDataWord (devc, ASSP_MEMORY_PORT, DSP_DATA_MEMORY); + HWMGR_WriteDataWord (devc, ASSP_INDEX_PORT, KDATA_SPDIF_FRAME0); + HWMGR_WriteDataWord (devc, ASSP_DATA_PORT, 0x102); /*;0x102 -- AC3 data */ + } + /*;0x100 -- pcm data */ + /* set the run-flag to start */ + kSetInstanceReady (devc, gphwi, AllegroWave->DspClientInstance); + } +} /* SRCMGR_StartPlay */ + + +void +SRCMGR_StartRecord (allegro_devc * devc, IN PALLEGRO_WAVE AllegroWave) +{ + ULONG Length; + ULONG SizeIn; + ULONG SizeOut; + ULONG StartOffset; + USHORT wCD_offset; + + if (AllegroWave->DspClientInstance) + { + + SRCMGR_SetFrequency (devc, AllegroWave); + + wCD_offset = + (WORD) (AllegroWave->DspClientInstance->dwDspDataClientArea); + + Length = devc->dma_adc.dmasize; /*AllegroWave->Buffer->Length; */ + AllegroWave->Length = Length; + StartOffset = 0x10 * 2; + SizeIn = MINISRC_IN_BUFFER_SIZE + StartOffset; + SizeOut = MINISRC_OUT_BUFFER_SIZE - StartOffset; + StartOffset = wCD_offset + MINISRC_TMP_BUFFER_SIZE / 2; + + kStartTransfer (devc, gphwi, AllegroWave->DspClientInstance, TRUE, 0L, 0L, devc->dma_adc.base, /*AllegroWave->Buffer->Physical, */ + Length, + StartOffset, + SizeIn, + StartOffset + SizeIn / 2 + 1, + SizeOut, gwDSPConnectIn, KCONNECT_DMA); + +/*------------------------------------------------------------------------------------------- */ +/* Transfer all parameters into DSP Data memory */ +/* All the change below should be consistent with DSP client --- khs 04/17/98 */ +/*------------------------------------------------------------------------------------------- */ + + /* left Volume */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + CDATA_LEFT_VOLUME, 0X7FFF); + + /* right Volume */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + CDATA_LEFT_VOLUME + 1, 0X7FFF); + + /* DIRECTION */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, wCD_offset + SRC3_DIRECTION_OFFSET, 1 /* recording */ + ); + + /* MODE */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 1, + (WORD) ! AllegroWave->FormatStereo); + + /* WORDLEN */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 2, + (WORD) ! AllegroWave->Format16Bit); + + /* FRACTION */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 3, 0X0000); + + /* FIRST_L */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 4, 0); + + /* FIRST_R */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 5, 0); + + /* SECOND_L */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 6, 0); + + /* SECOND_R */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 7, 0); + + /* DELTA_L */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 8, 0); + + /* DELTA_R */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 9, 0); + + /* ROUND */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 10, 0X8000); + + /* HIGHER BYTE MASK */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 11, 0XFF00); + + /* TEMPORARY INPUT BUFFER ADDRESS */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 12, + (WORD) (wCD_offset + 40 + 8)); + + /* TEMP0 */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 13, 0); + + /* C_FRACTION */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 14, 0); + + /* COUNTER */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 15, 0); + + if (0 < AllegroWave->Frequency && AllegroWave->Frequency < 8000) + { + Length = 48000 * 8 / AllegroWave->Frequency; + + /* add one more for remainder */ + ++Length; + + /* make it even */ + if (Length & 1) + ++Length; + + /* NUMIN */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 16, + (USHORT) Length); + } + else + /* NUMIN */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 16, 50); + + /* NUMOUT */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 17, 8); + + /*AY */ + /* NUMSTAGE */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 18, 0); + + /* COEF */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 19, 0); + + /* FILTERTAP */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 20, 0); + + /* BOOSTER */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 21, 0); + + /* SKIPLPF = FF ; no LPF for any recording */ + kDspWriteWord (devc, devc->base, MEMTYPE_INTERNAL_DATA, + wCD_offset + SRC3_DIRECTION_OFFSET + 22, 0xFF); + + /* set the run-flag to start */ + kSetInstanceReady (devc, gphwi, AllegroWave->DspClientInstance); + } +} /* SRCMGR_StartRec */ +void +SRCMGR_SetVolume (allegro_devc * devc, IN PCLIENT_INST client, IN USHORT left, + IN USHORT right) +{ + USHORT lvalue; + USHORT rvalue; + + if (client) + { + lvalue = left >> 1; + rvalue = right >> 1; + + kSetVolume (devc, gphwi, client, lvalue, rvalue, 0); + } +} /* SRCMGR_SetVolume */ + +void +SRCMGR_SetRearVolume (allegro_devc * devc, IN PCLIENT_INST client, + IN USHORT left, IN USHORT right) +{ + USHORT lvalue; + USHORT rvalue; + + if (client) + { + lvalue = left >> 1; + rvalue = right >> 1; + + kSetRearVolume (devc, gphwi, client, lvalue, rvalue); + } +} /* SRCMGR_SetVolume */ + +void +SRCMGR_SetupStream (allegro_devc * devc, IN PALLEGRO_WAVE AllegroWave) +{ + +#ifdef SRC4 + /* using host src */ + AllegroWave->SR_8khzFlag = FALSE; + +#else + /* not using host src */ + AllegroWave->SR_8khzFlag = TRUE; +#endif + if (STREAM_TYPE_NULL == AllegroWave->StreamType) + { + AllegroWave->StreamType = STREAM_TYPE_DSPSRC; + + /* 8-bit not supported by SRC */ + if (!AllegroWave->Format16Bit) + AllegroWave->StreamType = STREAM_TYPE_DSPMSRC; + } + +#if ALLEGRO_DEBUG + if (AllegroWave->StreamType == STREAM_TYPE_DSPMSRC) + { + _Debug_Printf_Service ("M. SRC\r\n"); + } + else + { + _Debug_Printf_Service ("SRC 3.X\r\n"); + } /* endif */ +#endif + /* see if we can acquire a DSP client instance for the new */ + /* requested format */ + if (AllegroWave->StreamType == STREAM_TYPE_DSPSRC) + { + switch (AllegroWave->Frequency) + { + case 44100: + AllegroWave->wFreqIndex = SRC3_SR_44100; + break; + + case 32000: + AllegroWave->wFreqIndex = SRC3_SR_32000; + break; +#if 1 + case 22050: + AllegroWave->wFreqIndex = SRC3_SR_22050; + break; + case 11025: + AllegroWave->wFreqIndex = SRC3_SR_11025; + break; + case 8000: + AllegroWave->wFreqIndex = SRC3_SR_8000; + + /* khs */ + AllegroWave->SR_8khzFlag = TRUE; + break; +#endif + default: + AllegroWave->StreamType = STREAM_TYPE_DSPMSRC; + } + } + +#if 1 + AllegroWave->StreamType = STREAM_TYPE_DSPMSRC; /*DON */ + dprintf1 (("SRCMGR_SetupStream Mode %d", AllegroWave->StreamType)); +#endif +#if ALLEGRO_DEBUG + if (AllegroWave->StreamType == STREAM_TYPE_DSPMSRC) + { + _Debug_Printf_Service ("M. SRC\r\n"); + } + else + { + _Debug_Printf_Service ("SRC 3.X\r\n"); + } /* endif */ +#endif + + /* ok, if it was determined we are to attempt to do a SCR stream */ + /* we still don't know if we can so we have to see if the SRC */ + /* manager will allow us to do it... and if so we have to try and */ + /* get an instance from the DSP kernel, if the SRC manager didn't */ + /* let us get it or the DSP kernel didn't allow it we defer it */ + /* back to Mini SRC stream */ + if (AllegroWave->StreamType == STREAM_TYPE_DSPSRC) + { + if (WAVE_CAPTURE == AllegroWave->WaveType) + { + if (!AllocateSRCRec) + { + + /* Temporary Buffer Size: Two Filter Tap buffer, one block of temporary output buffer */ + AllegroWave->wSRC3VarLen = SRC3_TEMP_OUTBUF_ADDR_OFFSET + 2 + + 2 * (gwSRC3_REC_FILTER_TAP_SIZE[AllegroWave->wFreqIndex] + + 1) + 2 + gwSRC3_REC_SIZE_IN[AllegroWave->wFreqIndex] + + 1 + gwSRC3_REC_SIZE_OUT[AllegroWave->wFreqIndex] + 1 + 1 + + FOR_FUTURE_USE; + + kOpenInstance (devc, gphwi, + CLIENT_SRC, + 0, + 2 * (AllegroWave->wSRC3VarLen + + gwSRC3_REC_IN_BufferSize[AllegroWave-> + wFreqIndex] / 2 + + 1 + + gwSRC3_REC_OUT_BufferSize[AllegroWave-> + wFreqIndex] / 2 + + 1), &AllegroWave->DspClientInstance); + if (AllegroWave->DspClientInstance) + { + +/* SRC does not support full-duplex */ +#if 1 + AllocateSRCPlay = TRUE; +#endif + AllocateSRCRec = TRUE; + } + } + } + else + { + if (!AllocateSRCPlay) + { + + /* khs 082098 */ + /* Temporary Buffer Size: Two Filter Tap buffer, one block of temporary input/output buffer */ + AllegroWave->wSRC3VarLen = SRC3_TEMP_OUTBUF_ADDR_OFFSET + 2 + + 2 * (gwSRC3_PB_FILTER_TAP_SIZE[AllegroWave->wFreqIndex] + 1) + + 2 + + gwSRC3_PB_SIZE_OUT[AllegroWave->wFreqIndex] + 1 + + gwSRC3_PB_SIZE_IN[AllegroWave->wFreqIndex] + 1 + + FOR_FUTURE_USE; + + kOpenInstance (devc, gphwi, CLIENT_SRC, 0, 2 * (AllegroWave->wSRC3VarLen + gwSRC3_IN_BufferSize[AllegroWave->wFreqIndex] / 2 + 1 + gwSRC3_OUT_BufferSize[AllegroWave->wFreqIndex] / 2 + 1), /* word */ + &AllegroWave->DspClientInstance); + dprintf3 (("kOpenIns:%x", AllegroWave->DspClientInstance)); + if (AllegroWave->DspClientInstance) + { + AllocateSRCPlay = TRUE; + +/* SRC does not support full-duplex */ +#if 1 + AllocateSRCRec = TRUE; +#endif + } + } + } + if (!AllegroWave->DspClientInstance) + AllegroWave->StreamType = STREAM_TYPE_DSPMSRC; + } + + if (STREAM_TYPE_DSPMSRC == AllegroWave->StreamType) + { + if (kOpenInstance (devc, gphwi, + IsAC3Format ? CLIENT_SPDIF : CLIENT_MINISRC, + 0, + IsAC3Format ? 2 * (wSPDIFVarLen + + gwSPDIF_IN_BufferSize / 2) : 2 * + (MINISRC_TMP_BUFFER_SIZE / 2 + + MINISRC_IN_BUFFER_SIZE / 2 + 1 + + MINISRC_OUT_BUFFER_SIZE / 2 + 1), + &AllegroWave->DspClientInstance) != KRETURN_SUCCESS) + { + dprintf1 (("%x:Open M SRC Inst!\n")); + num_errors++; + } + } +} /* SRCMGR_SetupStream */ + +ULONG +SRCMGR_GetPosition (allegro_devc * devc, IN PALLEGRO_WAVE AllegroWave) +{ + int i; + ULONG Position; + ULONG BufferPosition = 0; + KIRQL OldIrql; + +/*dprintf1(("GetPos=%x %x %x %x", AllegroWave->State, AllegroWave->DspClientInstance, AllegroWave->Length, AllegroWave->WaveType)); */ + + /* to make sure nothing funny happens if this stream is in stop */ + /* state, just return 0 */ + if (KSSTATE_STOP == AllegroWave->State || !AllegroWave->DspClientInstance) + return 0; + + KeAcquireSpinLock (&gpGDI->ControlSpinLock, &OldIrql); + + if (WAVE_CAPTURE == AllegroWave->WaveType) + { + +#ifndef DMAREC + /* khs 090298 for PIO recording */ + kPIOInterruptHandler (devc, gphwi, AllegroWave->DspClientInstance); +#endif + for (i = 0; i < 100; i++) + { + if (kQueryPosition (devc, gphwi, + AllegroWave->DspClientInstance, + FALSE, &BufferPosition) == KRETURN_SUCCESS) + break; + } + +#if 0 + if (BufferPosition >= AllegroWave->Length) + { + dprintf1 (("!%d ", BufferPosition)); + BufferPosition = 0; + } +#endif + Position = BufferPosition % AllegroWave->Length; + } + else + { + for (i = 0; i < 100; i++) + { + if (kQueryPosition (devc, gphwi, + AllegroWave->DspClientInstance, + TRUE, &BufferPosition) == KRETURN_SUCCESS) + break; + } + +#if 0 + if (BufferPosition >= AllegroWave->Length) + { + dprintf1 (("!%d ", BufferPosition)); + BufferPosition = 0; + } +#endif + Position = BufferPosition % AllegroWave->Length; + } + + KeReleaseSpinLock (&gpGDI->ControlSpinLock, OldIrql); + + return (Position); +} /* GetPosition */ + + +void +SetFormat (allegro_devc * devc, IN PALLEGRO_WAVE AllegroWave, + IN PWAVE_INFO WaveInfo) +{ + + /* close previous client if it is SRC and sampling rate is different */ + if (AllegroWave->DspClientInstance && + STREAM_TYPE_DSPSRC == AllegroWave->StreamType && + WaveInfo->SamplesPerSec != AllegroWave->Frequency) + { + dprintf1 (("SetFormat CloseInstance:%x", + AllegroWave->DspClientInstance)); + if (kCloseInstance + (devc, gphwi, AllegroWave->DspClientInstance, + KOPENCLOSE_SYNCHRONOUS) != KRETURN_SUCCESS) + { + _Debug_Printf_Service ("Close inst!\n"); + num_errors++; + } + +#if 0 + if (WAVE_CAPTURE == AllegroWave->WaveType) + AllocateSRCRec = FALSE; + else + AllocateSRCPlay = FALSE; +#else + AllocateSRCPlay = FALSE; + AllocateSRCRec = FALSE; +#endif + AllegroWave->DspClientInstance = NULL; + AllegroWave->StreamType = STREAM_TYPE_NULL; + } + AllegroWave->FormatStereo = (WaveInfo->Channels == 2); + AllegroWave->Format16Bit = (WaveInfo->BitsPerSample == 16); + AllegroWave->Frequency = WaveInfo->SamplesPerSec; + + dprintf1 (("SetFormat:%d,%d,%d", WaveInfo->SamplesPerSec, + WaveInfo->BitsPerSample, WaveInfo->Channels)); +} /* SetFormat */ + + +void +SetState (allegro_devc * devc, + IN PALLEGRO_WAVE AllegroWave, IN KSSTATE NewState) +{ + KIRQL OldIrql; + + dprintf1 (("SetState=(%x, %x)", AllegroWave->State, NewState)); + KeAcquireSpinLock (&gpGDI->ControlSpinLock, &OldIrql); + if (AllegroWave->State != NewState) + { + switch (NewState) + { + case KSSTATE_STOP: + + + AllegroWave->PositionBeforePaused = 0; + if (KSSTATE_RUN == AllegroWave->State) + { + StreamsRunning--; + + if (!StreamsRunning) + { + kSetTimer (devc, gphwi, 0); + WRITE_PORT_USHORT (devc->osdev, (devc->base + 0x18), + READ_PORT_USHORT (devc->osdev, + (devc->base + 0x18)) & + ~CLKRUN_GEN_ENABLE); + } + SRCMGR_Stop (devc, AllegroWave); + } + break; + + case KSSTATE_RUN: + + + /* client not opened */ + if (!AllegroWave->DspClientInstance) + { + SRCMGR_SetupStream (devc, AllegroWave); + } + + /* start the transfer on whatevr method specified */ + switch (AllegroWave->StreamType) + { + case STREAM_TYPE_DSPMSRC: + if (WAVE_CAPTURE == AllegroWave->WaveType) + SRCMGR_StartRecord (devc, AllegroWave); + else + SRCMGR_StartPlay (devc, AllegroWave); + break; + } + + StreamsRunning++; + + if (1 == StreamsRunning) + { + /* 4 ms * 12000 / 1000 */ + kSetTimer (devc, gphwi, 240); + WRITE_PORT_USHORT (devc->osdev, (devc->base + 0x18), + READ_PORT_USHORT (devc->osdev, + (devc->base + 0x18)) | + CLKRUN_GEN_ENABLE); + } + + break; + } + AllegroWave->State = NewState; + } + KeReleaseSpinLock (&gpGDI->ControlSpinLock, OldIrql); +} /* SetState */ + +#ifdef later +ULONG +GetMidiPosition () +{ + return SRCMGR_GetPosition (devc, MidiStream); +} + +PCLIENT_INST pClient; +#define DBG_TRACE dprintf1 + +DWORD +InitModem (allegro_devc * devc) +{ + int cnt = 0; + int wRC, retry = 0; + + do + { + wRC = kOpenInstance (devc, gphwi, CLIENT_MODEM, 0, 512 * 2 + 64, &pClient); /* HSP_Open */ + } + while ((wRC != KRETURN_SUCCESS) && (cnt++ < 100)); /* enddo */ + + if (wRC != KRETURN_SUCCESS) + { + DBG_TRACE (("KOpenInstance from HSP modem fail")); + return FALSE; + } /* endif */ + DBG_TRACE (("KOpenInstance from HSP modem OK")); + + dprintf1 (("pClient Area=%x", pClient->dwDspDataClientArea)); + /* setup the outbuffer address and length so Kernel can */ + /* move the output data to MIXER */ + + retry = 0; + do + { + + wRC = kStartTransfer (devc, gphwi, + pClient, + NULL, + NULL, + 0, + NULL, + 0, + NULL, + 0, + pClient->dwDspDataClientArea + 32, + 128, KCONNECT_NONE, KCONNECT_MIXER); + +#if ALLEGRO_DEBUG + if (wRC != KRETURN_SUCCESS) + { + DBG_TRACE (("kStartTransfer fail")); + } /* endif */ +#endif + } + while ((wRC != KRETURN_SUCCESS) && (retry++ < 100)); /* enddo */ + + + if (wRC != KRETURN_SUCCESS) + { + DBG_TRACE (("kStartTransfer fail")); + kCloseInstance (gphwi, pClient, 0); +#pragma message("----Closing client, can we handle this?") + return FALSE; + } + else + { + DBG_TRACE (("kStartTransfer OK")); + } /* endif */ + return TRUE; + +} + +VOID +CloseModem () +{ + + int cnt = 0; + int wRC; + + cnt = 0; + if (!pClient) + return; + + do + { + wRC = kStopTransfer (devc, gphwi, pClient); +#if ALLEGRO_DEBUG + if (wRC != KRETURN_SUCCESS) + { + DBG_TRACE (("DSPStopXfer fail")); + } /* endif */ +#endif + } + while ((wRC != KRETURN_SUCCESS) && (cnt++ < 100)); + + cnt = 0; + do + { + wRC = kCloseInstance (devc, gphwi, pClient, 0); + } + while ((wRC != KRETURN_SUCCESS) && (cnt++ < 100)); /* enddo */ + +} +#endif + +void +SRCMGR_SetPassThruVolume (allegro_devc * devc, IN PPASSTHRU client, + IN USHORT left, IN USHORT right) +{ + USHORT lvalue; + USHORT rvalue; + + if (client) + { + lvalue = left >> 1; + rvalue = right >> 1; + + kSetPassThruVolume (devc, gphwi, client, lvalue, rvalue); + dprintf3 (("kSetPassThruVolume %x %x", lvalue, rvalue)); + } +} /* SRCMGR_SetPassThruVolume */ + +void +SRCMGR_SetPassThruRearVolume (allegro_devc * devc, IN PPASSTHRU client, + IN USHORT left, IN USHORT right) +{ + USHORT lvalue; + USHORT rvalue; + + if (!client) + return; + + /*LeftPassThruVolRear = left; */ + /*RightPassThruVolRear = right; */ + + + if (client) + { + lvalue = left >> 1; + rvalue = right >> 1; + + kSetPassThruRearVolume (devc, gphwi, client, lvalue, rvalue); + } +} /* SRCMGR_SetPassThruRearVolume */ diff --git a/attic/drv/oss_als3xx/.devices b/attic/drv/oss_als3xx/.devices new file mode 100644 index 0000000..2a4e7aa --- /dev/null +++ b/attic/drv/oss_als3xx/.devices @@ -0,0 +1,2 @@ +oss_als3xx pci4005,300 Avance Logic ALS300 +oss_als3xx pci4005,308 Avance Logic ALS300+ diff --git a/attic/drv/oss_als3xx/.name b/attic/drv/oss_als3xx/.name new file mode 100644 index 0000000..f588080 --- /dev/null +++ b/attic/drv/oss_als3xx/.name @@ -0,0 +1 @@ +Avance Logic ALS300 diff --git a/attic/drv/oss_als3xx/.params b/attic/drv/oss_als3xx/.params new file mode 100644 index 0000000..4fd5829 --- /dev/null +++ b/attic/drv/oss_als3xx/.params @@ -0,0 +1,5 @@ +int als300_mpu_base=0; +/* + * Specify ALS300's MPU Base + * Values: 0x300, 0x310, 0x320, 0x330, 0x340, 0x0350, 0x360, 0x370 Default: 0 + */ diff --git a/attic/drv/oss_als3xx/als300.h b/attic/drv/oss_als3xx/als300.h new file mode 100644 index 0000000..59635e9 --- /dev/null +++ b/attic/drv/oss_als3xx/als300.h @@ -0,0 +1,324 @@ +/* + * Purpose: Definitions for the ALS300 driver. + */ +/* + * + * This file is part of Open Sound System. + * + * Copyright (C) 4Front Technologies 1996-2008. + * + * This this source file is released under GPL v2 license (no other versions). + * See the COPYING file included in the main directory of this source + * distribution for the license terms and conditions. + * + */ +#define FNO1 374 +#define FNO2 192 +static unsigned int FreqTable1[FNO1] = { + 3997, 0x162, + 4017, 0x062, + 4038, 0x161, + 4058, 0x061, + 4079, 0x160, + 4100, 0x060, + 4121, 0x15F, + 4143, 0x05F, + 4165, 0x15E, + 4187, 0x05E, + 4209, 0x15D, + 4231, 0x05D, + 4254, 0x15C, + 4277, 0x05C, + 4300, 0x15B, + 4323, 0x05B, + 4347, 0x15A, + 4371, 0x05A, + 4395, 0x159, + 4419, 0x059, + 4444, 0x158, + 4469, 0x058, + 4494, 0x157, + 4520, 0x057, + 4545, 0x156, + 4571, 0x056, + 4598, 0x155, + 4625, 0x055, + 4652, 0x154, + 4679, 0x054, + 4707, 0x153, + 4735, 0x053, + 4763, 0x152, + 4792, 0x052, + 4821, 0x151, + 4850, 0x051, + 4880, 0x150, + 4910, 0x050, + 4941, 0x14F, + 4972, 0x04F, + 5003, 0x14E, + 5034, 0x04E, + 5066, 0x14D, + 5099, 0x04D, + 5132, 0x14C, + 5165, 0x04C, + 5199, 0x14B, + 5233, 0x04B, + 5268, 0x14A, + 5303, 0x04A, + 5339, 0x149, + 5375, 0x049, + 5411, 0x148, + 5448, 0x048, + 5486, 0x147, + 5524, 0x047, + 5563, 0x146, + 5602, 0x046, + 5641, 0x145, + 5682, 0x045, + 5723, 0x144, + 5764, 0x044, + 5806, 0x143, + 5849, 0x043, + 5892, 0x142, + 5936, 0x042, + 5981, 0x141, + 6026, 0x041, + 6072, 0x140, + 6119, 0x040, + 6166, 0x13F, + 6214, 0x03F, + 6263, 0x13E, + 6313, 0x03E, + 6364, 0x13D, + 6415, 0x03D, + 6467, 0x13C, + 6520, 0x03C, + 6574, 0x13B, + 6629, 0x03B, + 6684, 0x13A, + 6741, 0x03A, + 6799, 0x139, + 6857, 0x039, + 6917, 0x138, + 6978, 0x038, + 7039, 0x137, + 7102, 0x037, + 7166, 0x136, + 7231, 0x036, + 7298, 0x135, + 7365, 0x035, + 7434, 0x134, + 7504, 0x034, + 7576, 0x133, + 7648, 0x033, + 7723, 0x132, + 7798, 0x032, + 7876, 0x131, + 7954, 0x031, + 8000, 0x201, + 8035, 0x130, + 8117, 0x030, + 8200, 0x12F, + 8286, 0x02F, + 8373, 0x12E, + 8462, 0x02E, + 8553, 0x12D, + 8646, 0x02D, + 8741, 0x12C, + 8838, 0x02C, + 8938, 0x12B, + 9039, 0x02B, + 9143, 0x12A, + 9249, 0x02A, + 9358, 0x129, + 9470, 0x029, + 9584, 0x128, + 9700, 0x028, + 9820, 0x127, + 9943, 0x027, + 10069, 0x126, + 10198, 0x026, + 10330, 0x125, + 10466, 0x025, + 10605, 0x124, + 10749, 0x024, + 10896, 0x123, + 11048, 0x023, + 11203, 0x122, + 11363, 0x022, + 11528, 0x121, + 11698, 0x021, + 11872, 0x120, + 12052, 0x020, + 12238, 0x11F, + 12429, 0x01F, + 12626, 0x11E, + 12830, 0x01E, + 13040, 0x11D, + 13257, 0x01D, + 13482, 0x11C, + 13714, 0x01C, + 13955, 0x11B, + 14204, 0x01B, + 14463, 0x11A, + 14730, 0x01A, + 15008, 0x119, + 15297, 0x019, + 15597, 0x118, + 15909, 0x018, + 16000, 0x202, + 16233, 0x117, + 16572, 0x017, + 16924, 0x116, + 17292, 0x016, + 17676, 0x115, + 18078, 0x015, + 18499, 0x114, + 18939, 0x014, + 19401, 0x113, + 19886, 0x013, + 20396, 0x112, + 20993, 0x012, + 21498, 0x111, + 22096, 0x011, + 22727, 0x110, + 23395, 0x010, + 24104, 0x10F, + 24858, 0x00F, + 25659, 0x10E, + 26515, 0x00E, + 27429, 0x10D, + 28409, 0x00D, + 29461, 0x10C, + 30594, 0x00C, + 31818, 0x10B, + 32000, 0x203, + 33143, 0x00B, + 34584, 0x10A, + 36156, 0x00A, + 37878, 0x109, + 39772, 0x009, + 41805, 0x108, + 44191, 0x008, + 46791, 0x107, + 48000, 0x000 +}; + + +#if 0 +static unsigned int FreqTable2[FNO2] = { + 3977, 0x231, + 4018, 0x330, + 4059, 0x230, + 4100, 0x32F, + 4146, 0x22F, + 4187, 0x32E, + 4231, 0x22E, + 4277, 0x32D, + 4323, 0x22D, + 4371, 0x32C, + 4419, 0x22C, + 4469, 0x32B, + 4520, 0x22B, + 4572, 0x32A, + 4625, 0x22A, + 4679, 0x329, + 4735, 0x229, + 4792, 0x328, + 4850, 0x228, + 4910, 0x327, + 4972, 0x227, + 5035, 0x326, + 5099, 0x226, + 5165, 0x325, + 5233, 0x225, + 5303, 0x324, + 5375, 0x224, + 5448, 0x323, + 5524, 0x223, + 5602, 0x322, + 5682, 0x222, + 5764, 0x321, + 5849, 0x221, + 5936, 0x320, + 6026, 0x220, + 6119, 0x31F, + 6215, 0x21F, + 6313, 0x31E, + 6415, 0x21E, + 6520, 0x31D, + 6629, 0x21D, + 6741, 0x31C, + 6857, 0x21C, + 6978, 0x31B, + 7102, 0x21B, + 7232, 0x31A, + 7365, 0x21A, + 7504, 0x319, + 7649, 0x219, + 7799, 0x318, + 7955, 0x218, + 8000, 0x201, + 8117, 0x317, + 8286, 0x217, + 8462, 0x316, + 8646, 0x216, + 8838, 0x315, + 9039, 0x215, + 9250, 0x314, + 9470, 0x214, + 9701, 0x313, + 9943, 0x213, + 10198, 0x312, + 10497, 0x212, + 10749, 0x311, + 11048, 0x211, + 11364, 0x310, + 11698, 0x210, + 12052, 0x30F, + 12429, 0x20F, + 12830, 0x30E, + 13258, 0x20E, + 13715, 0x30D, + 14205, 0x20D, + 14731, 0x30C, + 15297, 0x20C, + 15909, 0x30B, + 16000, 0x202, + 16572, 0x20B, + 17292, 0x30A, + 18078, 0x20A, + 18939, 0x309, + 19886, 0x209, + 20903, 0x308, + 22096, 0x208, + 23396, 0x307, + 24858, 0x207, + 26515, 0x306, + 28409, 0x206, + 30594, 0x305, + 32000, 0x203, + 33144, 0x205, + 36157, 0x304, + 39772, 0x204, + 44191, 0x303, + 48000, 0x000 +}; +#endif + +#define VERSION_A 0 +#define VERSION_B 1 +#define VERSION_C 2 +#define VERSION_D 3 +#define VERSION_E 4 +#define VERSION_F 5 +#define VERSION_G 6 +#define VERSION_H 7 +#define VERSION_I 8 +#define VERSION_J 9 +#define VERSION_K 10 +#define VERSION_L 11 +#define VERSION_M 12 +#define VERSION_N 13 +#define VERSION_O 14 +#define VERSION_P 15 diff --git a/attic/drv/oss_als3xx/oss_als3xx.c b/attic/drv/oss_als3xx/oss_als3xx.c new file mode 100644 index 0000000..bfc8fa3 --- /dev/null +++ b/attic/drv/oss_als3xx/oss_als3xx.c @@ -0,0 +1,898 @@ +/* + * Purpose: Driver for ALS ALS300 PCI audio controller. + */ +/* + * + * This file is part of Open Sound System. + * + * Copyright (C) 4Front Technologies 1996-2008. + * + * This this source file is released under GPL v2 license (no other versions). + * See the COPYING file included in the main directory of this source + * distribution for the license terms and conditions. + * + */ + +#include "oss_als3xx_cfg.h" +#include "oss_pci.h" +#include "ac97.h" +#include "als300.h" + +#define ALS_VENDOR_ID 0x4005 +#define ALS_300 0x0300 +#define ALS_300P 0x0308 + +extern int als300_mpu_base; + +#define MAX_PORTC 2 + +typedef struct als300_portc +{ + int speed, bits, channels; + int open_mode; + int audio_enabled; + int trigger_bits; + int audiodev; +} +als300_portc; + +typedef struct als300_devc +{ + oss_device_t *osdev; + oss_native_word base, mpu_base; + int mpu_attached, fm_attached; + int irq; + + volatile unsigned char intr_mask; +#define MDL_ALS300 0 +#define MDL_ALS300PLUS 1 + int model; + char *chip_name; + unsigned char chip_rev; + oss_mutex_t mutex; + oss_mutex_t low_mutex; + + /* Audio parameters */ + int open_mode; + als300_portc portc[2]; + oss_native_word srcode; + + /* Mixer parameters */ + ac97_devc ac97devc; + int mixer_dev; +} +als300_devc; + + +void +gcr_writel (als300_devc * devc, unsigned char index, oss_native_word data) +{ + OUTB (devc->osdev, index, devc->base + 0x0c); + OUTL (devc->osdev, data, devc->base + 0x08); +} + + +oss_native_word +gcr_readl (als300_devc * devc, unsigned char index) +{ + oss_native_word bufl; + OUTB (devc->osdev, index, devc->base + 0x0c); + bufl = INL (devc->osdev, devc->base + 0x08); + return (bufl); +} + +static int +ac97_write (void *devc_, int index, int data) +{ + oss_native_word access; + unsigned i, N; + unsigned char byte; + als300_devc *devc = devc_; + oss_native_word flags; + + MUTEX_ENTER_IRQDISABLE (devc->low_mutex, flags); + i = 0; + N = 1000; + do + { + byte = INB (devc->osdev, devc->base + 6) & 0x80; + if (byte == 0x00) + goto go; + oss_udelay (10); + i++; + } + while (i < N); + if (i >= N) + cmn_err (CE_WARN, "\n Write AC97 mixer index time out !!"); +go: + access = index; + access <<= 24; /*index */ + access &= 0x7fffffff; /*write */ + access |= data; /*data */ + OUTL (devc->osdev, access, devc->base); + MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags); + return 0; +} + +static int +ac97_read (void *devc_, int index) +{ + oss_native_word access; + unsigned int data; + unsigned i, N; + unsigned char byte; + oss_native_word flags; + als300_devc *devc = devc_; + + MUTEX_ENTER_IRQDISABLE (devc->low_mutex, flags); + i = 0; + N = 1000; + do + { + byte = INB (devc->osdev, devc->base + 6) & 0x80; + if (byte == 0x00) + goto next; + oss_udelay (10); + i++; + } + while (i < N); + if (i >= N) + cmn_err (CE_WARN, "\n Write AC97 mixer index time out !!"); +next: + access = index; + access <<= 24; /*index */ + access |= 0x80000000; + OUTL (devc->osdev, access, devc->base); + + i = 0; + N = 1000; + do + { + byte = INB (devc->osdev, devc->base + 6); + if ((byte & 0x40) != 0) + goto next1; + oss_udelay (10); + i++; + } + while (i < N); + if (i >= N) + cmn_err (CE_WARN, "Read AC97 mixer data time out !!"); +next1: + data = INW (devc->osdev, devc->base + 0x04); + MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags); + return data; +} + +static int +als300intr (oss_device_t * osdev) +{ + als300_devc *devc = (als300_devc *) osdev->devc; + int i; + unsigned int status, mpustatus, serviced = 0; + + /* Get the status */ + if (devc->model == MDL_ALS300) + status = INB (devc->osdev, devc->base + 0x07); + else + status = INB (devc->osdev, devc->base + 0xF); + + /* if playback - do output */ + for (i = 0; i < MAX_PORTC; i++) + { + als300_portc *portc = &devc->portc[i]; + + if (status & 0x08) + { + serviced = 1; + if (portc->trigger_bits & PCM_ENABLE_OUTPUT) + oss_audio_outputintr (portc->audiodev, 1); + } + + /* if record - do input */ + if (status & 0x04) + { + serviced = 1; + if (portc->trigger_bits & PCM_ENABLE_INPUT) + oss_audio_inputintr (portc->audiodev, 0); + } + } + + /* Handle the UART401 Interrupt */ + if (devc->model == MDL_ALS300) + { + mpustatus = INB (devc->osdev, devc->base + 0x0E); + if ((mpustatus & 0x10) || (status & 0x80)) + { + serviced = 1; +/* uart401intr (INT_HANDLER_CALL (devc->irq)); */ + } + } + else + { + if (status & 0x40) + { + serviced = 1; +/* uart401intr (INT_HANDLER_CALL (devc->irq)); */ + } + } + + /* Acknowledge the interrupt */ + if (status) + { + if (devc->model == MDL_ALS300) + { + OUTB (devc->osdev, status, devc->base + 0x07); /* acknowledge interrupt */ + } + else + { + OUTB (devc->osdev, status, devc->base + 0xF); /* acknowledge interrupt */ + } + } + return serviced; +} + +static int +als300_audio_set_rate (int dev, int arg) +{ + als300_portc *portc = audio_engines[dev]->portc; + + if (arg == 0) + return portc->speed; + + if (audio_engines[dev]->flags & ADEV_FIXEDRATE) + arg = 48000; + + if (arg > 48000) + arg = 48000; + if (arg < 5000) + arg = 5000; + portc->speed = arg; + return portc->speed; +} + +static short +als300_audio_set_channels (int dev, short arg) +{ + als300_portc *portc = audio_engines[dev]->portc; + + if (arg == 0) + return portc->channels; + + if (audio_engines[dev]->flags & ADEV_STEREOONLY) + arg = 2; + + if ((arg != 1) && (arg != 2)) + return portc->channels; + portc->channels = arg; + + return portc->channels; +} + +static unsigned int +als300_audio_set_format (int dev, unsigned int arg) +{ + als300_portc *portc = audio_engines[dev]->portc; + + if (arg == 0) + return portc->bits; + + if (audio_engines[dev]->flags & ADEV_16BITONLY) + arg = 16; + if (!(arg & (AFMT_U8 | AFMT_S16_LE))) + return portc->bits; + portc->bits = arg; + + return portc->bits; +} + +/*ARGSUSED*/ +static int +als300_audio_ioctl (int dev, unsigned int cmd, ioctl_arg arg) +{ + return OSS_EINVAL; +} + +static void als300_audio_trigger (int dev, int state); + +static void +als300_audio_reset (int dev) +{ + als300_audio_trigger (dev, 0); +} + +static void +als300_audio_reset_input (int dev) +{ + als300_portc *portc = audio_engines[dev]->portc; + als300_audio_trigger (dev, portc->trigger_bits & ~PCM_ENABLE_INPUT); +} + +static void +als300_audio_reset_output (int dev) +{ + als300_portc *portc = audio_engines[dev]->portc; + als300_audio_trigger (dev, portc->trigger_bits & ~PCM_ENABLE_OUTPUT); +} + +/*ARGSUSED*/ +static int +als300_audio_open (int dev, int mode, int open_flags) +{ + als300_portc *portc = audio_engines[dev]->portc; + als300_devc *devc = audio_engines[dev]->devc; + oss_native_word flags; + + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); + if (portc->open_mode) + { + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + return OSS_EBUSY; + } + + if (devc->open_mode & mode) + { + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + return OSS_EBUSY; + } + + devc->open_mode |= mode; + + portc->open_mode = mode; + portc->audio_enabled &= ~mode; + + if ((mode & OPEN_READ) && !(audio_engines[dev]->flags & ADEV_NOINPUT)) + { + audio_engines[dev]->fixed_rate = 48000; + audio_engines[dev]->flags |= + ADEV_FIXEDRATE | ADEV_STEREOONLY | ADEV_16BITONLY; + audio_engines[dev]->min_rate = 48000; + audio_engines[dev]->max_rate = 48000; + } + else + { + audio_engines[dev]->min_rate = 5000; + audio_engines[dev]->max_rate = 48000; + audio_engines[dev]->fixed_rate = 0; + audio_engines[dev]->flags &= + ~(ADEV_FIXEDRATE | ADEV_STEREOONLY | ADEV_16BITONLY); + } + + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + + return 0; +} + +static void +als300_audio_close (int dev, int mode) +{ + als300_portc *portc = audio_engines[dev]->portc; + als300_devc *devc = audio_engines[dev]->devc; + + als300_audio_reset (dev); + portc->open_mode = 0; + devc->open_mode &= ~mode; + portc->audio_enabled &= ~mode; +} + +/*ARGSUSED*/ +static void +als300_audio_output_block (int dev, oss_native_word buf, int count, + int fragsize, int intrflag) +{ + als300_portc *portc = audio_engines[dev]->portc; + + portc->audio_enabled |= PCM_ENABLE_OUTPUT; + portc->trigger_bits &= ~PCM_ENABLE_OUTPUT; +} + +/*ARGSUSED*/ +static void +als300_audio_start_input (int dev, oss_native_word buf, int count, + int fragsize, int intrflag) +{ + als300_portc *portc = audio_engines[dev]->portc; + + portc->audio_enabled |= PCM_ENABLE_INPUT; + portc->trigger_bits &= ~PCM_ENABLE_INPUT; +} + +static void +als300_audio_trigger (int dev, int state) +{ + als300_portc *portc = audio_engines[dev]->portc; + als300_devc *devc = audio_engines[dev]->devc; + oss_native_word old82 = 0, new82 = 0, old85 = 0, new85 = 0, mode = 0; + oss_native_word flags; + int i; + + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); + if (portc->open_mode & OPEN_WRITE) + { + if (state & PCM_ENABLE_OUTPUT) + { + if ((portc->audio_enabled & PCM_ENABLE_OUTPUT) && + !(portc->trigger_bits & PCM_ENABLE_OUTPUT)) + { + if (portc->bits == 8) + mode = 0x00140000L; + else if (portc->bits == 16) + mode = 0x00000000L; + if (portc->channels == 2) + mode |= 0x00000000L; + else if (portc->channels == 1) + mode |= 0x00080000L; + + old82 = gcr_readl (devc, 0x82); + new82 = (old82 & 0x0000ffff) | 0x00010000; + new82 = new82 | mode | devc->srcode << 22; +#if 1 + for (i = 0; i < 5000; i++) + { + if ((INB (devc->osdev, devc->base + 6) & 0x08) == 0x00) + goto PlayStart; + oss_udelay (10); + } + PlayStart: +#endif + gcr_writel (devc, 0x82, new82); + portc->trigger_bits |= PCM_ENABLE_OUTPUT; + } + } + else + { + if ((portc->audio_enabled & PCM_ENABLE_OUTPUT) && + (portc->trigger_bits & PCM_ENABLE_OUTPUT)) + { + portc->trigger_bits &= ~PCM_ENABLE_OUTPUT; + portc->audio_enabled &= ~PCM_ENABLE_OUTPUT; + gcr_writel (devc, 0x82, 0x00); + OUTB (devc->osdev, 0x8, devc->base + 7); /* acknowledge interrupt */ + } + } + } + + if (portc->open_mode & OPEN_READ) + { + if (state & PCM_ENABLE_INPUT) + { + if ((portc->audio_enabled & PCM_ENABLE_INPUT) && + !(portc->trigger_bits & PCM_ENABLE_INPUT)) + { + old85 = gcr_readl (devc, 0x85); + new85 = (old85 & 0x0000ffff) | 0x00010000; +#if 1 + for (i = 0; i < 5000; i++) + { + if ((INB (devc->osdev, devc->base + 6) & 0x08) == 0x00) + goto RecStart; + oss_udelay (10); + } + RecStart: +#endif + gcr_writel (devc, 0x85, new85); + portc->trigger_bits |= PCM_ENABLE_INPUT; + } + } + else + { + if ((portc->audio_enabled & PCM_ENABLE_INPUT) && + (portc->trigger_bits & PCM_ENABLE_INPUT)) + { + portc->trigger_bits &= ~PCM_ENABLE_INPUT; + portc->audio_enabled &= ~PCM_ENABLE_INPUT; + gcr_writel (devc, 0x85, 0x00); + OUTB (devc->osdev, 0x04, devc->base + 7); /* acknowledge interrupt */ + } + } + } + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); +} + +/*ARGSUSED*/ +unsigned int +FindClosestFreq (als300_devc * devc, unsigned int sr) +{ + unsigned int i, error = 50000, dif, code = 0; + + for (i = 0; i < FNO1; i += 2) + { + if (sr < FreqTable1[i]) + dif = FreqTable1[i] - sr; + else + dif = sr - FreqTable1[i]; + if (dif < error) + { + error = dif; + code = FreqTable1[i + 1]; + } + } + return code; +} + +/*ARGSUSED*/ +static int +als300_audio_prepare_for_input (int dev, int bsize, int bcount) +{ + als300_devc *devc = audio_engines[dev]->devc; + als300_portc *portc = audio_engines[dev]->portc; + dmap_t *dmap = audio_engines[dev]->dmap_in; + oss_native_word flags; + + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); + gcr_writel (devc, 0x85, dmap->fragment_size - 1); + gcr_writel (devc, 0x83, dmap->dmabuf_phys); + gcr_writel (devc, 0x84, dmap->dmabuf_phys + dmap->bytes_in_use - 1); + portc->audio_enabled &= ~PCM_ENABLE_INPUT; + portc->trigger_bits &= ~PCM_ENABLE_INPUT; + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + return 0; +} + +/*ARGSUSED*/ +static int +als300_audio_prepare_for_output (int dev, int bsize, int bcount) +{ + als300_devc *devc = audio_engines[dev]->devc; + als300_portc *portc = audio_engines[dev]->portc; + dmap_t *dmap = audio_engines[dev]->dmap_out; + oss_native_word flags; + + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); + devc->srcode = FindClosestFreq (devc, portc->speed); + gcr_writel (devc, 0x82, (dmap->fragment_size - 1)); + gcr_writel (devc, 0x80, dmap->dmabuf_phys); + gcr_writel (devc, 0x81, dmap->dmabuf_phys + dmap->bytes_in_use - 1); + portc->audio_enabled &= ~PCM_ENABLE_OUTPUT; + portc->trigger_bits &= ~PCM_ENABLE_OUTPUT; + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + return 0; +} + +#if 0 +static int +als300_get_buffer_pointer (int dev, dmap_t * dmap, int direction) +{ + als300_portc *portc = audio_engines[dev]->portc; + als300_devc *devc = audio_engines[dev]->devc; + + unsigned int ptr = 0; + + if (direction == DMODE_OUTPUT) + ptr = gcr_readl (devc, 0x9A); + if (direction == DMODE_INPUT) + ptr = gcr_readl (devc, 0x9B); + return ptr; +} +#endif + +static audiodrv_t als300_audio_driver = { + als300_audio_open, + als300_audio_close, + als300_audio_output_block, + als300_audio_start_input, + als300_audio_ioctl, + als300_audio_prepare_for_input, + als300_audio_prepare_for_output, + als300_audio_reset, + NULL, + NULL, + als300_audio_reset_input, + als300_audio_reset_output, + als300_audio_trigger, + als300_audio_set_rate, + als300_audio_set_format, + als300_audio_set_channels, + NULL, + NULL, + NULL, + NULL, + NULL, /* als300_alloc_buffer */ + NULL, /* als300_free_buffer */ + NULL, + NULL, + NULL /* als300_get_buffer_pointer */ +}; + +#ifdef OBSOLETED_STUFF +/* + * This device has "ISA style" MIDI and FM subsystems. Such devices don't + * use PCI config space for the I/O ports and interrupts. Instead the driver + * needs to allocate proper resources itself. This functionality is no longer + * possible. For this reason the MIDI and FM parts are not accessible. + */ +static void +attach_fm (als300_devc * devc) +{ + if (!opl3_detect (0x388, devc->osdev)) + return; + opl3_init (0x388, devc->osdev); + devc->fm_attached = 1; +} + +static void +attach_mpu (als300_devc * devc) +{ + struct address_info hw_config; + + hw_config.io_base = devc->mpu_base; + hw_config.irq = -devc->irq; + hw_config.dma = -1; + hw_config.dma2 = -1; + hw_config.always_detect = 0; + hw_config.name = "ALS300 MPU"; + hw_config.driver_use_1 = 0; + hw_config.driver_use_2 = 0; + hw_config.osdev = devc->osdev; +#ifdef CREATE_OSP + CREATE_OSP (hw_config.osdev); +#endif + hw_config.card_subtype = 0; + + if (!probe_uart401 (&hw_config)) + { + cmn_err (CE_WARN, "MPU-401 was not detected\n"); + return; + } + devc->mpu_attached = 1; + attach_uart401 (&hw_config); +} + +static void +unload_mpu (als300_devc * devc) +{ + struct address_info hw_config; + + hw_config.io_base = devc->mpu_base; + hw_config.irq = -devc->irq; + hw_config.dma = -1; + hw_config.dma2 = -1; + hw_config.always_detect = 0; + hw_config.name = "ALS300 MPU"; + hw_config.driver_use_1 = 0; + hw_config.driver_use_2 = 0; + hw_config.osdev = devc->osdev; +#ifdef CREATE_OSP + CREATE_OSP (hw_config.osdev); +#endif + hw_config.card_subtype = 0; + + devc->mpu_attached = 0; + unload_uart401 (&hw_config); +} +#endif + +static int +init_als300 (als300_devc * devc) +{ + int my_mixer; + int i; + int adev; + oss_native_word dwTemp; + int first_dev = 0; + + devc->mpu_attached = devc->fm_attached = 0; + +/* + * Enable BusMasterMode and IOSpace Access + */ + switch (devc->model) + { + case MDL_ALS300: + dwTemp = gcr_readl (devc, 0x98); + dwTemp |= devc->mpu_base >> 4; + dwTemp = gcr_readl (devc, 0x98); + dwTemp |= (1 << 19 | 1 << 18 | 1 << 17 | 1 << 16); + gcr_writel (devc, 0x98, dwTemp); + gcr_writel (devc, 0x99, 0); + dwTemp = gcr_readl (devc, 0x8c); + dwTemp |= 0x50; + if (devc->chip_rev < 4) + dwTemp &= ~0x8000; + else + dwTemp |= 0x8000; + gcr_writel (devc, 0x8c, (dwTemp | 0x50)); /*enable INTA */ + break; + + case MDL_ALS300PLUS: + dwTemp = ((oss_native_word) 0x200 << 16) | (0x388); + dwTemp |= 0x00010000; /* enable Game */ + dwTemp |= 0x00000001; /* enable FM */ + gcr_writel (devc, 0xa8, dwTemp); + dwTemp = (oss_native_word) (devc->mpu_base << 16); + dwTemp |= 0x00010000; /* enable MPU */ + gcr_writel (devc, 0xa9, dwTemp); + + dwTemp = gcr_readl (devc, 0x8c); + + gcr_writel (devc, 0x8c, dwTemp | 0x308050); /*enable INTA */ + gcr_writel (devc, 0x99, 0); /* no DDMA */ + break; + } + +#ifdef OBSOLETED_STUFF + attach_fm (devc); + + if (devc->mpu_base > 0) + attach_mpu (devc); +#endif + + if ((my_mixer = + ac97_install (&devc->ac97devc, "ALS300 AC97 Mixer", ac97_read, + ac97_write, devc, devc->osdev)) >= 0) + { + devc->mixer_dev = my_mixer; + } + else + return 0; + + for (i = 0; i < MAX_PORTC; i++) + { + char tmp_name[100]; + als300_portc *portc = &devc->portc[i]; + int caps = ADEV_AUTOMODE; + + if (i == 0) + { + sprintf (tmp_name, "%s (Rev %c)", devc->chip_name, + 'A' + devc->chip_rev); + caps |= ADEV_DUPLEX; + } + else + { + sprintf (tmp_name, "%s (shadow)", devc->chip_name); + caps |= ADEV_DUPLEX | ADEV_SHADOW; + } + + if ((adev = oss_install_audiodev (OSS_AUDIO_DRIVER_VERSION, + devc->osdev, + devc->osdev, + tmp_name, + &als300_audio_driver, + sizeof (audiodrv_t), + caps, + AFMT_U8 | AFMT_S16_LE, devc, -1)) < 0) + { + adev = -1; + return 0; + } + else + { + if (i == 0) + first_dev = adev; + audio_engines[adev]->portc = portc; + audio_engines[adev]->mixer_dev = my_mixer; + audio_engines[adev]->rate_source = first_dev; + audio_engines[adev]->mixer_dev = my_mixer; + audio_engines[adev]->min_block = 4096; + audio_engines[adev]->max_block = 4096; + audio_engines[adev]->min_rate = 5000; + audio_engines[adev]->max_rate = 48000; + audio_engines[adev]->caps |= PCM_CAP_FREERATE; + + portc->open_mode = 0; + portc->audiodev = adev; + portc->audio_enabled = 0; +#ifdef CONFIG_OSS_VMIX + if (i == 0) + vmix_attach_audiodev(devc->osdev, adev, -1, 0); +#endif + } + + } + + return 1; +} + +int +oss_als3xx_attach (oss_device_t * osdev) +{ + unsigned char pci_irq_line, pci_revision; + unsigned short pci_command, vendor, device; + unsigned int pci_ioaddr; + int err; + als300_devc *devc; + + DDB (cmn_err (CE_WARN, "Entered ALS ALS300 probe routine\n")); + + + pci_read_config_word (osdev, PCI_VENDOR_ID, &vendor); + pci_read_config_byte (osdev, PCI_REVISION_ID, &pci_revision); + pci_read_config_word (osdev, PCI_COMMAND, &pci_command); + pci_read_config_word (osdev, PCI_DEVICE_ID, &device); + pci_read_config_irq (osdev, PCI_INTERRUPT_LINE, &pci_irq_line); + pci_read_config_dword (osdev, PCI_BASE_ADDRESS_0, &pci_ioaddr); + + if (vendor != ALS_VENDOR_ID || (device != ALS_300 && device != ALS_300P)) + return 0; + + DDB (cmn_err (CE_WARN, "rev %x I/O base %04x\n", pci_revision, pci_ioaddr)); + + if (pci_ioaddr == 0) + { + cmn_err (CE_WARN, "I/O address not assigned by BIOS.\n"); + return 0; + } + + if (pci_irq_line == 0) + { + cmn_err (CE_WARN, "IRQ not assigned by BIOS (%d).\n", pci_irq_line); + return 0; + } + + if ((devc = PMALLOC (osdev, sizeof (*devc))) == NULL) + { + cmn_err (CE_WARN, "Out of memory\n"); + return 0; + } + + devc->osdev = osdev; + osdev->devc = devc; + devc->open_mode = 0; + + devc->base = MAP_PCI_IOADDR (devc->osdev, 0, pci_ioaddr); + /* Remove I/O space marker in bit 0. */ + devc->base &= ~3; + + devc->irq = pci_irq_line; + devc->mpu_base = als300_mpu_base; + + pci_command |= PCI_COMMAND_MASTER | PCI_COMMAND_IO; + pci_write_config_word (osdev, PCI_COMMAND, pci_command); + + + switch (device) + { + case ALS_300: + devc->model = MDL_ALS300; + devc->chip_name = "Avance Logic ALS300"; + devc->chip_rev = pci_revision; + break; + + case ALS_300P: + devc->model = MDL_ALS300PLUS; + devc->chip_name = "Avance Logic ALS300+"; + devc->chip_rev = pci_revision; + break; + } + + MUTEX_INIT (devc->osdev, devc->mutex, MH_DRV); + MUTEX_INIT (devc->osdev, devc->low_mutex, MH_DRV + 1); + + oss_register_device (osdev, devc->chip_name); + + if ((err = oss_register_interrupts (devc->osdev, 0, als300intr, NULL)) < 0) + { + cmn_err (CE_WARN, "Can't allocate IRQ%d, err=%d\n", pci_irq_line, err); + return 0; + } + + return init_als300 (devc); /* Detected */ +} + +int +oss_als3xx_detach (oss_device_t * osdev) +{ + als300_devc *devc = (als300_devc *) osdev->devc; + unsigned int dwTemp; + + if (oss_disable_device (osdev) < 0) + return 0; + + if (devc->model == MDL_ALS300PLUS) + { + dwTemp = gcr_readl (devc, 0x8c); + gcr_writel (devc, 0x8c, dwTemp &= ~0x8000); + } +#ifdef OBSOLETED_STUFF + if (devc->mpu_attached) + unload_mpu (devc); +#endif + oss_unregister_interrupts (devc->osdev); + + MUTEX_CLEANUP (devc->mutex); + MUTEX_CLEANUP (devc->low_mutex); + UNMAP_PCI_IOADDR (devc->osdev, 0); + + oss_unregister_device (devc->osdev); + return 1; +} diff --git a/attic/drv/oss_als3xx/oss_als3xx.man b/attic/drv/oss_als3xx/oss_als3xx.man new file mode 100644 index 0000000..97b9dcf --- /dev/null +++ b/attic/drv/oss_als3xx/oss_als3xx.man @@ -0,0 +1,19 @@ +NAME +oss_als3xx - Avance Logic ALS300 audio driver. + +DESCRIPTION +Open Sound System driver for Avance Logic ALS300 based soundcards. + +OPTIONS +o als300_mpu_base=<xxx> - set the ALS MPU 401 base I/O adress to one of + the legal values as described in the /plaform/i86pc/kernel/drv/als300.conf + file. This I/O address must not conflict with any other MIDI devices or + any other I/O adapters. + + eg: als3xx_mpu_base=0x300 +FILES +CONFIGFILEPATH/oss_als3xx.conf + +AUTHOR +4Front Technologies + diff --git a/attic/drv/oss_als4k/.config b/attic/drv/oss_als4k/.config new file mode 100644 index 0000000..5280084 --- /dev/null +++ b/attic/drv/oss_als4k/.config @@ -0,0 +1 @@ +platform=i86pc diff --git a/attic/drv/oss_als4k/.devices b/attic/drv/oss_als4k/.devices new file mode 100644 index 0000000..99d4af6 --- /dev/null +++ b/attic/drv/oss_als4k/.devices @@ -0,0 +1 @@ +oss_als4k pci4005,4000 Avance Logic ALS4000 diff --git a/attic/drv/oss_als4k/.name b/attic/drv/oss_als4k/.name new file mode 100644 index 0000000..df310ec --- /dev/null +++ b/attic/drv/oss_als4k/.name @@ -0,0 +1 @@ +Avance Logic ALS4000 diff --git a/attic/drv/oss_als4k/.params b/attic/drv/oss_als4k/.params new file mode 100644 index 0000000..337be40 --- /dev/null +++ b/attic/drv/oss_als4k/.params @@ -0,0 +1,11 @@ +int als4000_mpu_ioaddr=0; +/* + * MPU 401 I/O Address + * Values: 0x300, 0x310, 0x320, 0x330, 0x340, 0x350, 0x360, 0x370 Default: 0x330 + */ + +int als4000_mpu_irq=0; +/* + * MPU 401 IRQ + * Values: 5, 7, 9, 10, 11 Default: 0 + */ diff --git a/attic/drv/oss_als4k/oss_als4k.c b/attic/drv/oss_als4k/oss_als4k.c new file mode 100755 index 0000000..f5f9222 --- /dev/null +++ b/attic/drv/oss_als4k/oss_als4k.c @@ -0,0 +1,1153 @@ +/* + * Purpose: Driver for ALS ALS4000 PCI audio controller. + */ +/* + * + * This file is part of Open Sound System. + * + * Copyright (C) 4Front Technologies 1996-2008. + * + * This this source file is released under GPL v2 license (no other versions). + * See the COPYING file included in the main directory of this source + * distribution for the license terms and conditions. + * + */ + +#include "oss_als4k_cfg.h" +#include "oss_pci.h" + +#define ALS_VENDOR_ID 0x4005 +#define ALS_4000 0x4000 + +#define DSP_RESET (devc->base + 0x16) +#define DSP_READ (devc->base + 0x1A) +#define DSP_WRITE (devc->base + 0x1C) +#define DSP_COMMAND (devc->base + 0x1C) +#define DSP_STATUS (devc->base + 0x1C) +#define DSP_DATA_AVAIL (devc->base + 0x1E) +#define DSP_DATA_AVL16 (devc->base + 0x1F) +#define MIXER_ADDR (devc->base + 0x14) +#define MIXER_DATA (devc->base + 0x15) + +#define DSP_CMD_SPKON 0xD1 +#define DSP_CMD_SPKOFF 0xD3 + +#define ALS_RECORDING_DEVICES (SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD) +#define ALS_MIXER_DEVICES (SOUND_MASK_SYNTH | SOUND_MASK_PCM | \ + SOUND_MASK_LINE | SOUND_MASK_MIC | \ + SOUND_MASK_BASS | SOUND_MASK_TREBLE | \ + SOUND_MASK_IGAIN | SOUND_MASK_CD | \ + SOUND_MASK_VOLUME) +#define ALS4000_RECORDING_DEVICES (ALS_RECORDING_DEVICES) +#define ALS4000_MIXER_DEVICES (ALS_MIXER_DEVICES|SOUND_MASK_LINE2|SOUND_MASK_SPEAKER|SOUND_MASK_RECLEV) + +#define LEFT_CHN 0 +#define RIGHT_CHN 1 + +#define VOC_VOL 0x04 +#define MIC_VOL 0x0A +#define MIC_MIX 0x0A +#define RECORD_SRC 0x0C +#define IN_FILTER 0x0C +#define OUT_FILTER 0x0E +#define MASTER_VOL 0x22 +#define FM_VOL 0x26 +#define CD_VOL 0x28 +#define LINE_VOL 0x2E +#define IRQ_NR 0x80 +#define DMA_NR 0x81 +#define IRQ_STAT 0x82 +#define OPSW 0x3c + +static int default_levels[32] = { + 0x5a5a, /* Master Volume */ + 0x4b4b, /* Bass */ + 0x4b4b, /* Treble */ + 0x4b4b, /* FM */ + 0x4b4b, /* PCM */ + 0x4b4b, /* PC Speaker */ + 0x4b4b, /* Ext Line */ + 0x2020, /* Mic */ + 0x4b4b, /* CD */ + 0x0000, /* Recording monitor */ + 0x4b4b, /* SB PCM */ + 0x4b4b, /* Recording level */ + 0x4b4b, /* Input gain */ + 0x4b4b, /* Output gain */ + 0x4040, /* Line1 */ + 0x4040, /* Line2 */ + 0x1515 /* Line3 */ +}; + +#define MAX_PORTC 2 + +typedef struct als4000_portc +{ + int speed, bits, channels; + int open_mode; + int audio_enabled; + int trigger_bits; + int audiodev; +} +als4000_portc; + +typedef struct als4000_devc +{ + oss_device_t *osdev; + oss_native_word base, mpu_base; + int sb_attached, mpu_attached, fm_attached; + int irq, mpu_irq; + int play_rate_lock, rec_rate_lock; + + char *chip_name; + oss_mutex_t mutex; + oss_mutex_t low_mutex; + + /* Audio parameters */ + int open_mode; + als4000_portc portc[MAX_PORTC]; + oss_native_word srcode; + + /* Mixer parameters */ + int mixer_dev; + int *levels; + int recmask; +} +als4000_devc; + +extern int als4000_mpu_ioaddr; +extern int als4000_mpu_irq; + +void +als4000_gcr_writel (als4000_devc * devc, unsigned char index, + oss_native_word data) +{ + OUTB (devc->osdev, index, devc->base + 0x0c); + OUTL (devc->osdev, data, devc->base + 0x08); +} + + +oss_native_word +als4000_gcr_readl (als4000_devc * devc, unsigned char index) +{ + oss_native_word bufl; + + OUTB (devc->osdev, index, devc->base + 0x0c); + bufl = INL (devc->osdev, devc->base + 0x08); + return (bufl); +} + +static void +als4000_write (als4000_devc * devc, unsigned char val) +{ + int i; + + for (i = 0; i < 100000; i++) + if ((INB (devc->osdev, DSP_STATUS) & 0x80) == 0) + { + OUTB (devc->osdev, val, DSP_COMMAND); + return; + } + + cmn_err (CE_WARN, "Write Command(%x) timed out.\n", val); + return; +} + +static unsigned char +als4000_read (als4000_devc * devc) +{ + int i; + + for (i = 0; i < 100000; i++) + if (INB (devc->osdev, DSP_DATA_AVAIL) & 0x80) + { + return INB (devc->osdev, DSP_READ); + } + + cmn_err (CE_WARN, "Read Command timed out.\n"); + return 0xff; +} + +static void +als4000_setmixer (als4000_devc * devc, unsigned char port, + unsigned char value) +{ + OUTB (devc->osdev, port, MIXER_ADDR); + oss_udelay (20); + OUTB (devc->osdev, value, MIXER_DATA); + //oss_udelay (20); +} + +static unsigned int +als4000_getmixer (als4000_devc * devc, unsigned char port) +{ + unsigned char val; + + OUTB (devc->osdev, port, MIXER_ADDR); + oss_udelay (20); + val = INB (devc->osdev, MIXER_DATA); + //oss_udelay (20); + return val; +} + +struct mixer_def +{ + unsigned int regno:8; + unsigned int bitoffs:4; + unsigned int nbits:4; +}; + +typedef struct mixer_def mixer_tab[32][2]; +typedef struct mixer_def mixer_ent; + +#define MIX_ENT(name, reg_l, bit_l, len_l, reg_r, bit_r, len_r) \ + {{reg_l, bit_l, len_l}, {reg_r, bit_r, len_r}} + +static mixer_tab als4000_mix = { + MIX_ENT (SOUND_MIXER_VOLUME, 0x30, 7, 5, 0x31, 7, 5), + MIX_ENT (SOUND_MIXER_BASS, 0x46, 7, 4, 0x47, 7, 4), + MIX_ENT (SOUND_MIXER_TREBLE, 0x44, 7, 4, 0x45, 7, 4), + MIX_ENT (SOUND_MIXER_SYNTH, 0x34, 7, 5, 0x35, 7, 5), + MIX_ENT (SOUND_MIXER_PCM, 0x32, 7, 5, 0x33, 7, 5), + MIX_ENT (SOUND_MIXER_SPEAKER, 0x3b, 7, 2, 0x00, 0, 0), + MIX_ENT (SOUND_MIXER_LINE, 0x38, 7, 5, 0x39, 7, 5), + MIX_ENT (SOUND_MIXER_MIC, 0x3a, 7, 5, 0x00, 0, 0), + MIX_ENT (SOUND_MIXER_CD, 0x36, 7, 5, 0x37, 7, 5), + MIX_ENT (SOUND_MIXER_IMIX, 0x3c, 0, 1, 0x00, 0, 0), + MIX_ENT (SOUND_MIXER_ALTPCM, 0x00, 0, 0, 0x00, 0, 0), + MIX_ENT (SOUND_MIXER_RECLEV, 0x3f, 7, 2, 0x40, 7, 2), + MIX_ENT (SOUND_MIXER_IGAIN, 0x3f, 7, 2, 0x40, 7, 2), + MIX_ENT (SOUND_MIXER_OGAIN, 0x41, 7, 2, 0x42, 7, 2) +}; + +/*ARGSUSED*/ +static void +change_bits (als4000_devc * devc, unsigned char *regval, int dev, int chn, + int newval) +{ + unsigned char mask; + int shift; + + mask = (1 << als4000_mix[dev][chn].nbits) - 1; + newval = (int) ((newval * mask) + 50) / 100; /* Scale */ + + shift = + als4000_mix[dev][chn].bitoffs - als4000_mix[dev][LEFT_CHN].nbits + 1; + + *regval &= ~(mask << shift); /* Mask out previous value */ + *regval |= (newval & mask) << shift; /* Set the new value */ +} + +static int set_recmask (als4000_devc * devc, int mask); + +static int +als4000_mixer_set (als4000_devc * devc, int dev, int value) +{ + int left = value & 0x000000ff; + int right = (value & 0x0000ff00) >> 8; + + int regoffs; + unsigned char val; + + if (left > 100) + left = 100; + if (right > 100) + right = 100; + + if (dev > 31) + return OSS_EINVAL; + + if (!(ALS4000_MIXER_DEVICES & (1 << dev))) /* + * Not supported + */ + return OSS_EINVAL; + + regoffs = als4000_mix[dev][LEFT_CHN].regno; + + if (regoffs == 0) + return OSS_EINVAL; + + val = als4000_getmixer (devc, regoffs); + change_bits (devc, &val, dev, LEFT_CHN, left); + + devc->levels[dev] = left | (left << 8); + + if (als4000_mix[dev][RIGHT_CHN].regno != regoffs) /* + * Change register + */ + { + als4000_setmixer (devc, regoffs, val); /* + * Save the old one + */ + regoffs = als4000_mix[dev][RIGHT_CHN].regno; + + if (regoffs == 0) + return left | (left << 8); /* + * Just left channel present + */ + + val = als4000_getmixer (devc, regoffs); /* + * Read the new one + */ + } + + change_bits (devc, &val, dev, RIGHT_CHN, right); + + als4000_setmixer (devc, regoffs, val); + + devc->levels[dev] = left | (right << 8); + return left | (right << 8); +} + +/*ARGSUSED*/ +static int +als4000_mixer_ioctl (int dev, int audiodev, unsigned int cmd, ioctl_arg arg) +{ + als4000_devc *devc = mixer_devs[dev]->devc; + int val; + + if (((cmd >> 8) & 0xff) == 'M') + { + if (IOC_IS_OUTPUT (cmd)) + switch (cmd & 0xff) + { + case SOUND_MIXER_RECSRC: + val = *arg; + return *arg = set_recmask (devc, val); + break; + + default: + + val = *arg; + return *arg = als4000_mixer_set (devc, cmd & 0xff, val); + } + else + switch (cmd & 0xff) + { + + case SOUND_MIXER_RECSRC: + return *arg = devc->recmask; + break; + + case SOUND_MIXER_DEVMASK: + return *arg = ALS4000_MIXER_DEVICES; + break; + + case SOUND_MIXER_STEREODEVS: + return *arg = ALS4000_MIXER_DEVICES & + ~(SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_IMIX); + break; + + case SOUND_MIXER_RECMASK: + return *arg = ALS4000_RECORDING_DEVICES; + break; + + case SOUND_MIXER_CAPS: + return *arg = SOUND_CAP_EXCL_INPUT; + break; + + + default: + return *arg = devc->levels[cmd & 0x1f]; + } + } + else + return OSS_EINVAL; +} + + +static void +set_recsrc (als4000_devc * devc, int src) +{ + als4000_setmixer (devc, RECORD_SRC, + (als4000_getmixer (devc, RECORD_SRC) & ~7) | (src & 0x7)); +} + +static int +set_recmask (als4000_devc * devc, int mask) +{ + int devmask = mask & ALS4000_RECORDING_DEVICES; + + if (devmask != SOUND_MASK_MIC && + devmask != SOUND_MASK_LINE && devmask != SOUND_MASK_CD) + { /* + * More than one devices selected. Drop the * + * previous selection + */ + devmask &= ~devc->recmask; + } + + if (devmask != SOUND_MASK_MIC && + devmask != SOUND_MASK_LINE && devmask != SOUND_MASK_CD) + { /* + * More than one devices selected. Default to + * * mic + */ + devmask = SOUND_MASK_MIC; + } + + + if (devmask ^ devc->recmask) /* + * Input source changed + */ + { + switch (devmask) + { + + case SOUND_MASK_MIC: + set_recsrc (devc, 0); + break; + + case SOUND_MASK_LINE: + set_recsrc (devc, 6); + break; + + case SOUND_MASK_CD: + set_recsrc (devc, 2); + break; + + + default: + set_recsrc (devc, 0); + } + } + + devc->recmask = devmask; + return devc->recmask; +} + +static void +als4000_mixer_reset (als4000_devc * devc) +{ + char name[32]; + int i; + + sprintf (name, "ALS4000"); + + devc->levels = load_mixer_volumes (name, default_levels, 1); + devc->recmask = 0; + + for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) + als4000_mixer_set (devc, i, devc->levels[i]); + + set_recmask (devc, SOUND_MASK_MIC); +} + + +static mixer_driver_t als4000_mixer_driver = { + als4000_mixer_ioctl +}; + +static int +als4000intr (oss_device_t * osdev) +{ + als4000_devc *devc = (als4000_devc *) osdev->devc; + unsigned int status, i; + unsigned char mxstat; + int serviced = 0; + + + status = INB (devc->osdev, devc->base + 0x0e); + + for (i = 0; i < MAX_PORTC; i++) + { + als4000_portc *portc = &devc->portc[i]; + + if ((status & 0x80) && (portc->trigger_bits & PCM_ENABLE_OUTPUT)) + { + serviced = 1; + oss_audio_outputintr (portc->audiodev, 1); + } + if ((status & 0x40) && (portc->trigger_bits & PCM_ENABLE_INPUT)) + { + serviced = 1; + oss_audio_inputintr (portc->audiodev, 0); + } + } + + OUTB (devc->osdev, status, devc->base + 0x0e); /* acknowledge interrupt */ + +#if 0 + if (status & 0x10) + { + serviced = 1; + uart401intr (INT_HANDLER_CALL (devc->mpu_irq)); + } +#endif + mxstat = als4000_getmixer (devc, 0x82); + switch (mxstat) + { + case 0x1: + INB (devc->osdev, devc->base + 0x1e); + break; + case 0x2: + INB (devc->osdev, devc->base + 0x1f); + break; + case 0x4: + INB (devc->osdev, devc->base + 0x30); + break; + case 0x20: + INB (devc->osdev, devc->base + 0x16); + break; + } + return serviced; +} + +static int +als4000_audio_set_rate (int dev, int arg) +{ + als4000_portc *portc = audio_engines[dev]->portc; + + if (arg == 0) + return portc->speed; + + if (arg > 48000) + arg = 48000; + if (arg < 5000) + arg = 5000; + portc->speed = arg; + + return portc->speed; +} + +static short +als4000_audio_set_channels (int dev, short arg) +{ + als4000_portc *portc = audio_engines[dev]->portc; + + if ((arg != 1) && (arg != 2)) + return portc->channels; + portc->channels = arg; + + return portc->channels; +} + +static unsigned int +als4000_audio_set_format (int dev, unsigned int arg) +{ + als4000_portc *portc = audio_engines[dev]->portc; + + if (arg == 0) + return portc->bits; + + if (!(arg & (AFMT_U8 | AFMT_S16_LE))) + return portc->bits; + portc->bits = arg; + + return portc->bits; +} + +static void +als4000_speed (als4000_devc * devc, int speed) +{ + if (!(devc->play_rate_lock | devc->rec_rate_lock)) + { + als4000_write (devc, 0x41); + als4000_write (devc, (speed >> 8) & 0xFF); + als4000_write (devc, speed & 0xFF); + } +} + +/*ARGSUSED*/ +static int +als4000_audio_ioctl (int dev, unsigned int cmd, ioctl_arg arg) +{ + return OSS_EINVAL; +} + +static int +als4000_reset (als4000_devc * devc) +{ + int i; + unsigned char byte; + DDB (cmn_err (CE_WARN, "Entered als4000_reset()\n")); + + OUTB (devc->osdev, 1, DSP_RESET); + oss_udelay (20); + OUTB (devc->osdev, 0, DSP_RESET); + + byte = als4000_read (devc); + for (i = 0; i < 10000; i++) + if (byte != 0xAA) + { + DDB (cmn_err (CE_WARN, "No response to RESET\n")); + return 0; /* Sorry */ + } + + DDB (cmn_err (CE_WARN, "als4000_reset() OK\n")); + return 1; +} + +static void als4000_audio_trigger (int dev, int state); + +static void +als4000_audio_reset (int dev) +{ + als4000_audio_trigger (dev, 0); +} + +static void +als4000_audio_reset_input (int dev) +{ + als4000_portc *portc = audio_engines[dev]->portc; + als4000_audio_trigger (dev, portc->trigger_bits & ~PCM_ENABLE_INPUT); +} + +static void +als4000_audio_reset_output (int dev) +{ + als4000_portc *portc = audio_engines[dev]->portc; + als4000_audio_trigger (dev, portc->trigger_bits & ~PCM_ENABLE_OUTPUT); +} + +/*ARGSUSED*/ +static int +als4000_audio_open (int dev, int mode, int open_flags) +{ + als4000_portc *portc = audio_engines[dev]->portc; + als4000_devc *devc = audio_engines[dev]->devc; + oss_native_word flags; + + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); + if (portc->open_mode) + { + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + return OSS_EBUSY; + } + + if (devc->open_mode & mode) + { + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + return OSS_EBUSY; + } + + devc->open_mode |= mode; + + portc->open_mode = mode; + portc->audio_enabled &= ~mode; + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + + return 0; +} + +static void +als4000_audio_close (int dev, int mode) +{ + als4000_portc *portc = audio_engines[dev]->portc; + als4000_devc *devc = audio_engines[dev]->devc; + + als4000_audio_reset (dev); + als4000_reset (devc); + portc->open_mode = 0; + devc->open_mode &= ~mode; + portc->audio_enabled &= ~mode; +} + +/*ARGSUSED*/ +static void +als4000_audio_output_block (int dev, oss_native_word buf, int count, + int fragsize, int intrflag) +{ + als4000_portc *portc = audio_engines[dev]->portc; + + portc->audio_enabled |= PCM_ENABLE_OUTPUT; + portc->trigger_bits &= ~PCM_ENABLE_OUTPUT; +} + +/*ARGSUSED*/ +static void +als4000_audio_start_input (int dev, oss_native_word buf, int count, + int fragsize, int intrflag) +{ + als4000_portc *portc = audio_engines[dev]->portc; + + portc->audio_enabled |= PCM_ENABLE_INPUT; + portc->trigger_bits &= ~PCM_ENABLE_INPUT; +} + +static void +als4000_audio_trigger (int dev, int state) +{ + als4000_portc *portc = audio_engines[dev]->portc; + als4000_devc *devc = audio_engines[dev]->devc; + oss_native_word flags; + + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); + if (portc->open_mode & OPEN_WRITE) + { + if (state & PCM_ENABLE_OUTPUT) + { + if ((portc->audio_enabled & PCM_ENABLE_OUTPUT) && + !(portc->trigger_bits & PCM_ENABLE_OUTPUT)) + { + if (portc->bits == AFMT_U8) + als4000_write (devc, 0xd6); /*start 8bit dma */ + else + als4000_write (devc, 0xd4); /*start 16bit dma */ + devc->play_rate_lock = 1; + portc->trigger_bits |= PCM_ENABLE_OUTPUT; + } + } + else + { + if ((portc->audio_enabled & PCM_ENABLE_OUTPUT) && + (portc->trigger_bits & PCM_ENABLE_OUTPUT)) + { + portc->audio_enabled &= ~PCM_ENABLE_OUTPUT; + portc->trigger_bits &= ~PCM_ENABLE_OUTPUT; + if (portc->bits == AFMT_U8) + als4000_write (devc, 0xd0); /*exit 8bit dma */ + else + als4000_write (devc, 0xd5); /*exit 16bit dma */ + devc->play_rate_lock = 0; + } + } + } + + if (portc->open_mode & OPEN_READ) + { + if (state & PCM_ENABLE_INPUT) + { + if ((portc->audio_enabled & PCM_ENABLE_INPUT) && + !(portc->trigger_bits & PCM_ENABLE_INPUT)) + { + /* start recording */ + als4000_setmixer (devc, 0xde, + als4000_getmixer (devc, 0xde) | 0x80); + devc->rec_rate_lock = 1; + portc->trigger_bits |= PCM_ENABLE_INPUT; + } + } + else + { + if ((portc->audio_enabled & PCM_ENABLE_INPUT) && + (portc->trigger_bits & PCM_ENABLE_INPUT)) + { + portc->audio_enabled &= ~PCM_ENABLE_INPUT; + portc->trigger_bits &= ~PCM_ENABLE_INPUT; + /* stop recording */ + als4000_setmixer (devc, 0xde, + als4000_getmixer (devc, 0xde) & ~0x80); + devc->rec_rate_lock = 0; + } + } + } + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); +} + +/*ARGSUSED*/ +static int +als4000_audio_prepare_for_input (int dev, int bsize, int bcount) +{ + als4000_devc *devc = audio_engines[dev]->devc; + als4000_portc *portc = audio_engines[dev]->portc; + dmap_t *dmap = audio_engines[dev]->dmap_in; + oss_native_word flags; + int cnt, bits; + + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); + /* set speed */ + als4000_speed (devc, portc->speed); + + /* set mode */ + if (portc->bits == AFMT_S16_LE) + bits = 0x10; /*signed 16bit */ + else + bits = 0x04; /*unsigned 8bit */ + if (portc->channels == 2) + bits |= 0x20; /*stereo */ + als4000_setmixer (devc, 0xde, bits); + + /* set size and buffer address */ + als4000_gcr_writel (devc, 0xa2, dmap->dmabuf_phys); + als4000_gcr_writel (devc, 0xa3, dmap->bytes_in_use - 1); + + /* set tranfersize */ + cnt = dmap->fragment_size; + if (portc->bits == AFMT_S16_LE) + cnt >>= 1; + cnt--; + + als4000_setmixer (devc, 0xdc, cnt & 0xFF); + als4000_setmixer (devc, 0xdd, (cnt >> 8) & 0xFF); + + portc->audio_enabled &= ~PCM_ENABLE_INPUT; + portc->trigger_bits &= ~PCM_ENABLE_INPUT; + + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + return 0; +} + +/*ARGSUSED*/ +static int +als4000_audio_prepare_for_output (int dev, int bsize, int bcount) +{ + als4000_devc *devc = audio_engines[dev]->devc; + als4000_portc *portc = audio_engines[dev]->portc; + dmap_t *dmap = audio_engines[dev]->dmap_out; + oss_native_word flags; + int cnt; + + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); + /* set speed */ + als4000_speed (devc, portc->speed); + + /* set mode */ + als4000_write (devc, (portc->bits == AFMT_S16_LE ? 0xb6 : 0xc6)); + als4000_write (devc, ((portc->channels == 2 ? 0x20 : 0) + + (portc->bits == AFMT_S16_LE ? 0x10 : 0))); + + + /* set size and buffer address */ + als4000_gcr_writel (devc, 0x91, dmap->dmabuf_phys); + als4000_gcr_writel (devc, 0x92, (dmap->bytes_in_use - 1) | 0x00180000); + + /* set transfer size */ + cnt = dmap->fragment_size; + if (portc->bits == AFMT_S16_LE) + cnt >>= 1; + cnt--; + + als4000_write (devc, cnt & 0xff); /*length low */ + als4000_write (devc, (cnt >> 8)); /*length high */ + + als4000_write (devc, 0xd1); /* turn on speaker */ + + portc->audio_enabled &= ~PCM_ENABLE_OUTPUT; + portc->trigger_bits &= ~PCM_ENABLE_OUTPUT; + + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + return 0; +} + +static int +als4000_get_buffer_pointer (int dev, dmap_t * dmap, int direction) +{ + als4000_devc *devc = audio_engines[dev]->devc; + unsigned int ptr; + + if (direction == PCM_ENABLE_OUTPUT) + ptr = als4000_gcr_readl (devc, 0xa0); + else + ptr = als4000_gcr_readl (devc, 0xa4); + + return (ptr - dmap->dmabuf_phys) % dmap->bytes_in_use; +} + + +static audiodrv_t als4000_audio_driver = { + als4000_audio_open, + als4000_audio_close, + als4000_audio_output_block, + als4000_audio_start_input, + als4000_audio_ioctl, + als4000_audio_prepare_for_input, + als4000_audio_prepare_for_output, + als4000_audio_reset, + NULL, + NULL, + als4000_audio_reset_input, + als4000_audio_reset_output, + als4000_audio_trigger, + als4000_audio_set_rate, + als4000_audio_set_format, + als4000_audio_set_channels, + NULL, + NULL, + NULL, + NULL, + NULL, /* als4000_alloc_buffer, */ + NULL, /* als4000_free_buffer, */ + NULL, + NULL, + als4000_get_buffer_pointer +}; + +#ifdef OBSOLETED_STUFF +/* + * This device has "ISA style" MIDI and FM subsystems. Such devices don't + * use PCI config space for the I/O ports and interrupts. Instead the driver + * needs to allocate proper resources itself. This functionality is no longer + * possible. For this reason the MIDI and FM parts are not accessible. + */ +static void +attach_fm (als4000_devc * devc) +{ + if (!opl3_detect (0x388, devc->osdev)) + return; + opl3_init (0x388, devc->osdev); + devc->fm_attached = 1; +} + +static void +attach_mpu (als4000_devc * devc) +{ + struct address_info hw_config; + + hw_config.io_base = devc->mpu_base; + hw_config.irq = devc->mpu_irq; + hw_config.dma = -1; + hw_config.dma2 = -1; + hw_config.always_detect = 0; + hw_config.name = "Avance Logic ALS4000 MPU"; + hw_config.driver_use_1 = 0; + hw_config.driver_use_2 = 0; + hw_config.osdev = devc->osdev; +#ifdef CREATE_OSP + CREATE_OSP (hw_config.osdev); +#endif + hw_config.card_subtype = 0; + + if (!probe_uart401 (&hw_config)) + { + cmn_err (CE_WARN, "MPU-401 was not detected\n"); + return; + } + devc->mpu_attached = 1; + attach_uart401 (&hw_config); +} + +static void +unload_mpu (als4000_devc * devc) +{ + struct address_info hw_config; + + hw_config.io_base = devc->mpu_base; + hw_config.irq = devc->mpu_irq; + hw_config.dma = -1; + hw_config.dma2 = -1; + hw_config.always_detect = 0; + hw_config.name = "Avance Logic ALS4000 MPU"; + hw_config.driver_use_1 = 0; + hw_config.driver_use_2 = 0; + hw_config.osdev = devc->osdev; +#ifdef CREATE_OSP + CREATE_OSP (hw_config.osdev); +#endif + hw_config.card_subtype = 0; + + devc->mpu_attached = 0; + unload_uart401 (&hw_config); +} +#endif + +void +setup_als4000 (als4000_devc * devc) +{ + unsigned char byte, i; + oss_native_word dwTemp; + + dwTemp = ((oss_native_word) 0x200 << 16) | (0x388); + dwTemp |= 0x00010000; + dwTemp |= 0x00000001; + als4000_gcr_writel (devc, 0xa8, dwTemp); + dwTemp = ((oss_native_word) devc->mpu_base << 16); + dwTemp |= 0x00010000; + als4000_gcr_writel (devc, 0xa9, dwTemp); + + byte = als4000_getmixer (devc, 0xc0); + als4000_setmixer (devc, 0xc0, byte | 0x80); /*disable M80/M81 write protect */ + als4000_setmixer (devc, 0x81, 0x01); + als4000_setmixer (devc, 0xc0, (byte & 0x7F)); /*set M80/M81 write protect */ + + dwTemp = als4000_gcr_readl (devc, 0x8c); + als4000_gcr_writel (devc, 0x8c, dwTemp | 0x00028000); /*enable INTA */ + + for (i = 0x91; i < 0xa7; i++) + als4000_gcr_writel (devc, i, 0x00); + dwTemp = als4000_gcr_readl (devc, 0x99); + als4000_gcr_writel (devc, 0x99, dwTemp | 0x100); +} + + +static int +init_als4000 (als4000_devc * devc) +{ + int my_mixer; + int first_dev = 0; + unsigned char byte; + int i; + int adev; + + devc->mpu_attached = devc->fm_attached = 0; + + setup_als4000 (devc); + +#ifdef OBSOLETED_STUFF + attach_fm (devc); + if (devc->mpu_base > 0) + attach_mpu (devc); +#endif + + /* check ESP */ + als4000_write (devc, 0xE4); + als4000_write (devc, 0xaa); + als4000_write (devc, 0xE8); + byte = als4000_read (devc); + if (byte != 0xaa) + { + DDB (cmn_err (CE_WARN, "ESP Not OK\n")); + return 0; + } + + /* reset the DSP */ + als4000_reset (devc); + + if ((my_mixer = oss_install_mixer (OSS_MIXER_DRIVER_VERSION, + devc->osdev, + devc->osdev, + "Avance Logic ALS4000", + &als4000_mixer_driver, + sizeof (mixer_driver_t), devc)) < 0) + { + return 0; + } + als4000_mixer_reset (devc); + + for (i = 0; i < MAX_PORTC; i++) + { + char tmp_name[100]; + als4000_portc *portc = &devc->portc[i]; + int caps = ADEV_AUTOMODE; + + if (i == 0) + { + strcpy (tmp_name, devc->chip_name); + caps |= ADEV_DUPLEX; + } + else + { + strcpy (tmp_name, devc->chip_name); + caps |= ADEV_DUPLEX | ADEV_SHADOW; + } + + if ((adev = oss_install_audiodev (OSS_AUDIO_DRIVER_VERSION, + devc->osdev, + devc->osdev, + tmp_name, + &als4000_audio_driver, + sizeof (audiodrv_t), + caps, + AFMT_U8 | AFMT_S16_LE, devc, -1)) < 0) + { + adev = -1; + return 0; + } + else + { + if (i == 0) + first_dev = adev; + audio_engines[adev]->portc = portc; + audio_engines[adev]->rate_source = first_dev; + audio_engines[adev]->mixer_dev = my_mixer; + audio_engines[adev]->min_rate = 5000; + audio_engines[adev]->max_rate = 48000; + audio_engines[adev]->dmabuf_maxaddr = MEMLIMIT_ISA; + portc->open_mode = 0; + portc->audiodev = adev; + portc->audio_enabled = 0; +#ifdef CONFIG_OSS_VMIX + if (i == 0) + vmix_attach_audiodev(devc->osdev, adev, -1, 0); +#endif + } + } + return 1; +} + +int +oss_als4k_attach (oss_device_t * osdev) +{ + + unsigned char pci_irq_line, pci_revision; + unsigned short pci_command, vendor, device; + unsigned int pci_ioaddr; + int err; + als4000_devc *devc; + + DDB (cmn_err (CE_WARN, "Entered ALS ALS4000 probe routine\n")); + + pci_read_config_word (osdev, PCI_VENDOR_ID, &vendor); + pci_read_config_byte (osdev, PCI_REVISION_ID, &pci_revision); + pci_read_config_word (osdev, PCI_COMMAND, &pci_command); + pci_read_config_word (osdev, PCI_DEVICE_ID, &device); + pci_read_config_irq (osdev, PCI_INTERRUPT_LINE, &pci_irq_line); + pci_read_config_dword (osdev, PCI_BASE_ADDRESS_0, &pci_ioaddr); + + if (vendor != ALS_VENDOR_ID || device != ALS_4000) + return 0; + + DDB (cmn_err (CE_WARN, "ALS4000 I/O base %04x\n", pci_ioaddr)); + + if (pci_ioaddr == 0) + { + cmn_err (CE_WARN, "I/O address not assigned by BIOS.\n"); + return 0; + } + + if (pci_irq_line == 0) + { + cmn_err (CE_WARN, "IRQ not assigned by BIOS (%d).\n", pci_irq_line); + return 0; + } + + if ((devc = PMALLOC (osdev, sizeof (*devc))) == NULL) + { + cmn_err (CE_WARN, "Out of memory\n"); + return 0; + } + + devc->osdev = osdev; + osdev->devc = devc; + devc->irq = pci_irq_line; + devc->chip_name = "Avance Logic ALS4000"; + devc->mpu_base = als4000_mpu_ioaddr; + devc->mpu_irq = als4000_mpu_irq; + + + devc->base = MAP_PCI_IOADDR (devc->osdev, 0, pci_ioaddr); + /* Remove I/O space marker in bit 0. */ + devc->base &= ~3; + + pci_command |= PCI_COMMAND_MASTER | PCI_COMMAND_IO; + pci_write_config_word (osdev, PCI_COMMAND, pci_command); + + MUTEX_INIT (devc->osdev, devc->mutex, MH_DRV); + MUTEX_INIT (devc->osdev, devc->low_mutex, MH_DRV + 1); + + oss_register_device (osdev, devc->chip_name); + + if ((err = oss_register_interrupts (devc->osdev, 0, als4000intr, NULL)) < 0) + { + cmn_err (CE_WARN, "Error installing interrupt handler: %x\n", err); + return 0; + } + + return init_als4000 (devc); /* Detected */ +} + + +int +oss_als4k_detach (oss_device_t * osdev) +{ + als4000_devc *devc = (als4000_devc *) osdev->devc; + + if (oss_disable_device (osdev) < 0) + return 0; + + als4000_gcr_writel (devc, 0x8c, 0x0); + +#ifdef OBSOLETED_STUFF + if (devc->mpu_attached) + unload_mpu (devc); +#endif + + oss_unregister_interrupts (devc->osdev); + + MUTEX_CLEANUP (devc->mutex); + MUTEX_CLEANUP (devc->low_mutex); + UNMAP_PCI_IOADDR (devc->osdev, 0); + + oss_unregister_device (devc->osdev); + return 1; +} diff --git a/attic/drv/oss_als4k/oss_als4k.man b/attic/drv/oss_als4k/oss_als4k.man new file mode 100644 index 0000000..ace289f --- /dev/null +++ b/attic/drv/oss_als4k/oss_als4k.man @@ -0,0 +1,23 @@ +NAME +oss_als4k - ALS4000 audio driver. + +DESCRIPTION +Open Sound System driver for Avance Logic ALS4000 based soundcards. +ALS4000 characteristics: + o 8/16 bit + o mono/stereo + o 8Khz - 48Khz sampling rates + o FM Synthesis + o MIDI UART401 + +The ALS4000 has a Sound Blaster compatible mixer device. + +OPTIONS +None + +FILES +CONFIGFILEPATH/oss_als4k.conf + +AUTHOR +4Front Technologies + diff --git a/attic/drv/oss_digi32/.devices b/attic/drv/oss_digi32/.devices new file mode 100644 index 0000000..84782e9 --- /dev/null +++ b/attic/drv/oss_digi32/.devices @@ -0,0 +1,3 @@ +oss_digi32 pciea60,9896 RME Digi32 +oss_digi32 pciea60,9897 RME Digi32 Pro +oss_digi32 pciea60,9898 RME Digi32/8 diff --git a/attic/drv/oss_digi32/.name b/attic/drv/oss_digi32/.name new file mode 100644 index 0000000..c523b73 --- /dev/null +++ b/attic/drv/oss_digi32/.name @@ -0,0 +1 @@ +RME Digi32 diff --git a/attic/drv/oss_digi32/.params b/attic/drv/oss_digi32/.params new file mode 100644 index 0000000..89da064 --- /dev/null +++ b/attic/drv/oss_digi32/.params @@ -0,0 +1,7 @@ +int digi32_buffsize=64; +/* + * By default the Digi32 driver will allocate 64k of buffer both for + * recording and playback functions. This should be sufficient in most cases. + * If necessary the buffer sizes can be increased. + * Values: 64-128 Default: 64 + */ diff --git a/attic/drv/oss_digi32/oss_digi32.c b/attic/drv/oss_digi32/oss_digi32.c new file mode 100644 index 0000000..6bb1169 --- /dev/null +++ b/attic/drv/oss_digi32/oss_digi32.c @@ -0,0 +1,997 @@ +/* + * Purpose: Driver for RME Digi32 family + */ +/* + * + * This file is part of Open Sound System. + * + * Copyright (C) 4Front Technologies 1996-2008. + * + * This this source file is released under GPL v2 license (no other versions). + * See the COPYING file included in the main directory of this source + * distribution for the license terms and conditions. + * + */ + +#include "oss_digi32_cfg.h" +#include "oss_pci.h" + +#define RME_VENDOR_ID 0xea60 +#define RME_DIGI32 0x9896 +#define RME_DIGI32_PRO 0x9897 +#define RME_DIGI32_8 0x9898 + +#define RME_VENDOR_ID2 0x10ee +#define RME_DIGI96_8_PRO 0x3fc2 + +#define MAX_AUDIO_CHANNEL 4 + +/* + * Control register bits + */ +#define C_EMP 0x8000 +#define C_PD 0x4000 +#define C_AUTOSYNC 0x2000 +#define C_ADAT 0x1000 +#define C_DS 0x0800 +#define C_BM 0x0800 +#define C_PRO 0x0400 +#define C_MUTE 0x0200 +#define C_RESET 0x0100 +#define C_INP_1 0x0080 +#define C_INP_0 0x0040 +#define C_FREQ_1 0x0020 +#define C_FREQ_0 0x0010 +#define C_SEL 0x0008 +#define C_MODE24 0x0004 +#define C_MONO 0x0002 +#define C_START 0x0001 + +/* + * Status register bits + */ +#define S_INTR 0x80000000 +#define S_KMODE 0x40000000 /* 0=Quartz mode, 1=PLL mode */ +#define S_FBITS 0x38000000 /* F bits of CS8412/14 */ +#define S_FSHIFT 27 +#define S_ERF 0x04000000 /* ERF of the CS8412. 1=error */ +#define S_REV 0x0x300000 /* Revision bits */ +#define S_ADATLOCK 0x00080000 /* ADAT PLL locked */ + +typedef struct digi32_portc +{ + int open_mode; + int audio_dev; + int voice_chn; + int type; +#define TY_IN 1 +#define TY_OUT 2 +#define TY_BOTH 3 + + int active; + int channels; + int speed; + int speedsel; + int bits; + int inptr, outptr; + int tmp_autosync; + int bytes_per_sample; + int trigger_bits; +} +digi32_portc; + +typedef struct digi32_devc +{ + oss_device_t *osdev; + oss_mutex_t mutex; + char *chip_name; + int model; +#define MDL_BASIC 0 +#define MDL_8 1 +#define MDL_PRO 2 +#define MDL_96_8_PRO 3 + + int cs841x_part; +#define CS8412 0 +#define CS8414 1 + + unsigned int cmd; + + oss_native_word physaddr; + char *linaddr; + unsigned int *pFIFO; + unsigned int *pCTRL; + + int irq; + + digi32_portc portc[MAX_AUDIO_CHANNEL]; + int open_count; + int mixer_dev; + + int speed_locked; + int active_device_count; +} +digi32_devc; + +static int fbit_tab[2][8] = { + {0, 48000, 44100, 32000, 48000, 44100, 44056, 32000}, + {0, 0, 0, 96000, 88200, 48000, 44100, 32000} +}; + + +static void +write_command (digi32_devc * devc, unsigned int ctrl) +{ + devc->cmd = ctrl; + + PCI_WRITEL (devc->osdev, devc->pCTRL, ctrl); +} + +/*ARGSUSED*/ +static void +handle_recording (int dev) +{ + digi32_portc *portc = audio_engines[dev]->portc; + digi32_devc *devc = audio_engines[dev]->devc; + + int i, p; + unsigned int *buf; + + p = portc->inptr / 4; /* Dword addressing */ + buf = + (unsigned int *) &audio_engines[dev]->dmap_in-> + dmabuf[dmap_get_qtail (audio_engines[dev]->dmap_in) * + audio_engines[dev]->dmap_in->fragment_size]; + + /* Perform copy with channel swapping */ + if (portc->bytes_per_sample == 4) + { + /* 32 bit mode */ + for (i = 0; i < (8 * 1024) / 4; i += 2) + { + buf[i] = PCI_READL (devc->osdev, devc->pFIFO + i + 1 + p); + buf[i + 1] = PCI_READL (devc->osdev, devc->pFIFO + i + p); + } + } + else + { + /* 16 bit mode */ + unsigned int tmp; + + for (i = 0; i < (8 * 1024) / 4; i++) + { + tmp = PCI_READL (devc->osdev, devc->pFIFO + i + p); + buf[i] = ((tmp >> 16) & 0xffff) | ((tmp & 0xffff) << 16); + } + } + + if (!(portc->trigger_bits & PCM_ENABLE_OUTPUT)) /* Clean the samples */ + for (i = 0; i < (8 * 1024) / 4; i++) + { + PCI_WRITEL (devc->osdev, devc->pFIFO + i + p, 0); + } + + portc->inptr = (portc->inptr + (8 * 1024)) % (128 * 1024); /* Increment the pointer */ +} + +static int +digi32intr (oss_device_t * osdev) +{ + unsigned int status; + digi32_devc *devc = (digi32_devc *) osdev->devc; + digi32_portc *portc; + int i; + + status = PCI_READL (devc->osdev, devc->pCTRL); + if (!(status & S_INTR)) + return 0; + + for (i = 0; i < 2; i++) + { + portc = &devc->portc[i]; + + if (portc->trigger_bits & PCM_ENABLE_INPUT) + { + handle_recording (portc->audio_dev); + if (status & S_ERF && !(devc->cmd & C_AUTOSYNC)) + { + cmn_err (CE_WARN, "External sync dropped\n"); +#if 0 + devc->cmd |= C_AUTOSYNC; + write_command (devc, devc->cmd); +#endif + } + else + oss_audio_inputintr (portc->audio_dev, 0); + } + + if (portc->trigger_bits & PCM_ENABLE_OUTPUT) + { + oss_audio_outputintr (portc->audio_dev, 1); + } + } + write_command (devc, devc->cmd); /* Interrupt acknowledge */ + + return 1; +} + + +/*********************************** + * Audio routines + ***********************************/ + +static int +digi32_set_rate (int dev, int arg) +{ + digi32_devc *devc = audio_engines[dev]->devc; + digi32_portc *portc = audio_engines[dev]->portc; + + static int speed_table[6] = { 32000, 44100, 48000, 64000, 88200, 96000 }; + int n, i, best = 2, dif, bestdif = 0x7fffffff; + + if (arg == 0 || devc->active_device_count > 0 || devc->speed_locked) + arg = portc->speed; + + n = (devc->model == MDL_PRO) ? 6 : 3; + + for (i = 0; i < n; i++) + { + if (arg == speed_table[i]) /* Exact match */ + { + portc->speed = arg; + portc->speedsel = i; + return portc->speed; + } + + dif = arg - speed_table[i]; + if (dif < 0) + dif *= -1; + if (dif <= bestdif) + { + best = i; + bestdif = dif; + } + + } + + portc->speed = speed_table[best]; + portc->speedsel = best; + return portc->speed; +} + +static short +digi32_set_channels (int dev, short arg) +{ + digi32_portc *portc = audio_engines[dev]->portc; + + if ((arg == 0)) + return portc->channels; + arg = 2; + portc->channels = arg; + + return portc->channels; +} + +static unsigned int +digi32_set_format (int dev, unsigned int arg) +{ + digi32_devc *devc = audio_engines[dev]->devc; + digi32_portc *portc = audio_engines[dev]->portc; + + if (arg == 0 || devc->active_device_count > 0) + return portc->bits; + + if (arg != AFMT_S16_NE && arg != AFMT_S32_NE && arg != AFMT_AC3) + arg = AFMT_S16_NE; + + portc->bytes_per_sample = (arg & (AFMT_S32_LE | AFMT_S32_BE)) ? 4 : 2; + portc->bits = arg; + + return portc->bits; +} + +/*ARGSUSED*/ +static int +digi32_ioctl (int dev, unsigned int cmd, ioctl_arg arg) +{ + return OSS_EINVAL; +} + +static void digi32_trigger (int dev, int state); + +static void +digi32_reset (int dev) +{ + digi32_trigger (dev, 0); +} + +static void +digi32_reset_input (int dev) +{ + digi32_portc *portc = audio_engines[dev]->portc; + digi32_trigger (dev, portc->trigger_bits & ~PCM_ENABLE_INPUT); +} + +static void +digi32_reset_output (int dev) +{ + digi32_portc *portc = audio_engines[dev]->portc; + digi32_trigger (dev, portc->trigger_bits & ~PCM_ENABLE_OUTPUT); +} + +static void digi32_close (int dev, int mode); + +/*ARGSUSED*/ +static int +digi32_open (int dev, int mode, int open_flags) +{ + digi32_portc *portc = audio_engines[dev]->portc; + digi32_devc *devc = audio_engines[dev]->devc; + int i; + oss_native_word flags; + + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); + if (portc->open_mode != 0) + { + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + return OSS_EBUSY; + } + + portc->open_mode = mode; + portc->audio_dev = dev; + devc->speed_locked = 0; + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + + for (i = 0; i < 32 * 1024; i++) + PCI_WRITEL (devc->osdev, devc->pFIFO + i, 0); /* Clean the buffer */ + return 0; +} + +/*ARGSUSED*/ +static void +digi32_close (int dev, int mode) +{ + digi32_portc *portc = audio_engines[dev]->portc; + digi32_devc *devc = audio_engines[dev]->devc; + oss_native_word flags; + + digi32_reset (dev); + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); + portc->open_mode = 0; + portc->active = 0; + if (portc->tmp_autosync) + { + portc->tmp_autosync = 0; + devc->cmd |= C_AUTOSYNC; + write_command (devc, devc->cmd); + } + +/* + * Inactivate all auxiliary channels allocated for this device + */ + + if (--devc->open_count <= 0) + { + devc->open_count = 0; + } + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); +} + +/*ARGSUSED*/ +static void +digi32_output_block (int dev, oss_native_word ptr, int count, int fragsize, + int intrflag) +{ + digi32_portc *portc = audio_engines[dev]->portc; + digi32_devc *devc = audio_engines[dev]->devc; + + int i, p; + unsigned int *buf; + + p = portc->outptr / 4; /* Dword addressing */ + buf = (unsigned int *) &audio_engines[dev]->dmap_out->dmabuf[ptr]; + + + /* Perform copy with channel swapping */ + if (portc->bytes_per_sample == 4) + { + /* 32 bit mode */ + for (i = 0; i < (8 * 1024) / 4; i += 2) + { + PCI_WRITEL (devc->osdev, devc->pFIFO + i + p, buf[i + 1]); + PCI_WRITEL (devc->osdev, devc->pFIFO + i + 1 + p, buf[i]); + } + } + else + { + /* 16 bit mode */ + for (i = 0; i < (8 * 1024) / 4; i++) + { + unsigned int tmp = buf[i]; + tmp = ((tmp >> 16) & 0xffff) | ((tmp & 0xffff) << 16); + PCI_WRITEL (devc->osdev, devc->pFIFO + i + p, tmp); + } + } + + PCI_READL (devc->osdev, devc->pFIFO); /* Dummy read to flust cache on some archs */ + + portc->outptr = (portc->outptr + (8 * 1024)) % (128 * 1024); /* Increment the pointer */ + +#if 1 + if (!intrflag) + oss_audio_outputintr (dev, 0); +#endif +} + +/*ARGSUSED*/ +static void +digi32_start_input (int dev, oss_native_word ptr, int count, int fragsize, + int intrflag) +{ +} + +static void +digi32_trigger (int dev, int state) +{ + digi32_portc *portc = audio_engines[dev]->portc; + digi32_devc *devc = audio_engines[dev]->devc; + int cmd = devc->cmd; + oss_native_word flags; + + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); + state &= portc->open_mode; + + if (portc->active != state) + { + if (state) + { + if (devc->active_device_count == 0) + { + cmd |= C_START; + cmd &= ~C_RESET; + write_command (devc, cmd | C_SEL); + if ((state & OPEN_WRITE) && (portc->open_mode & OPEN_WRITE)) + portc->trigger_bits |= PCM_ENABLE_OUTPUT; + if ((state & OPEN_READ) && (portc->open_mode & OPEN_READ)) + portc->trigger_bits |= PCM_ENABLE_INPUT; + devc->active_device_count = 1; + } + } + else + { + if (devc->active_device_count != 0) + { + cmd &= ~C_START; + write_command (devc, cmd); + if (!(state & OPEN_WRITE) && (portc->open_mode & OPEN_WRITE)) + portc->trigger_bits &= ~PCM_ENABLE_OUTPUT; + if (!(state & OPEN_READ) && (portc->open_mode & OPEN_READ)) + portc->trigger_bits &= ~PCM_ENABLE_INPUT; + devc->active_device_count = 0; + } + } + } + + portc->active = state; + + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); +} + +/*ARGSUSED*/ +static int +digi32_prepare_for_output (int dev, int bsize, int bcount) +{ +/* NOTE! This routine is used for input too */ + + digi32_devc *devc = audio_engines[dev]->devc; + digi32_portc *portc = audio_engines[dev]->portc; + + int cmd = devc->cmd; + int dblbit = 0, prev_dblbit, speedsel; + + if (devc->active_device_count > 0) + return 0; + + if (bsize != 8 * 1024) + { + cmn_err (CE_CONT, "Illegal fragment size %d\n", bsize); + return OSS_EIO; + } + + prev_dblbit = cmd & C_DS; + cmd &= C_EMP | C_PRO | C_SEL | C_MUTE | C_INP_0 | C_INP_1 | C_AUTOSYNC; + cmd |= C_RESET; + + if (portc->bits & (AFMT_S32_BE | AFMT_S32_LE)) + cmd |= C_MODE24; + + if (portc->speedsel > 2) + dblbit = C_DS; + + speedsel = (portc->speedsel % 3) + 1; + cmd |= (speedsel << 4) | dblbit; + + if (dblbit != prev_dblbit) + { + write_command (devc, cmd | C_PD); + oss_udelay (10); + } + write_command (devc, cmd); + portc->outptr = 0; + portc->trigger_bits &= ~PCM_ENABLE_OUTPUT; + return 0; +} + +/*ARGSUSED*/ +static int +digi32_prepare_for_input (int dev, int bsize, int bcount) +{ + int i, status, fbits; + digi32_devc *devc = audio_engines[dev]->devc; + digi32_portc *portc = audio_engines[dev]->portc; + int cmd = devc->cmd; + int dblbit = 0, prev_dblbit, speedsel; + + if (devc->cmd & C_AUTOSYNC) + { + devc->cmd &= ~C_AUTOSYNC; /* Autosync must be used for input */ + portc->tmp_autosync = 1; + } + + write_command (devc, devc->cmd); + oss_udelay (100); + + for (i = 0; i < 1000; i++) + { + oss_udelay (10); + status = PCI_READL (devc->osdev, devc->pCTRL); + + if (!(status & S_ERF)) + break; + } + + if (i >= 1000) + { + cmn_err (CE_WARN, "No input signal detected\n"); + return OSS_EIO; + } + + devc->speed_locked = 1; + fbits = (status & S_FBITS) >> S_FSHIFT; + portc->speed = fbit_tab[devc->cs841x_part][fbits]; + DDB (cmn_err + (CE_WARN, "digi32: Measured input sampling rate is %d\n", + portc->speed)); + + if (devc->active_device_count > 0) + return 0; + + if (bsize != 8 * 1024) + { + cmn_err (CE_CONT, "Illegal fragment size %d\n", bsize); + return OSS_EIO; + } + + prev_dblbit = cmd & C_DS; + cmd &= C_EMP | C_PRO | C_SEL | C_MUTE | C_INP_0 | C_INP_1 | C_AUTOSYNC; + cmd |= C_RESET; + + if (portc->bits & (AFMT_S32_BE | AFMT_S32_LE)) + cmd |= C_MODE24; + + if (portc->speedsel > 2) + dblbit = C_DS; + + speedsel = (portc->speedsel % 3) + 1; + cmd |= (speedsel << 4) | dblbit; + + if (dblbit != prev_dblbit) + { + write_command (devc, cmd | C_PD); + oss_udelay (10); + } + write_command (devc, cmd); + portc->inptr = 0; + + portc->trigger_bits &= ~PCM_ENABLE_INPUT; + return 0; +} + +/*ARGSUSED*/ +static int +digi32_alloc_buffer (int dev, dmap_t * dmap, int direction) +{ + extern int digi32_buffsize; + + if (digi32_buffsize < 512) /* Given in kilobytes */ + digi32_buffsize *= 1024; + + if (digi32_buffsize < 4096) /* Smaller ones not acceptable */ + digi32_buffsize = 64 * 1024; + + if (dmap->dmabuf != NULL) + return 0; + dmap->dmabuf_phys = 0; /* Not mmap() capable */ + dmap->dmabuf = KERNEL_MALLOC (digi32_buffsize); + if (dmap->dmabuf == NULL) + return OSS_ENOSPC; + dmap->buffsize = digi32_buffsize; + + return 0; +} + +/*ARGSUSED*/ +static int +digi32_free_buffer (int dev, dmap_t * dmap, int direction) +{ + if (dmap->dmabuf == NULL) + return 0; + KERNEL_FREE (dmap->dmabuf); + + dmap->dmabuf = NULL; + return 0; +} + +#if 0 +static int +digi32_get_buffer_pointer (int dev, dmap_t * dmap, int direction) +{ +} +#endif + +/*ARGSUSED*/ +static void +digi32_setup_fragments (int dev, dmap_p dmap, int direction) +{ + /* Make sure the whole sample RAM is covered by the buffer */ + dmap->nfrags = dmap->buffsize / dmap->fragment_size; +} + +static audiodrv_t digi32_output_driver = { + digi32_open, + digi32_close, + digi32_output_block, + digi32_start_input, + digi32_ioctl, + digi32_prepare_for_input, + digi32_prepare_for_output, + digi32_reset, + NULL, + NULL, + digi32_reset_input, + digi32_reset_output, + digi32_trigger, + digi32_set_rate, + digi32_set_format, + digi32_set_channels, + NULL, + NULL, + NULL, + NULL, + digi32_alloc_buffer, + digi32_free_buffer, + NULL, + NULL, + NULL, /* digi32_get_buffer_pointer */ + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + digi32_setup_fragments +}; + +static int +attach_channel (digi32_devc * devc, int chnum, char *name, + audiodrv_t * drv, int type) +{ + int adev, opts; + digi32_portc *portc; + + if (chnum < 0 || chnum >= MAX_AUDIO_CHANNEL) + return 0; + + portc = &devc->portc[chnum]; + opts = + ADEV_DUPLEX | ADEV_STEREOONLY | ADEV_COLD | ADEV_NOMMAP | ADEV_NOVIRTUAL; + + if (chnum != 0) + opts |= ADEV_SHADOW; + + if ((adev = oss_install_audiodev (OSS_AUDIO_DRIVER_VERSION, + devc->osdev, + devc->osdev, + name, drv, sizeof (audiodrv_t), + opts, + AFMT_S16_NE | AFMT_S32_NE | AFMT_AC3, + devc, -1)) < 0) + { + return 0; + } + + audio_engines[adev]->mixer_dev = devc->mixer_dev; + audio_engines[adev]->portc = portc; + audio_engines[adev]->caps |= DSP_CH_STEREO; + audio_engines[adev]->min_block = 8 * 1024; + audio_engines[adev]->max_block = 8 * 1024; + audio_engines[adev]->min_rate = 32000; + audio_engines[adev]->max_rate = (devc->model == MDL_PRO) ? 96000 : 48000; + portc->open_mode = 0; + portc->voice_chn = chnum; + portc->speed = 48000; + portc->bits = AFMT_S16_NE; + portc->bytes_per_sample = 2; + portc->type = type; + return 1; +} + +/*ARGSUSED*/ +static int +digi32_mixer_ioctl (int dev, int audiodev, unsigned int cmd, ioctl_arg arg) +{ + if (cmd == SOUND_MIXER_READ_DEVMASK || + cmd == SOUND_MIXER_READ_RECMASK || cmd == SOUND_MIXER_READ_RECSRC) + return *arg = 0; + + if (cmd == SOUND_MIXER_READ_VOLUME || cmd == SOUND_MIXER_READ_PCM) + return *arg = 100 | (100 << 8); + if (cmd == SOUND_MIXER_WRITE_VOLUME || cmd == SOUND_MIXER_WRITE_PCM) + return *arg = 100 | (100 << 8); + return OSS_EINVAL; +} + +static mixer_driver_t digi32_mixer_driver = { + digi32_mixer_ioctl +}; + +static int +digi32_set_control (int dev, int ctrl, unsigned int cmd, int value) +{ + digi32_devc *devc = mixer_devs[dev]->devc; + int offs, nbits; + unsigned int data; + + if (ctrl < 0) + return OSS_EINVAL; + + offs = (ctrl >> 4) & 0x0f; /* # of bits in the field */ + nbits = ctrl & 0x0f; /* Shift amount */ + + if (cmd == SNDCTL_MIX_READ) + { + data = devc->cmd; + return (data >> offs) & ((1 << nbits) - 1); + } + + if (cmd == SNDCTL_MIX_WRITE) + { + if (value < 0 || value >= (1 << nbits)) + return OSS_EINVAL; + data = devc->cmd & ~(((1 << nbits) - 1) << offs); + data |= (value & ((1 << nbits) - 1)) << offs; + devc->cmd = data; + return value; + } + + return OSS_EINVAL; +} + +static int +digi32_mix_init (int dev) +{ + digi32_devc *devc = mixer_devs[dev]->devc; + int group, err; + + if ((group = mixer_ext_create_group (dev, 0, "DIGI32")) < 0) + return group; + + if (devc->model == MDL_PRO) + if ((err = mixer_ext_create_control (dev, group, + 0xf1, digi32_set_control, + MIXT_ONOFF, + "DIGI32_DEEMPH", 1, + MIXF_READABLE | MIXF_WRITEABLE)) < 0) + return err; + + if ((err = mixer_ext_create_control (dev, group, + 0xd1, digi32_set_control, + MIXT_ENUM, + "DIGI32_SYNC", 2, + MIXF_READABLE | MIXF_WRITEABLE)) < 0) + return err; + + if (devc->model != MDL_8) + if ((err = mixer_ext_create_control (dev, group, + 0xa1, digi32_set_control, + MIXT_ENUM, + "DIGI32_AESMODE", 2, + MIXF_READABLE | MIXF_WRITEABLE)) < 0) + return err; + + if ((err = mixer_ext_create_control (dev, group, + 0x91, digi32_set_control, + MIXT_ONOFF, + "DIGI32_MUTE", 1, + MIXF_READABLE | MIXF_WRITEABLE)) < 0) + return err; + + if ((err = mixer_ext_create_control (dev, group, + 0x62, digi32_set_control, + MIXT_ENUM, + "DIGI32_INPUT", 3, + MIXF_READABLE | MIXF_WRITEABLE)) < 0) + return err; + + + return 0; +} + +int +init_digi32 (digi32_devc * devc) +{ + int my_mixer; + char tmp[128]; + int ret; + + devc->mixer_dev = 0; + + if ((my_mixer = oss_install_mixer (OSS_MIXER_DRIVER_VERSION, + devc->osdev, + devc->osdev, + "RME Digi32 Control panel", + &digi32_mixer_driver, + sizeof (mixer_driver_t), devc)) < 0) + { + + devc->mixer_dev = -1; + return 0; + } + else + { + devc->mixer_dev = my_mixer; + mixer_devs[my_mixer]->priority = -1; /* Don't use as the default mixer */ + mixer_ext_set_init_fn (my_mixer, digi32_mix_init, 20); + } + + ret = + attach_channel (devc, 0, devc->chip_name, &digi32_output_driver, TY_BOTH); + if (ret > 0) + { + sprintf (tmp, "%s (shadow)", devc->chip_name); + ret = attach_channel (devc, 1, tmp, &digi32_output_driver, TY_BOTH); + } + /*setup the command */ + if (devc->model == MDL_PRO) + write_command (devc, C_PD); /* Reset DAC */ + + write_command (devc, C_AUTOSYNC); + return ret; +} + + +int +oss_digi32_attach (oss_device_t * osdev) +{ + digi32_devc *devc; + unsigned char pci_irq_line, pci_revision; + unsigned short pci_command, vendor, device; + unsigned int pci_ioaddr; + int err; + + DDB (cmn_err (CE_WARN, "Entered Digi32 detect routine\n")); + + pci_read_config_word (osdev, PCI_VENDOR_ID, &vendor); + pci_read_config_word (osdev, PCI_DEVICE_ID, &device); + + if ((vendor != RME_VENDOR_ID && vendor != RME_VENDOR_ID2) || + (device != RME_DIGI32_PRO && + device != RME_DIGI32 && device != RME_DIGI32_8)) + + return 0; + + pci_read_config_byte (osdev, PCI_REVISION_ID, &pci_revision); + pci_read_config_word (osdev, PCI_COMMAND, &pci_command); + pci_read_config_irq (osdev, PCI_INTERRUPT_LINE, &pci_irq_line); + pci_read_config_dword (osdev, PCI_MEM_BASE_ADDRESS_0, &pci_ioaddr); + + if (pci_ioaddr == 0) + { + cmn_err (CE_WARN, "BAR0 not initialized by BIOS\n"); + return 0; + } + + + if ((devc = PMALLOC (osdev, sizeof (*devc))) == NULL) + { + cmn_err (CE_WARN, "Out of memory\n"); + return 0; + } + + devc->osdev = osdev; + osdev->devc = devc; + devc->physaddr = pci_ioaddr; + + switch (device) + { + case RME_DIGI32_PRO: + devc->model = MDL_PRO; + if (pci_revision == 150) + { + devc->chip_name = "RME Digi 32 Pro (CS8414)"; + devc->cs841x_part = CS8414; + } + else + { + devc->chip_name = "RME Digi 32 Pro (CS8412)"; + devc->cs841x_part = CS8412; + } + break; + + case RME_DIGI32_8: + devc->chip_name = "RME Digi 32/8"; + devc->model = MDL_8; + devc->cs841x_part = CS8412; + break; + + case RME_DIGI32: + devc->chip_name = "RME Digi32"; + devc->model = MDL_BASIC; + devc->cs841x_part = CS8412; + break; + + case RME_DIGI96_8_PRO: + devc->chip_name = "RME Digi 96/8 Pro"; + devc->model = MDL_96_8_PRO; + devc->cs841x_part = CS8414; + break; + } + + DDB (cmn_err (CE_WARN, "Found Digi32 at 0x%x\n", pci_ioaddr)); + + pci_command |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config_word (osdev, PCI_COMMAND, pci_command); + + MUTEX_INIT (devc->osdev, devc->mutex, MH_DRV); + + oss_register_device (osdev, devc->chip_name); + + if ((err = oss_register_interrupts (devc->osdev, 0, digi32intr, NULL)) < 0) + { + cmn_err (CE_WARN, "Can't register interrupt handler, err=%d\n", err); + return 0; + } + + devc->linaddr = (char *) MAP_PCI_MEM (devc->osdev, 0, devc->physaddr, + 128 * 1024 + 4); + if (devc->linaddr == NULL) + { + cmn_err (CE_WARN, "Can't ioremap PCI registers\n"); + return 0; + } + + devc->pFIFO = (unsigned int *) devc->linaddr; + devc->pCTRL = (unsigned int *) (devc->linaddr + 0x20000); + + return init_digi32 (devc); /* Detected */ +} + +int +oss_digi32_detach (oss_device_t * osdev) +{ + digi32_devc *devc = (digi32_devc *) osdev->devc; + + if (oss_disable_device (osdev) < 0) + return 0; + + oss_unregister_interrupts (devc->osdev); + + MUTEX_CLEANUP (devc->mutex); + + UNMAP_PCI_MEM (devc->osdev, 0, devc->physaddr, devc->linaddr, + 128 * 1024 + 4); + + oss_unregister_device (devc->osdev); + + return 1; +} diff --git a/attic/drv/oss_digi32/oss_digi32.man b/attic/drv/oss_digi32/oss_digi32.man new file mode 100644 index 0000000..a975512 --- /dev/null +++ b/attic/drv/oss_digi32/oss_digi32.man @@ -0,0 +1,82 @@ +NAME +oss_digi32 - RME Digi32 professional audio driver. + +DESCRIPTION +RME Digi32 is a family of digital audio cards. The base model Digi32 has +digital input and output (both optical and RCA connectors). It supports +16/20/24 bit full duplex recording and playback with standard S/PDIF +devices. Digi32 Pro has added 20 bit analog output and it supports up to +96 kHz sampling rates. It also has XLR connectors for AES/EBU unput and output. +Digi32/8 is Digi32 with added support for ADAT compatible 8 channel optical +digital link. + +The Digi32 family is also sold as the PRODIF family by SEK'D. However some +SEK'D PRODIF models are not made by RME and they will _not_ work with OSS. +In particular "Prodif32 Plus" is _NOT_ supported by OSS. + +More information about these cards can be found from +http://www.rme-audio.com/english/ and http://www.sekd.com. + + RECORDING AND PLAYBACK + +Basic recording and playback functions will work like with any other +soundcard. However there are few things to note due to digital nature of +the cards: + +o Only 16 and 24/32 bit audio formats are supported. +o Only few sampling rates are possible. All Digi32 family members support + 32kHz, 44.1kHz and 48kHz sampling rates. In addition Digi32 Pro supports + 64kHz, 88.2kHz and 96kHz. +o When the device is opened for input or input/output access the sampling rate + will be locked to the input signal in the selected port. Opening the device + will fail if there is no valid signal connected to the input port. + + MEMORY USAGE + +By default the Digi32 driver will allocate 64k of buffer both for recording and +playback functions. This should be sufficient in most cases. If necessary +the buffer sizes can be increased by defining digi32_buffsize in the +oss_digi32.cfg file (in the directory you installed OSS). For example +digi32_buffsize=128 setw the buffer size to 128k. + + MIXER PANEL + +There are few settings that can be changed using the ossmix program +shipped with OSS. Note that these settings should not be changed +while recording and/or playback is active (otherwise results may be +inpredictable). The changes will take effect when playback/recording +is started next time. + +The following settings are available: + +o digi32.deemph ON|OFF (currently OFF) +Enables digital de-emphasis. Only available with Digi32 Pro. + +o digi32.sync <EXTERNAL|INTERNAL> (currently EXTERNAL) + This setting can be used to select between internal and external sync + source during playback. External sync will always be used when the device + is opened for recording. + +o digi32.aesmode <CONSUMER|PRO> (currently CONSUMER) + This setting can be used to switch between the consumer and the pro modes + on the S/PDIF port. Not available with Digi32/8. + +o digi32.mute ON|OFF (currently OFF) + This setting can be used to mute the card. + +o digi32.input <OPTICAL|RCA|INTERNAL|XLR> (XLR only on Digi 32/PRO) + This setting is used to select the active input. Note that XLR is supported + only by Digi32 Pro. + +OPTIONS +o digi32_buffer_size=<64..128> +By default the Digi32 driver will allocate 64k of buffer both for recording +and playback functions. This should be sufficient in most cases. If necessary +the buffer sizes can be increased. + +FILES +CONFIGFILEPATH/oss_digi32.conf Device configuration file + +AUTHOR +4Front Technologies + diff --git a/attic/drv/oss_maestro/.config b/attic/drv/oss_maestro/.config new file mode 100644 index 0000000..5280084 --- /dev/null +++ b/attic/drv/oss_maestro/.config @@ -0,0 +1 @@ +platform=i86pc diff --git a/attic/drv/oss_maestro/.devices b/attic/drv/oss_maestro/.devices new file mode 100644 index 0000000..f59fec3 --- /dev/null +++ b/attic/drv/oss_maestro/.devices @@ -0,0 +1,3 @@ +oss_maestro pci125d,1968 ESS Maestro-2 +oss_maestro pci125d,1978 ESS Maestro-2E +oss_maestro pci1285,100 ESS Maestro-1 diff --git a/attic/drv/oss_maestro/.name b/attic/drv/oss_maestro/.name new file mode 100644 index 0000000..2509347 --- /dev/null +++ b/attic/drv/oss_maestro/.name @@ -0,0 +1 @@ +ESS Maestro-2 diff --git a/attic/drv/oss_maestro/oss_maestro.c b/attic/drv/oss_maestro/oss_maestro.c new file mode 100644 index 0000000..d8ea3ff --- /dev/null +++ b/attic/drv/oss_maestro/oss_maestro.c @@ -0,0 +1,2397 @@ +/* + * Purpose: Driver for ESS Maestro1/2 (PCI) audio controller + */ +/* + * + * This file is part of Open Sound System. + * + * Copyright (C) 4Front Technologies 1996-2008. + * + * This this source file is released under GPL v2 license (no other versions). + * See the COPYING file included in the main directory of this source + * distribution for the license terms and conditions. + * + */ + +#include "oss_maestro_cfg.h" +#include "oss_pci.h" +#include "uart401.h" +#include "ac97.h" + +#ifndef PAGE_SIZE +#define PAGE_SIZE 4096 +#endif + +#define BYTE unsigned char +#define WORD unsigned short +#define DWORD unsigned int +#define HIWORD(dw) ((dw >> 16) & 0xffff) +#define LOWORD(dw) (dw & 0xffff) +#define HIBYTE(w) ((w >> 8) & 0xff) +#define LOBYTE(w) (w & 0xff) + +#define gwPTBaseIO devc->base +#define outpw(p,d) OUTW(devc->osdev, d, p) + +#define DISABLE 0 +#define ENABLE 1 + +#define CHANNEL0 0x0 +#define bAPURPlay 0x0 +#define bAPULPlay 0x1 + +#define bAPULSrc 0x2 +#define bAPURSrc 0x3 +#define bAPULMix 0x4 +#define bAPURMix 0x5 + + +#define ESS_VENDOR_ID 0x1285 +#define ESS_MAESTRO 0x0100 +#define ESS2_VENDOR_ID 0x125d +#define ESS_MAESTRO2 0x1968 +#define ESS_MAESTRO2E 0x1978 + +#define WSETBIT(w, b) (w | (1 << b)) +#define WMSKBIT(w, b) (w & ~(1 << b)) +#define DWSETBIT(w, b) (w | (1 << b)) +#define DWMSKBIT(w, b) (w & ~(1 << b)) + +static int SYSCLK; +#define ESSM_CFMT_STEREO 0x01 +#define ESSM_CFMT_16BIT 0x02 +#define ESSM_CFMT_MASK 0x03 +#define ESSM_CFMT_ASHIFT 0 +#define ESSM_CFMT_CSHIFT 4 + +#define MAXCOUNTDOWN 31 +DWORD dwFrequencyTable[] = { + 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536 +}; + +#define IO_PT_CODEC_CMD ( devc->base + 0x30 ) +#define IO_PT_CODEC_STATUS ( devc->base + 0x30 ) +#define IO_PT_CODEC_DATA ( devc->base + 0x32 ) +#define IO_PT_CODEC_FORMATA ( devc->base + 0x34 ) +#define IO_PT_CODEC_FORMATB ( devc->base + 0x36 ) + +#define _DST_MONO 0x00 +#define _DST_STEREO 0x08 + +#define _DST_NONE 0x00 +#define _DST_DAC 0x01 +#define _DST_MODEM 0x02 +#define _DST_RESERVED1 0x03 +#define _DST_DIRECTSOUND 0x04 +#define _DST_ASSP 0x05 +#define _DST_RESERVED2 0x06 +#define _DST_RESERVED3 0x07 + +#define PT101_MIXER_DEVS (SOUND_MASK_LINE1 | SOUND_MASK_LINE2 | \ + SOUND_MASK_MIC | SOUND_MASK_VOLUME | \ + SOUND_MASK_LINE3 | \ + SOUND_MASK_SYNTH | SOUND_MASK_CD | \ + SOUND_MASK_LINE | SOUND_MASK_PCM | \ + SOUND_MASK_IGAIN) + +#define PT101_MIXER_RECDEVS (SOUND_MASK_LINE | SOUND_MASK_MIC | \ + SOUND_MASK_CD | SOUND_MASK_LINE1 | \ + SOUND_MASK_LINE2 | SOUND_MASK_LINE3) + +#define PT101_MIXER_STEREODEVS (SOUND_MASK_LINE | SOUND_MASK_IGAIN | \ + SOUND_MASK_VOLUME | SOUND_MASK_SYNTH | \ + SOUND_MASK_CD | \ + SOUND_MASK_PCM | SOUND_MASK_LINE1 | \ + SOUND_MASK_LINE2 | SOUND_MASK_LINE3) + +static int default_mixer_levels[32] = { + 0x3232, /* Master Volume */ + 0x3232, /* Bass */ + 0x3232, /* Treble */ + 0x4b4b, /* FM */ + 0x3232, /* PCM */ + 0x1515, /* PC Speaker */ + 0x2020, /* Ext Line */ + 0x1010, /* Mic */ + 0x4b4b, /* CD */ + 0x0000, /* Recording monitor */ + 0x4b4b, /* Second PCM */ + 0x4b4b, /* Recording level */ + 0x4b4b, /* Input gain */ + 0x4b4b, /* Output gain */ + 0x2020, /* Line1 */ + 0x2020, /* Line2 */ + 0x1515 /* Line3 (usually line in) */ +}; + +typedef struct maestro_portc +{ + int speed, bits, channels; + int open_mode; + int audiodev; + int trigger_bits; + int audio_enabled; +} +maestro_portc; + +#define MAX_PORTC 2 + +typedef struct maestro_devc +{ + oss_device_t *osdev; + oss_native_word base; + int irq; + int model; + char *chip_name; + int open_mode; + /* Data table for virtualizing write-only registers */ + WORD wIDRRegDataTable[0x1F]; + WORD gwWCRegTable[0x200]; +#define MD_MAESTRO1 1 +#define MD_MAESTRO2 2 +#define MD_MAESTRO2E 3 + unsigned short gpio; + oss_mutex_t lock; + oss_mutex_t low_lock; + + struct dmabuf + { + unsigned char *rawbuf; + unsigned dmasize; + oss_native_word base; /* Offset for ptr */ + } + dma_adc, dma_dac, dma_mix; + int wApuBufferSize; + unsigned char *dmapages; + oss_native_word dmapages_phys; + int dmalen; + + /* Mixer parameters */ + ac97_devc ac97devc; + /* PT101 Mixer parameters */ + int my_mixer; + int *levels; + int recdevs; + int recmask; + + maestro_portc portc[MAX_PORTC]; +} +maestro_devc; + +extern WORD wRdAPUReg (maestro_devc * devc, BYTE _bChannel, BYTE _bRegIndex); + +static int +maestrointr (oss_device_t * osdev) +{ + maestro_devc *devc = (maestro_devc *) osdev->devc; + maestro_portc *portc; + int i; + int serviced = 0; + + if (!(INW (devc->osdev, devc->base + 0x1A))) + return 0; + + OUTW (devc->osdev, INW (devc->osdev, devc->base + 0x04) | 0x1, + devc->base + 0x04); + serviced = 1; + + /* ack all interrupts */ + OUTB (devc->osdev, 0xFF, devc->base + 0x1A); + for (i = 0; i < MAX_PORTC; i++) + { + portc = &devc->portc[i]; + + /* Handle Playback */ + if (portc->trigger_bits & PCM_ENABLE_OUTPUT) + { + dmap_t *dmapout = audio_engines[portc->audiodev]->dmap_out; + WORD wApuCurrentPos; + int n; + + wApuCurrentPos = wRdAPUReg (devc, bAPURPlay, 0x05); + wApuCurrentPos = (wApuCurrentPos - devc->dma_dac.base) & 0xFFFE; + wApuCurrentPos = (wApuCurrentPos % devc->wApuBufferSize) << 1; + wApuCurrentPos /= dmapout->fragment_size; /*Actual qhead */ + if (wApuCurrentPos == 0 || wApuCurrentPos > dmapout->nfrags) + wApuCurrentPos = 0; + n = 0; + while (dmap_get_qhead (dmapout) != wApuCurrentPos + && n++ < dmapout->nfrags) + oss_audio_outputintr (portc->audiodev, 0); + } + + /* Handle recording */ + if (portc->trigger_bits & PCM_ENABLE_INPUT) + { + dmap_t *dmapin = audio_engines[portc->audiodev]->dmap_in; + WORD wApuCurrentPos; + int n; + + wApuCurrentPos = wRdAPUReg (devc, bAPULSrc, 0x05); + wApuCurrentPos = (wApuCurrentPos - devc->dma_adc.base) & 0xFFFE; + wApuCurrentPos = (wApuCurrentPos % devc->wApuBufferSize) << 1; + wApuCurrentPos /= dmapin->fragment_size; /* Actual qtail */ + if (wApuCurrentPos == 0 || wApuCurrentPos > dmapin->nfrags) + wApuCurrentPos = 0; + n = 0; + while (dmap_get_qtail (dmapin) != wApuCurrentPos + && n++ < dmapin->nfrags) + oss_audio_inputintr (portc->audiodev, 0); + } + } + return serviced; +} + +static int +ac97_read (void *devc_, int addr) +{ + maestro_devc *devc = devc_; + int data, i; + oss_native_word flags; + int sanity = 10000; + + MUTEX_ENTER_IRQDISABLE (devc->low_lock, flags); + + for (i = 0; i < 100000; i++) + if (!(INB (devc->osdev, devc->base + 0x30) & 0x01)) + break; + OUTW (devc->osdev, addr | 0x80, devc->base + 0x30); + + while (INB (devc->osdev, devc->base + 0x30) & 1) + { + sanity--; + if (!sanity) + { + cmn_err (CE_WARN, "ac97 codec timeout - 0x%x.\n", addr); + MUTEX_EXIT_IRQRESTORE (devc->low_lock, flags); + return 0; + } + } + + data = INW (devc->osdev, devc->base + 0x32); + oss_udelay (100); + + MUTEX_EXIT_IRQRESTORE (devc->low_lock, flags); + return data & 0xffff; +} + +static int +ac97_write (void *devc_, int addr, int data) +{ + maestro_devc *devc = devc_; + int i; + oss_native_word flags; + + MUTEX_ENTER_IRQDISABLE (devc->low_lock, flags); + + for (i = 0; i < 10000; i++) + if (!(INB (devc->osdev, devc->base + 0x30) & 0x01)) + break; + OUTW (devc->osdev, data & 0xffff, devc->base + 0x32); + oss_udelay (100); + OUTW (devc->osdev, (addr & 0x7f) & ~0x80, devc->base + 0x30); + oss_udelay (100); + + MUTEX_EXIT_IRQRESTORE (devc->low_lock, flags); + + return 0; +} + +/**************************************************** + * PT101 CODEC Routines * + ****************************************************/ + +/************************************************************************/ +/* PT101 CODEC Read */ +/************************************************************************/ + +static int +pt101_set_recmask (maestro_devc * devc, int mask) +{ + int bits = 0; + mask &= devc->recmask; + + mask = mask & (devc->recdevs ^ mask); /* Pick the one recently turned on */ + + if (!mask) + return devc->recdevs; + + devc->recdevs = mask; + + switch (mask) + { + case SOUND_MASK_LINE: + bits = 0x0000; + break; + case SOUND_MASK_MIC: + bits = 0x0020; + break; + case SOUND_MASK_CD: + case SOUND_MASK_LINE1: + bits = 0x0040; + break; + /*CD*/ case SOUND_MASK_LINE2: + bits = 0x0060; + break; /*Video */ + case SOUND_MASK_LINE3: + bits = 0x0080; + break; /*Modem */ + default: /* Unknown bit (combination) */ + mask = SOUND_MASK_MIC; + bits = 0x0020; + } + + ac97_write (devc, 0x02, bits); + + return devc->levels[31] = devc->recdevs; +} + +static int +pt101_mixer_get (maestro_devc * devc, int dev) +{ + if (!((1 << dev) & PT101_MIXER_DEVS)) + return OSS_EINVAL; + + return devc->levels[dev]; +} + +static int +pt101_mixer_set (maestro_devc * devc, int dev, int value) +{ + + int left, right, lvl; + int lch, rch; + static const char pt101_mix_map[101] = { + 15, 15, 15, 15, 15, 15, 14, 14, 14, 14, 14, 14, 13, 13, 13, 13, 13, 13, + 12, 12, + 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 10, 10, 10, 10, 10, 10, 9, 9, 9, + 9, + 9, 9, 8, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, + 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 2, 2, + 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + }; + + + if (!((1 << dev) & PT101_MIXER_DEVS)) + return OSS_EINVAL; + + if (!((1 << dev) & PT101_MIXER_STEREODEVS)) + { + lvl = value & 0xff; + if (lvl > 100) + lvl = 100; + lch = rch = lvl; + value = lvl | (lvl << 8); + } + else + { + lch = value & 0xff; + rch = (value >> 8) & 0xff; + if (lch > 100) + lch = 100; + if (rch > 100) + rch = 100; + value = lch | (rch << 8); + } + +/* Now adjust the left and right channel to the mixer map*/ + left = pt101_mix_map[lch]; + right = pt101_mix_map[rch]; + + switch (dev) + { + case SOUND_MIXER_CD: + case SOUND_MIXER_LINE1: + if (rch == 0) + ac97_write (devc, 0x04, (ac97_read (devc, 0x04) & 0xFF7F) | 0x0080); + else + ac97_write (devc, 0x04, (ac97_read (devc, 0x04) & 0xFF7F)); + + if (lch == 0) + ac97_write (devc, 0x04, (ac97_read (devc, 0x04) & 0x7FFF) | 0x8000); + else + ac97_write (devc, 0x04, (ac97_read (devc, 0x04) & 0x7FFF)); + + ac97_write (devc, 0x04, ((ac97_read (devc, 0x04) & 0xFFE1) | (right << 1))); /*Right */ + ac97_write (devc, 0x04, ((ac97_read (devc, 0x04) & 0xE1FF) | (left << 9))); /*Left */ + break; + + case SOUND_MIXER_LINE2: + if (rch == 0) + ac97_write (devc, 0x05, (ac97_read (devc, 0x05) & 0xFF7F) | 0x0080); + else + ac97_write (devc, 0x05, (ac97_read (devc, 0x05) & 0xFF7F)); + + if (lch == 0) + ac97_write (devc, 0x05, (ac97_read (devc, 0x05) & 0x7FFF) | 0x8000); + else + ac97_write (devc, 0x05, (ac97_read (devc, 0x05) & 0x7FFF)); + + ac97_write (devc, 0x05, (WORD) ((ac97_read (devc, 0x05) & 0xFFE1) | ((WORD) right << 1))); /*Right */ + ac97_write (devc, 0x05, (WORD) ((ac97_read (devc, 0x05) & 0xE1FF) | ((WORD) left << 9))); /*Left */ + break; + + case SOUND_MIXER_LINE3: + if (rch == 0) + ac97_write (devc, 0x06, (ac97_read (devc, 0x06) & 0xFF7F) | 0x0080); + else + ac97_write (devc, 0x06, (ac97_read (devc, 0x06) & 0xFF7F)); + + if (lch == 0) + ac97_write (devc, 0x06, (ac97_read (devc, 0x06) & 0x7FFF) | 0x8000); + else + ac97_write (devc, 0x06, (ac97_read (devc, 0x06) & 0x7FFF)); + + ac97_write (devc, 0x06, (WORD) ((ac97_read (devc, 0x06) & 0xFFE1) | ((WORD) right << 1))); /*Right */ + ac97_write (devc, 0x06, (WORD) ((ac97_read (devc, 0x06) & 0xE1FF) | ((WORD) left << 9))); /*Left */ + break; + + case SOUND_MIXER_LINE: + if (rch == 0) + ac97_write (devc, 0x1D, (ac97_read (devc, 0x1D) & 0xFF7F) | 0x0080); + else + ac97_write (devc, 0x1D, (ac97_read (devc, 0x1D) & 0xFF7F)); + + if (lch == 0) + ac97_write (devc, 0x1D, (ac97_read (devc, 0x1D) & 0x7FFF) | 0x8000); + else + ac97_write (devc, 0x1D, (ac97_read (devc, 0x1D) & 0x7FFF)); + + ac97_write (devc, 0x1D, (WORD) ((ac97_read (devc, 0x1D) & 0xFFE1) | ((WORD) right << 1))); /*Right */ + ac97_write (devc, 0x1D, (WORD) ((ac97_read (devc, 0x1D) & 0xE1FF) | ((WORD) left << 9))); /*Left */ + break; + + case SOUND_MIXER_MIC: + if (rch == 0) + ac97_write (devc, 0x07, (ac97_read (devc, 0x07) & 0xFF7F) | 0x0080); + else + ac97_write (devc, 0x07, (ac97_read (devc, 0x07) & 0xFF7F)); + + if (lch == 0) + ac97_write (devc, 0x07, (ac97_read (devc, 0x07) & 0x7FFF) | 0x8000); + else + ac97_write (devc, 0x07, (ac97_read (devc, 0x07) & 0x7FFF)); + + left = right; + ac97_write (devc, 0x07, + (WORD) ((ac97_read (devc, 0x07) & 0xFFE1) | + ((WORD) right << 1))); + ac97_write (devc, 0x07, + (WORD) ((ac97_read (devc, 0x07) & 0xE1FF) | + ((WORD) right << 9))); + break; + + case SOUND_MIXER_SYNTH: + case SOUND_MIXER_VOLUME: + case SOUND_MIXER_PCM: + if (rch == 0) + ac97_write (devc, 0x09, (ac97_read (devc, 0x09) & 0xFF7F) | 0x0080); + else + ac97_write (devc, 0x09, (ac97_read (devc, 0x09) & 0xFF7F)); + + if (lch == 0) + ac97_write (devc, 0x09, (ac97_read (devc, 0x09) & 0x7FFF) | 0x8000); + else + ac97_write (devc, 0x09, (ac97_read (devc, 0x09) & 0x7FFF)); + + ac97_write (devc, 0x09, (WORD) ((ac97_read (devc, 0x09) & 0xFFE1) | ((WORD) right << 1))); /*Right */ + ac97_write (devc, 0x09, (WORD) ((ac97_read (devc, 0x09) & 0xE1FF) | ((WORD) left << 9))); /*Left */ + break; + + case SOUND_MIXER_IGAIN: + ac97_write (devc, 0x02, (WORD) ((ac97_read (devc, 0x02) & 0xFFF0) | ((WORD) right))); /*Right */ + ac97_write (devc, 0x02, (WORD) ((ac97_read (devc, 0x02) & 0xF0FF) | ((WORD) left << 8))); /*Left */ + break; + } + + return devc->levels[dev] = value; +} + +static void +pt101_mixer_reset (maestro_devc * devc) +{ + int i; + + devc->levels = load_mixer_volumes ("ESS PT101", default_mixer_levels, 1); + devc->recmask = PT101_MIXER_RECDEVS & PT101_MIXER_DEVS; + for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) + pt101_mixer_set (devc, i, devc->levels[i]); + pt101_set_recmask (devc, SOUND_MASK_MIC); +} + +/*ARGSUSED*/ +static int +pt101_mixer_ioctl (int dev, int audiodev, unsigned int cmd, ioctl_arg arg) +{ + maestro_devc *devc = mixer_devs[dev]->devc; + int val; + + if (((cmd >> 8) & 0xff) == 'M') + { + if (IOC_IS_OUTPUT (cmd)) + switch (cmd & 0xff) + { + case SOUND_MIXER_RECSRC: + val = *arg; + return *arg = pt101_set_recmask (devc, val); + break; + + default: + val = *arg; + return *arg = pt101_mixer_set (devc, cmd & 0xff, val); + } + else + switch (cmd & 0xff) + { + + case SOUND_MIXER_RECSRC: + return *arg = devc->recdevs; + break; + + case SOUND_MIXER_DEVMASK: + return *arg = PT101_MIXER_DEVS; + break; + + case SOUND_MIXER_STEREODEVS: + return *arg = PT101_MIXER_STEREODEVS; + break; + + case SOUND_MIXER_RECMASK: + return *arg = devc->recmask; + break; + + case SOUND_MIXER_CAPS: + return *arg = SOUND_CAP_EXCL_INPUT; + break; + + default: + return *arg = pt101_mixer_get (devc, cmd & 0xff); + } + } + else + return OSS_EINVAL; +} + +/* + * Low level I/O routines + */ +#define WAVE_CACHE_INDEX (devc->base + 0x10) +#define WAVE_CACHE_DATA (devc->base + 0x12) +#define WAVE_CACHE_CONTROL (devc->base + 0x14) + +/*****************************************************************************/ +/* Write Wave Cache Address I/O Port */ +/* */ +/*****************************************************************************/ +static void +vWrWCRegIndex (maestro_devc * devc, WORD _wRegIndex) +{ + OUTW (devc->osdev, LOWORD (_wRegIndex), WAVE_CACHE_INDEX); +} + +/*****************************************************************************/ +/* Write Wave Cache Data I/O Port */ +/* */ +/*****************************************************************************/ +static void +vWrWCRegData (maestro_devc * devc, WORD _wRegData) +{ + OUTW (devc->osdev, _wRegData, WAVE_CACHE_DATA); +} + +/*****************************************************************************/ +/* Read Wave Cache Addr I/O Port */ +/* */ +/*****************************************************************************/ +WORD +wRdWCRegIndex (maestro_devc * devc) +{ + return ((WORD) INW (devc->osdev, WAVE_CACHE_INDEX)); +} + +/*****************************************************************************/ +/* Read Wave Cache Data I/O Port */ +/* */ +/*****************************************************************************/ +WORD +wRdWCRegData (maestro_devc * devc) +{ + return ((WORD) (INW (devc->osdev, WAVE_CACHE_DATA))); +} + +/*****************************************************************************/ +/* Write Wave Cache Memory */ +/* */ +/*****************************************************************************/ +void +vWrWCReg (maestro_devc * devc, WORD _wRegIndex, WORD _wRegData) +{ + vWrWCRegIndex (devc, _wRegIndex); + vWrWCRegData (devc, _wRegData); +} + +/*****************************************************************************/ +/* Read Wave Cache Memory */ +/* */ +/*****************************************************************************/ +WORD +wRdWCReg (maestro_devc * devc, WORD _wRegIndex) +{ + WORD wRetVal; + + vWrWCRegIndex (devc, _wRegIndex); + wRetVal = wRdWCRegData (devc); + + return (wRetVal); +} + +/*****************************************************************************/ +/* */ +/* */ +/*****************************************************************************/ +void +vSetWCChannelControlBit (maestro_devc * devc, BYTE _bChannel, BYTE _bBit) +{ + vWrWCReg (devc, (WORD) (_bChannel << 3), + WSETBIT (wRdWCReg (devc, (WORD) (_bChannel << 3)), _bBit)); +} + +/*****************************************************************************/ +/* */ +/* */ +/*****************************************************************************/ +void +vMskWCChannelControlBit (maestro_devc * devc, BYTE _bChannel, BYTE _bBit) +{ + + vWrWCReg (devc, (WORD) (_bChannel << 3), + WMSKBIT (wRdWCReg (devc, (WORD) (_bChannel << 3)), _bBit)); +} + + +/*****************************************************************************/ +/* */ +/* */ +/*****************************************************************************/ +void +vSetWCChannelStereo (maestro_devc * devc, BYTE _bChannel, BYTE _bState) +{ + switch (_bState) + { + case 0: + /*MONO*/ vMskWCChannelControlBit (devc, _bChannel, 1); + break; + + case 1: + /*STEREO*/ vSetWCChannelControlBit (devc, _bChannel, 1); + break; + } +} + +/*****************************************************************************/ +/* */ +/* */ +/*****************************************************************************/ +void +vSetWCChannelWordSize (maestro_devc * devc, BYTE _bChannel, BYTE _bState) +{ + switch (_bState) + { + case 0: /* 8BIT */ + vSetWCChannelControlBit (devc, _bChannel, 2); + break; + + case 1: /* 16BIT */ + vMskWCChannelControlBit (devc, _bChannel, 2); + break; + } +} + +/*****************************************************************************/ +/* */ +/* */ +/*****************************************************************************/ +void +vSetWCChannelTagAddr (maestro_devc * devc, BYTE _bChannel, WORD _wTagAddr) +{ + vWrWCReg (devc, (WORD) (_bChannel << 3), + (WORD) ((wRdWCReg (devc, (WORD) (_bChannel << 3)) & 0x0007) | + (WORD) (_wTagAddr << 3))); +} + +#define WAVERAM_START 0x400000 + +#define IDR0_DATA_PORT 0x00 +#define IDR1_CRAM_POINTER 0x01 +#define IDR2_CRAM_INCREMENT 0x02 +#define IDR3_WAVE_DATA 0x03 +#define IDR4_WAVE_PTR_LO 0x04 +#define IDR5_WAVE_PTR_HI 0x05 +#define IDR6_TIMER_CTRL 0x06 +#define IDR7_WAVE_ROMRAM 0x07 + +/* Read/Write access for Indexed Data Registers */ +#define _RW 0 /* Read/Write */ +#define _WO 1 /* Write Only */ +#define _RO 2 /* Read Only */ + +static BYTE bIDRAccessTable[] = { + _RW, _RW, _RW, _RW, + _RW, _RW, _WO, _WO, + _WO, _WO, _WO, _WO, + _WO, _WO, _WO, _WO, + _WO, _WO, _RW, _WO, + _RO, _RW, _RW, _WO +}; + +#define PT_DATA_PORT devc->base +#define PT_INDEX_PORT (devc->base + 0x02) + +/*****************************************************************************/ +/* Write IDR Register Index */ +/* */ +/*****************************************************************************/ +static void +vWrIDRIndex (maestro_devc * devc, WORD _wRegIndex) +{ + OUTW (devc->osdev, _wRegIndex, PT_INDEX_PORT); +} + +/*****************************************************************************/ +/* Write IDR Register Data */ +/* */ +/*****************************************************************************/ +static void +vWrIDRData (maestro_devc * devc, WORD _wRegData) +{ + OUTW (devc->osdev, _wRegData, PT_DATA_PORT); +} + +/*****************************************************************************/ +/* Read IDR Register Data */ +/* */ +/*****************************************************************************/ +static WORD +wRdIDRData (maestro_devc * devc) +{ + return ((WORD) INW (devc->osdev, PT_DATA_PORT)); +} + +/*****************************************************************************/ +/* Write IDR Register */ +/* */ +/*****************************************************************************/ +static void +vWrIDR (maestro_devc * devc, WORD _wRegIndex, WORD _wRegData) +{ + vWrIDRIndex (devc, _wRegIndex); + + vWrIDRData (devc, _wRegData); + + devc->wIDRRegDataTable[_wRegIndex] = _wRegData; +} + +/*****************************************************************************/ +/* Read IDR Register */ +/* */ +/*****************************************************************************/ +static WORD +wRdIDR (maestro_devc * devc, WORD _wRegIndex) +{ + WORD wRetVal = 0; + + vWrIDRIndex (devc, _wRegIndex); + + switch (bIDRAccessTable[_wRegIndex]) + { + case _RW: + case _RO: + wRetVal = wRdIDRData (devc); + break; + + case _WO: + wRetVal = devc->wIDRRegDataTable[_wRegIndex]; + break; + } + + return (wRetVal); +} + +/*****************************************************************************/ +/* Set IDR Register Bit */ +/* */ +/*****************************************************************************/ +static void +vSetIDRBit (maestro_devc * devc, WORD _wRegIndex, BYTE _bRegBit) +{ + vWrIDR (devc, _wRegIndex, WSETBIT (wRdIDR (devc, _wRegIndex), _bRegBit)); +} + +/*****************************************************************************/ +/* Mask IDR Register Bit */ +/* */ +/*****************************************************************************/ +static void +vMskIDRBit (maestro_devc * devc, WORD _wRegIndex, BYTE _bRegBit) +{ + vWrIDR (devc, _wRegIndex, WMSKBIT (wRdIDR (devc, _wRegIndex), _bRegBit)); +} + +/**************************/ +#define _APU_MIXER 0x06 +#define _APU_SYNR 0x3C +#define _APU_SYNL 0x3D +#define _APU_DIGL 0x3E +#define _APU_DIGR 0x3F + +/* APU Modes */ +#define _APU_OFF 0x00 +#define _APU_16BITLINEAR 0x01 /* 16-Bit Linear Sample Player */ +#define _APU_16BITSTEREO 0x02 /* 16-Bit Stereo Sample Player */ +#define _APU_8BITLINEAR 0x03 /* 8-Bit Linear Sample Player */ +#define _APU_8BITSTEREO 0x04 /* 8-Bit Stereo Sample Player */ +#define _APU_8BITDIFF 0x05 /* 8-Bit Differential Sample Playrer */ +#define _APU_DIGITALDELAY 0x06 /* Digital Delay Line */ +#define _APU_DUALTAP 0x07 /* Dual Tap Reader */ +#define _APU_CORRELATOR 0x08 /* Correlator */ +#define _APU_INPUTMIXER 0x09 /* Input Mixer */ +#define _APU_WAVETABLE 0x0A /* Wave Table Mode */ +#define _APU_SRCONVERTOR 0x0B /* Sample Rate Convertor */ +#define _APU_16BITPINGPONG 0x0C /* 16-Bit Ping-Pong Sample Player */ + +#define _APU_RESERVED1 0x0D /* Reserved 1 */ +#define _APU_RESERVED2 0x0E /* Reserved 2 */ +#define _APU_RESERVED3 0x0F /* Reserved 3 */ + +/* APU Filtey Q Control */ +#define _APU_FILTER_LESSQ 0x00 +#define _APU_FILTER_MOREQ 0x03 + +/* APU Filter Control */ +#define _APU_FILTER_2POLE_LOPASS 0x00 +#define _APU_FILTER_2POLE_BANDPASS 0x01 +#define _APU_FILTER_2POLE_HIPASS 0x02 +#define _APU_FILTER_1POLE_LOPASS 0x03 +#define _APU_FILTER_1POLE_HIPASS 0x04 +#define _APU_FILTER_OFF 0x05 + +/* Polar Pan Control */ +#define _APU_PAN_CENTER_CIRCLE 0x00 +#define _APU_PAN_MIDDLE_RADIUS 0x01 +#define _APU_PAN_OUTSIDE_RADIUS 0x02 +#define _APU_PAN_ + +/* APU ATFP Type */ +#define _APU_ATFP_AMPLITUDE 0x00 +#define _APU_ATFP_TREMELO 0x01 +#define _APU_ATFP_FILTER 0x02 +#define _APU_ATFP_PAN 0x03 + +/* APU ATFP Flags */ +#define _APU_ATFP_FLG_OFF 0x00 +#define _APU_ATFP_FLG_WAIT 0x01 +#define _APU_ATFP_FLG_DONE 0x02 +#define _APU_ATFP_FLG_INPROCESS 0x03 + +static WORD +wRdAPURegIndex (maestro_devc * devc) +{ + return (wRdIDR (devc, IDR1_CRAM_POINTER)); +} + +static void +vWrAPURegIndex (maestro_devc * devc, WORD _wRegIndex) +{ + vWrIDR (devc, IDR1_CRAM_POINTER, _wRegIndex); + + while (wRdAPURegIndex (devc) != _wRegIndex) + { + } +} + +static WORD +wRdAPURegData (maestro_devc * devc) +{ + return (wRdIDR (devc, IDR0_DATA_PORT)); +} + +static void +vWrAPURegData (maestro_devc * devc, WORD _wRegData) +{ + while (wRdAPURegData (devc) != _wRegData) + { + vWrIDR (devc, IDR0_DATA_PORT, _wRegData); + } +} + +static void +vWrAPUReg (maestro_devc * devc, BYTE _bChannel, BYTE _bRegIndex, + WORD _wRegData) +{ + vWrAPURegIndex (devc, (WORD) ((_bChannel << 4) + _bRegIndex)); + vWrAPURegData (devc, _wRegData); +} + +/* Should be static */ WORD +wRdAPUReg (maestro_devc * devc, BYTE _bChannel, BYTE _bRegIndex) +{ + vWrAPURegIndex (devc, (WORD) ((_bChannel << 4) + _bRegIndex)); + return (wRdAPURegData (devc)); +} + +/*****************************************************************************/ +/* */ +/* */ +/*****************************************************************************/ +DWORD +wCalculateAPUFrequency (DWORD freq) +{ + if (freq == 48000) + return 0x10000; + + return ((freq / (SYSCLK / 1024L)) << 16) + + (((freq % (SYSCLK / 1024L)) << 16) / (SYSCLK / 1024L)); +} + + +static void +vSetAPUFrequency (maestro_devc * devc, BYTE _bChannel, DWORD _dwFrequency) +{ + vWrAPUReg (devc, _bChannel, 0x02, + (WORD) ((wRdAPUReg (devc, _bChannel, 0x02) & 0x00FF) | + (WORD) (LOBYTE (_dwFrequency) << 8))); + vWrAPUReg (devc, _bChannel, 0x03, (WORD) (_dwFrequency >> 8)); +} + +static void +vSetAPURegBit (maestro_devc * devc, BYTE _bChannel, BYTE _bRegIndex, + BYTE _bRegBit) +{ + vWrAPUReg (devc, _bChannel, _bRegIndex, + WSETBIT (wRdAPUReg (devc, _bChannel, _bRegIndex), _bRegBit)); +} + +static void +vMskAPURegBit (maestro_devc * devc, BYTE _bChannel, BYTE _bRegIndex, + BYTE _bRegBit) +{ + vWrAPUReg (devc, _bChannel, _bRegIndex, + WMSKBIT (wRdAPUReg (devc, _bChannel, _bRegIndex), _bRegBit)); +} + +static void +vSetAPUSubmixMode (maestro_devc * devc, BYTE _bChannel, BYTE _bState) +{ + switch (_bState) + { + case DISABLE: + vMskAPURegBit (devc, _bChannel, 0x02, 3); + break; + + case ENABLE: + vSetAPURegBit (devc, _bChannel, 0x02, 3); + break; + } +} + +static void +vSetAPUSubmixGroup (maestro_devc * devc, BYTE _bChannel, BYTE _bSubmixGroup) +{ + vWrAPUReg (devc, _bChannel, 0x02, + (WORD) ((wRdAPUReg (devc, _bChannel, 0x02) & 0xFFF8) | + _bSubmixGroup)); +} + +static void +vSetAPU6dB (maestro_devc * devc, BYTE _bChannel, BYTE _bState) +{ + switch (_bState) + { + case DISABLE: + vMskAPURegBit (devc, _bChannel, 0x02, 4); + break; + + case ENABLE: + vSetAPURegBit (devc, _bChannel, 0x02, 4); + break; + } +} + +static void +vSetAPUType (maestro_devc * devc, BYTE _bChannel, BYTE _bType) +{ + vWrAPUReg (devc, _bChannel, 0x00, + (wRdAPUReg (devc, _bChannel, 0x00) & 0xFF0F) | (_bType << 4)); +} + +static void +vSetAPUDMA (maestro_devc * devc, BYTE _bChannel, BYTE _bState) +{ + switch (_bState) + { + case DISABLE: + vMskAPURegBit (devc, _bChannel, 0x00, 14); + break; + + case ENABLE: + vSetAPURegBit (devc, _bChannel, 0x00, 14); + break; + } +} + +static void +vSetAPUFilterType (maestro_devc * devc, BYTE _bChannel, BYTE _bFilterType) +{ + vWrAPUReg (devc, _bChannel, 0x00, + (WORD) ((wRdAPUReg (devc, _bChannel, 0x00) & 0xFFF3) | + (_bFilterType << 2))); +} + +static void +vSetAPUFilterQ (maestro_devc * devc, BYTE _bChannel, BYTE _bFilterQ) +{ + vWrAPUReg (devc, _bChannel, 0x00, + (WORD) ((wRdAPUReg (devc, _bChannel, 0x00) & 0xFFFC) | + _bFilterQ)); +} + +static void +vSetAPUFilterTuning (maestro_devc * devc, BYTE _bChannel, BYTE _bFilterTuning) +{ + vWrAPUReg (devc, _bChannel, 0x0A, + (WORD) ((wRdAPUReg (devc, _bChannel, 0x0A) & 0x00FF) | + ((WORD) _bFilterTuning << 8))); +} + +static void +vSetAPUPolarPan (maestro_devc * devc, BYTE _bChannel, BYTE _bPolarPan) +{ + vWrAPUReg (devc, _bChannel, 0x0A, + (WORD) ((wRdAPUReg (devc, _bChannel, 0x0A) & 0xFFC0) | + _bPolarPan)); +} + +static void +vSetAPUDataSourceA (maestro_devc * devc, BYTE _bChannel, BYTE _bDataSourceA) +{ + vWrAPUReg (devc, _bChannel, 0x0B, + (WORD) ((wRdAPUReg (devc, _bChannel, 0x0B) & 0xFF80) | + _bDataSourceA)); +} + +static void +vSetAPUAmplitudeNow (maestro_devc * devc, BYTE _bChannel, BYTE _bAmplitude) +{ + vWrAPUReg (devc, _bChannel, 0x09, + (WORD) ((wRdAPUReg (devc, _bChannel, 0x09) & 0x00FF) | + (((WORD) _bAmplitude << 8)))); +} + +static void +vSetAPUWave64kPage (maestro_devc * devc, BYTE _bChannel, DWORD _wWaveStart) +{ + vWrAPUReg (devc, _bChannel, 0x04, ((_wWaveStart >> 16) & 0xFF) << 8); +} + +static void +vSetAPUWaveStart (maestro_devc * devc, BYTE _bChannel, WORD _wWaveStart) +{ + vWrAPUReg (devc, _bChannel, 0x05, _wWaveStart); +} + +static void +vSetAPUWaveEnd (maestro_devc * devc, BYTE _bChannel, WORD _wWaveEnd) +{ + vWrAPUReg (devc, _bChannel, 0x06, _wWaveEnd); +} + +static void +vSetAPUWaveLoop (maestro_devc * devc, BYTE _bChannel, WORD _wWaveLoop) +{ + vWrAPUReg (devc, _bChannel, 0x07, _wWaveLoop); +} + +static void +vSetAPUWavePtr (maestro_devc * devc, BYTE _bChannel, DWORD _dwWaveStart, + WORD _wWaveLength) +{ + /* start of sample */ + vSetAPUWave64kPage (devc, _bChannel, _dwWaveStart); + vSetAPUWaveStart (devc, _bChannel, LOWORD (_dwWaveStart)); + vSetAPUWaveEnd (devc, _bChannel, LOWORD ((_dwWaveStart + _wWaveLength))); + vSetAPUWaveLoop (devc, _bChannel, _wWaveLength); +} + +/*****************************************************************************/ +/* Write Wave Cache Control I/O Port */ +/* */ +/*****************************************************************************/ +static void +vWrWCControlReg (maestro_devc * devc, WORD _wWCControlRegFlags) +{ + OUTW (devc->osdev, _wWCControlRegFlags, WAVE_CACHE_CONTROL); +} + +/*****************************************************************************/ +/* Read Wave Cache Control I/O Port */ +/* */ +/*****************************************************************************/ +static WORD +wRdWCControlReg (maestro_devc * devc) +{ + return ((WORD) (INW (devc->osdev, WAVE_CACHE_CONTROL))); +} + +/*****************************************************************************/ +/* Set Wave Cache Control Bit Flag */ +/* */ +/*****************************************************************************/ +static void +vSetWCControlRegBit (maestro_devc * devc, BYTE _bWCControlRegBit) +{ + vWrWCControlReg (devc, WSETBIT (wRdWCControlReg (devc), _bWCControlRegBit)); +} + +/*****************************************************************************/ +/* Mask Wave Cache Control Bit Flag */ +/* */ +/*****************************************************************************/ +static void +vMskWCControlRegBit (maestro_devc * devc, BYTE _bWCControlRegBit) +{ + vWrWCControlReg (devc, WMSKBIT (wRdWCControlReg (devc), _bWCControlRegBit)); +} + +/*****************************************************************************/ +/* */ +/* */ +/*****************************************************************************/ +static void +vSetWCEnable (maestro_devc * devc, BYTE _bState) +{ + switch (_bState) + { + case DISABLE: + vMskWCControlRegBit (devc, 8); + break; + + case ENABLE: + vSetWCControlRegBit (devc, 8); + break; + } +} + +/*****************************************************************************/ +/* */ +/* */ +/*****************************************************************************/ +/*ARGSUSED*/ +void +vSetTimer (maestro_devc * devc, WORD _wInterruptFreq) +{ + + int prescale; + int divide; + + /* XXX make freq selector much smarter, see calc_bob_rate */ + int freq = 200; + + /* compute ideal interrupt frequency for buffer size & play rate */ + /* first, find best prescaler value to match freq */ + for (prescale = 5; prescale < 12; prescale++) + if (freq > (SYSCLK >> (prescale + 9))) + break; + + /* next, back off prescaler whilst getting divider into optimum range */ + divide = 1; + while ((prescale > 5) && (divide < 32)) + { + prescale--; + divide <<= 1; + } + divide >>= 1; + + /* now fine-tune the divider for best match */ + for (; divide < 31; divide++) + if (freq >= ((SYSCLK >> (prescale + 9)) / (divide + 1))) + break; + + /* divide = 0 is illegal, but don't let prescale = 4! */ + if (divide == 0) + { + divide++; + if (prescale > 5) + prescale--; + } + vWrIDR (devc, 0x06, (WORD) (0x9000 | (prescale << 5) | divide)); +} + +/* + ***************************************************************************** + */ + +static int +maestro_audio_set_rate (int dev, int arg) +{ + maestro_portc *portc = audio_engines[dev]->portc; + + if (arg == 0) + return portc->speed; + + if (arg > 48000) + arg = 48000; + if (arg < 5000) + arg = 5000; + portc->speed = arg; + return portc->speed; +} + +static short +maestro_audio_set_channels (int dev, short arg) +{ + maestro_portc *portc = audio_engines[dev]->portc; + + if ((arg != 1) && (arg != 2)) + return portc->channels; + portc->channels = arg; + + return portc->channels; +} + +static unsigned int +maestro_audio_set_format (int dev, unsigned int arg) +{ + maestro_portc *portc = audio_engines[dev]->portc; + + if (arg == 0) + return portc->bits; + + if (!(arg & (AFMT_U8 | AFMT_S16_LE))) + return portc->bits; + portc->bits = arg; + + return portc->bits; +} + +/*ARGSUSED*/ +static int +maestro_audio_ioctl (int dev, unsigned int cmd, ioctl_arg arg) +{ + return OSS_EINVAL; +} + +static void maestro_audio_trigger (int dev, int state); + +static void +maestro_audio_reset (int dev) +{ + maestro_audio_trigger (dev, 0); +} + +static void +maestro_audio_reset_input (int dev) +{ + maestro_portc *portc = audio_engines[dev]->portc; + maestro_audio_trigger (dev, portc->trigger_bits & ~PCM_ENABLE_INPUT); +} + +static void +maestro_audio_reset_output (int dev) +{ + maestro_portc *portc = audio_engines[dev]->portc; + maestro_audio_trigger (dev, portc->trigger_bits & ~PCM_ENABLE_OUTPUT); +} + +/*ARGSUSED*/ +static int +maestro_audio_open (int dev, int mode, int open_flags) +{ + oss_native_word flags; + maestro_portc *portc = audio_engines[dev]->portc; + maestro_devc *devc = audio_engines[dev]->devc; + + MUTEX_ENTER_IRQDISABLE (devc->lock, flags); + if (portc->open_mode) + { + MUTEX_EXIT_IRQRESTORE (devc->lock, flags); + return OSS_EBUSY; + } +#if 1 + if ((mode & OPEN_READ)) + { + audio_engines[dev]->flags |= ADEV_16BITONLY; + } + else + { + audio_engines[dev]->flags &= ~(ADEV_16BITONLY); + } +#endif + if (devc->open_mode & mode) + { + MUTEX_EXIT_IRQRESTORE (devc->lock, flags); + return OSS_EBUSY; + } + + devc->open_mode |= mode; + + portc->open_mode = mode; + portc->audio_enabled &= ~mode; + MUTEX_EXIT_IRQRESTORE (devc->lock, flags); + + return 0; +} + +static void +maestro_audio_close (int dev, int mode) +{ + maestro_portc *portc = audio_engines[dev]->portc; + maestro_devc *devc = audio_engines[dev]->devc; + + maestro_audio_reset (dev); + portc->open_mode = 0; + devc->open_mode &= ~mode; + portc->audio_enabled &= ~mode; +} + +/*ARGSUSED*/ +static void +maestro_audio_output_block (int dev, oss_native_word buf, int count, + int fragsize, int intrflag) +{ + maestro_portc *portc = audio_engines[dev]->portc; + + portc->audio_enabled |= PCM_ENABLE_OUTPUT; + portc->trigger_bits &= ~PCM_ENABLE_OUTPUT; +} + +/*ARGSUSED*/ +static void +maestro_audio_start_input (int dev, oss_native_word buf, int count, + int fragsize, int intrflag) +{ + maestro_portc *portc = audio_engines[dev]->portc; + + portc->audio_enabled |= PCM_ENABLE_INPUT; + portc->trigger_bits &= ~PCM_ENABLE_INPUT; + +} + +static void +maestro_audio_trigger (int dev, int state) +{ + oss_native_word flags; + maestro_portc *portc = audio_engines[dev]->portc; + maestro_devc *devc = audio_engines[dev]->devc; + + MUTEX_ENTER_IRQDISABLE (devc->lock, flags); + + if (portc->open_mode & OPEN_WRITE) + { + if (state & PCM_ENABLE_OUTPUT) + { + if ((portc->audio_enabled & PCM_ENABLE_OUTPUT) && + !(portc->trigger_bits & PCM_ENABLE_OUTPUT)) + { + if (portc->bits == AFMT_U8) + { + vSetAPUType (devc, bAPURPlay, 0x03); + if (portc->channels == 2) + { + vSetAPUType (devc, bAPURPlay, 0x04); + vSetAPUType (devc, bAPULPlay, 0x04); + } + } + if (portc->bits == AFMT_S16_LE) + { + vSetAPUType (devc, bAPURPlay, 0x01); + if (portc->channels == 2) + { + vSetAPUType (devc, bAPURPlay, 0x02); + vSetAPUType (devc, bAPULPlay, 0x02); + } + } + portc->trigger_bits |= PCM_ENABLE_OUTPUT; + } + } + else + { + if ((portc->audio_enabled & PCM_ENABLE_OUTPUT) && + (portc->trigger_bits & PCM_ENABLE_OUTPUT)) + { + portc->trigger_bits &= ~PCM_ENABLE_OUTPUT; + portc->audio_enabled &= ~PCM_ENABLE_OUTPUT; + vSetAPUType (devc, bAPURPlay, 0x0000); + vSetAPUType (devc, bAPULPlay, 0x0000); + } + } + } + + if (portc->open_mode & OPEN_READ) + { + if (state & PCM_ENABLE_INPUT) + { + if ((portc->audio_enabled & PCM_ENABLE_INPUT) && + !(portc->trigger_bits & PCM_ENABLE_INPUT)) + { + vSetAPUType (devc, bAPULMix, 0x09); + vSetAPUType (devc, bAPULSrc, 0x0B); + if (portc->channels == 2) + { + vSetAPUType (devc, bAPURMix, 0x09); + vSetAPUType (devc, bAPURSrc, 0x0B); + } + portc->trigger_bits |= PCM_ENABLE_INPUT; + } + } + else + { + if ((portc->audio_enabled & PCM_ENABLE_INPUT) && + (portc->trigger_bits & PCM_ENABLE_INPUT)) + { + portc->trigger_bits &= ~PCM_ENABLE_INPUT; + portc->audio_enabled &= ~PCM_ENABLE_INPUT; + vSetAPUType (devc, bAPURMix, 0x00); + vSetAPUType (devc, bAPURSrc, 0x00); + vSetAPUType (devc, bAPULMix, 0x00); + vSetAPUType (devc, bAPULSrc, 0x00); + } + } + } + MUTEX_EXIT_IRQRESTORE (devc->lock, flags); +} + +/*ARGSUSED*/ +static int +maestro_audio_prepare_for_input (int dev, int bsize, int bcount) +{ + maestro_devc *devc = audio_engines[dev]->devc; + maestro_portc *portc = audio_engines[dev]->portc; + dmap_t *dmap = audio_engines[dev]->dmap_in; + + oss_native_word flags; + + WORD wIndex, channel; + unsigned int wSampleRate = portc->speed; + int skip = 2; + +#if 0 + if (portc->channels == 2) + { + cmn_err (CE_WARN, "Stereo recording not supported\n"); + return OSS_EIO; + } +#endif + + MUTEX_ENTER_IRQDISABLE (devc->lock, flags); + + devc->wApuBufferSize = dmap->bytes_in_use >> 1; + + if (wSampleRate > 47999) + wSampleRate = 47999; + if (wSampleRate < 5000) + wSampleRate = 5000; + + + if (portc->channels == 2) + { + devc->wApuBufferSize >>= 1; + if (portc->bits == 16) + wSampleRate <<= 1; + skip = 1; + } + + for (channel = 2; channel < 6; channel += skip) + { + int bsize, route; + unsigned int physaddr; + unsigned int rate; + + /* Clear out the APU */ + for (wIndex = 0; wIndex < 16; wIndex++) + vWrAPUReg (devc, channel, (WORD) wIndex, 0x0000); + + /* data seems to flow from the codec, through an apu into + the 'mixbuf' bit of page, then through the SRC apu + and out to the real 'buffer'. */ + + if (channel & 0x04) + { + /* codec to mixbuf left */ + if (!(channel & 0x01)) + physaddr = devc->dma_mix.base; + else + /* codec to mixbuf right */ + physaddr = devc->dma_mix.base + (PAGE_SIZE >> 4); + + + bsize = PAGE_SIZE >> 5; /* 256 bytes needed for Mixbuf */ + route = 0x14 + (channel - 4); /* input routed from parallelin base */ + + /* The Mixer always runs at 48Khz. */ + rate = 0x10000; + vSetAPUFrequency (devc, channel, rate); + + } + else + { + /* sample rate converter takes input from the mixer apu and + outputs it to system memory */ + + if (!(channel & 0x01)) + /* left channel records its half */ + physaddr = dmap->dmabuf_phys; + + else + /* right channel records its half */ + physaddr = dmap->dmabuf_phys + devc->wApuBufferSize * 2; + + bsize = devc->wApuBufferSize; + /* get input from inputing apu */ + route = channel + 2; + + /* SRC takes 48Khz data from mixer and converts it to requested rate */ + rate = (DWORD) wCalculateAPUFrequency (wSampleRate); + vSetAPUFrequency (devc, channel, rate); + + + } + + /* set the wavecache control reg */ + vSetWCChannelTagAddr (devc, channel, + (LOWORD (physaddr) - 0x10) & 0xFFF8); + vSetWCChannelStereo (devc, channel, 0); + vSetWCChannelWordSize (devc, channel, 1); + + physaddr -= devc->dmapages_phys; + physaddr >>= 1; /* words */ + + /* base offset of dma calcs when reading the pointer + on this left one */ +#if 0 + if (channel == 2) + devc->dma_adc.base = physaddr & 0xFFFF; +#endif + physaddr |= 0x00400000; /* bit 22 -> System RAM */ + + /* Load the buffer into the wave engine */ + vSetAPUWavePtr (devc, channel, physaddr, bsize); + + /* Now set the rest of the APU params */ + vSetAPUSubmixMode (devc, channel, ENABLE); + vSetAPUSubmixGroup (devc, channel, 0x0); + vSetAPU6dB (devc, channel, DISABLE); + vSetAPUAmplitudeNow (devc, channel, 0xF0); + vSetAPUFilterTuning (devc, channel, 0x8F); + vSetAPUPolarPan (devc, channel, 0x08); + vSetAPUFilterType (devc, channel, 0x03); + vSetAPUFilterQ (devc, channel, 0x03); + vSetAPUDMA (devc, channel, ENABLE); + + /* route input */ + vSetAPUDataSourceA (devc, channel, route); + } + + vMskIDRBit (devc, 0x11, 0); + vMskIDRBit (devc, 0x17, 0); /* Disable Bob Timer Interrupts */ + vSetTimer (devc, SYSCLK / (devc->wApuBufferSize)); + vSetIDRBit (devc, 0x11, 0); + vSetIDRBit (devc, 0x17, 0); /* Enable Bob Timer Interrupts */ + portc->audio_enabled &= ~PCM_ENABLE_INPUT; + portc->trigger_bits &= ~PCM_ENABLE_INPUT; + + MUTEX_EXIT_IRQRESTORE (devc->lock, flags); + return 0; +} + +/*ARGSUSED*/ +static int +maestro_audio_prepare_for_output (int dev, int bsize, int bcount) +{ + maestro_devc *devc = audio_engines[dev]->devc; + maestro_portc *portc = audio_engines[dev]->portc; + dmap_t *dmap = audio_engines[dev]->dmap_out; + + oss_native_word flags; + + WORD wIndex, i; + DWORD dwPhysAddr; + unsigned int wSampleRate = portc->speed; + int numchans = 0; + + MUTEX_ENTER_IRQDISABLE (devc->lock, flags); + + devc->wApuBufferSize = dmap->bytes_in_use >> 1; + + if ((portc->bits == 8) && (portc->channels == 1)) + { + wSampleRate >>= 1; + } + + if (portc->channels == 2) + { + numchans++; + if (portc->bits == 16) + devc->wApuBufferSize >>= 1; + } + + for (i = 0; i <= numchans; i++) + { + + dwPhysAddr = dmap->dmabuf_phys; + + vSetWCChannelTagAddr (devc, i, + (WORD) ((LOWORD (dwPhysAddr) - 0x10) & 0xFFF8)); + + if (portc->bits == 16) + vSetWCChannelWordSize (devc, i, 1); + else + vSetWCChannelWordSize (devc, i, 0); + + if (portc->channels == 2) + vSetWCChannelStereo (devc, i, 1); + else + vSetWCChannelStereo (devc, i, 0); + + /* Calculate WP base address */ + dwPhysAddr -= devc->dmapages_phys; + dwPhysAddr >>= 1; /* adjust for word size */ +#if 0 + if (i) + devc->dma_dac.base = dwPhysAddr & 0xFFFF; +#endif + dwPhysAddr |= 0x00400000L; /* Enable bit 22 for system ram access */ + + + if (portc->channels == 2) + { + if (!i) + dwPhysAddr |= 0x00800000; + if (portc->bits == 16) + { + dwPhysAddr >>= 1; + } + } + for (wIndex = 0; wIndex < 16; wIndex++) + vWrAPUReg (devc, i, (BYTE) wIndex, 0x0000); + + vSetAPUFrequency (devc, i, + (DWORD) wCalculateAPUFrequency (wSampleRate)); + vSetAPUWavePtr (devc, i, dwPhysAddr, devc->wApuBufferSize); + vSetAPU6dB (devc, i, DISABLE); + vSetAPUAmplitudeNow (devc, i, 0xF0); + vSetAPUFilterTuning (devc, i, 0x8F); + if (portc->channels == 2) + vSetAPUPolarPan (devc, i, (i ? 0x10 : 0x00)); + else + vSetAPUPolarPan (devc, i, 0x08); + vSetAPUFilterType (devc, i, 0x03); + vSetAPUFilterQ (devc, i, 0x03); + vSetAPUDMA (devc, i, ENABLE); + } + + vMskIDRBit (devc, 0x11, 0); + vMskIDRBit (devc, 0x17, 0); /* Disable Bob Timer Interrupts */ + vSetTimer (devc, SYSCLK / devc->wApuBufferSize); + vSetIDRBit (devc, 0x11, 0); + vSetIDRBit (devc, 0x17, 0); /* Enable Bob Timer Interrupts */ + portc->audio_enabled &= ~PCM_ENABLE_OUTPUT; + portc->trigger_bits &= ~PCM_ENABLE_OUTPUT; + MUTEX_EXIT_IRQRESTORE (devc->lock, flags); + return 0; +} + +static int +maestro_alloc_buffer (int dev, dmap_t * dmap, int direction) +{ + maestro_devc *devc = audio_engines[dev]->devc; + + if (dmap->dmabuf != NULL) + return 0; + + if (direction == PCM_ENABLE_OUTPUT) + { + dmap->dmabuf = devc->dma_dac.rawbuf; + dmap->dmabuf_phys = devc->dma_dac.base; + dmap->buffsize = devc->dma_dac.dmasize; + } + + if (direction == PCM_ENABLE_INPUT) + { + dmap->dmabuf = devc->dma_adc.rawbuf; + dmap->dmabuf_phys = devc->dma_adc.base; + dmap->buffsize = devc->dma_adc.dmasize; + } + return 0; +} + +/*ARGSUSED*/ +static int +maestro_free_buffer (int dev, dmap_t * dmap, int direction) +{ + if (dmap->dmabuf == NULL) + return 0; + + dmap->dmabuf = NULL; + dmap->dmabuf_phys = 0; + dmap->buffsize = 0; + + return 0; +} + +/*ARGSUSED*/ +static int +maestro_get_buffer_pointer (int dev, dmap_t * dmap, int direction) +{ + maestro_devc *devc = audio_engines[dev]->devc; + maestro_portc *portc = audio_engines[dev]->portc; + int ptr = 0; + oss_native_word flags; + + if (!(portc->open_mode & direction)) + return 0; + + MUTEX_ENTER_IRQDISABLE (devc->low_lock, flags); + if (direction == PCM_ENABLE_INPUT) + { + ptr = wRdAPUReg (devc, bAPULSrc, 0x05); + ptr = (ptr - devc->dma_adc.base) & 0xFFFE; + } + + if (direction == PCM_ENABLE_OUTPUT) + { + ptr = wRdAPUReg (devc, bAPURPlay, 0x05); + ptr = (ptr - devc->dma_dac.base) & 0xFFFE; + } + ptr = (ptr % devc->wApuBufferSize) << 1; + MUTEX_EXIT_IRQRESTORE (devc->low_lock, flags); + return (ptr); +} + +static void +set_maestro_base (maestro_devc * devc) +{ + unsigned long packed_phys = devc->dmapages_phys >> 12; + vWrWCReg (devc, 0x01FC, packed_phys); + vWrWCReg (devc, 0x01FD, packed_phys); + vWrWCReg (devc, 0x01FE, packed_phys); + vWrWCReg (devc, 0x01FF, packed_phys); +} + +static int +allocate_maestro_bufs (maestro_devc * devc) +{ + unsigned char *rawbuf = NULL; + int size, extra, start; + oss_native_word phaddr; + + /* size = size of rec/play buffers + * start = offset from beginning for rec/play buffers + * extra=size of mix buf + start + */ +#if defined(sun) || defined(linux) + size = 32 * 1024; + start = 16 * 1024; + extra = 16 * 1024; +#else +#if defined (__FreeBSD__) + size = 64 * 1024; + start = 8 * 1024; + extra = 16 * 1024; +#else + size = 96 * 1024; + start = 16 * 1024; + extra = 16 * 1024; +#endif +#endif + devc->dmalen = size + extra; + + rawbuf = + (void *) CONTIG_MALLOC (devc->osdev, devc->dmalen, MEMLIMIT_28BITS, + &phaddr, TODO); + + if (!rawbuf) + return 1; + + DDB (cmn_err (CE_WARN, "addr=%p, size=%d\n", (void *) rawbuf, size)); + + if ((phaddr + size - 1) & ~((1 << 28) - 1)) + { + cmn_err (CE_WARN, "DMA buffer beyond 256MB\n"); + CONTIG_FREE (devc->osdev, rawbuf, size + extra, TODO); + return 1; + } + + devc->dmapages = rawbuf; + devc->dmapages_phys = phaddr; + + devc->dma_dac.rawbuf = rawbuf + start; + devc->dma_dac.dmasize = size / 2; + devc->dma_dac.base = phaddr + start; + + devc->dma_adc.rawbuf = devc->dma_dac.rawbuf + size / 2; + devc->dma_adc.dmasize = size / 2; + devc->dma_adc.base = devc->dma_dac.base + size / 2; + + devc->dma_mix.rawbuf = rawbuf + 4096; + devc->dma_mix.base = phaddr + 4096; + devc->dma_mix.dmasize = 4096; +#ifdef linux + /* reserve the pages for MMAP */ + oss_reserve_pages ((oss_native_word) devc->dma_dac.rawbuf, + (oss_native_word) devc->dma_dac.rawbuf + + devc->dma_dac.dmasize - 1); +#endif + return 0; +} + +static audiodrv_t maestro_audio_driver = { + maestro_audio_open, + maestro_audio_close, + maestro_audio_output_block, + maestro_audio_start_input, + maestro_audio_ioctl, + maestro_audio_prepare_for_input, + maestro_audio_prepare_for_output, + maestro_audio_reset, + NULL, + NULL, + maestro_audio_reset_input, + maestro_audio_reset_output, + maestro_audio_trigger, + maestro_audio_set_rate, + maestro_audio_set_format, + maestro_audio_set_channels, + NULL, + NULL, + NULL, /* maestro_check_input, */ + NULL, /* maestro_check_output, */ + maestro_alloc_buffer, + maestro_free_buffer, + NULL, + NULL, + maestro_get_buffer_pointer +}; + +static mixer_driver_t pt101_mixer_driver = { + pt101_mixer_ioctl +}; + + +static void +maestro_ac97_reset (maestro_devc * devc) +{ + int save_68; + +/* Reset the Codec */ + OUTW (devc->osdev, INW (devc->osdev, devc->base + 0x38) & 0xfffc, + devc->base + 0x38); + OUTW (devc->osdev, INW (devc->osdev, devc->base + 0x3a) & 0xfffc, + devc->base + 0x3a); + OUTW (devc->osdev, INW (devc->osdev, devc->base + 0x3c) & 0xfffc, + devc->base + 0x3c); + /* reset the first codec */ + OUTW (devc->osdev, 0x0000, devc->base + 0x36); + save_68 = INW (devc->osdev, devc->base + 0x68); + if (devc->gpio & 0x1) + save_68 |= 0x10; + OUTW (devc->osdev, 0xfffe, devc->base + 0x64); /* tickly gpio 0.. */ + OUTW (devc->osdev, 0x0001, devc->base + 0x68); + OUTW (devc->osdev, 0x0000, devc->base + 0x60); + oss_udelay (10); + OUTW (devc->osdev, 0x0001, devc->base + 0x60); + oss_udelay (100); + OUTW (devc->osdev, save_68 | 0x1, devc->base + 0x68); /* now restore .. */ + OUTW (devc->osdev, (INW (devc->osdev, devc->base + 0x38) & 0xfffc) | 0x1, + devc->base + 0x38); + OUTW (devc->osdev, (INW (devc->osdev, devc->base + 0x3a) & 0xfffc) | 0x1, + devc->base + 0x3a); + OUTW (devc->osdev, (INW (devc->osdev, devc->base + 0x3c) & 0xfffc) | 0x1, + devc->base + 0x3c); + + /* now the second codec */ + OUTW (devc->osdev, 0x0000, devc->base + 0x36); + OUTW (devc->osdev, 0xfff7, devc->base + 0x64); + save_68 = INW (devc->osdev, devc->base + 0x68); + OUTW (devc->osdev, 0x0009, devc->base + 0x68); + OUTW (devc->osdev, 0x0001, devc->base + 0x60); + oss_udelay (10); + OUTW (devc->osdev, 0x0009, devc->base + 0x60); + oss_udelay (100); + OUTW (devc->osdev, INW (devc->osdev, devc->base + 0x38) & 0xfffc, + devc->base + 0x38); + OUTW (devc->osdev, INW (devc->osdev, devc->base + 0x3a) & 0xfffc, + devc->base + 0x3a); + OUTW (devc->osdev, INW (devc->osdev, devc->base + 0x3c) & 0xfffc, + devc->base + 0x3c); +} + +static int +init_maestro (maestro_devc * devc) +{ + int my_mixer; + int i; + oss_native_word n; + unsigned short w; + int wIndex; + int first_dev = 0; + int codec_id; + int bRow, bAPU; + +/* Sound reset */ + OUTW (devc->osdev, 0x2000, 0x18 + devc->base); + oss_udelay (10); + OUTW (devc->osdev, 0x0000, 0x18 + devc->base); + oss_udelay (10); + +/* Setup 0x34 and 0x36 regs */ + OUTW (devc->osdev, 0xc090, devc->base + 0x34); + oss_udelay (1000); + OUTW (devc->osdev, 0x3000, devc->base + 0x36); + oss_udelay (1000); + +/* reset ac97 link */ + maestro_ac97_reset (devc); + +/* DirectSound*/ + n = INL (devc->osdev, devc->base + 0x34); + n &= ~0xF000; + n |= 12 << 12; /* Direct Sound, Stereo */ + OUTL (devc->osdev, n, devc->base + 0x34); + + n = INL (devc->osdev, devc->base + 0x34); + n &= ~0x0F00; /* Modem off */ + OUTL (devc->osdev, n, devc->base + 0x34); + + n = INL (devc->osdev, devc->base + 0x34); + n &= ~0x00F0; + n |= 9 << 4; /* DAC, Stereo */ + OUTL (devc->osdev, n, devc->base + 0x34); + + n = INL (devc->osdev, devc->base + 0x34); + n &= ~0x000F; /* ASSP off */ + OUTL (devc->osdev, n, devc->base + 0x34); + + n = INL (devc->osdev, devc->base + 0x34); + n |= (1 << 29); /* Enable ring bus */ + OUTL (devc->osdev, n, devc->base + 0x34); + + n = INL (devc->osdev, devc->base + 0x34); + n |= (1 << 28); /* Enable serial bus */ + OUTL (devc->osdev, n, devc->base + 0x34); + + n = INL (devc->osdev, devc->base + 0x34); + n &= ~0x00F00000; /* MIC off */ + OUTL (devc->osdev, n, devc->base + 0x34); + + n = INL (devc->osdev, devc->base + 0x34); + n &= ~0x000F0000; /* I2S off */ + OUTL (devc->osdev, n, devc->base + 0x34); + + w = INW (devc->osdev, devc->base + 0x18); + w &= ~(1 << 7); /* ClkRun off */ + OUTW (devc->osdev, w, devc->base + 0x18); + + w = INW (devc->osdev, devc->base + 0x18); + w &= ~(1 << 6); /* Harpo off */ + OUTW (devc->osdev, w, devc->base + 0x18); + + w = INW (devc->osdev, devc->base + 0x18); + w &= ~(1 << 4); /* ASSP irq off */ + OUTW (devc->osdev, w, devc->base + 0x18); + + w = INW (devc->osdev, devc->base + 0x18); + w &= ~(1 << 3); /* ISDN irq off */ + OUTW (devc->osdev, w, devc->base + 0x18); + + w = INW (devc->osdev, devc->base + 0x18); + w |= (1 << 2); /* Direct Sound IRQ on */ + OUTW (devc->osdev, w, devc->base + 0x18); + + w = INW (devc->osdev, devc->base + 0x18); + w &= ~(1 << 1); /* MPU401 IRQ off */ + OUTW (devc->osdev, w, devc->base + 0x18); + + w = INW (devc->osdev, devc->base + 0x18); + w &= ~(1 << 0); /* SB IRQ on */ + OUTW (devc->osdev, w, devc->base + 0x18); + + OUTB (devc->osdev, 0x00, gwPTBaseIO + 0xA4); + OUTB (devc->osdev, 0x03, gwPTBaseIO + 0xA2); + OUTB (devc->osdev, 0x00, gwPTBaseIO + 0xA6); + + if (devc->model == ESS_MAESTRO) + { +/* Clear out wavecache */ + for (wIndex = 0; wIndex < 0x0200; wIndex++) + vWrWCReg (devc, wIndex, 0x0000); +/* Clear out APU */ + for (wIndex = 0; wIndex < 0x40; wIndex++) + vWrAPUReg (devc, wIndex, 0x00, 0x0000); +/* Clear out WP */ + for (wIndex = 0; wIndex < 0x1F; wIndex++) + devc->wIDRRegDataTable[wIndex] = 0x0000; + } + else + { +/* Clear out Wave Cache */ + for (bRow = 0; bRow < 0x10; bRow++) + { + vWrWCReg (devc, (WORD) (0x01E0 + bRow), 0x0000); + } + + /* Clear Control RAM */ + for (bAPU = 0x00; bAPU < 0x40; bAPU++) + { + for (bRow = 0; bRow < 0x0E; bRow++) + { + vWrAPUReg (devc, bAPU, bRow, 0x0000); + } + } + } + + vWrIDR (devc, 0x02, 0x0000); /* CRam Increment */ + vWrIDR (devc, 0x08, 0xB004); /* Audio Serial Configuration */ + vWrIDR (devc, 0x09, 0x001B); /* Audio Serial Configuration */ + vWrIDR (devc, 0x0A, 0x8000); /* Audio Serial Configuration */ + vWrIDR (devc, 0x0B, 0x3F37); /* Audio Serial Configuration */ + vWrIDR (devc, 0x0C, 0x0098); + + /* parallel out */ + vWrIDR (devc, 0x0C, (wRdIDR (devc, 0x0C) & ~0xF000) | 0x8000); + /* parallel in */ + vWrIDR (devc, 0x0C, (wRdIDR (devc, 0x0C) & ~0x0F00) | 0x0500); + + vWrIDR (devc, 0x0D, 0x7632); /*Audio Serial Configuration */ + OUTW (devc->osdev, INW (devc->osdev, 0x14 + devc->base) | (1 << 8), + 0x14 + devc->base); + OUTW (devc->osdev, INW (devc->osdev, 0x14 + devc->base) & 0xFE03, + 0x14 + devc->base); + OUTW (devc->osdev, (INW (devc->osdev, 0x14 + devc->base) & 0xFFFC), + 0x14 + devc->base); + OUTW (devc->osdev, INW (devc->osdev, 0x14 + devc->base) | (1 << 7), + 0x14 + devc->base); + + /* enable the Wavecache */ + vSetWCEnable (devc, ENABLE); + /* Unmask WP interrupts */ + OUTW (devc->osdev, (WORD) (INW (devc->osdev, devc->base + 0x18) + | 0x0004), devc->base + 0x18); + + if (devc->model == ESS_MAESTRO) + { + OUTW (devc->osdev, 0xA1A0, gwPTBaseIO + 0x14); + } + else + { + OUTW (devc->osdev, 0xA1A0, gwPTBaseIO + 0x14); + } + +/* First get the Codec ID type - check if it is PT101 or AC97*/ + codec_id = ac97_read (devc, 0x00); + +/* initialize the PT101 Codec */ + if (codec_id == 0x80) + { + ac97_write (devc, 0x09, 0x0000); /*DAC Mute */ + ac97_write (devc, 0x0F, 0x0000); + ac97_write (devc, 0x11, 0x0000); + ac97_write (devc, 0x14, 0x0000); + ac97_write (devc, 0x1A, 0x0105); + ac97_write (devc, 0x1E, 0x0101); /*set PT101 reg 0x1F */ + ac97_write (devc, 0x1F, 0x8080); /*set PT101 reg 0x1F */ + } + + if ((devc->model == ESS_MAESTRO2E) || (devc->model == ESS_MAESTRO2)) + { + outpw (gwPTBaseIO + 0x02, (WORD) 0x0001); + outpw (gwPTBaseIO + 0x00, (WORD) 0x03C0); + outpw (gwPTBaseIO + 0x02, (WORD) 0x1); + outpw (gwPTBaseIO + 0x02, (WORD) 0x1); + outpw (gwPTBaseIO + 0x00, (WORD) 0x3c0); + outpw (gwPTBaseIO + 0x02, (WORD) 0x0000); + outpw (gwPTBaseIO + 0x00, (WORD) 0x4010); + outpw (gwPTBaseIO + 0x02, (WORD) 0x0001); + outpw (gwPTBaseIO + 0x00, (WORD) 0x03D0); + outpw (gwPTBaseIO + 0x02, (WORD) 0x1); + outpw (gwPTBaseIO + 0x02, (WORD) 0x1); + outpw (gwPTBaseIO + 0x00, (WORD) 0x3d0); + outpw (gwPTBaseIO + 0x02, (WORD) 0x0000); + outpw (gwPTBaseIO + 0x00, (WORD) 0x4010); + } + else + { + outpw (gwPTBaseIO + 0x02, (WORD) 0x0001); + outpw (gwPTBaseIO + 0x00, (WORD) 0x03C0); + outpw (gwPTBaseIO + 0x02, (WORD) 0x00); + outpw (gwPTBaseIO + 0x00, (WORD) 0x401F); + + outpw (gwPTBaseIO + 0x02, (WORD) 0x0001); + outpw (gwPTBaseIO + 0x00, (WORD) 0x03D0); + outpw (gwPTBaseIO + 0x02, (WORD) 0x00); + outpw (gwPTBaseIO + 0x00, (WORD) 0x401F); + } + +/***********************ALLOCATE MEMORY************************/ + { + int ret; + + ret = allocate_maestro_bufs (devc); + if (ret != 0) + { + cmn_err (CE_WARN, "Couldn't allocate Maestro memory\n"); + return 1; + } + set_maestro_base (devc); + } +/******************INIT MIXERS*********************************/ + if (codec_id == 0x80) + { + my_mixer = oss_install_mixer (OSS_MIXER_DRIVER_VERSION, + devc->osdev, + devc->osdev, + "ESS PT101", + &pt101_mixer_driver, + sizeof (mixer_driver_t), devc); + if (my_mixer < 0) + return 0; + else + pt101_mixer_reset (devc); + } + else + { + /* Reset the codec */ + my_mixer = ac97_install (&devc->ac97devc, "Maestro2 AC97 Mixer", + ac97_read, ac97_write, devc, devc->osdev); + if (my_mixer < 0) + return 0; + } + for (i = 0; i < MAX_PORTC; i++) + { + int adev; + int caps = ADEV_AUTOMODE; + maestro_portc *portc = &devc->portc[i]; + char tmp_name[100]; + strcpy (tmp_name, devc->chip_name); + + if (i == 0) + { + strcpy (tmp_name, devc->chip_name); + caps |= ADEV_DUPLEX; + } + else + { + strcpy (tmp_name, devc->chip_name); + caps |= ADEV_DUPLEX | ADEV_SHADOW; + } + + if ((adev = oss_install_audiodev (OSS_AUDIO_DRIVER_VERSION, + devc->osdev, + devc->osdev, + tmp_name, + &maestro_audio_driver, + sizeof (audiodrv_t), + caps, + AFMT_U8 | AFMT_S16_LE, devc, -1)) < 0) + { + adev = -1; + return 0; + } + else + { + if (i == 0) + first_dev = adev; + audio_engines[adev]->portc = portc; + audio_engines[adev]->rate_source = first_dev; +#if 0 + audio_engines[adev]->min_block = 4096; + audio_engines[adev]->max_block = 4096; +#endif + audio_engines[adev]->min_rate = 5000; + audio_engines[adev]->max_rate = 48000; + audio_engines[adev]->caps |= PCM_CAP_FREERATE; + portc->audiodev = adev; + portc->open_mode = 0; + portc->trigger_bits = 0; + portc->speed = 0; + portc->bits = 0; + portc->channels = 0; + audio_engines[adev]->mixer_dev = my_mixer; + audio_engines[adev]->vmix_flags = VMIX_MULTIFRAG; +#ifdef CONFIG_OSS_VMIX + if (i == 0) + vmix_attach_audiodev(devc->osdev, adev, -1, 0); +#endif + } + } + return 1; +} + +/* NEC Versas ? */ +#define NEC_VERSA_SUBID1 0x80581033 +#define NEC_VERSA_SUBID2 0x803c1033 + +int +oss_maestro_attach (oss_device_t * osdev) +{ + unsigned short sdata; + unsigned char pci_irq_line, pci_revision; + unsigned short pci_command, vendor, device; + unsigned int pci_ioaddr, subid; + maestro_devc *devc; + + DDB (cmn_err (CE_WARN, "Entered ESS Maestro probe routine\n")); + + pci_read_config_word (osdev, PCI_VENDOR_ID, &vendor); + pci_read_config_dword (osdev, PCI_SUBSYSTEM_VENDOR_ID, &subid); + pci_read_config_byte (osdev, PCI_REVISION_ID, &pci_revision); + pci_read_config_word (osdev, PCI_COMMAND, &pci_command); + pci_read_config_word (osdev, PCI_DEVICE_ID, &device); + pci_read_config_irq (osdev, PCI_INTERRUPT_LINE, &pci_irq_line); + pci_read_config_dword (osdev, PCI_BASE_ADDRESS_0, &pci_ioaddr); + if ((vendor != ESS_VENDOR_ID && vendor != ESS2_VENDOR_ID) || + (device != ESS_MAESTRO && device != ESS_MAESTRO2 && + device != ESS_MAESTRO2E)) + + return 0; + + DDB (cmn_err (CE_WARN, "Maestro I/O base %04x\n", pci_ioaddr)); + + + if (pci_ioaddr == 0) + { + cmn_err (CE_WARN, "I/O address not assigned by BIOS.\n"); + return 0; + } + + if (pci_irq_line == 0) + { + cmn_err (CE_WARN, "IRQ not assigned by BIOS (%d).\n", pci_irq_line); + return 0; + } + + if ((devc = PMALLOC (osdev, sizeof (*devc))) == NULL) + { + cmn_err (CE_WARN, "Out of memory\n"); + return 0; + } + + + devc->osdev = osdev; + osdev->devc = devc; + + devc->base = MAP_PCI_IOADDR (devc->osdev, 0, pci_ioaddr); + /* Remove I/O space marker in bit 0. */ + devc->base &= ~0x3; + + pci_command |= PCI_COMMAND_MASTER | PCI_COMMAND_IO; + pci_write_config_word (osdev, PCI_COMMAND, pci_command); + + switch (device) + { + case ESS_MAESTRO2E: + devc->model = MD_MAESTRO2E; + devc->chip_name = "Maestro-2E"; + SYSCLK = 50000000L; + break; + + case ESS_MAESTRO2: + devc->model = MD_MAESTRO2; + devc->chip_name = "Maestro-2"; + SYSCLK = 50000000L; + break; + + case ESS_MAESTRO: + default: + devc->model = MD_MAESTRO1; + devc->chip_name = "Maestro-1"; + SYSCLK = 49152000L; + break; + } + + if (subid == NEC_VERSA_SUBID1 || subid == NEC_VERSA_SUBID2) + { + /* turn on external amp? */ + OUTW (devc->osdev, 0xf9ff, devc->base + 0x64); + OUTW (devc->osdev, INW (devc->osdev, devc->base + 0x68) | 0x600, + devc->base + 0x68); + OUTW (devc->osdev, 0x0209, devc->base + 0x60); + } + + + /* Legacy Audio Control */ + pci_read_config_word (osdev, 0x40, &sdata); + sdata |= (1 << 15); /* legacy decode off */ + sdata &= ~(1 << 14); /* Disable SIRQ */ + sdata &= ~(0x1f); /* disable mpu irq/io, game port, fm, SB */ + + pci_write_config_word (osdev, 0x40, sdata); + + /* MIDI/SB I/O, IRQ Control */ + pci_read_config_word (osdev, 0x50, &sdata); + sdata &= ~(1 << 5); + pci_write_config_word (osdev, 0x50, sdata); + + /* GPIO Control */ + pci_read_config_word (osdev, 0x52, &sdata); + sdata &= ~(1 << 15); /* Turn off internal clock multiplier */ + /* XXX how do we know which to use? */ + sdata &= ~(1 << 14); /* External clock */ + sdata &= ~(1 << 7); /* HWV off */ + sdata &= ~(1 << 6); /* Debounce off */ + sdata &= ~(1 << 5); /* GPIO 4:5 */ + sdata |= (1 << 4); /* Disconnect from the CHI. */ + /* Enabling this made dell 7500 work. */ + sdata &= ~(1 << 2); /* MIDI fix off (undoc) */ + sdata &= ~(1 << 1); /* reserved, always write 0 */ + pci_write_config_word (osdev, 0x52, sdata); + if (devc->model == ESS_MAESTRO2E) + { + pci_write_config_word (osdev, 0x54, 0x0000); + pci_write_config_word (osdev, 0x56, 0x0000); + pci_write_config_word (osdev, 0x58, 0x0000); + pci_write_config_word (osdev, 0xC4, 0x8000); + pci_read_config_word (osdev, 0x68, &devc->gpio); + } + + MUTEX_INIT (devc->osdev, devc->lock, MH_DRV); + MUTEX_INIT (devc->osdev, devc->low_lock, MH_DRV + 1); + + oss_register_device (osdev, devc->chip_name); + + if (oss_register_interrupts (devc->osdev, 0, maestrointr, NULL) < 0) + { + cmn_err (CE_WARN, "Can't allocate IRQ%d\n", pci_irq_line); + return 0; + } + + return init_maestro (devc); /* Detected */ +} + + +int +oss_maestro_detach (oss_device_t * osdev) +{ + maestro_devc *devc = (maestro_devc *) osdev->devc; + + if (oss_disable_device (osdev) < 0) + return 0; + + /* Stop WP interrutps */ + OUTW (devc->osdev, (WORD) (INW (devc->osdev, devc->base + 0x18) & 0xFFF8), + devc->base + 0x18); + OUTW (devc->osdev, 0x0001, devc->base + 0x04); + vSetWCEnable (devc, DISABLE); + vMskIDRBit (devc, 0x17, 0); /* Disable Bob Timer Interrupts */ + + oss_unregister_interrupts (devc->osdev); + if (devc->dmapages != NULL) + CONTIG_FREE (devc->osdev, devc->dmapages, devc->dmalen, TODO); + + MUTEX_CLEANUP (devc->lock); + MUTEX_CLEANUP (devc->low_lock); + UNMAP_PCI_IOADDR (devc->osdev, 0); + + oss_unregister_device (osdev); + return 1; + +} diff --git a/attic/drv/oss_maestro/oss_maestro.man b/attic/drv/oss_maestro/oss_maestro.man new file mode 100644 index 0000000..1b386dd --- /dev/null +++ b/attic/drv/oss_maestro/oss_maestro.man @@ -0,0 +1,19 @@ +NAME +oss_maestro - ESS Maestro audio driver. + +DESCRIPTION +Open Sound System driver for ESS Maestro1/Maestro2/Maestro2E soundcards +Maestro device characteristics: + o 8/16 bit playback/record + o mono/stereo playback/recording + o 8KHz to 48Khz sample rate. + +OPTIONS +None + +FILES +CONFIGFILEPATH/oss_maestro.conf Device configuration file + +AUTHOR +4Front Technologies + diff --git a/attic/drv/oss_neomagic/.config b/attic/drv/oss_neomagic/.config new file mode 100644 index 0000000..5280084 --- /dev/null +++ b/attic/drv/oss_neomagic/.config @@ -0,0 +1 @@ +platform=i86pc diff --git a/attic/drv/oss_neomagic/.devices b/attic/drv/oss_neomagic/.devices new file mode 100644 index 0000000..f5449f0 --- /dev/null +++ b/attic/drv/oss_neomagic/.devices @@ -0,0 +1 @@ +oss_neomagic pci10c8,8005 Neomagic NM2200AV diff --git a/attic/drv/oss_neomagic/.name b/attic/drv/oss_neomagic/.name new file mode 100644 index 0000000..02c6d63 --- /dev/null +++ b/attic/drv/oss_neomagic/.name @@ -0,0 +1 @@ +Neomagic NM2200AV diff --git a/attic/drv/oss_neomagic/neomagic.h b/attic/drv/oss_neomagic/neomagic.h new file mode 100644 index 0000000..ba35123 --- /dev/null +++ b/attic/drv/oss_neomagic/neomagic.h @@ -0,0 +1,302 @@ +/* + * Purpose: Definitions for the neomagic driver + */ +/* + * + * This file is part of Open Sound System. + * + * Copyright (C) 4Front Technologies 1996-2008. + * + * This this source file is released under GPL v2 license (no other versions). + * See the COPYING file included in the main directory of this source + * distribution for the license terms and conditions. + * + */ + +typedef unsigned char U8; +typedef unsigned short U16; +typedef unsigned int U32; + +/* The revisions that we currently handle. */ +enum neomagicrev +{ + REV_NEOMAGICAV, REV_NEOMAGICZX +}; + +#define MAX_PORTC 2 + +/* The two memory ports. */ +typedef struct neomagic_portc +{ + unsigned int physaddr; /* Physical address of the port. */ + char *ptr; /* Our mapped-in pointer. */ + unsigned int start_offset; /* PTR's offset within the physical port. */ + unsigned int end_offset; /* And the offset of the end of the buffer. */ + unsigned int samplerate; + unsigned char bits; + unsigned char stereo; +} +neomagic_portc; + + +typedef struct neomagic_devc +{ + /* OS struct for OSS */ + oss_device_t *osdev; + + /* Our IRQ number. */ + int irq; + + /* Mutex */ + oss_mutex_t mutex; + oss_mutex_t low_mutex; + + /* Magic number used to verify that this struct is valid. */ +#define NM_MAGIC_SIG 0x55aa00ff + int magsig; + + enum neomagicrev rev; /* Revision number */ + + char *chip_name; /* Chip name. */ + + ac97_devc ac97devc; + + int dev[2]; /* Our audio device numbers. */ + + int opencnt[2]; /* The # of times each device has been opened. */ + + /* We use two devices, because we can do simultaneous play and record. + This keeps track of which device is being used for what purpose; + these are the actual device numbers. */ + int dev_for_play; + int dev_for_record; + + int mixer_dev; /* The mixer device. */ + + /* + * Can only be opened once for each operation. These aren't set + * until an actual I/O operation is performed; this allows one + * device to be open for read/write without inhibiting I/O to + * the other device. + */ + int is_open_play; + int is_open_record; + + int playing; /* Non-zero if we're currently playing a sample. */ + int recording; /* Same for recording a sample. */ + + neomagic_portc portc[MAX_PORTC]; + + /* The following are offsets within memory port 1. */ + unsigned int coeffBuf; + unsigned int allCoeffBuf; + + /* Record and playback buffers. */ + unsigned int abuf1, abuf2; + char *abuf1virt, *abuf2virt; + + /* Offset of the mixer status register in memory port 2. */ + unsigned int mixer_status_offset; + + /* + * Status mask bit; (*mixer_status_loc & mixer_status_mask) == 0 means + * it's ready. + */ + unsigned short mixer_status_mask; + + /* The sizes of the playback and record ring buffers. */ + unsigned int playbackBufferSize; + unsigned int recordBufferSize; + + /* The devc interrupt service routine. */ + int (*introutine) (struct neomagic_devc *); + + int mixer_cache[64]; +} +neomagic_devc; + +/* The BIOS signature. */ +#define NM_SIGNATURE 0x4e4d0000 +/* Signature mask. */ +#define NM_SIG_MASK 0xffff0000 + +/* Size of the second memory area. */ +#define NM_PORT2_SIZE 4096 + +/* The base offset of the mixer in the second memory area. */ +#define NM_MIXER_OFFSET 0x600 + +/* The maximum size of a coefficient entry. */ +#define NM_MAX_COEFFICIENT 0x5000 + +/* The interrupt register. */ +#define NM_INT_REG 0xa04 +/* And its bits. */ +#define NM_PLAYBACK_INT 0x40 +#define NM_RECORD_INT 0x100 +#define NM_MISC_INT_1 0x4000 +#define NM_MISC_INT_2 0x1 +#define NM_ACK_INT(CARD, X) neomagic_writePort16((CARD), 2, NM_INT_REG, (X) << 1) + +/* The AV's "mixer ready" status bit and location. */ +#define NM_MIXER_STATUS_OFFSET 0xa06 +#define NM_MIXER_READY_MASK 0x0800 +#define NM_PRESENCE_MASK 0x0050 +#define NM_PRESENCE_VALUE 0x0040 + +/* + * For the ZX. It uses the same interrupt register, but it holds 32 + * bits instead of 16. + */ +#define NMZX_PLAYBACK_INT 0x10000 +#define NMZX_RECORD_INT 0x80000 +#define NMZX_MISC_INT_1 0x8 +#define NMZX_MISC_INT_2 0x2 +#define NMZX_ACK_INT(CARD, X) neomagic_writePort32((CARD), 2, NM_INT_REG, (X)) + +/* The ZX's "mixer ready" status bit and location. */ +#define NMZX_MIXER_STATUS_OFFSET 0xa08 +#define NMZX_MIXER_READY_MASK 0x0800 + +/* The playback registers start from here. */ +#define NM_PLAYBACK_REG_OFFSET 0x0 +/* The record registers start from here. */ +#define NM_RECORD_REG_OFFSET 0x200 + +/* The rate register is located 2 bytes from the start of the register area. */ +#define NM_RATE_REG_OFFSET 2 + +/* Mono/stereo flag, number of bits on playback, and rate mask. */ +#define NM_RATE_STEREO 1 +#define NM_RATE_BITS_16 2 +#define NM_RATE_MASK 0xf0 + +/* Playback enable register. */ +#define NM_PLAYBACK_ENABLE_REG (NM_PLAYBACK_REG_OFFSET + 0x1) +#define NM_PLAYBACK_ENABLE_FLAG 1 +#define NM_PLAYBACK_ONESHOT 2 +#define NM_PLAYBACK_FREERUN 4 + +/* Mutes the audio output. */ +#define NM_AUDIO_MUTE_REG (NM_PLAYBACK_REG_OFFSET + 0x18) +#define NM_AUDIO_MUTE_LEFT 0x8000 +#define NM_AUDIO_MUTE_RIGHT 0x0080 + +/* Recording enable register. */ +#define NM_RECORD_ENABLE_REG (NM_RECORD_REG_OFFSET + 0) +#define NM_RECORD_ENABLE_FLAG 1 +#define NM_RECORD_FREERUN 2 + +#define NM_RBUFFER_START (NM_RECORD_REG_OFFSET + 0x4) +#define NM_RBUFFER_END (NM_RECORD_REG_OFFSET + 0x10) +#define NM_RBUFFER_WMARK (NM_RECORD_REG_OFFSET + 0xc) +#define NM_RBUFFER_CURRP (NM_RECORD_REG_OFFSET + 0x8) + +#define NM_PBUFFER_START (NM_PLAYBACK_REG_OFFSET + 0x4) +#define NM_PBUFFER_END (NM_PLAYBACK_REG_OFFSET + 0x14) +#define NM_PBUFFER_WMARK (NM_PLAYBACK_REG_OFFSET + 0xc) +#define NM_PBUFFER_CURRP (NM_PLAYBACK_REG_OFFSET + 0x8) + +/* A few trivial routines to make it easier to work with the registers + on the chip. */ + +/* This is a common code portion used to fix up the port offsets. */ +#define NM_FIX_PORT \ + if (port < 1 || port > 2 || devc == NULL) \ + return 0; \ +\ + if (offset < devc->portc[port - 1].start_offset \ + || offset >= devc->portc[port - 1].end_offset) { \ + cmn_err(CE_WARN, "Bad access: port %d, offset 0x%x\n", port, offset); \ + return 0; \ + } \ + offset -= devc->portc[port - 1].start_offset; + +#define DEFwritePortX(X, func) \ +static inline int neomagic_writePort##X (neomagic_devc *devc,\ + int port, int offset, int value)\ +{\ + U##X *addr;\ +\ + DDB (cmn_err(CE_CONT, "Writing 0x%x to %d:0x%x\n", value, port, offset));\ +\ + NM_FIX_PORT;\ +\ + addr = (U##X *)(devc->portc[port - 1].ptr + offset);\ + func (value, addr);\ + return 0;\ +} + +static inline void +nm_writeb (unsigned char value, unsigned char *ptr) +{ + *ptr = value; +} + +static inline void +nm_writew (unsigned short value, unsigned short *ptr) +{ + *ptr = value; +} + +static inline void +nm_writel (unsigned int value, unsigned int *ptr) +{ + *ptr = value; +} + + +DEFwritePortX (8, nm_writeb) +DEFwritePortX (16, nm_writew) DEFwritePortX (32, nm_writel) +#define DEFreadPortX(X, func) \ +static inline U##X neomagic_readPort##X (neomagic_devc *devc,\ + int port, int offset)\ +{\ + U##X *addr;\ +\ + NM_FIX_PORT\ +\ + addr = (U##X *)(devc->portc[port - 1].ptr + offset);\ + return func(addr);\ +} + static inline unsigned char + nm_readb (unsigned char *ptr) +{ + return *ptr; +} + +static inline unsigned short +nm_readw (unsigned short *ptr) +{ + return *ptr; +} + +static inline unsigned int +nm_readl (unsigned int *ptr) +{ + return *ptr; +} + +DEFreadPortX (8, nm_readb) +DEFreadPortX (16, nm_readw) +DEFreadPortX (32, nm_readl) + +static inline int +neomagic_writeBuffer8 (neomagic_devc * devc, unsigned char *src, + int port, int offset, int amt) +{ + NM_FIX_PORT; + memcpy (devc->portc[port - 1].ptr + offset, src, amt); + return 0; +} + +#if 0 +static inline int +neomagic_readBuffer8 (neomagic_devc * devc, unsigned char *dst, int port, + int offset, int amt) +{ + NM_FIX_PORT; + memcpy (dst, devc->portc[port - 1].ptr + offset, amt); + return 0; +} +#endif diff --git a/attic/drv/oss_neomagic/neomagic_coeff.h b/attic/drv/oss_neomagic/neomagic_coeff.h new file mode 100644 index 0000000..e7eb972 --- /dev/null +++ b/attic/drv/oss_neomagic/neomagic_coeff.h @@ -0,0 +1,4687 @@ +/* + * Purpose: Coefficient table used by the neomagic driver + */ +#ifndef NEOMAGIC_COEFF_H +#define NEOMAGIC_COEFF_H +/* + * + * This file is part of Open Sound System. + * + * Copyright (C) 4Front Technologies 1996-2008. + * + * This this source file is released under GPL v2 license (no other versions). + * See the COPYING file included in the main directory of this source + * distribution for the license terms and conditions. + * + */ + +#define NM_TOTAL_COEFF_COUNT 0x3158 + +static unsigned char coefficients[NM_TOTAL_COEFF_COUNT * 4] = { + 0xFF, 0xFF, 0x2F, 0x00, 0x4B, 0xFF, 0xA5, 0x01, 0xEF, 0xFC, 0x21, + 0x05, 0x87, 0xF7, 0x62, 0x11, 0xE9, 0x45, 0x5E, 0xF9, 0xB5, 0x01, + 0xDE, 0xFF, 0xA4, 0xFF, 0x60, 0x00, 0xCA, 0xFF, 0x0D, 0x00, 0xFD, + 0xFF, 0x36, 0x00, 0x36, 0xFF, 0xE6, 0x01, 0x3D, 0xFC, 0xD6, 0x06, + 0x4C, 0xF3, 0xED, 0x20, 0x3D, 0x3D, 0x4A, 0xF3, 0x4E, 0x05, 0xB1, + 0xFD, 0xE1, 0x00, 0xC3, 0xFF, 0x05, 0x00, 0x02, 0x00, 0xFD, 0xFF, + 0x2A, 0x00, 0x5C, 0xFF, 0xAA, 0x01, 0x71, 0xFC, 0x07, 0x07, 0x7E, + 0xF1, 0x44, 0x30, 0x44, 0x30, 0x7E, 0xF1, 0x07, 0x07, 0x71, 0xFC, + 0xAA, 0x01, 0x5C, 0xFF, 0x2A, 0x00, 0xFD, 0xFF, 0x02, 0x00, 0x05, + 0x00, 0xC3, 0xFF, 0xE1, 0x00, 0xB1, 0xFD, 0x4E, 0x05, 0x4A, 0xF3, + 0x3D, 0x3D, 0xED, 0x20, 0x4C, 0xF3, 0xD6, 0x06, 0x3D, 0xFC, 0xE6, + 0x01, 0x36, 0xFF, 0x36, 0x00, 0xFD, 0xFF, 0x0D, 0x00, 0xCA, 0xFF, + 0x60, 0x00, 0xA4, 0xFF, 0xDE, 0xFF, 0xB5, 0x01, 0x5E, 0xF9, 0xE9, + 0x45, 0x62, 0x11, 0x87, 0xF7, 0x21, 0x05, 0xEF, 0xFC, 0xA5, 0x01, + 0x4B, 0xFF, 0x2F, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x1E, 0x00, 0x84, + 0xFF, 0x11, 0x01, 0x34, 0xFE, 0x8F, 0x02, 0xC7, 0xFC, 0xAE, 0x03, + 0xF7, 0x48, 0xAE, 0x03, 0xC7, 0xFC, 0x8F, 0x02, 0x34, 0xFE, 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0x63, + 0x01, 0x8D, 0xFF, 0x0F, 0x00 +}; + +static unsigned short CoefficientSizes[] = { + /* Playback */ + 0x00C0, 0x5000, 0x0060, 0x2800, 0x0040, 0x0060, 0x1400, 0x0000, + /* Record */ + 0x0020, 0x1260, 0x0020, 0x1260, 0x0000, 0x0040, 0x1260, 0x0000, +}; + +#ifndef JUST_DATA + +static unsigned short +neomagic_getStartOffset (unsigned char which) +{ + unsigned short offset = 0; + + while (which-- > 0) + offset += CoefficientSizes[which]; + + return offset; +} + +static void +neomagic_loadOneCoefficient (struct neomagic_devc *devc, int devnum, + unsigned int port, unsigned short which) +{ + unsigned int coeffBuf = devc->coeffBuf; + unsigned short offset = neomagic_getStartOffset (which); + unsigned short size = CoefficientSizes[which]; + + /* The record engine's coefficient buffer is offset, so we can + have two simultaneous coefficients (for two different rates). */ + if (which >= 8) + { + coeffBuf += NM_MAX_COEFFICIENT; + } + + DDB (cmn_err + (CE_CONT, + "Loading coefficient buffer 0x%x-0x%x with coefficient %d, size %d, port 0x%x\n", + coeffBuf, coeffBuf + size - 1, which, size, port)); + neomagic_writeBuffer8 (devc, coefficients + offset, 1, coeffBuf, size); + neomagic_writePort32 (devc, 2, port + 0, coeffBuf); + /* ??? Record seems to behave differently than playback. */ + if (devnum == 0) + size--; + neomagic_writePort32 (devc, 2, port + 4, coeffBuf + size); +} + +void +neomagic_loadCoefficient (struct neomagic_devc *devc, int which, int number) +{ + static unsigned short addrs[3] = { 0x1c, 0x21c, 0x408 }; + /* The enable register for the specified engine. */ + unsigned int poffset = (which == 1 ? 0x200 : 1); + + if (neomagic_readPort8 (devc, 2, poffset) & 1) + { + cmn_err (CE_WARN, + "NEOMAGIC: Engine was enabled while loading coefficients!\n"); + return; + } + + /* The recording engine uses coefficient values 8-15. */ + if (which == 1) + number += 8; + + neomagic_loadOneCoefficient (devc, which, addrs[which], number); +} + +#endif /* JUST_DATA */ + +#endif diff --git a/attic/drv/oss_neomagic/oss_neomagic.c b/attic/drv/oss_neomagic/oss_neomagic.c new file mode 100644 index 0000000..3440d38 --- /dev/null +++ b/attic/drv/oss_neomagic/oss_neomagic.c @@ -0,0 +1,1379 @@ +/* + * Purpose: Audio driver for the NeoMagic NM2200 PCI audio controller (AV and ZX). + */ + +/* + * + * This file is part of Open Sound System. + * + * Copyright (C) 4Front Technologies 1996-2008. + * + * This this source file is released under GPL v2 license (no other versions). + * See the COPYING file included in the main directory of this source + * distribution for the license terms and conditions. + * + */ + +#include "oss_neomagic_cfg.h" +#include "oss_pci.h" +#include "ac97.h" +#include "neomagic.h" +#include "neomagic_coeff.h" + +/* + * The size of the playback reserve. When the playback buffer has less + * than NEOMAGIC_PLAY_WMARK_SIZE bytes to output, we request a new + * buffer. + */ +#define NEOMAGIC_PLAY_WMARK_SIZE 0 + +static audiodrv_t neomagic_audio_driver; + +static int neomagic_interrupt_av (struct neomagic_devc *devc); +static int neomagic_interrupt_zx (struct neomagic_devc *devc); + +#define NEOMAGIC_VENDOR_ID 0x10c8 +#define PCI_DEVICE_ID_NEOMAGIC_NEOMAGICAV_AUDIO 0x8005 +#define PCI_DEVICE_ID_NEOMAGIC_NEOMAGICZX_AUDIO 0x8006 +#define PCI_DEVICE_ID_NEOMAGIC_NM2360_AUDIO 0x8016 + + +static int buffertop = 0x18000; + +/* The actual rates supported by the devc. */ +static int samplerates[9] = { + 8000, 11025, 16000, 22050, 24000, 32000, 44100, 48000, 99999999 +}; + +/* + * Set the devc samplerate, word size and stereo mode to correspond to + * the settings in the CARD struct for the specified device in DEV. + * We keep two separate sets of information, one for each device; the + * hardware is not actually configured until a read or write is + * attempted. + */ + +int +neomagic_setInfo (int dev, struct neomagic_devc *devc) +{ + int x; + int w; + int targetrate; + + if (devc->dev[0] == dev) + w = 0; + else if (devc->dev[1] == dev) + w = 1; + else + return OSS_ENODEV; + + targetrate = devc->portc[w].samplerate; + + if ((devc->portc[w].bits != 8 && devc->portc[w].bits != 16) + || targetrate < samplerates[0] || targetrate > samplerates[7]) + return OSS_EINVAL; + + for (x = 0; x < 8; x++) + if (targetrate < ((samplerates[x] + samplerates[x + 1]) / 2)) + break; + + if (x < 8) + { + unsigned char ratebits = ((x << 4) & NM_RATE_MASK); + if (devc->portc[w].bits == 16) + ratebits |= NM_RATE_BITS_16; + if (devc->portc[w].stereo == 2) + ratebits |= NM_RATE_STEREO; + + devc->portc[w].samplerate = samplerates[x]; + + + if (devc->dev_for_play == dev && devc->playing) + { + DDB (cmn_err (CE_WARN, "Setting play ratebits to 0x%x\n", + ratebits)); + neomagic_loadCoefficient (devc, 0, x); + neomagic_writePort8 (devc, 2, + NM_PLAYBACK_REG_OFFSET + NM_RATE_REG_OFFSET, + ratebits); + } + + if (devc->dev_for_record == dev && devc->recording) + { + DDB (cmn_err (CE_WARN, "Setting record ratebits to 0x%x\n", + ratebits)); + neomagic_loadCoefficient (devc, 1, x); + neomagic_writePort8 (devc, 2, + NM_RECORD_REG_OFFSET + NM_RATE_REG_OFFSET, + ratebits); + } + return 0; + } + else + return OSS_EINVAL; +} + +/* Start the play process going. */ +static void +startPlay (struct neomagic_devc *devc) +{ + if (!devc->playing) + { + devc->playing = 1; + neomagic_setInfo (devc->dev_for_play, devc); + + /* Enable playback engine and interrupts. */ + neomagic_writePort8 (devc, 2, NM_PLAYBACK_ENABLE_REG, + NM_PLAYBACK_ENABLE_FLAG | NM_PLAYBACK_FREERUN); + + /* Enable both channels. */ + neomagic_writePort16 (devc, 2, NM_AUDIO_MUTE_REG, 0x0); + } +} + +/* + * Request one chunk of AMT bytes from the recording device. When the + * operation is complete, the data will be copied into BUFFER and the + * function oss_audio_inputintr will be invoked. + */ + +static void +neomagic_read_block (struct neomagic_devc *devc, oss_native_word physbuf, + unsigned int amt) +{ + unsigned int endpos; + unsigned int ringsize = devc->recordBufferSize; + unsigned int startOffset = + physbuf - (devc->portc[0].physaddr + devc->abuf2); + unsigned char samplesize = 1; + int dev = devc->dev_for_record; + int which; + + if (devc->dev[0] == dev) + which = 0; + else + which = 1; + + if (devc->portc[which].bits == 16) + samplesize *= 2; + if (devc->portc[which].stereo == 2) + samplesize *= 2; + + /* + * If we happen to go past the end of the buffer a bit (due to a + * delayed interrupt) it's OK. So might as well set the watermark + * right at the end of the reqested data. + */ + endpos = (startOffset + amt - samplesize) % ringsize; + neomagic_writePort32 (devc, 2, NM_RBUFFER_WMARK, devc->abuf2 + endpos); +} + +static void +startRecord (struct neomagic_devc *devc) +{ + if (!devc->recording) + { + devc->recording = 1; + neomagic_setInfo (devc->dev_for_record, devc); + /* Enable recording engine and interrupts. */ + neomagic_writePort8 (devc, 2, NM_RECORD_ENABLE_REG, + NM_RECORD_ENABLE_FLAG | NM_RECORD_FREERUN); + } +} + + +/* Stop the play engine. */ +static void +stopPlay (struct neomagic_devc *devc) +{ + /* Shut off sound from both channels. */ + neomagic_writePort16 (devc, 2, NM_AUDIO_MUTE_REG, + NM_AUDIO_MUTE_LEFT | NM_AUDIO_MUTE_RIGHT); + /* Disable play engine. */ + neomagic_writePort8 (devc, 2, NM_PLAYBACK_ENABLE_REG, 0); + if (devc->playing) + { + /* Reset the relevant state bits. */ + devc->playing = 0; + } +} + +/* Stop recording. */ +static void +stopRecord (struct neomagic_devc *devc) +{ + /* Disable recording engine. */ + neomagic_writePort8 (devc, 2, NM_RECORD_ENABLE_REG, 0); + + if (devc->recording) + { + devc->recording = 0; + } +} + +/* + * Ring buffers, man. That's where the hip-hop, wild-n-wooly action's at. + * 1972? (Well, I suppose it was cheep-n-easy to implement.) + * + * Write AMT bytes of BUFFER to the playback ring buffer. + + * Actually, the write has been done for us, so all we have to do is + * note that the stop point has changed. + */ + +static void +neomagic_write_block (struct neomagic_devc *devc, oss_native_word physbuf, + unsigned int amt) +{ + unsigned int ringsize = devc->playbackBufferSize; + unsigned int physBufAddr = (devc->portc[0].physaddr + devc->abuf1); + int sampsize = 1; + unsigned int playstop; + int dev = devc->dev_for_play; + int which; + + if (devc->dev[0] == dev) + which = 0; + else + which = 1; + + if (devc->portc[which].bits == 16) + sampsize *= 2; + if (devc->portc[which].stereo == 2) + sampsize *= 2; + + playstop = (physbuf + amt - physBufAddr - sampsize) % ringsize; + neomagic_writePort32 (devc, 2, NM_PBUFFER_WMARK, devc->abuf1 + playstop); +} + + + +/* + * Initialize the hardware. + */ +static void +neomagic_initHw (struct neomagic_devc *devc) +{ + /* Reset everything. */ + neomagic_writePort8 (devc, 2, 0x0, 0x11); + neomagic_writePort16 (devc, 2, 0x214, 0); + + stopRecord (devc); + stopPlay (devc); +} + + +static int +neomagic_interrupt (oss_device_t * osdev) +{ + struct neomagic_devc *devc = (neomagic_devc *) osdev->devc; + + return devc->introutine (devc); +} + +static int +neomagic_interrupt_av (struct neomagic_devc *devc) +{ + unsigned short status; + int serviced = 0; + + status = neomagic_readPort16 (devc, 2, NM_INT_REG); + + if (status & NM_PLAYBACK_INT) + { + serviced = 1; + status &= ~NM_PLAYBACK_INT; + NM_ACK_INT (devc, NM_PLAYBACK_INT); + + if (devc->playing) + oss_audio_outputintr (devc->dev_for_play, 1); + } + + if (status & NM_RECORD_INT) + { + serviced = 1; + status &= ~NM_RECORD_INT; + NM_ACK_INT (devc, NM_RECORD_INT); + + if (devc->recording) + oss_audio_inputintr (devc->dev_for_record, 0); + } + + if (status & NM_MISC_INT_1) + { + unsigned char cbyte; + + serviced = 1; + status &= ~NM_MISC_INT_1; + cmn_err (CE_WARN, "Got misc interrupt #1\n"); + NM_ACK_INT (devc, NM_MISC_INT_1); + neomagic_writePort16 (devc, 2, NM_INT_REG, 0x8000); + cbyte = neomagic_readPort8 (devc, 2, 0x400); + neomagic_writePort8 (devc, 2, 0x400, cbyte | 2); + } + + if (status & NM_MISC_INT_2) + { + unsigned char cbyte; + + serviced = 1; + status &= ~NM_MISC_INT_2; + cmn_err (CE_WARN, "Got misc interrupt #2\n"); + NM_ACK_INT (devc, NM_MISC_INT_2); + cbyte = neomagic_readPort8 (devc, 2, 0x400); + neomagic_writePort8 (devc, 2, 0x400, cbyte & ~2); + } + + /* Unknown interrupt. */ + if (status) + { + NM_ACK_INT (devc, status); + } + return serviced; +} + +/* + * Handle a potential interrupt for the device referred to by DEV_ID. + * This handler is for the 256ZX, and is very similar to the non-ZX + * routine. + */ + +static int +neomagic_interrupt_zx (struct neomagic_devc *devc) +{ + unsigned int status; + int serviced = 0; + + status = neomagic_readPort32 (devc, 2, NM_INT_REG); + + if (status & NMZX_PLAYBACK_INT) + { + serviced = 1; + status &= ~NMZX_PLAYBACK_INT; + NMZX_ACK_INT (devc, NMZX_PLAYBACK_INT); + + if (devc->playing) + oss_audio_outputintr (devc->dev_for_play, 1); + } + + if (status & NMZX_RECORD_INT) + { + serviced = 1; + status &= ~NMZX_RECORD_INT; + NMZX_ACK_INT (devc, NMZX_RECORD_INT); + + if (devc->recording) + oss_audio_inputintr (devc->dev_for_record, 0); + } + + if (status & NMZX_MISC_INT_1) + { + unsigned char cbyte; + + serviced = 1; + status &= ~NMZX_MISC_INT_1; + cmn_err (CE_WARN, "Got misc interrupt #1\n"); + NMZX_ACK_INT (devc, NMZX_MISC_INT_1); + cbyte = neomagic_readPort8 (devc, 2, 0x400); + neomagic_writePort8 (devc, 2, 0x400, cbyte | 2); + } + + if (status & NMZX_MISC_INT_2) + { + unsigned char cbyte; + + serviced = 1; + status &= ~NMZX_MISC_INT_2; + cmn_err (CE_WARN, "Got misc interrupt #2\n"); + NMZX_ACK_INT (devc, NMZX_MISC_INT_2); + cbyte = neomagic_readPort8 (devc, 2, 0x400); + neomagic_writePort8 (devc, 2, 0x400, cbyte & ~2); + } + + /* Unknown interrupt. */ + if (status) + { + NMZX_ACK_INT (devc, status); + } + return serviced; +} + + +/* + * Waits for the mixer to become ready to be written; returns a zero value + * if it timed out. + */ + +static int +neomagic_isReady (struct neomagic_devc *devc) +{ + int t2 = 10; + unsigned int testaddr; + unsigned short testb; + int done = 0; + + testaddr = devc->mixer_status_offset; + testb = devc->mixer_status_mask; + + /* + * Loop around waiting for the mixer to become ready. + */ + while (!done && t2-- > 0) + { + if ((neomagic_readPort16 (devc, 2, testaddr) & testb) == 0) + done = 1; + else + oss_udelay (10); + } + return done; +} + +/* + * Return the contents of the AC97 mixer register REG. Returns a positive + * value if successful, or a negative error code. + */ +static int +neomagic_readAC97Reg (void *devc_, int reg) +{ + struct neomagic_devc *devc = (struct neomagic_devc *) devc_; + oss_native_word flags; + int res; + + /* for some reason any access to register 28 hangs the devc */ + if (reg == 0x28) + return 0; + MUTEX_ENTER_IRQDISABLE (devc->low_mutex, flags); + if (reg < 128) + { + if (reg < 64 && devc->mixer_cache[reg] >= 0) + { + MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags); + return devc->mixer_cache[reg / 2]; + } + else + { + neomagic_isReady (devc); + res = neomagic_readPort16 (devc, 2, NM_MIXER_OFFSET + reg); + /* Magic delay. Bleah yucky. */ + oss_udelay (1000); + MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags); + return res; + } + } + else + { + MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags); + return OSS_EINVAL; + } +} + +/* + * Writes VALUE to AC97 mixer register REG. Returns 0 if successful, or + * a negative error code. + */ +static int +neomagic_writeAC97Reg (void *devc_, int reg, int value) +{ + oss_native_word flags; + int tries = 2; + int done = 0; + + struct neomagic_devc *devc = (struct neomagic_devc *) devc_; + + /* for some reason any access to register 0x28 hangs the device */ + if (reg == 0x28) + return 0; + + MUTEX_ENTER_IRQDISABLE (devc->low_mutex, flags); + + neomagic_isReady (devc); + + /* Wait for the write to take, too. */ + while ((tries-- > 0) && !done) + { + neomagic_writePort16 (devc, 2, NM_MIXER_OFFSET + reg, value); + if (neomagic_isReady (devc)) + { + done = 1; + break; + } + } + + oss_udelay (1000); + devc->mixer_cache[reg / 2] = value; + MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags); + + return !done; +} + +/* + * Initial register values to be written to the AC97 mixer. + * While most of these are identical to the reset values, we do this + * so that we have most of the register contents cached--this avoids + * reading from the mixer directly (which seems to be problematic, + * probably due to ignorance). + */ +struct initialValues +{ + unsigned short port; + unsigned short value; +}; + +/* Initialize the AC97 into a known state. */ +static int +neomagic_resetAC97 (struct neomagic_devc *devc) +{ + int x; + + for (x = 0; x < 64; x++) + { + devc->mixer_cache[x] = -1; + } + + /* Enable the internal AC97 controller. */ + neomagic_writePort8 (devc, 2, 0x6c0, 1); + /* Now cycle it through test modes (presumably to reset it). */ +#if 0 + neomagic_writePort8 (devc, 2, 0x6cc, 0x87); + neomagic_writePort8 (devc, 2, 0x6cc, 0x80); +#endif + neomagic_writePort8 (devc, 2, 0x6cc, 0x0); + return 0; +} + + +/* + * See if the signature left by the NEOMAGIC BIOS is intact; if so, we use + * the associated address as the end of our audio buffer in the video + * RAM. + */ + +static void +neomagic_peek_for_sig (struct neomagic_devc *devc) +{ + unsigned int port1offset + = devc->portc[0].physaddr + devc->portc[0].end_offset - 0x0400; + + /* The signature is located 1K below the end of video RAM. */ + char *temp = (char *) MAP_PCI_MEM (devc->osdev, 0, port1offset, 1024); + unsigned int *ptemp = (unsigned int *) temp; + + /* Default buffer end is 5120 bytes below the top of RAM. */ + unsigned int default_value = devc->portc[0].end_offset - 0x1400; + + unsigned int sig; + + /* Install the default value first, so we don't have to repeatedly + do it if there is a problem. */ + devc->portc[0].end_offset = default_value; + + if (temp == NULL) + { + cmn_err (CE_WARN, "Unable to scan for devc signature in video RAM\n"); + return; + } + + sig = PCI_READL (devc->osdev, ptemp); + + if ((sig & NM_SIG_MASK) == NM_SIGNATURE) + { + unsigned int pointer = PCI_READL (devc->osdev, ptemp + 4); + + /* + * If it's obviously invalid, don't use it (the port already has a + * suitable default value set). + */ + if (pointer != 0xffffffff) + devc->portc[0].end_offset = pointer; + + cmn_err (CE_WARN, "Found devc signature in video RAM: 0x%x\n", pointer); + } + + UNMAP_PCI_MEM (devc->osdev, 0, port1offset, temp, 1024); +} + +/* + * Install a driver for the Neomagic 2200 device referenced by PORT1ADDR, + */ + +static int +neomagic_install (neomagic_devc * devc, unsigned int port1addr, + unsigned int port2addr) +{ + int x, adev, err; + oss_native_word physaddr; + int size; + + devc->playing = 0; + devc->recording = 0; + + /* Init the memory port info. */ + for (x = 0; x < 2; x++) + { + devc->portc[x].ptr = NULL; + devc->portc[x].start_offset = 0; + devc->portc[x].end_offset = 0; + } + devc->portc[0].physaddr = port1addr; + + /* Port 2 is easy. */ + devc->portc[1].physaddr = port2addr; + devc->portc[1].start_offset = 0; + devc->portc[1].end_offset = NM_PORT2_SIZE; + + /* But we have to map in port 2 so we can check how much RAM the + card has. */ + + physaddr = devc->portc[1].physaddr + devc->portc[1].start_offset; + size = devc->portc[1].end_offset - devc->portc[1].start_offset; + if (size == 0) + cmn_err (CE_NOTE, "Bad I/O region size\n"); + devc->portc[1].ptr = (char *) MAP_PCI_MEM (devc->osdev, 1, physaddr, size); + + if (devc->portc[1].ptr == NULL) + { + cmn_err (CE_WARN, "Unable to remap port 1\n"); + return 0; + } + + /* + * The NEOMAGIC has two memory ports. The first port is nothing + * more than a chunk of video RAM, which is used as the I/O ring + * buffer. The second port has the actual juicy stuff (like the + * mixer and the playback engine control registers). + */ + + if (devc->rev == REV_NEOMAGICAV) + { + /* Ok, try to see if this is a non-AC97 version of the hardware. */ + /* unsigned char oldval = neomagic_readPort8 (devc, 2, 0x6c0); */ + + /* First enable the AC97 controller. */ + neomagic_writePort8 (devc, 2, 0x6c0, 1); + devc->portc[0].end_offset = 2560 * 1024; + devc->introutine = neomagic_interrupt_av; + devc->mixer_status_offset = NM_MIXER_STATUS_OFFSET; + devc->mixer_status_mask = NM_MIXER_READY_MASK; + } + else + { + /* Not sure if there is any relevant detect for the ZX or not. */ + if (neomagic_readPort8 (devc, 2, 0xa0b) != 0) + devc->portc[0].end_offset = 6144 * 1024; + else + devc->portc[0].end_offset = 4096 * 1024; + + devc->introutine = neomagic_interrupt_zx; + devc->mixer_status_offset = NMZX_MIXER_STATUS_OFFSET; + devc->mixer_status_mask = NMZX_MIXER_READY_MASK; + } + +#if 1 + if (buffertop >= 0x18000 && buffertop < devc->portc[0].end_offset) + devc->portc[0].end_offset = buffertop; + else + neomagic_peek_for_sig (devc); +#endif + + devc->portc[0].start_offset = devc->portc[0].end_offset - 0x18000; + + /* Map in this buffer so the driver can use it as DMA memory */ + physaddr = devc->portc[0].physaddr + devc->portc[0].start_offset; + size = devc->portc[0].end_offset - devc->portc[0].start_offset; + devc->portc[0].ptr = (char *) MAP_PCI_MEM (devc->osdev, 0, physaddr, size); + + if (devc->portc[0].ptr == NULL) + { + cmn_err (CE_WARN, "Unable to remap port 0\n"); + return 0; + } + + /* + * Init the board. + */ + + devc->playbackBufferSize = 16384; + devc->recordBufferSize = 16384; + + devc->coeffBuf = devc->portc[0].end_offset - NM_MAX_COEFFICIENT * 2; + /* set record buffer start address */ + devc->abuf2 = (devc->coeffBuf - devc->recordBufferSize); + /* set playback buffer start address */ + devc->abuf1 = (devc->abuf2 - devc->playbackBufferSize); + + devc->abuf2virt = devc->portc[0].ptr + + devc->abuf2 - devc->portc[0].start_offset; + + devc->abuf1virt = devc->portc[0].ptr + + devc->abuf1 - devc->portc[0].start_offset; + + devc->is_open_play = 0; + devc->is_open_record = 0; + devc->opencnt[0] = 0; + devc->opencnt[1] = 0; + + MUTEX_INIT (devc->osdev, devc->mutex, MH_DRV); + MUTEX_INIT (devc->osdev, devc->low_mutex, MH_DRV + 1); + + neomagic_initHw (devc); + neomagic_resetAC97 (devc); + + /* + * Install the AC97 mixer + */ + + devc->mixer_dev = ac97_install (&devc->ac97devc, "Neomagic AC97 Mixer", + neomagic_readAC97Reg, + neomagic_writeAC97Reg, devc, devc->osdev); + if (devc->mixer_dev < 0) + { + cmn_err (CE_WARN, "Failed to install AC97 mixer device\n"); + return 0; + } + + for (x = 0; x < 2; x++) + { + if ((adev = + oss_install_audiodev (OSS_AUDIO_DRIVER_VERSION, + devc->osdev, + devc->osdev, + devc->chip_name, + &neomagic_audio_driver, + sizeof (audiodrv_t), + 0, AFMT_U8 | AFMT_S16_LE, devc, -1)) < 0) + { + adev = -1; + return 0; + } + + else + { + audio_engines[adev]->mixer_dev = devc->mixer_dev; + audio_engines[adev]->min_rate = 6023; + audio_engines[adev]->max_rate = 48000; + audio_engines[adev]->caps |= PCM_CAP_FREERATE; + devc->dev[x] = adev; + devc->portc[x].bits = 8; + devc->portc[x].stereo = 1; + devc->portc[x].samplerate = 8000; + } + } + + if ((err = + oss_register_interrupts (devc->osdev, 0, neomagic_interrupt, + NULL)) < 0) + { + cmn_err (CE_WARN, "Can't register interrupt handler, err=%d\n", err); + return 0; + } + + return 1; +} + +/* + * Open the device + * + * DEV - device + * MODE - mode to open device (logical OR of OPEN_READ and OPEN_WRITE) + * + * Called when opening the DMAbuf (dmabuf.c:259) + */ +/*ARGSUSED*/ +static int +neomagic_audio_open (int dev, int mode, int open_flags) +{ + struct neomagic_devc *devc = audio_engines[dev]->devc; + int w; + + if (devc == NULL) + return OSS_ENODEV; + + if (devc->dev[0] == dev) + w = 0; + else if (devc->dev[1] == dev) + w = 1; + else + return OSS_ENODEV; + + if (devc->opencnt[w] > 0) + return OSS_EBUSY; + + /* No bits set? Huh? */ + if (!((mode & OPEN_READ) || (mode & OPEN_WRITE))) + return OSS_EIO; + + /* + * If it's open for both read and write, and the devc's currently + * being read or written to, then do the opposite of what has + * already been done. Otherwise, don't specify any mode until the + * user actually tries to do I/O. (Some programs open the device + * for both read and write, but only actually do reading or writing.) + */ + + if ((mode & OPEN_WRITE) && (mode & OPEN_READ)) + { + if (devc->is_open_play) + mode = OPEN_WRITE; + else if (devc->is_open_record) + mode = OPEN_READ; + else + mode = 0; + } + + if (mode & OPEN_WRITE) + { + if (devc->is_open_play == 0) + { + devc->dev_for_play = dev; + devc->is_open_play = 1; + audio_engines[dev]->fixed_rate = 0; + audio_engines[dev]->min_rate = 5000; + audio_engines[dev]->max_rate = 48000; + audio_engines[dev]->flags &= + ~(ADEV_FIXEDRATE | ADEV_16BITONLY | ADEV_STEREOONLY); + } + else + return OSS_EBUSY; + } + + if (mode & OPEN_READ) + { + if (devc->is_open_record == 0) + { + devc->dev_for_record = dev; + devc->is_open_record = 1; + audio_engines[dev]->fixed_rate = 48000; + audio_engines[dev]->min_rate = 48000; + audio_engines[dev]->max_rate = 48000; + audio_engines[dev]->flags |= + ADEV_FIXEDRATE | ADEV_16BITONLY | ADEV_STEREOONLY; + } + else + return OSS_EBUSY; + } + + devc->opencnt[w]++; + return 0; +} + +/* + * Close the device + * + * DEV - device + * + * Called when closing the DMAbuf (dmabuf.c:477) + * after halt_xfer + */ +/*ARGSUSED*/ +static void +neomagic_audio_close (int dev, int mode) +{ + struct neomagic_devc *devc = audio_engines[dev]->devc; + + if (devc != NULL) + { + int w; + + if (devc->dev[0] == dev) + w = 0; + else if (devc->dev[1] == dev) + w = 1; + else + return; + + devc->opencnt[w]--; + if (devc->opencnt[w] <= 0) + { + devc->opencnt[w] = 0; + + if (devc->dev_for_play == dev) + { + stopPlay (devc); + devc->is_open_play = 0; + devc->dev_for_play = -1; + } + + if (devc->dev_for_record == dev) + { + stopRecord (devc); + devc->is_open_record = 0; + devc->dev_for_record = -1; + } + } + } +} + +static int +neomagic_set_rate (int dev, int arg) +{ + struct neomagic_devc *devc = audio_engines[dev]->devc; + int which; + + if (devc == NULL) + return OSS_ENODEV; + + if (devc->dev[0] == dev) + which = 0; + else + which = 1; + + if (audio_engines[dev]->flags & ADEV_FIXEDRATE) + { + arg = 48000; + } + + + if (arg == 0) + return devc->portc[which].samplerate; + + if (arg > 48000) + arg = 48000; + if (arg < 5000) + arg = 5000; + + devc->portc[which].samplerate = arg; + return devc->portc[which].samplerate; +} + +static short +neomagic_set_channels (int dev, short arg) +{ + struct neomagic_devc *devc = audio_engines[dev]->devc; + int which; + + if (devc == NULL) + return OSS_ENODEV; + + if (devc->dev[0] == dev) + which = 0; + else + which = 1; + + if (audio_engines[dev]->flags & ADEV_STEREOONLY) + { + arg = 2; + } + if ((arg != 1) && (arg != 2)) + return devc->portc[which].stereo; + devc->portc[which].stereo = arg; + return devc->portc[which].stereo; +} + +static unsigned int +neomagic_set_format (int dev, unsigned int arg) +{ + struct neomagic_devc *devc = audio_engines[dev]->devc; + int which; + + if (devc->dev[0] == dev) + which = 0; + else + which = 1; + + if (audio_engines[dev]->flags & ADEV_16BITONLY) + { + arg = 16; + } + + if (!(arg & (AFMT_U8 | AFMT_S16_LE))) + return devc->portc[which].bits; + devc->portc[which].bits = arg; + return devc->portc[which].bits; +} + +/*ARGSUSED*/ +static int +neomagic_audio_ioctl (int dev, unsigned int cmd, ioctl_arg arg) +{ + return OSS_EINVAL; +} + +/* + * Output a block to sound device + * + * dev - device number + * buf - physical address of buffer + * count - byte count in buffer + * intrflag - set if this has been called from an interrupt + * (via oss_audio_outputintr) + * restart_dma - set if engine needs to be re-initialised + * + * Called when: + * 1. Starting output (dmabuf.c:1327) + * 2. (dmabuf.c:1504) + * 3. A new buffer needs to be sent to the device (dmabuf.c:1579) + */ +/*ARGSUSED*/ +static void +neomagic_audio_output_block (int dev, oss_native_word physbuf, + int count, int fragsize, int intrflag) +{ + struct neomagic_devc *devc = audio_engines[dev]->devc; + + if (devc != NULL) + { + devc->is_open_play = 1; + devc->dev_for_play = dev; + neomagic_write_block (devc, physbuf, count); + } +} + +/* Ditto, but do recording instead. */ +/*ARGSUSED*/ +static void +neomagic_audio_start_input (int dev, oss_native_word physbuf, int count, + int fragsize, int intrflag) +{ + struct neomagic_devc *devc = audio_engines[dev]->devc; + + if (devc != NULL) + { + devc->is_open_record = 1; + devc->dev_for_record = dev; + neomagic_read_block (devc, physbuf, count); + } +} + +/* + * Prepare for inputting samples to DEV. + * Each requested buffer will be BSIZE byes long, with a total of + * BCOUNT buffers. + */ + +static int +neomagic_audio_prepare_for_input (int dev, int bsize, int bcount) +{ + struct neomagic_devc *devc = audio_engines[dev]->devc; + oss_native_word flags; + + if (devc == NULL) + return OSS_ENODEV; + + if (devc->is_open_record && devc->dev_for_record != dev) + return OSS_EBUSY; + + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); + /* + * If we're not currently recording, set up the start and end registers + * for the recording engine. + */ + if (!devc->recording) + { + neomagic_writePort32 (devc, 2, NM_RBUFFER_START, devc->abuf2); + neomagic_writePort32 (devc, 2, NM_RBUFFER_END, + devc->abuf2 + bsize * bcount); + + neomagic_writePort32 (devc, 2, NM_RBUFFER_CURRP, devc->abuf2); + } + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + return 0; +} + +/* + * Prepare for outputting samples to `dev' + * + * Each buffer that will be passed will be `bsize' bytes long, + * with a total of `bcount' buffers. + * + * Called when: + * 1. A trigger enables audio output (dmabuf.c:978) + * 2. We get a write buffer without dma_mode setup (dmabuf.c:1152) + * 3. We restart a transfer (dmabuf.c:1324) + */ + +static int +neomagic_audio_prepare_for_output (int dev, int bsize, int bcount) +{ + struct neomagic_devc *devc = audio_engines[dev]->devc; + oss_native_word flags; + + if (devc == NULL) + return OSS_ENODEV; + + if (devc->is_open_play && devc->dev_for_play != dev) + return OSS_EBUSY; + + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); + /* + * Setup the buffer start and end registers. + */ + if (!devc->playing) + { + /* The PBUFFER_END register in this case points to one sample + before the end of the buffer. */ + int w = (devc->dev_for_play == devc->dev[0] ? 0 : 1); + int sampsize = (devc->portc[w].bits == 16 ? 2 : 1); + + if (devc->portc[w].stereo == 2) + sampsize *= 2; + + /* Need to set the not-normally-changing-registers up. */ + neomagic_writePort32 (devc, 2, NM_PBUFFER_START, devc->abuf1); + neomagic_writePort32 (devc, 2, NM_PBUFFER_END, + devc->abuf1 + bsize * bcount - sampsize); + neomagic_writePort32 (devc, 2, NM_PBUFFER_CURRP, devc->abuf1); + } + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + + return 0; +} + +/* Stop the current operations associated with DEV. */ +static void +neomagic_audio_reset (int dev) +{ + struct neomagic_devc *devc = audio_engines[dev]->devc; + + if (devc != NULL) + { + if (devc->dev_for_play == dev) + stopPlay (devc); + if (devc->dev_for_record == dev) + stopRecord (devc); + } +} + + +static int +neomagic_alloc_buffer (int dev, dmap_t * dmap, int direction) +{ + struct neomagic_devc *devc = audio_engines[dev]->devc; + + if (direction & PCM_ENABLE_OUTPUT) + { + dmap->dmabuf = (void *) devc->abuf1virt; + dmap->dmabuf_phys = devc->portc[0].physaddr + devc->abuf1; + dmap->buffsize = devc->playbackBufferSize; + } + else if (direction & PCM_ENABLE_INPUT) + { + dmap->dmabuf = (void *) devc->abuf2virt; + dmap->dmabuf_phys = devc->portc[0].physaddr + devc->abuf2; + dmap->buffsize = devc->recordBufferSize; + } + + return 0; +} + +/*ARGSUSED*/ +static int +neomagic_free_buffer (int dev, dmap_t * dmap, int direction) +{ + if (dmap->dmabuf == NULL) + return 0; + dmap->dmabuf = NULL; + return 0; +} + +static void +neomagic_trigger (int dev, int state) +{ + struct neomagic_devc *devc = audio_engines[dev]->devc; + oss_native_word flags; + + if (devc != NULL) + { + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); + if (devc->dev_for_play == dev) + { + if (state & PCM_ENABLE_OUTPUT) + { + startPlay (devc); + } + else + { + stopPlay (devc); + } + } + if (devc->dev_for_record == dev) + { + if (state & PCM_ENABLE_INPUT) + { + startRecord (devc); + } + else + { + stopRecord (devc); + } + } + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + } +} + +#if 0 +static int +neomagic_get_buffer_pointer (int dev, dmap_t * dmap, int direction) +{ + struct neomagic_devc *devc = audio_engines[dev]->devc; + unsigned int amt = 0; + oss_native_word flags; + + if (devc == NULL) + return OSS_ENODEV; + + MUTEX_ENTER_IRQDISABLE (devc->low_mutex, flags); + if (direction == PCM_ENABLE_OUTPUT) + { + if (devc->dev_for_play == dev && devc->playing) + { + amt = neomagic_readPort32 (devc, 2, NM_PBUFFER_CURRP) - devc->abuf1; + } + } + + if (direction == PCM_ENABLE_INPUT) + { + if (devc->dev_for_record == dev && devc->recording) + { + amt = neomagic_readPort32 (devc, 2, NM_RBUFFER_CURRP) - devc->abuf2; + } + } + + MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags); + return amt; +} +#endif + + +static audiodrv_t neomagic_audio_driver = { + neomagic_audio_open, /* open */ + neomagic_audio_close, /* close */ + neomagic_audio_output_block, /* output_block */ + neomagic_audio_start_input, /* start_input */ + neomagic_audio_ioctl, /* ioctl */ + neomagic_audio_prepare_for_input, /* prepare_for_input */ + neomagic_audio_prepare_for_output, /* prepare_for_output */ + neomagic_audio_reset, /* reset */ + NULL, /*+local_qlen */ + NULL, /*+copy_from_user */ + NULL, /*+halt_input */ + NULL, /* halt_output */ + neomagic_trigger, /*+trigger */ + neomagic_set_rate, /*+set_rate */ + neomagic_set_format, /*+set_format */ + neomagic_set_channels, /*+set_channels */ + NULL, + NULL, + NULL, + NULL, + neomagic_alloc_buffer, + neomagic_free_buffer, + NULL, + NULL, + NULL /*neomagic_get_buffer_pointer */ +}; + +int +oss_neomagic_attach (oss_device_t * osdev) +{ + unsigned char pci_irq_line, pci_revision; + unsigned short pci_command, vendor, device; + unsigned int port1addr, port2addr; + neomagic_devc *devc; + + DDB (cmn_err (CE_WARN, "Entered NM2200 probe routine\n")); + + pci_read_config_word (osdev, PCI_VENDOR_ID, &vendor); + pci_read_config_word (osdev, PCI_DEVICE_ID, &device); + + if ((vendor != NEOMAGIC_VENDOR_ID) || + (device != PCI_DEVICE_ID_NEOMAGIC_NEOMAGICAV_AUDIO && + device != PCI_DEVICE_ID_NEOMAGIC_NEOMAGICZX_AUDIO && + device != PCI_DEVICE_ID_NEOMAGIC_NM2360_AUDIO)) + + return 0; + + pci_read_config_word (osdev, PCI_COMMAND, &pci_command); + pci_read_config_byte (osdev, PCI_REVISION_ID, &pci_revision); + pci_read_config_irq (osdev, PCI_INTERRUPT_LINE, &pci_irq_line); + pci_read_config_dword (osdev, PCI_MEM_BASE_ADDRESS_0, &port1addr); + pci_read_config_dword (osdev, PCI_MEM_BASE_ADDRESS_1, &port2addr); + + if ((port1addr == 0) || (port2addr == 0)) + { + cmn_err (CE_WARN, "undefined MEMORY I/O address.\n"); + return 0; + } + + if (pci_irq_line == 0) + { + cmn_err (CE_WARN, "IRQ not assigned by BIOS.\n"); + return 0; + } + + + if ((devc = PMALLOC (osdev, sizeof (*devc))) == NULL) + { + cmn_err (CE_WARN, "Out of memory\n"); + return 0; + } + + devc->osdev = osdev; + osdev->devc = devc; + devc->irq = pci_irq_line; + + + switch (device) + { + case PCI_DEVICE_ID_NEOMAGIC_NEOMAGICAV_AUDIO: + devc->rev = REV_NEOMAGICAV; + devc->chip_name = "Neomagic NM2200AV"; + break; + case PCI_DEVICE_ID_NEOMAGIC_NEOMAGICZX_AUDIO: + devc->rev = REV_NEOMAGICZX; + devc->chip_name = "Neomagic NM2200ZX"; + break; + case PCI_DEVICE_ID_NEOMAGIC_NM2360_AUDIO: + devc->rev = REV_NEOMAGICZX; + devc->chip_name = "Neomagic NM22360"; + break; + default: + return 0; + break; + } + + + pci_command |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config_word (osdev, PCI_COMMAND, pci_command); + + port1addr &= ~0x0F; + port2addr &= ~0x0F; + + oss_register_device (osdev, devc->chip_name); + + return neomagic_install (devc, port1addr, port2addr); +} + + +int +oss_neomagic_detach (oss_device_t * osdev) +{ + struct neomagic_devc *devc = (neomagic_devc *) osdev->devc; + int i; + + if (oss_disable_device (osdev) < 0) + return 0; + +#if 0 + stopPlay (devc); + stopRecord (devc); +#endif + + neomagic_initHw (devc); + oss_unregister_interrupts (devc->osdev); + + MUTEX_CLEANUP (devc->mutex); + MUTEX_CLEANUP (devc->low_mutex); + + for (i = 0; i < MAX_PORTC; i++) + { + UNMAP_PCI_MEM (devc->osdev, 0, + devc->portc[i].physaddr + devc->portc[i].start_offset, + devc->portc[i].ptr, + devc->portc[i].end_offset - devc->portc[i].start_offset); + + devc->portc[i].ptr = NULL; + } + + oss_unregister_device (devc->osdev); + return 1; +} diff --git a/attic/drv/oss_neomagic/oss_neomagic.man b/attic/drv/oss_neomagic/oss_neomagic.man new file mode 100644 index 0000000..3e4f0d0 --- /dev/null +++ b/attic/drv/oss_neomagic/oss_neomagic.man @@ -0,0 +1,19 @@ +NAME +oss_neomagic - Neomagic audio driver. + +DESCRIPTION +Open Sound System driver for Neomagic NM2200/NM2200-ZX audio controllers +Neomagic device characteristics: + o 8/16 bit playback/record + o mono/stereo playback/recording + o 8KHz to 48Khz sample rate. + +OPTIONS +None + +FILES +CONFIGFILEPATH/oss_neomagic.conf Device configuration file + +AUTHOR +4Front Technologies + diff --git a/attic/drv/oss_s3vibes/.config b/attic/drv/oss_s3vibes/.config new file mode 100644 index 0000000..5280084 --- /dev/null +++ b/attic/drv/oss_s3vibes/.config @@ -0,0 +1 @@ +platform=i86pc diff --git a/attic/drv/oss_s3vibes/.devices b/attic/drv/oss_s3vibes/.devices new file mode 100644 index 0000000..cc530e0 --- /dev/null +++ b/attic/drv/oss_s3vibes/.devices @@ -0,0 +1 @@ +oss_s3vibes pci5333,ca00 S3 Sonic Vibes diff --git a/attic/drv/oss_s3vibes/.name b/attic/drv/oss_s3vibes/.name new file mode 100644 index 0000000..7906362 --- /dev/null +++ b/attic/drv/oss_s3vibes/.name @@ -0,0 +1 @@ +S3 Sonic Vibes diff --git a/attic/drv/oss_s3vibes/oss_s3vibes.c b/attic/drv/oss_s3vibes/oss_s3vibes.c new file mode 100644 index 0000000..076988d --- /dev/null +++ b/attic/drv/oss_s3vibes/oss_s3vibes.c @@ -0,0 +1,931 @@ + +/* + * Purpose: Driver for S3 SonicVibes PCI audio controller. + */ +/* + * + * This file is part of Open Sound System. + * + * Copyright (C) 4Front Technologies 1996-2008. + * + * This this source file is released under GPL v2 license (no other versions). + * See the COPYING file included in the main directory of this source + * distribution for the license terms and conditions. + * + */ + +#include "oss_s3vibes_cfg.h" +#include "oss_pci.h" + +#ifdef USE_LICENSING +#include "private/licensing/licensing.h" +#endif + +#define S3_VENDOR_ID 0x5333 +#define S3_SONICVIBES 0xca00 + +#define MIXER_DEVS (SOUND_MASK_LINE1 | SOUND_MASK_LINE2 | \ + SOUND_MASK_MIC | SOUND_MASK_VOLUME | \ + SOUND_MASK_CD | SOUND_MASK_LINE | \ + SOUND_MASK_PCM | SOUND_MASK_SYNTH | \ + SOUND_MASK_RECLEV|SOUND_MASK_DEPTH ) + +#define REC_DEVS (SOUND_MASK_LINE1 | SOUND_MASK_LINE2 | \ + SOUND_MASK_MIC | \ + SOUND_MASK_CD | SOUND_MASK_LINE) + +#define STEREO_DEVS (SOUND_MASK_LINE1 | SOUND_MASK_LINE | \ + SOUND_MASK_VOLUME | \ + SOUND_MASK_CD | SOUND_MASK_LINE | \ + SOUND_MASK_PCM | SOUND_MASK_RECLEV) + +#define LEFT_CHN 0 +#define RIGHT_CHN 1 + +static int default_mixer_levels[32] = { + 0x3232, /* Master Volume */ + 0x3232, /* Bass */ + 0x3232, /* Treble */ + 0x4b4b, /* FM */ + 0x3232, /* PCM */ + 0x1515, /* PC Speaker */ + 0x2020, /* Ext Line */ + 0x1010, /* Mic */ + 0x4b4b, /* CD */ + 0x0000, /* Recording monitor */ + 0x4b4b, /* Second PCM */ + 0x4b4b, /* Recording level */ + 0x4b4b, /* Input gain */ + 0x4b4b, /* Output gain */ + 0x2020, /* Line1 */ + 0x2020, /* Line2 */ + 0x1515 /* Line3 (usually line in) */ +}; + +#define MAX_PORTC 2 + +typedef struct vibes_portc +{ + int audio_dev; + int open_mode; + int channels; + int bits; + int speed; + int trigger_bits; + int audio_enabled; +} +vibes_portc; + +typedef struct vibes_devc +{ + oss_device_t *osdev; + int sb_base; + int enh_base; + int fm_base; + int mpu_base; + int game_base; + int dmaa_base; + int dmac_base; + int irq; + oss_mutex_t mutex; + oss_mutex_t low_mutex; + + /* Mixer parameters */ + int my_mixer; + int *levels; + int recdevs; + + /* Audio parameters */ + int audio_open_mode; + vibes_portc portc[MAX_PORTC]; +} +vibes_devc; + + +static int +vibesintr (oss_device_t * osdev) +{ + vibes_devc *devc = (vibes_devc *) osdev->devc; + vibes_portc *portc; + unsigned char stat; + int serviced = 0; + int i; + + stat = INB (devc->osdev, devc->enh_base + 0x02); + + for (i = 0; i < MAX_PORTC; i++) + { + portc = &devc->portc[i]; + if ((stat & 0x01) && (portc->trigger_bits & PCM_ENABLE_OUTPUT)) + { + serviced = 1; + oss_audio_outputintr (portc->audio_dev, 1); + } + + if ((stat & 0x04) && (portc->trigger_bits & PCM_ENABLE_INPUT)) + { + serviced = 1; + oss_audio_inputintr (portc->audio_dev, 0); + } + } + return serviced; +} + +static unsigned char +vibes_mixer_read (vibes_devc * devc, int reg) +{ + oss_native_word flags; + unsigned char data, tmp; + + MUTEX_ENTER_IRQDISABLE (devc->low_mutex, flags); + /* Select register index */ + tmp = INB (devc->osdev, devc->enh_base + 4) & 0xc0; + OUTB (devc->osdev, tmp | (reg & 0x3f), devc->enh_base + 4); + oss_udelay (10); + /* Read the register */ + data = INB (devc->osdev, devc->enh_base + 5); + MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags); + return data; +} + +static void +vibes_mixer_write (vibes_devc * devc, int reg, unsigned char data) +{ + oss_native_word flags; + unsigned char tmp; + + MUTEX_ENTER_IRQDISABLE (devc->low_mutex, flags); + /* Select register index */ + tmp = INB (devc->osdev, devc->enh_base + 0x04) & 0xc0; + OUTB (devc->osdev, tmp | (reg & 0x3f), devc->enh_base + 4); + oss_udelay (10); + /* Write the register */ + OUTB (devc->osdev, data, devc->enh_base + 0x05); + MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags); +} + +static int +vibes_set_recmask (vibes_devc * devc, int mask) +{ + unsigned char bits = 0, tmp; + oss_native_word flags; + mask &= REC_DEVS; + + if (mask & (mask - 1)) /* More than one bits selected */ + mask = mask & (devc->recdevs ^ mask); /* Pick the one recently turned on */ + + switch (mask) + { + case SOUND_MASK_CD: + bits = 0; + break; + case SOUND_MASK_LINE2: + bits = 3; + break; + case SOUND_MASK_LINE: + bits = 4; + break; + case SOUND_MASK_LINE1: + bits = 5; + break; + case SOUND_MASK_MIC: + bits = 6; + break; + + default: /* Unknown bit (combination) */ + mask = SOUND_MASK_MIC; + bits = 6; + } + + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); + tmp = vibes_mixer_read (devc, 0x00) & 0x1f; /* Left ADC source */ + vibes_mixer_write (devc, 0x00, tmp | (bits << 5)); + tmp = vibes_mixer_read (devc, 0x01) & 0x1f; /* Right ADC source */ + vibes_mixer_write (devc, 0x01, tmp | (bits << 5)); + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + return devc->recdevs = mask; +} + +static int +vibes_mixer_get (vibes_devc * devc, int dev) +{ + if (!((1 << dev) & MIXER_DEVS)) + return OSS_EINVAL; + + return devc->levels[dev]; +} + +static void +set_volume (vibes_devc * devc, int reg, int level, int width) +{ + unsigned char tmp, bits; + int scale = (1 << width) - 1; + + tmp = vibes_mixer_read (devc, reg) & ~(0x80 | scale); + + if (level == 0) + bits = 0x80; + else + { + bits = (scale * level) / 100; + bits = scale - bits; /* Reverse */ + } + + vibes_mixer_write (devc, reg, tmp | bits); +} + +static int +vibes_mixer_set (vibes_devc * devc, int dev, int value) +{ + int left = value & 0x000000ff; + int right = (value & 0x0000ff00) >> 8; + + if (left > 100) + left = 100; + if (right > 100) + right = 100; + + switch (dev) + { + case SOUND_MIXER_LINE1: + set_volume (devc, 0x02, left, 5); + set_volume (devc, 0x03, right, 5); + break; + + case SOUND_MIXER_CD: + set_volume (devc, 0x04, left, 5); + set_volume (devc, 0x05, right, 5); + break; + + case SOUND_MIXER_LINE: + set_volume (devc, 0x06, left, 5); + set_volume (devc, 0x07, right, 5); + break; + + case SOUND_MIXER_MIC: + set_volume (devc, 0x08, left, 4); /* Mono control with just 4 bits */ + right = left; + break; + + case SOUND_MIXER_SYNTH: + set_volume (devc, 0x0a, left, 5); + set_volume (devc, 0x0b, right, 5); + break; + + case SOUND_MIXER_LINE2: + set_volume (devc, 0x0c, left, 5); + set_volume (devc, 0x0d, right, 5); + break; + + case SOUND_MIXER_VOLUME: + set_volume (devc, 0x0e, left, 6); + set_volume (devc, 0x0f, right, 6); + break; + + case SOUND_MIXER_PCM: + set_volume (devc, 0x10, left, 5); + set_volume (devc, 0x11, right, 5); + break; + + case SOUND_MIXER_RECLEV: + { + int tmp, bits; + + bits = (15 * left) / 100; + bits = 15 - bits; /* Reverse */ + tmp = vibes_mixer_read (devc, 0x00) & ~15; + vibes_mixer_write (devc, 0x00, tmp | bits); + + bits = (15 * right) / 100; + bits = 15 - bits; /* Reverse */ + tmp = vibes_mixer_read (devc, 0x01) & ~15; + vibes_mixer_write (devc, 0x01, tmp | bits); + } + break; + + case SOUND_MIXER_DEPTH: + set_volume (devc, 0x2c, left, 3); + right = left; + break; +#if 0 + case SOUND_MIXER_CENTER: + set_volume (devc, 0x2d, left, 3); + right = left; + break; +#endif + } + + value = left | (right << 8); + + return devc->levels[dev] = value; +} + +static void +vibes_mixer_reset (vibes_devc * devc) +{ + int i; + + for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) + if (MIXER_DEVS & (1 << i)) + vibes_mixer_set (devc, i, devc->levels[i]); + vibes_set_recmask (devc, SOUND_MASK_MIC); +} + +/*ARGSUSED*/ +static int +vibes_mixer_ioctl (int dev, int audiodev, unsigned int cmd, ioctl_arg arg) +{ + vibes_devc *devc = mixer_devs[dev]->devc; + + if (((cmd >> 8) & 0xff) == 'M') + { + int val; + + if (IOC_IS_OUTPUT (cmd)) + switch (cmd & 0xff) + { + case SOUND_MIXER_RECSRC: + val = *arg; + return *arg = vibes_set_recmask (devc, val); + break; + + default: + val = *arg; + return *arg = vibes_mixer_set (devc, cmd & 0xff, val); + } + else + switch (cmd & 0xff) /* + * Return parameters + */ + { + + case SOUND_MIXER_RECSRC: + return *arg = devc->recdevs; + break; + + case SOUND_MIXER_DEVMASK: + return *arg = MIXER_DEVS; + break; + + case SOUND_MIXER_STEREODEVS: + return *arg = STEREO_DEVS; + break; + + case SOUND_MIXER_RECMASK: + return *arg = REC_DEVS; + break; + + case SOUND_MIXER_CAPS: + return *arg = SOUND_CAP_EXCL_INPUT; + break; + + default: + return *arg = vibes_mixer_get (devc, cmd & 0xff); + } + } + else + return OSS_EINVAL; +} + +static mixer_driver_t vibes_mixer_driver = { + vibes_mixer_ioctl +}; + +static int +vibes_audio_set_rate (int dev, int arg) +{ + vibes_portc *portc = audio_engines[dev]->portc; + + if (arg == 0) + return portc->speed; + + if (arg > 48000) + arg = 48000; + if (arg < 5000) + arg = 5000; + portc->speed = arg; + return portc->speed; +} + +static short +vibes_audio_set_channels (int dev, short arg) +{ + vibes_portc *portc = audio_engines[dev]->portc; + + if ((arg != 1) && (arg != 2)) + return portc->channels; + portc->channels = arg; + + return portc->channels; +} + +static unsigned int +vibes_audio_set_format (int dev, unsigned int arg) +{ + vibes_portc *portc = audio_engines[dev]->portc; + + if (arg == 0) + return portc->bits; + + if (!(arg & (AFMT_U8 | AFMT_S16_LE))) + return portc->bits; + portc->bits = arg; + + return portc->bits; +} + +/*ARGSUSED*/ +static int +vibes_audio_ioctl (int dev, unsigned int cmd, ioctl_arg arg) +{ + return OSS_EINVAL; +} + +static void +vibes_halt_output (int dev) +{ + vibes_devc *devc = audio_engines[dev]->devc; + vibes_portc *portc = audio_engines[dev]->portc; + + unsigned char tmp; + oss_native_word flags; + + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); + tmp = vibes_mixer_read (devc, 0x13) & ~0x01; + vibes_mixer_write (devc, 0x13, tmp); + OUTB (devc->osdev, 0xff, devc->dmaa_base + 0x0d); + portc->trigger_bits &= ~PCM_ENABLE_OUTPUT; + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); +} + +static void +vibes_halt_input (int dev) +{ + vibes_devc *devc = audio_engines[dev]->devc; + vibes_portc *portc = audio_engines[dev]->portc; + + unsigned char tmp; + oss_native_word flags; + + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); + tmp = vibes_mixer_read (devc, 0x13) & ~0x02; + vibes_mixer_write (devc, 0x13, tmp); + OUTB (devc->osdev, 0xff, devc->dmac_base + 0x0d); + portc->trigger_bits &= ~PCM_ENABLE_INPUT; + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); +} + +static void +vibes_audio_reset (int dev) +{ + vibes_portc *portc = audio_engines[dev]->portc; + + if (portc->open_mode & OPEN_WRITE) + vibes_halt_output (dev); + if (portc->open_mode & OPEN_READ) + vibes_halt_input (dev); +} + +/*ARGSUSED*/ +static int +vibes_audio_open (int dev, int mode, int open_flags) +{ + oss_native_word flags; + vibes_devc *devc = audio_engines[dev]->devc; + vibes_portc *portc = audio_engines[dev]->portc; + + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); + if (devc->audio_open_mode & mode) + { + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + return OSS_EBUSY; + } + + devc->audio_open_mode |= mode; + portc->open_mode = mode; + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + + return 0; +} + +static void +vibes_audio_close (int dev, int mode) +{ + vibes_devc *devc = audio_engines[dev]->devc; + vibes_portc *portc = audio_engines[dev]->portc; + + vibes_audio_reset (dev); + devc->audio_open_mode &= ~mode; + portc->open_mode = 0; +} + +/*ARGSUSED*/ +static void +vibes_audio_output_block (int dev, oss_native_word buf, int count, + int fragsize, int intrflag) +{ + vibes_devc *devc = audio_engines[dev]->devc; + oss_native_word flags; + int c = fragsize - 1; + int dma_base = devc->dmaa_base; + + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); + vibes_mixer_write (devc, 0x18, (c >> 8) & 0xff); + vibes_mixer_write (devc, 0x19, c & 0xff); + + /* Setup DMA_A registers */ + count = count - 1; + OUTB (devc->osdev, 0xff, dma_base + 0x0d); + OUTB (devc->osdev, 0x01, dma_base + 0x0f); + OUTB (devc->osdev, (buf) & 0xff, dma_base + 0x00); + OUTB (devc->osdev, (buf >> 8) & 0xff, dma_base + 0x01); + OUTB (devc->osdev, (buf >> 16) & 0xff, dma_base + 0x02); + OUTB (devc->osdev, (buf >> 24) & 0xff, dma_base + 0x03); + OUTB (devc->osdev, (count) & 0xff, dma_base + 0x04); + OUTB (devc->osdev, (count >> 8) & 0xff, dma_base + 0x05); + OUTB (devc->osdev, (count >> 16) & 0xff, dma_base + 0x06); + OUTB (devc->osdev, 0x18, dma_base + 0x0b); + OUTB (devc->osdev, 0x00, dma_base + 0x0f); + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); +} + +/*ARGSUSED*/ +static void +vibes_audio_start_input (int dev, oss_native_word buf, int count, + int fragsize, int intrflag) +{ + vibes_devc *devc = audio_engines[dev]->devc; + oss_native_word flags; + int c = (fragsize >> 1) - 1; + int dma_base = devc->dmac_base; + + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); + vibes_mixer_write (devc, 0x1c, (c >> 8) & 0xff); + vibes_mixer_write (devc, 0x1d, c & 0xff); + + /* Setup DMA_C registers */ + count = count / 2 - 1; /* Word count */ + OUTB (devc->osdev, 0xff, dma_base + 0x0d); + OUTB (devc->osdev, (buf) & 0xff, dma_base + 0x00); + OUTB (devc->osdev, (buf >> 8) & 0xff, dma_base + 0x01); + OUTB (devc->osdev, (buf >> 16) & 0xff, dma_base + 0x02); + OUTB (devc->osdev, (buf >> 24) & 0xff, dma_base + 0x03); + OUTB (devc->osdev, (count) & 0xff, dma_base + 0x04); + OUTB (devc->osdev, (count >> 8) & 0xff, dma_base + 0x05); + OUTB (devc->osdev, (count >> 16) & 0xff, dma_base + 0x06); + OUTB (devc->osdev, 0x14, dma_base + 0x0b); + OUTB (devc->osdev, 0x00, dma_base + 0x0f); + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); +} + +/*ARGSUSED*/ +static void +vibes_audio_trigger (int dev, int state) +{ + vibes_portc *portc = audio_engines[dev]->portc; + vibes_devc *devc = audio_engines[dev]->devc; + + unsigned char tmp; + oss_native_word flags; + + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); + tmp = vibes_mixer_read (devc, 0x13) & ~0x07; + if (portc->open_mode & OPEN_WRITE) + { + tmp |= 0x01; + portc->trigger_bits |= PCM_ENABLE_OUTPUT; + } + if (portc->open_mode & OPEN_READ) + { + tmp |= 0x02; + portc->trigger_bits |= PCM_ENABLE_INPUT; + } + vibes_mixer_write (devc, 0x13, tmp); + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); +} + +static void +setup_output_rate (vibes_devc * devc, vibes_portc * portc) +{ + unsigned int p = portc->speed; + + p = (p * 65536) / 48000; + p = (p - 1) & 0xffff; + + if (p <= 1) + p = 1; + if (p > 0xffff) + p = 0xffff; + + vibes_mixer_write (devc, 0x1e, (p) & 0xff); + vibes_mixer_write (devc, 0x1f, (p >> 8) & 0xff); +} + +static void +setup_input_rate (vibes_devc * devc, vibes_portc * portc) +{ + unsigned char tmp; + + /* Use separate sampling rate for ADC and DAC */ + + tmp = vibes_mixer_read (devc, 0x22) | 0x10; + vibes_mixer_write (devc, 0x22, tmp); /* Use alternate sampling rate */ + vibes_mixer_write (devc, 0x23, ((48000 / portc->speed) - 1) << 4); +} + +/*ARGSUSED*/ +static int +vibes_audio_prepare_for_input (int dev, int bsize, int bcount) +{ + vibes_devc *devc = audio_engines[dev]->devc; + vibes_portc *portc = audio_engines[dev]->portc; + unsigned char tmp; + oss_native_word flags; + + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); + OUTB (devc->osdev, 0x40, devc->enh_base + 0x04); /* Set MCE */ + tmp = vibes_mixer_read (devc, 0x12) & ~0x30; + if (portc->channels != 1) + tmp |= 0x10; + if (portc->bits != 8) + tmp |= 0x20; + vibes_mixer_write (devc, 0x12, tmp); + setup_input_rate (devc, portc); + OUTB (devc->osdev, 0x00, devc->enh_base + 0x04); /* Clear MCE */ + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + + return 0; +} + +/*ARGSUSED*/ +static int +vibes_audio_prepare_for_output (int dev, int bsize, int bcount) +{ + vibes_devc *devc = audio_engines[dev]->devc; + vibes_portc *portc = audio_engines[dev]->portc; + unsigned char tmp; + oss_native_word flags; + + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); + tmp = vibes_mixer_read (devc, 0x12) & ~0x03; + if (portc->channels != 1) + tmp |= 0x01; + if (portc->bits != 8) + tmp |= 0x02; + + OUTB (devc->osdev, 0x40, devc->enh_base + 0x04); /* Set MCE */ + vibes_mixer_write (devc, 0x12, tmp); + setup_output_rate (devc, portc); + OUTB (devc->osdev, 0x00, devc->enh_base + 0x04); /* Clear MCE */ + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + + return 0; +} + +#if 0 +static int +vibes_get_buffer_pointer (int dev, dmap_t * dmap, int direction) +{ + vibes_devc *devc = audio_engines[dev]->devc; + /* vibes_portc *portc = audio_engines[dev]->portc; */ + unsigned int tmp = 0; + oss_native_word flags; + + MUTEX_ENTER_IRQDISABLE (devc->low_mutex, flags); + if (direction == DMODE_OUTPUT) + { + tmp = INB (devc->osdev, devc->dmaa_base + 0x04); + tmp |= INB (devc->osdev, devc->dmaa_base + 0x05) << 8; + tmp |= INB (devc->osdev, devc->dmaa_base + 0x06) << 16; + + tmp = dmap->bytes_in_use % tmp; + } + MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags); + return tmp; +} +#endif + +static audiodrv_t vibes_audio_driver = { + vibes_audio_open, + vibes_audio_close, + vibes_audio_output_block, + vibes_audio_start_input, + vibes_audio_ioctl, + vibes_audio_prepare_for_input, + vibes_audio_prepare_for_output, + vibes_audio_reset, + NULL, + NULL, + vibes_halt_input, + vibes_halt_output, + vibes_audio_trigger, + vibes_audio_set_rate, + vibes_audio_set_format, + vibes_audio_set_channels, + NULL, + NULL, + NULL, /* vibes_check_input, */ + NULL, /* vibes_check_output, */ + NULL, /*vibes_alloc_buffer, */ + NULL, /* vibes_free_buffer, */ + NULL, + NULL, + NULL /* vibes_get_buffer_pointer */ +}; + +static int +init_vibes (vibes_devc * devc) +{ + int my_mixer, adev; + int i; + unsigned char tmp; + vibes_portc *portc; + + + /* Setup CM00 */ + tmp = INB (devc->osdev, devc->enh_base + 0x00); + OUTB (devc->osdev, tmp | 0x01, devc->enh_base + 0x00); /* Enhanced mode on */ + + my_mixer = 0; + if ((my_mixer = oss_install_mixer (OSS_MIXER_DRIVER_VERSION, + devc->osdev, + devc->osdev, + "S3 SonicVibes", + &vibes_mixer_driver, + sizeof (mixer_driver_t), devc)) < 0) + { + my_mixer = -1; + return 0; + } + else + { + devc->my_mixer = my_mixer; + devc->recdevs = 0; + vibes_set_recmask (devc, SOUND_MASK_MIC); + devc->levels = load_mixer_volumes ("S3VIBES", default_mixer_levels, 1); + vibes_mixer_reset (devc); + } + + for (i = 0; i < MAX_PORTC; i++) + { + int flags = ADEV_AUTOMODE | ADEV_DUPLEX; + + portc = &devc->portc[i]; + + if (i > 0) + flags |= ADEV_SHADOW; + + if ((adev = oss_install_audiodev (OSS_AUDIO_DRIVER_VERSION, + devc->osdev, + devc->osdev, + "S3 SonicVibes", + &vibes_audio_driver, + sizeof (audiodrv_t), + flags, + AFMT_U8 | AFMT_S16_LE, devc, -1)) < 0) + { + return 0; + } + + audio_engines[adev]->mixer_dev = devc->my_mixer; + audio_engines[adev]->portc = portc; + audio_engines[adev]->dmabuf_maxaddr = MEMLIMIT_ISA; + portc->open_mode = 0; + portc->channels = 1; + portc->bits = 8; + portc->audio_dev = adev; + portc->open_mode = 0; + portc->trigger_bits = 0; + portc->audio_enabled = 0; +#ifdef CONFIG_OSS_VMIX + if (i == 0) + vmix_attach_audiodev(devc->osdev, adev, -1, 0); +#endif + } + return 1; +} + +int +oss_s3vibes_attach (oss_device_t * osdev) +{ + unsigned int dmaa_base, dmac_base; + unsigned char pci_irq_line, pci_revision; + unsigned short pci_command, vendor, device; + unsigned int pci_ioaddr0, pci_ioaddr1, pci_ioaddr2, pci_ioaddr3, + pci_ioaddr4; + vibes_devc *devc; + + DDB (cmn_err (CE_WARN, "Entered S3 SonicVibes probe routine\n")); + + pci_read_config_word (osdev, PCI_VENDOR_ID, &vendor); + pci_read_config_byte (osdev, PCI_REVISION_ID, &pci_revision); + pci_read_config_word (osdev, PCI_COMMAND, &pci_command); + pci_read_config_word (osdev, PCI_DEVICE_ID, &device); + pci_read_config_irq (osdev, PCI_INTERRUPT_LINE, &pci_irq_line); + pci_read_config_dword (osdev, PCI_BASE_ADDRESS_0, &pci_ioaddr0); + pci_read_config_dword (osdev, PCI_BASE_ADDRESS_1, &pci_ioaddr1); + pci_read_config_dword (osdev, PCI_BASE_ADDRESS_2, &pci_ioaddr2); + pci_read_config_dword (osdev, PCI_BASE_ADDRESS_3, &pci_ioaddr3); + pci_read_config_dword (osdev, PCI_BASE_ADDRESS_4, &pci_ioaddr4); + pci_read_config_dword (osdev, 0x40, &dmaa_base); + pci_read_config_dword (osdev, 0x48, &dmac_base); + + if (vendor != S3_VENDOR_ID || device != S3_SONICVIBES) + return 0; + + if (pci_ioaddr0 == 0) + { + cmn_err (CE_WARN, "I/O address not assigned by BIOS.\n"); + return 0; + } + + if (pci_irq_line == 0) + { + cmn_err (CE_WARN, "IRQ not assigned by BIOS (%d).\n", pci_irq_line); + return 0; + } + + if ((devc = PMALLOC (osdev, sizeof (*devc))) == NULL) + { + cmn_err (CE_WARN, "Out of memory\n"); + return 0; + } + + devc->osdev = osdev; + osdev->devc = devc; + devc->irq = pci_irq_line; + + devc->sb_base = MAP_PCI_IOADDR (devc->osdev, 0, pci_ioaddr0); + devc->enh_base = MAP_PCI_IOADDR (devc->osdev, 1, pci_ioaddr1); + devc->fm_base = MAP_PCI_IOADDR (devc->osdev, 2, pci_ioaddr2); + devc->mpu_base = MAP_PCI_IOADDR (devc->osdev, 3, pci_ioaddr3); + devc->game_base = MAP_PCI_IOADDR (devc->osdev, 4, pci_ioaddr4); + + /* Remove I/O space marker in bit 0. */ + devc->sb_base &= ~3; + devc->enh_base &= ~3; + devc->fm_base &= ~3; + devc->mpu_base &= ~3; + devc->game_base &= ~3; + + DDB (cmn_err (CE_WARN, "SB compatibility base %04x\n", devc->sb_base)); + DDB (cmn_err (CE_WARN, "Enhanced base %04x\n", devc->enh_base)); + DDB (cmn_err (CE_WARN, "FM base %04x\n", devc->fm_base)); + DDB (cmn_err (CE_WARN, "MIDI base %04x\n", devc->mpu_base)); + DDB (cmn_err (CE_WARN, "Game port base %04x\n", devc->game_base)); + DDB (cmn_err (CE_WARN, "DMA_A port base %04x\n", dmaa_base)); + DDB (cmn_err (CE_WARN, "DMA_C port base %04x\n", dmac_base)); + + dmaa_base = (dmaa_base & 0x000f) + devc->sb_base; + dmac_base = (dmac_base & 0x000f) + devc->sb_base + 16; + + dmaa_base |= 0x09; /* Enable. Allow 32 bit addressing */ + dmac_base |= 0x01; /* Enable */ + + pci_write_config_dword (osdev, 0x40, dmaa_base); + pci_write_config_dword (osdev, 0x48, dmac_base); + DDB (cmn_err (CE_WARN, "DMA_A port base relocated to %04x\n", dmaa_base)); + DDB (cmn_err (CE_WARN, "DMA_C port base relocated to %04x\n", dmac_base)); + + devc->dmaa_base = dmaa_base & ~0x000f; + devc->dmac_base = dmac_base & ~0x000f; + + pci_command |= PCI_COMMAND_MASTER | PCI_COMMAND_IO; + pci_write_config_word (osdev, PCI_COMMAND, pci_command); + + MUTEX_INIT (devc->osdev, devc->mutex, MH_DRV); + MUTEX_INIT (devc->osdev, devc->low_mutex, MH_DRV + 1); + + oss_register_device (osdev, "S3 Sonic Vibes"); + + if (oss_register_interrupts (devc->osdev, 0, vibesintr, NULL) < 0) + { + cmn_err (CE_WARN, "Can't allocate IRQ%d\n", pci_irq_line); + return 0; + } + + return init_vibes (devc); /* Detected */ +} + +int +oss_s3vibes_detach (oss_device_t * osdev) +{ + vibes_devc *devc = (vibes_devc *) osdev->devc; + + if (oss_disable_device (osdev) < 0) + return 0; + + oss_unregister_interrupts (devc->osdev); + + MUTEX_CLEANUP (devc->mutex); + MUTEX_CLEANUP (devc->low_mutex); + UNMAP_PCI_IOADDR (devc->osdev, 0); + UNMAP_PCI_IOADDR (devc->osdev, 1); + UNMAP_PCI_IOADDR (devc->osdev, 2); + UNMAP_PCI_IOADDR (devc->osdev, 3); + UNMAP_PCI_IOADDR (devc->osdev, 4); + + oss_unregister_device (devc->osdev); + return 1; + +} diff --git a/attic/drv/oss_s3vibes/oss_s3vibes.man b/attic/drv/oss_s3vibes/oss_s3vibes.man new file mode 100644 index 0000000..9949d94 --- /dev/null +++ b/attic/drv/oss_s3vibes/oss_s3vibes.man @@ -0,0 +1,19 @@ +NAME +oss_s3vibes - S3 Sonic Vibes audio driver + +DESCRIPTION +Open Sound System driver for S3 Sonic Vibes audio controller. +S3Vibes device characteristics: + o 8/16 bit playback/record + o mono/stereo playback/recording + o 8KHz to 44.1Khz sample rate. + +OPTIONS +None + +FILES +CONFIGFILEPATH/oss_s3vibes.conf Device configuration file + +AUTHOR +4Front Technologies + diff --git a/attic/drv/oss_vortex/.devices b/attic/drv/oss_vortex/.devices new file mode 100644 index 0000000..97accba --- /dev/null +++ b/attic/drv/oss_vortex/.devices @@ -0,0 +1,3 @@ +oss_vortex pci12eb,1 Aureal Vortex (AU8820) +oss_vortex pci12eb,2 Aureal Vortex2 (AU8830) +oss_vortex AU8810 Aureal Vortex Advantage (AU8810) *** NOT SUPPORTED *** diff --git a/attic/drv/oss_vortex/.name b/attic/drv/oss_vortex/.name new file mode 100644 index 0000000..ed0ca62 --- /dev/null +++ b/attic/drv/oss_vortex/.name @@ -0,0 +1 @@ +Aureal Vortex (AU8820) and Vortex2 (AU8830) diff --git a/attic/drv/oss_vortex/oss_vortex.c b/attic/drv/oss_vortex/oss_vortex.c new file mode 100644 index 0000000..d8c1738 --- /dev/null +++ b/attic/drv/oss_vortex/oss_vortex.c @@ -0,0 +1,1749 @@ +/* + * Purpose: Driver for Aureal Semiconductor Vortex PCI audio controller. + */ +/* + * + * This file is part of Open Sound System. + * + * Copyright (C) 4Front Technologies 1996-2008. + * + * This this source file is released under GPL v2 license (no other versions). + * See the COPYING file included in the main directory of this source + * distribution for the license terms and conditions. + * + */ + +#include "vortex.h" + +#undef USE_SRC + +#define AUREAL_VENDOR_ID 0x12eb +#define AUREAL_VORTEX 0x0001 +#define AUREAL_VORTEX2 0x0002 + +#define global_base (0x12800) +# define GIRQSTAT global_base+0x0 +# define MODIRQST 0x00004000 +# define MIDIRQST 0x00002000 +# define TIMIRQST 0x00001000 +# define COIRQLST 0x00000800 +# define COIRQPST 0x00000400 +# define FRCIRQST 0x00000200 +# define SBIRQST 0x00000100 +# define SBMIRQST 0x00000080 +# define FMIRQST 0x00000040 +# define DMAENDIRQST 0x00000020 +# define DMABERRST 0x00000010 +# define FIFOERRST 0x00000008 +# define REGERRST 0x00000004 +# define MPARERRST 0x00000002 +# define MFATERRST 0x00000001 +# define GIRQCTL global_base+0x4 +# define GSTAT global_base+0x8 +# define GCTL global_base+0xc +# define SFTRST 0x00800000 +# define ARBRST 0x00400000 +# define EXTRST 0x00200000 +# define RBTOEN 0x00100000 +# define AINCEN 0x00080000 +# define TTXFLUSH 0x00040000 +# define TRVFLUSH 0x00020000 +# define MFIFOFLUSH 0x00010000 +# define FRCIRQ 0x00008000 +# define GIRQEN 0x00004000 + +#define dma_base (0x10000) + +#define midi_base (0x11000) +# define MIDIDAT midi_base+0x0 +# define MIDICMD midi_base+0x4 +# define MIDISTAT MIDICMD +# define MIDIVAL 0x00000080 +# define CMDOK 0x00000040 +# define MPUMODE 0x00000001 +# define GAMECTL midi_base+0xc +# define JOYMODE 0x00000040 +# define MIDITXFULL 0x00000008 +# define MIDIRXINIT 0x00000004 +# define MIDIRXOVFL 0x00000002 +# define MIDIDATVAL 0x00000001 + +#define fifo_base (0xe000) +#define adb_destinations 103 +#define adbarb_block_base (0x10800) +#define serial_block_base (0x11800) +# define CODSMPLTMR serial_block_base+0x19c +#define adbarb_wtdram_base_addr (adbarb_block_base + 0x000) +#define adbarb_wtdram_srhdr_base_addr (adbarb_block_base + (adb_destinations * 4)) +#define adbarb_sr_active_addr (adbarb_block_base + 0x200) +#define adbarb_srb_last_addr (adbarb_block_base + 0x204) +#define codec_control_reg_addr (serial_block_base + 0x0184) +#define cmd_status_reg_addr (serial_block_base + 0x0188) +#define channel_enable_reg_addr (serial_block_base + 0x0190) +#define serial_ram_reg_addr (serial_block_base + 0x00) + +#define fifo_chan0_src_addr 0x00 +#define fifo_chan1_src_addr 0x01 +#define fifo_chan2_dst_addr 0x02 +#define fifo_chan2a_dst_addr 0x022 +#define fifo_chan3_dst_addr 0x03 +#define fifo_chan3a_dst_addr 0x023 +#define fifo_chan4_dst_addr 0x04 +#define fifo_chan5_dst_addr 0x05 +#define fifo_chan6_dst_addr 0x06 +#define fifo_chan7_dst_addr 0x07 +#define fifo_chan8_dst_addr 0x08 +#define fifo_chan9_dst_addr 0x09 +#define fifo_chana_dst_addr 0x0a +#define fifo_chanb_dst_addr 0x0b +#define src_chan0_src_addr 0x10 +#define src_chan1_src_addr 0x11 +#define src_chan0_dst_addr 0x10 +#define src_chan1_dst_addr 0x11 +#define codec_chan0_src_addr 0x48 +#define codec_chan1_src_addr 0x49 +#define codec_chan0_dst_addr 0x58 +#define codec_chan1_dst_addr 0x59 + +#define src_base (0xc000) +#define src_input_fifo (src_base + 0x000) +#define src_output_double_buffer (src_base + 0x800) +#define src_next_channel (src_base + 0xc00) +#define src_sr_header (src_base + 0xc40) +#define src_active_sample_rate (src_base + 0xcc0) +#define src_throttle_source (src_base + 0xcc4) +#define src_throttle_count_size (src_base + 0xcc8) +#define src_channel_params (src_base + 0xe00) + +/* static int dst_routed[256] = { 0 }; */ + + +static unsigned int +ReadReg (vortex_devc * devc, oss_native_word addr) +{ + return READL (addr); +} + +static void +WriteReg (vortex_devc * devc, oss_native_word addr, unsigned int data) +{ + WRITEL (addr, data); +} + +static void +ReadCodecRegister (vortex_devc * devc, int cIndex, int *pdwData) +{ + int dwCmdStRegAddr; + int dwCmdStRegData; + int nCnt = 0; + + dwCmdStRegAddr = cIndex << 16; + WriteReg (devc, cmd_status_reg_addr, dwCmdStRegAddr); + do + { + dwCmdStRegData = ReadReg (devc, cmd_status_reg_addr); + if (nCnt++ > 10) + oss_udelay (10); + } + while ((dwCmdStRegData & 0x00FF0000) != ((1 << 23) | (dwCmdStRegAddr)) + && (nCnt < 100)); + if (nCnt >= 100) + { + *pdwData = dwCmdStRegData; + cmn_err (CE_WARN, + "timeout waiting for Status Valid bit in the Command Status Reg, index %x\n", + cIndex); + } + else + *pdwData = dwCmdStRegData & 0x0000ffff; +} + +static void +WriteCodecCommand (vortex_devc * devc, int cIndex, int wData) +{ + int dwData; + int nCnt = 0; + + do + { + dwData = ReadReg (devc, codec_control_reg_addr); + if (nCnt++ > 10) + oss_udelay (100); + } + while (!(dwData & 0x0100) && (nCnt < 100)); + if (nCnt >= 100) + cmn_err (CE_WARN, "timeout waiting for Codec Command Write OK bit.\n"); + + + do + { + dwData = ReadReg (devc, codec_control_reg_addr); + if (nCnt++ > 1) + oss_udelay (100); + } + while (!(dwData & 0x0100) && (nCnt < 100)); + if (nCnt >= 100) + cmn_err (CE_WARN, "timeout waiting for Codec Command Write OK bit.\n"); + + dwData = (cIndex << 16) | (1 << 23) | wData; + WriteReg (devc, cmd_status_reg_addr, dwData); + oss_udelay (1000); + + /* Read it back to make sure it got there */ + do + { + dwData = ReadReg (devc, codec_control_reg_addr); + if (nCnt++ > 1) + oss_udelay (1000); + } + while (!(dwData & 0x0100) && (nCnt < 100)); + if (nCnt >= 100) + cmn_err (CE_WARN, "timeout waiting for Codec Command Write OK bit.\n"); + ReadCodecRegister (devc, cIndex, &dwData); + if (dwData != (int) wData) + { + do + { + dwData = ReadReg (devc, codec_control_reg_addr); + if (nCnt++ > 1) + oss_udelay (1000); + } + while (!(dwData & 0x0100) && (nCnt < 100)); + if (nCnt >= 1000) + cmn_err (CE_WARN, + "timeout waiting for Codec Command Write OK bit.\n"); + dwData = (cIndex << 16) | (1 << 23) | wData; + WriteReg (devc, cmd_status_reg_addr, dwData); + do + { + dwData = ReadReg (devc, codec_control_reg_addr); + if (nCnt++ > 1) + oss_udelay (100); + } + while (!(dwData & 0x0100) && (nCnt < 50)); + if (nCnt >= 10) + cmn_err (CE_WARN, + "timeout waiting for Codec Command Write OK bit.\n"); +#if 0 + ReadCodecRegister (devc, cIndex, &dwData); + if (dwData != (int) wData) + { + cmn_err (CE_WARN, + "Vortex ERROR: Write to index %x failed (exp %04x, got %04x)\n", + cIndex, wData, dwData); + } +#endif + } +} + +static int +ac97_read (void *devc_, int addr) +{ + vortex_devc *devc = devc_; + int data; + oss_native_word flags; + + MUTEX_ENTER_IRQDISABLE (devc->low_mutex, flags); + ReadCodecRegister (devc, addr, &data); + MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags); + return data & 0xffff; +} + +static int +ac97_write (void *devc_, int addr, int data) +{ + vortex_devc *devc = devc_; + oss_native_word flags; + + MUTEX_ENTER_IRQDISABLE (devc->low_mutex, flags); + WriteCodecCommand (devc, addr, data); + MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags); + return 0; +} + +static void +ClearDataFifo (vortex_devc * devc, int nChannel) +{ + int j; + /* Clear out FIFO data */ + for (j = 0; j < 32; j++) + WriteReg (devc, fifo_base + (0x80 * nChannel) + (0x4 * j), 0x0); +} + +static int +vortexintr (oss_device_t * osdev) +{ + vortex_devc *devc = (vortex_devc *) osdev->devc; + int status; + int i; + int serviced = 0; + + /* + * TODO: Fix mutexes and move the inputintr/outputintr calls outside the + * mutex block. + */ + /* MUTEX_ENTER (devc->mutex, flags); */ + status = ReadReg (devc, GIRQSTAT); + +#if 0 + if (status & MFATERRST) + cmn_err (CE_WARN, "Master fatal error interrupt\n"); + if (status & MPARERRST) + cmn_err (CE_WARN, "Master parity error interrupt\n"); +#endif + + if (status & TIMIRQST) /* Timer interrupt */ + { + ReadReg (devc, CODSMPLTMR); /* Clear the interrupt */ + WriteReg (devc, CODSMPLTMR, 0x00001000); + serviced = 1; + } + + if (status & DMAENDIRQST) /* DMA end interrupt */ + { + for (i = 0; i < MAX_PORTC; i++) + { + vortex_portc *portc = &devc->portc[i]; + + if (portc->trigger_bits & PCM_ENABLE_OUTPUT) + { + dmap_t *dmap = audio_engines[portc->audiodev]->dmap_out; + + int pos = 0, n; + unsigned int dmastat; + + dmastat = ReadReg (devc, dma_base + 0x5c0); + pos = ((dmastat >> 12) & 0x03) * 4096 + (dmastat & 4095); + + pos /= dmap->fragment_size - 1; + if (pos < 0 || pos >= dmap->nfrags) + pos = 0; + + n = 0; + while (dmap_get_qhead (dmap) != pos && n++ < dmap->nfrags) + oss_audio_outputintr (portc->audiodev, 0); + } + + if (portc->trigger_bits & PCM_ENABLE_INPUT) + { + dmap_t *dmap = audio_engines[portc->audiodev]->dmap_in; + + int pos = 0, n; + unsigned int dmastat; + + dmastat = ReadReg (devc, dma_base + 0x5c8); + + pos = ((dmastat >> 12) & 0x03) * 4096 + (dmastat & 4095); + + pos /= dmap->fragment_size; + if (pos < 0 || pos >= dmap->nfrags) + pos = 0; + + n = 0; + while (dmap_get_qtail (dmap) != pos && n++ < dmap->nfrags) + oss_audio_inputintr (portc->audiodev, 0); + } + ReadReg (devc, dma_base + 0x600); /* Read Dma Status0 */ + ReadReg (devc, dma_base + 0x604); /* Read Dma Status1 */ + ReadReg (devc, dma_base + 0x608); /* Read Dma Status2 */ + serviced = 1; + } + } + + if (status & MIDIRQST) /* MIDI interrupt */ + { + int uart_stat = ReadReg (devc, MIDISTAT); + int n = 10; + + while (!(uart_stat & MIDIVAL) && n--) + { + int d; + d = ReadReg (devc, MIDIDAT) & 0xff; + + if (devc->midi_opened & OPEN_READ && devc->midi_input_intr) + devc->midi_input_intr (devc->midi_dev, d); + uart_stat = ReadReg (devc, MIDISTAT); + } + serviced = 1; + } + if (status != 0) + { + WriteReg (devc, GIRQSTAT, status & 0x7ff); /* Ack pulse interrupts */ + serviced = 1; + } + + /* MUTEX_EXIT (devc->mutex, flags); */ + return serviced; +} + +static void +cold_reset (vortex_devc * devc) +{ + int i; + int bSigmatelCodec = 0; + + for (i = 0; i < 32; i = i + 1) + { + WriteReg (devc, serial_ram_reg_addr + 0x80 + (i * 4), 0); + oss_udelay (100); + } + if (bSigmatelCodec) + { + /* Disable clock */ + WriteReg (devc, codec_control_reg_addr, 0x00a8); + oss_udelay (100); + /* Set Sync High */ + /* WriteReg(devc, codec_control_reg_addr, 0x40a8); */ + /* delay(100); */ + /* Place CODEC into reset */ + WriteReg (devc, codec_control_reg_addr, 0x80a8); + oss_udelay (100); + /* Give CODEC some Clocks with reset asserted */ + WriteReg (devc, codec_control_reg_addr, 0x80e8); + oss_udelay (100); + /* Turn off clocks */ + WriteReg (devc, codec_control_reg_addr, 0x80a8); + oss_udelay (100); + /* Take out of reset */ + /* WriteReg(devc, codec_control_reg_addr, 0x40a8); */ + /* oss_udelay(100); */ + /* Release reset */ + WriteReg (devc, codec_control_reg_addr, 0x00a8); + oss_udelay (100); + /* Turn on clocks */ + WriteReg (devc, codec_control_reg_addr, 0x00e8); + oss_udelay (100); + } + else + { + WriteReg (devc, codec_control_reg_addr, 0x8068); + oss_udelay (10); + WriteReg (devc, codec_control_reg_addr, 0x00e8); + oss_udelay (10); + } +} + +static void +InitCodec (vortex_devc * devc) +{ + int i; + cold_reset (devc); + for (i = 0; i < 32; i = i + 1) + { + WriteReg (devc, serial_ram_reg_addr + 0x80 + (i * 4), 0); + oss_udelay (10); + } + /* Set up the codec in AC97 mode */ + WriteReg (devc, codec_control_reg_addr, 0x00e8); + oss_udelay (10); + /* Clear the channel enable register */ + WriteReg (devc, channel_enable_reg_addr, 0); +} + +static void +SetupCodec (vortex_devc * devc) +{ + int dwData; + int count = 0; + int dwBit26 = 1 << 26; + + /* do the following only for ac97 codecs */ + /* Wait for Codec Ready (bit 26) */ + do + { + dwData = ReadReg (devc, codec_control_reg_addr); + if (count++ > 1) + oss_udelay (10); + } + while ((count < 100) && !(dwData & dwBit26)); + if (count >= 100) + { + cmn_err (CE_WARN, "Error: timeout waiting for Codec Ready bit.\n"); + cmn_err (CE_WARN, "Codec Interface Control Register is %08x\n", dwData); + } + /* Write interesting data to the Codec 97 Mixer registers */ + /* Master Volume 0dB Attunuation, Not muted. */ + WriteCodecCommand (devc, 0x02, 0x0f0f); + oss_udelay (10); + /* Master Volume mono muted. */ + WriteCodecCommand (devc, 0x06, 0x8000); + oss_udelay (10); + /* Mic Volume muted. */ + WriteCodecCommand (devc, 0x0e, 0x8000); + oss_udelay (10); + /* Line In Volume muted. */ + WriteCodecCommand (devc, 0x10, 0x8000); + oss_udelay (10); + /* CD Volume muted. */ + WriteCodecCommand (devc, 0x12, 0x8000); + oss_udelay (10); + /* Aux Volume muted. */ + WriteCodecCommand (devc, 0x16, 0x8000); + oss_udelay (10); + /* PCM out Volume 0 dB Gain, Not muted. */ + WriteCodecCommand (devc, 0x18, 0x0f0f); + oss_udelay (10); + /* Record select, select Mic for recording */ + WriteCodecCommand (devc, 0x1a, 0x0404); + oss_udelay (10); + /* Record Gain, 0dB */ + WriteCodecCommand (devc, 0x1c, 0x8000); + oss_udelay (10); + + /* Poll the Section Ready bits in the Status Register (index 0x26) */ + count = 0; + do + { + ReadCodecRegister (devc, 0x26, &dwData); + if (count++ > 1) + oss_udelay (10); + } + while (!(dwData & 0x02) && (count < 10)); + if (!(dwData & 0x02)) + cmn_err (CE_WARN, "DAC section ready bit is not set.\n"); + + /* Read and confirm the data in the Codec 97 Mixer registers. */ + /* just the PCM reg, as a sanity check */ + ReadCodecRegister (devc, 0x18, &dwData); + if ((dwData & 0x0000ffff) != 0xf0f) + { + cmn_err (CE_WARN, "PCM volume reg is %x, sb 0xf0f.\n", dwData); + } +} + +static void +InitAdb (vortex_devc * devc) +{ +/* parameter values for write_op */ +#define op_none 0 /* dst_op = x */ +#define op_tail 1 /* dst_op = x */ +#define op_add 2 /* dst_op = dst_addr being added */ +#define op_adds 3 /* dst_op = dst_addr being added */ +#define op_del 4 /* dst_op = dst_addr being deleted */ +#define op_dels 5 /* dst_op = dst_addr being deleted */ +#define op_inval 6 /* dst_op = x */ + + int i; +#if 0 + unsigned char /*reg [3:0] */ write_op; + unsigned char /*reg [6:0] */ dst_op; + unsigned char /*reg [6:0] */ src_op; + unsigned char /*reg [SS:0] */ sr_op; +#endif + /* misc */ + + devc->sr_active = 0; + /* the initial tail for each list is the header location */ + for (i = 0; i <= 31; i = i + 1) + devc->tail_index[i] = adb_destinations + i; + for (i = 0; i <= 127; i = i + 1) + devc->dst_index[i] = 0x7f; /*~('b0); */ + for (i = 0; i <= 127; i = i + 1) + devc->sr_list[i] = 0x1f; /*~('b0); */ +#if 0 + write_op = op_none; + dst_op = 0x7f; /* ~('b0); */ + src_op = 0x7f; /* ~('b0); */ + sr_op = 0x1f; /* ~('b0); */ +#endif + /* Disable any active sample rate */ + WriteReg (devc, 0x10800 + 0x200, 0); + /* Null out all the linked lists */ + for (i = 0; i < 0x1f0; i = i + 4) + { + WriteReg (devc, 0x10800 + i, 0xffffffff); + } +} + +static void +SetBit (unsigned int owData[], int nBit, unsigned char cVal) +{ + if (cVal) + owData[nBit / 32] |= (1 << (nBit % 32)); + else + owData[nBit / 32] &= ~(1 << (nBit % 32)); +} + +/*ARGSUSED*/ +static int +add_route (vortex_devc * devc, unsigned int sr, + unsigned int src_addr, unsigned int dst_addr, int verify) +{ + + unsigned int ram_hdr_addr; + unsigned int ram_dst_addr; + unsigned int ram_tail_addr; + unsigned int sr_ram_index; + + sr_ram_index = adb_destinations + sr; + ram_hdr_addr = adbarb_wtdram_srhdr_base_addr + (sr * 4); /* VHRDxx[sr] */ + ram_dst_addr = adbarb_wtdram_base_addr + (dst_addr * 4); /* VDSTxx[dst_addr] */ + ram_tail_addr = adbarb_wtdram_base_addr + (devc->tail_index[sr] * 4); + + /* since always add to end of list, ram[dst_addr] will be the new tail. */ + /* and, since we could be adding to an active list, the tail needs */ + /* to be NULLed before the new link is inserted */ + /* (since we need to check the current tail next, devc->tail_index is */ + /* updated a bit later below.) */ + WriteReg (devc, ram_dst_addr, 0xffffffff); + + /* check if this sr has a list started yet */ + if (devc->tail_index[sr] == (adb_destinations + sr)) + { + /* current tail for this sample rate indicates that list is empty, */ + /* thus this route will be head of list */ + WriteReg (devc, ram_hdr_addr, ((src_addr << 7) | dst_addr)); + devc->dst_index[dst_addr] = sr_ram_index; + } + else + { + /* add to end of list */ + WriteReg (devc, ram_tail_addr, ((src_addr << 7) | dst_addr)); + devc->dst_index[dst_addr] = devc->tail_index[sr]; + } + + /* keep track of the new tail */ + devc->tail_index[sr] = dst_addr; + + /* keep track of which sample rate list this dst_addr now belongs to */ + devc->sr_list[dst_addr] = sr; + + /* mark dst_addr as routed */ + /* dst_routed[dst_addr] = 1; */ + SetBit ((unsigned int *) &devc->dst_routed, dst_addr, 1); + + return 0; +} + +/*ARGSUSED*/ +static void +del_route (vortex_devc * devc, unsigned char dst_addr, int verify) +{ + + unsigned int data, ram_dst_addr, ram_rtd_addr; + unsigned char sr; + + ram_dst_addr = adbarb_wtdram_base_addr + (dst_addr * 4); + ram_rtd_addr = adbarb_wtdram_base_addr + (devc->dst_index[dst_addr] * 4); + + /* get the sr list that this dst_addr belongs to */ + sr = devc->sr_list[dst_addr]; + + /* mark dst as no longer routed */ + SetBit ((unsigned int *) &devc->dst_routed, dst_addr, 0); + + /* remove the dst from the sr_list then check to see if this was the */ + /* last route in the list. if so, disable wtd for this sample rate */ + devc->sr_list[dst_addr] = 0x1f; /*~('b0); */ + + /* find out what's linked to us so we can reroute it. if we are the */ + /* tail, this will be NULL and will get relinked as such */ + data = ReadReg (devc, ram_dst_addr); + + /* now update the list by writing what was linked to us to where we */ + /* were once at in the list */ + WriteReg (devc, ram_rtd_addr, data); + + /* update the devc->dst_index for this reroute */ + /* devc->dst_index[data[6:0]] = devc->dst_index[dst_addr]; */ + devc->dst_index[data & 0x7f] = devc->dst_index[dst_addr]; + + /* Invalidate the now deleted route. Data for dst_addr = 7e; */ + /* NOTE: the adbarb_monitor needs this write to track properly! */ + WriteReg (devc, ram_dst_addr, 0xfffffffe); + + /* if we are removing the tail, reset the tail pointer */ + if (devc->tail_index[sr] == dst_addr) + { + devc->tail_index[sr] = devc->dst_index[dst_addr]; + } + + /* clean up all data elements used to track this dst_addr */ + /* XXX check field size below */ + devc->dst_index[dst_addr] = 0x7f; /* ~('b0); */ +} + +static void +SetupRoutes (vortex_devc * devc) +{ + /* First add the record routes */ + add_route (devc, 17, codec_chan0_src_addr, fifo_chan2_dst_addr, 0); + add_route (devc, 17, codec_chan1_src_addr, fifo_chan3_dst_addr, 0); + add_route (devc, 17, codec_chan0_src_addr, fifo_chan2a_dst_addr, 0); + add_route (devc, 17, codec_chan1_src_addr, fifo_chan3a_dst_addr, 0); + + /* Now add the playback routes */ + add_route (devc, 17, fifo_chan0_src_addr, codec_chan0_dst_addr, 0); + add_route (devc, 17, fifo_chan0_src_addr, codec_chan1_dst_addr, 0); +} + +static void +EnableCodecChannel (vortex_devc * devc, unsigned char channel) +{ + unsigned int data; + + data = ReadReg (devc, channel_enable_reg_addr); + data = data | (1 << (8 + channel)); /*(1'b1 << (8+channel)); */ + WriteReg (devc, channel_enable_reg_addr, data); +} + +static void +DisableCodecChannel (vortex_devc * devc, unsigned char channel) +{ + unsigned int data; + + data = ReadReg (devc, channel_enable_reg_addr); + data = data & ~(1 << (8 + channel)); /*~(1'b1 << (8+channel)); */ + WriteReg (devc, channel_enable_reg_addr, data); +} + +static void +EnableAdbWtd (vortex_devc * devc, int sr) +{ + unsigned int dwData; + + dwData = ReadReg (devc, adbarb_sr_active_addr); + dwData |= (1 << sr); + WriteReg (devc, adbarb_sr_active_addr, dwData); + devc->sr_active |= (1 << sr); +} + +static void +DisableAdbWtd (vortex_devc * devc, int sr) +{ + unsigned int dwData; + + dwData = ReadReg (devc, adbarb_sr_active_addr); + dwData &= ~(1 << sr); + WriteReg (devc, adbarb_sr_active_addr, dwData); + devc->sr_active &= ~(1 << sr); +} + +/*ARGSUSED*/ +static int +vortex_midi_open (int dev, int mode, oss_midi_inputbyte_t inputbyte, + oss_midi_inputbuf_t inputbuf, + oss_midi_outputintr_t outputintr) +{ + vortex_devc *devc = (vortex_devc *) midi_devs[dev]->devc; + + if (devc->midi_opened) + { + return OSS_EBUSY; + } + + devc->midi_input_intr = inputbyte; + devc->midi_opened = mode; + + if (mode & OPEN_READ) + { + int tmp = ReadReg (devc, GIRQCTL); + WriteReg (devc, GIRQCTL, tmp | MIDIRQST); /* Enable MIDI interrupts */ + tmp = ReadReg (devc, GIRQCTL); + } + + WriteReg (devc, MIDICMD, 0x000000ff); /* Reset MIDI */ + WriteReg (devc, MIDICMD, 0x0000003f); /* Enter UART mode */ + if ((ReadReg (devc, MIDIDAT) & 0xff) != 0xfe) + cmn_err (CE_WARN, "Vortex warning! MIDI init not acknowledged\n"); + return 0; +} + +/*ARGSUSED*/ +static void +vortex_midi_close (int dev, int mode) +{ + vortex_devc *devc = (vortex_devc *) midi_devs[dev]->devc; + + int tmp = ReadReg (devc, GIRQCTL); + WriteReg (devc, GIRQCTL, tmp & ~MIDIRQST); /* Disable MIDI interrupts */ + WriteReg (devc, MIDICMD, 0x000000ff); /* Reset MIDI */ + + devc->midi_opened = 0; +} + +static int +vortex_midi_out (int dev, unsigned char midi_byte) +{ + int n = 10; + vortex_devc *devc = (vortex_devc *) midi_devs[dev]->devc; + + while ((ReadReg (devc, MIDISTAT) & CMDOK) && n--); + if (ReadReg (devc, MIDISTAT) & CMDOK) + return 0; + WriteReg (devc, MIDIDAT, midi_byte); + return 1; +} + +/*ARGSUSED*/ +static int +vortex_midi_ioctl (int dev, unsigned cmd, ioctl_arg arg) +{ + return OSS_EINVAL; +} + +static midi_driver_t vortex_midi_driver = { + vortex_midi_open, + vortex_midi_close, + vortex_midi_ioctl, + vortex_midi_out +}; + +static void +vortex_midi_init (vortex_devc * devc) +{ + /* Derive the MIDI baud rate from 49.152 MHz clock */ + WriteReg (devc, GAMECTL, 0x00006100); + WriteReg (devc, MIDICMD, 0x000000ff); /* Reset MIDI */ + WriteReg (devc, MIDICMD, 0x0000003f); /* Enter UART mode */ + + /* All commands should return 0xfe as an acknowledgement */ + if ((ReadReg (devc, MIDIDAT) & 0xff) != 0xfe) + cmn_err (CE_WARN, "Vortex warning! MIDI init not acknowledged\n"); + WriteReg (devc, MIDICMD, 0x000000ff); /* Reset MIDI */ +} + +/*********************************** + * Audio routines + ***********************************/ + +static int +vortex_set_rate (int dev, int arg) +{ + vortex_portc *portc = audio_engines[dev]->portc; + + if (arg == 0) + return portc->speed; + + if (audio_engines[dev]->flags & ADEV_FIXEDRATE) + arg = 48000; + + if (arg > 48000) + arg = 48000; + if (arg < 5000) + arg = 5000; + portc->speed = arg; + return portc->speed; +} + +static short +vortex_set_channels (int dev, short arg) +{ + vortex_portc *portc = audio_engines[dev]->portc; + + if (audio_engines[dev]->flags & ADEV_STEREOONLY) + arg = 2; + + if ((arg != 1) && (arg != 2)) + return portc->channels; + portc->channels = arg; + + return portc->channels; +} + +static unsigned int +vortex_set_format (int dev, unsigned int arg) +{ + vortex_portc *portc = audio_engines[dev]->portc; + + if (audio_engines[dev]->flags & ADEV_16BITONLY) + arg = 16; + + if (!(arg & (AFMT_U8 | AFMT_S16_LE))) + return portc->bits; + portc->bits = arg; + + return portc->bits; +} + +/*ARGSUSED*/ +static int +vortex_ioctl (int dev, unsigned int cmd, ioctl_arg arg) +{ + return OSS_EINVAL; +} + +#ifdef USE_SRC +static void cleanup_src (int dev); +#endif + +static void vortex_trigger (int dev, int state); + +static void +vortex_reset (int dev) +{ + vortex_trigger (dev, 0); + +#ifdef USE_SRC + cleanup_src (dev); + del_route (devc, src_chan0_dst_addr, 0); + del_route (devc, src_chan1_dst_addr, 0); +#endif +} + +static void +vortex_reset_input (int dev) +{ + vortex_portc *portc = audio_engines[dev]->portc; + vortex_trigger (dev, portc->trigger_bits & ~PCM_ENABLE_INPUT); +} + +static void +vortex_reset_output (int dev) +{ + vortex_portc *portc = audio_engines[dev]->portc; + vortex_trigger (dev, portc->trigger_bits & ~PCM_ENABLE_OUTPUT); +} + +/*ARGSUSED*/ +static int +vortex_open (int dev, int mode, int open_flags) +{ + oss_native_word flags; + vortex_portc *portc = audio_engines[dev]->portc; + vortex_devc *devc = audio_engines[dev]->devc; + + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); + if (portc->open_mode != 0) + { + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + return OSS_EBUSY; + } + + if (devc->open_mode & mode) + { + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + return OSS_EBUSY; + } + + devc->open_mode |= mode; + + portc->open_mode = mode; + portc->audio_enabled &= ~mode; + + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + + return 0; +} + +static void +vortex_close (int dev, int mode) +{ + vortex_portc *portc = audio_engines[dev]->portc; + vortex_devc *devc = audio_engines[dev]->devc; + + vortex_reset (dev); + portc->open_mode = 0; + devc->open_mode &= ~mode; + portc->audio_enabled &= ~mode; +} + +/* + * InitFifos + */ +static void +init_fifos (vortex_devc * devc) +{ + int i; + + /* Zero Out the FIFO Pointers */ + for (i = 0; i < 48; i++) + { + WriteReg (devc, fifo_base + 0x1800 + (4 * i), 0x00000020); + } + for (i = 2; i < 6; i++) + { + WriteReg (devc, fifo_base + 0x1800 + (4 * i), 0x00000000); + } + WriteReg (devc, fifo_base + 0x18c0, 0x00000843); + /* Clear out FIFO data */ + for (i = 0; i < 4; i++) + ClearDataFifo (devc, i); + + /* Set up the DMA engine to grab DMA memory */ + WriteReg (devc, dma_base + 0x61c, 0); /* Clear Dma Status0 */ + WriteReg (devc, dma_base + 0x620, 0); /* Clear Dma Status1 */ + WriteReg (devc, dma_base + 0x624, 0); /* Clear Dma Status2 */ +} + +#ifdef USE_SRC +static void +setup_src (int dev) +{ + vortex_portc *portc = audio_engines[dev]->portc; + vortex_devc *devc = audio_engines[dev]->devc; + + int i, j, chn; + + for (j = 0; j < 2; j++) + { + unsigned int tmp, ratio, link; + chn = portc->voice_chn + j; + + for (i = 0; i < 128; i += 4) + WriteReg (devc, src_input_fifo + (128 * chn) + i, 0); + for (i = 0; i < 8; i += 4) + WriteReg (devc, src_output_double_buffer + (chn * 8) + i, 0); + + ratio = 48000 / portc->speed; + tmp = 0; + tmp |= chn & 0xf; /* Correlated channel */ + if (ratio > 4) + tmp |= ((17 - ratio - 1) << 4); + else + tmp |= (12 << 4); /* Zero crossing */ + WriteReg (devc, src_channel_params + 0xe00 + 4 * chn, tmp); /* [0] */ + + ratio = (48000 << 14) / portc->speed; + WriteReg (devc, src_channel_params + 0xe40 * 4 * chn, ratio); /* [1] */ + + WriteReg (devc, src_channel_params + 0xe80 + 4 * chn, 0); /* [2] */ + WriteReg (devc, src_channel_params + 0xec0 + 4 * chn, 0); /* [3] */ + WriteReg (devc, src_channel_params + 0xf00 + 4 * chn, 0); /* [4] */ + WriteReg (devc, src_channel_params + 0xf40 + 4 * chn, 1); /* [5] */ + + ratio = 48000 / portc->speed; + tmp = 0x3000f; /* Throttle in, FIFO depth=15 */ + WriteReg (devc, src_channel_params + 0xf80 + 4 * chn, tmp); /* [6] */ + + link = ReadReg (devc, src_sr_header + 0); + WriteReg (devc, src_next_channel + chn * 4, link); + WriteReg (devc, src_sr_header + 0, 0x10 | chn); + + link = ReadReg (devc, src_throttle_source); + link |= (1 << chn); + WriteReg (devc, src_throttle_source, link); + + link = ReadReg (devc, src_active_sample_rate); + link |= (1 << 0); + WriteReg (devc, src_active_sample_rate, link); + + } +} + +static void +cleanup_src (int dev) +{ + vortex_portc *portc = audio_engines[dev]->portc; + vortex_devc *devc = audio_engines[dev]->devc; + + int i, j, chn; + + for (j = 0; j < 2; j++) + { + chn = portc->voice_chn + j; + + for (i = 0; i < 128; i += 4) + WriteReg (devc, src_input_fifo + (128 * chn) + i, 0); + for (i = 0; i < 8; i += 4) + WriteReg (devc, src_output_double_buffer + (chn * 8) + i, 0); + WriteReg (devc, src_next_channel + chn * 4, 0); + WriteReg (devc, src_sr_header + 0, 0); + + WriteReg (devc, src_active_sample_rate, 0); + + } +} +#endif + +/*ARGSUSED*/ +static void +vortex_output_block (int dev, oss_native_word buf, int count, int fragsize, + int intrflag) +{ + vortex_portc *portc = audio_engines[dev]->portc; + + portc->audio_enabled |= PCM_ENABLE_OUTPUT; + portc->trigger_bits &= ~PCM_ENABLE_OUTPUT; +} + +/*ARGSUSED*/ +static void +vortex_start_input (int dev, oss_native_word buf, int count, int fragsize, + int intrflag) +{ + vortex_portc *portc = audio_engines[dev]->portc; + + portc->audio_enabled |= PCM_ENABLE_INPUT; + portc->trigger_bits &= ~PCM_ENABLE_INPUT; +} + +static void +vortex_trigger (int dev, int state) +{ + vortex_devc *devc = audio_engines[dev]->devc; + vortex_portc *portc = audio_engines[dev]->portc; + unsigned int fifo_mode; + oss_native_word flags; + + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); + + if (portc->open_mode & OPEN_WRITE) + { + if (state & PCM_ENABLE_OUTPUT) + { + if ((portc->audio_enabled & PCM_ENABLE_OUTPUT) && + !(portc->trigger_bits & PCM_ENABLE_OUTPUT)) + { + /* Start the FIFOs */ + fifo_mode = 0x30030; + if (portc->channels == 2) + { + fifo_mode |= 0x00000002; + WriteReg (devc, fifo_base + 0x1800, fifo_mode); /* Left Pb */ + } + else + { + WriteReg (devc, fifo_base + 0x1800, fifo_mode); /* Left Pb */ + WriteReg (devc, fifo_base + 0x1804, fifo_mode); /* Right Pb */ + } + + WriteReg (devc, CODSMPLTMR, 0x1000); /* start timer */ + portc->trigger_bits |= PCM_ENABLE_OUTPUT; + } + } + else + { + if ((portc->audio_enabled & PCM_ENABLE_OUTPUT) && + (portc->trigger_bits & PCM_ENABLE_OUTPUT)) + { + portc->trigger_bits &= ~PCM_ENABLE_OUTPUT; + portc->audio_enabled &= ~PCM_ENABLE_OUTPUT; + + WriteReg (devc, CODSMPLTMR, 0x0); /* stop timer */ + WriteReg (devc, fifo_base + 0x1800, 0); /* Left Playback */ + WriteReg (devc, fifo_base + 0x1804, 0); /* Right Playback */ + + ClearDataFifo (devc, 0); + ClearDataFifo (devc, 1); + } + } + } + if (portc->open_mode & OPEN_READ) + { + if (state & PCM_ENABLE_INPUT) + { + if ((portc->audio_enabled & PCM_ENABLE_INPUT) && + !(portc->trigger_bits & PCM_ENABLE_INPUT)) + { + /* Start the FIFOs */ + fifo_mode = 0x30010; + if (portc->channels == 2) + fifo_mode |= 0x00000002; + WriteReg (devc, fifo_base + 0x1808, fifo_mode); /* Left Rec */ + WriteReg (devc, fifo_base + 0x180c, fifo_mode); /* Right Rec */ + WriteReg (devc, CODSMPLTMR, 0x1000); /* start timer */ + portc->trigger_bits |= PCM_ENABLE_INPUT; + } + } + else + { + if ((portc->audio_enabled & PCM_ENABLE_INPUT) && + (portc->trigger_bits & PCM_ENABLE_INPUT)) + { + portc->trigger_bits &= ~PCM_ENABLE_INPUT; + portc->audio_enabled &= ~PCM_ENABLE_INPUT; + + WriteReg (devc, CODSMPLTMR, 0x0); /* stop timer */ + + WriteReg (devc, fifo_base + 0x1808, 0); /* Left Record */ + WriteReg (devc, fifo_base + 0x180c, 0); /* Right Record */ + + ClearDataFifo (devc, 2); + ClearDataFifo (devc, 3); + } + } + } + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); +} + +/*ARGSUSED*/ +static int +vortex_prepare_for_input (int dev, int bsize, int bcount) +{ + unsigned int nBufSize, ChSizeGotoReg0, ChSizeGotoReg1, ch_mode; + dmap_t *dmap = audio_engines[dev]->dmap_in; + vortex_devc *devc = audio_engines[dev]->devc; + vortex_portc *portc = audio_engines[dev]->portc; + oss_native_word flags; + int SAMPLES = 1024; + + + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); + +#ifdef USE_SRC + setup_src (dev); + add_route (devc, 17, src_chan0_src_addr, codec_chan0_dst_addr, 0); + add_route (devc, 17, src_chan1_src_addr, codec_chan1_dst_addr, 0); + + add_route (devc, 0, fifo_chan0_src_addr, src_chan0_dst_addr, 0); + if (portc->channels == 2) + add_route (devc, 0, fifo_chan0_src_addr, src_chan1_dst_addr, 0); + else + add_route (devc, 0, fifo_chan1_src_addr, src_chan1_dst_addr, 0); +#endif + + nBufSize = (SAMPLES * 2 * 2) - 1; + + ch_mode = 0x00001000; + + switch (portc->bits) + { + case AFMT_U8: + ch_mode |= 0x00004000; + break; + + case AFMT_S16_LE: + ch_mode |= 0x00020000; + break; + + case AFMT_MU_LAW: + ch_mode |= 0x00008000; + break; + + case AFMT_A_LAW: + ch_mode |= 0x0000c000; + break; + + } + + /* Left Record Channel VDB Chan 2 */ + WriteReg (devc, dma_base + 0x220, dmap->dmabuf_phys); /* Set Chan0 Address */ + WriteReg (devc, dma_base + 0x224, dmap->dmabuf_phys + 4096); /* Set Chan0 Address */ + WriteReg (devc, dma_base + 0x228, dmap->dmabuf_phys + 2 * 4096); /* Set Chan0 Address */ + WriteReg (devc, dma_base + 0x22c, dmap->dmabuf_phys + 3 * 4096); /* Set Chan0 Address */ + + ChSizeGotoReg0 = (0xde000000) | (nBufSize << 12) | (nBufSize); + ChSizeGotoReg1 = (0xfc000000) | (nBufSize << 12) | (nBufSize); + WriteReg (devc, dma_base + 0x410, ChSizeGotoReg0); /* Set Chan0 Size to SAMPLES*2*2, Loop over 0 */ + WriteReg (devc, dma_base + 0x414, ChSizeGotoReg1); /* Set Chan0 Size to SAMPLES*2*2, Loop over 0 */ + WriteReg (devc, dma_base + 0x588, ch_mode); /* Set Chan0 Mode */ + + /* Right Record Channel VDB Chan 3 */ + WriteReg (devc, dma_base + 0x230, dmap->dmabuf_phys); /* Set Chan1 Address */ + WriteReg (devc, dma_base + 0x234, dmap->dmabuf_phys + 4096); /* Set Chan0 Address */ + WriteReg (devc, dma_base + 0x238, dmap->dmabuf_phys + 2 * 4096); /* Set Chan0 Address */ + WriteReg (devc, dma_base + 0x23c, dmap->dmabuf_phys + 3 * 4096); /* Set Chan0 Address */ + + ChSizeGotoReg0 = (0x56000000) | (nBufSize << 12) | (nBufSize); + ChSizeGotoReg1 = (0x74000000) | (nBufSize << 12) | (nBufSize); + WriteReg (devc, dma_base + 0x418, ChSizeGotoReg0); + WriteReg (devc, dma_base + 0x41c, ChSizeGotoReg1); + WriteReg (devc, dma_base + 0x58c, ch_mode); /* Set Chan1 Mode */ + + portc->audio_enabled &= ~PCM_ENABLE_INPUT; + portc->trigger_bits &= ~PCM_ENABLE_INPUT; + + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + return 0; +} + +/*ARGSUSED*/ +static int +vortex_prepare_for_output (int dev, int bsize, int bcount) +{ + unsigned int nBufSize, ChSizeGotoReg0, ChSizeGotoReg1, ch_mode; + int SAMPLES = 1024; + dmap_t *dmap = audio_engines[dev]->dmap_out; + vortex_devc *devc = audio_engines[dev]->devc; + vortex_portc *portc = audio_engines[dev]->portc; + oss_native_word flags; + + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); + +#ifdef USE_SRC + setup_src (dev); + add_route (devc, 17, src_chan0_src_addr, codec_chan0_dst_addr, 0); + add_route (devc, 17, src_chan1_src_addr, codec_chan1_dst_addr, 0); + + add_route (devc, 0, fifo_chan0_src_addr, src_chan0_dst_addr, 0); + if (portc->channels == 2) + add_route (devc, 0, fifo_chan0_src_addr, src_chan1_dst_addr, 0); + else + add_route (devc, 0, fifo_chan1_src_addr, src_chan1_dst_addr, 0); +#endif + + nBufSize = (SAMPLES * 2 * 2) - 1; + + ch_mode = 0x00003000; + + switch (portc->bits) + { + case AFMT_U8: + ch_mode |= 0x00004000; + break; + + case AFMT_S16_LE: + ch_mode |= 0x00020000; + break; + + case AFMT_MU_LAW: + ch_mode |= 0x00008000; + break; + + case AFMT_A_LAW: + ch_mode |= 0x0000c000; + break; + + } + + /* Left Playback Channel VDB Chan 0 */ + WriteReg (devc, dma_base + 0x200, dmap->dmabuf_phys); /* Set Chan0 Address */ + WriteReg (devc, dma_base + 0x204, dmap->dmabuf_phys + 4096); /* Set Chan0 Address */ + WriteReg (devc, dma_base + 0x208, dmap->dmabuf_phys + 2 * 4096); /* Set Chan0 Address */ + WriteReg (devc, dma_base + 0x20c, dmap->dmabuf_phys + 3 * 4096); /* Set Chan0 Address */ + + ChSizeGotoReg0 = (0xde000000) | (nBufSize << 12) | (nBufSize); + ChSizeGotoReg1 = (0xfc000000) | (nBufSize << 12) | (nBufSize); + WriteReg (devc, dma_base + 0x400, ChSizeGotoReg0); /* Set Chan0 Size to SAMPLES*2*2, Loop over 0 */ + WriteReg (devc, dma_base + 0x404, ChSizeGotoReg1); /* Set Chan0 Size to SAMPLES*2*2, Loop over 0 */ + WriteReg (devc, dma_base + 0x580, ch_mode); /* Set Chan0 Mode */ + + /* Right Playback Channel VDB Chan 1 */ + WriteReg (devc, dma_base + 0x210, dmap->dmabuf_phys); /* Set Chan1 Address */ + WriteReg (devc, dma_base + 0x214, dmap->dmabuf_phys + 4096); /* Set Chan1 Address */ + WriteReg (devc, dma_base + 0x218, dmap->dmabuf_phys + 2 * 4096); /* Set Chan1 Address */ + WriteReg (devc, dma_base + 0x21c, dmap->dmabuf_phys + 3 * 4096); /* Set Chan1 Address */ + + ChSizeGotoReg0 = (0x56000000) | (nBufSize << 12) | (nBufSize); + ChSizeGotoReg1 = (0x74000000) | (nBufSize << 12) | (nBufSize); + WriteReg (devc, dma_base + 0x408, ChSizeGotoReg0); + WriteReg (devc, dma_base + 0x40c, ChSizeGotoReg1); + + WriteReg (devc, dma_base + 0x584, ch_mode); /* Set Chan1 Mode */ + + portc->audio_enabled &= ~PCM_ENABLE_OUTPUT; + portc->trigger_bits &= ~PCM_ENABLE_OUTPUT; + + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + return 0; +} + +/*ARGSUSED*/ +static int +vortex_free_buffer (int dev, dmap_t * dmap, int direction) +{ + vortex_devc *devc = audio_engines[dev]->devc; + + if (dmap->dmabuf == NULL) + return 0; +#if 1 + CONTIG_FREE (devc->osdev, dmap->dmabuf, dmap->buffsize, TODO); +#ifdef linux + oss_unreserve_pages ((oss_native_word) dmap->dmabuf, + (oss_native_word) dmap->dmabuf + 4 * 4096 - 1); +#endif +#else + dmap->buffsize += 4096; /* Return the stolen page back */ + oss_free_dmabuf (dev, dmap); +#endif + + dmap->dmabuf = NULL; + return 0; +} + +/*ARGSUSED*/ +static int +vortex_alloc_buffer (int dev, dmap_t * dmap, int direction) +{ + vortex_devc *devc = audio_engines[dev]->devc; + oss_native_word phaddr; + + if (dmap->dmabuf != NULL) + return 0; +#if 1 + dmap->buffsize = 4 * 4096; /* 4 subbuffers */ + dmap->dmabuf = + CONTIG_MALLOC (devc->osdev, dmap->buffsize, MEMLIMIT_32BITS, &phaddr, TODO); + dmap->dmabuf_phys = phaddr; +#ifdef linux + oss_reserve_pages ((oss_native_word) dmap->dmabuf, + (oss_native_word) dmap->dmabuf + 4 * 4096 - 1); +#endif +#else + if ((err = oss_alloc_dmabuf (dev, dmap, direction)) < 0) + return err; + + /* Reserve the last page for internal use (channel buffers) */ + p = dmap->buffsize - 4096; + dmap->buffsize = p; + + if (dmap->buffsize < (4 * 1024)) + { + cmn_err (CE_WARN, "Allocated DMA buffer smaller than 8k\n"); + vortex_free_buffer (dev, dmap, direction); + return OSS_ENOSPC; + } +#endif + + return 0; +} + +/*ARGSUSED*/ +static int +vortex_get_buffer_pointer (int dev, dmap_t * dmap, int direction) +{ + vortex_devc *devc = audio_engines[dev]->devc; + oss_native_word flags, dmastat = 0; + int ptr = 0; + + MUTEX_ENTER_IRQDISABLE (devc->low_mutex, flags); + if (direction == PCM_ENABLE_OUTPUT) + { + dmastat = ReadReg (devc, dma_base + 0x5c0); + } + if (direction == PCM_ENABLE_INPUT) + { + dmastat = ReadReg (devc, dma_base + 0x5c8); + } + ptr = ((dmastat >> 12) & 0x03) * 4096 + (dmastat & 4095); + MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags); + return ptr; +} + +static audiodrv_t vortex_driver = { + vortex_open, + vortex_close, + vortex_output_block, + vortex_start_input, + vortex_ioctl, + vortex_prepare_for_input, + vortex_prepare_for_output, + vortex_reset, + NULL, + NULL, + vortex_reset_input, + vortex_reset_output, + vortex_trigger, + vortex_set_rate, + vortex_set_format, + vortex_set_channels, + NULL, + NULL, + NULL, /* vortex_check_input, */ + NULL, /* vortex_check_output, */ + vortex_alloc_buffer, + vortex_free_buffer, + NULL, + NULL, + vortex_get_buffer_pointer +}; + +static void +attach_channel (vortex_devc * devc, int my_mixer) +{ + int adev, i; + int first_dev = 0; + + for (i = 0; i < MAX_PORTC; i++) + { + char tmp_name[100]; + vortex_portc *portc = &devc->portc[i]; + int caps = + ADEV_FIXEDRATE | ADEV_AUTOMODE | ADEV_STEREOONLY | ADEV_16BITONLY; + + if (i == 0) + { + sprintf (tmp_name, "Aureal Vortex (%s)", devc->name); + caps |= ADEV_DUPLEX; + } + else + { + sprintf (tmp_name, "Aureal Vortex (%s) (shadow)", devc->name); + caps |= ADEV_DUPLEX | ADEV_SHADOW; + } + if ((adev = oss_install_audiodev (OSS_AUDIO_DRIVER_VERSION, + devc->osdev, + devc->osdev, + tmp_name, + &vortex_driver, + sizeof (audiodrv_t), + caps, + AFMT_U8 | AFMT_S16_LE, devc, -1)) < 0) + { + adev = -1; + return; + } + else + { + if (i == 0) + first_dev = adev; + audio_engines[adev]->portc = portc; + audio_engines[adev]->vmix_flags = VMIX_MULTIFRAG; + audio_engines[adev]->rate_source = first_dev; + audio_engines[adev]->fixed_rate = 48000; + audio_engines[adev]->min_rate = 48000; + audio_engines[adev]->max_rate = 48000; +#if 0 + audio_engines[adev]->min_block = 4096; + audio_engines[adev]->max_block = 4096; +#endif + audio_engines[adev]->mixer_dev = my_mixer; + portc->voice_chn = 0; + portc->open_mode = 0; + portc->audiodev = adev; + portc->audio_enabled = 0; +#ifdef CONFIG_OSS_VMIX + if (i == 0) + vmix_attach_audiodev(devc->osdev, adev, -1, 0); +#endif + } + } + return; +} + +#ifdef USE_SRC +static void +init_src (vortex_devc * devc) +{ + int i; + + for (i = 0; i < 0x800; i += 4) + WriteReg (devc, src_input_fifo + i, 0); + for (i = 0; i < 0x080; i += 4) + WriteReg (devc, src_output_double_buffer + i, 0); + for (i = 0; i < 0x040; i += 4) + WriteReg (devc, src_next_channel + i, 0); + for (i = 0; i < 0x054; i += 4) + WriteReg (devc, src_sr_header + i, 0); + + WriteReg (devc, src_active_sample_rate, 0); + WriteReg (devc, src_throttle_source, 0); + WriteReg (devc, src_throttle_count_size, 511); + + for (i = 0; i < 0x1bf; i += 4) + WriteReg (devc, src_channel_params + i, 0); +} +#endif + +int init_vortex2 (vortex_devc * devc, int is_mx300); +int vortex2intr (oss_device_t * osdev); + +static int +init_vortex (vortex_devc * devc) +{ + int my_mixer; + int i; + +/* + * Reset Vortex + */ + WriteReg (devc, GCTL, 0xffffffff); + oss_udelay (1000); + + InitCodec (devc); + SetupCodec (devc); + InitAdb (devc); + EnableCodecChannel (devc, 0); + EnableCodecChannel (devc, 1); + init_fifos (devc); + EnableAdbWtd (devc, 17); + SetupRoutes (devc); +#ifdef USE_SRC + init_src (devc); +#endif + + /* + * DMA controller memory is supposed to contain 0xdeadbeef after + * reset. + */ + if (ReadReg (devc, 0x10000 + 0x7c0) != 0xdeadbeef) + cmn_err (CE_WARN, + "DMA memory check returned unexpected result %08x\n", + ReadReg (devc, 0x10000 + 0x7c0)); + + my_mixer = ac97_install (&devc->ac97devc, "AC97 Mixer", ac97_read, + ac97_write, devc, devc->osdev); + if (my_mixer >= 0) + devc->mixer_dev = my_mixer; + else + return 0; + + WriteReg (devc, GCTL, ReadReg (devc, GCTL) | GIRQEN); /* Enable IRQ */ + WriteReg (devc, CODSMPLTMR, 0x0); + WriteReg (devc, GIRQCTL, DMAENDIRQST | DMABERRST | TIMIRQST); + + for (i = 0; i < 2; i++) + devc->dst_routed[i] = 0; + + /* Turn on vortex serial interface outputs to codec */ + EnableCodecChannel (devc, 0); + EnableCodecChannel (devc, 1); + + /* Zero Out the FIFO Pointers */ + for (i = 0; i < 48; i++) + { + WriteReg (devc, fifo_base + 0x1800 + (4 * i), 0x00000020); + } + for (i = 2; i < 6; i++) + { + WriteReg (devc, fifo_base + 0x1800 + (4 * i), 0x00000000); + } + WriteReg (devc, fifo_base + 0x18c0, 0x00000843); + /* Clear out FIFO data */ + for (i = 0; i < 4; i++) + ClearDataFifo (devc, i); + + /* Set up the DMA engine to grab DMA memory */ + WriteReg (devc, dma_base + 0x61c, 0); /* Clear Dma Status0 */ + WriteReg (devc, dma_base + 0x620, 0); /* Clear Dma Status1 */ + WriteReg (devc, dma_base + 0x624, 0); /* Clear Dma Status2 */ + + attach_channel (devc, my_mixer); + + devc->midi_dev = oss_install_mididev (OSS_MIDI_DRIVER_VERSION, "VORTEX", + "Aureal Vortex UART", + &vortex_midi_driver, + sizeof (midi_driver_t), + /* &std_midi_synth, */ NULL, + 0, devc, devc->osdev); + devc->midi_opened = 0; + vortex_midi_init (devc); + + return 1; +} + +int +oss_vortex_attach (oss_device_t * osdev) +{ + unsigned char pci_irq_line, pci_revision /*, pci_latency */ ; + unsigned short pci_command, vendor, device; + unsigned short subsystemid, subvendor; + int is_mx300 = 0; + vortex_devc *devc; + + DDB (cmn_err (CE_WARN, "Entered Aureal Vortex probe routine\n")); + + oss_pci_byteswap (osdev, 1); + + pci_read_config_word (osdev, PCI_VENDOR_ID, &vendor); + pci_read_config_word (osdev, PCI_DEVICE_ID, &device); + + if (vendor != AUREAL_VENDOR_ID || (device != AUREAL_VORTEX && + device != AUREAL_VORTEX2)) + return 0; + + pci_read_config_word (osdev, PCI_COMMAND, &pci_command); + pci_read_config_byte (osdev, PCI_REVISION_ID, &pci_revision); + pci_read_config_irq (osdev, PCI_INTERRUPT_LINE, &pci_irq_line); + + pci_read_config_word (osdev, PCI_SUBSYSTEM_ID, &subsystemid); + pci_read_config_word (osdev, PCI_SUBSYSTEM_VENDOR_ID, &subvendor); + + if (pci_irq_line == 0) + { + cmn_err (CE_WARN, "IRQ not assigned by BIOS (%d).\n", pci_irq_line); + return 0; + } + + if ((devc = PMALLOC (osdev, sizeof (*devc))) == NULL) + { + cmn_err (CE_WARN, "Out of memory\n"); + return 0; + } + + devc->osdev = osdev; + osdev->devc = devc; + + pci_read_config_dword (osdev, PCI_MEM_BASE_ADDRESS_0, &devc->bar0addr); + + if (device == AUREAL_VORTEX2) + { + devc->name = "Aureal Vortex AU8830"; + devc->id = AUREAL_VORTEX2; + devc->bar0_size = 256 * 1024; + } + else + { + devc->name = "Aureal Vortex AU8820"; + devc->id = AUREAL_VORTEX; + devc->bar0_size = 128 * 1024; + } + + pci_command |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_command &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY); + pci_write_config_word (osdev, PCI_COMMAND, pci_command); + + if (subvendor == 0x1092 && subsystemid == 0x3001) + is_mx300 = 1; + + /* Prgram IORDY for VIA chipset failure */ + pci_write_config_byte (osdev, 0x40, 0xff); + + /* Map the shared memory area */ + devc->bar0virt = + (unsigned int *) MAP_PCI_MEM (devc->osdev, 0, devc->bar0addr, + devc->bar0_size); + devc->dwRegister = devc->bar0virt; + + /* Disable all interrupts */ + WriteReg (devc, GIRQCTL, 0x00000000); + + oss_register_device (osdev, devc->name); + + if (devc->id == AUREAL_VORTEX) + if (oss_register_interrupts (devc->osdev, 0, vortexintr, NULL) < 0) + { + cmn_err (CE_WARN, "Can't allocate IRQ%d\n", pci_irq_line); + return 0; + } + + if (devc->id == AUREAL_VORTEX2) + if (oss_register_interrupts (devc->osdev, 0, vortex2intr, NULL) < 0) + { + cmn_err (CE_WARN, "Can't allocate IRQ%d\n", pci_irq_line); + return 0; + } + + + MUTEX_INIT (devc->osdev, devc->mutex, MH_DRV); + MUTEX_INIT (devc->osdev, devc->low_mutex, MH_DRV + 1); + + if (devc->id == AUREAL_VORTEX2) + return init_vortex2 (devc, is_mx300); + else + return init_vortex (devc); /* Detected */ +} + + +extern void unload_vortex2 (oss_device_t * osdev); + +int +oss_vortex_detach (oss_device_t * osdev) +{ + vortex_devc *devc = (vortex_devc *) osdev->devc; + + if (oss_disable_device (osdev) < 0) + return 0; + + if (devc->id == AUREAL_VORTEX2) + unload_vortex2 (osdev); + else + { + DisableCodecChannel (devc, 0); + DisableCodecChannel (devc, 1); + DisableAdbWtd (devc, 17); + + /* Disable routes */ + del_route (devc, codec_chan0_dst_addr, 0); + del_route (devc, codec_chan1_dst_addr, 0); + del_route (devc, fifo_chan2_dst_addr, 0); + del_route (devc, fifo_chan3_dst_addr, 0); + del_route (devc, fifo_chan2a_dst_addr, 0); + del_route (devc, fifo_chan3a_dst_addr, 0); + + /* Disable all interrupts */ + WriteReg (devc, GIRQCTL, 0x00000000); + } + + oss_unregister_interrupts (devc->osdev); + + MUTEX_CLEANUP (devc->mutex); + MUTEX_CLEANUP (devc->low_mutex); + + UNMAP_PCI_MEM (devc->osdev, 0, devc->bar0addr, devc->bar0virt, + devc->bar0_size); + + oss_unregister_device (devc->osdev); + return 1; +} diff --git a/attic/drv/oss_vortex/oss_vortex.man b/attic/drv/oss_vortex/oss_vortex.man new file mode 100644 index 0000000..0715a15 --- /dev/null +++ b/attic/drv/oss_vortex/oss_vortex.man @@ -0,0 +1,21 @@ +NAME +oss_vortex - Aureal Vortex audio driver + +DESCRIPTION +Open Sound System driver for old Aureal Semiconductor AU8820 (Vortex1) and +AU8830 (Vortex2) audio controllers. + +Vortex device characteristics: + o 8/16 bit playback/record + o mono/stereo playback/recording + o 8KHz to 48Khz sample rate. + +OPTIONS +None + +FILES +CONFIGFILEPATH/oss_vortex.conf Device configuration file + +AUTHOR +4Front Technologies + diff --git a/attic/drv/oss_vortex/oss_vortex2.c b/attic/drv/oss_vortex/oss_vortex2.c new file mode 100644 index 0000000..b0ceffe --- /dev/null +++ b/attic/drv/oss_vortex/oss_vortex2.c @@ -0,0 +1,1756 @@ +/* + * Purpose: Driver for Aureal Semiconductor Vortex 2 PCI audio controller. + */ +/* + * + * This file is part of Open Sound System. + * + * Copyright (C) 4Front Technologies 1996-2008. + * + * This this source file is released under GPL v2 license (no other versions). + * See the COPYING file included in the main directory of this source + * distribution for the license terms and conditions. + * + */ + +#include "vortex.h" + +#undef USE_SRC +#undef USE_SPDIF + +#define AUREAL_VENDOR_ID 0x12eb +#define AUREAL_VORTEX2 0x0002 + +# define ISR (devc->global_base+0x0) +# define CODIRQST 0x00008000 +# define MODIRQST 0x00004000 +# define MIDIRQST 0x00002000 +# define TIMIRQST 0x00001000 +# define COIRQLST 0x00000800 +# define COIRQPST 0x00000400 +# define FRCIRQST 0x00000200 +# define SBIRQST 0x00000100 +# define SBMIRQST 0x00000080 +# define FMIRQST 0x00000040 +# define DMAENDIRQST 0x00000020 +# define DMABERRST 0x00000010 +# define FIFOERRST 0x00000008 +# define REGERRST 0x00000004 +# define MPARERRST 0x00000002 +# define MFATERRST 0x00000001 +# define ICR devc->global_base+0x4 +# define GSR devc->global_base+0x8 +# define GCR devc->global_base+0xc +# define SFTRST 0x00800000 +# define ARBRST 0x00400000 +# define EXTRST 0x00200000 +# define RBTOEN 0x00100000 +# define AINCEN 0x00080000 +# define TTXFLUSH 0x00040000 +# define TRVFLUSH 0x00020000 +# define MFIFOFLUSH 0x00010000 +# define FRCIRQ 0x00008000 +# define GIRQEN 0x00004000 +# define MIDIDAT devc->midi_base+0x0 +# define MIDICMD devc->midi_base+0x4 +# define MIDISTAT MIDICMD +# define MIDIVAL 0x00000080 +# define CMDOK 0x00000040 +# define MPUMODE 0x00000001 +# define GAMECTL devc->midi_base+0xc +# define JOYMODE 0x00000040 +# define MIDITXFULL 0x00000008 +# define MIDIRXINIT 0x00000004 +# define MIDIRXOVFL 0x00000002 +# define MIDIDATVAL 0x00000001 + +#define adb_destinations 173 +# define CODSMPLTMR (devc->serial_block_base+0x19c) +#define adbarb_base devc->adbarb_block_base +#define adbarb_wtdram_base_addr (devc->adbarb_block_base + 0x000) +#define adbarb_wtdram_srhdr_base_addr (devc->adbarb_block_base + (adb_destinations * 4)) +#define adbarb_sr_active_addr (devc->adbarb_block_base + 0x400) + +#define codec_control_reg_addr (devc->serial_block_base + 0x184) +#define cmd_status_reg_addr (devc->serial_block_base + 0x188) +#define channel_enable_reg_addr (devc->serial_block_base + 0x190) +#define serial_ram_reg_addr (devc->serial_block_base + 0x00) + +#define spdif_ctrl_reg (devc->serial_block_base + 0x0194) /* offset for spdif control register */ +#define codec_sample_counter (devc->serial_block_base + 0x0198) /* offset for spdif control register */ +#define spdif_cfg_dword 0x86 /* enable port, enable CRC, set clock toinput (48kHz) */ +#define spdif_ch_status_reg0 0x0 /* Set to consumer, digital audio, */ +#define spdif_ch_status_reg_base (devc->serial_block_base + 0x1D0) /* Set to the first address location */ + +#define fifo_chan0_src_addr 0x00 +#define fifo_chan1_src_addr 0x01 +#define fifo_chan6_src_addr 0x06 +#define fifo_chan7_src_addr 0x07 +#define fifo_chan8_src_addr 0x08 +#define fifo_chan9_src_addr 0x09 +#define fifo_chan2_dst_addr 0x02 +#define fifo_chan2a_dst_addr 0x022 +#define fifo_chan3_dst_addr 0x03 +#define fifo_chan3a_dst_addr 0x023 +#define fifo_chan4_dst_addr 0x04 +#define fifo_chan5_dst_addr 0x05 +#define fifo_chan6_dst_addr 0x06 +#define fifo_chan7_dst_addr 0x07 +#define fifo_chan8_dst_addr 0x08 +#define fifo_chan9_dst_addr 0x09 +#define fifo_chana_dst_addr 0x0a +#define fifo_chanb_dst_addr 0x0b + +#define codec_chan0_src_addr 0x70 +#define codec_chan1_src_addr 0x71 +#define codec_chan0_dst_addr 0x88 +#define codec_chan1_dst_addr 0x89 +#define codec_chan4_dst_addr 0x8c +#define codec_chan5_dst_addr 0x8d + +#define spdif_chan0_dst_addr 0x92 +#define spdif_chan1_dst_addr 0x93 + +#define src_chan0_dst_addr 0x40 +#define src_chan1_dst_addr 0x41 +#define src_chan0_src_addr 0x20 +#define src_chan1_src_addr 0x21 + +#define src_base_offset (devc->src_base) +#define src_input_fifo_base (devc->src_base + 0x000) +#define src_output_fifo_base (devc->src_base + 0x800) +#define src_next_ch_base (devc->src_base + 0xc00) +#define src_sr_header_base (devc->src_base + 0xc40) +#define src_active_sample_rate (devc->src_base + 0xcc0) +#define src_throttle_source (devc->src_base + 0xcc4) +#define src_throttle_count_size (devc->src_base + 0xcc8) +#define src_ch_params_base (devc->src_base + 0xe00) +#define src_ch_param0 (devc->src_base + 0xe00) +#define src_ch_param1 (devc->src_base + 0xe40) +#define src_ch_param2 (devc->src_base + 0xe80) +#define src_ch_param3 (devc->src_base + 0xec0) +#define src_ch_param4 (devc->src_base + 0xf00) +#define src_ch_param5 (devc->src_base + 0xf40) +#define src_ch_param6 (devc->src_base + 0xf80) + +#define pif_gpio_control (devc->parallel_base + 0x05c) + +/************************************************************ + * Vortex2 Routines * + ************************************************************/ + + +static unsigned int +V2ReadReg (vortex_devc * devc, oss_native_word addr) +{ + return READL (addr); +} + +static void +V2WriteReg (vortex_devc * devc, oss_native_word addr, oss_native_word data) +{ + WRITEL (addr, data); +} + +static void +V2ReadCodecRegister (vortex_devc * devc, int cIndex, int *pdwData) +{ + int dwCmdStRegAddr; + int dwCmdStRegData; + int nCnt = 0; + + dwCmdStRegAddr = cIndex << 16; + V2WriteReg (devc, cmd_status_reg_addr, dwCmdStRegAddr); + do + { + dwCmdStRegData = V2ReadReg (devc, cmd_status_reg_addr); + if (nCnt++ > 1) + oss_udelay (10); + } + while ((dwCmdStRegData & 0x00FF0000) != ((1 << 23) | (dwCmdStRegAddr)) + && (nCnt < 10)); + if (nCnt >= 50) + { + *pdwData = -1; + cmn_err (CE_WARN, "AC97 Timeout\n"); + } + else + *pdwData = dwCmdStRegData & 0x0000ffff; +} + +static void +V2WriteCodecCommand (vortex_devc * devc, int cIndex, int wData) +{ + int dwData; + int nCnt = 0; + + + do + { + dwData = V2ReadReg (devc, codec_control_reg_addr); + if (nCnt++ > 1) + oss_udelay (10); + } + while (!(dwData & 0x0100) && (nCnt < 50)); + if (nCnt >= 10) + cmn_err (CE_WARN, "AC97 write timeout.\n"); + + + do + { + dwData = V2ReadReg (devc, codec_control_reg_addr); + if (nCnt++ > 1) + oss_udelay (10); + } + while (!(dwData & 0x0100) && (nCnt < 100)); + if (nCnt >= 100) + cmn_err (CE_WARN, "AC97 timeout(2)\n"); + + dwData = (cIndex << 16) | (1 << 23) | wData; + V2WriteReg (devc, cmd_status_reg_addr, dwData); + oss_udelay (20); + /* Read it back to make sure it got there */ + do + { + dwData = V2ReadReg (devc, codec_control_reg_addr); + if (nCnt++ > 1) + oss_udelay (10); + } + while (!(dwData & 0x0100) && (nCnt < 100)); + if (nCnt >= 100) + cmn_err (CE_WARN, "AC97 timeout(3)\n"); + V2ReadCodecRegister (devc, cIndex, &dwData); + if (dwData != (int) wData) + { + do + { + dwData = V2ReadReg (devc, codec_control_reg_addr); + if (nCnt++ > 1) + oss_udelay (10); + } + while (!(dwData & 0x0100) && (nCnt < 10)); + if (nCnt >= 10) + cmn_err (CE_WARN, "AC97 Timeout(4).\n"); + dwData = (cIndex << 16) | (1 << 23) | wData; + V2WriteReg (devc, cmd_status_reg_addr, dwData); + do + { + dwData = V2ReadReg (devc, codec_control_reg_addr); + if (nCnt++ > 1) + oss_udelay (10); + } + while (!(dwData & 0x0100) && (nCnt < 100)); + if (nCnt >= 100) + cmn_err (CE_WARN, "AC97 timeout(5).\n"); +#if 0 + V2ReadCodecRegister (devc, cIndex, &dwData); + if (dwData != (int) wData) + { + cmn_err (CE_WARN, + "Vortex ERROR: Write to index %x failed (exp %04x, got %04x)\n", + cIndex, wData, dwData); + } +#endif + } +} + +static void +ClearDataFifo (vortex_devc * devc, int nChannel) +{ + int j; + + /* Clear out FIFO data */ + for (j = 0; j < 64; j++) + V2WriteReg (devc, + devc->fifo_base + 0x4000 + (0x100 * nChannel) + (0x4 * j), + 0x0); +} + +static void +cold_reset (vortex_devc * devc) +{ + int i, reg; + int bSigmatelCodec = 0; + + V2ReadCodecRegister (devc, 0x7c, ®); + if (reg == 0x8384) + { + DDB (cmn_err (CE_WARN, "Sigmatel codec detected\n")); + bSigmatelCodec = 1; + } + + for (i = 0; i < 32; i = i + 1) + { + V2WriteReg (devc, serial_ram_reg_addr + 0x80 + (i * 4), 0); + oss_udelay (10); + } + if (bSigmatelCodec) + { + /* Disable clock */ + V2WriteReg (devc, codec_control_reg_addr, 0x00a8); + oss_udelay (100); + /* Set Sync High */ + /* V2WriteReg(devc, codec_control_reg_addr, 0x40a8); */ + /* delay(100); */ + /* Place CODEC into reset */ + V2WriteReg (devc, codec_control_reg_addr, 0x80a8); + oss_udelay (100); + /* Give CODEC some Clocks with reset asserted */ + V2WriteReg (devc, codec_control_reg_addr, 0x80e8); + oss_udelay (100); + /* Turn off clocks */ + V2WriteReg (devc, codec_control_reg_addr, 0x80a8); + oss_udelay (100); + /* Take out of reset */ + /* V2WriteReg(devc, codec_control_reg_addr, 0x40a8); */ + /* oss_udelay(100); */ + /* Release reset */ + V2WriteReg (devc, codec_control_reg_addr, 0x00a8); + oss_udelay (100); + /* Turn on clocks */ + V2WriteReg (devc, codec_control_reg_addr, 0x00e8); + oss_udelay (100); + } + else + { + V2WriteReg (devc, codec_control_reg_addr, 0x8068); + oss_udelay (10); + V2WriteReg (devc, codec_control_reg_addr, 0x00e8); + oss_udelay (10); + } +} + +static void +V2InitCodec (vortex_devc * devc) +{ + int i; + cold_reset (devc); + for (i = 0; i < 32; i = i + 1) + { + V2WriteReg (devc, serial_ram_reg_addr + 0x80 + (i * 4), 0); + oss_udelay (10); + } + + /* Set up the codec in AC97 mode */ + V2WriteReg (devc, codec_control_reg_addr, 0x00e8); + oss_udelay (10); + /* Clear the channel enable register */ + V2WriteReg (devc, channel_enable_reg_addr, 0); + + /* Set up Sigmatel STAC9708 Codec with initialization routine rev. 0.50 */ + + V2WriteCodecCommand (devc, 0x26, 0x800f); /* set EAPD to unmute */ + oss_udelay (10); + + V2WriteCodecCommand (devc, 0x76, 0xabba); + oss_udelay (10); /* Turn on secondary output DACs */ + V2WriteCodecCommand (devc, 0x78, 0x1000); + oss_udelay (10); + + V2WriteCodecCommand (devc, 0x70, 0xabba); + oss_udelay (10); /* Turn on extra current to reduce THD */ + V2WriteCodecCommand (devc, 0x72, 0x07); + oss_udelay (10); +} + +static void +V2SetupCodec (vortex_devc * devc) +{ + int dwData; + int count = 0; + int dwBit28 = 1 << 28; + + /* do the following only for ac97 codecs */ + /* Wait for Codec Ready (bit 28) */ + do + { + dwData = V2ReadReg (devc, codec_control_reg_addr); + if (count++ > 1) + oss_udelay (10); + } + while ((count < 100) && !(dwData & dwBit28)); + if (count >= 100) + { +#if 1 + cmn_err (CE_WARN, "Error: timeout waiting for Codec Ready bit.\n"); + cmn_err (CE_WARN, "Codec Interface Control Register is %08x\n", dwData); +#endif + } + /* Write interesting data to the Codec 97 Mixer registers */ + /* Master Volume 0dB Attunuation, Not muted. */ + V2WriteCodecCommand (devc, 0x02, 0x0a0a); + oss_udelay (10); + /* Master Volume mono muted. */ + V2WriteCodecCommand (devc, 0x06, 0x8000); + oss_udelay (10); + /* Mic Volume muted. */ + V2WriteCodecCommand (devc, 0x0e, 0x8000); + oss_udelay (10); + /* Line In Volume muted. */ + V2WriteCodecCommand (devc, 0x10, 0x8000); + oss_udelay (10); + /* CD Volume muted. */ + V2WriteCodecCommand (devc, 0x12, 0x8000); + oss_udelay (10); + /* Aux Volume muted. */ + V2WriteCodecCommand (devc, 0x16, 0x8000); + oss_udelay (10); + /* PCM out Volume 0 dB Gain, Not muted. */ + V2WriteCodecCommand (devc, 0x18, 0x0f0f); + oss_udelay (10); + /* Record select, select Mic for recording */ + V2WriteCodecCommand (devc, 0x1a, 0x0404); + oss_udelay (10); + /* Record Gain, 0dB */ + V2WriteCodecCommand (devc, 0x1c, 0x8000); + oss_udelay (10); + + /* Poll the Section Ready bits in the Status Register (index 0x26) */ + count = 0; + do + { + V2ReadCodecRegister (devc, 0x26, &dwData); + if (count++ > 1) + oss_udelay (10); + } + while (!(dwData & 0x02) && (count < 10)); + if (!(dwData & 0x02)) + cmn_err (CE_WARN, "DAC section ready bit is not set.\n"); + + /* Read and confirm the data in the Codec 97 Mixer registers. */ + /* just the PCM reg, as a sanity check */ + V2ReadCodecRegister (devc, 0x18, &dwData); + if ((dwData & 0x0000ffff) != 0xf0f) + { + cmn_err (CE_WARN, "PCM volume reg is %x, sb 0xf0f.\n", dwData); + } +} + +static void +V2InitAdb (vortex_devc * devc) +{ +/* parameter values for write_op */ +#define none 0 /* dst_op = x */ +#define tail 1 /* dst_op = x */ +#define add 2 /* dst_op = dst_addr being added */ +#define adds 3 /* dst_op = dst_addr being added */ +#define del 4 /* dst_op = dst_addr being deleted */ +#define dels 5 /* dst_op = dst_addr being deleted */ +#define inval 6 /* dst_op = x */ + + int i; + +#if 0 + unsigned char /*reg [3:0] */ write_op; + unsigned char /*reg [6:0] */ dst_op; + unsigned char /*reg [6:0] */ src_op; + unsigned char /*reg [SS:0] */ sr_op; +#endif + /* misc */ + + devc->sr_active = 0; + /* the initial tail for each list is the header location */ + for (i = 0; i <= 31; i = i + 1) + devc->tail_index[i] = adb_destinations + i; + for (i = 0; i <= 127; i = i + 1) + devc->dst_index[i] = 0x7f; /*~('b0); */ + for (i = 0; i <= 127; i = i + 1) + devc->sr_list[i] = 0x1f; /*~('b0); */ + +#if 0 + write_op = none; + dst_op = 0x7f; /* ~('b0); */ + src_op = 0x7f; /* ~('b0); */ + sr_op = 0x1f; /* ~('b0); */ +#endif + /* Disable any active sample rate */ + V2WriteReg (devc, adbarb_base + 0x400, 0); + /* Null out all the linked lists */ + for (i = 0; i < 0x1f0; i = i + 4) + { + V2WriteReg (devc, adbarb_base + i, 0xffffffff); + } +} + +#ifdef USE_SRC +static void +V2DisableSrc (vortex_devc * devc) +{ + V2WriteReg (devc, (oss_native_word) (src_active_sample_rate), (oss_native_word) (0x0)); /* activate 0 and 1 */ + return; +} + + +static void +V2EnableSrc (vortex_devc * devc) +{ + int i, j; + + for (i = 0; i < 16; i++) + { + V2WriteReg (devc, (unsigned long) (src_next_ch_base + (0x4 * i)), (unsigned long) (0x0)); /* clear next ch list */ + } + + for (i = 0; i < 22; i++) + { + V2WriteReg (devc, (unsigned long) (src_sr_header_base + (0x4 * i)), (unsigned long) (0x0)); /* Clear header list */ + } + + for (i = 0; i < 16; i++) + { + for (j = 0; j < 32; j++) + { + V2WriteReg (devc, (unsigned long) (src_input_fifo_base + (0x4 * ((0x20 * i) + j))), (unsigned long) (0xdeadbabe)); /* clear input fifo */ + } + } + + for (i = 0; i < 16; i++) + { + for (j = 0; j < 2; j++) + { + V2WriteReg (devc, (unsigned long) (src_output_fifo_base + (0x4 * ((0x2 * i) + j))), (unsigned long) (0x5555aaaa)); /* clear input fifo */ + } + } + + for (i = 0; i < 16; i++) + { + V2WriteReg (devc, (unsigned long) (src_ch_params_base + (0x04 * i)), (unsigned long) (0xc0)); /* samples per wing */ + V2WriteReg (devc, (unsigned long) (src_ch_params_base + (0x04 * (0x10 + i))), (unsigned long) (0x45a9)); /* conversion ratio */ + V2WriteReg (devc, (unsigned long) (src_ch_params_base + (0x04 * (0x20 + i))), (unsigned long) (0x0)); /* Drift error = 0 */ + V2WriteReg (devc, (unsigned long) (src_ch_params_base + (0x04 * (0x30 + i))), (unsigned long) (0x0)); /* Drift error = 0 */ + V2WriteReg (devc, (unsigned long) (src_ch_params_base + (0x04 * (0x40 + i))), (unsigned long) (0x0)); /* fraction = 0 */ + V2WriteReg (devc, (unsigned long) (src_ch_params_base + (0x04 * (0x50 + i))), (unsigned long) (0x1)); /* drift out count = 1 */ + V2WriteReg (devc, (unsigned long) (src_ch_params_base + (0x04 * (0x60 + i))), (unsigned long) (0x30f00)); /* conversion ratio */ + } + + + V2WriteReg (devc, (unsigned long) (src_next_ch_base), (unsigned long) (0x1)); /* point to SRC1 as last in list */ + V2WriteReg (devc, (unsigned long) (src_sr_header_base + (0x04 * 20)), (unsigned long) (0x10)); /* Using spdif sr (20) point to ch 0 */ + V2WriteReg (devc, (unsigned long) (src_ch_params_base), (unsigned long) (0xc0)); /* samples per wing */ + V2WriteReg (devc, (unsigned long) (src_ch_params_base + (0x04)), (unsigned long) (0xc1)); /* samples per wing */ + V2WriteReg (devc, (unsigned long) (src_ch_params_base + (0x04 * 0x10)), (unsigned long) (0x45a9)); /* conversion ratio */ + V2WriteReg (devc, (unsigned long) (src_ch_params_base + (0x04 * 0x11)), (unsigned long) (0x45a9)); /* conversion ratio */ + V2WriteReg (devc, (unsigned long) (src_ch_params_base + (0x04 * 0x20)), (unsigned long) (0x0)); /* Drift error = 0 */ + V2WriteReg (devc, (unsigned long) (src_ch_params_base + (0x04 * 0x21)), (unsigned long) (0x0)); /* Drift error = 0 */ + V2WriteReg (devc, (unsigned long) (src_ch_params_base + (0x04 * 0x30)), (unsigned long) (0x0)); /* Drift error = 0 */ + V2WriteReg (devc, (unsigned long) (src_ch_params_base + (0x04 * 0x31)), (unsigned long) (0x0)); /* Drift error = 0 */ + + V2WriteReg (devc, (unsigned long) (src_ch_params_base + (0x04 * 0x40)), (unsigned long) (0x0)); /* fraction = 0 */ + V2WriteReg (devc, (unsigned long) (src_ch_params_base + (0x04 * 0x41)), (unsigned long) (0x0)); /* fraction = 0 */ + V2WriteReg (devc, (unsigned long) (src_ch_params_base + (0x04 * 0x50)), (unsigned long) (0x1)); /* drift out count = 1 */ + V2WriteReg (devc, (unsigned long) (src_ch_params_base + (0x04 * 0x51)), (unsigned long) (0x1)); /* drift out count = 1 */ + V2WriteReg (devc, (unsigned long) (src_ch_params_base + (0x04 * 0x60)), (unsigned long) (0x30f00)); /* pointers, throttle in */ + V2WriteReg (devc, (unsigned long) (src_ch_params_base + (0x04 * 0x61)), (unsigned long) (0x30f00)); /* pointers, throttle in */ + V2WriteReg (devc, (unsigned long) (src_throttle_source), (unsigned long) (0x3)); /* choose counter for ch 0 & 1 */ + V2WriteReg (devc, (unsigned long) (src_throttle_count_size), (unsigned long) (0x1ff)); /* counter size = 511 */ + V2WriteReg (devc, (unsigned long) (src_active_sample_rate), (unsigned long) (0x100000)); /* activate sr 20 for codec */ + +} +#endif + +static void +SetBit (unsigned int owData[], int nBit, unsigned char cVal) +{ + if (cVal) + owData[nBit / 32] |= (1 << (nBit % 32)); + else + owData[nBit / 32] &= ~(1 << (nBit % 32)); +} + +/*ARGSUSED*/ +static int +add_route (vortex_devc * devc, unsigned int sr, + unsigned int src_addr, unsigned int dst_addr, int verify) +{ + + unsigned int ram_hdr_addr; + unsigned int ram_dst_addr; + unsigned int ram_tail_addr; + unsigned int sr_ram_index; + + sr_ram_index = adb_destinations + sr; + ram_hdr_addr = adbarb_wtdram_srhdr_base_addr + (sr * 4); /* VHRDxx[sr] */ + ram_dst_addr = adbarb_wtdram_base_addr + (dst_addr * 4); /* VDSTxx[dst_addr] */ + ram_tail_addr = adbarb_wtdram_base_addr + (devc->tail_index[sr] * 4); + + /* since always add to end of list, ram[dst_addr] will be the new tail. */ + /* and, since we could be adding to an active list, the tail needs */ + /* to be NULLed before the new link is inserted */ + /* (since we need to check the current tail next, devc->tail_index is */ + /* updated a bit later below.) */ + V2WriteReg (devc, ram_dst_addr, 0xffffffff); + + /* check if this sr has a list started yet */ + if (devc->tail_index[sr] == (adb_destinations + sr)) + { + /* current tail for this sample rate indicates that list is empty, */ + /* thus this route will be head of list */ + V2WriteReg (devc, ram_hdr_addr, ((src_addr << 8) | dst_addr)); + devc->dst_index[dst_addr] = sr_ram_index; + } + else + { + /* add to end of list */ + V2WriteReg (devc, ram_tail_addr, ((src_addr << 8) | dst_addr)); + devc->dst_index[dst_addr] = devc->tail_index[sr]; + } + + /* keep track of the new tail */ + devc->tail_index[sr] = dst_addr; + + /* keep track of which sample rate list this dst_addr now belongs to */ + devc->sr_list[dst_addr] = sr; + + /* mark dst_addr as routed */ + /* devc->dst_routed[dst_addr] = 1; */ + SetBit ((unsigned int *) &devc->dst_routed, dst_addr, 1); + + return 0; +} + +/*ARGSUSED*/ +static void +del_route (vortex_devc * devc, unsigned char dst_addr, int verify) +{ + + unsigned int data, ram_dst_addr, ram_rtd_addr; + unsigned char sr; + + + ram_dst_addr = adbarb_wtdram_base_addr + (dst_addr * 4); + ram_rtd_addr = adbarb_wtdram_base_addr + (devc->dst_index[dst_addr] * 4); + + /* get the sr list that this dst_addr belongs to */ + sr = devc->sr_list[dst_addr]; + + /* mark dst as no longer routed */ + SetBit ((unsigned int *) &devc->dst_routed, dst_addr, 0); + + /* remove the dst from the sr_list then check to see if this was the */ + /* last route in the list. if so, disable wtd for this sample rate */ + devc->sr_list[dst_addr] = 0x1f; /*~('b0); */ + + /* find out what's linked to us so we can reroute it. if we are the */ + /* tail, this will be NULL and will get relinked as such */ + data = V2ReadReg (devc, ram_dst_addr); + + /* now update the list by writing what was linked to us to where we */ + /* were once at in the list */ + V2WriteReg (devc, ram_rtd_addr, data); + + /* update the devc->dst_index for this reroute */ + /* devc->dst_index[data[6:0]] = devc->dst_index[dst_addr]; */ + devc->dst_index[data & 0x7f] = devc->dst_index[dst_addr]; + + /* Invalidate the now deleted route. Data for dst_addr = 7e; */ + /* NOTE: the adbarb_monitor needs this write to track properly! */ + V2WriteReg (devc, ram_dst_addr, 0xfffffffe); + + /* if we are removing the tail, reset the tail pointer */ + if (devc->tail_index[sr] == dst_addr) + { + devc->tail_index[sr] = devc->dst_index[dst_addr]; + } + + /* clean up all data elements used to track this dst_addr */ + /* XXX check field size below */ + devc->dst_index[dst_addr] = 0x7f; /* ~('b0); */ +} + +static void +EnableCodecChannel (vortex_devc * devc, unsigned char channel) +{ + unsigned int data; + + data = V2ReadReg (devc, channel_enable_reg_addr); + data = data | (1 << (8 + channel)); /*(1'b1 << (8+channel)); */ + V2WriteReg (devc, channel_enable_reg_addr, data); +} + +static void +DisableCodecChannel (vortex_devc * devc, unsigned char channel) +{ + unsigned int data; + + data = V2ReadReg (devc, channel_enable_reg_addr); + data = data & ~(1 << (8 + channel)); /*~(1'b1 << (8+channel)); */ + V2WriteReg (devc, channel_enable_reg_addr, data); +} + +static void +EnableAdbWtd (vortex_devc * devc, int sr) +{ + unsigned int dwData; + + dwData = V2ReadReg (devc, adbarb_sr_active_addr); + dwData |= (1 << sr); + V2WriteReg (devc, adbarb_sr_active_addr, dwData); + devc->sr_active |= (1 << sr); +} + +static void +DisableAdbWtd (vortex_devc * devc, int sr) +{ + unsigned int dwData; + + dwData = V2ReadReg (devc, adbarb_sr_active_addr); + dwData &= ~(1 << sr); + V2WriteReg (devc, adbarb_sr_active_addr, dwData); + devc->sr_active &= ~(1 << sr); +} + +static void +V2SetupRoutes (vortex_devc * devc) +{ + + /* Add the record routes */ + add_route (devc, 17, codec_chan0_src_addr, fifo_chan2_dst_addr, 0); + add_route (devc, 17, codec_chan1_src_addr, fifo_chan3_dst_addr, 0); + add_route (devc, 17, codec_chan0_src_addr, fifo_chan2a_dst_addr, 0); + add_route (devc, 17, codec_chan1_src_addr, fifo_chan3a_dst_addr, 0); + + /* Add the playback routes */ + add_route (devc, 17, fifo_chan0_src_addr, codec_chan0_dst_addr, 0); + add_route (devc, 17, fifo_chan0_src_addr, codec_chan1_dst_addr, 0); +} + +static void +init_fifos (vortex_devc * devc) +/* */ +/* Frequency to use. 1..256 which translates to nFreq/48000 */ +/* if 0 then use 12 for left and 24 for right. */ +/* */ +/* inputs: */ +/* nFreq -- frequency to use. */ +/* outputs: */ +/* none. */ +{ + int i; + + /* Zero Out all the FIFO Pointers, WT(64) & VDB(32) */ + for (i = 0; i < 96; i++) + { + V2WriteReg (devc, devc->fifo_base + 0x6000 + (4 * i), 0x00000020); + } + /* Program Channels 2,3,4,5 as record channels */ + for (i = 2; i < 6; i++) + { + V2WriteReg (devc, devc->fifo_base + 0x6100 + (4 * i), 0x00000000); + } + /* Set Trigger Levels */ + V2WriteReg (devc, devc->fifo_base + 0x7008, 0x00000843); + + + /* Clear out FIFO data for channels 0-9 */ + for (i = 0; i < 10; i++) + ClearDataFifo (devc, i); + + /* Set up the DMA engine to grab DMA memory */ + V2WriteReg (devc, devc->dma_base + 0xa80, 0); /* Clear Dma Status0 */ + V2WriteReg (devc, devc->dma_base + 0xa84, 0); /* Clear Dma Status1 */ + V2WriteReg (devc, devc->dma_base + 0xa88, 0); /* Clear Dma Status2 */ + V2WriteReg (devc, devc->dma_base + 0xa8c, 0); /* Clear Dma Status3 */ + V2WriteReg (devc, devc->dma_base + 0xa90, 0); /* Clear Dma Status4 */ + V2WriteReg (devc, devc->dma_base + 0xa94, 0); /* Clear Dma Status5 */ +} + +#ifdef USE_SRC +static void +v2setup_src (int dev) +{ + vortex_portc *portc = audio_engines[dev]->portc; + vortex_devc *devc = audio_engines[dev]->devc; + + int i, j, chn; + + for (j = 0; j < 2; j++) + { + unsigned int tmp, ratio, link; + chn = portc->voice_chn + j; + + for (i = 0; i < 128; i += 4) + V2WriteReg (devc, src_input_fifo_base + (128 * chn) + i, 0); + for (i = 0; i < 8; i += 4) + V2WriteReg (devc, src_output_fifo_base + (chn * 8) + i, 0); + + ratio = 48000 / portc->speed; + tmp = 0; + tmp |= chn & 0xf; /* Correlated channel */ + if (ratio > 4) + tmp |= ((17 - ratio - 1) << 4); + else + tmp |= (12 << 4); /* Zero crossing */ + V2WriteReg (devc, src_ch_params_base + 0xe00 + 4 * chn, tmp); /* [0] */ + + ratio = (48000 << 14) / portc->speed; + V2WriteReg (devc, src_ch_params_base + 0xe40 * 4 * chn, ratio); /* [1] */ + + V2WriteReg (devc, src_ch_params_base + 0xe80 + 4 * chn, 0); /* [2] */ + V2WriteReg (devc, src_ch_params_base + 0xec0 + 4 * chn, 0); /* [3] */ + V2WriteReg (devc, src_ch_params_base + 0xf00 + 4 * chn, 0); /* [4] */ + V2WriteReg (devc, src_ch_params_base + 0xf40 + 4 * chn, 1); /* [5] */ + + ratio = 48000 / portc->speed; + tmp = 0x3000f; /* Throttle in, FIFO depth=15 */ + V2WriteReg (devc, src_ch_params_base + 0xf80 + 4 * chn, tmp); /* [6] */ + + link = V2ReadReg (devc, src_sr_header_base + 0); + V2WriteReg (devc, src_next_ch_base + chn * 4, link); + V2WriteReg (devc, src_sr_header_base + 0, 0x10 | chn); + + link = V2ReadReg (devc, src_throttle_source); + link |= (1 << chn); + V2WriteReg (devc, src_throttle_source, link); + + link = V2ReadReg (devc, src_active_sample_rate); + link |= (1 << 0); + V2WriteReg (devc, src_active_sample_rate, link); + + } +} + +static void +v2cleanup_src (int dev) +{ + vortex_portc *portc = audio_engines[dev]->portc; + vortex_devc *devc = audio_engines[dev]->devc; + + int i, j, chn; + + for (j = 0; j < 2; j++) + { + unsigned int link; + + chn = portc->voice_chn + j; + + for (i = 0; i < 128; i += 4) + V2WriteReg (devc, src_input_fifo_base + (128 * chn) + i, 0); + for (i = 0; i < 8; i += 4) + V2WriteReg (devc, src_output_fifo_base + (chn * 8) + i, 0); + V2WriteReg (devc, src_next_ch_base + chn * 4, 0); + V2WriteReg (devc, src_sr_header_base + 0, 0); + + link = V2ReadReg (devc, src_active_sample_rate); + link &= ~(1 << chn); + V2WriteReg (devc, src_active_sample_rate, link); + + } +} +#endif + +/******************************************************** + * Vortex2 MIDI Routines * + ********************************************************/ +/*ARGSUSED*/ +static int +vortex2_midi_open (int dev, int mode, oss_midi_inputbyte_t inputbyte, + oss_midi_inputbuf_t inputbuf, + oss_midi_outputintr_t outputintr) +{ + vortex_devc *devc = (vortex_devc *) midi_devs[dev]->devc; + + if (devc->midi_opened) + { + return OSS_EBUSY; + } + + devc->midi_input_intr = inputbyte; + devc->midi_opened = mode; + + if (mode & OPEN_READ) + { + int tmp = V2ReadReg (devc, ICR); + V2WriteReg (devc, ICR, tmp | MIDIRQST); /* Enable MIDI interrupts */ + tmp = V2ReadReg (devc, ICR); + } + + V2WriteReg (devc, MIDICMD, 0x000000ff); /* Reset MIDI */ + V2WriteReg (devc, MIDICMD, 0x0000003f); /* Enter UART mode */ + if ((V2ReadReg (devc, MIDIDAT) & 0xff) != 0xfe) + cmn_err (CE_NOTE, "MIDI init not acknowledged\n"); + return 0; +} + +/*ARGSUSED*/ +static void +vortex2_midi_close (int dev, int mode) +{ + vortex_devc *devc = (vortex_devc *) midi_devs[dev]->devc; + + int tmp = V2ReadReg (devc, ICR); + V2WriteReg (devc, ICR, tmp & ~MIDIRQST); /* Disable MIDI interrupts */ + V2WriteReg (devc, MIDICMD, 0x000000ff); /* Reset MIDI */ + + devc->midi_opened = 0; +} + +static int +vortex2_midi_out (int dev, unsigned char midi_byte) +{ + int n = 10; + vortex_devc *devc = (vortex_devc *) midi_devs[dev]->devc; + + while ((V2ReadReg (devc, MIDISTAT) & CMDOK) && n--); + if (V2ReadReg (devc, MIDISTAT) & CMDOK) + return 0; + V2WriteReg (devc, MIDIDAT, midi_byte); + return 1; +} + +/*ARGSUSED*/ +static int +vortex2_midi_ioctl (int dev, unsigned cmd, ioctl_arg arg) +{ + return OSS_EINVAL; +} + +static midi_driver_t vortex2_midi_driver = { + vortex2_midi_open, + vortex2_midi_close, + vortex2_midi_ioctl, + vortex2_midi_out +}; + +static void +vortex2_midi_init (vortex_devc * devc) +{ + /* Derive the MIDI baud rate from 49.152 MHz clock */ + V2WriteReg (devc, GAMECTL, 0x00006100); + V2WriteReg (devc, MIDICMD, 0x000000ff); /* Reset MIDI */ + V2WriteReg (devc, MIDICMD, 0x0000003f); /* Enter UART mode */ + + /* All commands should return 0xfe as an acknowledgement */ + if ((V2ReadReg (devc, MIDIDAT) & 0xff) != 0xfe) + cmn_err (CE_NOTE, "MIDI init not acknowledged\n"); + V2WriteReg (devc, MIDICMD, 0x000000ff); /* Reset MIDI */ +} + +/**************************************************** + * OSS Audio routines * + ****************************************************/ + +static int +ac97_read (void *devc_, int addr) +{ + vortex_devc *devc = devc_; + int data; + oss_native_word flags; + + MUTEX_ENTER_IRQDISABLE (devc->low_mutex, flags); + V2ReadCodecRegister (devc, addr, &data); + MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags); + return data & 0xffff; +} + +static int +ac97_write (void *devc_, int addr, int data) +{ + vortex_devc *devc = devc_; + oss_native_word flags; + + MUTEX_ENTER_IRQDISABLE (devc->low_mutex, flags); + V2WriteCodecCommand (devc, addr, data); + MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags); + return 0; +} + +int +vortex2intr (oss_device_t * osdev) +{ + vortex_devc *devc = (vortex_devc *) osdev->devc; + int status; + int i; + int serviced = 0; + + /* + * TODO: Fix mutexes and move the inputintr/outputintr calls outside the + * mutex block. + */ + /* MUTEX_ENTER (devc->mutex, flags); */ + status = V2ReadReg (devc, ISR); + + if (status & MFATERRST) + cmn_err (CE_WARN, "Aureal Master fatal error interrupt\n"); + + if (status & MPARERRST) + cmn_err (CE_WARN, "Aureal Master parity error interrupt\n"); + + if (status & TIMIRQST) /* Timer interrupt */ + { + V2ReadReg (devc, CODSMPLTMR); /* Clear the interrupt */ + V2WriteReg (devc, CODSMPLTMR, 0x1000); + serviced = 1; + } + + if (status & (DMAENDIRQST | DMABERRST)) /* DMA end interrupt */ + { + for (i = 0; i < MAX_PORTC; i++) + { + vortex_portc *portc = &devc->portc[i]; + + if (portc->trigger_bits & PCM_ENABLE_OUTPUT) + { + dmap_t *dmap = audio_engines[portc->audiodev]->dmap_out; + + int pos = 0, n; + unsigned int dmastat; + + dmastat = V2ReadReg (devc, devc->dma_base + 0xd00 + (64 * 4)); + pos = ((dmastat >> 12) & 0x03) * 4096 + (dmastat & 4095); + pos /= dmap->fragment_size; + if (pos < 0 || pos >= dmap->nfrags) + pos = 0; + + n = 0; + while (dmap_get_qhead (dmap) != pos && n++ < dmap->nfrags) + oss_audio_outputintr (portc->audiodev, 0); + } + + if (portc->trigger_bits & PCM_ENABLE_INPUT) + { + dmap_t *dmap = audio_engines[portc->audiodev]->dmap_in; + + int pos = 0, n; + unsigned int dmastat; + + dmastat = V2ReadReg (devc, devc->dma_base + 0xd08 + (64 * 4)); + + pos = ((dmastat >> 12) & 0x03) * 4096 + (dmastat & 4095); + pos /= dmap->fragment_size; + if (pos < 0 || pos >= dmap->nfrags) + pos = 0; + + n = 0; + while (dmap_get_qtail (dmap) != pos && n++ < dmap->nfrags) + oss_audio_inputintr (portc->audiodev, 0); + } + V2ReadReg (devc, devc->dma_base + 0xa80); /* Read Dma Status0 */ + V2ReadReg (devc, devc->dma_base + 0xa84); /* Read Dma Status1 */ + V2ReadReg (devc, devc->dma_base + 0xa88); /* Read Dma Status2 */ + V2ReadReg (devc, devc->dma_base + 0xa8c); /* Read Dma Status3 */ + V2ReadReg (devc, devc->dma_base + 0xa90); /* Read Dma Status4 */ + V2ReadReg (devc, devc->dma_base + 0xa94); /* Read Dma Status5 */ + serviced = 1; + } + } + + if (status & MIDIRQST) /* MIDI interrupt */ + { + int uart_stat = V2ReadReg (devc, MIDISTAT); + int n = 10; + + while (!(uart_stat & MIDIVAL) && n--) + { + int d; + d = V2ReadReg (devc, MIDIDAT) & 0xff; + + if (devc->midi_opened & OPEN_READ && devc->midi_input_intr) + devc->midi_input_intr (devc->midi_dev, d); + uart_stat = V2ReadReg (devc, MIDISTAT); + } + serviced = 1; + } + + if (status != 0) + { + V2WriteReg (devc, ISR, status & 0x7ff); /* Ack pulse interrupts */ + status = V2ReadReg (devc, ISR); + serviced = 1; + } + /* MUTEX_EXIT (devc->mutex, flags); */ + return serviced; +} + + +static int +vortex2_set_rate (int dev, int arg) +{ + vortex_portc *portc = audio_engines[dev]->portc; + + if (arg == 0) + return portc->speed; + + if (audio_engines[dev]->flags & ADEV_FIXEDRATE) + arg = 48000; + + if (arg > 48000) + arg = 48000; + if (arg < 5000) + arg = 5000; + portc->speed = arg; + return portc->speed; +} + +static short +vortex2_set_channels (int dev, short arg) +{ + vortex_portc *portc = audio_engines[dev]->portc; + + if (audio_engines[dev]->flags & ADEV_STEREOONLY) + arg = 2; + + if ((arg != 1) && (arg != 2)) + return portc->channels; + portc->channels = arg; + + return portc->channels; +} + +static unsigned int +vortex2_set_format (int dev, unsigned int arg) +{ + vortex_portc *portc = audio_engines[dev]->portc; + + if (audio_engines[dev]->flags & ADEV_16BITONLY) + arg = 16; + + if (!(arg & (AFMT_U8 | AFMT_S16_LE))) + return portc->bits; + portc->bits = arg; + + return portc->bits; +} + +/*ARGSUSED*/ +static int +vortex2_ioctl (int dev, unsigned int cmd, ioctl_arg arg) +{ + return OSS_EINVAL; +} + +static void vortex2_trigger (int dev, int state); + +static void +vortex2_reset (int dev) +{ + vortex2_trigger (dev, 0); + +#ifdef USE_SRC + v2cleanup_src (dev); + del_route (devc, src_chan0_src_addr, 0); + del_route (devc, src_chan1_src_addr, 0); + del_route (devc, src_chan0_dst_addr, 0); + del_route (devc, src_chan1_dst_addr, 0); +#endif + +#ifdef USE_SPDIF + del_route (devc, spdif_chan0_dst_addr, 0); + del_route (devc, spdif_chan1_dst_addr, 0); +#endif +} + +static void +vortex2_reset_input (int dev) +{ + vortex_portc *portc = audio_engines[dev]->portc; + vortex2_trigger (dev, portc->trigger_bits & ~PCM_ENABLE_INPUT); +} + +static void +vortex2_reset_output (int dev) +{ + vortex_portc *portc = audio_engines[dev]->portc; + vortex2_trigger (dev, portc->trigger_bits & ~PCM_ENABLE_OUTPUT); +} + +/*ARGSUSED*/ +static int +vortex2_open (int dev, int mode, int open_flags) +{ + oss_native_word flags; + vortex_portc *portc = audio_engines[dev]->portc; + vortex_devc *devc = audio_engines[dev]->devc; + + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); + if (portc->open_mode) + { + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + return OSS_EBUSY; + } + + if (devc->open_mode & mode) + { + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + return OSS_EBUSY; + } + + devc->open_mode |= mode; + + portc->open_mode = mode; + portc->audio_enabled &= ~mode; + + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + return 0; +} + +static void +vortex2_close (int dev, int mode) +{ + vortex_portc *portc = audio_engines[dev]->portc; + vortex_devc *devc = audio_engines[dev]->devc; + + vortex2_reset (dev); + portc->open_mode = 0; + devc->open_mode &= ~mode; + portc->audio_enabled = ~mode; +} + +/*ARGSUSED*/ +static void +vortex2_output_block (int dev, oss_native_word buf, int count, int fragsize, + int intrflag) +{ + vortex_portc *portc = audio_engines[dev]->portc; + + portc->audio_enabled |= PCM_ENABLE_OUTPUT; + portc->trigger_bits &= ~PCM_ENABLE_OUTPUT; +} + +/*ARGSUSED*/ +static void +vortex2_start_input (int dev, oss_native_word buf, int count, int fragsize, + int intrflag) +{ + vortex_portc *portc = audio_engines[dev]->portc; + + portc->audio_enabled |= PCM_ENABLE_INPUT; + portc->trigger_bits &= ~PCM_ENABLE_INPUT; +} + +static void +vortex2_trigger (int dev, int state) +{ + vortex_devc *devc = audio_engines[dev]->devc; + vortex_portc *portc = audio_engines[dev]->portc; + unsigned int fifo_mode; + oss_native_word flags; + + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); + + if (portc->open_mode & OPEN_WRITE) + { + if (state & PCM_ENABLE_OUTPUT) + { + if ((portc->audio_enabled & PCM_ENABLE_OUTPUT) && + !(portc->trigger_bits & PCM_ENABLE_OUTPUT)) + { + /* Start the fifos */ + fifo_mode = 0xc0030; + if (portc->channels == 2) + { + fifo_mode |= 0x2; + V2WriteReg (devc, devc->fifo_base + 0x6100, fifo_mode); + } + else + { + V2WriteReg (devc, devc->fifo_base + 0x6100, fifo_mode); + V2WriteReg (devc, devc->fifo_base + 0x6104, fifo_mode); + } + V2WriteReg (devc, CODSMPLTMR, 0x1000); /* start timer */ + portc->trigger_bits |= PCM_ENABLE_OUTPUT; + } + } + else + { + if ((portc->audio_enabled & PCM_ENABLE_OUTPUT) && + (portc->trigger_bits & PCM_ENABLE_OUTPUT)) + { + portc->trigger_bits &= ~PCM_ENABLE_OUTPUT; + portc->audio_enabled &= ~PCM_ENABLE_OUTPUT; + + V2WriteReg (devc, CODSMPLTMR, 0x0); /* stop timer */ + + V2WriteReg (devc, devc->fifo_base + 0x6100, 0); /* Left Play */ + V2WriteReg (devc, devc->fifo_base + 0x6104, 0); /* Right Play */ + + ClearDataFifo (devc, 0); + ClearDataFifo (devc, 1); + } + } + } + + if (portc->open_mode & OPEN_READ) + { + if (state & PCM_ENABLE_INPUT) + { + if ((portc->audio_enabled & PCM_ENABLE_INPUT) && + !(portc->trigger_bits & PCM_ENABLE_INPUT)) + { + /* Start the fifos */ + fifo_mode = 0xc0010; + if (portc->channels == 2) + fifo_mode |= 2; + V2WriteReg (devc, devc->fifo_base + 0x6108, fifo_mode); /* LRecord */ + V2WriteReg (devc, devc->fifo_base + 0x610c, fifo_mode); /* RRecord */ + V2WriteReg (devc, CODSMPLTMR, 0x1000); /* start timer */ + portc->trigger_bits |= PCM_ENABLE_INPUT; + } + } + else + { + if ((portc->audio_enabled & PCM_ENABLE_INPUT) && + (portc->trigger_bits & PCM_ENABLE_INPUT)) + { + portc->trigger_bits &= ~PCM_ENABLE_INPUT; + portc->audio_enabled &= ~PCM_ENABLE_INPUT; + + V2WriteReg (devc, CODSMPLTMR, 0x0); /* stop timer */ + + V2WriteReg (devc, devc->fifo_base + 0x6108, 0); /* LRecord */ + V2WriteReg (devc, devc->fifo_base + 0x610c, 0); /* RRecord */ + + ClearDataFifo (devc, 2); + ClearDataFifo (devc, 3); + } + } + } + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); +} + +/*ARGSUSED*/ +static int +vortex2_prepare_for_input (int dev, int bsize, int bcount) +{ + unsigned int nBufSize, ChSizeGotoReg0, ChSizeGotoReg1; + unsigned int ch_mode, dma_base, dma_base4, dma_base8; + + dmap_t *dmap = audio_engines[dev]->dmap_in; + vortex_devc *devc = audio_engines[dev]->devc; + vortex_portc *portc = audio_engines[dev]->portc; + unsigned int SAMPLES = 1024; + oss_native_word flags; + + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); +#ifdef USE_SRC + v2setup_src (dev); +#endif + +#ifdef USE_SRC + /* Add the routes */ + add_route (devc, 17, codec_chan0_src_addr, src_chan0_dst_addr, 0); + add_route (devc, 17, codec_chan1_src_addr, src_chan1_dst_addr, 0); + add_route (devc, 1, src_chan0_src_addr, fifo_chan2_dst_addr, 0); + add_route (devc, 1, src_chan1_src_addr, fifo_chan3_dst_addr, 0); +#endif + + nBufSize = (SAMPLES * 2 * 2) - 1; + + ch_mode = 0x00001000; + switch (portc->bits) + { + case AFMT_U8: + ch_mode |= 0x00004000; + break; + case AFMT_S16_LE: + ch_mode |= 0x00020000; + break; + } + + dma_base = devc->dma_base + 16 * portc->voice_chn; + dma_base8 = devc->dma_base + 8 * portc->voice_chn; + dma_base4 = devc->dma_base + 4 * portc->voice_chn; + + /* Left Record Channel VDB ch2 */ + V2WriteReg (devc, dma_base + 0x420, dmap->dmabuf_phys); + V2WriteReg (devc, dma_base + 0x424, dmap->dmabuf_phys + 4096); + V2WriteReg (devc, dma_base + 0x428, dmap->dmabuf_phys + 2 * 4096); + V2WriteReg (devc, dma_base + 0x42c, dmap->dmabuf_phys + 3 * 4096); + + ChSizeGotoReg0 = (0xde000000) | (nBufSize << 12) | (nBufSize); + ChSizeGotoReg1 = (0xfc000000) | (nBufSize << 12) | (nBufSize); + + V2WriteReg (devc, dma_base8 + 0x810, ChSizeGotoReg0); + V2WriteReg (devc, dma_base8 + 0x814, ChSizeGotoReg1); + V2WriteReg (devc, dma_base4 + 0xa08, ch_mode); + + /* Right Record Channel VDB ch3 */ + V2WriteReg (devc, dma_base + 0x430, dmap->dmabuf_phys); + V2WriteReg (devc, dma_base + 0x434, dmap->dmabuf_phys + 4096); + V2WriteReg (devc, dma_base + 0x438, dmap->dmabuf_phys + 2 * 4096); + V2WriteReg (devc, dma_base + 0x43c, dmap->dmabuf_phys + 3 * 4096); + + ChSizeGotoReg0 = (0x56000000) | (nBufSize << 12) | (nBufSize); + ChSizeGotoReg0 = (0x74000000) | (nBufSize << 12) | (nBufSize); + V2WriteReg (devc, dma_base8 + 0x818, ChSizeGotoReg0); + V2WriteReg (devc, dma_base8 + 0x81c, ChSizeGotoReg1); + V2WriteReg (devc, dma_base4 + 0xa0c, ch_mode); + + portc->audio_enabled &= ~PCM_ENABLE_INPUT; + portc->trigger_bits &= ~PCM_ENABLE_INPUT; + + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + return 0; +} + +/*ARGSUSED*/ +static int +vortex2_prepare_for_output (int dev, int bsize, int bcount) +{ + unsigned int nBufSize, ChSizeGotoReg0, ChSizeGotoReg1; + unsigned int ch_mode, dma_base, dma_base4, dma_base8; + + dmap_t *dmap = audio_engines[dev]->dmap_out; + vortex_devc *devc = audio_engines[dev]->devc; + vortex_portc *portc = audio_engines[dev]->portc; + unsigned int SAMPLES = 1024; + oss_native_word flags; + + MUTEX_ENTER_IRQDISABLE (devc->mutex, flags); +#ifdef USE_SRC + v2setup_src (dev); + add_route (devc, 17, fifo_chan0_src_addr, src_chan0_dst_addr, 0); + add_route (devc, 17, fifo_chan1_src_addr, src_chan1_dst_addr, 0); + add_route (devc, 1, src_chan0_src_addr, codec_chan0_dst_addr, 0); + add_route (devc, 1, src_chan1_src_addr, codec_chan1_dst_addr, 0); +#endif + + nBufSize = (SAMPLES * 2 * 2) - 1; + + ch_mode = 0x00003000; + switch (portc->bits) + { + case AFMT_U8: + ch_mode |= 0x00004000; + break; + + case AFMT_S16_LE: + ch_mode |= 0x00020000; + break; + } + + dma_base = devc->dma_base + 16 * portc->voice_chn; + dma_base8 = devc->dma_base + 8 * portc->voice_chn; + dma_base4 = devc->dma_base + 4 * portc->voice_chn; + + /* Left Playback Channel #0 */ + V2WriteReg (devc, dma_base + 0x400, dmap->dmabuf_phys); + V2WriteReg (devc, dma_base + 0x404, dmap->dmabuf_phys + 4096); + V2WriteReg (devc, dma_base + 0x408, dmap->dmabuf_phys + 2 * 4096); + V2WriteReg (devc, dma_base + 0x40c, dmap->dmabuf_phys + 3 * 4096); + + ChSizeGotoReg0 = (0xde000000) | (nBufSize << 12) | (nBufSize); + ChSizeGotoReg1 = (0xfc000000) | (nBufSize << 12) | (nBufSize); + V2WriteReg (devc, dma_base8 + 0x800, ChSizeGotoReg0); + V2WriteReg (devc, dma_base8 + 0x804, ChSizeGotoReg1); + V2WriteReg (devc, dma_base4 + 0xa00, ch_mode); /* Set Chan0 Mode */ + + /* Right Playback Channel #1 */ + V2WriteReg (devc, dma_base + 0x410, dmap->dmabuf_phys); + V2WriteReg (devc, dma_base + 0x414, dmap->dmabuf_phys + 4096); + V2WriteReg (devc, dma_base + 0x418, dmap->dmabuf_phys + 2 * 4096); + V2WriteReg (devc, dma_base + 0x41c, dmap->dmabuf_phys + 3 * 4096); + ChSizeGotoReg0 = (0x56000000) | (nBufSize << 12) | (nBufSize); + ChSizeGotoReg1 = (0x74000000) | (nBufSize << 12) | (nBufSize); + V2WriteReg (devc, dma_base8 + 0x808, ChSizeGotoReg0); + V2WriteReg (devc, dma_base8 + 0x80c, ChSizeGotoReg1); + V2WriteReg (devc, dma_base4 + 0xa04, ch_mode); /* Set Chan1 Mode */ + + portc->audio_enabled &= ~PCM_ENABLE_OUTPUT; + portc->trigger_bits &= ~PCM_ENABLE_OUTPUT; + + MUTEX_EXIT_IRQRESTORE (devc->mutex, flags); + return 0; +} + +/*ARGSUSED*/ +static int +vortex2_free_buffer (int dev, dmap_t * dmap, int direction) +{ + vortex_devc *devc = audio_engines[dev]->devc; + + if (dmap->dmabuf == NULL) + return 0; +#if 1 + CONTIG_FREE (devc->osdev, dmap->dmabuf, dmap->buffsize, TODO); +#ifdef linux + oss_unreserve_pages ((oss_native_word) dmap->dmabuf, + (oss_native_word) dmap->dmabuf + 4 * 4096 - 1); +#endif + +#else + dmap->buffsize = devc->origbufsize; + oss_free_dmabuf (dev, dmap); +#endif + + dmap->dmabuf = NULL; + return 0; +} + +/*ARGSUSED*/ +static int +vortex2_alloc_buffer (int dev, dmap_t * dmap, int direction) +{ + vortex_devc *devc = audio_engines[dev]->devc; + oss_native_word phaddr; + /*int err; */ + + if (dmap->dmabuf != NULL) + return 0; +#if 1 + dmap->buffsize = 4 * 4096; /* 4 subbuffers */ + dmap->dmabuf = + CONTIG_MALLOC (devc->osdev, dmap->buffsize, MEMLIMIT_32BITS, &phaddr, TODO); + dmap->dmabuf_phys = phaddr; +#ifdef linux + oss_reserve_pages ((oss_native_word) dmap->dmabuf, + (oss_native_word) dmap->dmabuf + 4 * 4096 - 1); +#endif +#else + if ((err = oss_alloc_dmabuf (dev, dmap, direction)) < 0) + return err; + devc->origbufsize = dmap->buffsize; + dmap->buffsize = 4 * 4096; +#endif + + return 0; +} + +/*ARGSUSED*/ +static int +vortex2_get_buffer_pointer (int dev, dmap_t * dmap, int direction) +{ + vortex_devc *devc = audio_engines[dev]->devc; + oss_native_word flags, dmastat = 0; + int ptr = 0; + + MUTEX_ENTER_IRQDISABLE (devc->low_mutex, flags); + if (direction == PCM_ENABLE_OUTPUT) + { + dmastat = V2ReadReg (devc, devc->dma_base + 0xd00 + (64 * 4)); + } + if (direction == PCM_ENABLE_INPUT) + { + dmastat = V2ReadReg (devc, devc->dma_base + 0xd08 + (64 * 4)); + } + ptr = ((dmastat >> 12) & 0x03) * 4096 + (dmastat & 4095); + MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags); + return ptr; +} + +static audiodrv_t vortex2_driver = { + vortex2_open, + vortex2_close, + vortex2_output_block, + vortex2_start_input, + vortex2_ioctl, + vortex2_prepare_for_input, + vortex2_prepare_for_output, + vortex2_reset, + NULL, + NULL, + vortex2_reset_input, + vortex2_reset_output, + vortex2_trigger, + vortex2_set_rate, + vortex2_set_format, + vortex2_set_channels, + NULL, + NULL, + NULL, /* vortex2_check_input, */ + NULL, /* vortex2_check_output, */ + vortex2_alloc_buffer, + vortex2_free_buffer, + NULL, + NULL, + vortex2_get_buffer_pointer +}; + +#ifdef USE_SPDIF +static void +V2EnableSpdif (vortex_devc * devc) +{ + unsigned short data; + long n; + + for (n = 0; n <= 11; n++) + { + V2WriteReg (devc, spdif_ch_status_reg_base + (0x0004 * n), 0x0); + } + + V2WriteReg (devc, spdif_ch_status_reg_base, spdif_ch_status_reg0); /* first 4 bytes of channel status word */ + + V2WriteReg (devc, spdif_ctrl_reg, spdif_cfg_dword); /* set port to enable crc, input clock */ + + data = V2ReadReg (devc, channel_enable_reg_addr); + data = data | (1 << (18)); /* set bits 18 and 19 to enable S/PDIF; */ + data = data | (1 << (19)); /* set bits 18 and 19 to enable S/PDIF; */ + V2WriteReg (devc, channel_enable_reg_addr, data); +} +#endif + +static void +attach_channel_vortex2 (vortex_devc * devc, int my_mixer) +{ + int adev; + int i; + int first_dev = 0; + + for (i = 0; i < MAX_PORTC; i++) + { + char tmp_name[100]; + vortex_portc *portc = &devc->portc[i]; + int caps = + ADEV_FIXEDRATE | ADEV_AUTOMODE | ADEV_STEREOONLY | ADEV_16BITONLY; + + sprintf (tmp_name, "Aureal Vortex 2 (%s)", devc->name); + if (i == 0) + { + strcpy (tmp_name, devc->name); + caps |= ADEV_DUPLEX; + } + else + { + sprintf (tmp_name, "%s (shadow)", devc->name); + caps |= ADEV_DUPLEX | ADEV_SHADOW; + } + + if ((adev = oss_install_audiodev (OSS_AUDIO_DRIVER_VERSION, + devc->osdev, + devc->osdev, + tmp_name, + &vortex2_driver, + sizeof (audiodrv_t), + caps, + AFMT_U8 | AFMT_S16_LE, devc, -1)) < 0) + { + adev = -1; + return; + } + else + { + if (i == 0) + first_dev = adev; + audio_engines[adev]->portc = portc; + audio_engines[adev]->rate_source = first_dev; + audio_engines[adev]->fixed_rate = 48000; + audio_engines[adev]->min_rate = 48000; + audio_engines[adev]->max_rate = 48000; + audio_engines[adev]->vmix_flags = VMIX_MULTIFRAG; +#if 0 + audio_engines[adev]->min_block = 4096; + audio_engines[adev]->max_block = 4096; +#endif + audio_engines[adev]->mixer_dev = my_mixer; + portc->voice_chn = 0; + portc->open_mode = 0; + portc->audiodev = adev; + portc->audio_enabled = 0; +#ifdef CONFIG_OSS_VMIX + if (i == 0) + vmix_attach_audiodev(devc->osdev, adev, -1, 0); +#endif + } + } + return; +} + +int +init_vortex2 (vortex_devc * devc, int is_mx300) +{ + int my_mixer; + int i; + + devc->global_base = (0x2a000); + devc->dma_base = (0x27000); + devc->midi_base = (0x28800); + devc->fifo_base = (0x10000); + devc->adbarb_block_base = (0x28000); + devc->serial_block_base = (0x29000); + devc->parallel_base = (0x22000); + devc->src_base = (0x26000); + +/* + * Reset Vortex + */ + V2WriteReg (devc, GCR, 0xffffffff); + oss_udelay (1000); + + V2WriteReg (devc, GCR, V2ReadReg (devc, GCR) | GIRQEN); /* Enable IRQ */ + V2WriteReg (devc, CODSMPLTMR, 0x0); + V2WriteReg (devc, ICR, DMAENDIRQST | DMABERRST | TIMIRQST); + oss_udelay (100); + + if (is_mx300) + { + unsigned int temp; + + temp = V2ReadReg (devc, pif_gpio_control); + temp = 0x0c0 | temp; /* set GPIO3 to stereo 2x mode */ + temp = 0x080 | temp; /* enable GPIO3 */ + temp = 0xffffffbf & temp; /* set GPIO3 to low quad mode */ + V2WriteReg (devc, pif_gpio_control, temp); + } + + V2InitCodec (devc); + V2SetupCodec (devc); + V2InitAdb (devc); + EnableCodecChannel (devc, 0); + EnableCodecChannel (devc, 1); + init_fifos (devc); + EnableAdbWtd (devc, 17); + V2SetupRoutes (devc); +#ifdef USE_SRC + V2EnableSrc (devc); +#endif +#ifdef USE_SPDIF + V2EnableSpdif +#endif + /* + * DMA controller memory is supposed to contain 0xdeadbeef after + * reset. + */ + if (V2ReadReg (devc, devc->dma_base + 0xcfc) != 0xdeadbeef) + cmn_err (CE_WARN, + "DMA memory check returned unexpected result %08x\n", + V2ReadReg (devc, devc->dma_base + 0xcfc)); + + my_mixer = + ac97_install (&devc->ac97devc, "Vortex2 AC97 Mixer", ac97_read, + ac97_write, devc, devc->osdev); + if (my_mixer >= 0) + { + devc->mixer_dev = my_mixer; + } + else + return 0; + + + for (i = 0; i < 2; i++) + devc->dst_routed[i] = 0; + + attach_channel_vortex2 (devc, my_mixer); + + devc->midi_dev = + oss_install_mididev (OSS_MIDI_DRIVER_VERSION, "VORTEX", + "Aureal Vortex2 UART", &vortex2_midi_driver, + sizeof (midi_driver_t), + /*&std_midi_synth, */ NULL, + 0, devc, devc->osdev); + vortex2_midi_init (devc); + devc->midi_opened = 0; + return 1; +} + +void +unload_vortex2 (oss_device_t * osdev) +{ + vortex_devc *devc = (vortex_devc *) osdev->devc; + +#ifdef USE_SRC + V2DisableSrc (devc); +#endif + DisableCodecChannel (devc, 0); + DisableCodecChannel (devc, 1); + DisableAdbWtd (devc, 17); + + /* Disable routes */ + del_route (devc, codec_chan0_dst_addr, 0); + del_route (devc, codec_chan1_dst_addr, 0); + del_route (devc, fifo_chan2_dst_addr, 0); + del_route (devc, fifo_chan3_dst_addr, 0); + del_route (devc, fifo_chan2a_dst_addr, 0); + del_route (devc, fifo_chan3a_dst_addr, 0); + + /* Disable all interrupts */ + V2WriteReg (devc, ICR, 0x00000000); +} diff --git a/attic/drv/oss_vortex/vortex.h b/attic/drv/oss_vortex/vortex.h new file mode 100644 index 0000000..749d446 --- /dev/null +++ b/attic/drv/oss_vortex/vortex.h @@ -0,0 +1,80 @@ +/* + * Purpose: Definitions for the Vortex driver + */ +/* + * + * This file is part of Open Sound System. + * + * Copyright (C) 4Front Technologies 1996-2008. + * + * This this source file is released under GPL v2 license (no other versions). + * See the COPYING file included in the main directory of this source + * distribution for the license terms and conditions. + * + */ +#include "oss_vortex_cfg.h" +#include "midi_core.h" +#include <ac97.h> +#include <oss_pci.h> + +#define MAX_PORTC 2 + +typedef struct +{ + int open_mode; + int speed, bits, channels; + int voice_chn; + int audio_enabled; + int trigger_bits; + int audiodev; +} +vortex_portc; + + +typedef struct vortex_devc +{ + oss_device_t *osdev; + unsigned int bar0addr; + unsigned int *bar0virt; + volatile unsigned int *dwRegister; + unsigned int bar0_size; + int irq; + char *name; + int id; /* Vortex1 or Vortex2 */ + oss_mutex_t mutex; + oss_mutex_t low_mutex; + + /* Block pointers */ + oss_native_word global_base; + oss_native_word dma_base; + oss_native_word midi_base; + oss_native_word fifo_base; + oss_native_word adbarb_block_base; + oss_native_word serial_block_base; + oss_native_word parallel_base; + oss_native_word src_base; + + /* Mixer parameters */ + ac97_devc ac97devc; + int mixer_dev; + + /* Audio parameters */ + vortex_portc portc[MAX_PORTC]; + int open_mode; + int origbufsize; + + oss_native_word sr_active; + unsigned int tail_index[32]; + unsigned int dst_index[32]; + unsigned char sr_list[256]; + unsigned int dst_routed[256]; + + /* MIDI */ + int midi_opened; + int midi_dev; + oss_midi_inputbyte_t midi_input_intr; +} +vortex_devc; + +#define READL(a) (devc->dwRegister[a>>2]) +#define WRITEL(a, d) (devc->dwRegister[a>>2]=d) |