diff options
| author | mazen.neifer <mazen.neifer@b4165226-8c1b-0410-80e1-07324e54c907> | 2008-05-19 23:09:26 +0000 |
|---|---|---|
| committer | mazen.neifer <mazen.neifer@b4165226-8c1b-0410-80e1-07324e54c907> | 2008-05-19 23:09:26 +0000 |
| commit | 813400110f1597853e3ed83ee1fa3358bff218f1 (patch) | |
| tree | 99008889b2b02bc10e2c276ca2ede6b358395e3c /debian/patches | |
| parent | 5c8088bd3b2c6b90f9f9f42da30a6cb7a83aca42 (diff) | |
| download | fpc-813400110f1597853e3ed83ee1fa3358bff218f1.tar.gz | |
* Fixed patch enabling far jumps on sparc.
git-svn-id: https://bollin.googlecode.com/svn/fpc/trunk@3210 b4165226-8c1b-0410-80e1-07324e54c907
Diffstat (limited to 'debian/patches')
| -rwxr-xr-x | debian/patches/05_compiler_sparc_cgcpu.dpatch | 29 |
1 files changed, 23 insertions, 6 deletions
diff --git a/debian/patches/05_compiler_sparc_cgcpu.dpatch b/debian/patches/05_compiler_sparc_cgcpu.dpatch index 172e80ac..f2dca6ba 100755 --- a/debian/patches/05_compiler_sparc_cgcpu.dpatch +++ b/debian/patches/05_compiler_sparc_cgcpu.dpatch @@ -3,7 +3,7 @@ ## ## All lines beginning with `## DP:' are a description of the patch. ## DP: This patch fixes a non deterministic register allocation for -## DP: sprac architecture. +## DP: sprac architecture and permits long jumps for huge programs. @DPATCH@ Index: fpcsrc/compiler/sparc/cgcpu.pas @@ -19,18 +19,35 @@ Index: fpcsrc/compiler/sparc/cgcpu.pas { signed integer registers } OS_8, OS_S8: -@@ -1347,7 +1347,14 @@ - list.concat(taicpu.op_reg(A_JMP,NR_L1)); +@@ -540,6 +540,9 @@ + InternalError(2002122101); + end; + handle_load_store(list,false,op,reg,ref); ++ if (fromsize=OS_S8) and ++ (tosize=OS_16) then ++ a_load_reg_reg(list,fromsize,tosize,reg,reg); + end; + end; + +@@ -1342,12 +1345,19 @@ + reference_reset_base(href,NR_O0,0); + cg.a_load_ref_reg(list,OS_ADDR,OS_ADDR,href,NR_L0); + { jmp *vmtoffs(%eax) ; method offs } +- reference_reset_base(href,NR_L0,procdef._class.vmtmethodoffset(procdef.extnumber)); ++ reference_reset_base(href,NR_G1,procdef._class.vmtmethodoffset(procdef.extnumber)); + list.concat(taicpu.op_ref_reg(A_LD,href,NR_L1)); +- list.concat(taicpu.op_reg(A_JMP,NR_L1)); ++ list.concat(taicpu.op_reg(A_JMP,NR_G1)); end else - list.concat(taicpu.op_sym(A_BA,current_asmdata.RefAsmSymbol(procdef.mangledname))); + begin + reference_reset_symbol(href,current_asmdata.RefAsmSymbol(procdef.mangledname),0); + href.refaddr := addr_hi; -+ list.concat(taicpu.op_ref_reg(A_SETHI,href,NR_L1)); ++ list.concat(taicpu.op_ref_reg(A_SETHI,href,NR_G1)); + href.refaddr := addr_lo; -+ list.concat(taicpu.op_reg_ref_reg(A_OR,NR_G0,href,NR_L1)); -+ list.concat(taicpu.op_reg(A_JMP,NR_L1)); ++ list.concat(taicpu.op_reg_ref_reg(A_OR,NR_G1,href,NR_G1)); ++ list.concat(taicpu.op_reg(A_JMP,NR_G1)); + end; { Delay slot } list.Concat(TAiCpu.Op_none(A_NOP)); |