- GCC 5

git-svn-id: svn://anonscm.debian.org/gcccvs/branches/sid/gcc-5@7784 6ca36cf4-e1d1-0310-8c6f-e303bb2178ca

104 files changed, 3754 insertions, 64469 deletions

diff --git a/debian/changelog b/debian/changelog
index 42c1093..27b3cb0 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,12 @@
+gcc-5 (5-20150121-1) experimental; urgency=medium
+
+  * GCC 5.
+  * Build new binary packages libcc1-0, libgccjit0, libgccjit-5-dev,
+    libgccjit-5-dbg, libgccjit-5-doc.
+  * Update symbols files (still incomplete).
+
+ -- Matthias Klose <doko@debian.org>  Wed, 21 Jan 2015 21:02:05 +0100
+
 gcc-4.9 (4.9.2-10) UNRELEASED; urgency=medium
 
   * Update to SVN 20150120 (r219885) from the gcc-4_9-branch.
diff --git a/debian/control b/debian/control
index a237ed6..d5c38c5 100644
--- a/debian/control
+++ b/debian/control
@@ -1,4 +1,4 @@
-Source: gcc-4.9
+Source: gcc-5
 Section: devel
 Priority: optional
 Maintainer: Debian GCC Maintainers <debian-gcc@lists.debian.org>
@@ -21,10 +21,10 @@ Build-Depends: debhelper (>= 5.0.62), dpkg-dev (>= 1.17.11),
   dejagnu [!m68k], realpath (>= 1.9.12), chrpath, lsb-release, quilt
 Build-Depends-Indep: doxygen (>= 1.7.2), graphviz (>= 2.2), ghostscript, texlive-latex-base, xsltproc, libxml2-utils, docbook-xsl-ns, 
 Homepage: http://gcc.gnu.org/
-Vcs-Browser: http://svn.debian.org/viewsvn/gcccvs/branches/sid/gcc-4.9/
-Vcs-Svn: svn://anonscm.debian.org/gcccvs/branches/sid/gcc-4.9
+Vcs-Browser: http://svn.debian.org/viewsvn/gcccvs/branches/sid/gcc-5/
+Vcs-Svn: svn://anonscm.debian.org/gcccvs/branches/sid/gcc-5
 
-Package: gcc-4.9-base
+Package: gcc-5-base
 Architecture: any
 Multi-Arch: same
 Section: libs
@@ -40,7 +40,7 @@ Package: libgcc1
 Architecture: any
 Section: libs
 Priority: required
-Depends: gcc-4.9-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
 Provides: libgcc1-armel [armel], libgcc1-armhf [armhf]
 Multi-Arch: same
 Pre-Depends: multiarch-support
@@ -54,7 +54,7 @@ Package: libgcc1-dbg
 Architecture: any
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libgcc1 (= ${gcc:EpochVersion}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libgcc1 (= ${gcc:EpochVersion}), ${misc:Depends}
 Provides: libgcc1-dbg-armel [armel], libgcc1-dbg-armhf [armhf]
 Multi-Arch: same
 Description: GCC support library (debug symbols)
@@ -64,7 +64,7 @@ Package: libgcc2
 Architecture: m68k
 Section: libs
 Priority: required
-Depends: gcc-4.9-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
 Multi-Arch: same
 Pre-Depends: multiarch-support
 Breaks: ${multiarch:breaks}
@@ -77,17 +77,17 @@ Package: libgcc2-dbg
 Architecture: m68k
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libgcc2 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libgcc2 (= ${gcc:Version}), ${misc:Depends}
 Multi-Arch: same
 Description: GCC support library (debug symbols)
  Debug symbols for the GCC support library.
 
-Package: libgcc-4.9-dev
+Package: libgcc-5-dev
 Architecture: any
 Section: libdevel
 Priority: optional
 Recommends: ${dep:libcdev}
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libgcc}, ${dep:libssp}, ${dep:libgomp}, ${dep:libitm},
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libgcc}, ${dep:libssp}, ${dep:libgomp}, ${dep:libitm},
  ${dep:libatomic}, ${dep:libbtrace}, ${dep:libasan}, ${dep:liblsan},
  ${dep:libtsan}, ${dep:libubsan}, ${dep:libcilkrts}, ${dep:libvtv},
  ${dep:libqmath}, ${dep:libunwinddev}, ${shlibs:Depends}, ${misc:Depends}
@@ -104,7 +104,7 @@ Pre-Depends: multiarch-support
 Breaks: ${multiarch:breaks}
 Section: libs
 Priority: required
-Depends: gcc-4.9-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
 Description: GCC support library
  Shared version of the support library, a library of internal subroutines
  that GCC uses to overcome shortcomings of particular machines, or
@@ -115,7 +115,7 @@ Architecture: hppa
 Multi-Arch: same
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libgcc4 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libgcc4 (= ${gcc:Version}), ${misc:Depends}
 Description: GCC support library (debug symbols)
  Debug symbols for the GCC support library.
 
@@ -123,7 +123,7 @@ Package: lib64gcc1
 Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
 Section: libs
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${misc:Depends}
 Conflicts: libgcc1 (<= 1:3.3-0pre9)
 Description: GCC support library (64bit)
  Shared version of the support library, a library of internal subroutines
@@ -134,16 +134,16 @@ Package: lib64gcc1-dbg
 Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), lib64gcc1 (= ${gcc:EpochVersion}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), lib64gcc1 (= ${gcc:EpochVersion}), ${misc:Depends}
 Description: GCC support library (debug symbols)
  Debug symbols for the GCC support library.
 
-Package: lib64gcc-4.9-dev
+Package: lib64gcc-5-dev
 Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
 Section: libdevel
 Priority: optional
 Recommends: ${dep:libcdev}
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libgccbiarch}, ${dep:libsspbiarch},
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libgccbiarch}, ${dep:libsspbiarch},
  ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libatomicbiarch},
  ${dep:libbtracebiarch}, ${dep:libasanbiarch}, ${dep:liblsanbiarch},
  ${dep:libtsanbiarch}, ${dep:libubsanbiarch},
@@ -157,7 +157,7 @@ Package: lib32gcc1
 Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
 Section: libs
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${misc:Depends}
 Conflicts: ${confl:lib32}
 Description: GCC support library (32 bit Version)
  Shared version of the support library, a library of internal subroutines
@@ -168,16 +168,16 @@ Package: lib32gcc1-dbg
 Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), lib32gcc1 (= ${gcc:EpochVersion}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), lib32gcc1 (= ${gcc:EpochVersion}), ${misc:Depends}
 Description: GCC support library (debug symbols)
  Debug symbols for the GCC support library.
 
-Package: lib32gcc-4.9-dev
+Package: lib32gcc-5-dev
 Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
 Section: libdevel
 Priority: optional
 Recommends: ${dep:libcdev}
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libgccbiarch}, ${dep:libsspbiarch},
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libgccbiarch}, ${dep:libsspbiarch},
  ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libatomicbiarch},
  ${dep:libbtracebiarch}, ${dep:libasanbiarch}, ${dep:liblsanbiarch},
  ${dep:libtsanbiarch}, ${dep:libubsanbiarch},
@@ -191,7 +191,7 @@ Package: libn32gcc1
 Architecture: mips mipsel mips64 mips64el
 Section: libs
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${misc:Depends}
 Conflicts: libgcc1 (<= 1:3.3-0pre9)
 Description: GCC support library (n32)
  Shared version of the support library, a library of internal subroutines
@@ -202,16 +202,16 @@ Package: libn32gcc1-dbg
 Architecture: mips mipsel mips64 mips64el
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libn32gcc1 (= ${gcc:EpochVersion}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libn32gcc1 (= ${gcc:EpochVersion}), ${misc:Depends}
 Description: GCC support library (debug symbols)
  Debug symbols for the GCC support library.
 
-Package: libn32gcc-4.9-dev
+Package: libn32gcc-5-dev
 Architecture: mips mipsel mips64 mips64el
 Section: libdevel
 Priority: optional
 Recommends: ${dep:libcdev}
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libgccbiarch}, ${dep:libsspbiarch},
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libgccbiarch}, ${dep:libsspbiarch},
  ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libatomicbiarch},
  ${dep:libbtracebiarch}, ${dep:libasanbiarch}, ${dep:liblsanbiarch},
  ${dep:libtsanbiarch}, ${dep:libubsanbiarch},
@@ -225,7 +225,7 @@ Package: libx32gcc1
 Architecture: amd64 i386
 Section: libs
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${misc:Depends}
 Description: GCC support library (x32)
  Shared version of the support library, a library of internal subroutines
  that GCC uses to overcome shortcomings of particular machines, or
@@ -235,16 +235,16 @@ Package: libx32gcc1-dbg
 Architecture: amd64 i386
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libx32gcc1 (= ${gcc:EpochVersion}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libx32gcc1 (= ${gcc:EpochVersion}), ${misc:Depends}
 Description: GCC support library (debug symbols)
  Debug symbols for the GCC support library.
 
-Package: libx32gcc-4.9-dev
+Package: libx32gcc-5-dev
 Architecture: amd64 i386
 Section: libdevel
 Priority: optional
 Recommends: ${dep:libcdev}
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libgccbiarch}, ${dep:libsspbiarch},
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libgccbiarch}, ${dep:libsspbiarch},
  ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libatomicbiarch},
  ${dep:libbtracebiarch}, ${dep:libasanbiarch}, ${dep:liblsanbiarch},
  ${dep:libtsanbiarch}, ${dep:libubsanbiarch},
@@ -254,22 +254,23 @@ Description: GCC support library (x32 development files)
  This package contains the headers and static library files necessary for
  building C programs which use libgcc, libgomp, libquadmath, libssp or libitm.
 
-Package: gcc-4.9
+Package: gcc-5
 Architecture: any
 Section: devel
 Priority: optional
-Depends: cpp-4.9 (= ${gcc:Version}), gcc-4.9-base (= ${gcc:Version}),
+Depends: cpp-5 (= ${gcc:Version}), gcc-5-base (= ${gcc:Version}),
+  libcc1-0 (= ${gcc:Version}), 
   binutils (>= ${binutils:Version}), 
   ${dep:libgccdev}, ${shlibs:Depends}, ${misc:Depends}
 Recommends: ${dep:libcdev}
 Replaces: gccgo-4.9 (<< ${gcc:Version})
-Suggests: ${gcc:multilib}, gcc-4.9-doc (>= ${gcc:SoftVersion}),
- gcc-4.9-locales (>= ${gcc:SoftVersion}),
+Suggests: ${gcc:multilib}, gcc-5-doc (>= ${gcc:SoftVersion}),
+ gcc-5-locales (>= ${gcc:SoftVersion}),
  libgcc1-dbg (>= ${libgcc:Version}),
  libgomp1-dbg (>= ${gcc:Version}),
  libitm1-dbg (>= ${gcc:Version}),
  libatomic1-dbg (>= ${gcc:Version}),
- libasan1-dbg (>= ${gcc:Version}),
+ libasan2-dbg (>= ${gcc:Version}),
  liblsan0-dbg (>= ${gcc:Version}),
  libtsan0-dbg (>= ${gcc:Version}),
  libubsan0-dbg (>= ${gcc:Version}),
@@ -279,42 +280,42 @@ Provides: c-compiler
 Description: GNU C compiler
  This is the GNU C compiler, a fairly portable optimizing compiler for C.
 
-Package: gcc-4.9-multilib
+Package: gcc-5-multilib
 Architecture: amd64 i386 kfreebsd-amd64 mips mips64 mips64el mipsel mipsn32 mipsn32el powerpc ppc64 s390 s390x sparc sparc64 x32
 Section: devel
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), gcc-4.9 (= ${gcc:Version}), ${dep:libcbiarchdev}, ${dep:libgccbiarchdev}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), gcc-5 (= ${gcc:Version}), ${dep:libcbiarchdev}, ${dep:libgccbiarchdev}, ${shlibs:Depends}, ${misc:Depends}
 Description: GNU C compiler (multilib files)
  This is the GNU C compiler, a fairly portable optimizing compiler for C.
  .
  On architectures with multilib support, the package contains files
  and dependencies for the non-default multilib architecture(s).
 
-Package: gcc-4.9-plugin-dev
+Package: gcc-5-plugin-dev
 Architecture: any
 Section: devel
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), gcc-4.9 (= ${gcc:Version}), libgmp-dev (>= 2:5.0.1~), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), gcc-5 (= ${gcc:Version}), libgmp-dev (>= 2:5.0.1~), ${shlibs:Depends}, ${misc:Depends}
 Description: Files for GNU GCC plugin development.
  This package contains (header) files for GNU GCC plugin development. It
  is only used for the development of GCC plugins, but not needed to run
  plugins.
 
-Package: gcc-4.9-hppa64
+Package: gcc-5-hppa64
 Architecture: hppa
 Section: devel
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
 Conflicts: gcc-3.3-hppa64 (<= 1:3.3.4-5), gcc-3.4-hppa64 (<= 3.4.1-3), gcc-4.7-hppa64 (<< 4.7.3-13), gcc-4.8-hppa64 (<< 4.8.2-22)
 Description: GNU C compiler (cross compiler for hppa64)
  This is the GNU C compiler, a fairly portable optimizing compiler for C.
 
-Package: cpp-4.9
+Package: cpp-5
 Architecture: any
 Section: interpreters
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
-Suggests: gcc-4.9-locales (>= ${gcc:SoftVersion})
+Depends: gcc-5-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Suggests: gcc-5-locales (>= ${gcc:SoftVersion})
 Replaces: gccgo-4.9 (<< ${gcc:Version})
 Description: GNU C preprocessor
  A macro processor that is used automatically by the GNU C compiler
@@ -323,12 +324,12 @@ Description: GNU C preprocessor
  This package has been separated from gcc for the benefit of those who
  require the preprocessor but not the compiler.
 
-Package: gcc-4.9-locales
+Package: gcc-5-locales
 Architecture: all
 Section: devel
 Priority: optional
-Depends: gcc-4.9-base (>= ${gcc:SoftVersion}), cpp-4.9 (>= ${gcc:SoftVersion}), ${misc:Depends}
-Recommends: gcc-4.9 (>= ${gcc:SoftVersion})
+Depends: gcc-5-base (>= ${gcc:SoftVersion}), cpp-5 (>= ${gcc:SoftVersion}), ${misc:Depends}
+Recommends: gcc-5 (>= ${gcc:SoftVersion})
 Description: GCC, the GNU compiler collection (native language support files)
  Native language support for GCC. Lets GCC speak your language,
  if translations are available.
@@ -336,21 +337,21 @@ Description: GCC, the GNU compiler collection (native language support files)
  Please do NOT submit bug reports in other languages than "C".
  Always reset your language settings to use the "C" locales.
 
-Package: g++-4.9
+Package: g++-5
 Architecture: any
 Section: devel
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), gcc-4.9 (= ${gcc:Version}), libstdc++-4.9-dev (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), gcc-5 (= ${gcc:Version}), libstdc++-5-dev (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
 Provides: c++-compiler, c++abi2-dev
-Suggests: ${gxx:multilib}, gcc-4.9-doc (>= ${gcc:SoftVersion}), libstdc++6-4.9-dbg (>= ${gcc:Version})
+Suggests: ${gxx:multilib}, gcc-5-doc (>= ${gcc:SoftVersion}), libstdc++6-5-dbg (>= ${gcc:Version})
 Description: GNU C++ compiler
  This is the GNU C++ compiler, a fairly portable optimizing compiler for C++.
 
-Package: g++-4.9-multilib
+Package: g++-5-multilib
 Architecture: amd64 i386 kfreebsd-amd64 mips mips64 mips64el mipsel mipsn32 mipsn32el powerpc ppc64 s390 s390x sparc sparc64 x32
 Section: devel
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), g++-4.9 (= ${gcc:Version}), gcc-4.9-multilib (= ${gcc:Version}), ${dep:libcxxbiarchdev}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), g++-5 (= ${gcc:Version}), gcc-5-multilib (= ${gcc:Version}), ${dep:libcxxbiarchdev}, ${shlibs:Depends}, ${misc:Depends}
 Suggests: ${dep:libcxxbiarchdbg}
 Description: GNU C++ compiler (multilib files)
  This is the GNU C++ compiler, a fairly portable optimizing compiler for C++.
@@ -366,7 +367,7 @@ Multi-Arch: same
 Pre-Depends: multiarch-support
 Breaks: ${multiarch:breaks}
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
 Description: GCC OpenMP (GOMP) support library
  GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
  in the GNU Compiler Collection.
@@ -375,7 +376,7 @@ Package: libgomp1-dbg
 Architecture: any
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libgomp1 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libgomp1 (= ${gcc:Version}), ${misc:Depends}
 Provides: libgomp1-dbg-armel [armel], libgomp1-dbg-armhf [armhf]
 Multi-Arch: same
 Description: GCC OpenMP (GOMP) support library (debug symbols)
@@ -386,7 +387,7 @@ Package: lib32gomp1
 Section: libs
 Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Conflicts: ${confl:lib32}
 Description: GCC OpenMP (GOMP) support library (32bit)
  GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
@@ -396,7 +397,7 @@ Package: lib32gomp1-dbg
 Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), lib32gomp1 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), lib32gomp1 (= ${gcc:Version}), ${misc:Depends}
 Description: GCC OpenMP (GOMP) support library (32 bit debug symbols)
  GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
  in the GNU Compiler Collection.
@@ -405,7 +406,7 @@ Package: lib64gomp1
 Section: libs
 Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Description: GCC OpenMP (GOMP) support library (64bit)
  GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
  in the GNU Compiler Collection.
@@ -414,7 +415,7 @@ Package: lib64gomp1-dbg
 Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), lib64gomp1 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), lib64gomp1 (= ${gcc:Version}), ${misc:Depends}
 Description: GCC OpenMP (GOMP) support library (64bit debug symbols)
  GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
  in the GNU Compiler Collection.
@@ -423,7 +424,7 @@ Package: libn32gomp1
 Section: libs
 Architecture: mips mipsel mips64 mips64el
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Description: GCC OpenMP (GOMP) support library (n32)
  GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
  in the GNU Compiler Collection.
@@ -432,7 +433,7 @@ Package: libn32gomp1-dbg
 Architecture: mips mipsel mips64 mips64el
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libn32gomp1 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libn32gomp1 (= ${gcc:Version}), ${misc:Depends}
 Description: GCC OpenMP (GOMP) support library (n32 debug symbols)
  GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
 
@@ -440,7 +441,7 @@ Package: libx32gomp1
 Section: libs
 Architecture: amd64 i386
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Description: GCC OpenMP (GOMP) support library (x32)
  GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
  in the GNU Compiler Collection.
@@ -449,7 +450,7 @@ Package: libx32gomp1-dbg
 Architecture: amd64 i386
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libx32gomp1 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libx32gomp1 (= ${gcc:Version}), ${misc:Depends}
 Description: GCC OpenMP (GOMP) support library (x32 debug symbols)
  GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
 
@@ -460,7 +461,7 @@ Provides: libitm1-armel [armel], libitm1-armhf [armhf]
 Multi-Arch: same
 Pre-Depends: multiarch-support
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
 Description: GNU Transactional Memory Library
  GNU Transactional Memory Library (libitm) provides transaction support for
  accesses to the memory of a process, enabling easy-to-use synchronization of
@@ -470,7 +471,7 @@ Package: libitm1-dbg
 Architecture: any
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libitm1 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libitm1 (= ${gcc:Version}), ${misc:Depends}
 Provides: libitm1-dbg-armel [armel], libitm1-dbg-armhf [armhf]
 Multi-Arch: same
 Description: GNU Transactional Memory Library (debug symbols)
@@ -482,7 +483,7 @@ Package: lib32itm1
 Section: libs
 Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Conflicts: ${confl:lib32}
 Description: GNU Transactional Memory Library (32bit)
  GNU Transactional Memory Library (libitm) provides transaction support for
@@ -493,7 +494,7 @@ Package: lib32itm1-dbg
 Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), lib32itm1 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), lib32itm1 (= ${gcc:Version}), ${misc:Depends}
 Description: GNU Transactional Memory Library (32 bit debug symbols)
  GNU Transactional Memory Library (libitm) provides transaction support for
  accesses to the memory of a process, enabling easy-to-use synchronization of
@@ -503,7 +504,7 @@ Package: lib64itm1
 Section: libs
 Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Description: GNU Transactional Memory Library (64bit)
  GNU Transactional Memory Library (libitm) provides transaction support for
  accesses to the memory of a process, enabling easy-to-use synchronization of
@@ -513,7 +514,7 @@ Package: lib64itm1-dbg
 Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), lib64itm1 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), lib64itm1 (= ${gcc:Version}), ${misc:Depends}
 Description: GNU Transactional Memory Library (64bit debug symbols)
  GNU Transactional Memory Library (libitm) provides transaction support for
  accesses to the memory of a process, enabling easy-to-use synchronization of
@@ -545,7 +546,7 @@ Package: libx32itm1
 Section: libs
 Architecture: amd64 i386
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Description: GNU Transactional Memory Library (x32)
  This manual documents the usage and internals of libitm. It provides
  transaction support for accesses to the memory of a process, enabling
@@ -555,7 +556,7 @@ Package: libx32itm1-dbg
 Architecture: amd64 i386
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libx32itm1 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libx32itm1 (= ${gcc:Version}), ${misc:Depends}
 Description: GNU Transactional Memory Library (x32 debug symbols)
  This manual documents the usage and internals of libitm. It provides
  transaction support for accesses to the memory of a process, enabling
@@ -568,7 +569,7 @@ Provides: libatomic1-armel [armel], libatomic1-armhf [armhf]
 Multi-Arch: same
 Pre-Depends: multiarch-support
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
 Description: support library providing __atomic built-in functions
  library providing __atomic built-in functions. When an atomic call cannot
  be turned into lock-free instructions, GCC will make calls into this library.
@@ -577,7 +578,7 @@ Package: libatomic1-dbg
 Architecture: any
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libatomic1 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libatomic1 (= ${gcc:Version}), ${misc:Depends}
 Provides: libatomic1-dbg-armel [armel], libatomic1-dbg-armhf [armhf]
 Multi-Arch: same
 Description: support library providing __atomic built-in functions (debug symbols)
@@ -588,7 +589,7 @@ Package: lib32atomic1
 Section: libs
 Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Conflicts: ${confl:lib32}
 Description: support library providing __atomic built-in functions (32bit)
  library providing __atomic built-in functions. When an atomic call cannot
@@ -598,7 +599,7 @@ Package: lib32atomic1-dbg
 Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), lib32atomic1 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), lib32atomic1 (= ${gcc:Version}), ${misc:Depends}
 Description: support library providing __atomic built-in functions (32 bit debug symbols)
  library providing __atomic built-in functions. When an atomic call cannot
  be turned into lock-free instructions, GCC will make calls into this library.
@@ -607,7 +608,7 @@ Package: lib64atomic1
 Section: libs
 Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Description: support library providing __atomic built-in functions (64bit)
  library providing __atomic built-in functions. When an atomic call cannot
  be turned into lock-free instructions, GCC will make calls into this library.
@@ -616,7 +617,7 @@ Package: lib64atomic1-dbg
 Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), lib64atomic1 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), lib64atomic1 (= ${gcc:Version}), ${misc:Depends}
 Description: support library providing __atomic built-in functions (64bit debug symbols)
  library providing __atomic built-in functions. When an atomic call cannot
  be turned into lock-free instructions, GCC will make calls into this library.
@@ -625,7 +626,7 @@ Package: libn32atomic1
 Section: libs
 Architecture: mips mipsel mips64 mips64el
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Description: support library providing __atomic built-in functions (n32)
  library providing __atomic built-in functions. When an atomic call cannot
  be turned into lock-free instructions, GCC will make calls into this library.
@@ -634,7 +635,7 @@ Package: libn32atomic1-dbg
 Architecture: mips mipsel mips64 mips64el
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libn32atomic1 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libn32atomic1 (= ${gcc:Version}), ${misc:Depends}
 Description: support library providing __atomic built-in functions (n32 debug symbols)
  library providing __atomic built-in functions. When an atomic call cannot
  be turned into lock-free instructions, GCC will make calls into this library.
@@ -643,7 +644,7 @@ Package: libx32atomic1
 Section: libs
 Architecture: amd64 i386
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Description: support library providing __atomic built-in functions (x32)
  library providing __atomic built-in functions. When an atomic call cannot
  be turned into lock-free instructions, GCC will make calls into this library.
@@ -652,67 +653,67 @@ Package: libx32atomic1-dbg
 Architecture: amd64 i386
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libx32atomic1 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libx32atomic1 (= ${gcc:Version}), ${misc:Depends}
 Description: support library providing __atomic built-in functions (x32 debug symbols)
  library providing __atomic built-in functions. When an atomic call cannot
  be turned into lock-free instructions, GCC will make calls into this library.
 
-Package: libasan1
+Package: libasan2
 Section: libs
 Architecture: any
-Provides: libasan1-armel [armel], libasan1-armhf [armhf]
+Provides: libasan2-armel [armel], libasan2-armhf [armhf]
 Multi-Arch: same
 Pre-Depends: multiarch-support
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
 Description: AddressSanitizer -- a fast memory error detector
  AddressSanitizer (ASan) is a fast memory error detector.  It finds
  use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
 
-Package: libasan1-dbg
+Package: libasan2-dbg
 Architecture: any
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libasan1 (= ${gcc:Version}), ${misc:Depends}
-Provides: libasan1-dbg-armel [armel], libasan1-dbg-armhf [armhf]
+Depends: gcc-5-base (= ${gcc:Version}), libasan2 (= ${gcc:Version}), ${misc:Depends}
+Provides: libasan2-dbg-armel [armel], libasan2-dbg-armhf [armhf]
 Multi-Arch: same
 Description: AddressSanitizer -- a fast memory error detector (debug symbols)
  AddressSanitizer (ASan) is a fast memory error detector.  It finds
  use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
 
-Package: lib32asan1
+Package: lib32asan2
 Section: libs
 Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Conflicts: ${confl:lib32}
 Description: AddressSanitizer -- a fast memory error detector (32bit)
  AddressSanitizer (ASan) is a fast memory error detector.  It finds
  use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
 
-Package: lib32asan1-dbg
+Package: lib32asan2-dbg
 Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), lib32asan1 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), lib32asan2 (= ${gcc:Version}), ${misc:Depends}
 Description: AddressSanitizer -- a fast memory error detector (32 bit debug symbols)
  AddressSanitizer (ASan) is a fast memory error detector.  It finds
  use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
 
-Package: lib64asan1
+Package: lib64asan2
 Section: libs
 Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Description: AddressSanitizer -- a fast memory error detector (64bit)
  AddressSanitizer (ASan) is a fast memory error detector.  It finds
  use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
 
-Package: lib64asan1-dbg
+Package: lib64asan2-dbg
 Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), lib64asan1 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), lib64asan2 (= ${gcc:Version}), ${misc:Depends}
 Description: AddressSanitizer -- a fast memory error detector (64bit debug symbols)
  AddressSanitizer (ASan) is a fast memory error detector.  It finds
  use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
@@ -737,20 +738,20 @@ Description: AddressSanitizer -- a fast memory error detector (64bit debug symbo
 # AddressSanitizer (ASan) is a fast memory error detector.  It finds
 # use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
 
-Package: libx32asan1
+Package: libx32asan2
 Section: libs
 Architecture: amd64 i386
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Description: AddressSanitizer -- a fast memory error detector (x32)
  AddressSanitizer (ASan) is a fast memory error detector.  It finds
  use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
 
-Package: libx32asan1-dbg
+Package: libx32asan2-dbg
 Architecture: amd64 i386
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libx32asan1 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libx32asan2 (= ${gcc:Version}), ${misc:Depends}
 Description: AddressSanitizer -- a fast memory error detector (x32 debug symbols)
  AddressSanitizer (ASan) is a fast memory error detector.  It finds
  use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
@@ -761,7 +762,7 @@ Architecture: any
 Multi-Arch: same
 Pre-Depends: multiarch-support
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
 Description: LeakSanitizer -- a memory leak detector (runtime)
  LeakSanitizer (Lsan) is a memory leak detector which is integrated
  into AddressSanitizer.
@@ -770,7 +771,7 @@ Package: liblsan0-dbg
 Architecture: any
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), liblsan0 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), liblsan0 (= ${gcc:Version}), ${misc:Depends}
 Multi-Arch: same
 Description: LeakSanitizer -- a memory leak detector (debug symbols)
  LeakSanitizer (Lsan) is a memory leak detector which is integrated
@@ -780,7 +781,7 @@ Package: lib32lsan0
 Section: libs
 Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Conflicts: ${confl:lib32}
 Description: LeakSanitizer -- a memory leak detector (32bit)
  LeakSanitizer (Lsan) is a memory leak detector which is integrated
@@ -790,7 +791,7 @@ Package: lib32lsan0-dbg
 Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), lib32lsan0 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), lib32lsan0 (= ${gcc:Version}), ${misc:Depends}
 Description: LeakSanitizer -- a memory leak detector (32 bit debug symbols)
  LeakSanitizer (Lsan) is a memory leak detector which is integrated
  into AddressSanitizer.
@@ -839,7 +840,7 @@ Package: libx32lsan0
 Section: libs
 Architecture: amd64 i386
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Description: LeakSanitizer -- a memory leak detector (x32)
  LeakSanitizer (Lsan) is a memory leak detector which is integrated
  into AddressSanitizer.
@@ -848,7 +849,7 @@ Package: libx32lsan0-dbg
 Architecture: amd64 i386
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libx32lsan0 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libx32lsan0 (= ${gcc:Version}), ${misc:Depends}
 Description: LeakSanitizer -- a memory leak detector (x32 debug symbols)
  LeakSanitizer (Lsan) is a memory leak detector which is integrated
  into AddressSanitizer.
@@ -860,7 +861,7 @@ Provides: libtsan0-armel [armel], libtsan0-armhf [armhf]
 Multi-Arch: same
 Pre-Depends: multiarch-support
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
 Description: ThreadSanitizer -- a Valgrind-based detector of data races (runtime)
  ThreadSanitizer (Tsan) is a data race detector for C/C++ programs. 
  The Linux and Mac versions are based on Valgrind. 
@@ -869,7 +870,7 @@ Package: libtsan0-dbg
 Architecture: any
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libtsan0 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libtsan0 (= ${gcc:Version}), ${misc:Depends}
 Provides: libtsan0-dbg-armel [armel], libtsan0-dbg-armhf [armhf]
 Multi-Arch: same
 Description: ThreadSanitizer -- a Valgrind-based detector of data races (debug symbols)
@@ -883,7 +884,7 @@ Provides: libubsan0-armel [armel], libubsan0-armhf [armhf]
 Multi-Arch: same
 Pre-Depends: multiarch-support
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
 Description: UBSan -- undefined behaviour sanitizer (runtime)
  UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
  Various computations will be instrumented to detect undefined behavior
@@ -893,7 +894,7 @@ Package: libubsan0-dbg
 Architecture: any
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libubsan0 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libubsan0 (= ${gcc:Version}), ${misc:Depends}
 Provides: libubsan0-dbg-armel [armel], libubsan0-dbg-armhf [armhf]
 Multi-Arch: same
 Description: UBSan -- undefined behaviour sanitizer (debug symbols)
@@ -905,7 +906,7 @@ Package: lib32ubsan0
 Section: libs
 Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Conflicts: ${confl:lib32}
 Description: UBSan -- undefined behaviour sanitizer (32bit)
  UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
@@ -916,7 +917,7 @@ Package: lib32ubsan0-dbg
 Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), lib32ubsan0 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), lib32ubsan0 (= ${gcc:Version}), ${misc:Depends}
 Description: UBSan -- undefined behaviour sanitizer (32 bit debug symbols)
  UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
  Various computations will be instrumented to detect undefined behavior
@@ -926,7 +927,7 @@ Package: lib64ubsan0
 Section: libs
 Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Description: UBSan -- undefined behaviour sanitizer (64bit)
  UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
  Various computations will be instrumented to detect undefined behavior
@@ -936,7 +937,7 @@ Package: lib64ubsan0-dbg
 Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), lib64ubsan0 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), lib64ubsan0 (= ${gcc:Version}), ${misc:Depends}
 Description: UBSan -- undefined behaviour sanitizer (64bit debug symbols)
  UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
  Various computations will be instrumented to detect undefined behavior
@@ -968,7 +969,7 @@ Package: libx32ubsan0
 Section: libs
 Architecture: amd64 i386
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Description: UBSan -- undefined behaviour sanitizer (x32)
  UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
  Various computations will be instrumented to detect undefined behavior
@@ -978,7 +979,7 @@ Package: libx32ubsan0-dbg
 Architecture: amd64 i386
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libx32ubsan0 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libx32ubsan0 (= ${gcc:Version}), ${misc:Depends}
 Description: UBSan -- undefined behaviour sanitizer (x32 debug symbols)
  UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
  Various computations will be instrumented to detect undefined behavior
@@ -991,7 +992,7 @@ Provides: libcilkrts5-armel [armel], libcilkrts5-armhf [armhf]
 Multi-Arch: same
 Pre-Depends: multiarch-support
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
 Description: Intel Cilk Plus language extensions (runtime)
  Intel Cilk Plus is an extension to the C and C++ languages to support
  data and task parallelism.
@@ -1000,7 +1001,7 @@ Package: libcilkrts5-dbg
 Architecture: any
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libcilkrts5 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libcilkrts5 (= ${gcc:Version}), ${misc:Depends}
 Provides: libcilkrts5-dbg-armel [armel], libcilkrts5-dbg-armhf [armhf]
 Multi-Arch: same
 Description: Intel Cilk Plus language extensions (debug symbols)
@@ -1011,7 +1012,7 @@ Package: lib32cilkrts5
 Section: libs
 Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Conflicts: ${confl:lib32}
 Description: Intel Cilk Plus language extensions (32bit)
  Intel Cilk Plus is an extension to the C and C++ languages to support
@@ -1021,7 +1022,7 @@ Package: lib32cilkrts5-dbg
 Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), lib32cilkrts5 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), lib32cilkrts5 (= ${gcc:Version}), ${misc:Depends}
 Description: Intel Cilk Plus language extensions (32 bit debug symbols)
  Intel Cilk Plus is an extension to the C and C++ languages to support
  data and task parallelism.
@@ -1030,7 +1031,7 @@ Package: lib64cilkrts5
 Section: libs
 Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Description: Intel Cilk Plus language extensions (64bit)
  Intel Cilk Plus is an extension to the C and C++ languages to support
  data and task parallelism.
@@ -1039,7 +1040,7 @@ Package: lib64cilkrts5-dbg
 Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), lib64cilkrts5 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), lib64cilkrts5 (= ${gcc:Version}), ${misc:Depends}
 Description: Intel Cilk Plus language extensions (64bit debug symbols)
  Intel Cilk Plus is an extension to the C and C++ languages to support
  data and task parallelism.
@@ -1048,7 +1049,7 @@ Package: libx32cilkrts5
 Section: libs
 Architecture: amd64 i386
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Description: Intel Cilk Plus language extensions (x32)
  Intel Cilk Plus is an extension to the C and C++ languages to support
  data and task parallelism.
@@ -1057,7 +1058,7 @@ Package: libx32cilkrts5-dbg
 Architecture: amd64 i386
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libx32cilkrts5 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libx32cilkrts5 (= ${gcc:Version}), ${misc:Depends}
 Description: Intel Cilk Plus language extensions (x32 debug symbols)
  Intel Cilk Plus is an extension to the C and C++ languages to support
  data and task parallelism.
@@ -1068,7 +1069,7 @@ Architecture: any
 Multi-Arch: same
 Pre-Depends: multiarch-support
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
 Description: GCC Quad-Precision Math Library
  A library, which provides quad-precision mathematical functions on targets
  supporting the __float128 datatype. The library is used to provide on such
@@ -1078,7 +1079,7 @@ Package: libquadmath0-dbg
 Architecture: any
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libquadmath0 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libquadmath0 (= ${gcc:Version}), ${misc:Depends}
 Multi-Arch: same
 Description: GCC Quad-Precision Math Library (debug symbols)
  A library, which provides quad-precision mathematical functions on targets
@@ -1088,7 +1089,7 @@ Package: lib32quadmath0
 Section: libs
 Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Conflicts: ${confl:lib32}
 Description: GCC Quad-Precision Math Library (32bit)
  A library, which provides quad-precision mathematical functions on targets
@@ -1099,7 +1100,7 @@ Package: lib32quadmath0-dbg
 Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), lib32quadmath0 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), lib32quadmath0 (= ${gcc:Version}), ${misc:Depends}
 Description: GCC Quad-Precision Math Library (32 bit debug symbols)
  A library, which provides quad-precision mathematical functions on targets
  supporting the __float128 datatype.
@@ -1108,7 +1109,7 @@ Package: lib64quadmath0
 Section: libs
 Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Description: GCC Quad-Precision Math Library  (64bit)
  A library, which provides quad-precision mathematical functions on targets
  supporting the __float128 datatype. The library is used to provide on such
@@ -1118,7 +1119,7 @@ Package: lib64quadmath0-dbg
 Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), lib64quadmath0 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), lib64quadmath0 (= ${gcc:Version}), ${misc:Depends}
 Description: GCC Quad-Precision Math Library  (64bit debug symbols)
  A library, which provides quad-precision mathematical functions on targets
  supporting the __float128 datatype.
@@ -1148,7 +1149,7 @@ Package: libx32quadmath0
 Section: libs
 Architecture: amd64 i386
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Description: GCC Quad-Precision Math Library (x32)
  A library, which provides quad-precision mathematical functions on targets
  supporting the __float128 datatype. The library is used to provide on such
@@ -1158,27 +1159,82 @@ Package: libx32quadmath0-dbg
 Architecture: amd64 i386
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libx32quadmath0 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libx32quadmath0 (= ${gcc:Version}), ${misc:Depends}
 Description: GCC Quad-Precision Math Library (x32 debug symbols)
  A library, which provides quad-precision mathematical functions on targets
  supporting the __float128 datatype.
 
-Package: gobjc++-4.9
+Package: libcc1-0
+Section: libs
+Architecture: any
+Multi-Arch: same
+Pre-Depends: multiarch-support
+Priority: optional
+Depends: gcc-5-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: GCC cc1 plugin for GDB
+ libcc1 is a plugin for GDB.
+
+Package: libgccjit0
+Section: libs
+Architecture: any
+Multi-Arch: same
+Pre-Depends: multiarch-support
+Priority: optional
+Depends: gcc-5-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: GCC just-in-time compilation (shared library)
+ libgccjit provides an embeddable shared library with an API for adding
+ compilation to existing programs using GCC.
+
+Package: libgccjit-5-dev
+Section: libs
+Architecture: any
+Multi-Arch: same
+Pre-Depends: multiarch-support
+Priority: optional
+Depends: gcc-5-base (= ${gcc:Version}), libgccjit0 (= ${gcc:Version}),
+ ${shlibs:Depends}, ${misc:Depends}
+Suggests: libgccjit-5-dbg
+Description: GCC just-in-time compilation (development files)
+ libgccjit provides an embeddable shared library with an API for adding
+ compilation to existing programs using GCC.
+
+Package: libgccjit-5-dbg
+Section: debug
+Architecture: any
+Multi-Arch: same
+Pre-Depends: multiarch-support
+Priority: extra
+Depends: gcc-5-base (= ${gcc:Version}), libgccjit0 (= ${gcc:Version}),
+ ${shlibs:Depends}, ${misc:Depends}
+Description: GCC just-in-time compilation (debug information)
+ libgccjit provides an embeddable shared library with an API for adding
+ compilation to existing programs using GCC.
+
+Package: libgccjit-5-doc
+Section: doc
+Architecture: all
+Priority: extra
+Depends: gcc-5-base (= ${gcc:Version}), ${misc:Depends}
+Description: GCC just-in-time compilation (documentation)
+ libgccjit provides an embeddable shared library with an API for adding
+ compilation to existing programs using GCC.
+
+Package: gobjc++-5
 Architecture: any
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), gobjc-4.9 (= ${gcc:Version}), g++-4.9 (= ${gcc:Version}), ${shlibs:Depends}, libobjc-4.9-dev (= ${gcc:Version}), ${misc:Depends}
-Suggests: ${gobjcxx:multilib}, gcc-4.9-doc (>= ${gcc:SoftVersion})
+Depends: gcc-5-base (= ${gcc:Version}), gobjc-5 (= ${gcc:Version}), g++-5 (= ${gcc:Version}), ${shlibs:Depends}, libobjc-5-dev (= ${gcc:Version}), ${misc:Depends}
+Suggests: ${gobjcxx:multilib}, gcc-5-doc (>= ${gcc:SoftVersion})
 Provides: objc++-compiler
 Description: GNU Objective-C++ compiler
  This is the GNU Objective-C++ compiler, which compiles
  Objective-C++ on platforms supported by the gcc compiler. It uses the
  gcc backend to generate optimized code.
 
-Package: gobjc++-4.9-multilib
+Package: gobjc++-5-multilib
 Architecture: amd64 i386 kfreebsd-amd64 mips mips64 mips64el mipsel mipsn32 mipsn32el powerpc ppc64 s390 s390x sparc sparc64 x32
 Section: devel
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), gobjc++-4.9 (= ${gcc:Version}), g++-4.9-multilib (= ${gcc:Version}), gobjc-4.9-multilib (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), gobjc++-5 (= ${gcc:Version}), g++-5-multilib (= ${gcc:Version}), gobjc-5-multilib (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
 Description: GNU Objective-C++ compiler (multilib files)
  This is the GNU Objective-C++ compiler, which compiles Objective-C++ on
  platforms supported by the gcc compiler.
@@ -1186,22 +1242,22 @@ Description: GNU Objective-C++ compiler (multilib files)
  On architectures with multilib support, the package contains files
  and dependencies for the non-default multilib architecture(s).
 
-Package: gobjc-4.9
+Package: gobjc-5
 Architecture: any
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), gcc-4.9 (= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, libobjc-4.9-dev (= ${gcc:Version}), ${misc:Depends}
-Suggests: ${gobjc:multilib}, gcc-4.9-doc (>= ${gcc:SoftVersion}), libobjc4-dbg (>= ${gcc:Version})
+Depends: gcc-5-base (= ${gcc:Version}), gcc-5 (= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, libobjc-5-dev (= ${gcc:Version}), ${misc:Depends}
+Suggests: ${gobjc:multilib}, gcc-5-doc (>= ${gcc:SoftVersion}), libobjc4-dbg (>= ${gcc:Version})
 Provides: objc-compiler
 Description: GNU Objective-C compiler
  This is the GNU Objective-C compiler, which compiles
  Objective-C on platforms supported by the gcc compiler. It uses the
  gcc backend to generate optimized code.
 
-Package: gobjc-4.9-multilib
+Package: gobjc-5-multilib
 Architecture: amd64 i386 kfreebsd-amd64 mips mips64 mips64el mipsel mipsn32 mipsn32el powerpc ppc64 s390 s390x sparc sparc64 x32
 Section: devel
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), gobjc-4.9 (= ${gcc:Version}), gcc-4.9-multilib (= ${gcc:Version}), ${dep:libobjcbiarchdev}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), gobjc-5 (= ${gcc:Version}), gcc-5-multilib (= ${gcc:Version}), ${dep:libobjcbiarchdev}, ${shlibs:Depends}, ${misc:Depends}
 Description: GNU Objective-C compiler (multilib files)
  This is the GNU Objective-C compiler, which compiles Objective-C on platforms
  supported by the gcc compiler.
@@ -1209,48 +1265,48 @@ Description: GNU Objective-C compiler (multilib files)
  On architectures with multilib support, the package contains files
  and dependencies for the non-default multilib architecture(s).
 
-Package: libobjc-4.9-dev
+Package: libobjc-5-dev
 Architecture: any
 Section: libdevel
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), libgcc-4.9-dev (= ${gcc:Version}), libobjc4 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libgcc-5-dev (= ${gcc:Version}), libobjc4 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
 Multi-Arch: same
 Description: Runtime library for GNU Objective-C applications (development files)
  This package contains the headers and static library files needed to build
  GNU ObjC applications.
 
-Package: lib64objc-4.9-dev
+Package: lib64objc-5-dev
 Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
 Section: libdevel
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), lib64gcc-4.9-dev (= ${gcc:Version}), lib64objc4 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), lib64gcc-5-dev (= ${gcc:Version}), lib64objc4 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
 Description: Runtime library for GNU Objective-C applications (64bit development files)
  This package contains the headers and static library files needed to build
  GNU ObjC applications.
 
-Package: lib32objc-4.9-dev
+Package: lib32objc-5-dev
 Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
 Section: libdevel
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), lib32gcc-4.9-dev (= ${gcc:Version}), lib32objc4 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), lib32gcc-5-dev (= ${gcc:Version}), lib32objc4 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
 Description: Runtime library for GNU Objective-C applications (32bit development files)
  This package contains the headers and static library files needed to build
  GNU ObjC applications.
 
-Package: libn32objc-4.9-dev
+Package: libn32objc-5-dev
 Architecture: mips mipsel mips64 mips64el
 Section: libdevel
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), libn32gcc-4.9-dev (= ${gcc:Version}), libn32objc4 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libn32gcc-5-dev (= ${gcc:Version}), libn32objc4 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
 Description: Runtime library for GNU Objective-C applications (n32 development files)
  This package contains the headers and static library files needed to build
  GNU ObjC applications.
 
-Package: libx32objc-4.9-dev
+Package: libx32objc-5-dev
 Architecture: amd64 i386
 Section: libdevel
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), libx32gcc-4.9-dev (= ${gcc:Version}), libx32objc4 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libx32gcc-5-dev (= ${gcc:Version}), libx32objc4 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
 Description: Runtime library for GNU Objective-C applications (x32 development files)
  This package contains the headers and static library files needed to build
  GNU ObjC applications.
@@ -1262,7 +1318,7 @@ Provides: libobjc4-armel [armel], libobjc4-armhf [armhf]
 Multi-Arch: same
 Pre-Depends: multiarch-support
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
 Description: Runtime library for GNU Objective-C applications
  Library needed for GNU ObjC applications linked against the shared library.
 
@@ -1272,7 +1328,7 @@ Architecture: any
 Provides: libobjc4-dbg-armel [armel], libobjc4-dbg-armhf [armhf]
 Multi-Arch: same
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libobjc4 (= ${gcc:Version}), libgcc1-dbg (>= ${libgcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libobjc4 (= ${gcc:Version}), libgcc1-dbg (>= ${libgcc:Version}), ${misc:Depends}
 Description: Runtime library for GNU Objective-C applications (debug symbols)
  Library needed for GNU ObjC applications linked against the shared library.
 
@@ -1280,7 +1336,7 @@ Package: lib64objc4
 Section: libs
 Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Description: Runtime library for GNU Objective-C applications (64bit)
  Library needed for GNU ObjC applications linked against the shared library.
 
@@ -1288,7 +1344,7 @@ Package: lib64objc4-dbg
 Section: debug
 Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), lib64objc4 (= ${gcc:Version}), lib64gcc1-dbg (>= ${gcc:EpochVersion}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), lib64objc4 (= ${gcc:Version}), lib64gcc1-dbg (>= ${gcc:EpochVersion}), ${misc:Depends}
 Description: Runtime library for GNU Objective-C applications (64 bit debug symbols)
  Library needed for GNU ObjC applications linked against the shared library.
 
@@ -1296,7 +1352,7 @@ Package: lib32objc4
 Section: libs
 Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Conflicts: ${confl:lib32}
 Description: Runtime library for GNU Objective-C applications (32bit)
  Library needed for GNU ObjC applications linked against the shared library.
@@ -1305,7 +1361,7 @@ Package: lib32objc4-dbg
 Section: debug
 Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), lib32objc4 (= ${gcc:Version}), lib32gcc1-dbg (>= ${gcc:EpochVersion}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), lib32objc4 (= ${gcc:Version}), lib32gcc1-dbg (>= ${gcc:EpochVersion}), ${misc:Depends}
 Description: Runtime library for GNU Objective-C applications (32 bit debug symbols)
  Library needed for GNU ObjC applications linked against the shared library.
 
@@ -1313,7 +1369,7 @@ Package: libn32objc4
 Section: libs
 Architecture: mips mipsel mips64 mips64el
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Description: Runtime library for GNU Objective-C applications (n32)
  Library needed for GNU ObjC applications linked against the shared library.
 
@@ -1321,7 +1377,7 @@ Package: libn32objc4-dbg
 Section: debug
 Architecture: mips mipsel mips64 mips64el
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libn32objc4 (= ${gcc:Version}), libn32gcc1-dbg (>= ${gcc:EpochVersion}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libn32objc4 (= ${gcc:Version}), libn32gcc1-dbg (>= ${gcc:EpochVersion}), ${misc:Depends}
 Description: Runtime library for GNU Objective-C applications (n32 debug symbols)
  Library needed for GNU ObjC applications linked against the shared library.
 
@@ -1329,7 +1385,7 @@ Package: libx32objc4
 Section: libs
 Architecture: amd64 i386
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Description: Runtime library for GNU Objective-C applications (x32)
  Library needed for GNU ObjC applications linked against the shared library.
 
@@ -1337,26 +1393,26 @@ Package: libx32objc4-dbg
 Section: debug
 Architecture: amd64 i386
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libx32objc4 (= ${gcc:Version}), libx32gcc1-dbg (>= ${gcc:EpochVersion}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libx32objc4 (= ${gcc:Version}), libx32gcc1-dbg (>= ${gcc:EpochVersion}), ${misc:Depends}
 Description: Runtime library for GNU Objective-C applications (x32 debug symbols)
  Library needed for GNU ObjC applications linked against the shared library.
 
-Package: gfortran-4.9
+Package: gfortran-5
 Architecture: any
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), gcc-4.9 (= ${gcc:Version}), libgfortran-4.9-dev (= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), gcc-5 (= ${gcc:Version}), libgfortran-5-dev (= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends}
 Provides: fortran95-compiler, ${fortran:mod-version}
-Suggests: ${gfortran:multilib}, gfortran-4.9-doc, libgfortran3-dbg (>= ${gcc:Version})
+Suggests: ${gfortran:multilib}, gfortran-5-doc, libgfortran3-dbg (>= ${gcc:Version})
 Description: GNU Fortran compiler
  This is the GNU Fortran compiler, which compiles
  Fortran on platforms supported by the gcc compiler. It uses the
  gcc backend to generate optimized code.
 
-Package: gfortran-4.9-multilib
+Package: gfortran-5-multilib
 Architecture: amd64 i386 kfreebsd-amd64 mips mips64 mips64el mipsel mipsn32 mipsn32el powerpc ppc64 s390 s390x sparc sparc64 x32
 Section: devel
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), gfortran-4.9 (= ${gcc:Version}), gcc-4.9-multilib (= ${gcc:Version}), ${dep:libgfortranbiarchdev}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), gfortran-5 (= ${gcc:Version}), gcc-5-multilib (= ${gcc:Version}), ${dep:libgfortranbiarchdev}, ${shlibs:Depends}, ${misc:Depends}
 Description: GNU Fortran compiler (multilib files)
  This is the GNU Fortran compiler, which compiles Fortran on platforms
  supported by the gcc compiler.
@@ -1364,48 +1420,48 @@ Description: GNU Fortran compiler (multilib files)
  On architectures with multilib support, the package contains files
  and dependencies for the non-default multilib architecture(s).
 
-Package: libgfortran-4.9-dev
+Package: libgfortran-5-dev
 Architecture: any
 Section: libdevel
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), libgcc-4.9-dev (= ${gcc:Version}), libgfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libgcc-5-dev (= ${gcc:Version}), libgfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
 Multi-Arch: same
 Description: Runtime library for GNU Fortran applications (development files)
  This package contains the headers and static library files needed to build
  GNU Fortran applications.
 
-Package: lib64gfortran-4.9-dev
+Package: lib64gfortran-5-dev
 Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
 Section: libdevel
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), lib64gcc-4.9-dev (= ${gcc:Version}), lib64gfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), lib64gcc-5-dev (= ${gcc:Version}), lib64gfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
 Description: Runtime library for GNU Fortran applications (64bit development files)
  This package contains the headers and static library files needed to build
  GNU Fortran applications.
 
-Package: lib32gfortran-4.9-dev
+Package: lib32gfortran-5-dev
 Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
 Section: libdevel
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), lib32gcc-4.9-dev (= ${gcc:Version}), lib32gfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), lib32gcc-5-dev (= ${gcc:Version}), lib32gfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
 Description: Runtime library for GNU Fortran applications (32bit development files)
  This package contains the headers and static library files needed to build
  GNU Fortran applications.
 
-Package: libn32gfortran-4.9-dev
+Package: libn32gfortran-5-dev
 Architecture: mips mipsel mips64 mips64el
 Section: libdevel
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), libn32gcc-4.9-dev (= ${gcc:Version}), libn32gfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libn32gcc-5-dev (= ${gcc:Version}), libn32gfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
 Description: Runtime library for GNU Fortran applications (n32 development files)
  This package contains the headers and static library files needed to build
  GNU Fortran applications.
 
-Package: libx32gfortran-4.9-dev
+Package: libx32gfortran-5-dev
 Architecture: amd64 i386
 Section: libdevel
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), libx32gcc-4.9-dev (= ${gcc:Version}), libx32gfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libx32gcc-5-dev (= ${gcc:Version}), libx32gfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
 Description: Runtime library for GNU Fortran applications (x32 development files)
  This package contains the headers and static library files needed to build
  GNU Fortran applications.
@@ -1418,7 +1474,7 @@ Multi-Arch: same
 Pre-Depends: multiarch-support
 Breaks: ${multiarch:breaks}
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
 Description: Runtime library for GNU Fortran applications
  Library needed for GNU Fortran applications linked against the
  shared library.
@@ -1429,7 +1485,7 @@ Architecture: any
 Provides: libgfortran3-dbg-armel [armel], libgfortran3-dbg-armhf [armhf]
 Multi-Arch: same
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libgfortran3 (= ${gcc:Version}), libgcc1-dbg (>= ${libgcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libgfortran3 (= ${gcc:Version}), libgcc1-dbg (>= ${libgcc:Version}), ${misc:Depends}
 Description: Runtime library for GNU Fortran applications (debug symbols)
  Library needed for GNU Fortran applications linked against the
  shared library.
@@ -1438,7 +1494,7 @@ Package: lib64gfortran3
 Section: libs
 Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Description: Runtime library for GNU Fortran applications (64bit)
  Library needed for GNU Fortran applications linked against the
  shared library.
@@ -1447,7 +1503,7 @@ Package: lib64gfortran3-dbg
 Section: debug
 Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), lib64gfortran3 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), lib64gfortran3 (= ${gcc:Version}), ${misc:Depends}
 Description: Runtime library for GNU Fortran applications (64bit debug symbols)
  Library needed for GNU Fortran applications linked against the
  shared library.
@@ -1456,7 +1512,7 @@ Package: lib32gfortran3
 Section: libs
 Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Conflicts: ${confl:lib32}
 Description: Runtime library for GNU Fortran applications (32bit)
  Library needed for GNU Fortran applications linked against the
@@ -1466,7 +1522,7 @@ Package: lib32gfortran3-dbg
 Section: debug
 Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), lib32gfortran3 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), lib32gfortran3 (= ${gcc:Version}), ${misc:Depends}
 Description: Runtime library for GNU Fortran applications (32 bit debug symbols)
  Library needed for GNU Fortran applications linked against the
  shared library.
@@ -1475,7 +1531,7 @@ Package: libn32gfortran3
 Section: libs
 Architecture: mips mipsel mips64 mips64el
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Description: Runtime library for GNU Fortran applications (n32)
  Library needed for GNU Fortran applications linked against the
  shared library.
@@ -1484,7 +1540,7 @@ Package: libn32gfortran3-dbg
 Section: debug
 Architecture: mips mipsel mips64 mips64el
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libn32gfortran3 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libn32gfortran3 (= ${gcc:Version}), ${misc:Depends}
 Description: Runtime library for GNU Fortran applications (n32 debug symbols)
  Library needed for GNU Fortran applications linked against the
  shared library.
@@ -1493,7 +1549,7 @@ Package: libx32gfortran3
 Section: libs
 Architecture: amd64 i386
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Description: Runtime library for GNU Fortran applications (x32)
  Library needed for GNU Fortran applications linked against the
  shared library.
@@ -1502,26 +1558,26 @@ Package: libx32gfortran3-dbg
 Section: debug
 Architecture: amd64 i386
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libx32gfortran3 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libx32gfortran3 (= ${gcc:Version}), ${misc:Depends}
 Description: Runtime library for GNU Fortran applications (x32 debug symbols)
  Library needed for GNU Fortran applications linked against the
  shared library.
 
-Package: gccgo-4.9
+Package: gccgo-5
 Architecture: any
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), gcc-4.9 (= ${gcc:Version}), libgo5 (>= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), gcc-5 (= ${gcc:Version}), libgo7 (>= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends}
 Provides: go-compiler
-Suggests: ${go:multilib}, gccgo-4.9-doc, libgo5-dbg (>= ${gcc:Version})
+Suggests: ${go:multilib}, gccgo-5-doc, libgo7-dbg (>= ${gcc:Version})
 Description: GNU Go compiler
  This is the GNU Go compiler, which compiles Go on platforms supported
  by the gcc compiler. It uses the gcc backend to generate optimized code.
 
-Package: gccgo-4.9-multilib
+Package: gccgo-5-multilib
 Architecture: amd64 i386 kfreebsd-amd64 mips mips64 mips64el mipsel mipsn32 mipsn32el powerpc ppc64 s390 s390x sparc sparc64 x32
 Section: devel
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), gccgo-4.9 (= ${gcc:Version}), gcc-4.9-multilib (= ${gcc:Version}), ${dep:libgobiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), gccgo-5 (= ${gcc:Version}), gcc-5-multilib (= ${gcc:Version}), ${dep:libgobiarch}, ${shlibs:Depends}, ${misc:Depends}
 Suggests: ${dep:libgobiarchdbg}
 Description: GNU Go compiler (multilib files)
  This is the GNU Go compiler, which compiles Go on platforms supported
@@ -1530,125 +1586,125 @@ Description: GNU Go compiler (multilib files)
  On architectures with multilib support, the package contains files
  and dependencies for the non-default multilib architecture(s).
 
-Package: libgo5
+Package: libgo7
 Section: libs
 Architecture: any
-Provides: libgo5-armel [armel], libgo5-armhf [armhf]
+Provides: libgo7-armel [armel], libgo7-armhf [armhf]
 Multi-Arch: same
 Pre-Depends: multiarch-support
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
 Replaces: libgo3
 Description: Runtime library for GNU Go applications
  Library needed for GNU Go applications linked against the
  shared library.
 
-Package: libgo5-dbg
+Package: libgo7-dbg
 Section: debug
 Architecture: any
-Provides: libgo5-dbg-armel [armel], libgo5-dbg-armhf [armhf]
+Provides: libgo7-dbg-armel [armel], libgo7-dbg-armhf [armhf]
 Multi-Arch: same
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libgo5 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libgo7 (= ${gcc:Version}), ${misc:Depends}
 Description: Runtime library for GNU Go applications (debug symbols)
  Library needed for GNU Go applications linked against the
  shared library.
 
-Package: lib64go5
+Package: lib64go7
 Section: libs
 Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Replaces: lib64go3
 Description: Runtime library for GNU Go applications (64bit)
  Library needed for GNU Go applications linked against the
  shared library.
 
-Package: lib64go5-dbg
+Package: lib64go7-dbg
 Section: debug
 Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), lib64go5 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), lib64go7 (= ${gcc:Version}), ${misc:Depends}
 Description: Runtime library for GNU Go applications (64bit debug symbols)
  Library needed for GNU Go applications linked against the
  shared library.
 
-Package: lib32go5
+Package: lib32go7
 Section: libs
 Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Conflicts: ${confl:lib32}
 Replaces: lib32go3
 Description: Runtime library for GNU Go applications (32bit)
  Library needed for GNU Go applications linked against the
  shared library.
 
-Package: lib32go5-dbg
+Package: lib32go7-dbg
 Section: debug
 Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), lib32go5 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), lib32go7 (= ${gcc:Version}), ${misc:Depends}
 Description: Runtime library for GNU Go applications (32 bit debug symbols)
  Library needed for GNU Go applications linked against the
  shared library.
 
-Package: libn32go5
+Package: libn32go7
 Section: libs
 Architecture: mips mipsel mips64 mips64el
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Replaces: libn32go3
 Description: Runtime library for GNU Go applications (n32)
  Library needed for GNU Go applications linked against the
  shared library.
 
-Package: libn32go5-dbg
+Package: libn32go7-dbg
 Section: debug
 Architecture: mips mipsel mips64 mips64el
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libn32go5 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libn32go7 (= ${gcc:Version}), ${misc:Depends}
 Description: Runtime library for GNU Go applications (n32 debug symbols)
  Library needed for GNU Go applications linked against the
  shared library.
 
-Package: libx32go5
+Package: libx32go7
 Section: libs
 Architecture: amd64 i386
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
 Replaces: libx32go3
 Description: Runtime library for GNU Go applications (x32)
  Library needed for GNU Go applications linked against the
  shared library.
 
-Package: libx32go5-dbg
+Package: libx32go7-dbg
 Section: debug
 Architecture: amd64 i386
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libx32go5 (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libx32go7 (= ${gcc:Version}), ${misc:Depends}
 Description: Runtime library for GNU Go applications (x32 debug symbols)
  Library needed for GNU Go applications linked against the
  shared library.
 
-Package: gcj-4.9
+Package: gcj-5
 Section: java
 Architecture: any
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:gcj}, ${dep:gcjcross}, ${dep:libcdev}, ${dep:ecj}, ${shlibs:Depends}, dpkg (>= 1.15.4) | install-info, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:gcj}, ${dep:gcjcross}, ${dep:libcdev}, ${dep:ecj}, ${shlibs:Depends}, dpkg (>= 1.15.4) | install-info, ${misc:Depends}
 Recommends: libecj-java-gcj
 Description: GCJ byte code and native compiler for Java(TM)
  GCJ is a front end to the GCC compiler which can natively compile both
  Java(tm) source and bytecode files. The compiler can also generate class
  files.
 
-Package: gcj-4.9-jdk
+Package: gcj-5-jdk
 Section: java
 Architecture: any
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:gcj}, ${dep:libcdev}, gcj-4.9 (= ${gcj:Version}), gcj-4.9-jre (= ${gcj:Version}), libgcj15-dev (= ${gcj:Version}), fastjar, libgcj-bc, java-common, libantlr-java, ${shlibs:Depends}, dpkg (>= 1.15.4) | install-info, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:gcj}, ${dep:libcdev}, gcj-5 (= ${gcj:Version}), gcj-5-jre (= ${gcj:Version}), libgcj16-dev (= ${gcj:Version}), fastjar, libgcj-bc, java-common, libantlr-java, ${shlibs:Depends}, dpkg (>= 1.15.4) | install-info, ${misc:Depends}
 Recommends: libecj-java-gcj
-Suggests: gcj-4.9-source (>= ${gcj:SoftVersion}), libgcj15-dbg (>= ${gcc:Version})
+Suggests: gcj-5-source (>= ${gcj:SoftVersion}), libgcj16-dbg (>= ${gcc:Version})
 Provides: java-compiler, java-sdk, java2-sdk, java5-sdk
 Conflicts: gcj-4.4, cpp-4.1 (<< 4.1.1), gcc-4.1 (<< 4.1.1)
 Replaces: libgcj11 (<< 4.5-20100101-1)
@@ -1661,12 +1717,12 @@ Description: GCJ and Classpath development tools for Java(TM)
  The package contains as well a collection of wrapper scripts and symlinks.
  It is meant to provide a Java-SDK-like interface to the GCJ tool set.
 
-Package: gcj-4.9-jre-headless
+Package: gcj-5-jre-headless
 Priority: optional
 Section: java
 Architecture: any
-Depends: gcc-4.9-base (= ${gcc:Version}), gcj-4.9-jre-lib (>= ${gcj:SoftVersion}), libgcj15 (= ${gcj:Version}), ${dep:prctl}, ${shlibs:Depends}, ${misc:Depends}
-Suggests: fastjar, gcj-4.9-jdk (= ${gcj:Version}), libgcj15-awt (= ${gcj:Version})
+Depends: gcc-5-base (= ${gcc:Version}), gcj-5-jre-lib (>= ${gcj:SoftVersion}), libgcj16 (= ${gcj:Version}), ${dep:prctl}, ${shlibs:Depends}, ${misc:Depends}
+Suggests: fastjar, gcj-5-jdk (= ${gcj:Version}), libgcj16-awt (= ${gcj:Version})
 Provides: java5-runtime-headless, java2-runtime-headless, java1-runtime-headless, java-runtime-headless
 Description: Java runtime environment using GIJ/Classpath (headless version)
  GIJ is a Java bytecode interpreter, not limited to interpreting bytecode.
@@ -1678,11 +1734,11 @@ Description: Java runtime environment using GIJ/Classpath (headless version)
  It is meant to provide a Java-RTE-like interface to the GIJ/GCJ tool set,
  limited to the headless tools and libraries.
 
-Package: gcj-4.9-jre
+Package: gcj-5-jre
 Section: java
 Architecture: any
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), gcj-4.9-jre-headless (= ${gcj:Version}), libgcj15-awt (= ${gcj:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), gcj-5-jre-headless (= ${gcj:Version}), libgcj16-awt (= ${gcj:Version}), ${shlibs:Depends}, ${misc:Depends}
 Provides: java5-runtime, java2-runtime, java1-runtime, java-runtime
 Description: Java runtime environment using GIJ/Classpath
  GIJ is a Java bytecode interpreter, not limited to interpreting bytecode.
@@ -1693,75 +1749,75 @@ Description: Java runtime environment using GIJ/Classpath
  The package contains as well a collection of wrapper scripts and symlinks.
  It is meant to provide a Java-RTE-like interface to the GIJ/GCJ tool set.
 
-Package: libgcj15
+Package: libgcj16
 Section: libs
 Architecture: any
 Priority: optional
 Pre-Depends: multiarch-support
 Multi-Arch: same
-Depends: gcc-4.9-base (>= ${gcc:SoftVersion}), libgcj-common (>= 1:4.1.1-21), ${shlibs:Depends}, ${misc:Depends}
-Recommends: gcj-4.9-jre-lib (>= ${gcj:SoftVersion})
-Suggests: libgcj15-dbg (>= ${gcc:Version}), libgcj15-awt (= ${gcj:Version})
+Depends: gcc-5-base (>= ${gcc:SoftVersion}), libgcj-common (>= 1:4.1.1-21), ${shlibs:Depends}, ${misc:Depends}
+Recommends: gcj-5-jre-lib (>= ${gcj:SoftVersion})
+Suggests: libgcj16-dbg (>= ${gcc:Version}), libgcj16-awt (= ${gcj:Version})
 Description: Java runtime library for use with gcj
  This is the runtime that goes along with the gcj front end to
  gcc. libgcj includes parts of the Java Class Libraries, plus glue to
  connect the libraries to the compiler and the underlying OS.
  .
  To show file names and line numbers in stack traces, the packages
- libgcj15-dbg and binutils are required.
+ libgcj16-dbg and binutils are required.
 
-Package: gcj-4.9-jre-lib
+Package: gcj-5-jre-lib
 Section: java
 Architecture: all
 Priority: optional
-Depends: gcc-4.9-base (>= ${gcc:SoftVersion}), libgcj15 (>= ${gcj:SoftVersion}), ${misc:Depends}
+Depends: gcc-5-base (>= ${gcc:SoftVersion}), libgcj16 (>= ${gcj:SoftVersion}), ${misc:Depends}
 Description: Java runtime library for use with gcj (jar files)
  This is the jar file that goes along with the gcj front end to gcc.
 
-Package: libgcj15-awt
+Package: libgcj16-awt
 Section: libs
 Architecture: any
 Priority: optional
 Pre-Depends: multiarch-support
 Multi-Arch: same
-Depends: gcc-4.9-base (>= ${gcc:SoftVersion}), libgcj15 (= ${gcj:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (>= ${gcc:SoftVersion}), libgcj16 (= ${gcj:Version}), ${shlibs:Depends}, ${misc:Depends}
 Suggests: ${pkg:gcjqt}
 Description: AWT peer runtime libraries for use with gcj
  These are runtime libraries holding the AWT peer implementations
  for libgcj (currently the GTK+ based peer library is required, the
  QT bases library is not built).
 
-Package: libgcj15-dev
+Package: libgcj16-dev
 Section: libdevel
 Architecture: any
 Multi-Arch: same
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), libgcj15-awt (= ${gcj:Version}), libgcj-bc, ${pkg:gcjgtk}, ${pkg:gcjqt}, zlib1g-dev, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libgcj16-awt (= ${gcj:Version}), libgcj-bc, ${pkg:gcjgtk}, ${pkg:gcjqt}, zlib1g-dev, ${shlibs:Depends}, ${misc:Depends}
 Suggests: libgcj-doc
 Description: Java development headers for use with gcj
  These are the development headers that go along with the gcj front end
  to gcc. libgcj includes parts of the Java Class Libraries, plus glue
  to connect the libraries to the compiler and the underlying OS.
 
-Package: libgcj15-dbg
+Package: libgcj16-dbg
 Section: debug
 Architecture: any
 Priority: extra
 Pre-Depends: multiarch-support
 Multi-Arch: same
-Depends: gcc-4.9-base (= ${gcc:Version}), libgcj15 (= ${gcj:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libgcj16 (= ${gcj:Version}), ${misc:Depends}
 Recommends: binutils, libc6-dbg | libc-dbg
-Description: Debugging symbols for libraries provided in libgcj15-dev
+Description: Debugging symbols for libraries provided in libgcj16-dev
  The package provides debugging symbols for the libraries provided
- in libgcj15-dev.
+ in libgcj16-dev.
  .
  binutils is required to show file names and line numbers in stack traces.
 
-Package: gcj-4.9-source
+Package: gcj-5-source
 Section: java
 Architecture: all
 Priority: optional
-Depends: gcc-4.9-base (>= ${gcc:SoftVersion}), gcj-4.9-jdk (>= ${gcj:SoftVersion}), ${misc:Depends}
+Depends: gcc-5-base (>= ${gcc:SoftVersion}), gcj-5-jdk (>= ${gcj:SoftVersion}), ${misc:Depends}
 Description: GCJ java sources for use in IDEs like eclipse and netbeans
  These are the java source files packaged as a zip file for use in development
  environments like eclipse and netbeans.
@@ -1770,8 +1826,8 @@ Package: libgcj-doc
 Section: doc
 Architecture: all
 Priority: optional
-Depends: gcc-4.9-base (>= ${gcc:SoftVersion}), ${misc:Depends}
-Enhances: libgcj15-dev
+Depends: gcc-5-base (>= ${gcc:SoftVersion}), ${misc:Depends}
+Enhances: libgcj16-dev
 Provides: classpath-doc
 Description: libgcj API documentation and example programs
  Autogenerated documentation describing the API of the libgcj library.
@@ -1781,13 +1837,13 @@ Package: libstdc++6
 Architecture: any
 Section: libs
 Priority: important
-Depends: gcc-4.9-base (= ${gcc:Version}), ${dep:libc}, ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), ${dep:libc}, ${shlibs:Depends}, ${misc:Depends}
 Provides: libstdc++6-armel [armel], libstdc++6-armhf [armhf]
 Multi-Arch: same
 Pre-Depends: multiarch-support
 Breaks: ${multiarch:breaks}
 Conflicts: scim (<< 1.4.2-1)
-Replaces: libstdc++6-4.9-dbg (<< 4.9.0-3)
+Replaces: libstdc++6-5-dbg (<< 4.9.0-3)
 Description: GNU Standard C++ Library v3
  This package contains an additional runtime library for C++ programs
  built with the GNU compiler.
@@ -1800,7 +1856,7 @@ Package: lib32stdc++6
 Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
 Section: libs
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), lib32gcc1 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), lib32gcc1 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
 Conflicts: ${confl:lib32}
 Description: GNU Standard C++ Library v3 (32 bit Version)
  This package contains an additional runtime library for C++ programs
@@ -1810,7 +1866,7 @@ Package: lib64stdc++6
 Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
 Section: libs
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), lib64gcc1 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), lib64gcc1 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
 Description: GNU Standard C++ Library v3 (64bit)
  This package contains an additional runtime library for C++ programs
  built with the GNU compiler.
@@ -1823,7 +1879,7 @@ Package: libn32stdc++6
 Architecture: mips mipsel mips64 mips64el
 Section: libs
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), libn32gcc1 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libn32gcc1 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
 Description: GNU Standard C++ Library v3 (n32)
  This package contains an additional runtime library for C++ programs
  built with the GNU compiler.
@@ -1836,7 +1892,7 @@ Package: libx32stdc++6
 Architecture: amd64 i386
 Section: libs
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), libx32gcc1 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libx32gcc1 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
 Description: GNU Standard C++ Library v3 (x32)
  This package contains an additional runtime library for C++ programs
  built with the GNU compiler.
@@ -1845,17 +1901,17 @@ Description: GNU Standard C++ Library v3 (x32)
  was included up to g++-2.95. The first version of libstdc++-v3 appeared
  in g++-3.0.
 
-Package: libstdc++-4.9-dev
+Package: libstdc++-5-dev
 Architecture: any
 Multi-Arch: same
 Section: libdevel
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), libgcc-4.9-dev (= ${gcc:Version}),
+Depends: gcc-5-base (= ${gcc:Version}), libgcc-5-dev (= ${gcc:Version}),
  libstdc++6 (>= ${gcc:Version}), ${dep:libcdev}, ${misc:Depends}
 Conflicts: libg++27-dev, libg++272-dev (<< 2.7.2.8-1), libstdc++2.8-dev,
  libg++2.8-dev, libstdc++2.9-dev, libstdc++2.9-glibc2.1-dev,
  libstdc++2.10-dev (<< 1:2.95.3-2), libstdc++3.0-dev
-Suggests: libstdc++-4.9-doc
+Suggests: libstdc++-5-doc
 Provides: libstdc++-dev
 Description: GNU Standard C++ Library v3 (development files)
  This package contains the headers and static library files necessary for
@@ -1865,28 +1921,28 @@ Description: GNU Standard C++ Library v3 (development files)
  was included up to g++-2.95. The first version of libstdc++-v3 appeared
  in g++-3.0.
 
-Package: libstdc++-4.9-pic
+Package: libstdc++-5-pic
 Architecture: any
 Multi-Arch: same
 Section: libdevel
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libstdc++6 (>= ${gcc:Version}),
- libstdc++-4.9-dev (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libstdc++6 (>= ${gcc:Version}),
+ libstdc++-5-dev (= ${gcc:Version}), ${misc:Depends}
 Description: GNU Standard C++ Library v3 (shared library subset kit)
  This is used to develop subsets of the libstdc++ shared libraries for
  use on custom installation floppies and in embedded systems.
  .
  Unless you are making one of those, you will not need this package.
 
-Package: libstdc++6-4.9-dbg
+Package: libstdc++6-5-dbg
 Architecture: any
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libstdc++6 (>= ${gcc:Version}),
+Depends: gcc-5-base (= ${gcc:Version}), libstdc++6 (>= ${gcc:Version}),
  libgcc1-dbg (>= ${libgcc:Version}), ${shlibs:Depends}, ${misc:Depends}
-Provides: libstdc++6-4.9-dbg-armel [armel], libstdc++6-4.9-dbg-armhf [armhf]
+Provides: libstdc++6-5-dbg-armel [armel], libstdc++6-5-dbg-armhf [armhf]
 Multi-Arch: same
-Recommends: libstdc++-4.9-dev (= ${gcc:Version})
+Recommends: libstdc++-5-dev (= ${gcc:Version})
 Conflicts: libstdc++5-dbg, libstdc++5-3.3-dbg, libstdc++6-dbg,
  libstdc++6-4.0-dbg, libstdc++6-4.1-dbg, libstdc++6-4.2-dbg,
  libstdc++6-4.3-dbg, libstdc++6-4.4-dbg, libstdc++6-4.5-dbg,
@@ -1895,12 +1951,12 @@ Description: GNU Standard C++ Library v3 (debugging files)
  This package contains the shared library of libstdc++ compiled with
  debugging symbols.
 
-Package: lib32stdc++-4.9-dev
+Package: lib32stdc++-5-dev
 Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
 Section: libdevel
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), lib32gcc-4.9-dev (= ${gcc:Version}),
- lib32stdc++6 (>= ${gcc:Version}), libstdc++-4.9-dev (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), lib32gcc-5-dev (= ${gcc:Version}),
+ lib32stdc++6 (>= ${gcc:Version}), libstdc++-5-dev (= ${gcc:Version}), ${misc:Depends}
 Description: GNU Standard C++ Library v3 (development files)
  This package contains the headers and static library files necessary for
  building C++ programs which use libstdc++.
@@ -1909,12 +1965,12 @@ Description: GNU Standard C++ Library v3 (development files)
  was included up to g++-2.95. The first version of libstdc++-v3 appeared
  in g++-3.0.
 
-Package: lib32stdc++6-4.9-dbg
+Package: lib32stdc++6-5-dbg
 Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), lib32stdc++6 (>= ${gcc:Version}),
- libstdc++-4.9-dev (= ${gcc:Version}), lib32gcc1-dbg (>= ${gcc:EpochVersion}),
+Depends: gcc-5-base (= ${gcc:Version}), lib32stdc++6 (>= ${gcc:Version}),
+ libstdc++-5-dev (= ${gcc:Version}), lib32gcc1-dbg (>= ${gcc:EpochVersion}),
  ${shlibs:Depends}, ${misc:Depends}
 Conflicts: lib32stdc++6-dbg, lib32stdc++6-4.0-dbg,
  lib32stdc++6-4.1-dbg, lib32stdc++6-4.2-dbg, lib32stdc++6-4.3-dbg,
@@ -1924,12 +1980,12 @@ Description: GNU Standard C++ Library v3 (debugging files)
  This package contains the shared library of libstdc++ compiled with
  debugging symbols.
 
-Package: lib64stdc++-4.9-dev
+Package: lib64stdc++-5-dev
 Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
 Section: libdevel
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), lib64gcc-4.9-dev (= ${gcc:Version}),
- lib64stdc++6 (>= ${gcc:Version}), libstdc++-4.9-dev (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), lib64gcc-5-dev (= ${gcc:Version}),
+ lib64stdc++6 (>= ${gcc:Version}), libstdc++-5-dev (= ${gcc:Version}), ${misc:Depends}
 Description: GNU Standard C++ Library v3 (development files)
  This package contains the headers and static library files necessary for
  building C++ programs which use libstdc++.
@@ -1938,12 +1994,12 @@ Description: GNU Standard C++ Library v3 (development files)
  was included up to g++-2.95. The first version of libstdc++-v3 appeared
  in g++-3.0.
 
-Package: lib64stdc++6-4.9-dbg
+Package: lib64stdc++6-5-dbg
 Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), lib64stdc++6 (>= ${gcc:Version}),
- libstdc++-4.9-dev (= ${gcc:Version}), lib64gcc1-dbg (>= ${gcc:EpochVersion}),
+Depends: gcc-5-base (= ${gcc:Version}), lib64stdc++6 (>= ${gcc:Version}),
+ libstdc++-5-dev (= ${gcc:Version}), lib64gcc1-dbg (>= ${gcc:EpochVersion}),
  ${shlibs:Depends}, ${misc:Depends}
 Conflicts: lib64stdc++6-dbg, lib64stdc++6-4.0-dbg,
  lib64stdc++6-4.1-dbg, lib64stdc++6-4.2-dbg, lib64stdc++6-4.3-dbg,
@@ -1953,12 +2009,12 @@ Description: GNU Standard C++ Library v3 (debugging files)
  This package contains the shared library of libstdc++ compiled with
  debugging symbols.
 
-Package: libn32stdc++-4.9-dev
+Package: libn32stdc++-5-dev
 Architecture: mips mipsel mips64 mips64el
 Section: libdevel
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), libn32gcc-4.9-dev (= ${gcc:Version}),
- libn32stdc++6 (>= ${gcc:Version}), libstdc++-4.9-dev (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libn32gcc-5-dev (= ${gcc:Version}),
+ libn32stdc++6 (>= ${gcc:Version}), libstdc++-5-dev (= ${gcc:Version}), ${misc:Depends}
 Description: GNU Standard C++ Library v3 (development files)
  This package contains the headers and static library files necessary for
  building C++ programs which use libstdc++.
@@ -1967,12 +2023,12 @@ Description: GNU Standard C++ Library v3 (development files)
  was included up to g++-2.95. The first version of libstdc++-v3 appeared
  in g++-3.0.
 
-Package: libn32stdc++6-4.9-dbg
+Package: libn32stdc++6-5-dbg
 Architecture: mips mipsel mips64 mips64el
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libn32stdc++6 (>= ${gcc:Version}),
- libstdc++-4.9-dev (= ${gcc:Version}), libn32gcc1-dbg (>= ${gcc:EpochVersion}),
+Depends: gcc-5-base (= ${gcc:Version}), libn32stdc++6 (>= ${gcc:Version}),
+ libstdc++-5-dev (= ${gcc:Version}), libn32gcc1-dbg (>= ${gcc:EpochVersion}),
  ${shlibs:Depends}, ${misc:Depends}
 Conflicts: libn32stdc++6-dbg, libn32stdc++6-4.0-dbg,
  libn32stdc++6-4.1-dbg, libn32stdc++6-4.2-dbg, libn32stdc++6-4.3-dbg,
@@ -1982,12 +2038,12 @@ Description: GNU Standard C++ Library v3 (debugging files)
  This package contains the shared library of libstdc++ compiled with
  debugging symbols.
 
-Package: libx32stdc++-4.9-dev
+Package: libx32stdc++-5-dev
 Architecture: amd64 i386
 Section: libdevel
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), libx32gcc-4.9-dev (= ${gcc:Version}), libx32stdc++6 (>= ${gcc:Version}),
- libstdc++-4.9-dev (= ${gcc:Version}), ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), libx32gcc-5-dev (= ${gcc:Version}), libx32stdc++6 (>= ${gcc:Version}),
+ libstdc++-5-dev (= ${gcc:Version}), ${misc:Depends}
 Description: GNU Standard C++ Library v3 (development files)
  This package contains the headers and static library files necessary for
  building C++ programs which use libstdc++.
@@ -1996,12 +2052,12 @@ Description: GNU Standard C++ Library v3 (development files)
  was included up to g++-2.95. The first version of libstdc++-v3 appeared
  in g++-3.0.
 
-Package: libx32stdc++6-4.9-dbg
+Package: libx32stdc++6-5-dbg
 Architecture: amd64 i386
 Section: debug
 Priority: extra
-Depends: gcc-4.9-base (= ${gcc:Version}), libx32stdc++6 (>= ${gcc:Version}),
- libstdc++-4.9-dev (= ${gcc:Version}), libx32gcc1-dbg (>= ${gcc:EpochVersion}),
+Depends: gcc-5-base (= ${gcc:Version}), libx32stdc++6 (>= ${gcc:Version}),
+ libstdc++-5-dev (= ${gcc:Version}), libx32gcc1-dbg (>= ${gcc:EpochVersion}),
  ${shlibs:Depends}, ${misc:Depends}
 Conflicts: libx32stdc++6-dbg, libx32stdc++6-4.6-dbg,
  libx32stdc++6-4.7-dbg, libx32stdc++6-4.8-dbg
@@ -2009,11 +2065,11 @@ Description: GNU Standard C++ Library v3 (debugging files)
  This package contains the shared library of libstdc++ compiled with
  debugging symbols.
 
-Package: libstdc++-4.9-doc
+Package: libstdc++-5-doc
 Architecture: all
 Section: doc
 Priority: optional
-Depends: gcc-4.9-base (>= ${gcc:SoftVersion}), ${misc:Depends}
+Depends: gcc-5-base (>= ${gcc:SoftVersion}), ${misc:Depends}
 Conflicts: libstdc++5-doc, libstdc++5-3.3-doc, libstdc++6-doc,
  libstdc++6-4.0-doc, libstdc++6-4.1-doc, libstdc++6-4.2-doc, libstdc++6-4.3-doc,
  libstdc++6-4.4-doc, libstdc++6-4.5-doc, libstdc++6-4.6-doc, libstdc++6-4.7-doc,
@@ -2026,40 +2082,6 @@ Description: GNU Standard C++ Library v3 (documentation files)
  alphabetical list, compound list, file list, namespace members,
  compound members and file members.
 
-Package: gdc-4.9
-Architecture: any
-Priority: optional
-Depends: gcc-4.9-base (>= ${gcc:SoftVersion}), g++-4.9 (>= ${gcc:SoftVersion}), ${dep:gdccross}, ${dep:phobosdev}, ${shlibs:Depends}, ${misc:Depends}
-Provides: gdc, d-compiler, d-v2-compiler
-Replaces: gdc (<< 4.4.6-5)
-Description: GNU D compiler (version 2), based on the GCC backend
- This is the GNU D compiler, which compiles D on platforms supported by gcc.
- It uses the gcc backend to generate optimised code.
- .
- This compiler supports D language version 2.
-
-Package: libphobos-4.9-dev
-Architecture: amd64 armel armhf i386 x32 kfreebsd-amd64 kfreebsd-i386
-Section: libdevel
-Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), zlib1g-dev, ${shlibs:Depends}, ${misc:Depends}
-Description: Phobos D standard library
- This is the Phobos standard library that comes with the D2 compiler.
- .
- For more information check http://www.dlang.org/phobos/
-
-#Package: libphobos`'PHOBOS_V`'PV`'TS-dbg
-#Section: debug
-#Architecture: ifdef(`TARGET',`CROSS_ARCH',`libphobos_archs')
-#Priority: extra
-#Depends: BASEDEP, libphobos`'PHOBOS_V`'PV-dev (= ${gdc:Version}), ${misc:Depends}
-#Provides: libphobos`'PHOBOS_V`'TS-dbg
-#BUILT_USING`'dnl
-#Description: The Phobos D standard library (debug symbols)
-# This is the Phobos standard library that comes with the D2 compiler.
-# .
-# For more information check http://www.dlang.org/phobos/
-
 #Package: gcc`'PV-soft-float
 #Architecture: arm armel armhf
 #Priority: PRI(optional)
@@ -2073,7 +2095,7 @@ Description: Phobos D standard library
 Package: fixincludes
 Architecture: any
 Priority: optional
-Depends: gcc-4.9-base (= ${gcc:Version}), gcc-4.9 (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Depends: gcc-5-base (= ${gcc:Version}), gcc-5 (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
 Description: Fix non-ANSI header files
  FixIncludes was created to fix non-ANSI system header files. Many
  system manufacturers supply proprietary headers that are not ANSI compliant.
@@ -2084,7 +2106,7 @@ Description: Fix non-ANSI header files
  package is built, so we make fixincludes available at build time of other
  packages, such that checking tools like lintian can make use of it.
 
-Package: gcc-4.9-source
+Package: gcc-5-source
 Architecture: all
 Priority: optional
 Depends: make, autoconf2.64, quilt, patchutils, gawk, ${misc:Depends}
diff --git a/debian/control.m4 b/debian/control.m4
index 452e86d..e409575 100644
--- a/debian/control.m4
+++ b/debian/control.m4
@@ -740,6 +740,7 @@ Architecture: any
 Section: devel
 Priority: ifdef(`TARGET',`extra',`PRI(optional)')
 Depends: cpp`'PV`'TS (= ${gcc:Version}),ifenabled(`gccbase',` BASEDEP,')
+  libcc1-`'CC1_SO (= ${gcc:Version}),
   binutils`'TS (>= ${binutils:Version}),
   ${dep:libgccdev}, ${shlibs:Depends}, ${misc:Depends}
 Recommends: ${dep:libcdev}
@@ -2972,6 +2973,71 @@ Description: GCC Quad-Precision Math Library (hard float ABI debug symbols)
 ')`'dnl libsfqmath
 ')`'dnl libqmath
 
+Package: libcc1-`'CC1_SO
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: multiarch-support
+')`'dnl
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC cc1 plugin for GDB
+ libcc1 is a plugin for GDB.
+
+ifenabled(`libjit',`
+Package: libgccjit`'GCCJIT_SO
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: multiarch-support
+')`'dnl
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC just-in-time compilation (shared library)
+ libgccjit provides an embeddable shared library with an API for adding
+ compilation to existing programs using GCC.
+
+Package: libgccjit`'PV-dev
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: multiarch-support
+')`'dnl
+Priority: ifdef(`TARGET',`extra',`PRI(optional)')
+Depends: BASEDEP, libgccjit`'GCCJIT_SO (= ${gcc:Version}),
+ ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Suggests: libgccjit`'PV-dbg
+Description: GCC just-in-time compilation (development files)
+ libgccjit provides an embeddable shared library with an API for adding
+ compilation to existing programs using GCC.
+
+Package: libgccjit`'PV-dbg
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: multiarch-support
+')`'dnl
+Priority: extra
+Depends: BASEDEP, libgccjit`'GCCJIT_SO (= ${gcc:Version}),
+ ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC just-in-time compilation (debug information)
+ libgccjit provides an embeddable shared library with an API for adding
+ compilation to existing programs using GCC.
+
+Package: libgccjit`'PV-doc
+Section: doc
+Architecture: all
+Priority: extra
+Depends: BASEDEP, ${misc:Depends}
+Description: GCC just-in-time compilation (documentation)
+ libgccjit provides an embeddable shared library with an API for adding
+ compilation to existing programs using GCC.
+')`'dnl libjit
+
 ifenabled(`objpp',`
 ifenabled(`objppdev',`
 Package: gobjc++`'PV`'TS
diff --git a/debian/copyright b/debian/copyright
index 7ad2635..4b278d7 100644
--- a/debian/copyright
+++ b/debian/copyright
@@ -10,7 +10,7 @@ Packaging is done by the Debian GCC Maintainers
   svn://gcc.gnu.org/svn/gcc/           (for prereleases)
   http://bitbucket.org/goshawk/gdc     (for D)
 
-The current gcc-4.9 source package is taken from the SVN gcc-4_9-branch.
+The current gcc-5 source package is taken from the SVN gcc-5-branch.
 
 Changes: See changelog.Debian.gz
 
@@ -19,15 +19,15 @@ library, and documentation as follows:
 
 Language       Compiler package  Library package    Documentation
 ---------------------------------------------------------------------------
-Ada            gnat-4.9          libgnat-4.9        gnat-4.9-doc
-C              gcc-4.9                              gcc-4.9-doc
-C++            g++-4.9           libstdc++6         libstdc++6-4.9-doc
-D              gdc-4.9
-Fortran 95     gfortran-4.9      libgfortran3       gfortran-4.9-doc
-Go             gccgo-4.9         libgo0
-Java           gcj-4.9           libgcj10           libgcj-doc
-Objective C    gobjc-4.9         libobjc2
-Objective C++  gobjc++-4.9
+Ada            gnat-5          libgnat-5        gnat-5-doc
+C              gcc-5                              gcc-5-doc
+C++            g++-5           libstdc++6         libstdc++6-5-doc
+D              gdc-5
+Fortran 95     gfortran-5      libgfortran3       gfortran-5-doc
+Go             gccgo-5         libgo0
+Java           gcj-5           libgcj10           libgcj-doc
+Objective C    gobjc-5         libobjc2
+Objective C++  gobjc++-5
 
 For some language run-time libraries, Debian provides source files,
 development files, debugging symbols and libraries containing position-
@@ -35,24 +35,24 @@ independent code in separate packages:
 
 Language  Sources      Development   Debugging            Position-Independent
 ------------------------------------------------------------------------------
-C++                                  libstdc++6-4.9-dbg  libstdc++6-4.9-pic
-D         libphobos-4.9-dev
+C++                                  libstdc++6-5-dbg  libstdc++6-5-pic
+D         libphobos-5-dev
 Java      libgcj10-src libgcj10-dev  libgcj10-dbg
 
 Additional packages include:
 
 All languages:
 libgcc1, libgcc2, libgcc4       GCC intrinsics (platform-dependent)
-gcc-4.9-base                    Base files common to all compilers
-gcc-4.9-soft-float              Software floating point (ARM only)
-gcc-4.9-source                  The sources with patches
+gcc-5-base                    Base files common to all compilers
+gcc-5-soft-float              Software floating point (ARM only)
+gcc-5-source                  The sources with patches
 
 Ada:
-libgnatvsn-dev, libgnatvsn4.9   GNAT version library
-libgnatprj-dev, libgnatprj4.9   GNAT Project Manager library
+libgnatvsn-dev, libgnatvsn5   GNAT version library
+libgnatprj-dev, libgnatprj5   GNAT Project Manager library
 
 C:
-cpp-4.9, cpp-4.9-doc            GNU C Preprocessor
+cpp-5, cpp-5-doc            GNU C Preprocessor
 libssp0-dev, libssp0            GCC stack smashing protection library
 libquadmath0                    Math routines for the __float128 type
 fixincludes                     Fix non-ANSI header files
@@ -120,7 +120,7 @@ Runtime Library Exception (included in this file):
  - libstdc++-v3
  - libobjc
  - libgfortran
- - The libgnat-4.9 Ada support library and libgnatvsn library.
+ - The libgnat-5 Ada support library and libgnatvsn library.
  - Various config files in gcc/config/ used in runtime libraries.
  - libvtv
 
@@ -602,8 +602,8 @@ libcilkrts:
 
 
 D:
-gdc-4.9                         GNU D Compiler
-libphobos-4.9-dev               D standard runtime library
+gdc-5                         GNU D Compiler
+libphobos-5-dev               D standard runtime library
 
 The D source package is made up of the following components.
 
diff --git a/debian/gij-hppa b/debian/gij-hppa
index 8ecffdf..49d7f4e 100644
--- a/debian/gij-hppa
+++ b/debian/gij-hppa
@@ -7,4 +7,4 @@ case "$(prctl --unaligned=)" in *signal)
     prctl="prctl --unaligned=default"
 esac
 
-exec $prctl /usr/bin/gij-4.9.bin "$@"
+exec $prctl /usr/bin/gij-5.bin "$@"
diff --git a/debian/libasan.symbols.common b/debian/libasan.symbols.common
index b27d381..8782c5e 100644
--- a/debian/libasan.symbols.common
+++ b/debian/libasan.symbols.common
@@ -2,8 +2,11 @@
  _ZN11__sanitizer7OnPrintEPKc@Base 4.9
  _ZdaPv@Base 4.8
  _ZdaPvRKSt9nothrow_t@Base 4.8
+ _ZdaPvm@Base 5
  _ZdlPv@Base 4.8
  _ZdlPvRKSt9nothrow_t@Base 4.8
+ _ZdlPvm@Base 5
+ __asan_addr_is_in_fake_stack@Base 5
  __asan_address_is_poisoned@Base 4.8
  __asan_after_dynamic_init@Base 4.8
  __asan_backtrace_alloc@Base 4.9
@@ -36,15 +39,19 @@
  __asan_cplus_demangle_v3@Base 4.9
  __asan_cplus_demangle_v3_callback@Base 4.9
  __asan_describe_address@Base 4.8
- __asan_get_allocated_size@Base 4.8
- __asan_get_current_allocated_bytes@Base 4.8
- __asan_get_estimated_allocated_size@Base 4.8
- __asan_get_free_bytes@Base 4.8
- __asan_get_heap_size@Base 4.8
- __asan_get_ownership@Base 4.8
- __asan_get_unmapped_bytes@Base 4.8
+ __asan_get_alloc_stack@Base 5
+ __asan_get_current_fake_stack@Base 5
+ __asan_get_free_stack@Base 5
+ __asan_get_report_access_size@Base 5
+ __asan_get_report_access_type@Base 5
+ __asan_get_report_address@Base 5
+ __asan_get_report_bp@Base 5
+ __asan_get_report_description@Base 5
+ __asan_get_report_pc@Base 5
+ __asan_get_report_sp@Base 5
+ __asan_get_shadow_mapping@Base 5
  __asan_handle_no_return@Base 4.8
- __asan_init_v3@Base 4.9
+ __asan_init_v4@Base 5
  __asan_internal_memcmp@Base 4.9
  __asan_internal_memcpy@Base 4.9
  __asan_internal_memset@Base 4.9
@@ -56,7 +63,20 @@
  __asan_is_gnu_v3_mangled_dtor@Base 4.9
  __asan_java_demangle_v3@Base 4.9
  __asan_java_demangle_v3_callback@Base 4.9
+ __asan_load16@Base 5
+ __asan_load1@Base 5
+ __asan_load2@Base 5
+ __asan_load4@Base 5
+ __asan_load8@Base 5
+ __asan_loadN@Base 5
+ __asan_load_cxx_array_cookie@Base 5
+ __asan_locate_address@Base 5
+ __asan_memcpy@Base 5
+ __asan_memmove@Base 5
+ __asan_memset@Base 5
  __asan_option_detect_stack_use_after_return@Base 4.9
+ __asan_poison_cxx_array_cookie@Base 5
+ __asan_poison_intra_object_redzone@Base 5
  __asan_poison_memory_region@Base 4.8
  __asan_poison_stack_memory@Base 4.8
  __asan_print_accumulated_stats@Base 4.8
@@ -69,12 +89,14 @@
  __asan_report_load4@Base 4.8
  __asan_report_load8@Base 4.8
  __asan_report_load_n@Base 4.8
+ __asan_report_present@Base 5
  __asan_report_store16@Base 4.8
  __asan_report_store1@Base 4.8
  __asan_report_store2@Base 4.8
  __asan_report_store4@Base 4.8
  __asan_report_store8@Base 4.8
  __asan_report_store_n@Base 4.8
+ __asan_rt_version@Base 5
  __asan_set_death_callback@Base 4.8
  __asan_set_error_exit_code@Base 4.8
  __asan_set_error_report_callback@Base 4.8
@@ -100,27 +122,57 @@
  __asan_stack_malloc_7@Base 4.9
  __asan_stack_malloc_8@Base 4.9
  __asan_stack_malloc_9@Base 4.9
+ __asan_store16@Base 5
+ __asan_store1@Base 5
+ __asan_store2@Base 5
+ __asan_store4@Base 5
+ __asan_store8@Base 5
+ __asan_storeN@Base 5
+ __asan_test_only_reported_buggy_pointer@Base 5
+ __asan_unpoison_intra_object_redzone@Base 5
  __asan_unpoison_memory_region@Base 4.8
  __asan_unpoison_stack_memory@Base 4.8
  __asan_unregister_globals@Base 4.8
  __cxa_atexit@Base 4.9
  __cxa_throw@Base 4.8
+ __getdelim@Base 5
  __interceptor___cxa_atexit@Base 4.9
  __interceptor___cxa_throw@Base 4.8
+ __interceptor___getdelim@Base 5
+ __interceptor___isoc99_fprintf@Base 5
  __interceptor___isoc99_fscanf@Base 4.8
+ __interceptor___isoc99_printf@Base 5
  __interceptor___isoc99_scanf@Base 4.8
+ __interceptor___isoc99_snprintf@Base 5
+ __interceptor___isoc99_sprintf@Base 5
  __interceptor___isoc99_sscanf@Base 4.8
+ __interceptor___isoc99_vfprintf@Base 5
  __interceptor___isoc99_vfscanf@Base 4.8
+ __interceptor___isoc99_vprintf@Base 5
  __interceptor___isoc99_vscanf@Base 4.8
+ __interceptor___isoc99_vsnprintf@Base 5
+ __interceptor___isoc99_vsprintf@Base 5
  __interceptor___isoc99_vsscanf@Base 4.8
  __interceptor___libc_memalign@Base 4.8
+ __interceptor___overflow@Base 5
+ __interceptor___tls_get_addr@Base 5
+ __interceptor___uflow@Base 5
+ __interceptor___underflow@Base 5
+ __interceptor___woverflow@Base 5
+ __interceptor___wuflow@Base 5
+ __interceptor___wunderflow@Base 5
  __interceptor___xpg_strerror_r@Base 4.9
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  __interceptor__longjmp@Base 4.8
+ __interceptor__obstack_begin@Base 5
+ __interceptor__obstack_begin_1@Base 5
+ __interceptor__obstack_newchunk@Base 5
  __interceptor_accept4@Base 4.9
  __interceptor_accept@Base 4.9
+ __interceptor_aligned_alloc@Base 5
  __interceptor_asctime@Base 4.8
  __interceptor_asctime_r@Base 4.8
+ __interceptor_asprintf@Base 5
  __interceptor_atoi@Base 4.8
  __interceptor_atol@Base 4.8
  __interceptor_atoll@Base 4.8
@@ -128,6 +180,8 @@
  __interceptor_backtrace_symbols@Base 4.9
  __interceptor_calloc@Base 4.8
  __interceptor_canonicalize_file_name@Base 4.9
+ __interceptor_capget@Base 5
+ __interceptor_capset@Base 5
  __interceptor_cfree@Base 4.8
  __interceptor_clock_getres@Base 4.9
  __interceptor_clock_gettime@Base 4.9
@@ -135,7 +189,11 @@
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  __interceptor_ctime@Base 4.8
  __interceptor_ctime_r@Base 4.8
+ __interceptor_dlclose@Base 5
+ __interceptor_dlopen@Base 5
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+ __interceptor_endgrent@Base 5
+ __interceptor_endpwent@Base 5
  __interceptor_ether_aton@Base 4.9
  __interceptor_ether_aton_r@Base 4.9
  __interceptor_ether_hostton@Base 4.9
@@ -143,7 +201,23 @@
  __interceptor_ether_ntoa@Base 4.9
  __interceptor_ether_ntoa_r@Base 4.9
  __interceptor_ether_ntohost@Base 4.9
+ __interceptor_fclose@Base 5
+ __interceptor_fdopen@Base 5
+ __interceptor_fflush@Base 5
+ __interceptor_fgetgrent@Base 5
+ __interceptor_fgetgrent_r@Base 5
+ __interceptor_fgetpwent@Base 5
+ __interceptor_fgetpwent_r@Base 5
+ __interceptor_fgetxattr@Base 5
+ __interceptor_flistxattr@Base 5
+ __interceptor_fmemopen@Base 5
+ __interceptor_fopen64@Base 5
+ __interceptor_fopen@Base 5
+ __interceptor_fork@Base 5
+ __interceptor_fprintf@Base 5
  __interceptor_free@Base 4.8
+ __interceptor_freopen64@Base 5
+ __interceptor_freopen@Base 5
  __interceptor_frexp@Base 4.9
  __interceptor_frexpf@Base 4.9
  __interceptor_frexpl@Base 4.9
@@ -152,10 +226,13 @@
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  __interceptor_fstatvfs64@Base 4.9
  __interceptor_fstatvfs@Base 4.9
+ __interceptor_ftime@Base 5
  __interceptor_get_current_dir_name@Base 4.9
  __interceptor_getaddrinfo@Base 4.9
  __interceptor_getcwd@Base 4.9
  __interceptor_getdelim@Base 4.9
+ __interceptor_getgrent@Base 5
+ __interceptor_getgrent_r@Base 5
  __interceptor_getgrgid@Base 4.9
  __interceptor_getgrgid_r@Base 4.9
  __interceptor_getgrnam@Base 4.9
@@ -169,23 +246,32 @@
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  __interceptor_gethostent@Base 4.9
  __interceptor_gethostent_r@Base 4.9
+ __interceptor_getifaddrs@Base 5
  __interceptor_getitimer@Base 4.9
  __interceptor_getline@Base 4.9
  __interceptor_getmntent@Base 4.9
  __interceptor_getmntent_r@Base 4.9
  __interceptor_getnameinfo@Base 4.9
+ __interceptor_getpass@Base 5
  __interceptor_getpeername@Base 4.9
+ __interceptor_getpwent@Base 5
+ __interceptor_getpwent_r@Base 5
  __interceptor_getpwnam@Base 4.9
  __interceptor_getpwnam_r@Base 4.9
  __interceptor_getpwuid@Base 4.9
  __interceptor_getpwuid_r@Base 4.9
+ __interceptor_getresgid@Base 5
+ __interceptor_getresuid@Base 5
  __interceptor_getsockname@Base 4.9
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+ __interceptor_getxattr@Base 5
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  __interceptor_glob@Base 4.9
  __interceptor_gmtime@Base 4.8
  __interceptor_gmtime_r@Base 4.8
  __interceptor_iconv@Base 4.9
+ __interceptor_if_indextoname@Base 5
+ __interceptor_if_nametoindex@Base 5
  __interceptor_index@Base 4.8
  __interceptor_inet_aton@Base 4.9
  __interceptor_inet_ntop@Base 4.9
@@ -198,6 +284,9 @@
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  __interceptor_lgammal@Base 4.9
  __interceptor_lgammal_r@Base 4.9
+ __interceptor_lgetxattr@Base 5
+ __interceptor_listxattr@Base 5
+ __interceptor_llistxattr@Base 5
  __interceptor_localtime@Base 4.8
  __interceptor_localtime_r@Base 4.8
  __interceptor_longjmp@Base 4.8
@@ -211,10 +300,13 @@
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  __interceptor_mbstowcs@Base 4.9
  __interceptor_memalign@Base 4.8
+ __interceptor_memchr@Base 5
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  __interceptor_memcpy@Base 4.8
  __interceptor_memmove@Base 4.8
+ __interceptor_memrchr@Base 5
  __interceptor_memset@Base 4.8
+ __interceptor_mktime@Base 5
  __interceptor_mlock@Base 4.8
  __interceptor_mlockall@Base 4.8
  __interceptor_modf@Base 4.9
@@ -222,6 +314,8 @@
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  __interceptor_munlock@Base 4.8
  __interceptor_munlockall@Base 4.8
+ __interceptor_open_memstream@Base 5
+ __interceptor_open_wmemstream@Base 5
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  __interceptor_posix_memalign@Base 4.8
  __interceptor_ppoll@Base 4.9
@@ -230,6 +324,7 @@
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  __interceptor_preadv64@Base 4.9
  __interceptor_preadv@Base 4.9
+ __interceptor_printf@Base 5
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@@ -239,20 +334,28 @@
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- __interceptor_pthread_cond_broadcast@Base 4.9
- __interceptor_pthread_cond_init@Base 4.9
- __interceptor_pthread_cond_signal@Base 4.9
- __interceptor_pthread_cond_wait@Base 4.9
+ __interceptor_pthread_barrierattr_getpshared@Base 5
+ __interceptor_pthread_condattr_getclock@Base 5
+ __interceptor_pthread_condattr_getpshared@Base 5
  __interceptor_pthread_create@Base 4.8
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  __interceptor_pthread_mutex_unlock@Base 4.9
+ __interceptor_pthread_mutexattr_getprioceiling@Base 5
+ __interceptor_pthread_mutexattr_getprotocol@Base 5
+ __interceptor_pthread_mutexattr_getpshared@Base 5
+ __interceptor_pthread_mutexattr_getrobust@Base 5
+ __interceptor_pthread_mutexattr_getrobust_np@Base 5
+ __interceptor_pthread_mutexattr_gettype@Base 5
+ __interceptor_pthread_rwlockattr_getkind_np@Base 5
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+ __interceptor_rand_r@Base 5
  __interceptor_random_r@Base 4.9
  __interceptor_read@Base 4.8
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@@ -270,8 +373,10 @@
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  __interceptor_scanf@Base 4.8
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+ __interceptor_setgrent@Base 5
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+ __interceptor_setpwent@Base 5
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@@ -285,6 +390,8 @@
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  __interceptor_sincosf@Base 4.9
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+ __interceptor_snprintf@Base 5
+ __interceptor_sprintf@Base 5
  __interceptor_sscanf@Base 4.8
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@@ -315,12 +422,20 @@
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+ __interceptor_vsprintf@Base 5
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@@ -334,21 +449,75 @@
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+ __interceptor_xdr_hyper@Base 5
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+ __interceptor_xdr_int32_t@Base 5
+ __interceptor_xdr_int64_t@Base 5
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+ __interceptor_xdr_int@Base 5
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+ __interceptor_xdr_longlong_t@Base 5
+ __interceptor_xdr_quad_t@Base 5
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+ __interceptor_xdr_u_hyper@Base 5
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+ __interceptor_xdr_u_long@Base 5
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+ __lsan_register_root_region@Base 5
+ __lsan_unregister_root_region@Base 5
+ __overflow@Base 5
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+ __sanitizer_cov_indir_call16@Base 5
+ __sanitizer_cov_init@Base 5
+ __sanitizer_cov_module_init@Base 5
+ __sanitizer_get_allocated_size@Base 5
+ __sanitizer_get_current_allocated_bytes@Base 5
+ __sanitizer_get_estimated_allocated_size@Base 5
+ __sanitizer_get_free_bytes@Base 5
+ __sanitizer_get_heap_size@Base 5
+ __sanitizer_get_ownership@Base 5
+ __sanitizer_get_unmapped_bytes@Base 5
+ __sanitizer_maybe_open_cov_file@Base 5
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@@ -1036,13 +1205,25 @@
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+ __sanitizer_verify_contiguous_container@Base 5
+ __tls_get_addr@Base 5
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+ _obstack_begin@Base 5
+ _obstack_begin_1@Base 5
+ _obstack_newchunk@Base 5
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+ aligned_alloc@Base 5
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+ asprintf@Base 5
  atoi@Base 4.8
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  atoll@Base 4.8
@@ -1050,6 +1231,8 @@
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+ capget@Base 5
+ capset@Base 5
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  clock_getres@Base 4.9
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@@ -1057,7 +1240,11 @@
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  ether_aton@Base 4.9
  ether_aton_r@Base 4.9
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@@ -1065,7 +1252,23 @@
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  ether_ntoa_r@Base 4.9
  ether_ntohost@Base 4.9
+ fclose@Base 5
+ fdopen@Base 5
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+ freopen64@Base 5
+ freopen@Base 5
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@@ -1074,10 +1277,13 @@
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+ ftime@Base 5
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  getcwd@Base 4.9
  getdelim@Base 4.9
+ getgrent@Base 5
+ getgrent_r@Base 5
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  getgrgid_r@Base 4.9
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@@ -1091,23 +1297,32 @@
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  gethostent@Base 4.9
  gethostent_r@Base 4.9
+ getifaddrs@Base 5
  getitimer@Base 4.9
  getline@Base 4.9
  getmntent@Base 4.9
  getmntent_r@Base 4.9
  getnameinfo@Base 4.9
+ getpass@Base 5
  getpeername@Base 4.9
+ getpwent@Base 5
+ getpwent_r@Base 5
  getpwnam@Base 4.9
  getpwnam_r@Base 4.9
  getpwuid@Base 4.9
  getpwuid_r@Base 4.9
+ getresgid@Base 5
+ getresuid@Base 5
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  gmtime@Base 4.8
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  iconv@Base 4.9
+ if_indextoname@Base 5
+ if_nametoindex@Base 5
  index@Base 4.8
  inet_aton@Base 4.9
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@@ -1120,6 +1335,9 @@
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+ lgetxattr@Base 5
+ listxattr@Base 5
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@@ -1133,10 +1351,13 @@
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+ memchr@Base 5
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  memcpy@Base 4.8
  memmove@Base 4.8
+ memrchr@Base 5
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+ mktime@Base 5
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@@ -1144,6 +1365,8 @@
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  munlockall@Base 4.8
+ open_memstream@Base 5
+ open_wmemstream@Base 5
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@@ -1152,6 +1375,7 @@
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+ printf@Base 5
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@@ -1161,20 +1385,28 @@
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- pthread_cond_broadcast@Base 4.9
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- pthread_cond_signal@Base 4.9
- pthread_cond_wait@Base 4.9
+ pthread_barrierattr_getpshared@Base 5
+ pthread_condattr_getclock@Base 5
+ pthread_condattr_getpshared@Base 5
  pthread_create@Base 4.8
  pthread_getschedparam@Base 4.9
  pthread_mutex_lock@Base 4.9
  pthread_mutex_unlock@Base 4.9
+ pthread_mutexattr_getprioceiling@Base 5
+ pthread_mutexattr_getprotocol@Base 5
+ pthread_mutexattr_getpshared@Base 5
+ pthread_mutexattr_getrobust@Base 5
+ pthread_mutexattr_getrobust_np@Base 5
+ pthread_mutexattr_gettype@Base 5
+ pthread_rwlockattr_getkind_np@Base 5
+ pthread_rwlockattr_getpshared@Base 5
  pthread_setname_np@Base 4.9
  pvalloc@Base 4.8
  pwrite64@Base 4.8
  pwrite@Base 4.8
  pwritev64@Base 4.9
  pwritev@Base 4.9
+ rand_r@Base 5
  random_r@Base 4.9
  read@Base 4.8
  readdir64@Base 4.9
@@ -1192,8 +1424,10 @@
  scandir@Base 4.9
  scanf@Base 4.8
  sched_getaffinity@Base 4.9
+ setgrent@Base 5
  setitimer@Base 4.9
  setlocale@Base 4.9
+ setpwent@Base 5
  sigaction@Base 4.8
  sigemptyset@Base 4.9
  sigfillset@Base 4.9
@@ -1207,6 +1441,8 @@
  sincos@Base 4.9
  sincosf@Base 4.9
  sincosl@Base 4.9
+ snprintf@Base 5
+ sprintf@Base 5
  sscanf@Base 4.8
  statfs64@Base 4.9
  statfs@Base 4.9
@@ -1237,12 +1473,20 @@
  tempnam@Base 4.9
  textdomain@Base 4.9
  time@Base 4.9
+ timerfd_gettime@Base 5
+ timerfd_settime@Base 5
  times@Base 4.9
  tmpnam@Base 4.9
  tmpnam_r@Base 4.9
+ tsearch@Base 5
  valloc@Base 4.8
+ vasprintf@Base 5
+ vfprintf@Base 5
  vfscanf@Base 4.8
+ vprintf@Base 5
  vscanf@Base 4.8
+ vsnprintf@Base 5
+ vsprintf@Base 5
  vsscanf@Base 4.8
  wait3@Base 4.9
  wait4@Base 4.9
@@ -1256,3 +1500,33 @@
  wordexp@Base 4.9
  write@Base 4.8
  writev@Base 4.9
+ xdr_bool@Base 5
+ xdr_bytes@Base 5
+ xdr_char@Base 5
+ xdr_double@Base 5
+ xdr_enum@Base 5
+ xdr_float@Base 5
+ xdr_hyper@Base 5
+ xdr_int16_t@Base 5
+ xdr_int32_t@Base 5
+ xdr_int64_t@Base 5
+ xdr_int8_t@Base 5
+ xdr_int@Base 5
+ xdr_long@Base 5
+ xdr_longlong_t@Base 5
+ xdr_quad_t@Base 5
+ xdr_short@Base 5
+ xdr_string@Base 5
+ xdr_u_char@Base 5
+ xdr_u_hyper@Base 5
+ xdr_u_int@Base 5
+ xdr_u_long@Base 5
+ xdr_u_longlong_t@Base 5
+ xdr_u_quad_t@Base 5
+ xdr_u_short@Base 5
+ xdr_uint16_t@Base 5
+ xdr_uint32_t@Base 5
+ xdr_uint64_t@Base 5
+ xdr_uint8_t@Base 5
+ xdrmem_create@Base 5
+ xdrstdio_create@Base 5
diff --git a/debian/libasan1.symbols b/debian/libasan2.symbols
index 4482485..4369491 100644
--- a/debian/libasan1.symbols
+++ b/debian/libasan2.symbols
@@ -1,4 +1,4 @@
-libasan.so.1 libasan1 #MINVER#
+libasan.so.2 libasan2 #MINVER#
 #include "libasan.symbols.common"
 (arch=!arm64 !alpha !amd64 !ia64 !ppc64 !ppc64el !s390x !sparc64 !kfreebsd-amd64)#include "libasan.symbols.32"
 (arch=arm64 alpha amd64 ia64 ppc64 ppc64el s390x sparc64 kfreebsd-amd64)#include "libasan.symbols.64"
diff --git a/debian/libgcj-doc.doc-base b/debian/libgcj-doc.doc-base
index a8c4774..188795b 100644
--- a/debian/libgcj-doc.doc-base
+++ b/debian/libgcj-doc.doc-base
@@ -2,9 +2,9 @@ Document: libgcj-doc
 Title: The GNU LibGCJ Classpath library
 Author: Various
 Abstract: Autogenerated documentation describing the libgcj
- library (GCC 4.9), based on the classpath library.
+ library (GCC 5), based on the classpath library.
 Section: Programming/Java
 
 Format: html
-Index: /usr/share/doc/gcc-4.9-base/api/index.html
-Files: /usr/share/doc/gcc-4.9-base/api/*.html
+Index: /usr/share/doc/gcc-5-base/api/index.html
+Files: /usr/share/doc/gcc-5-base/api/*.html
diff --git a/debian/libgfortran3.symbols.10 b/debian/libgfortran3.symbols.10
index 2e2f1b8..69276a8 100644
--- a/debian/libgfortran3.symbols.10
+++ b/debian/libgfortran3.symbols.10
@@ -1,3 +1,13 @@
+ __ieee_arithmetic_MOD_ieee_support_datatype_10@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_denormal_10@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_divide_10@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_inf_10@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_io_10@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_nan_10@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_rounding_10@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_sqrt_10@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_standard_10@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_underflow_control_10@GFORTRAN_1.6 5
  __iso_c_binding_c_f_pointer_c10@GFORTRAN_1.0 4.3
  __iso_c_binding_c_f_pointer_r10@GFORTRAN_1.0 4.3
  _gfortran_arandom_r10@GFORTRAN_1.0 4.3
diff --git a/debian/libgfortran3.symbols.16 b/debian/libgfortran3.symbols.16
index ea8c84f..1329059 100644
--- a/debian/libgfortran3.symbols.16
+++ b/debian/libgfortran3.symbols.16
@@ -1,3 +1,13 @@
+ __ieee_arithmetic_MOD_ieee_support_datatype_16@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_denormal_16@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_divide_16@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_inf_16@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_io_16@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_nan_16@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_rounding_16@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_sqrt_16@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_standard_16@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_underflow_control_16@GFORTRAN_1.6 5
  __iso_c_binding_c_f_pointer_i16@GFORTRAN_1.0 4.3
  _gfortran_all_l16@GFORTRAN_1.0 4.3
  _gfortran_any_l16@GFORTRAN_1.0 4.3
diff --git a/debian/libgfortran3.symbols.common b/debian/libgfortran3.symbols.common
index 64305af..e851d38 100644
--- a/debian/libgfortran3.symbols.common
+++ b/debian/libgfortran3.symbols.common
@@ -5,8 +5,64 @@
  GFORTRAN_1.3@GFORTRAN_1.3 4.6
  GFORTRAN_1.4@GFORTRAN_1.4 4.6
  GFORTRAN_1.5@GFORTRAN_1.5 4.8
+ GFORTRAN_1.6@GFORTRAN_1.6 5
  GFORTRAN_C99_1.0@GFORTRAN_C99_1.0 4.3
  GFORTRAN_C99_1.1@GFORTRAN_C99_1.1 4.5
+ __ieee_arithmetic_MOD_ieee_class_4@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_class_8@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_class_type_eq@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_class_type_ne@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_get_rounding_mode@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_get_underflow_mode@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_round_type_eq@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_round_type_ne@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_selected_real_kind@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_set_rounding_mode@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_set_underflow_mode@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_datatype_4@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_datatype_8@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_datatype_noarg@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_denormal_4@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_denormal_8@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_denormal_noarg@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_divide_4@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_divide_8@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_divide_noarg@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_inf_4@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_inf_8@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_inf_noarg@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_io_4@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_io_8@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_io_noarg@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_nan_4@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_nan_8@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_nan_noarg@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_rounding_4@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_rounding_8@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_rounding_noarg@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_sqrt_4@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_sqrt_8@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_sqrt_noarg@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_standard_4@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_standard_8@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_standard_noarg@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_underflow_control_4@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_underflow_control_8@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_support_underflow_control_noarg@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_value_4@GFORTRAN_1.6 5
+ __ieee_arithmetic_MOD_ieee_value_8@GFORTRAN_1.6 5
+ __ieee_exceptions_MOD_ieee_all@GFORTRAN_1.6 5
+ __ieee_exceptions_MOD_ieee_get_flag@GFORTRAN_1.6 5
+ __ieee_exceptions_MOD_ieee_get_halting_mode@GFORTRAN_1.6 5
+ __ieee_exceptions_MOD_ieee_get_status@GFORTRAN_1.6 5
+ __ieee_exceptions_MOD_ieee_set_flag@GFORTRAN_1.6 5
+ __ieee_exceptions_MOD_ieee_set_halting_mode@GFORTRAN_1.6 5
+ __ieee_exceptions_MOD_ieee_set_status@GFORTRAN_1.6 5
+ __ieee_exceptions_MOD_ieee_support_flag_4@GFORTRAN_1.6 5
+ __ieee_exceptions_MOD_ieee_support_flag_8@GFORTRAN_1.6 5
+ __ieee_exceptions_MOD_ieee_support_flag_noarg@GFORTRAN_1.6 5
+ __ieee_exceptions_MOD_ieee_support_halting@GFORTRAN_1.6 5
+ __ieee_exceptions_MOD_ieee_usual@GFORTRAN_1.6 5
  __iso_c_binding_c_f_pointer@GFORTRAN_1.0 4.3
  __iso_c_binding_c_f_pointer_c4@GFORTRAN_1.0 4.3
  __iso_c_binding_c_f_pointer_c8@GFORTRAN_1.0 4.3
@@ -251,6 +307,8 @@
  _gfortran_iargc@GFORTRAN_1.0 4.3
  _gfortran_idate_i4@GFORTRAN_1.0 4.3
  _gfortran_idate_i8@GFORTRAN_1.0 4.3
+ _gfortran_ieee_procedure_entry@GFORTRAN_1.6 5
+ _gfortran_ieee_procedure_exit@GFORTRAN_1.6 5
  _gfortran_ierrno_i4@GFORTRAN_1.0 4.3
  _gfortran_ierrno_i8@GFORTRAN_1.0 4.3
  _gfortran_internal_pack@GFORTRAN_1.0 4.3
diff --git a/debian/libgomp1.symbols.common b/debian/libgomp1.symbols.common
index 47f0987..f13109a 100644
--- a/debian/libgomp1.symbols.common
+++ b/debian/libgomp1.symbols.common
@@ -1,7 +1,26 @@
+ GOACC_2.0@GOACC_2.0 5
+ GOACC_data_end@GOACC_2.0 5
+ GOACC_data_start@GOACC_2.0 5
+ GOACC_enter_exit_data@GOACC_2.0 5
+ GOACC_get_num_threads@GOACC_2.0 5
+ GOACC_get_thread_num@GOACC_2.0 5
+ GOACC_parallel@GOACC_2.0 5
+ GOACC_update@GOACC_2.0 5
+ GOACC_wait@GOACC_2.0 5
  GOMP_1.0@GOMP_1.0 4.2.1
  GOMP_2.0@GOMP_2.0 4.4
  GOMP_3.0@GOMP_3.0 4.7
+ GOMP_4.0.1@GOMP_4.0.1 5
  GOMP_4.0@GOMP_4.0 4.9
+ GOMP_PLUGIN_1.0@GOMP_PLUGIN_1.0 5
+ GOMP_PLUGIN_acc_thread@GOMP_PLUGIN_1.0 5
+ GOMP_PLUGIN_async_unmap_vars@GOMP_PLUGIN_1.0 5
+ GOMP_PLUGIN_debug@GOMP_PLUGIN_1.0 5
+ GOMP_PLUGIN_error@GOMP_PLUGIN_1.0 5
+ GOMP_PLUGIN_fatal@GOMP_PLUGIN_1.0 5
+ GOMP_PLUGIN_malloc@GOMP_PLUGIN_1.0 5
+ GOMP_PLUGIN_malloc_cleared@GOMP_PLUGIN_1.0 5
+ GOMP_PLUGIN_realloc@GOMP_PLUGIN_1.0 5
  GOMP_atomic_end@GOMP_1.0 4.2.1
  GOMP_atomic_start@GOMP_1.0 4.2.1
  GOMP_barrier@GOMP_1.0 4.2.1
@@ -47,6 +66,7 @@
  GOMP_loop_ull_runtime_start@GOMP_2.0 4.4
  GOMP_loop_ull_static_next@GOMP_2.0 4.4
  GOMP_loop_ull_static_start@GOMP_2.0 4.4
+ GOMP_offload_register@GOMP_4.0.1 5
  GOMP_ordered_end@GOMP_1.0 4.2.1
  GOMP_ordered_start@GOMP_1.0 4.2.1
  GOMP_parallel@GOMP_4.0 4.9
@@ -80,11 +100,88 @@
  GOMP_taskwait@GOMP_2.0 4.4
  GOMP_taskyield@GOMP_3.0 4.7
  GOMP_teams@GOMP_4.0 4.9
+ OACC_2.0@OACC_2.0 5
  OMP_1.0@OMP_1.0 4.2.1
  OMP_2.0@OMP_2.0 4.2.1
  OMP_3.0@OMP_3.0 4.4
  OMP_3.1@OMP_3.1 4.7
  OMP_4.0@OMP_4.0 4.9
+ acc_async_test@OACC_2.0 5
+ acc_async_test_all@OACC_2.0 5
+ acc_async_test_all_h_@OACC_2.0 5
+ acc_async_test_h_@OACC_2.0 5
+ acc_copyin@OACC_2.0 5
+ acc_copyin_32_h_@OACC_2.0 5
+ acc_copyin_64_h_@OACC_2.0 5
+ acc_copyin_array_h_@OACC_2.0 5
+ acc_copyout@OACC_2.0 5
+ acc_copyout_32_h_@OACC_2.0 5
+ acc_copyout_64_h_@OACC_2.0 5
+ acc_copyout_array_h_@OACC_2.0 5
+ acc_create@OACC_2.0 5
+ acc_create_32_h_@OACC_2.0 5
+ acc_create_64_h_@OACC_2.0 5
+ acc_create_array_h_@OACC_2.0 5
+ acc_delete@OACC_2.0 5
+ acc_delete_32_h_@OACC_2.0 5
+ acc_delete_64_h_@OACC_2.0 5
+ acc_delete_array_h_@OACC_2.0 5
+ acc_deviceptr@OACC_2.0 5
+ acc_free@OACC_2.0 5
+ acc_get_cuda_stream@OACC_2.0 5
+ acc_get_current_cuda_context@OACC_2.0 5
+ acc_get_current_cuda_device@OACC_2.0 5
+ acc_get_device_num@OACC_2.0 5
+ acc_get_device_num_h_@OACC_2.0 5
+ acc_get_device_type@OACC_2.0 5
+ acc_get_device_type_h_@OACC_2.0 5
+ acc_get_num_devices@OACC_2.0 5
+ acc_get_num_devices_h_@OACC_2.0 5
+ acc_hostptr@OACC_2.0 5
+ acc_init@OACC_2.0 5
+ acc_init_h_@OACC_2.0 5
+ acc_is_present@OACC_2.0 5
+ acc_is_present_32_h_@OACC_2.0 5
+ acc_is_present_64_h_@OACC_2.0 5
+ acc_is_present_array_h_@OACC_2.0 5
+ acc_malloc@OACC_2.0 5
+ acc_map_data@OACC_2.0 5
+ acc_memcpy_from_device@OACC_2.0 5
+ acc_memcpy_to_device@OACC_2.0 5
+ acc_on_device@OACC_2.0 5
+ acc_on_device_h_@OACC_2.0 5
+ acc_present_or_copyin@OACC_2.0 5
+ acc_present_or_copyin_32_h_@OACC_2.0 5
+ acc_present_or_copyin_64_h_@OACC_2.0 5
+ acc_present_or_copyin_array_h_@OACC_2.0 5
+ acc_present_or_create@OACC_2.0 5
+ acc_present_or_create_32_h_@OACC_2.0 5
+ acc_present_or_create_64_h_@OACC_2.0 5
+ acc_present_or_create_array_h_@OACC_2.0 5
+ acc_set_cuda_stream@OACC_2.0 5
+ acc_set_device_num@OACC_2.0 5
+ acc_set_device_num_h_@OACC_2.0 5
+ acc_set_device_type@OACC_2.0 5
+ acc_set_device_type_h_@OACC_2.0 5
+ acc_shutdown@OACC_2.0 5
+ acc_shutdown_h_@OACC_2.0 5
+ acc_unmap_data@OACC_2.0 5
+ acc_update_device@OACC_2.0 5
+ acc_update_device_32_h_@OACC_2.0 5
+ acc_update_device_64_h_@OACC_2.0 5
+ acc_update_device_array_h_@OACC_2.0 5
+ acc_update_self@OACC_2.0 5
+ acc_update_self_32_h_@OACC_2.0 5
+ acc_update_self_64_h_@OACC_2.0 5
+ acc_update_self_array_h_@OACC_2.0 5
+ acc_wait@OACC_2.0 5
+ acc_wait_all@OACC_2.0 5
+ acc_wait_all_async@OACC_2.0 5
+ acc_wait_all_async_h_@OACC_2.0 5
+ acc_wait_all_h_@OACC_2.0 5
+ acc_wait_async@OACC_2.0 5
+ acc_wait_async_h_@OACC_2.0 5
+ acc_wait_h_@OACC_2.0 5
  omp_destroy_lock@OMP_1.0 4.2.1
  omp_destroy_lock@OMP_3.0 4.4
  omp_destroy_lock_@OMP_1.0 4.2.1
diff --git a/debian/liblsan0.symbols b/debian/liblsan0.symbols
index b3de598..0cc9d5a 100644
--- a/debian/liblsan0.symbols
+++ b/debian/liblsan0.symbols
@@ -49,6 +49,7 @@ liblsan.so.0 liblsan0 #MINVER#
  __asan_java_demangle_v3@Base 4.9
  __asan_java_demangle_v3_callback@Base 4.9
  __interceptor___libc_memalign@Base 4.9
+ __interceptor_aligned_alloc@Base 5
  __interceptor_calloc@Base 4.9
  __interceptor_cfree@Base 4.9
  __interceptor_free@Base 4.9
@@ -68,11 +69,26 @@ liblsan.so.0 liblsan0 #MINVER#
  __lsan_do_leak_check@Base 4.9
  __lsan_enable@Base 4.9
  __lsan_ignore_object@Base 4.9
+ __lsan_register_root_region@Base 5
+ __lsan_unregister_root_region@Base 5
  __sanitizer_cov@Base 4.9
  __sanitizer_cov_dump@Base 4.9
+ __sanitizer_cov_indir_call16@Base 5
+ __sanitizer_cov_init@Base 5
+ __sanitizer_cov_module_init@Base 5
+ __sanitizer_get_allocated_size@Base 5
+ __sanitizer_get_current_allocated_bytes@Base 5
+ __sanitizer_get_estimated_allocated_size@Base 5
+ __sanitizer_get_free_bytes@Base 5
+ __sanitizer_get_heap_size@Base 5
+ __sanitizer_get_ownership@Base 5
+ __sanitizer_get_unmapped_bytes@Base 5
+ __sanitizer_maybe_open_cov_file@Base 5
+ __sanitizer_print_stack_trace@Base 5
  __sanitizer_report_error_summary@Base 4.9
  __sanitizer_sandbox_on_notify@Base 4.9
  __sanitizer_set_report_path@Base 4.9
+ aligned_alloc@Base 5
  calloc@Base 4.9
  cfree@Base 4.9
  free@Base 4.9
diff --git a/debian/libstdc++6.symbols.32bit b/debian/libstdc++6.symbols.32bit
index 88c4c0f..96e47bd 100644
--- a/debian/libstdc++6.symbols.32bit
+++ b/debian/libstdc++6.symbols.32bit
@@ -94,6 +94,95 @@
  _ZNKSsixEj@GLIBCXX_3.4 4.1.1
  _ZNKSt11__timepunctIcE6_M_putEPcjPKcPK2tm@GLIBCXX_3.4 4.1.1
  _ZNKSt11__timepunctIwE6_M_putEPwjPKwPK2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt19__codecvt_utf8_baseIDiE9do_lengthER11__mbstate_tPKcS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIDsE9do_lengthER11__mbstate_tPKcS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIwE9do_lengthER11__mbstate_tPKcS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDiE9do_lengthER11__mbstate_tPKcS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDsE9do_lengthER11__mbstate_tPKcS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIwE9do_lengthER11__mbstate_tPKcS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDiE9do_lengthER11__mbstate_tPKcS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDsE9do_lengthER11__mbstate_tPKcS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIwE9do_lengthER11__mbstate_tPKcS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12find_last_ofEPKcj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12find_last_ofEPKcjj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12find_last_ofERKS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12find_last_ofEcj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13find_first_ofEPKcj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13find_first_ofEPKcjj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13find_first_ofERKS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13find_first_ofEcj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEjjPKc@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE16find_last_not_ofEPKcj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE16find_last_not_ofEPKcjj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE16find_last_not_ofERKS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE16find_last_not_ofEcj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE17find_first_not_ofEPKcj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE17find_first_not_ofEPKcjj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE17find_first_not_ofERKS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE17find_first_not_ofEcj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE2atEj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4copyEPcjj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4findEPKcj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4findEPKcjj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4findERKS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4findEcj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5rfindEPKcj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5rfindEPKcjj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5rfindERKS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5rfindEcj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6substrEjj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7compareEjjPKc@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7compareEjjPKcj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7compareEjjRKS4_@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7compareEjjRKS4_jj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8_M_checkEjPKc@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8_M_limitEjj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEixEj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12find_last_ofEPKwj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12find_last_ofEPKwjj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12find_last_ofERKS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12find_last_ofEwj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13find_first_ofEPKwj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13find_first_ofEPKwjj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13find_first_ofERKS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13find_first_ofEwj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE15_M_check_lengthEjjPKc@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwjj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE16find_last_not_ofERKS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE16find_last_not_ofEwj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwjj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE17find_first_not_ofERKS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE17find_first_not_ofEwj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE2atEj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4copyEPwjj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4findEPKwj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4findEPKwjj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4findERKS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4findEwj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5rfindEPKwj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5rfindEPKwjj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5rfindERKS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5rfindEwj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6substrEjj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7compareEjjPKw@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7compareEjjPKwj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7compareEjjRKS4_@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7compareEjjRKS4_jj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE8_M_checkEjPKc@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE8_M_limitEjj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEixEj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx117collateIcE12_M_transformEPcPKcj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx117collateIwE12_M_transformEPwPKwj@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_numES4_S4_RiiijRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE15_M_extract_nameES4_S4_RiPPKcjRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE24_M_extract_wday_or_monthES4_S4_RiPPKcjRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_numES4_S4_RiiijRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE15_M_extract_nameES4_S4_RiPPKwjRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE24_M_extract_wday_or_monthES4_S4_RiPPKwjRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDic11__mbstate_tE9do_lengthERS0_PKcS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDsc11__mbstate_tE9do_lengthERS0_PKcS4_j@GLIBCXX_3.4.21 5
  _ZNKSt7codecvtIcc11__mbstate_tE9do_lengthERS0_PKcS4_j@GLIBCXX_3.4 4.1.1
  _ZNKSt7codecvtIwc11__mbstate_tE9do_lengthERS0_PKcS4_j@GLIBCXX_3.4 4.1.1
  _ZNKSt7collateIcE12_M_transformEPcPKcj@GLIBCXX_3.4 4.1.1
@@ -270,9 +359,17 @@
  _ZNSt12__basic_fileIcE7seekoffExSt12_Ios_Seekdir@GLIBCXX_3.4 4.1.1
  _ZNSt12__basic_fileIcE8xsputn_2EPKciS2_i@GLIBCXX_3.4 4.1.1
  _ZNSt12ctype_bynameIcEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIcEC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5
+ _ZNSt12ctype_bynameIcEC1ERKSsj@GLIBCXX_3.4.21 5
  _ZNSt12ctype_bynameIcEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIcEC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5
+ _ZNSt12ctype_bynameIcEC2ERKSsj@GLIBCXX_3.4.21 5
  _ZNSt12ctype_bynameIwEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIwEC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5
+ _ZNSt12ctype_bynameIwEC1ERKSsj@GLIBCXX_3.4.21 5
  _ZNSt12ctype_bynameIwEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIwEC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5
+ _ZNSt12ctype_bynameIwEC2ERKSsj@GLIBCXX_3.4.21 5
  _ZNSt12strstreambuf6setbufEPci@GLIBCXX_3.4 4.1.1
  _ZNSt12strstreambuf7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
  _ZNSt12strstreambuf8_M_allocEj@GLIBCXX_3.4 4.1.1
@@ -321,9 +418,17 @@
  _ZNSt13basic_ostreamIwSt11char_traitsIwEE5writeEPKwi@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_ostreamIwSt11char_traitsIwEE8_M_writeEPKwi@GLIBCXX_3.4 4.1.1
  _ZNSt14codecvt_bynameIcc11__mbstate_tEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIcc11__mbstate_tEC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5
+ _ZNSt14codecvt_bynameIcc11__mbstate_tEC1ERKSsj@GLIBCXX_3.4.21 5
  _ZNSt14codecvt_bynameIcc11__mbstate_tEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIcc11__mbstate_tEC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5
+ _ZNSt14codecvt_bynameIcc11__mbstate_tEC2ERKSsj@GLIBCXX_3.4.21 5
  _ZNSt14codecvt_bynameIwc11__mbstate_tEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIwc11__mbstate_tEC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5
+ _ZNSt14codecvt_bynameIwc11__mbstate_tEC1ERKSsj@GLIBCXX_3.4.21 5
  _ZNSt14codecvt_bynameIwc11__mbstate_tEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIwc11__mbstate_tEC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5
+ _ZNSt14codecvt_bynameIwc11__mbstate_tEC2ERKSsj@GLIBCXX_3.4.21 5
  _ZNSt14collate_bynameIcEC1EPKcj@GLIBCXX_3.4 4.1.1
  _ZNSt14collate_bynameIcEC2EPKcj@GLIBCXX_3.4 4.1.1
  _ZNSt14collate_bynameIwEC1EPKcj@GLIBCXX_3.4 4.1.1
@@ -358,21 +463,39 @@
  _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
  _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE8_M_pbumpEPwS4_x@GLIBCXX_3.4.16 4.6.0
  _ZNSt15messages_bynameIcEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15messages_bynameIcEC1ERKSsj@GLIBCXX_3.4.21 5
  _ZNSt15messages_bynameIcEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15messages_bynameIcEC2ERKSsj@GLIBCXX_3.4.21 5
  _ZNSt15messages_bynameIwEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15messages_bynameIwEC1ERKSsj@GLIBCXX_3.4.21 5
  _ZNSt15messages_bynameIwEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15messages_bynameIwEC2ERKSsj@GLIBCXX_3.4.21 5
  _ZNSt15numpunct_bynameIcEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIcEC1ERKSsj@GLIBCXX_3.4.21 5
  _ZNSt15numpunct_bynameIcEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIcEC2ERKSsj@GLIBCXX_3.4.21 5
  _ZNSt15numpunct_bynameIwEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIwEC1ERKSsj@GLIBCXX_3.4.21 5
  _ZNSt15numpunct_bynameIwEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIwEC2ERKSsj@GLIBCXX_3.4.21 5
  _ZNSt15time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1ERKSsj@GLIBCXX_3.4.21 5
  _ZNSt15time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2ERKSsj@GLIBCXX_3.4.21 5
  _ZNSt15time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1ERKSsj@GLIBCXX_3.4.21 5
  _ZNSt15time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2ERKSsj@GLIBCXX_3.4.21 5
  _ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1ERKNSt7__cxx1112basic_stringIcS2_SaIcEEEj@GLIBCXX_3.4.21 5-20150121-1
+ _ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1ERKSsj@GLIBCXX_3.4.21 5-20150121-1
  _ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2ERKNSt7__cxx1112basic_stringIcS2_SaIcEEEj@GLIBCXX_3.4.21 5-20150121-1
+ _ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2ERKSsj@GLIBCXX_3.4.21 5-20150121-1
  _ZNSt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1ERKSsj@GLIBCXX_3.4.21 5-20150121-1
  _ZNSt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2ERKSsj@GLIBCXX_3.4.21 5-20150121-1
  _ZNSt16__numpunct_cacheIcEC1Ej@GLIBCXX_3.4 4.1.1
  _ZNSt16__numpunct_cacheIcEC2Ej@GLIBCXX_3.4 4.1.1
  _ZNSt16__numpunct_cacheIwEC1Ej@GLIBCXX_3.4 4.1.1
@@ -382,13 +505,21 @@
  _ZNSt17__timepunct_cacheIwEC1Ej@GLIBCXX_3.4 4.1.1
  _ZNSt17__timepunct_cacheIwEC2Ej@GLIBCXX_3.4 4.1.1
  _ZNSt17moneypunct_bynameIcLb0EEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb0EEC1ERKSsj@GLIBCXX_3.4.21 5
  _ZNSt17moneypunct_bynameIcLb0EEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb0EEC2ERKSsj@GLIBCXX_3.4.21 5
  _ZNSt17moneypunct_bynameIcLb1EEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb1EEC1ERKSsj@GLIBCXX_3.4.21 5
  _ZNSt17moneypunct_bynameIcLb1EEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb1EEC2ERKSsj@GLIBCXX_3.4.21 5
  _ZNSt17moneypunct_bynameIwLb0EEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb0EEC1ERKSsj@GLIBCXX_3.4.21 5
  _ZNSt17moneypunct_bynameIwLb0EEC2EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb0EEC2ERKSsj@GLIBCXX_3.4.21 5
  _ZNSt17moneypunct_bynameIwLb1EEC1EPKcj@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb1EEC1ERKSsj@GLIBCXX_3.4.21 5
  _ZNSt17moneypunct_bynameIwLb1EEC2EPKcj@GLIBCXX_3.4 4.1.1
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  _ZNSt18__moneypunct_cacheIcLb1EEC1Ej@GLIBCXX_3.4 4.1.1
@@ -397,6 +528,7 @@
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  _ZNSt18__moneypunct_cacheIwLb1EEC2Ej@GLIBCXX_3.4 4.1.1
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  _ZNSt5ctypeIcEC2EP15__locale_structPKtbj@GLIBCXX_3.4 4.1.1
@@ -414,6 +546,230 @@
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+ _ZNSt7__cxx1115numpunct_bynameIcEC1EPKcj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1115numpunct_bynameIcEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1115numpunct_bynameIcEC2EPKcj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1115numpunct_bynameIcEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1115numpunct_bynameIwEC1EPKcj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1115numpunct_bynameIwEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1115numpunct_bynameIwEC2EPKcj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1115numpunct_bynameIwEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1115time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1EPKcj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1115time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1ERKNS_12basic_stringIcS3_SaIcEEEj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1115time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2EPKcj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1115time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2ERKNS_12basic_stringIcS3_SaIcEEEj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1115time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1EPKcj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1115time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1ERKNS_12basic_stringIcS2_IcESaIcEEEj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1115time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2EPKcj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1115time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2ERKNS_12basic_stringIcS2_IcESaIcEEEj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1117moneypunct_bynameIcLb0EEC1EPKcj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1117moneypunct_bynameIcLb0EEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1117moneypunct_bynameIcLb0EEC2EPKcj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1117moneypunct_bynameIcLb0EEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1117moneypunct_bynameIcLb1EEC1EPKcj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1117moneypunct_bynameIcLb1EEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1117moneypunct_bynameIcLb1EEC2EPKcj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1117moneypunct_bynameIcLb1EEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1117moneypunct_bynameIwLb0EEC1EPKcj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1117moneypunct_bynameIwLb0EEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1117moneypunct_bynameIwLb0EEC2EPKcj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1117moneypunct_bynameIwLb0EEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1117moneypunct_bynameIwLb1EEC1EPKcj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1117moneypunct_bynameIwLb1EEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1117moneypunct_bynameIwLb1EEC2EPKcj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1117moneypunct_bynameIwLb1EEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx117collateIcEC1EP15__locale_structj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx117collateIcEC1Ej@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx117collateIcEC2EP15__locale_structj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx117collateIcEC2Ej@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx117collateIwEC1EP15__locale_structj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx117collateIwEC1Ej@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx117collateIwEC2EP15__locale_structj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx117collateIwEC2Ej@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118messagesIcEC1EP15__locale_structPKcj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118messagesIcEC1Ej@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118messagesIcEC2EP15__locale_structPKcj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118messagesIcEC2Ej@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118messagesIwEC1EP15__locale_structPKcj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118messagesIwEC1Ej@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118messagesIwEC2EP15__locale_structPKcj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118messagesIwEC2Ej@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118numpunctIcEC1EP15__locale_structj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118numpunctIcEC1EPSt16__numpunct_cacheIcEj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118numpunctIcEC1Ej@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118numpunctIcEC2EP15__locale_structj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118numpunctIcEC2EPSt16__numpunct_cacheIcEj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118numpunctIcEC2Ej@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118numpunctIwEC1EP15__locale_structj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118numpunctIwEC1EPSt16__numpunct_cacheIwEj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118numpunctIwEC1Ej@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118numpunctIwEC2EP15__locale_structj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118numpunctIwEC2EPSt16__numpunct_cacheIwEj@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118numpunctIwEC2Ej@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Ej@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Ej@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Ej@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Ej@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Ej@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Ej@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Ej@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Ej@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1Ej@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2Ej@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1Ej@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2Ej@GLIBCXX_3.4.21 5
  _ZNSt7codecvtIcc11__mbstate_tEC1EP15__locale_structj@GLIBCXX_3.4 4.1.1
  _ZNSt7codecvtIcc11__mbstate_tEC1Ej@GLIBCXX_3.4 4.1.1
  _ZNSt7codecvtIcc11__mbstate_tEC2EP15__locale_structj@GLIBCXX_3.4 4.1.1
@@ -487,6 +843,7 @@
  _ZSt16__ostream_insertIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKS3_i@GLIBCXX_3.4.9 4.2.1
  _ZSt17__copy_streambufsIcSt11char_traitsIcEEiPSt15basic_streambufIT_T0_ES6_@GLIBCXX_3.4.6 4.1.1
  _ZSt17__copy_streambufsIwSt11char_traitsIwEEiPSt15basic_streambufIT_T0_ES6_@GLIBCXX_3.4.6 4.1.1
+ _ZSt17__verify_groupingPKcjRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
  _ZSt17__verify_groupingPKcjRKSs@GLIBCXX_3.4.10 4.3
  _ZSt21__copy_streambufs_eofIcSt11char_traitsIcEEiPSt15basic_streambufIT_T0_ES6_Rb@GLIBCXX_3.4.9 4.2.1
  _ZSt21__copy_streambufs_eofIwSt11char_traitsIwEEiPSt15basic_streambufIT_T0_ES6_Rb@GLIBCXX_3.4.9 4.2.1
@@ -502,6 +859,10 @@
  _ZThn8_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
  _ZThn8_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
  _ZThn8_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4.21 5
+ _ZThn8_NSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4.21 5
+ _ZThn8_NSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4.21 5
+ _ZThn8_NSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4.21 5
  _ZThn8_NSt9strstreamD0Ev@GLIBCXX_3.4 4.1.1
  _ZThn8_NSt9strstreamD1Ev@GLIBCXX_3.4 4.1.1
  _ZTv0_n12_NSdD0Ev@GLIBCXX_3.4 4.1.1
@@ -544,8 +905,22 @@
  _ZTv0_n12_NSt19basic_ostringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
  _ZTv0_n12_NSt19basic_ostringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
  _ZTv0_n12_NSt19basic_ostringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4.21 5
+ _ZTv0_n12_NSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4.21 5
+ _ZTv0_n12_NSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4.21 5
+ _ZTv0_n12_NSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4.21 5
+ _ZTv0_n12_NSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4.21 5
+ _ZTv0_n12_NSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4.21 5
+ _ZTv0_n12_NSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4.21 5
+ _ZTv0_n12_NSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4.21 5
+ _ZTv0_n12_NSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4.21 5
+ _ZTv0_n12_NSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4.21 5
+ _ZTv0_n12_NSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4.21 5
+ _ZTv0_n12_NSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4.21 5
  _ZTv0_n12_NSt9strstreamD0Ev@GLIBCXX_3.4 4.1.1
  _ZTv0_n12_NSt9strstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _ZdaPvj@CXXABI_1.3.9 5
+ _ZdlPvj@CXXABI_1.3.9 5
  _Znaj@GLIBCXX_3.4 4.1.1
  _ZnajRKSt9nothrow_t@GLIBCXX_3.4 4.1.1
  _Znwj@GLIBCXX_3.4 4.1.1
diff --git a/debian/libstdc++6.symbols.64bit b/debian/libstdc++6.symbols.64bit
index b9fe43b..c2a5e16 100644
--- a/debian/libstdc++6.symbols.64bit
+++ b/debian/libstdc++6.symbols.64bit
@@ -92,6 +92,95 @@
  _ZNKSsixEm@GLIBCXX_3.4 4.1.1
  _ZNKSt11__timepunctIcE6_M_putEPcmPKcPK2tm@GLIBCXX_3.4 4.1.1
  _ZNKSt11__timepunctIwE6_M_putEPwmPKwPK2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt19__codecvt_utf8_baseIDiE9do_lengthER11__mbstate_tPKcS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIDsE9do_lengthER11__mbstate_tPKcS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIwE9do_lengthER11__mbstate_tPKcS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDiE9do_lengthER11__mbstate_tPKcS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDsE9do_lengthER11__mbstate_tPKcS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIwE9do_lengthER11__mbstate_tPKcS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDiE9do_lengthER11__mbstate_tPKcS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDsE9do_lengthER11__mbstate_tPKcS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIwE9do_lengthER11__mbstate_tPKcS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12find_last_ofEPKcm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12find_last_ofEPKcmm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12find_last_ofERKS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12find_last_ofEcm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13find_first_ofEPKcm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13find_first_ofEPKcmm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13find_first_ofERKS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13find_first_ofEcm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE16find_last_not_ofEPKcm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE16find_last_not_ofEPKcmm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE16find_last_not_ofERKS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE16find_last_not_ofEcm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE17find_first_not_ofEPKcm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE17find_first_not_ofEPKcmm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE17find_first_not_ofERKS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE17find_first_not_ofEcm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE2atEm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4copyEPcmm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4findEPKcm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4findEPKcmm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4findERKS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4findEcm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5rfindEPKcm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5rfindEPKcmm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5rfindERKS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5rfindEcm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6substrEmm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7compareEmmPKc@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7compareEmmPKcm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7compareEmmRKS4_@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7compareEmmRKS4_mm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8_M_checkEmPKc@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8_M_limitEmm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEixEm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12find_last_ofEPKwm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12find_last_ofEPKwmm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12find_last_ofERKS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12find_last_ofEwm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13find_first_ofEPKwm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13find_first_ofEPKwmm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13find_first_ofERKS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13find_first_ofEwm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE15_M_check_lengthEmmPKc@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwmm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE16find_last_not_ofERKS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE16find_last_not_ofEwm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwmm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE17find_first_not_ofERKS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE17find_first_not_ofEwm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE2atEm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4copyEPwmm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4findEPKwm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4findEPKwmm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4findERKS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4findEwm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5rfindEPKwm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5rfindEPKwmm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5rfindERKS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5rfindEwm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6substrEmm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7compareEmmPKw@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7compareEmmPKwm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7compareEmmRKS4_@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7compareEmmRKS4_mm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE8_M_checkEmPKc@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE8_M_limitEmm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEixEm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx117collateIcE12_M_transformEPcPKcm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx117collateIwE12_M_transformEPwPKwm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_numES4_S4_RiiimRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE15_M_extract_nameES4_S4_RiPPKcmRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE24_M_extract_wday_or_monthES4_S4_RiPPKcmRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_numES4_S4_RiiimRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE15_M_extract_nameES4_S4_RiPPKwmRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE24_M_extract_wday_or_monthES4_S4_RiPPKwmRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDic11__mbstate_tE9do_lengthERS0_PKcS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDsc11__mbstate_tE9do_lengthERS0_PKcS4_m@GLIBCXX_3.4.21 5
  _ZNKSt7codecvtIcc11__mbstate_tE9do_lengthERS0_PKcS4_m@GLIBCXX_3.4 4.1.1
  _ZNKSt7codecvtIwc11__mbstate_tE9do_lengthERS0_PKcS4_m@GLIBCXX_3.4 4.1.1
  _ZNKSt7collateIcE12_M_transformEPcPKcm@GLIBCXX_3.4 4.1.1
@@ -268,9 +357,17 @@
  _ZNSt12__basic_fileIcE7seekoffElSt12_Ios_Seekdir@GLIBCXX_3.4 4.1.1
  _ZNSt12__basic_fileIcE8xsputn_2EPKclS2_l@GLIBCXX_3.4 4.1.1
  _ZNSt12ctype_bynameIcEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIcEC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5
+ _ZNSt12ctype_bynameIcEC1ERKSsm@GLIBCXX_3.4.21 5
  _ZNSt12ctype_bynameIcEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIcEC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5
+ _ZNSt12ctype_bynameIcEC2ERKSsm@GLIBCXX_3.4.21 5
  _ZNSt12ctype_bynameIwEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIwEC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5
+ _ZNSt12ctype_bynameIwEC1ERKSsm@GLIBCXX_3.4.21 5
  _ZNSt12ctype_bynameIwEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt12ctype_bynameIwEC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5
+ _ZNSt12ctype_bynameIwEC2ERKSsm@GLIBCXX_3.4.21 5
  _ZNSt12strstreambuf6setbufEPcl@GLIBCXX_3.4 4.1.1
  _ZNSt12strstreambuf7seekoffElSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
  _ZNSt12strstreambuf8_M_allocEm@GLIBCXX_3.4 4.1.1
@@ -319,9 +416,17 @@
  _ZNSt13basic_ostreamIwSt11char_traitsIwEE5writeEPKwl@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_ostreamIwSt11char_traitsIwEE8_M_writeEPKwl@GLIBCXX_3.4 4.1.1
  _ZNSt14codecvt_bynameIcc11__mbstate_tEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIcc11__mbstate_tEC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5
+ _ZNSt14codecvt_bynameIcc11__mbstate_tEC1ERKSsm@GLIBCXX_3.4.21 5
  _ZNSt14codecvt_bynameIcc11__mbstate_tEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIcc11__mbstate_tEC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5
+ _ZNSt14codecvt_bynameIcc11__mbstate_tEC2ERKSsm@GLIBCXX_3.4.21 5
  _ZNSt14codecvt_bynameIwc11__mbstate_tEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIwc11__mbstate_tEC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5
+ _ZNSt14codecvt_bynameIwc11__mbstate_tEC1ERKSsm@GLIBCXX_3.4.21 5
  _ZNSt14codecvt_bynameIwc11__mbstate_tEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt14codecvt_bynameIwc11__mbstate_tEC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5
+ _ZNSt14codecvt_bynameIwc11__mbstate_tEC2ERKSsm@GLIBCXX_3.4.21 5
  _ZNSt14collate_bynameIcEC1EPKcm@GLIBCXX_3.4 4.1.1
  _ZNSt14collate_bynameIcEC2EPKcm@GLIBCXX_3.4 4.1.1
  _ZNSt14collate_bynameIwEC1EPKcm@GLIBCXX_3.4 4.1.1
@@ -356,21 +461,40 @@
  _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE7seekoffElSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
  _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE8_M_pbumpEPwS4_l@GLIBCXX_3.4.16 4.6.0
  _ZNSt15messages_bynameIcEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15messages_bynameIcEC1ERKSsm@GLIBCXX_3.4.21 5
  _ZNSt15messages_bynameIcEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15messages_bynameIcEC2ERKSsm@GLIBCXX_3.4.21 5
  _ZNSt15messages_bynameIwEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15messages_bynameIwEC1ERKSsm@GLIBCXX_3.4.21 5
  _ZNSt15messages_bynameIwEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15messages_bynameIwEC2ERKSsm@GLIBCXX_3.4.21 5
  _ZNSt15numpunct_bynameIcEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIcEC1ERKSsm@GLIBCXX_3.4.21 5
  _ZNSt15numpunct_bynameIcEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIcEC2ERKSsm@GLIBCXX_3.4.21 5
  _ZNSt15numpunct_bynameIwEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIwEC1ERKSsm@GLIBCXX_3.4.21 5
  _ZNSt15numpunct_bynameIwEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15numpunct_bynameIwEC2ERKSsm@GLIBCXX_3.4.21 5
+
  _ZNSt15time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1ERKSsm@GLIBCXX_3.4.21 5
  _ZNSt15time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2ERKSsm@GLIBCXX_3.4.21 5
  _ZNSt15time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1ERKSsm@GLIBCXX_3.4.21 5
  _ZNSt15time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2ERKSsm@GLIBCXX_3.4.21 5
  _ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1ERKNSt7__cxx1112basic_stringIcS2_SaIcEEEm@GLIBCXX_3.4.21 5-20150121-1
+ _ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1ERKSsm@GLIBCXX_3.4.21 5-20150121-1
+ _ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2ERKNSt7__cxx1112basic_stringIcS2_SaIcEEEm@GLIBCXX_3.4.21 5-20150121-1
  _ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2ERKSsm@GLIBCXX_3.4.21 5-20150121-1
  _ZNSt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1ERKSsm@GLIBCXX_3.4.21 5-20150121-1
  _ZNSt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2ERKSsm@GLIBCXX_3.4.21 5-20150121-1
  _ZNSt16__numpunct_cacheIcEC1Em@GLIBCXX_3.4 4.1.1
  _ZNSt16__numpunct_cacheIcEC2Em@GLIBCXX_3.4 4.1.1
  _ZNSt16__numpunct_cacheIwEC1Em@GLIBCXX_3.4 4.1.1
@@ -380,13 +504,21 @@
  _ZNSt17__timepunct_cacheIwEC1Em@GLIBCXX_3.4 4.1.1
  _ZNSt17__timepunct_cacheIwEC2Em@GLIBCXX_3.4 4.1.1
  _ZNSt17moneypunct_bynameIcLb0EEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb0EEC1ERKSsm@GLIBCXX_3.4.21 5
  _ZNSt17moneypunct_bynameIcLb0EEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb0EEC2ERKSsm@GLIBCXX_3.4.21 5
  _ZNSt17moneypunct_bynameIcLb1EEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb1EEC1ERKSsm@GLIBCXX_3.4.21 5
  _ZNSt17moneypunct_bynameIcLb1EEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIcLb1EEC2ERKSsm@GLIBCXX_3.4.21 5
  _ZNSt17moneypunct_bynameIwLb0EEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb0EEC1ERKSsm@GLIBCXX_3.4.21 5
  _ZNSt17moneypunct_bynameIwLb0EEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb0EEC2ERKSsm@GLIBCXX_3.4.21 5
  _ZNSt17moneypunct_bynameIwLb1EEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb1EEC1ERKSsm@GLIBCXX_3.4.21 5
  _ZNSt17moneypunct_bynameIwLb1EEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt17moneypunct_bynameIwLb1EEC2ERKSsm@GLIBCXX_3.4.21 5
  _ZNSt18__moneypunct_cacheIcLb0EEC1Em@GLIBCXX_3.4 4.1.1
  _ZNSt18__moneypunct_cacheIcLb0EEC2Em@GLIBCXX_3.4 4.1.1
  _ZNSt18__moneypunct_cacheIcLb1EEC1Em@GLIBCXX_3.4 4.1.1
@@ -395,6 +527,7 @@
  _ZNSt18__moneypunct_cacheIwLb0EEC2Em@GLIBCXX_3.4 4.1.1
  _ZNSt18__moneypunct_cacheIwLb1EEC1Em@GLIBCXX_3.4 4.1.1
  _ZNSt18__moneypunct_cacheIwLb1EEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt28__atomic_futex_unsigned_base19_M_futex_wait_untilEPjjbNSt6chrono8durationIlSt5ratioILl1ELl1EEEENS2_IlS3_ILl1ELl1000000000EEEE@GLIBCXX_3.4.21 5
  _ZNSt5ctypeIcEC1EP15__locale_structPKtbm@GLIBCXX_3.4 4.1.1
  _ZNSt5ctypeIcEC1EPKtbm@GLIBCXX_3.4 4.1.1
  _ZNSt5ctypeIcEC2EP15__locale_structPKtbm@GLIBCXX_3.4 4.1.1
@@ -412,6 +545,231 @@
  _ZNSt6locale5_ImplC2EPKcm@GLIBCXX_3.4 4.1.1
  _ZNSt6locale5_ImplC2ERKS0_m@GLIBCXX_3.4 4.1.1
  _ZNSt6locale5_ImplC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt7__cxx1110moneypunctIcLb0EEC1EP15__locale_structPKcm@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1110moneypunctIcLb0EEC1EPSt18__moneypunct_cacheIcLb0EEm@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1110moneypunctIcLb0EEC1Em@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1110moneypunctIcLb0EEC2EP15__locale_structPKcm@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1110moneypunctIcLb0EEC2EPSt18__moneypunct_cacheIcLb0EEm@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1110moneypunctIcLb0EEC2Em@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1110moneypunctIcLb1EEC1EP15__locale_structPKcm@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1110moneypunctIcLb1EEC1EPSt18__moneypunct_cacheIcLb1EEm@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1110moneypunctIcLb1EEC1Em@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1110moneypunctIcLb1EEC2EP15__locale_structPKcm@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1110moneypunctIcLb1EEC2EPSt18__moneypunct_cacheIcLb1EEm@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1110moneypunctIcLb1EEC2Em@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1110moneypunctIwLb0EEC1EP15__locale_structPKcm@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1110moneypunctIwLb0EEC1EPSt18__moneypunct_cacheIwLb0EEm@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1110moneypunctIwLb0EEC1Em@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1110moneypunctIwLb0EEC2EP15__locale_structPKcm@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1110moneypunctIwLb0EEC2EPSt18__moneypunct_cacheIwLb0EEm@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1110moneypunctIwLb0EEC2Em@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1110moneypunctIwLb1EEC1EP15__locale_structPKcm@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1110moneypunctIwLb1EEC1EPSt18__moneypunct_cacheIwLb1EEm@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1110moneypunctIwLb1EEC1Em@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1110moneypunctIwLb1EEC2EP15__locale_structPKcm@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1110moneypunctIwLb1EEC2EPSt18__moneypunct_cacheIwLb1EEm@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1110moneypunctIwLb1EEC2Em@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_destroyEm@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_S_compareEmm@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_capacityEm@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructEmc@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13_M_set_lengthEm@GLIBCXX_3.4.21 5
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+ _ZNSt7__cxx118messagesIcEC2Em@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118messagesIwEC1EP15__locale_structPKcm@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118messagesIwEC1Em@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118messagesIwEC2EP15__locale_structPKcm@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118messagesIwEC2Em@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118numpunctIcEC1EP15__locale_structm@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118numpunctIcEC1EPSt16__numpunct_cacheIcEm@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118numpunctIcEC1Em@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118numpunctIcEC2EP15__locale_structm@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118numpunctIcEC2EPSt16__numpunct_cacheIcEm@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118numpunctIcEC2Em@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118numpunctIwEC1EP15__locale_structm@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118numpunctIwEC1EPSt16__numpunct_cacheIwEm@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118numpunctIwEC1Em@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118numpunctIwEC2EP15__locale_structm@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118numpunctIwEC2EPSt16__numpunct_cacheIwEm@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118numpunctIwEC2Em@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_3.4.21 5
+ _ZNSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_3.4.21 5
  _ZNSt7codecvtIcc11__mbstate_tEC1EP15__locale_structm@GLIBCXX_3.4 4.1.1
  _ZNSt7codecvtIcc11__mbstate_tEC1Em@GLIBCXX_3.4 4.1.1
  _ZNSt7codecvtIcc11__mbstate_tEC2EP15__locale_structm@GLIBCXX_3.4 4.1.1
@@ -485,6 +843,7 @@
  _ZSt16__ostream_insertIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKS3_l@GLIBCXX_3.4.9 4.2.1
  _ZSt17__copy_streambufsIcSt11char_traitsIcEElPSt15basic_streambufIT_T0_ES6_@GLIBCXX_3.4.8 4.1.1
  _ZSt17__copy_streambufsIwSt11char_traitsIwEElPSt15basic_streambufIT_T0_ES6_@GLIBCXX_3.4.8 4.1.1
+ _ZSt17__verify_groupingPKcmRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
  _ZSt17__verify_groupingPKcmRKSs@GLIBCXX_3.4.10 4.3
  _ZSt21__copy_streambufs_eofIcSt11char_traitsIcEElPSt15basic_streambufIT_T0_ES6_Rb@GLIBCXX_3.4.9 4.2.1
  _ZSt21__copy_streambufs_eofIwSt11char_traitsIwEElPSt15basic_streambufIT_T0_ES6_Rb@GLIBCXX_3.4.9 4.2.1
@@ -506,6 +865,10 @@
  _ZThn16_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
  _ZThn16_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
  _ZThn16_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn16_NSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4.21 5
+ _ZThn16_NSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4.21 5
+ _ZThn16_NSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4.21 5
+ _ZThn16_NSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4.21 5
  _ZThn16_NSt9strstreamD0Ev@GLIBCXX_3.4 4.1.1
  _ZThn16_NSt9strstreamD1Ev@GLIBCXX_3.4 4.1.1
  _ZTv0_n24_NSdD0Ev@GLIBCXX_3.4 4.1.1
@@ -548,8 +911,22 @@
  _ZTv0_n24_NSt19basic_ostringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
  _ZTv0_n24_NSt19basic_ostringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
  _ZTv0_n24_NSt19basic_ostringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4.21 5
+ _ZTv0_n24_NSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4.21 5
+ _ZTv0_n24_NSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4.21 5
+ _ZTv0_n24_NSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4.21 5
+ _ZTv0_n24_NSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4.21 5
+ _ZTv0_n24_NSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4.21 5
+ _ZTv0_n24_NSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4.21 5
+ _ZTv0_n24_NSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4.21 5
+ _ZTv0_n24_NSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4.21 5
+ _ZTv0_n24_NSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4.21 5
+ _ZTv0_n24_NSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4.21 5
+ _ZTv0_n24_NSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4.21 5
  _ZTv0_n24_NSt9strstreamD0Ev@GLIBCXX_3.4 4.1.1
  _ZTv0_n24_NSt9strstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _ZdaPvm@CXXABI_1.3.9 5
+ _ZdlPvm@CXXABI_1.3.9 5
  _Znam@GLIBCXX_3.4 4.1.1
  _ZnamRKSt9nothrow_t@GLIBCXX_3.4 4.1.1
  _Znwm@GLIBCXX_3.4 4.1.1
diff --git a/debian/libstdc++6.symbols.common b/debian/libstdc++6.symbols.common
index 9a24292..23523a3 100644
--- a/debian/libstdc++6.symbols.common
+++ b/debian/libstdc++6.symbols.common
@@ -6,7 +6,9 @@
  CXXABI_1.3.6@CXXABI_1.3.6 4.7
  CXXABI_1.3.7@CXXABI_1.3.7 4.8
  CXXABI_1.3.8@CXXABI_1.3.8 4.9
+ CXXABI_1.3.9@CXXABI_1.3.9 5
  CXXABI_1.3@CXXABI_1.3 4.1.1
+ CXXABI_FLOAT128@CXXABI_FLOAT128 5
  CXXABI_TM_1@CXXABI_TM_1 4.7
  GLIBCXX_3.4.10@GLIBCXX_3.4.10 4.3
  GLIBCXX_3.4.11@GLIBCXX_3.4.11 4.4.0
@@ -20,6 +22,7 @@
  GLIBCXX_3.4.19@GLIBCXX_3.4.19 4.8
  GLIBCXX_3.4.1@GLIBCXX_3.4.1 4.1.1
  GLIBCXX_3.4.20@GLIBCXX_3.4.20 4.9
+ GLIBCXX_3.4.21@GLIBCXX_3.4.21 5
  GLIBCXX_3.4.2@GLIBCXX_3.4.2 4.1.1
  GLIBCXX_3.4.3@GLIBCXX_3.4.3 4.1.1
  GLIBCXX_3.4.4@GLIBCXX_3.4.4 4.1.1
@@ -35,6 +38,22 @@
  _ZGVNSt10moneypunctIwLb1EE2idE@GLIBCXX_3.4 4.1.1
  _ZGVNSt11__timepunctIcE2idE@GLIBCXX_3.4 4.1.1
  _ZGVNSt11__timepunctIwE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt7__cxx1110moneypunctIcLb0EE2idE@GLIBCXX_3.4.21 5
+ _ZGVNSt7__cxx1110moneypunctIcLb1EE2idE@GLIBCXX_3.4.21 5
+ _ZGVNSt7__cxx1110moneypunctIwLb0EE2idE@GLIBCXX_3.4.21 5
+ _ZGVNSt7__cxx1110moneypunctIwLb1EE2idE@GLIBCXX_3.4.21 5
+ _ZGVNSt7__cxx117collateIcE2idE@GLIBCXX_3.4.21 5
+ _ZGVNSt7__cxx117collateIwE2idE@GLIBCXX_3.4.21 5
+ _ZGVNSt7__cxx118messagesIcE2idE@GLIBCXX_3.4.21 5
+ _ZGVNSt7__cxx118messagesIwE2idE@GLIBCXX_3.4.21 5
+ _ZGVNSt7__cxx118numpunctIcE2idE@GLIBCXX_3.4.21 5
+ _ZGVNSt7__cxx118numpunctIwE2idE@GLIBCXX_3.4.21 5
+ _ZGVNSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_3.4.21 5
+ _ZGVNSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_3.4.21 5
+ _ZGVNSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_3.4.21 5
+ _ZGVNSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_3.4.21 5
+ _ZGVNSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_3.4.21 5
+ _ZGVNSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_3.4.21 5
  _ZGVNSt7collateIcE2idE@GLIBCXX_3.4 4.1.1
  _ZGVNSt7collateIwE2idE@GLIBCXX_3.4 4.1.1
  _ZGVNSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_3.4 4.1.1
@@ -114,10 +133,13 @@
  _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE8overflowEi@GLIBCXX_3.4.10 4.3.0~rc2
  _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE9pbackfailEi@GLIBCXX_3.4.10 4.3.0~rc2
  _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE9underflowEv@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEEC1EOS3_@GLIBCXX_3.4.21 5
  _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEEC1EP8_IO_FILE@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEEC2EOS3_@GLIBCXX_3.4.21 5
  _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEEC2EP8_IO_FILE@GLIBCXX_3.4.10 4.3.0~rc2
  _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4.10 4.3.0~rc2
  _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEEaSEOS3_@GLIBCXX_3.4.21 5
  _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE4fileEv@GLIBCXX_3.4.2 4.1.1
  _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE4syncEv@GLIBCXX_3.4.10 4.3.0~rc2
  _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE5uflowEv@GLIBCXX_3.4.10 4.3.0~rc2
@@ -125,10 +147,13 @@
  _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE8overflowEj@GLIBCXX_3.4.10 4.3.0~rc2
  _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE9pbackfailEj@GLIBCXX_3.4.10 4.3.0~rc2
  _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE9underflowEv@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEEC1EOS3_@GLIBCXX_3.4.21 5
  _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEEC1EP8_IO_FILE@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEEC2EOS3_@GLIBCXX_3.4.21 5
  _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEEC2EP8_IO_FILE@GLIBCXX_3.4.10 4.3.0~rc2
  _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4.10 4.3.0~rc2
  _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEEaSEOS3_@GLIBCXX_3.4.21 5
  _ZN9__gnu_cxx27__verbose_terminate_handlerEv@CXXABI_1.3 4.1.1
  _ZN9__gnu_cxx6__poolILb0EE10_M_destroyEv@GLIBCXX_3.4.4 4.1.1
  _ZN9__gnu_cxx6__poolILb0EE13_M_initializeEv@GLIBCXX_3.4.4 4.1.1
@@ -368,6 +393,24 @@
  _ZNKSt18basic_stringstreamIcSt11char_traitsIcESaIcEE5rdbufEv@GLIBCXX_3.4 4.1.1
  _ZNKSt18basic_stringstreamIwSt11char_traitsIwESaIwEE3strEv@GLIBCXX_3.4 4.1.1
  _ZNKSt18basic_stringstreamIwSt11char_traitsIwESaIwEE5rdbufEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt19__codecvt_utf8_baseIDiE10do_unshiftER11__mbstate_tPcS3_RS3_@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIDiE11do_encodingEv@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIDiE13do_max_lengthEv@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIDiE16do_always_noconvEv@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIDiE5do_inER11__mbstate_tPKcS4_RS4_PDiS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIDiE6do_outER11__mbstate_tPKDiS4_RS4_PcS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIDsE10do_unshiftER11__mbstate_tPcS3_RS3_@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIDsE11do_encodingEv@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIDsE13do_max_lengthEv@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIDsE16do_always_noconvEv@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIDsE5do_inER11__mbstate_tPKcS4_RS4_PDsS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIDsE6do_outER11__mbstate_tPKDsS4_RS4_PcS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIwE10do_unshiftER11__mbstate_tPcS3_RS3_@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIwE11do_encodingEv@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIwE13do_max_lengthEv@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIwE16do_always_noconvEv@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIwE5do_inER11__mbstate_tPKcS4_RS4_PwS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIwE6do_outER11__mbstate_tPKwS4_RS4_PcS6_RS6_@GLIBCXX_3.4.21 5
  _ZNKSt19basic_istringstreamIcSt11char_traitsIcESaIcEE3strEv@GLIBCXX_3.4 4.1.1
  _ZNKSt19basic_istringstreamIcSt11char_traitsIcESaIcEE5rdbufEv@GLIBCXX_3.4 4.1.1
  _ZNKSt19basic_istringstreamIwSt11char_traitsIwESaIwEE3strEv@GLIBCXX_3.4 4.1.1
@@ -376,7 +419,50 @@
  _ZNKSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE5rdbufEv@GLIBCXX_3.4 4.1.1
  _ZNKSt19basic_ostringstreamIwSt11char_traitsIwESaIwEE3strEv@GLIBCXX_3.4 4.1.1
  _ZNKSt19basic_ostringstreamIwSt11char_traitsIwESaIwEE5rdbufEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt20__codecvt_utf16_baseIDiE10do_unshiftER11__mbstate_tPcS3_RS3_@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDiE11do_encodingEv@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDiE13do_max_lengthEv@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDiE16do_always_noconvEv@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDiE5do_inER11__mbstate_tPKcS4_RS4_PDiS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDiE6do_outER11__mbstate_tPKDiS4_RS4_PcS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDsE10do_unshiftER11__mbstate_tPcS3_RS3_@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDsE11do_encodingEv@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDsE13do_max_lengthEv@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDsE16do_always_noconvEv@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDsE5do_inER11__mbstate_tPKcS4_RS4_PDsS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDsE6do_outER11__mbstate_tPKDsS4_RS4_PcS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIwE10do_unshiftER11__mbstate_tPcS3_RS3_@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIwE11do_encodingEv@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIwE13do_max_lengthEv@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIwE16do_always_noconvEv@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIwE5do_inER11__mbstate_tPKcS4_RS4_PwS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIwE6do_outER11__mbstate_tPKwS4_RS4_PcS6_RS6_@GLIBCXX_3.4.21 5
  _ZNKSt20bad_array_new_length4whatEv@CXXABI_1.3.8 4.9
+ _ZNKSt25__codecvt_utf8_utf16_baseIDiE10do_unshiftER11__mbstate_tPcS3_RS3_@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDiE11do_encodingEv@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDiE13do_max_lengthEv@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDiE16do_always_noconvEv@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDiE5do_inER11__mbstate_tPKcS4_RS4_PDiS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDiE6do_outER11__mbstate_tPKDiS4_RS4_PcS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDsE10do_unshiftER11__mbstate_tPcS3_RS3_@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDsE11do_encodingEv@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDsE13do_max_lengthEv@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDsE16do_always_noconvEv@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDsE5do_inER11__mbstate_tPKcS4_RS4_PDsS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDsE6do_outER11__mbstate_tPKDsS4_RS4_PcS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIwE10do_unshiftER11__mbstate_tPcS3_RS3_@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIwE11do_encodingEv@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIwE13do_max_lengthEv@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIwE16do_always_noconvEv@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIwE5do_inER11__mbstate_tPKcS4_RS4_PwS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIwE6do_outER11__mbstate_tPKwS4_RS4_PcS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt3_V214error_category10_M_messageB5cxx11Ei@GLIBCXX_3.4.21 5
+ _ZNKSt3_V214error_category10_M_messageEi@GLIBCXX_3.4.21 5
+ _ZNKSt3_V214error_category10equivalentERKSt10error_codei@GLIBCXX_3.4.21 5
+ _ZNKSt3_V214error_category10equivalentEiRKSt15error_condition@GLIBCXX_3.4.21 5
+ _ZNKSt3_V214error_category23default_error_conditionEi@GLIBCXX_3.4.21 5
+ _ZNKSt3tr14hashINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEEclES6_@GLIBCXX_3.4.21 5
+ _ZNKSt3tr14hashINSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEEEclES6_@GLIBCXX_3.4.21 5
  _ZNKSt3tr14hashIRKSbIwSt11char_traitsIwESaIwEEEclES6_@GLIBCXX_3.4.10 4.3
  _ZNKSt3tr14hashIRKSsEclES2_@GLIBCXX_3.4.10 4.3
  _ZNKSt3tr14hashISbIwSt11char_traitsIwESaIwEEEclES4_@GLIBCXX_3.4.10 4.3
@@ -410,8 +496,265 @@
  _ZNKSt5ctypeIwE9do_narrowEPKwS2_cPc@GLIBCXX_3.4 4.1.1
  _ZNKSt5ctypeIwE9do_narrowEwc@GLIBCXX_3.4 4.1.1
  _ZNKSt6locale2id5_M_idEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt6locale4nameB5cxx11Ev@GLIBCXX_3.4.21 5
  _ZNKSt6locale4nameEv@GLIBCXX_3.4 4.1.1
  _ZNKSt6localeeqERKS_@GLIBCXX_3.4 4.1.1
+ _ZNKSt7__cxx1110moneypunctIcLb0EE10neg_formatEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb0EE10pos_formatEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb0EE11curr_symbolEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb0EE11do_groupingEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb0EE11frac_digitsEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb0EE13decimal_pointEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb0EE13do_neg_formatEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb0EE13do_pos_formatEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb0EE13negative_signEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb0EE13positive_signEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb0EE13thousands_sepEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb0EE14do_curr_symbolEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb0EE14do_frac_digitsEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb0EE16do_decimal_pointEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb0EE16do_negative_signEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb0EE16do_positive_signEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb0EE16do_thousands_sepEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb0EE8groupingEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb1EE10neg_formatEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb1EE10pos_formatEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb1EE11curr_symbolEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb1EE11do_groupingEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb1EE11frac_digitsEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb1EE13decimal_pointEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb1EE13do_neg_formatEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb1EE13do_pos_formatEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb1EE13negative_signEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb1EE13positive_signEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb1EE13thousands_sepEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb1EE14do_curr_symbolEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb1EE14do_frac_digitsEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb1EE16do_decimal_pointEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb1EE16do_negative_signEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb1EE16do_positive_signEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb1EE16do_thousands_sepEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIcLb1EE8groupingEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb0EE10neg_formatEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb0EE10pos_formatEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb0EE11curr_symbolEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb0EE11do_groupingEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb0EE11frac_digitsEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb0EE13decimal_pointEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb0EE13do_neg_formatEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb0EE13do_pos_formatEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb0EE13negative_signEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb0EE13positive_signEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb0EE13thousands_sepEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb0EE14do_curr_symbolEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb0EE14do_frac_digitsEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb0EE16do_decimal_pointEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb0EE16do_negative_signEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb0EE16do_positive_signEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb0EE16do_thousands_sepEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb0EE8groupingEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb1EE10neg_formatEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb1EE10pos_formatEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb1EE11curr_symbolEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb1EE11do_groupingEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb1EE11frac_digitsEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb1EE13decimal_pointEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb1EE13do_neg_formatEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb1EE13do_pos_formatEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb1EE13negative_signEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb1EE13positive_signEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb1EE13thousands_sepEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb1EE14do_curr_symbolEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb1EE14do_frac_digitsEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb1EE16do_decimal_pointEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb1EE16do_negative_signEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb1EE16do_positive_signEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb1EE16do_thousands_sepEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1110moneypunctIwLb1EE8groupingEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_disjunctEPKc@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13_M_local_dataEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13get_allocatorEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE16_M_get_allocatorEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE3endEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4backEv@GLIBCXX_3.4.21 5
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+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4dataEv@GLIBCXX_3.4.21 5
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+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5beginEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5c_strEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5crendEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5emptyEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5frontEv@GLIBCXX_3.4.21 5
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+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13get_allocatorEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE16_M_get_allocatorEv@GLIBCXX_3.4.21 5
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+ _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4backEv@GLIBCXX_3.4.21 5
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+ _ZNKSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEE3strEv@GLIBCXX_3.4.21 5
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+ _ZNKSt7__cxx117collateIcE10_M_compareEPKcS3_@GLIBCXX_3.4.21 5
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+ _ZNKSt7__cxx118messagesIcE20_M_convert_from_charEPc@GLIBCXX_3.4.21 5
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+ _ZNKSt7__cxx118messagesIcE4openERKNS_12basic_stringIcSt11char_traitsIcESaIcEEERKSt6localePKc@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118messagesIcE5closeEi@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118messagesIcE6do_getEiiiRKNS_12basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118messagesIcE7do_openERKNS_12basic_stringIcSt11char_traitsIcESaIcEEERKSt6locale@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118messagesIcE8do_closeEi@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118messagesIwE18_M_convert_to_charERKNS_12basic_stringIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118messagesIwE20_M_convert_from_charEPc@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118messagesIwE3getEiiiRKNS_12basic_stringIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118messagesIwE4openERKNS_12basic_stringIcSt11char_traitsIcESaIcEEERKSt6locale@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118messagesIwE4openERKNS_12basic_stringIcSt11char_traitsIcESaIcEEERKSt6localePKc@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118messagesIwE5closeEi@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118messagesIwE6do_getEiiiRKNS_12basic_stringIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118messagesIwE7do_openERKNS_12basic_stringIcSt11char_traitsIcESaIcEEERKSt6locale@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118messagesIwE8do_closeEi@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118numpunctIcE11do_groupingEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118numpunctIcE11do_truenameEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118numpunctIcE12do_falsenameEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118numpunctIcE13decimal_pointEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118numpunctIcE13thousands_sepEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118numpunctIcE16do_decimal_pointEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118numpunctIcE16do_thousands_sepEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118numpunctIcE8groupingEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118numpunctIcE8truenameEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118numpunctIcE9falsenameEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118numpunctIwE11do_groupingEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118numpunctIwE11do_truenameEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118numpunctIwE12do_falsenameEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118numpunctIwE13decimal_pointEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118numpunctIwE13thousands_sepEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118numpunctIwE16do_decimal_pointEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118numpunctIwE16do_thousands_sepEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118numpunctIwE8groupingEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118numpunctIwE8truenameEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118numpunctIwE9falsenameEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE10date_orderEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE11do_get_dateES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE11do_get_timeES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE11do_get_yearES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE11get_weekdayES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE13do_date_orderEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE13get_monthnameES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14do_get_weekdayES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE16do_get_monthnameES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE21_M_extract_via_formatES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tmPKc@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tmPKcSD_@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tmcc@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tmcc@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE8get_dateES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE8get_timeES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE8get_yearES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE10date_orderEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE11do_get_dateES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE11do_get_timeES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE11do_get_yearES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE11get_weekdayES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE13do_date_orderEv@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE13get_monthnameES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14do_get_weekdayES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE16do_get_monthnameES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE21_M_extract_via_formatES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tmPKw@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tmPKwSD_@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tmcc@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tmcc@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE8get_dateES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE8get_timeES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE8get_yearES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE10_M_extractILb0EEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRNS_12basic_stringIcS3_SaIcEEE@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE10_M_extractILb1EEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRNS_12basic_stringIcS3_SaIcEEE@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRNS_12basic_stringIcS3_SaIcEEE@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRe@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRNS_12basic_stringIcS3_SaIcEEE@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRe@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE10_M_extractILb0EEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRNS_12basic_stringIcS2_IcESaIcEEE@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE10_M_extractILb1EEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRNS_12basic_stringIcS2_IcESaIcEEE@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRNS_12basic_stringIwS3_SaIwEEE@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRe@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRNS_12basic_stringIwS3_SaIwEEE@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRe@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_bRSt8ios_basecRKNS_12basic_stringIcS3_SaIcEEE@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_bRSt8ios_basece@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_bRSt8ios_basecRKNS_12basic_stringIcS3_SaIcEEE@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_bRSt8ios_basece@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE9_M_insertILb0EEES4_S4_RSt8ios_basecRKNS_12basic_stringIcS3_SaIcEEE@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE9_M_insertILb1EEES4_S4_RSt8ios_basecRKNS_12basic_stringIcS3_SaIcEEE@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_bRSt8ios_basewRKNS_12basic_stringIwS3_SaIwEEE@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_bRSt8ios_basewe@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_bRSt8ios_basewRKNS_12basic_stringIwS3_SaIwEEE@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_bRSt8ios_basewe@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE9_M_insertILb0EEES4_S4_RSt8ios_basewRKNS_12basic_stringIwS3_SaIwEEE@GLIBCXX_3.4.21 5
+ _ZNKSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE9_M_insertILb1EEES4_S4_RSt8ios_basewRKNS_12basic_stringIwS3_SaIwEEE@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDic11__mbstate_tE10do_unshiftERS0_PcS3_RS3_@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDic11__mbstate_tE11do_encodingEv@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDic11__mbstate_tE13do_max_lengthEv@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDic11__mbstate_tE16do_always_noconvEv@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDic11__mbstate_tE5do_inERS0_PKcS4_RS4_PDiS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDic11__mbstate_tE6do_outERS0_PKDiS4_RS4_PcS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDsc11__mbstate_tE10do_unshiftERS0_PcS3_RS3_@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDsc11__mbstate_tE11do_encodingEv@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDsc11__mbstate_tE13do_max_lengthEv@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDsc11__mbstate_tE16do_always_noconvEv@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDsc11__mbstate_tE5do_inERS0_PKcS4_RS4_PDsS6_RS6_@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDsc11__mbstate_tE6do_outERS0_PKDsS4_RS4_PcS6_RS6_@GLIBCXX_3.4.21 5
  _ZNKSt7codecvtIcc11__mbstate_tE10do_unshiftERS0_PcS3_RS3_@GLIBCXX_3.4 4.1.1
  _ZNKSt7codecvtIcc11__mbstate_tE11do_encodingEv@GLIBCXX_3.4 4.1.1
  _ZNKSt7codecvtIcc11__mbstate_tE13do_max_lengthEv@GLIBCXX_3.4 4.1.1
@@ -542,6 +885,7 @@
  _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES3_RSt8ios_basewy@GLIBCXX_3.4 4.1.1
  _ZNKSt8bad_cast4whatEv@GLIBCXX_3.4.9 4.2.1
  _ZNKSt8ios_base7failure4whatEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8ios_base7failureB5cxx114whatEv@GLIBCXX_3.4.21 5
  _ZNKSt8messagesIcE18_M_convert_to_charERKSs@GLIBCXX_3.4 4.1.1
  _ZNKSt8messagesIcE20_M_convert_from_charEPc@GLIBCXX_3.4 4.1.1
  _ZNKSt8messagesIcE3getEiiiRKSs@GLIBCXX_3.4 4.1.1
@@ -589,6 +933,8 @@
  _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE13get_monthnameES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
  _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14do_get_weekdayES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
  _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE16do_get_monthnameES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tmPKcSC_@GLIBCXX_3.4.21 5
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tmcc@GLIBCXX_3.4.21 5
  _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE21_M_extract_via_formatES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tmPKc@GLIBCXX_3.4 4.1.1
  _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE8get_dateES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
  _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE8get_timeES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
@@ -603,6 +949,8 @@
  _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14do_get_weekdayES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
  _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE16do_get_monthnameES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
  _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE21_M_extract_via_formatES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tmPKw@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tmPKwSC_@GLIBCXX_3.4.21 5
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tmcc@GLIBCXX_3.4.21 5
  _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE8get_dateES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
  _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE8get_timeES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
  _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE8get_yearES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
@@ -625,6 +973,7 @@
  _ZNKSt9basic_iosIcSt11char_traitsIcEE6narrowEcc@GLIBCXX_3.4 4.1.1
  _ZNKSt9basic_iosIcSt11char_traitsIcEE7rdstateEv@GLIBCXX_3.4 4.1.1
  _ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9basic_iosIcSt11char_traitsIcEEcvbEv@GLIBCXX_3.4.21 5
  _ZNKSt9basic_iosIcSt11char_traitsIcEEntEv@GLIBCXX_3.4 4.1.1
  _ZNKSt9basic_iosIwSt11char_traitsIwEE10exceptionsEv@GLIBCXX_3.4 4.1.1
  _ZNKSt9basic_iosIwSt11char_traitsIwEE3badEv@GLIBCXX_3.4 4.1.1
@@ -638,6 +987,7 @@
  _ZNKSt9basic_iosIwSt11char_traitsIwEE6narrowEwc@GLIBCXX_3.4 4.1.1
  _ZNKSt9basic_iosIwSt11char_traitsIwEE7rdstateEv@GLIBCXX_3.4 4.1.1
  _ZNKSt9basic_iosIwSt11char_traitsIwEEcvPvEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9basic_iosIwSt11char_traitsIwEEcvbEv@GLIBCXX_3.4.21 5
  _ZNKSt9basic_iosIwSt11char_traitsIwEEntEv@GLIBCXX_3.4 4.1.1
  _ZNKSt9exception4whatEv@GLIBCXX_3.4 4.1.1
  _ZNKSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE10_M_extractILb0EEES3_S3_S3_RSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_3.4 4.1.1
@@ -765,13 +1115,17 @@
  _ZNSbIwSt11char_traitsIwESaIwEEpLERKS2_@GLIBCXX_3.4 4.1.1
  _ZNSbIwSt11char_traitsIwESaIwEEpLESt16initializer_listIwE@GLIBCXX_3.4.11 4.4.0
  _ZNSbIwSt11char_traitsIwESaIwEEpLEw@GLIBCXX_3.4 4.1.1
+ _ZNSd4swapERSd@GLIBCXX_3.4.21 5
+ _ZNSdC1EOSd@GLIBCXX_3.4.21 5
  _ZNSdC1EPSt15basic_streambufIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
  _ZNSdC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSdC2EOSd@GLIBCXX_3.4.21 5
  _ZNSdC2EPSt15basic_streambufIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
  _ZNSdC2Ev@GLIBCXX_3.4 4.1.1
  _ZNSdD0Ev@GLIBCXX_3.4 4.1.1
  _ZNSdD1Ev@GLIBCXX_3.4 4.1.1
  _ZNSdD2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSdaSEOSd@GLIBCXX_3.4.21 5
  _ZNSi10_M_extractIPvEERSiRT_@GLIBCXX_3.4.9 4.2.1
  _ZNSi10_M_extractIbEERSiRT_@GLIBCXX_3.4.9 4.2.1
  _ZNSi10_M_extractIdEERSiRT_@GLIBCXX_3.4.9 4.2.1
@@ -788,6 +1142,7 @@
  _ZNSi3getERc@GLIBCXX_3.4 4.1.1
  _ZNSi3getEv@GLIBCXX_3.4 4.1.1
  _ZNSi4peekEv@GLIBCXX_3.4 4.1.1
+ _ZNSi4swapERSi@GLIBCXX_3.4.21 5
  _ZNSi4syncEv@GLIBCXX_3.4 4.1.1
  _ZNSi5seekgESt4fposI11__mbstate_tE@GLIBCXX_3.4 4.1.1
  _ZNSi5tellgEv@GLIBCXX_3.4 4.1.1
@@ -797,13 +1152,16 @@
  _ZNSi6sentryC1ERSib@GLIBCXX_3.4 4.1.1
  _ZNSi6sentryC2ERSib@GLIBCXX_3.4 4.1.1
  _ZNSi7putbackEc@GLIBCXX_3.4 4.1.1
+ _ZNSiC1EOSi@GLIBCXX_3.4.21 5
  _ZNSiC1EPSt15basic_streambufIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
  _ZNSiC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSiC2EOSi@GLIBCXX_3.4.21 5
  _ZNSiC2EPSt15basic_streambufIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
  _ZNSiC2Ev@GLIBCXX_3.4 4.1.1
  _ZNSiD0Ev@GLIBCXX_3.4 4.1.1
  _ZNSiD1Ev@GLIBCXX_3.4 4.1.1
  _ZNSiD2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSiaSEOSi@GLIBCXX_3.4.21 5
  _ZNSirsEPFRSiS_E@GLIBCXX_3.4 4.1.1
  _ZNSirsEPFRSt8ios_baseS0_E@GLIBCXX_3.4 4.1.1
  _ZNSirsEPFRSt9basic_iosIcSt11char_traitsIcEES3_E@GLIBCXX_3.4 4.1.1
@@ -822,6 +1180,7 @@
  _ZNSirsERx@GLIBCXX_3.4 4.1.1
  _ZNSirsERy@GLIBCXX_3.4 4.1.1
  _ZNSo3putEc@GLIBCXX_3.4 4.1.1
+ _ZNSo4swapERSo@GLIBCXX_3.4.21 5
  _ZNSo5flushEv@GLIBCXX_3.4 4.1.1
  _ZNSo5seekpESt4fposI11__mbstate_tE@GLIBCXX_3.4 4.1.1
  _ZNSo5tellpEv@GLIBCXX_3.4 4.1.1
@@ -837,13 +1196,18 @@
  _ZNSo9_M_insertImEERSoT_@GLIBCXX_3.4.9 4.2.1
  _ZNSo9_M_insertIxEERSoT_@GLIBCXX_3.4.9 4.2.1
  _ZNSo9_M_insertIyEERSoT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSoC1EOSo@GLIBCXX_3.4.21 5
  _ZNSoC1EPSt15basic_streambufIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
+ _ZNSoC1ERSd@GLIBCXX_3.4.21 5
  _ZNSoC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSoC2EOSo@GLIBCXX_3.4.21 5
  _ZNSoC2EPSt15basic_streambufIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
+ _ZNSoC2ERSd@GLIBCXX_3.4.21 5
  _ZNSoC2Ev@GLIBCXX_3.4 4.1.1
  _ZNSoD0Ev@GLIBCXX_3.4 4.1.1
  _ZNSoD1Ev@GLIBCXX_3.4 4.1.1
  _ZNSoD2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSoaSEOSo@GLIBCXX_3.4.21 5
  _ZNSolsEPFRSoS_E@GLIBCXX_3.4 4.1.1
  _ZNSolsEPFRSt8ios_baseS0_E@GLIBCXX_3.4 4.1.1
  _ZNSolsEPFRSt9basic_iosIcSt11char_traitsIcEES3_E@GLIBCXX_3.4 4.1.1
@@ -944,6 +1308,12 @@
  _ZNSspLERKSs@GLIBCXX_3.4 4.1.1
  _ZNSspLESt16initializer_listIcE@GLIBCXX_3.4.11 4.4.0
  _ZNSspLEc@GLIBCXX_3.4 4.1.1
+ _ZNSt10_Sp_lockerC1EPKv@GLIBCXX_3.4.21 5
+ _ZNSt10_Sp_lockerC1EPKvS1_@GLIBCXX_3.4.21 5
+ _ZNSt10_Sp_lockerC2EPKv@GLIBCXX_3.4.21 5
+ _ZNSt10_Sp_lockerC2EPKvS1_@GLIBCXX_3.4.21 5
+ _ZNSt10_Sp_lockerD1Ev@GLIBCXX_3.4.21 5
+ _ZNSt10_Sp_lockerD2Ev@GLIBCXX_3.4.21 5
  _ZNSt10__num_base11_S_atoms_inE@GLIBCXX_3.4 4.1.1
  _ZNSt10__num_base12_S_atoms_outE@GLIBCXX_3.4 4.1.1
  _ZNSt10__num_base15_S_format_floatERKSt8ios_basePcc@GLIBCXX_3.4 4.1.1
@@ -952,6 +1322,7 @@
  _ZNSt10bad_typeidD2Ev@GLIBCXX_3.4 4.1.1
  _ZNSt10ctype_base5alnumE@GLIBCXX_3.4 4.1.1
  _ZNSt10ctype_base5alphaE@GLIBCXX_3.4 4.1.1
+ _ZNSt10ctype_base5blankE@GLIBCXX_3.4.21 5
  _ZNSt10ctype_base5cntrlE@GLIBCXX_3.4 4.1.1
  _ZNSt10ctype_base5digitE@GLIBCXX_3.4 4.1.1
  _ZNSt10ctype_base5graphE@GLIBCXX_3.4 4.1.1
@@ -1019,17 +1390,29 @@
  _ZNSt11char_traitsIcE2eqERKcS2_@GLIBCXX_3.4.5 4.1.1
  _ZNSt11char_traitsIwE2eqERKwS2_@GLIBCXX_3.4 4.1.1
  _ZNSt11char_traitsIwE2eqERKwS2_@GLIBCXX_3.4.5 4.1.1
+ _ZNSt11logic_errorC1EPKc@GLIBCXX_3.4.21 5
+ _ZNSt11logic_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
+ _ZNSt11logic_errorC1ERKS_@GLIBCXX_3.4.21 5
  _ZNSt11logic_errorC1ERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt11logic_errorC2EPKc@GLIBCXX_3.4.21 5
+ _ZNSt11logic_errorC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
+ _ZNSt11logic_errorC2ERKS_@GLIBCXX_3.4.21 5
  _ZNSt11logic_errorC2ERKSs@GLIBCXX_3.4 4.1.1
  _ZNSt11logic_errorD0Ev@GLIBCXX_3.4 4.1.1
  _ZNSt11logic_errorD1Ev@GLIBCXX_3.4 4.1.1
  _ZNSt11logic_errorD2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt11logic_erroraSERKS_@GLIBCXX_3.4.21 5
+ _ZNSt11range_errorC1EPKc@GLIBCXX_3.4.21 5
+ _ZNSt11range_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
  _ZNSt11range_errorC1ERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt11range_errorC2EPKc@GLIBCXX_3.4.21 5
+ _ZNSt11range_errorC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
  _ZNSt11range_errorC2ERKSs@GLIBCXX_3.4 4.1.1
  _ZNSt11range_errorD0Ev@GLIBCXX_3.4 4.1.1
  _ZNSt11range_errorD1Ev@GLIBCXX_3.4 4.1.1
  _ZNSt11range_errorD2Ev@GLIBCXX_3.4.15 4.6
  _ZNSt11regex_errorC1ENSt15regex_constants10error_typeE@GLIBCXX_3.4.20 4.9
+ _ZNSt11regex_errorC2ENSt15regex_constants10error_typeE@GLIBCXX_3.4.21 5
  _ZNSt11regex_errorD0Ev@GLIBCXX_3.4.15 4.6
  _ZNSt11regex_errorD1Ev@GLIBCXX_3.4.15 4.6
  _ZNSt11regex_errorD2Ev@GLIBCXX_3.4.15 4.6
@@ -1052,7 +1435,11 @@
  _ZNSt12ctype_bynameIwED0Ev@GLIBCXX_3.4 4.1.1
  _ZNSt12ctype_bynameIwED1Ev@GLIBCXX_3.4 4.1.1
  _ZNSt12ctype_bynameIwED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt12domain_errorC1EPKc@GLIBCXX_3.4.21 5
+ _ZNSt12domain_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
  _ZNSt12domain_errorC1ERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt12domain_errorC2EPKc@GLIBCXX_3.4.21 5
+ _ZNSt12domain_errorC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
  _ZNSt12domain_errorC2ERKSs@GLIBCXX_3.4 4.1.1
  _ZNSt12domain_errorD0Ev@GLIBCXX_3.4 4.1.1
  _ZNSt12domain_errorD1Ev@GLIBCXX_3.4 4.1.1
@@ -1060,12 +1447,20 @@
  _ZNSt12future_errorD0Ev@GLIBCXX_3.4.14 4.5
  _ZNSt12future_errorD1Ev@GLIBCXX_3.4.14 4.5
  _ZNSt12future_errorD2Ev@GLIBCXX_3.4.14 4.5
+ _ZNSt12length_errorC1EPKc@GLIBCXX_3.4.21 5
+ _ZNSt12length_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
  _ZNSt12length_errorC1ERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt12length_errorC2EPKc@GLIBCXX_3.4.21 5
+ _ZNSt12length_errorC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
  _ZNSt12length_errorC2ERKSs@GLIBCXX_3.4 4.1.1
  _ZNSt12length_errorD0Ev@GLIBCXX_3.4 4.1.1
  _ZNSt12length_errorD1Ev@GLIBCXX_3.4 4.1.1
  _ZNSt12length_errorD2Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt12out_of_rangeC1EPKc@GLIBCXX_3.4.21 5
+ _ZNSt12out_of_rangeC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
  _ZNSt12out_of_rangeC1ERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt12out_of_rangeC2EPKc@GLIBCXX_3.4.21 5
+ _ZNSt12out_of_rangeC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
  _ZNSt12out_of_rangeC2ERKSs@GLIBCXX_3.4 4.1.1
  _ZNSt12out_of_rangeD0Ev@GLIBCXX_3.4 4.1.1
  _ZNSt12out_of_rangeD1Ev@GLIBCXX_3.4 4.1.1
@@ -1120,6 +1515,7 @@
  _ZNSt13__future_base12_Result_baseD0Ev@GLIBCXX_3.4.15 4.6
  _ZNSt13__future_base12_Result_baseD1Ev@GLIBCXX_3.4.15 4.6
  _ZNSt13__future_base12_Result_baseD2Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt13__future_base13_State_baseV211_Make_ready6_M_setEv@GLIBCXX_3.4.21 5
  _ZNSt13__future_base19_Async_state_commonD0Ev@GLIBCXX_3.4.17 4.7.0~rc1
  _ZNSt13__future_base19_Async_state_commonD1Ev@GLIBCXX_3.4.17 4.7.0~rc1
  _ZNSt13__future_base19_Async_state_commonD2Ev@GLIBCXX_3.4.17 4.7.0~rc1
@@ -1133,7 +1529,9 @@
  _ZNSt13basic_filebufIcSt11char_traitsIcEE26_M_destroy_internal_bufferEv@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_filebufIcSt11char_traitsIcEE27_M_allocate_internal_bufferEv@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE4openERKNSt7__cxx1112basic_stringIcS1_SaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5
  _ZNSt13basic_filebufIcSt11char_traitsIcEE4openERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
+ _ZNSt13basic_filebufIcSt11char_traitsIcEE4swapERS2_@GLIBCXX_3.4.21 5
  _ZNSt13basic_filebufIcSt11char_traitsIcEE4syncEv@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_filebufIcSt11char_traitsIcEE5imbueERKSt6locale@GLIBCXX_3.4 4.1.1
@@ -1142,11 +1540,14 @@
  _ZNSt13basic_filebufIcSt11char_traitsIcEE9pbackfailEi@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_filebufIcSt11char_traitsIcEE9showmanycEv@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_filebufIcSt11char_traitsIcEE9underflowEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEEC1EOS2_@GLIBCXX_3.4.21 5
  _ZNSt13basic_filebufIcSt11char_traitsIcEEC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEEC2EOS2_@GLIBCXX_3.4.21 5
  _ZNSt13basic_filebufIcSt11char_traitsIcEEC2Ev@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_filebufIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_filebufIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_filebufIcSt11char_traitsIcEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIcSt11char_traitsIcEEaSEOS2_@GLIBCXX_3.4.21 5
  _ZNSt13basic_filebufIwSt11char_traitsIwEE14_M_get_ext_posER11__mbstate_t@GLIBCXX_3.4.15 4.6
  _ZNSt13basic_filebufIwSt11char_traitsIwEE15_M_create_pbackEv@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_filebufIwSt11char_traitsIwEE16_M_destroy_pbackEv@GLIBCXX_3.4 4.1.1
@@ -1154,7 +1555,9 @@
  _ZNSt13basic_filebufIwSt11char_traitsIwEE26_M_destroy_internal_bufferEv@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_filebufIwSt11char_traitsIwEE27_M_allocate_internal_bufferEv@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_filebufIwSt11char_traitsIwEE4openEPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE4openERKNSt7__cxx1112basic_stringIcS0_IcESaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5
  _ZNSt13basic_filebufIwSt11char_traitsIwEE4openERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
+ _ZNSt13basic_filebufIwSt11char_traitsIwEE4swapERS2_@GLIBCXX_3.4.21 5
  _ZNSt13basic_filebufIwSt11char_traitsIwEE4syncEv@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_filebufIwSt11char_traitsIwEE5closeEv@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_filebufIwSt11char_traitsIwEE5imbueERKSt6locale@GLIBCXX_3.4 4.1.1
@@ -1163,37 +1566,52 @@
  _ZNSt13basic_filebufIwSt11char_traitsIwEE9pbackfailEj@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_filebufIwSt11char_traitsIwEE9showmanycEv@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_filebufIwSt11char_traitsIwEE9underflowEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEEC1EOS2_@GLIBCXX_3.4.21 5
  _ZNSt13basic_filebufIwSt11char_traitsIwEEC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEEC2EOS2_@GLIBCXX_3.4.21 5
  _ZNSt13basic_filebufIwSt11char_traitsIwEEC2Ev@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_filebufIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_filebufIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_filebufIwSt11char_traitsIwEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_filebufIwSt11char_traitsIwEEaSEOS2_@GLIBCXX_3.4.21 5
  _ZNSt13basic_fstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_fstreamIcSt11char_traitsIcEE4openERKNSt7__cxx1112basic_stringIcS1_SaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5
  _ZNSt13basic_fstreamIcSt11char_traitsIcEE4openERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
+ _ZNSt13basic_fstreamIcSt11char_traitsIcEE4swapERS2_@GLIBCXX_3.4.21 5
  _ZNSt13basic_fstreamIcSt11char_traitsIcEE5closeEv@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_fstreamIcSt11char_traitsIcEE7is_openEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_fstreamIcSt11char_traitsIcEEC1EOS2_@GLIBCXX_3.4.21 5
  _ZNSt13basic_fstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_fstreamIcSt11char_traitsIcEEC1ERKNSt7__cxx1112basic_stringIcS1_SaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5
  _ZNSt13basic_fstreamIcSt11char_traitsIcEEC1ERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
  _ZNSt13basic_fstreamIcSt11char_traitsIcEEC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_fstreamIcSt11char_traitsIcEEC2EOS2_@GLIBCXX_3.4.21 5
  _ZNSt13basic_fstreamIcSt11char_traitsIcEEC2EPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_fstreamIcSt11char_traitsIcEEC2ERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
  _ZNSt13basic_fstreamIcSt11char_traitsIcEEC2Ev@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_fstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_fstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_fstreamIcSt11char_traitsIcEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_fstreamIcSt11char_traitsIcEEaSEOS2_@GLIBCXX_3.4.21 5
  _ZNSt13basic_fstreamIwSt11char_traitsIwEE4openEPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_fstreamIwSt11char_traitsIwEE4openERKNSt7__cxx1112basic_stringIcS0_IcESaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5
  _ZNSt13basic_fstreamIwSt11char_traitsIwEE4openERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
+ _ZNSt13basic_fstreamIwSt11char_traitsIwEE4swapERS2_@GLIBCXX_3.4.21 5
  _ZNSt13basic_fstreamIwSt11char_traitsIwEE5closeEv@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_fstreamIwSt11char_traitsIwEE7is_openEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_fstreamIwSt11char_traitsIwEEC1EOS2_@GLIBCXX_3.4.21 5
  _ZNSt13basic_fstreamIwSt11char_traitsIwEEC1EPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_fstreamIwSt11char_traitsIwEEC1ERKNSt7__cxx1112basic_stringIcS0_IcESaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5
  _ZNSt13basic_fstreamIwSt11char_traitsIwEEC1ERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
  _ZNSt13basic_fstreamIwSt11char_traitsIwEEC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_fstreamIwSt11char_traitsIwEEC2EOS2_@GLIBCXX_3.4.21 5
  _ZNSt13basic_fstreamIwSt11char_traitsIwEEC2EPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_fstreamIwSt11char_traitsIwEEC2ERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
  _ZNSt13basic_fstreamIwSt11char_traitsIwEEC2Ev@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_fstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_fstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_fstreamIwSt11char_traitsIwEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_fstreamIwSt11char_traitsIwEEaSEOS2_@GLIBCXX_3.4.21 5
  _ZNSt13basic_istreamIwSt11char_traitsIwEE10_M_extractIPvEERS2_RT_@GLIBCXX_3.4.9 4.2.1
  _ZNSt13basic_istreamIwSt11char_traitsIwEE10_M_extractIbEERS2_RT_@GLIBCXX_3.4.9 4.2.1
  _ZNSt13basic_istreamIwSt11char_traitsIwEE10_M_extractIdEERS2_RT_@GLIBCXX_3.4.9 4.2.1
@@ -1210,6 +1628,7 @@
  _ZNSt13basic_istreamIwSt11char_traitsIwEE3getERw@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_istreamIwSt11char_traitsIwEE3getEv@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_istreamIwSt11char_traitsIwEE4peekEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE4swapERS2_@GLIBCXX_3.4.21 5
  _ZNSt13basic_istreamIwSt11char_traitsIwEE4syncEv@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_istreamIwSt11char_traitsIwEE5seekgESt4fposI11__mbstate_tE@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_istreamIwSt11char_traitsIwEE5tellgEv@GLIBCXX_3.4 4.1.1
@@ -1219,13 +1638,16 @@
  _ZNSt13basic_istreamIwSt11char_traitsIwEE6sentryC1ERS2_b@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_istreamIwSt11char_traitsIwEE6sentryC2ERS2_b@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_istreamIwSt11char_traitsIwEE7putbackEw@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEEC1EOS2_@GLIBCXX_3.4.21 5
  _ZNSt13basic_istreamIwSt11char_traitsIwEEC1EPSt15basic_streambufIwS1_E@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_istreamIwSt11char_traitsIwEEC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEEC2EOS2_@GLIBCXX_3.4.21 5
  _ZNSt13basic_istreamIwSt11char_traitsIwEEC2EPSt15basic_streambufIwS1_E@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_istreamIwSt11char_traitsIwEEC2Ev@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_istreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_istreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_istreamIwSt11char_traitsIwEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEEaSEOS2_@GLIBCXX_3.4.21 5
  _ZNSt13basic_istreamIwSt11char_traitsIwEErsEPFRS2_S3_E@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_istreamIwSt11char_traitsIwEErsEPFRSt8ios_baseS4_E@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_istreamIwSt11char_traitsIwEErsEPFRSt9basic_iosIwS1_ES5_E@GLIBCXX_3.4 4.1.1
@@ -1244,6 +1666,7 @@
  _ZNSt13basic_istreamIwSt11char_traitsIwEErsERx@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_istreamIwSt11char_traitsIwEErsERy@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE4swapERS2_@GLIBCXX_3.4.21 5
  _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_ostreamIwSt11char_traitsIwEE5seekpESt4fposI11__mbstate_tE@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_ostreamIwSt11char_traitsIwEE5tellpEv@GLIBCXX_3.4 4.1.1
@@ -1259,13 +1682,18 @@
  _ZNSt13basic_ostreamIwSt11char_traitsIwEE9_M_insertImEERS2_T_@GLIBCXX_3.4.9 4.2.1
  _ZNSt13basic_ostreamIwSt11char_traitsIwEE9_M_insertIxEERS2_T_@GLIBCXX_3.4.9 4.2.1
  _ZNSt13basic_ostreamIwSt11char_traitsIwEE9_M_insertIyEERS2_T_@GLIBCXX_3.4.9 4.2.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEEC1EOS2_@GLIBCXX_3.4.21 5
  _ZNSt13basic_ostreamIwSt11char_traitsIwEEC1EPSt15basic_streambufIwS1_E@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEEC1ERSt14basic_iostreamIwS1_E@GLIBCXX_3.4.21 5
  _ZNSt13basic_ostreamIwSt11char_traitsIwEEC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEEC2EOS2_@GLIBCXX_3.4.21 5
  _ZNSt13basic_ostreamIwSt11char_traitsIwEEC2EPSt15basic_streambufIwS1_E@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEEC2ERSt14basic_iostreamIwS1_E@GLIBCXX_3.4.21 5
  _ZNSt13basic_ostreamIwSt11char_traitsIwEEC2Ev@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_ostreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_ostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_ostreamIwSt11char_traitsIwEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEEaSEOS2_@GLIBCXX_3.4.21 5
  _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEPFRS2_S3_E@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEPFRSt8ios_baseS4_E@GLIBCXX_3.4 4.1.1
  _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEPFRSt9basic_iosIwS1_ES5_E@GLIBCXX_3.4 4.1.1
@@ -1782,7 +2210,11 @@
  _ZNSt14numeric_limitsIyE9is_iec559E@GLIBCXX_3.4 4.1.1
  _ZNSt14numeric_limitsIyE9is_moduloE@GLIBCXX_3.4 4.1.1
  _ZNSt14numeric_limitsIyE9is_signedE@GLIBCXX_3.4 4.1.1
+ _ZNSt14overflow_errorC1EPKc@GLIBCXX_3.4.21 5
+ _ZNSt14overflow_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
  _ZNSt14overflow_errorC1ERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt14overflow_errorC2EPKc@GLIBCXX_3.4.21 5
+ _ZNSt14overflow_errorC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
  _ZNSt14overflow_errorC2ERKSs@GLIBCXX_3.4 4.1.1
  _ZNSt14overflow_errorD0Ev@GLIBCXX_3.4 4.1.1
  _ZNSt14overflow_errorD1Ev@GLIBCXX_3.4 4.1.1
@@ -1799,6 +2231,7 @@
  _ZNSt15basic_streambufIcSt11char_traitsIcEE10pubseekposESt4fposI11__mbstate_tESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
  _ZNSt15basic_streambufIcSt11char_traitsIcEE4setgEPcS3_S3_@GLIBCXX_3.4 4.1.1
  _ZNSt15basic_streambufIcSt11char_traitsIcEE4setpEPcS3_@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIcSt11char_traitsIcEE4swapERS2_@GLIBCXX_3.4.21 5
  _ZNSt15basic_streambufIcSt11char_traitsIcEE4syncEv@GLIBCXX_3.4 4.1.1
  _ZNSt15basic_streambufIcSt11char_traitsIcEE5gbumpEi@GLIBCXX_3.4 4.1.1
  _ZNSt15basic_streambufIcSt11char_traitsIcEE5imbueERKSt6locale@GLIBCXX_3.4 4.1.1
@@ -1830,6 +2263,7 @@
  _ZNSt15basic_streambufIwSt11char_traitsIwEE10pubseekposESt4fposI11__mbstate_tESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
  _ZNSt15basic_streambufIwSt11char_traitsIwEE4setgEPwS3_S3_@GLIBCXX_3.4 4.1.1
  _ZNSt15basic_streambufIwSt11char_traitsIwEE4setpEPwS3_@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_streambufIwSt11char_traitsIwEE4swapERS2_@GLIBCXX_3.4.21 5
  _ZNSt15basic_streambufIwSt11char_traitsIwEE4syncEv@GLIBCXX_3.4 4.1.1
  _ZNSt15basic_streambufIwSt11char_traitsIwEE5gbumpEi@GLIBCXX_3.4 4.1.1
  _ZNSt15basic_streambufIwSt11char_traitsIwEE5imbueERKSt6locale@GLIBCXX_3.4 4.1.1
@@ -1910,7 +2344,11 @@
  _ZNSt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED0Ev@GLIBCXX_3.4 4.1.1
  _ZNSt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED1Ev@GLIBCXX_3.4 4.1.1
  _ZNSt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt15underflow_errorC1EPKc@GLIBCXX_3.4.21 5
+ _ZNSt15underflow_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
  _ZNSt15underflow_errorC1ERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt15underflow_errorC2EPKc@GLIBCXX_3.4.21 5
+ _ZNSt15underflow_errorC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
  _ZNSt15underflow_errorC2ERKSs@GLIBCXX_3.4 4.1.1
  _ZNSt15underflow_errorD0Ev@GLIBCXX_3.4 4.1.1
  _ZNSt15underflow_errorD1Ev@GLIBCXX_3.4 4.1.1
@@ -1926,7 +2364,11 @@
  _ZNSt16bad_array_lengthD0Ev@CXXABI_1.3.8 4.9
  _ZNSt16bad_array_lengthD1Ev@CXXABI_1.3.8 4.9
  _ZNSt16bad_array_lengthD2Ev@CXXABI_1.3.8 4.9
+ _ZNSt16invalid_argumentC1EPKc@GLIBCXX_3.4.21 5
+ _ZNSt16invalid_argumentC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
  _ZNSt16invalid_argumentC1ERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt16invalid_argumentC2EPKc@GLIBCXX_3.4.21 5
+ _ZNSt16invalid_argumentC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
  _ZNSt16invalid_argumentC2ERKSs@GLIBCXX_3.4 4.1.1
  _ZNSt16invalid_argumentD0Ev@GLIBCXX_3.4 4.1.1
  _ZNSt16invalid_argumentD1Ev@GLIBCXX_3.4 4.1.1
@@ -1981,21 +2423,29 @@
  _ZNSt18__moneypunct_cacheIwLb1EED1Ev@GLIBCXX_3.4 4.1.1
  _ZNSt18__moneypunct_cacheIwLb1EED2Ev@GLIBCXX_3.4 4.1.1
  _ZNSt18basic_stringstreamIcSt11char_traitsIcESaIcEE3strERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt18basic_stringstreamIcSt11char_traitsIcESaIcEE4swapERS3_@GLIBCXX_3.4.21 5
+ _ZNSt18basic_stringstreamIcSt11char_traitsIcESaIcEEC1EOS3_@GLIBCXX_3.4.21 5
  _ZNSt18basic_stringstreamIcSt11char_traitsIcESaIcEEC1ERKSsSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
  _ZNSt18basic_stringstreamIcSt11char_traitsIcESaIcEEC1ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt18basic_stringstreamIcSt11char_traitsIcESaIcEEC2EOS3_@GLIBCXX_3.4.21 5
  _ZNSt18basic_stringstreamIcSt11char_traitsIcESaIcEEC2ERKSsSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
  _ZNSt18basic_stringstreamIcSt11char_traitsIcESaIcEEC2ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
  _ZNSt18basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
  _ZNSt18basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
  _ZNSt18basic_stringstreamIcSt11char_traitsIcESaIcEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt18basic_stringstreamIcSt11char_traitsIcESaIcEEaSEOS3_@GLIBCXX_3.4.21 5
  _ZNSt18basic_stringstreamIwSt11char_traitsIwESaIwEE3strERKSbIwS1_S2_E@GLIBCXX_3.4 4.1.1
+ _ZNSt18basic_stringstreamIwSt11char_traitsIwESaIwEE4swapERS3_@GLIBCXX_3.4.21 5
+ _ZNSt18basic_stringstreamIwSt11char_traitsIwESaIwEEC1EOS3_@GLIBCXX_3.4.21 5
  _ZNSt18basic_stringstreamIwSt11char_traitsIwESaIwEEC1ERKSbIwS1_S2_ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
  _ZNSt18basic_stringstreamIwSt11char_traitsIwESaIwEEC1ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt18basic_stringstreamIwSt11char_traitsIwESaIwEEC2EOS3_@GLIBCXX_3.4.21 5
  _ZNSt18basic_stringstreamIwSt11char_traitsIwESaIwEEC2ERKSbIwS1_S2_ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
  _ZNSt18basic_stringstreamIwSt11char_traitsIwESaIwEEC2ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
  _ZNSt18basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
  _ZNSt18basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
  _ZNSt18basic_stringstreamIwSt11char_traitsIwESaIwEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt18basic_stringstreamIwSt11char_traitsIwESaIwEEaSEOS3_@GLIBCXX_3.4.21 5
  _ZNSt18condition_variable10notify_allEv@GLIBCXX_3.4.11 4.4.0
  _ZNSt18condition_variable10notify_oneEv@GLIBCXX_3.4.11 4.4.0
  _ZNSt18condition_variable4waitERSt11unique_lockISt5mutexE@GLIBCXX_3.4.11 4.4.0
@@ -2003,42 +2453,76 @@
  _ZNSt18condition_variableC2Ev@GLIBCXX_3.4.11 4.4.0
  _ZNSt18condition_variableD1Ev@GLIBCXX_3.4.11 4.4.0
  _ZNSt18condition_variableD2Ev@GLIBCXX_3.4.11 4.4.0
+ _ZNSt19__codecvt_utf8_baseIDiED0Ev@GLIBCXX_3.4.21 5
+ _ZNSt19__codecvt_utf8_baseIDiED1Ev@GLIBCXX_3.4.21 5
+ _ZNSt19__codecvt_utf8_baseIDiED2Ev@GLIBCXX_3.4.21 5
+ _ZNSt19__codecvt_utf8_baseIDsED0Ev@GLIBCXX_3.4.21 5
+ _ZNSt19__codecvt_utf8_baseIDsED1Ev@GLIBCXX_3.4.21 5
+ _ZNSt19__codecvt_utf8_baseIDsED2Ev@GLIBCXX_3.4.21 5
+ _ZNSt19__codecvt_utf8_baseIwED0Ev@GLIBCXX_3.4.21 5
+ _ZNSt19__codecvt_utf8_baseIwED1Ev@GLIBCXX_3.4.21 5
+ _ZNSt19__codecvt_utf8_baseIwED2Ev@GLIBCXX_3.4.21 5
  _ZNSt19basic_istringstreamIcSt11char_traitsIcESaIcEE3strERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_istringstreamIcSt11char_traitsIcESaIcEE4swapERS3_@GLIBCXX_3.4.21 5
+ _ZNSt19basic_istringstreamIcSt11char_traitsIcESaIcEEC1EOS3_@GLIBCXX_3.4.21 5
  _ZNSt19basic_istringstreamIcSt11char_traitsIcESaIcEEC1ERKSsSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
  _ZNSt19basic_istringstreamIcSt11char_traitsIcESaIcEEC1ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_istringstreamIcSt11char_traitsIcESaIcEEC2EOS3_@GLIBCXX_3.4.21 5
  _ZNSt19basic_istringstreamIcSt11char_traitsIcESaIcEEC2ERKSsSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
  _ZNSt19basic_istringstreamIcSt11char_traitsIcESaIcEEC2ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
  _ZNSt19basic_istringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
  _ZNSt19basic_istringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
  _ZNSt19basic_istringstreamIcSt11char_traitsIcESaIcEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_istringstreamIcSt11char_traitsIcESaIcEEaSEOS3_@GLIBCXX_3.4.21 5
  _ZNSt19basic_istringstreamIwSt11char_traitsIwESaIwEE3strERKSbIwS1_S2_E@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_istringstreamIwSt11char_traitsIwESaIwEE4swapERS3_@GLIBCXX_3.4.21 5
+ _ZNSt19basic_istringstreamIwSt11char_traitsIwESaIwEEC1EOS3_@GLIBCXX_3.4.21 5
  _ZNSt19basic_istringstreamIwSt11char_traitsIwESaIwEEC1ERKSbIwS1_S2_ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
  _ZNSt19basic_istringstreamIwSt11char_traitsIwESaIwEEC1ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_istringstreamIwSt11char_traitsIwESaIwEEC2EOS3_@GLIBCXX_3.4.21 5
  _ZNSt19basic_istringstreamIwSt11char_traitsIwESaIwEEC2ERKSbIwS1_S2_ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
  _ZNSt19basic_istringstreamIwSt11char_traitsIwESaIwEEC2ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
  _ZNSt19basic_istringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
  _ZNSt19basic_istringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
  _ZNSt19basic_istringstreamIwSt11char_traitsIwESaIwEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_istringstreamIwSt11char_traitsIwESaIwEEaSEOS3_@GLIBCXX_3.4.21 5
  _ZNSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE3strERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE4swapERS3_@GLIBCXX_3.4.21 5
+ _ZNSt19basic_ostringstreamIcSt11char_traitsIcESaIcEEC1EOS3_@GLIBCXX_3.4.21 5
  _ZNSt19basic_ostringstreamIcSt11char_traitsIcESaIcEEC1ERKSsSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
  _ZNSt19basic_ostringstreamIcSt11char_traitsIcESaIcEEC1ESt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt19basic_ostringstreamIcSt11char_traitsIcESaIcEEC2EOS3_@GLIBCXX_3.4.21 5
  _ZNSt19basic_ostringstreamIcSt11char_traitsIcESaIcEEC2ERKSsSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
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@@ -2138,9 +2637,430 @@
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  _ZNSt8ios_base7failureC2ERKSs@GLIBCXX_3.4 4.1.1
  _ZNSt8ios_base7failureD0Ev@GLIBCXX_3.4 4.1.1
@@ -2289,11 +3220,15 @@
  _ZNSt9basic_iosIcSt11char_traitsIcEE3tieEPSo@GLIBCXX_3.4 4.1.1
  _ZNSt9basic_iosIcSt11char_traitsIcEE4fillEc@GLIBCXX_3.4 4.1.1
  _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIcSt11char_traitsIcEE4moveEOS2_@GLIBCXX_3.4.21 5
+ _ZNSt9basic_iosIcSt11char_traitsIcEE4moveERS2_@GLIBCXX_3.4.21 5
+ _ZNSt9basic_iosIcSt11char_traitsIcEE4swapERS2_@GLIBCXX_3.4.21 5
  _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
  _ZNSt9basic_iosIcSt11char_traitsIcEE5imbueERKSt6locale@GLIBCXX_3.4 4.1.1
  _ZNSt9basic_iosIcSt11char_traitsIcEE5rdbufEPSt15basic_streambufIcS1_E@GLIBCXX_3.4 4.1.1
  _ZNSt9basic_iosIcSt11char_traitsIcEE7copyfmtERKS2_@GLIBCXX_3.4 4.1.1
  _ZNSt9basic_iosIcSt11char_traitsIcEE8setstateESt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIcSt11char_traitsIcEE9set_rdbufEPSt15basic_streambufIcS1_E@GLIBCXX_3.4.21 5
  _ZNSt9basic_iosIcSt11char_traitsIcEEC1EPSt15basic_streambufIcS1_E@GLIBCXX_3.4 4.1.1
  _ZNSt9basic_iosIcSt11char_traitsIcEEC1Ev@GLIBCXX_3.4 4.1.1
  _ZNSt9basic_iosIcSt11char_traitsIcEEC2EPSt15basic_streambufIcS1_E@GLIBCXX_3.4 4.1.1
@@ -2307,11 +3242,15 @@
  _ZNSt9basic_iosIwSt11char_traitsIwEE3tieEPSt13basic_ostreamIwS1_E@GLIBCXX_3.4 4.1.1
  _ZNSt9basic_iosIwSt11char_traitsIwEE4fillEw@GLIBCXX_3.4 4.1.1
  _ZNSt9basic_iosIwSt11char_traitsIwEE4initEPSt15basic_streambufIwS1_E@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIwSt11char_traitsIwEE4moveEOS2_@GLIBCXX_3.4.21 5
+ _ZNSt9basic_iosIwSt11char_traitsIwEE4moveERS2_@GLIBCXX_3.4.21 5
+ _ZNSt9basic_iosIwSt11char_traitsIwEE4swapERS2_@GLIBCXX_3.4.21 5
  _ZNSt9basic_iosIwSt11char_traitsIwEE5clearESt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
  _ZNSt9basic_iosIwSt11char_traitsIwEE5imbueERKSt6locale@GLIBCXX_3.4 4.1.1
  _ZNSt9basic_iosIwSt11char_traitsIwEE5rdbufEPSt15basic_streambufIwS1_E@GLIBCXX_3.4 4.1.1
  _ZNSt9basic_iosIwSt11char_traitsIwEE7copyfmtERKS2_@GLIBCXX_3.4 4.1.1
  _ZNSt9basic_iosIwSt11char_traitsIwEE8setstateESt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNSt9basic_iosIwSt11char_traitsIwEE9set_rdbufEPSt15basic_streambufIwS1_E@GLIBCXX_3.4.21 5
  _ZNSt9basic_iosIwSt11char_traitsIwEEC1EPSt15basic_streambufIwS1_E@GLIBCXX_3.4 4.1.1
  _ZNSt9basic_iosIwSt11char_traitsIwEEC1Ev@GLIBCXX_3.4 4.1.1
  _ZNSt9basic_iosIwSt11char_traitsIwEEC2EPSt15basic_streambufIwS1_E@GLIBCXX_3.4 4.1.1
@@ -2370,9 +3309,55 @@
  _ZSt15get_new_handlerv@GLIBCXX_3.4.20 4.9
  _ZSt15set_new_handlerPFvvE@GLIBCXX_3.4 4.1.1
  _ZSt15system_categoryv@GLIBCXX_3.4.11 4.4.0
+ _ZNSt13random_device14_M_init_pretr1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
+ _ZNSt13random_device7_M_initERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
+ _ZNSt13runtime_errorC1EPKc@GLIBCXX_3.4.21 5
+ _ZNSt13runtime_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
+ _ZNSt13runtime_errorC1ERKS_@GLIBCXX_3.4.21 5
+ _ZNSt13runtime_errorC2EPKc@GLIBCXX_3.4.21 5
+ _ZNSt13runtime_errorC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
+ _ZNSt13runtime_errorC2ERKS_@GLIBCXX_3.4.21 5
+ _ZNSt13runtime_erroraSERKS_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openERKNSt7__cxx1112basic_stringIcS1_SaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEE4swapERS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EOS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1ERKNSt7__cxx1112basic_stringIcS1_SaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC2EOS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEEaSEOS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEE4openERKNSt7__cxx1112basic_stringIcS0_IcESaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEE4swapERS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEEC1EOS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEEC1ERKNSt7__cxx1112basic_stringIcS0_IcESaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEEC2EOS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEEaSEOS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_iostreamIwSt11char_traitsIwEE4swapERS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_iostreamIwSt11char_traitsIwEEC1EOS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_iostreamIwSt11char_traitsIwEEC2EOS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_iostreamIwSt11char_traitsIwEEaSEOS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openERKNSt7__cxx1112basic_stringIcS1_SaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ofstreamIcSt11char_traitsIcEE4swapERS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EOS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1ERKNSt7__cxx1112basic_stringIcS1_SaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC2EOS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ofstreamIcSt11char_traitsIcEEaSEOS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ofstreamIwSt11char_traitsIwEE4openERKNSt7__cxx1112basic_stringIcS0_IcESaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ofstreamIwSt11char_traitsIwEE4swapERS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ofstreamIwSt11char_traitsIwEEC1EOS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ofstreamIwSt11char_traitsIwEEC1ERKNSt7__cxx1112basic_stringIcS0_IcESaIcEEESt13_Ios_Openmode@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ofstreamIwSt11char_traitsIwEEC2EOS2_@GLIBCXX_3.4.21 5
+ _ZNSt14basic_ofstreamIwSt11char_traitsIwEEaSEOS2_@GLIBCXX_3.4.21 5
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEE4swapERS3_@GLIBCXX_3.4.21 5
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEEC1EOS3_@GLIBCXX_3.4.21 5
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEEC2EOS3_@GLIBCXX_3.4.21 5
+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEEaSEOS3_@GLIBCXX_3.4.21 5
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE4swapERS3_@GLIBCXX_3.4.21 5
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEEC1EOS3_@GLIBCXX_3.4.21 5
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEEC2EOS3_@GLIBCXX_3.4.21 5
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEEaSEOS3_@GLIBCXX_3.4.21 5
  _ZSt16__throw_bad_castv@GLIBCXX_3.4 4.1.1
  _ZSt16generic_categoryv@GLIBCXX_3.4.11 4.4.0
  _ZSt17__throw_bad_allocv@GLIBCXX_3.4 4.1.1
+ _ZSt17iostream_categoryv@GLIBCXX_3.4.21 5
  _ZSt18_Rb_tree_decrementPKSt18_Rb_tree_node_base@GLIBCXX_3.4 4.1.1
  _ZSt18_Rb_tree_decrementPSt18_Rb_tree_node_base@GLIBCXX_3.4 4.1.1
  _ZSt18_Rb_tree_incrementPKSt18_Rb_tree_node_base@GLIBCXX_3.4 4.1.1
@@ -2398,6 +3383,7 @@
  _ZSt24__throw_invalid_argumentPKc@GLIBCXX_3.4 4.1.1
  _ZSt24__throw_out_of_range_fmtPKcz@GLIBCXX_3.4.20 4.9
  _ZSt25__throw_bad_function_callv@GLIBCXX_3.4.14 4.5
+ _ZSt25notify_all_at_thread_exitRSt18condition_variableSt11unique_lockISt5mutexE@GLIBCXX_3.4.21 5
  _ZSt28_Rb_tree_rebalance_for_erasePSt18_Rb_tree_node_baseRS_@GLIBCXX_3.4 4.1.1
  _ZSt29_Rb_tree_insert_and_rebalancebPSt18_Rb_tree_node_baseS0_RS_@GLIBCXX_3.4 4.1.1
  _ZSt2wsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_@GLIBCXX_3.4 4.1.1
@@ -2416,11 +3402,29 @@
  _ZSt5wcerr@GLIBCXX_3.4 4.1.1
  _ZSt5wclog@GLIBCXX_3.4 4.1.1
  _ZSt5wcout@GLIBCXX_3.4 4.1.1
+ _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE@GLIBCXX_3.4.21 5
+ _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_@GLIBCXX_3.4.21 5
  _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RSbIS4_S5_T1_E@GLIBCXX_3.4 4.1.1
  _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RSbIS4_S5_T1_ES4_@GLIBCXX_3.4 4.1.1
+ _ZSt7getlineIwSt11char_traitsIwESaIwEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE@GLIBCXX_3.4.21 5
+ _ZSt7getlineIwSt11char_traitsIwESaIwEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_@GLIBCXX_3.4.21 5
  _ZSt7getlineIwSt11char_traitsIwESaIwEERSt13basic_istreamIT_T0_ES7_RSbIS4_S5_T1_E@GLIBCXX_3.4 4.1.1
  _ZSt7getlineIwSt11char_traitsIwESaIwEERSt13basic_istreamIT_T0_ES7_RSbIS4_S5_T1_ES4_@GLIBCXX_3.4 4.1.1
  _ZSt7nothrow@GLIBCXX_3.4 4.1.1
+ _ZSt9has_facetINSt7__cxx1110moneypunctIcLb0EEEEbRKSt6locale@GLIBCXX_3.4.21 5
+ _ZSt9has_facetINSt7__cxx1110moneypunctIwLb0EEEEbRKSt6locale@GLIBCXX_3.4.21 5
+ _ZSt9has_facetINSt7__cxx117collateIcEEEbRKSt6locale@GLIBCXX_3.4.21 5
+ _ZSt9has_facetINSt7__cxx117collateIwEEEbRKSt6locale@GLIBCXX_3.4.21 5
+ _ZSt9has_facetINSt7__cxx118messagesIcEEEbRKSt6locale@GLIBCXX_3.4.21 5
+ _ZSt9has_facetINSt7__cxx118messagesIwEEEbRKSt6locale@GLIBCXX_3.4.21 5
+ _ZSt9has_facetINSt7__cxx118numpunctIcEEEbRKSt6locale@GLIBCXX_3.4.21 5
+ _ZSt9has_facetINSt7__cxx118numpunctIwEEEbRKSt6locale@GLIBCXX_3.4.21 5
+ _ZSt9has_facetINSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEEEbRKSt6locale@GLIBCXX_3.4.21 5
+ _ZSt9has_facetINSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEEEbRKSt6locale@GLIBCXX_3.4.21 5
+ _ZSt9has_facetINSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEEEbRKSt6locale@GLIBCXX_3.4.21 5
+ _ZSt9has_facetINSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEEEbRKSt6locale@GLIBCXX_3.4.21 5
+ _ZSt9has_facetINSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEEEbRKSt6locale@GLIBCXX_3.4.21 5
+ _ZSt9has_facetINSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEEEbRKSt6locale@GLIBCXX_3.4.21 5
  _ZSt9has_facetISt10moneypunctIcLb0EEEbRKSt6locale@GLIBCXX_3.4 4.1.1
  _ZSt9has_facetISt10moneypunctIwLb0EEEbRKSt6locale@GLIBCXX_3.4 4.1.1
  _ZSt9has_facetISt11__timepunctIcEEbRKSt6locale@GLIBCXX_3.4 4.1.1
@@ -2448,6 +3452,22 @@
  _ZSt9has_facetISt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEEbRKSt6locale@GLIBCXX_3.4 4.1.1
  _ZSt9has_facetISt9money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEEbRKSt6locale@GLIBCXX_3.4 4.1.1
  _ZSt9terminatev@GLIBCXX_3.4 4.1.1
+ _ZSt9use_facetINSt7__cxx1110moneypunctIcLb0EEEERKT_RKSt6locale@GLIBCXX_3.4.21 5
+ _ZSt9use_facetINSt7__cxx1110moneypunctIcLb1EEEERKT_RKSt6locale@GLIBCXX_3.4.21 5
+ _ZSt9use_facetINSt7__cxx1110moneypunctIwLb0EEEERKT_RKSt6locale@GLIBCXX_3.4.21 5
+ _ZSt9use_facetINSt7__cxx1110moneypunctIwLb1EEEERKT_RKSt6locale@GLIBCXX_3.4.21 5
+ _ZSt9use_facetINSt7__cxx117collateIcEEERKT_RKSt6locale@GLIBCXX_3.4.21 5
+ _ZSt9use_facetINSt7__cxx117collateIwEEERKT_RKSt6locale@GLIBCXX_3.4.21 5
+ _ZSt9use_facetINSt7__cxx118messagesIcEEERKT_RKSt6locale@GLIBCXX_3.4.21 5
+ _ZSt9use_facetINSt7__cxx118messagesIwEEERKT_RKSt6locale@GLIBCXX_3.4.21 5
+ _ZSt9use_facetINSt7__cxx118numpunctIcEEERKT_RKSt6locale@GLIBCXX_3.4.21 5
+ _ZSt9use_facetINSt7__cxx118numpunctIwEEERKT_RKSt6locale@GLIBCXX_3.4.21 5
+ _ZSt9use_facetINSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEEERKT_RKSt6locale@GLIBCXX_3.4.21 5
+ _ZSt9use_facetINSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEEERKT_RKSt6locale@GLIBCXX_3.4.21 5
+ _ZSt9use_facetINSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEEERKT_RKSt6locale@GLIBCXX_3.4.21 5
+ _ZSt9use_facetINSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEEERKT_RKSt6locale@GLIBCXX_3.4.21 5
+ _ZSt9use_facetINSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEEERKT_RKSt6locale@GLIBCXX_3.4.21 5
+ _ZSt9use_facetINSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEEERKT_RKSt6locale@GLIBCXX_3.4.21 5
  _ZSt9use_facetISt10moneypunctIcLb0EEERKT_RKSt6locale@GLIBCXX_3.4 4.1.1
  _ZSt9use_facetISt10moneypunctIcLb1EEERKT_RKSt6locale@GLIBCXX_3.4 4.1.1
  _ZSt9use_facetISt10moneypunctIwLb0EEERKT_RKSt6locale@GLIBCXX_3.4 4.1.1
@@ -2488,6 +3508,7 @@
  _ZStlsIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_St5_Setw@GLIBCXX_3.4 4.1.1
  _ZStlsIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_St8_Setbase@GLIBCXX_3.4 4.1.1
  _ZStlsIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_St8_SetfillIS3_E@GLIBCXX_3.4 4.1.1
+ _ZStlsIcSt11char_traitsIcESaIcEERSt13basic_ostreamIT_T0_ES7_RKNSt7__cxx1112basic_stringIS4_S5_T1_EE@GLIBCXX_3.4.21 5
  _ZStlsIcSt11char_traitsIcESaIcEERSt13basic_ostreamIT_T0_ES7_RKSbIS4_S5_T1_E@GLIBCXX_3.4 4.1.1
  _ZStlsIdcSt11char_traitsIcEERSt13basic_ostreamIT0_T1_ES6_RKSt7complexIT_E@GLIBCXX_3.4 4.1.1
  _ZStlsIdwSt11char_traitsIwEERSt13basic_ostreamIT0_T1_ES6_RKSt7complexIT_E@GLIBCXX_3.4 4.1.1
@@ -2505,6 +3526,7 @@
  _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_St8_Setbase@GLIBCXX_3.4 4.1.1
  _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_St8_SetfillIS3_E@GLIBCXX_3.4 4.1.1
  _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_c@GLIBCXX_3.4 4.1.1
+ _ZStlsIwSt11char_traitsIwESaIwEERSt13basic_ostreamIT_T0_ES7_RKNSt7__cxx1112basic_stringIS4_S5_T1_EE@GLIBCXX_3.4.21 5
  _ZStlsIwSt11char_traitsIwESaIwEERSt13basic_ostreamIT_T0_ES7_RKSbIS4_S5_T1_E@GLIBCXX_3.4 4.1.1
  _ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_EPKS3_RKS6_@GLIBCXX_3.4 4.1.1
  _ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_ERKS6_S8_@GLIBCXX_3.4 4.1.1
@@ -2524,6 +3546,7 @@
  _ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_St5_Setw@GLIBCXX_3.4 4.1.1
  _ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_St8_Setbase@GLIBCXX_3.4 4.1.1
  _ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_St8_SetfillIS3_E@GLIBCXX_3.4 4.1.1
+ _ZStrsIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE@GLIBCXX_3.4.21 5
  _ZStrsIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RSbIS4_S5_T1_E@GLIBCXX_3.4 4.1.1
  _ZStrsIdcSt11char_traitsIcEERSt13basic_istreamIT0_T1_ES6_RSt7complexIT_E@GLIBCXX_3.4 4.1.1
  _ZStrsIdwSt11char_traitsIwEERSt13basic_istreamIT0_T1_ES6_RSt7complexIT_E@GLIBCXX_3.4 4.1.1
@@ -2539,6 +3562,7 @@
  _ZStrsIwSt11char_traitsIwEERSt13basic_istreamIT_T0_ES6_St5_Setw@GLIBCXX_3.4 4.1.1
  _ZStrsIwSt11char_traitsIwEERSt13basic_istreamIT_T0_ES6_St8_Setbase@GLIBCXX_3.4 4.1.1
  _ZStrsIwSt11char_traitsIwEERSt13basic_istreamIT_T0_ES6_St8_SetfillIS3_E@GLIBCXX_3.4 4.1.1
+ _ZStrsIwSt11char_traitsIwESaIwEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE@GLIBCXX_3.4.21 5
  _ZStrsIwSt11char_traitsIwESaIwEERSt13basic_istreamIT_T0_ES7_RSbIS4_S5_T1_E@GLIBCXX_3.4 4.1.1
  _ZTIDd@CXXABI_1.3.4 4.5
  _ZTIDe@CXXABI_1.3.4 4.5
@@ -2565,7 +3589,45 @@
  _ZTINSt13__future_base11_State_baseE@GLIBCXX_3.4.15 4.6
  _ZTINSt13__future_base12_Result_baseE@GLIBCXX_3.4.15 4.6
  _ZTINSt13__future_base19_Async_state_commonE@GLIBCXX_3.4.17 4.7.0~rc1
+ _ZTINSt3_V214error_categoryE@GLIBCXX_3.4.21 5
  _ZTINSt6locale5facetE@GLIBCXX_3.4 4.1.1
+ _ZTINSt7__cxx1110moneypunctIcLb0EEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx1110moneypunctIcLb1EEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx1110moneypunctIwLb0EEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx1110moneypunctIwLb1EEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx1114collate_bynameIcEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx1114collate_bynameIwEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx1115messages_bynameIcEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx1115messages_bynameIwEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx1115numpunct_bynameIcEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx1115numpunct_bynameIwEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx1115time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx1115time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx1117moneypunct_bynameIcLb0EEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx1117moneypunct_bynameIcLb1EEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx1117moneypunct_bynameIwLb0EEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx1117moneypunct_bynameIwLb1EEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx117collateIcEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx117collateIwEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx118messagesIcEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx118messagesIwEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx118numpunctIcEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx118numpunctIwEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5
+ _ZTINSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5
+ _ZTINSt8ios_base7failureB5cxx11E@GLIBCXX_3.4.21 5
  _ZTINSt8ios_base7failureE@GLIBCXX_3.4 4.1.1
  _ZTIPDd@CXXABI_1.3.4 4.5
  _ZTIPDe@CXXABI_1.3.4 4.5
@@ -2585,6 +3647,7 @@
  _ZTIPKd@CXXABI_1.3 4.1.1
  _ZTIPKe@CXXABI_1.3 4.1.1
  _ZTIPKf@CXXABI_1.3 4.1.1
+ _ZTIPKg@CXXABI_FLOAT128 5
  _ZTIPKh@CXXABI_1.3 4.1.1
  _ZTIPKi@CXXABI_1.3 4.1.1
  _ZTIPKj@CXXABI_1.3 4.1.1
@@ -2602,6 +3665,7 @@
  _ZTIPd@CXXABI_1.3 4.1.1
  _ZTIPe@CXXABI_1.3 4.1.1
  _ZTIPf@CXXABI_1.3 4.1.1
+ _ZTIPg@CXXABI_FLOAT128 5
  _ZTIPh@CXXABI_1.3 4.1.1
  _ZTIPi@CXXABI_1.3 4.1.1
  _ZTIPj@CXXABI_1.3 4.1.1
@@ -2685,17 +3749,28 @@
  _ZTISt17moneypunct_bynameIwLb1EE@GLIBCXX_3.4 4.1.1
  _ZTISt18basic_stringstreamIcSt11char_traitsIcESaIcEE@GLIBCXX_3.4 4.1.1
  _ZTISt18basic_stringstreamIwSt11char_traitsIwESaIwEE@GLIBCXX_3.4 4.1.1
+ _ZTISt19__codecvt_utf8_baseIDiE@GLIBCXX_3.4.21 5
+ _ZTISt19__codecvt_utf8_baseIDsE@GLIBCXX_3.4.21 5
+ _ZTISt19__codecvt_utf8_baseIwE@GLIBCXX_3.4.21 5
  _ZTISt19basic_istringstreamIcSt11char_traitsIcESaIcEE@GLIBCXX_3.4 4.1.1
  _ZTISt19basic_istringstreamIwSt11char_traitsIwESaIwEE@GLIBCXX_3.4 4.1.1
  _ZTISt19basic_ostringstreamIcSt11char_traitsIcESaIcEE@GLIBCXX_3.4 4.1.1
  _ZTISt19basic_ostringstreamIwSt11char_traitsIwESaIwEE@GLIBCXX_3.4 4.1.1
+ _ZTISt20__codecvt_utf16_baseIDiE@GLIBCXX_3.4.21 5
+ _ZTISt20__codecvt_utf16_baseIDsE@GLIBCXX_3.4.21 5
+ _ZTISt20__codecvt_utf16_baseIwE@GLIBCXX_3.4.21 5
  _ZTISt20bad_array_new_length@CXXABI_1.3.8 4.9
  _ZTISt21__ctype_abstract_baseIcE@GLIBCXX_3.4 4.1.1
  _ZTISt21__ctype_abstract_baseIwE@GLIBCXX_3.4 4.1.1
  _ZTISt23__codecvt_abstract_baseIcc11__mbstate_tE@GLIBCXX_3.4 4.1.1
  _ZTISt23__codecvt_abstract_baseIwc11__mbstate_tE@GLIBCXX_3.4 4.1.1
+ _ZTISt25__codecvt_utf8_utf16_baseIDiE@GLIBCXX_3.4.21 5
+ _ZTISt25__codecvt_utf8_utf16_baseIDsE@GLIBCXX_3.4.21 5
+ _ZTISt25__codecvt_utf8_utf16_baseIwE@GLIBCXX_3.4.21 5
  _ZTISt5ctypeIcE@GLIBCXX_3.4 4.1.1
  _ZTISt5ctypeIwE@GLIBCXX_3.4 4.1.1
+ _ZTISt7codecvtIDic11__mbstate_tE@GLIBCXX_3.4.21 5
+ _ZTISt7codecvtIDsc11__mbstate_tE@GLIBCXX_3.4.21 5
  _ZTISt7codecvtIcc11__mbstate_tE@GLIBCXX_3.4 4.1.1
  _ZTISt7codecvtIwc11__mbstate_tE@GLIBCXX_3.4 4.1.1
  _ZTISt7collateIcE@GLIBCXX_3.4 4.1.1
@@ -2731,6 +3806,7 @@
  _ZTId@CXXABI_1.3 4.1.1
  _ZTIe@CXXABI_1.3 4.1.1
  _ZTIf@CXXABI_1.3 4.1.1
+ _ZTIg@CXXABI_FLOAT128 5
  _ZTIh@CXXABI_1.3 4.1.1
  _ZTIi@CXXABI_1.3 4.1.1
  _ZTIj@CXXABI_1.3 4.1.1
@@ -2758,6 +3834,43 @@
  _ZTSN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
  _ZTSNSt13__future_base19_Async_state_commonE@GLIBCXX_3.4.17 4.7.0~rc1
  _ZTSNSt6locale5facetE@GLIBCXX_3.4 4.1.1
+ _ZTSNSt7__cxx1110moneypunctIcLb0EEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx1110moneypunctIcLb1EEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx1110moneypunctIwLb0EEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx1110moneypunctIwLb1EEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx1114collate_bynameIcEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx1114collate_bynameIwEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx1115messages_bynameIcEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx1115messages_bynameIwEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx1115numpunct_bynameIcEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx1115numpunct_bynameIwEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx1115time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx1115time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx1117moneypunct_bynameIcLb0EEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx1117moneypunct_bynameIcLb1EEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx1117moneypunct_bynameIwLb0EEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx1117moneypunct_bynameIwLb1EEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx117collateIcEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx117collateIwEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx118messagesIcEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx118messagesIwEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx118numpunctIcEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx118numpunctIwEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5
+ _ZTSNSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5
+ _ZTSNSt8ios_base7failureB5cxx11E@GLIBCXX_3.4.21 5
  _ZTSNSt8ios_base7failureE@GLIBCXX_3.4 4.1.1
  _ZTSPKa@CXXABI_1.3 4.1.1
  _ZTSPKb@CXXABI_1.3 4.1.1
@@ -2765,11 +3878,14 @@
  _ZTSPKd@CXXABI_1.3 4.1.1
  _ZTSPKe@CXXABI_1.3 4.1.1
  _ZTSPKf@CXXABI_1.3 4.1.1
+ _ZTSPKg@CXXABI_FLOAT128 5
  _ZTSPKh@CXXABI_1.3 4.1.1
  _ZTSPKi@CXXABI_1.3 4.1.1
  _ZTSPKj@CXXABI_1.3 4.1.1
  _ZTSPKl@CXXABI_1.3 4.1.1
  _ZTSPKm@CXXABI_1.3 4.1.1
+ _ZTSPKn@CXXABI_1.3.9 5
+ _ZTSPKo@CXXABI_1.3.9 5
  _ZTSPKs@CXXABI_1.3 4.1.1
  _ZTSPKt@CXXABI_1.3 4.1.1
  _ZTSPKv@CXXABI_1.3 4.1.1
@@ -2782,11 +3898,14 @@
  _ZTSPd@CXXABI_1.3 4.1.1
  _ZTSPe@CXXABI_1.3 4.1.1
  _ZTSPf@CXXABI_1.3 4.1.1
+ _ZTSPg@CXXABI_FLOAT128 5
  _ZTSPh@CXXABI_1.3 4.1.1
  _ZTSPi@CXXABI_1.3 4.1.1
  _ZTSPj@CXXABI_1.3 4.1.1
  _ZTSPl@CXXABI_1.3 4.1.1
  _ZTSPm@CXXABI_1.3 4.1.1
+ _ZTSPn@CXXABI_1.3.9 5
+ _ZTSPo@CXXABI_1.3.9 5
  _ZTSPs@CXXABI_1.3 4.1.1
  _ZTSPt@CXXABI_1.3 4.1.1
  _ZTSPv@CXXABI_1.3 4.1.1
@@ -2860,17 +3979,28 @@
  _ZTSSt17moneypunct_bynameIwLb1EE@GLIBCXX_3.4 4.1.1
  _ZTSSt18basic_stringstreamIcSt11char_traitsIcESaIcEE@GLIBCXX_3.4 4.1.1
  _ZTSSt18basic_stringstreamIwSt11char_traitsIwESaIwEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt19__codecvt_utf8_baseIDiE@GLIBCXX_3.4.21 5
+ _ZTSSt19__codecvt_utf8_baseIDsE@GLIBCXX_3.4.21 5
+ _ZTSSt19__codecvt_utf8_baseIwE@GLIBCXX_3.4.21 5
  _ZTSSt19basic_istringstreamIcSt11char_traitsIcESaIcEE@GLIBCXX_3.4 4.1.1
  _ZTSSt19basic_istringstreamIwSt11char_traitsIwESaIwEE@GLIBCXX_3.4 4.1.1
  _ZTSSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE@GLIBCXX_3.4 4.1.1
  _ZTSSt19basic_ostringstreamIwSt11char_traitsIwESaIwEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt20__codecvt_utf16_baseIDiE@GLIBCXX_3.4.21 5
+ _ZTSSt20__codecvt_utf16_baseIDsE@GLIBCXX_3.4.21 5
+ _ZTSSt20__codecvt_utf16_baseIwE@GLIBCXX_3.4.21 5
  _ZTSSt20bad_array_new_length@CXXABI_1.3.8 4.9
  _ZTSSt21__ctype_abstract_baseIcE@GLIBCXX_3.4 4.1.1
  _ZTSSt21__ctype_abstract_baseIwE@GLIBCXX_3.4 4.1.1
  _ZTSSt23__codecvt_abstract_baseIcc11__mbstate_tE@GLIBCXX_3.4 4.1.1
  _ZTSSt23__codecvt_abstract_baseIwc11__mbstate_tE@GLIBCXX_3.4 4.1.1
+ _ZTSSt25__codecvt_utf8_utf16_baseIDiE@GLIBCXX_3.4.21 5
+ _ZTSSt25__codecvt_utf8_utf16_baseIDsE@GLIBCXX_3.4.21 5
+ _ZTSSt25__codecvt_utf8_utf16_baseIwE@GLIBCXX_3.4.21 5
  _ZTSSt5ctypeIcE@GLIBCXX_3.4 4.1.1
  _ZTSSt5ctypeIwE@GLIBCXX_3.4 4.1.1
+ _ZTSSt7codecvtIDic11__mbstate_tE@GLIBCXX_3.4.21 5
+ _ZTSSt7codecvtIDsc11__mbstate_tE@GLIBCXX_3.4.21 5
  _ZTSSt7codecvtIcc11__mbstate_tE@GLIBCXX_3.4 4.1.1
  _ZTSSt7codecvtIwc11__mbstate_tE@GLIBCXX_3.4 4.1.1
  _ZTSSt7collateIcE@GLIBCXX_3.4 4.1.1
@@ -2906,17 +4036,26 @@
  _ZTSd@CXXABI_1.3 4.1.1
  _ZTSe@CXXABI_1.3 4.1.1
  _ZTSf@CXXABI_1.3 4.1.1
+ _ZTSg@CXXABI_FLOAT128 5
  _ZTSh@CXXABI_1.3 4.1.1
  _ZTSi@CXXABI_1.3 4.1.1
  _ZTSj@CXXABI_1.3 4.1.1
  _ZTSl@CXXABI_1.3 4.1.1
  _ZTSm@CXXABI_1.3 4.1.1
+ _ZTSn@CXXABI_1.3.9 5
+ _ZTSo@CXXABI_1.3.9 5
  _ZTSs@CXXABI_1.3 4.1.1
  _ZTSt@CXXABI_1.3 4.1.1
  _ZTSv@CXXABI_1.3 4.1.1
  _ZTSw@CXXABI_1.3 4.1.1
  _ZTSx@CXXABI_1.3 4.1.1
  _ZTSy@CXXABI_1.3 4.1.1
+ _ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
+ _ZTTNSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5
+ _ZTTNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
+ _ZTTNSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5
+ _ZTTNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
+ _ZTTNSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5
  _ZTTSd@GLIBCXX_3.4 4.1.1
  _ZTTSi@GLIBCXX_3.4 4.1.1
  _ZTTSo@GLIBCXX_3.4 4.1.1
@@ -2953,7 +4092,45 @@
  _ZTVNSt13__future_base11_State_baseE@GLIBCXX_3.4.15 4.6
  _ZTVNSt13__future_base12_Result_baseE@GLIBCXX_3.4.15 4.6
  _ZTVNSt13__future_base19_Async_state_commonE@GLIBCXX_3.4.17 4.7.0~rc1
+ _ZTVNSt3_V214error_categoryE@GLIBCXX_3.4.21 5
  _ZTVNSt6locale5facetE@GLIBCXX_3.4 4.1.1
+ _ZTVNSt7__cxx1110moneypunctIcLb0EEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx1110moneypunctIcLb1EEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx1110moneypunctIwLb0EEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx1110moneypunctIwLb1EEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx1114collate_bynameIcEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx1114collate_bynameIwEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx1115messages_bynameIcEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx1115messages_bynameIwEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx1115numpunct_bynameIcEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx1115numpunct_bynameIwEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx1115time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx1115time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx1117moneypunct_bynameIcLb0EEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx1117moneypunct_bynameIcLb1EEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx1117moneypunct_bynameIwLb0EEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx1117moneypunct_bynameIwLb1EEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx117collateIcEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx117collateIwEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx118messagesIcEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx118messagesIwEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx118numpunctIcEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx118numpunctIwEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5
+ _ZTVNSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5
+ _ZTVNSt8ios_base7failureB5cxx11E@GLIBCXX_3.4.21 5
  _ZTVNSt8ios_base7failureE@GLIBCXX_3.4 4.1.1
  _ZTVSd@GLIBCXX_3.4 4.1.1
  _ZTVSi@GLIBCXX_3.4 4.1.1
@@ -3023,17 +4200,28 @@
  _ZTVSt17moneypunct_bynameIwLb1EE@GLIBCXX_3.4 4.1.1
  _ZTVSt18basic_stringstreamIcSt11char_traitsIcESaIcEE@GLIBCXX_3.4 4.1.1
  _ZTVSt18basic_stringstreamIwSt11char_traitsIwESaIwEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt19__codecvt_utf8_baseIDiE@GLIBCXX_3.4.21 5
+ _ZTVSt19__codecvt_utf8_baseIDsE@GLIBCXX_3.4.21 5
+ _ZTVSt19__codecvt_utf8_baseIwE@GLIBCXX_3.4.21 5
  _ZTVSt19basic_istringstreamIcSt11char_traitsIcESaIcEE@GLIBCXX_3.4 4.1.1
  _ZTVSt19basic_istringstreamIwSt11char_traitsIwESaIwEE@GLIBCXX_3.4 4.1.1
  _ZTVSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE@GLIBCXX_3.4 4.1.1
  _ZTVSt19basic_ostringstreamIwSt11char_traitsIwESaIwEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt20__codecvt_utf16_baseIDiE@GLIBCXX_3.4.21 5
+ _ZTVSt20__codecvt_utf16_baseIDsE@GLIBCXX_3.4.21 5
+ _ZTVSt20__codecvt_utf16_baseIwE@GLIBCXX_3.4.21 5
  _ZTVSt20bad_array_new_length@CXXABI_1.3.8 4.9
  _ZTVSt21__ctype_abstract_baseIcE@GLIBCXX_3.4 4.1.1
  _ZTVSt21__ctype_abstract_baseIwE@GLIBCXX_3.4 4.1.1
  _ZTVSt23__codecvt_abstract_baseIcc11__mbstate_tE@GLIBCXX_3.4 4.1.1
  _ZTVSt23__codecvt_abstract_baseIwc11__mbstate_tE@GLIBCXX_3.4 4.1.1
+ _ZTVSt25__codecvt_utf8_utf16_baseIDiE@GLIBCXX_3.4.21 5
+ _ZTVSt25__codecvt_utf8_utf16_baseIDsE@GLIBCXX_3.4.21 5
+ _ZTVSt25__codecvt_utf8_utf16_baseIwE@GLIBCXX_3.4.21 5
  _ZTVSt5ctypeIcE@GLIBCXX_3.4 4.1.1
  _ZTVSt5ctypeIwE@GLIBCXX_3.4 4.1.1
+ _ZTVSt7codecvtIDic11__mbstate_tE@GLIBCXX_3.4.21 5
+ _ZTVSt7codecvtIDsc11__mbstate_tE@GLIBCXX_3.4.21 5
  _ZTVSt7codecvtIcc11__mbstate_tE@GLIBCXX_3.4 4.1.1
  _ZTVSt7codecvtIwc11__mbstate_tE@GLIBCXX_3.4 4.1.1
  _ZTVSt7collateIcE@GLIBCXX_3.4 4.1.1
diff --git a/debian/libtsan0.symbols b/debian/libtsan0.symbols
index 1c52baf..321638a 100644
--- a/debian/libtsan0.symbols
+++ b/debian/libtsan0.symbols
@@ -17,6 +17,7 @@ libtsan.so.0 libtsan0 #MINVER#
  AnnotateIgnoreWritesBegin@Base 4.9
  AnnotateIgnoreWritesEnd@Base 4.9
  AnnotateMemoryIsInitialized@Base 4.9
+ AnnotateMemoryIsUninitialized@Base 5
  AnnotateMutexIsNotPHB@Base 4.9
  AnnotateMutexIsUsedAsCondVar@Base 4.9
  AnnotateNewMemory@Base 4.9
@@ -43,6 +44,7 @@ libtsan.so.0 libtsan0 #MINVER#
  _ZN11__sanitizer11CheckFailedEPKciS1_yy@Base 4.9
  _ZN11__sanitizer7OnPrintEPKc@Base 4.9
  _ZN6__tsan10OnFinalizeEb@Base 4.9
+ _ZN6__tsan12OnInitializeEv@Base 5
  _ZN6__tsan8OnReportEPKNS_10ReportDescEb@Base 4.9
  _ZdaPv@Base 4.9
  _ZdaPvRKSt9nothrow_t@Base 4.9
@@ -98,37 +100,61 @@ libtsan.so.0 libtsan0 #MINVER#
  __cxa_guard_release@Base 4.9
  __fxstat64@Base 4.9
  __fxstat@Base 4.9
+ __getdelim@Base 5
  __interceptor___close@Base 4.9
  __interceptor___cxa_atexit@Base 4.9
  __interceptor___fxstat64@Base 4.9
  __interceptor___fxstat@Base 4.9
+ __interceptor___getdelim@Base 5
+ __interceptor___isoc99_fprintf@Base 5
  __interceptor___isoc99_fscanf@Base 4.9
+ __interceptor___isoc99_printf@Base 5
  __interceptor___isoc99_scanf@Base 4.9
+ __interceptor___isoc99_snprintf@Base 5
+ __interceptor___isoc99_sprintf@Base 5
  __interceptor___isoc99_sscanf@Base 4.9
+ __interceptor___isoc99_vfprintf@Base 5
  __interceptor___isoc99_vfscanf@Base 4.9
+ __interceptor___isoc99_vprintf@Base 5
  __interceptor___isoc99_vscanf@Base 4.9
+ __interceptor___isoc99_vsnprintf@Base 5
+ __interceptor___isoc99_vsprintf@Base 5
  __interceptor___isoc99_vsscanf@Base 4.9
  __interceptor___libc_memalign@Base 4.9
  __interceptor___lxstat64@Base 4.9
  __interceptor___lxstat@Base 4.9
+ __interceptor___overflow@Base 5
  __interceptor___res_iclose@Base 4.9
  __interceptor___sigsetjmp@Base 4.9
+ __interceptor___tls_get_addr@Base 5
+ __interceptor___uflow@Base 5
+ __interceptor___underflow@Base 5
+ __interceptor___woverflow@Base 5
+ __interceptor___wuflow@Base 5
+ __interceptor___wunderflow@Base 5
  __interceptor___xpg_strerror_r@Base 4.9
  __interceptor___xstat64@Base 4.9
  __interceptor___xstat@Base 4.9
  __interceptor__exit@Base 4.9
+ __interceptor__obstack_begin@Base 5
+ __interceptor__obstack_begin_1@Base 5
+ __interceptor__obstack_newchunk@Base 5
  __interceptor__setjmp@Base 4.9
  __interceptor_abort@Base 4.9
  __interceptor_accept4@Base 4.9
  __interceptor_accept@Base 4.9
+ __interceptor_aligned_alloc@Base 5
  __interceptor_asctime@Base 4.9
  __interceptor_asctime_r@Base 4.9
+ __interceptor_asprintf@Base 5
  __interceptor_atexit@Base 4.9
  __interceptor_backtrace@Base 4.9
  __interceptor_backtrace_symbols@Base 4.9
  __interceptor_bind@Base 4.9
  __interceptor_calloc@Base 4.9
  __interceptor_canonicalize_file_name@Base 4.9
+ __interceptor_capget@Base 5
+ __interceptor_capset@Base 5
  __interceptor_cfree@Base 4.9
  __interceptor_clock_getres@Base 4.9
  __interceptor_clock_gettime@Base 4.9
@@ -146,6 +172,8 @@ libtsan.so.0 libtsan0 #MINVER#
  __interceptor_dup2@Base 4.9
  __interceptor_dup3@Base 4.9
  __interceptor_dup@Base 4.9
+ __interceptor_endgrent@Base 5
+ __interceptor_endpwent@Base 5
  __interceptor_epoll_create1@Base 4.9
  __interceptor_epoll_create@Base 4.9
  __interceptor_epoll_ctl@Base 4.9
@@ -159,11 +187,18 @@ libtsan.so.0 libtsan0 #MINVER#
  __interceptor_ether_ntohost@Base 4.9
  __interceptor_eventfd@Base 4.9
  __interceptor_fclose@Base 4.9
+ __interceptor_fdopen@Base 5
  __interceptor_fflush@Base 4.9
+ __interceptor_fgetxattr@Base 5
+ __interceptor_flistxattr@Base 5
+ __interceptor_fmemopen@Base 5
+ __interceptor_fopen64@Base 5
  __interceptor_fopen@Base 4.9
  __interceptor_fork@Base 4.9
+ __interceptor_fprintf@Base 5
  __interceptor_fread@Base 4.9
  __interceptor_free@Base 4.9
+ __interceptor_freopen64@Base 5
  __interceptor_freopen@Base 4.9
  __interceptor_frexp@Base 4.9
  __interceptor_frexpf@Base 4.9
@@ -175,6 +210,7 @@ libtsan.so.0 libtsan0 #MINVER#
  __interceptor_fstatfs@Base 4.9
  __interceptor_fstatvfs64@Base 4.9
  __interceptor_fstatvfs@Base 4.9
+ __interceptor_ftime@Base 5
  __interceptor_fwrite@Base 4.9
  __interceptor_get_current_dir_name@Base 4.9
  __interceptor_getaddrinfo@Base 4.9
@@ -189,17 +225,27 @@ libtsan.so.0 libtsan0 #MINVER#
  __interceptor_gethostbyname_r@Base 4.9
  __interceptor_gethostent@Base 4.9
  __interceptor_gethostent_r@Base 4.9
+ __interceptor_getifaddrs@Base 5
  __interceptor_getitimer@Base 4.9
  __interceptor_getline@Base 4.9
  __interceptor_getmntent@Base 4.9
  __interceptor_getmntent_r@Base 4.9
+ __interceptor_getnameinfo@Base 5
+ __interceptor_getpass@Base 5
  __interceptor_getpeername@Base 4.9
+ __interceptor_getresgid@Base 5
+ __interceptor_getresuid@Base 5
  __interceptor_getsockname@Base 4.9
  __interceptor_getsockopt@Base 4.9
  __interceptor_gettimeofday@Base 4.9
+ __interceptor_getxattr@Base 5
+ __interceptor_glob64@Base 5
+ __interceptor_glob@Base 5
  __interceptor_gmtime@Base 4.9
  __interceptor_gmtime_r@Base 4.9
  __interceptor_iconv@Base 4.9
+ __interceptor_if_indextoname@Base 5
+ __interceptor_if_nametoindex@Base 5
  __interceptor_inet_aton@Base 4.9
  __interceptor_inet_ntop@Base 4.9
  __interceptor_inet_pton@Base 4.9
@@ -214,7 +260,10 @@ libtsan.so.0 libtsan0 #MINVER#
  __interceptor_lgammaf_r@Base 4.9
  __interceptor_lgammal@Base 4.9
  __interceptor_lgammal_r@Base 4.9
+ __interceptor_lgetxattr@Base 5
  __interceptor_listen@Base 4.9
+ __interceptor_listxattr@Base 5
+ __interceptor_llistxattr@Base 5
  __interceptor_localtime@Base 4.9
  __interceptor_localtime_r@Base 4.9
  __interceptor_longjmp@Base 4.9
@@ -233,6 +282,7 @@ libtsan.so.0 libtsan0 #MINVER#
  __interceptor_memmove@Base 4.9
  __interceptor_memrchr@Base 4.9
  __interceptor_memset@Base 4.9
+ __interceptor_mktime@Base 5
  __interceptor_mlock@Base 4.9
  __interceptor_mlockall@Base 4.9
  __interceptor_mmap64@Base 4.9
@@ -247,6 +297,8 @@ libtsan.so.0 libtsan0 #MINVER#
  __interceptor_on_exit@Base 4.9
  __interceptor_open64@Base 4.9
  __interceptor_open@Base 4.9
+ __interceptor_open_memstream@Base 5
+ __interceptor_open_wmemstream@Base 5
  __interceptor_opendir@Base 4.9
  __interceptor_pipe2@Base 4.9
  __interceptor_pipe@Base 4.9
@@ -258,6 +310,7 @@ libtsan.so.0 libtsan0 #MINVER#
  __interceptor_pread@Base 4.9
  __interceptor_preadv64@Base 4.9
  __interceptor_preadv@Base 4.9
+ __interceptor_printf@Base 5
  __interceptor_pthread_attr_getaffinity_np@Base 4.9
  __interceptor_pthread_attr_getdetachstate@Base 4.9
  __interceptor_pthread_attr_getguardsize@Base 4.9
@@ -270,12 +323,15 @@ libtsan.so.0 libtsan0 #MINVER#
  __interceptor_pthread_barrier_destroy@Base 4.9
  __interceptor_pthread_barrier_init@Base 4.9
  __interceptor_pthread_barrier_wait@Base 4.9
+ __interceptor_pthread_barrierattr_getpshared@Base 5
  __interceptor_pthread_cond_broadcast@Base 4.9
  __interceptor_pthread_cond_destroy@Base 4.9
  __interceptor_pthread_cond_init@Base 4.9
  __interceptor_pthread_cond_signal@Base 4.9
  __interceptor_pthread_cond_timedwait@Base 4.9
  __interceptor_pthread_cond_wait@Base 4.9
+ __interceptor_pthread_condattr_getclock@Base 5
+ __interceptor_pthread_condattr_getpshared@Base 5
  __interceptor_pthread_create@Base 4.9
  __interceptor_pthread_detach@Base 4.9
  __interceptor_pthread_getschedparam@Base 4.9
@@ -287,6 +343,12 @@ libtsan.so.0 libtsan0 #MINVER#
  __interceptor_pthread_mutex_timedlock@Base 4.9
  __interceptor_pthread_mutex_trylock@Base 4.9
  __interceptor_pthread_mutex_unlock@Base 4.9
+ __interceptor_pthread_mutexattr_getprioceiling@Base 5
+ __interceptor_pthread_mutexattr_getprotocol@Base 5
+ __interceptor_pthread_mutexattr_getpshared@Base 5
+ __interceptor_pthread_mutexattr_getrobust@Base 5
+ __interceptor_pthread_mutexattr_getrobust_np@Base 5
+ __interceptor_pthread_mutexattr_gettype@Base 5
  __interceptor_pthread_once@Base 4.9
  __interceptor_pthread_rwlock_destroy@Base 4.9
  __interceptor_pthread_rwlock_init@Base 4.9
@@ -297,6 +359,8 @@ libtsan.so.0 libtsan0 #MINVER#
  __interceptor_pthread_rwlock_trywrlock@Base 4.9
  __interceptor_pthread_rwlock_unlock@Base 4.9
  __interceptor_pthread_rwlock_wrlock@Base 4.9
+ __interceptor_pthread_rwlockattr_getkind_np@Base 5
+ __interceptor_pthread_rwlockattr_getpshared@Base 5
  __interceptor_pthread_setname_np@Base 4.9
  __interceptor_pthread_spin_destroy@Base 4.9
  __interceptor_pthread_spin_init@Base 4.9
@@ -311,6 +375,7 @@ libtsan.so.0 libtsan0 #MINVER#
  __interceptor_pwritev64@Base 4.9
  __interceptor_pwritev@Base 4.9
  __interceptor_raise@Base 4.9
+ __interceptor_rand_r@Base 5
  __interceptor_random_r@Base 4.9
  __interceptor_read@Base 4.9
  __interceptor_readdir64@Base 4.9
@@ -339,9 +404,11 @@ libtsan.so.0 libtsan0 #MINVER#
  __interceptor_sem_wait@Base 4.9
  __interceptor_send@Base 4.9
  __interceptor_sendmsg@Base 4.9
+ __interceptor_setgrent@Base 5
  __interceptor_setitimer@Base 4.9
  __interceptor_setjmp@Base 4.9
  __interceptor_setlocale@Base 4.9
+ __interceptor_setpwent@Base 5
  __interceptor_shmctl@Base 4.9
  __interceptor_sigaction@Base 4.9
  __interceptor_sigemptyset@Base 4.9
@@ -360,8 +427,10 @@ libtsan.so.0 libtsan0 #MINVER#
  __interceptor_sincosf@Base 4.9
  __interceptor_sincosl@Base 4.9
  __interceptor_sleep@Base 4.9
+ __interceptor_snprintf@Base 5
  __interceptor_socket@Base 4.9
  __interceptor_socketpair@Base 4.9
+ __interceptor_sprintf@Base 5
  __interceptor_sscanf@Base 4.9
  __interceptor_stat64@Base 4.9
  __interceptor_stat@Base 4.9
@@ -391,14 +460,25 @@ libtsan.so.0 libtsan0 #MINVER#
  __interceptor_tempnam@Base 4.9
  __interceptor_textdomain@Base 4.9
  __interceptor_time@Base 4.9
+ __interceptor_timerfd_gettime@Base 5
+ __interceptor_timerfd_settime@Base 5
  __interceptor_times@Base 4.9
+ __interceptor_tmpfile64@Base 5
+ __interceptor_tmpfile@Base 5
  __interceptor_tmpnam@Base 4.9
  __interceptor_tmpnam_r@Base 4.9
+ __interceptor_tsearch@Base 5
  __interceptor_unlink@Base 4.9
  __interceptor_usleep@Base 4.9
  __interceptor_valloc@Base 4.9
+ __interceptor_vasprintf@Base 5
+ __interceptor_vfork@Base 5
+ __interceptor_vfprintf@Base 5
  __interceptor_vfscanf@Base 4.9
+ __interceptor_vprintf@Base 5
  __interceptor_vscanf@Base 4.9
+ __interceptor_vsnprintf@Base 5
+ __interceptor_vsprintf@Base 5
  __interceptor_vsscanf@Base 4.9
  __interceptor_wait3@Base 4.9
  __interceptor_wait4@Base 4.9
@@ -411,18 +491,71 @@ libtsan.so.0 libtsan0 #MINVER#
  __interceptor_wordexp@Base 4.9
  __interceptor_write@Base 4.9
  __interceptor_writev@Base 4.9
+ __interceptor_xdr_bool@Base 5
+ __interceptor_xdr_bytes@Base 5
+ __interceptor_xdr_char@Base 5
+ __interceptor_xdr_double@Base 5
+ __interceptor_xdr_enum@Base 5
+ __interceptor_xdr_float@Base 5
+ __interceptor_xdr_hyper@Base 5
+ __interceptor_xdr_int16_t@Base 5
+ __interceptor_xdr_int32_t@Base 5
+ __interceptor_xdr_int64_t@Base 5
+ __interceptor_xdr_int8_t@Base 5
+ __interceptor_xdr_int@Base 5
+ __interceptor_xdr_long@Base 5
+ __interceptor_xdr_longlong_t@Base 5
+ __interceptor_xdr_quad_t@Base 5
+ __interceptor_xdr_short@Base 5
+ __interceptor_xdr_string@Base 5
+ __interceptor_xdr_u_char@Base 5
+ __interceptor_xdr_u_hyper@Base 5
+ __interceptor_xdr_u_int@Base 5
+ __interceptor_xdr_u_long@Base 5
+ __interceptor_xdr_u_longlong_t@Base 5
+ __interceptor_xdr_u_quad_t@Base 5
+ __interceptor_xdr_u_short@Base 5
+ __interceptor_xdr_uint16_t@Base 5
+ __interceptor_xdr_uint32_t@Base 5
+ __interceptor_xdr_uint64_t@Base 5
+ __interceptor_xdr_uint8_t@Base 5
+ __interceptor_xdrmem_create@Base 5
+ __interceptor_xdrstdio_create@Base 5
+ __isoc99_fprintf@Base 5
  __isoc99_fscanf@Base 4.9
+ __isoc99_printf@Base 5
  __isoc99_scanf@Base 4.9
+ __isoc99_snprintf@Base 5
+ __isoc99_sprintf@Base 5
  __isoc99_sscanf@Base 4.9
+ __isoc99_vfprintf@Base 5
  __isoc99_vfscanf@Base 4.9
+ __isoc99_vprintf@Base 5
  __isoc99_vscanf@Base 4.9
+ __isoc99_vsnprintf@Base 5
+ __isoc99_vsprintf@Base 5
  __isoc99_vsscanf@Base 4.9
  __libc_memalign@Base 4.9
  __lxstat64@Base 4.9
  __lxstat@Base 4.9
+ __overflow@Base 5
  __res_iclose@Base 4.9
  __sanitizer_cov@Base 4.9
  __sanitizer_cov_dump@Base 4.9
+ __sanitizer_cov_indir_call16@Base 5
+ __sanitizer_cov_init@Base 5
+ __sanitizer_cov_module_init@Base 5
+ __sanitizer_free_hook@Base 5
+ __sanitizer_get_allocated_size@Base 5
+ __sanitizer_get_current_allocated_bytes@Base 5
+ __sanitizer_get_estimated_allocated_size@Base 5
+ __sanitizer_get_free_bytes@Base 5
+ __sanitizer_get_heap_size@Base 5
+ __sanitizer_get_ownership@Base 5
+ __sanitizer_get_unmapped_bytes@Base 5
+ __sanitizer_malloc_hook@Base 5
+ __sanitizer_maybe_open_cov_file@Base 5
+ __sanitizer_print_stack_trace@Base 5
  __sanitizer_report_error_summary@Base 4.9
  __sanitizer_sandbox_on_notify@Base 4.9
  __sanitizer_set_report_path@Base 4.9
@@ -1111,6 +1244,7 @@ libtsan.so.0 libtsan0 #MINVER#
  __sanitizer_unaligned_store32@Base 4.9
  __sanitizer_unaligned_store64@Base 4.9
  __sigsetjmp@Base 4.9
+ __tls_get_addr@Base 5
  __tsan_acquire@Base 4.9
  __tsan_atomic128_compare_exchange_strong@Base 4.9
  __tsan_atomic128_compare_exchange_val@Base 4.9
@@ -1179,6 +1313,7 @@ libtsan.so.0 libtsan0 #MINVER#
  __tsan_func_exit@Base 4.9
  __tsan_init@Base 4.9
  __tsan_java_alloc@Base 4.9
+ __tsan_java_finalize@Base 5
  __tsan_java_fini@Base 4.9
  __tsan_java_free@Base 4.9
  __tsan_java_init@Base 4.9
@@ -1210,22 +1345,34 @@ libtsan.so.0 libtsan0 #MINVER#
  __tsan_write4@Base 4.9
  __tsan_write8@Base 4.9
  __tsan_write_range@Base 4.9
+ __uflow@Base 5
+ __underflow@Base 5
+ __woverflow@Base 5
+ __wuflow@Base 5
+ __wunderflow@Base 5
  __xpg_strerror_r@Base 4.9
  __xstat64@Base 4.9
  __xstat@Base 4.9
  _exit@Base 4.9
+ _obstack_begin@Base 5
+ _obstack_begin_1@Base 5
+ _obstack_newchunk@Base 5
  _setjmp@Base 4.9
  abort@Base 4.9
  accept4@Base 4.9
  accept@Base 4.9
+ aligned_alloc@Base 5
  asctime@Base 4.9
  asctime_r@Base 4.9
+ asprintf@Base 5
  atexit@Base 4.9
  backtrace@Base 4.9
  backtrace_symbols@Base 4.9
  bind@Base 4.9
  calloc@Base 4.9
  canonicalize_file_name@Base 4.9
+ capget@Base 5
+ capset@Base 5
  cfree@Base 4.9
  clock_getres@Base 4.9
  clock_gettime@Base 4.9
@@ -1243,6 +1390,8 @@ libtsan.so.0 libtsan0 #MINVER#
  dup2@Base 4.9
  dup3@Base 4.9
  dup@Base 4.9
+ endgrent@Base 5
+ endpwent@Base 5
  epoll_create1@Base 4.9
  epoll_create@Base 4.9
  epoll_ctl@Base 4.9
@@ -1256,11 +1405,18 @@ libtsan.so.0 libtsan0 #MINVER#
  ether_ntohost@Base 4.9
  eventfd@Base 4.9
  fclose@Base 4.9
+ fdopen@Base 5
  fflush@Base 4.9
+ fgetxattr@Base 5
+ flistxattr@Base 5
+ fmemopen@Base 5
+ fopen64@Base 5
  fopen@Base 4.9
  fork@Base 4.9
+ fprintf@Base 5
  fread@Base 4.9
  free@Base 4.9
+ freopen64@Base 5
  freopen@Base 4.9
  frexp@Base 4.9
  frexpf@Base 4.9
@@ -1272,6 +1428,7 @@ libtsan.so.0 libtsan0 #MINVER#
  fstatfs@Base 4.9
  fstatvfs64@Base 4.9
  fstatvfs@Base 4.9
+ ftime@Base 5
  fwrite@Base 4.9
  get_current_dir_name@Base 4.9
  getaddrinfo@Base 4.9
@@ -1286,17 +1443,27 @@ libtsan.so.0 libtsan0 #MINVER#
  gethostbyname_r@Base 4.9
  gethostent@Base 4.9
  gethostent_r@Base 4.9
+ getifaddrs@Base 5
  getitimer@Base 4.9
  getline@Base 4.9
  getmntent@Base 4.9
  getmntent_r@Base 4.9
+ getnameinfo@Base 5
+ getpass@Base 5
  getpeername@Base 4.9
+ getresgid@Base 5
+ getresuid@Base 5
  getsockname@Base 4.9
  getsockopt@Base 4.9
  gettimeofday@Base 4.9
+ getxattr@Base 5
+ glob64@Base 5
+ glob@Base 5
  gmtime@Base 4.9
  gmtime_r@Base 4.9
  iconv@Base 4.9
+ if_indextoname@Base 5
+ if_nametoindex@Base 5
  inet_aton@Base 4.9
  inet_ntop@Base 4.9
  inet_pton@Base 4.9
@@ -1311,7 +1478,10 @@ libtsan.so.0 libtsan0 #MINVER#
  lgammaf_r@Base 4.9
  lgammal@Base 4.9
  lgammal_r@Base 4.9
+ lgetxattr@Base 5
  listen@Base 4.9
+ listxattr@Base 5
+ llistxattr@Base 5
  localtime@Base 4.9
  localtime_r@Base 4.9
  longjmp@Base 4.9
@@ -1330,6 +1500,7 @@ libtsan.so.0 libtsan0 #MINVER#
  memmove@Base 4.9
  memrchr@Base 4.9
  memset@Base 4.9
+ mktime@Base 5
  mlock@Base 4.9
  mlockall@Base 4.9
  mmap64@Base 4.9
@@ -1344,6 +1515,8 @@ libtsan.so.0 libtsan0 #MINVER#
  on_exit@Base 4.9
  open64@Base 4.9
  open@Base 4.9
+ open_memstream@Base 5
+ open_wmemstream@Base 5
  opendir@Base 4.9
  pipe2@Base 4.9
  pipe@Base 4.9
@@ -1355,6 +1528,7 @@ libtsan.so.0 libtsan0 #MINVER#
  pread@Base 4.9
  preadv64@Base 4.9
  preadv@Base 4.9
+ printf@Base 5
  pthread_attr_getaffinity_np@Base 4.9
  pthread_attr_getdetachstate@Base 4.9
  pthread_attr_getguardsize@Base 4.9
@@ -1367,12 +1541,15 @@ libtsan.so.0 libtsan0 #MINVER#
  pthread_barrier_destroy@Base 4.9
  pthread_barrier_init@Base 4.9
  pthread_barrier_wait@Base 4.9
+ pthread_barrierattr_getpshared@Base 5
  pthread_cond_broadcast@Base 4.9
  pthread_cond_destroy@Base 4.9
  pthread_cond_init@Base 4.9
  pthread_cond_signal@Base 4.9
  pthread_cond_timedwait@Base 4.9
  pthread_cond_wait@Base 4.9
+ pthread_condattr_getclock@Base 5
+ pthread_condattr_getpshared@Base 5
  pthread_create@Base 4.9
  pthread_detach@Base 4.9
  pthread_getschedparam@Base 4.9
@@ -1384,6 +1561,12 @@ libtsan.so.0 libtsan0 #MINVER#
  pthread_mutex_timedlock@Base 4.9
  pthread_mutex_trylock@Base 4.9
  pthread_mutex_unlock@Base 4.9
+ pthread_mutexattr_getprioceiling@Base 5
+ pthread_mutexattr_getprotocol@Base 5
+ pthread_mutexattr_getpshared@Base 5
+ pthread_mutexattr_getrobust@Base 5
+ pthread_mutexattr_getrobust_np@Base 5
+ pthread_mutexattr_gettype@Base 5
  pthread_once@Base 4.9
  pthread_rwlock_destroy@Base 4.9
  pthread_rwlock_init@Base 4.9
@@ -1394,6 +1577,8 @@ libtsan.so.0 libtsan0 #MINVER#
  pthread_rwlock_trywrlock@Base 4.9
  pthread_rwlock_unlock@Base 4.9
  pthread_rwlock_wrlock@Base 4.9
+ pthread_rwlockattr_getkind_np@Base 5
+ pthread_rwlockattr_getpshared@Base 5
  pthread_setname_np@Base 4.9
  pthread_spin_destroy@Base 4.9
  pthread_spin_init@Base 4.9
@@ -1408,6 +1593,7 @@ libtsan.so.0 libtsan0 #MINVER#
  pwritev64@Base 4.9
  pwritev@Base 4.9
  raise@Base 4.9
+ rand_r@Base 5
  random_r@Base 4.9
  read@Base 4.9
  readdir64@Base 4.9
@@ -1436,9 +1622,11 @@ libtsan.so.0 libtsan0 #MINVER#
  sem_wait@Base 4.9
  send@Base 4.9
  sendmsg@Base 4.9
+ setgrent@Base 5
  setitimer@Base 4.9
  setjmp@Base 4.9
  setlocale@Base 4.9
+ setpwent@Base 5
  shmctl@Base 4.9
  sigaction@Base 4.9
  sigemptyset@Base 4.9
@@ -1457,8 +1645,10 @@ libtsan.so.0 libtsan0 #MINVER#
  sincosf@Base 4.9
  sincosl@Base 4.9
  sleep@Base 4.9
+ snprintf@Base 5
  socket@Base 4.9
  socketpair@Base 4.9
+ sprintf@Base 5
  sscanf@Base 4.9
  stat64@Base 4.9
  stat@Base 4.9
@@ -1488,14 +1678,25 @@ libtsan.so.0 libtsan0 #MINVER#
  tempnam@Base 4.9
  textdomain@Base 4.9
  time@Base 4.9
+ timerfd_gettime@Base 5
+ timerfd_settime@Base 5
  times@Base 4.9
+ tmpfile64@Base 5
+ tmpfile@Base 5
  tmpnam@Base 4.9
  tmpnam_r@Base 4.9
+ tsearch@Base 5
  unlink@Base 4.9
  usleep@Base 4.9
  valloc@Base 4.9
+ vasprintf@Base 5
+ vfork@Base 5
+ vfprintf@Base 5
  vfscanf@Base 4.9
+ vprintf@Base 5
  vscanf@Base 4.9
+ vsnprintf@Base 5
+ vsprintf@Base 5
  vsscanf@Base 4.9
  wait3@Base 4.9
  wait4@Base 4.9
@@ -1508,3 +1709,33 @@ libtsan.so.0 libtsan0 #MINVER#
  wordexp@Base 4.9
  write@Base 4.9
  writev@Base 4.9
+ xdr_bool@Base 5
+ xdr_bytes@Base 5
+ xdr_char@Base 5
+ xdr_double@Base 5
+ xdr_enum@Base 5
+ xdr_float@Base 5
+ xdr_hyper@Base 5
+ xdr_int16_t@Base 5
+ xdr_int32_t@Base 5
+ xdr_int64_t@Base 5
+ xdr_int8_t@Base 5
+ xdr_int@Base 5
+ xdr_long@Base 5
+ xdr_longlong_t@Base 5
+ xdr_quad_t@Base 5
+ xdr_short@Base 5
+ xdr_string@Base 5
+ xdr_u_char@Base 5
+ xdr_u_hyper@Base 5
+ xdr_u_int@Base 5
+ xdr_u_long@Base 5
+ xdr_u_longlong_t@Base 5
+ xdr_u_quad_t@Base 5
+ xdr_u_short@Base 5
+ xdr_uint16_t@Base 5
+ xdr_uint32_t@Base 5
+ xdr_uint64_t@Base 5
+ xdr_uint8_t@Base 5
+ xdrmem_create@Base 5
+ xdrstdio_create@Base 5
diff --git a/debian/libubsan0.symbols b/debian/libubsan0.symbols
index 67a9cba..0e78ea0 100644
--- a/debian/libubsan0.symbols
+++ b/debian/libubsan0.symbols
@@ -42,6 +42,10 @@ libubsan.so.0 libubsan0 #MINVER#
  __asan_java_demangle_v3_callback@Base 4.9
  __sanitizer_cov@Base 4.9
  __sanitizer_cov_dump@Base 4.9
+ __sanitizer_cov_indir_call16@Base 5
+ __sanitizer_cov_init@Base 5
+ __sanitizer_cov_module_init@Base 5
+ __sanitizer_maybe_open_cov_file@Base 5
  __sanitizer_report_error_summary@Base 4.9
  __sanitizer_sandbox_on_notify@Base 4.9
  __sanitizer_set_report_path@Base 4.9
@@ -63,6 +67,10 @@ libubsan.so.0 libubsan0 #MINVER#
  __ubsan_handle_mul_overflow_abort@Base 4.9
  __ubsan_handle_negate_overflow@Base 4.9
  __ubsan_handle_negate_overflow_abort@Base 4.9
+ __ubsan_handle_nonnull_arg@Base 5
+ __ubsan_handle_nonnull_arg_abort@Base 5
+ __ubsan_handle_nonnull_return@Base 5
+ __ubsan_handle_nonnull_return_abort@Base 5
  __ubsan_handle_out_of_bounds@Base 4.9
  __ubsan_handle_out_of_bounds_abort@Base 4.9
  __ubsan_handle_shift_out_of_bounds@Base 4.9
diff --git a/debian/patches/ada-749574.diff b/debian/patches/ada-749574.diff
index dbcc94b..9dec870 100644
--- a/debian/patches/ada-749574.diff
+++ b/debian/patches/ada-749574.diff
@@ -18,7 +18,7 @@ Index: b/src/gcc/ada/gnatlink.adb
 ===================================================================
 --- a/src/gcc/ada/gnatlink.adb
 +++ b/src/gcc/ada/gnatlink.adb
-@@ -273,7 +273,12 @@
+@@ -266,7 +266,12 @@ procedure Gnatlink is
           Findex2 := File_Name'Last + 1;
        end if;
  
diff --git a/debian/patches/ada-arm.diff b/debian/patches/ada-arm.diff
index ce7f9bc..ed023d9 100644
--- a/debian/patches/ada-arm.diff
+++ b/debian/patches/ada-arm.diff
@@ -4,7 +4,7 @@ Index: b/src/gcc/ada/gcc-interface/Makefile.in
 ===================================================================
 --- a/src/gcc/ada/gcc-interface/Makefile.in
 +++ b/src/gcc/ada/gcc-interface/Makefile.in
-@@ -1964,7 +1964,10 @@ ifeq ($(strip $(filter-out arm% linux-gn
+@@ -1925,7 +1925,10 @@ ifeq ($(strip $(filter-out arm% linux-gn
      LIBGNAT_TARGET_PAIRS += \
      system.ads<system-linux-armeb.ads
    else
diff --git a/debian/patches/ada-gcc-name.diff b/debian/patches/ada-gcc-name.diff
index 0701a89..65fa8fa 100644
--- a/debian/patches/ada-gcc-name.diff
+++ b/debian/patches/ada-gcc-name.diff
@@ -1,4 +1,4 @@
-# DP: use gcc-4.9 instead of gcc as the command name.
+# DP: use gcc-5 instead of gcc as the command name.
 
 Index: b/src/gcc/ada/comperr.adb
 ===================================================================
@@ -9,7 +9,7 @@ Index: b/src/gcc/ada/comperr.adb
  
                 Write_Str
 -                 ("| Include the exact gcc or gnatmake command " &
-+                 ("| Include the exact gcc-4.9 or gnatmake command " &
++                 ("| Include the exact gcc-5 or gnatmake command " &
                    "that you entered.");
                 End_Line;
  
@@ -22,7 +22,7 @@ Index: b/src/gcc/ada/gnatlink.adb
     --  generated file.
  
 -   Gcc : String_Access := Program_Name ("gcc", "gnatlink");
-+   Gcc : String_Access := Program_Name ("gcc-4.9", "gnatlink");
++   Gcc : String_Access := Program_Name ("gcc-5", "gnatlink");
  
     Read_Mode : constant String := "r" & ASCII.NUL;
  
@@ -32,7 +32,7 @@ Index: b/src/gcc/ada/gnatlink.adb
        Write_Line ("  --GCC=comp Use comp as the compiler");
 -      Write_Line ("  --LINK=nam Use 'nam' for the linking rather than 'gcc'");
 +      Write_Line ("  --LINK=nam Use 'nam' for the linking rather " &
-+                  "than 'gcc-4.9'");
++                  "than 'gcc-5'");
        Write_Eol;
        Write_Line ("  [non-Ada-objects]  list of non Ada object files");
        Write_Line ("  [linker-options]   other options for the linker");
@@ -45,7 +45,7 @@ Index: b/src/gcc/ada/make.adb
     ----------------------------------------------------
  
 -   Gcc          : String_Access := Program_Name ("gcc", "gnatmake");
-+   Gcc          : String_Access := Program_Name ("gcc-4.9", "gnatmake");
++   Gcc          : String_Access := Program_Name ("gcc-5", "gnatmake");
     Original_Gcc : constant String_Access := Gcc;
     --  Original_Gcc is used to check if Gcc has been modified by a switch
     --  --GCC=, so that for VM platforms, it is not modified again, as it can
@@ -58,7 +58,7 @@ Index: b/src/gcc/ada/gnatchop.adb
     --  The name of the file holding the GNAT configuration pragmas
  
 -   Gcc : String_Access := new String'("gcc");
-+   Gcc : String_Access := new String'("gcc-4.9");
++   Gcc : String_Access := new String'("gcc-5");
     --  May be modified by switch --GCC=
  
     Gcc_Set : Boolean := False;
@@ -71,7 +71,7 @@ Index: b/src/gcc/ada/mdll-utl.adb
     Dlltool_Exec  : OS_Lib.String_Access;
  
 -   Gcc_Name      : constant String := "gcc";
-+   Gcc_Name      : constant String := "gcc-4.9";
++   Gcc_Name      : constant String := "gcc-5";
     Gcc_Exec      : OS_Lib.String_Access;
  
     Gnatbind_Name : constant String := "gnatbind";
@@ -80,7 +80,7 @@ Index: b/src/gcc/ada/mdll-utl.adb
        end if;
  
 -      Print_Command ("gcc", Arguments (1 .. A));
-+      Print_Command ("gcc-4.9", Arguments (1 .. A));
++      Print_Command ("gcc-5", Arguments (1 .. A));
  
        OS_Lib.Spawn (Gcc_Exec.all, Arguments (1 .. A), Success);
  
@@ -93,7 +93,7 @@ Index: b/src/gcc/ada/mlib-utl.adb
           if Gcc_Exec = null then
              if Gcc_Name = null then
 -               Gcc_Name := Osint.Program_Name ("gcc", "gnatmake");
-+               Gcc_Name := Osint.Program_Name ("gcc-4.9", "gnatmake");
++               Gcc_Name := Osint.Program_Name ("gcc-5", "gnatmake");
              end if;
  
              Gcc_Exec := Locate_Exec_On_Path (Gcc_Name.all);
@@ -106,7 +106,7 @@ Index: b/src/gcc/ada/prj-makr.adb
     procedure Dup2 (Old_Fd, New_Fd : File_Descriptor);
  
 -   Gcc      : constant String := "gcc";
-+   Gcc      : constant String := "gcc-4.9";
++   Gcc      : constant String := "gcc-5";
     Gcc_Path : String_Access := null;
  
     Non_Empty_Node : constant Project_Node_Id := 1;
diff --git a/debian/patches/ada-hurd.diff b/debian/patches/ada-hurd.diff
index 29cd8f9..c1692ad 100644
--- a/debian/patches/ada-hurd.diff
+++ b/debian/patches/ada-hurd.diff
@@ -1,4 +1,4 @@
-Index: gnat-4.9-4.9.0/src/gcc/ada/s-osinte-gnu.ads
+Index: b/src/gcc/ada/s-osinte-gnu.ads
 ===================================================================
 --- /dev/null
 +++ b/src/gcc/ada/s-osinte-gnu.ads
@@ -804,7 +804,7 @@ Index: b/src/gcc/ada/gcc-interface/Makefile.in
 ===================================================================
 --- a/src/gcc/ada/gcc-interface/Makefile.in
 +++ b/src/gcc/ada/gcc-interface/Makefile.in
-@@ -1296,6 +1296,35 @@ ifeq ($(strip $(filter-out %86 kfreebsd%
+@@ -1385,6 +1385,35 @@ ifeq ($(strip $(filter-out %86 kfreebsd%
    MISCLIB = -lutil
  endif
  
diff --git a/debian/patches/ada-kfreebsd.diff b/debian/patches/ada-kfreebsd.diff
index dbabf5d..a7afd80 100644
--- a/debian/patches/ada-kfreebsd.diff
+++ b/debian/patches/ada-kfreebsd.diff
@@ -4,7 +4,7 @@ Index: b/src/gcc/ada/terminals.c
 ===================================================================
 --- a/src/gcc/ada/terminals.c
 +++ b/src/gcc/ada/terminals.c
-@@ -987,6 +987,7 @@
+@@ -1071,6 +1071,7 @@ __gnat_setup_winsize (void *desc, int ro
  /* On some system termio is either absent or including it will disable termios
     (HP-UX) */
  #if ! defined (__hpux__) && ! defined (FREEBSD) && \
@@ -179,7 +179,7 @@ Index: b/src/gcc/ada/gcc-interface/Makefile.in
 ===================================================================
 --- a/src/gcc/ada/gcc-interface/Makefile.in
 +++ b/src/gcc/ada/gcc-interface/Makefile.in
-@@ -1272,7 +1272,7 @@
+@@ -1361,7 +1361,7 @@ ifeq ($(strip $(filter-out %86 kfreebsd%
    a-intnam.ads<a-intnam-freebsd.ads \
    s-inmaop.adb<s-inmaop-posix.adb \
    s-intman.adb<s-intman-posix.adb \
@@ -188,7 +188,7 @@ Index: b/src/gcc/ada/gcc-interface/Makefile.in
    s-osinte.ads<s-osinte-kfreebsd-gnu.ads \
    s-osprim.adb<s-osprim-posix.adb \
    s-taprop.adb<s-taprop-posix.adb \
-@@ -1330,7 +1330,7 @@
+@@ -1421,7 +1421,7 @@ ifeq ($(strip $(filter-out x86_64 kfreeb
    a-numaux.ads<a-numaux-x86.ads \
    s-inmaop.adb<s-inmaop-posix.adb \
    s-intman.adb<s-intman-posix.adb \
@@ -201,7 +201,7 @@ Index: b/src/gcc/ada/s-osinte-kfreebsd-gnu.ads
 ===================================================================
 --- a/src/gcc/ada/s-osinte-kfreebsd-gnu.ads
 +++ b/src/gcc/ada/s-osinte-kfreebsd-gnu.ads
-@@ -45,6 +45,7 @@
+@@ -45,6 +45,7 @@ package System.OS_Interface is
     pragma Preelaborate;
  
     pragma Linker_Options ("-lpthread");
@@ -209,7 +209,7 @@ Index: b/src/gcc/ada/s-osinte-kfreebsd-gnu.ads
  
     subtype int            is Interfaces.C.int;
     subtype char           is Interfaces.C.char;
-@@ -206,9 +207,7 @@
+@@ -206,9 +207,7 @@ package System.OS_Interface is
     function nanosleep (rqtp, rmtp : access timespec) return int;
     pragma Import (C, nanosleep, "nanosleep");
  
@@ -220,7 +220,7 @@ Index: b/src/gcc/ada/s-osinte-kfreebsd-gnu.ads
  
     function clock_gettime
       (clock_id : clockid_t;
-@@ -252,6 +251,16 @@
+@@ -252,6 +251,16 @@ package System.OS_Interface is
     function getpid return pid_t;
     pragma Import (C, getpid, "getpid");
  
@@ -237,7 +237,7 @@ Index: b/src/gcc/ada/s-osinte-kfreebsd-gnu.ads
     -------------
     -- Threads --
     -------------
-@@ -282,6 +291,14 @@
+@@ -282,6 +291,14 @@ package System.OS_Interface is
     PTHREAD_SCOPE_PROCESS : constant := 0;
     PTHREAD_SCOPE_SYSTEM  : constant := 2;
  
@@ -252,7 +252,7 @@ Index: b/src/gcc/ada/s-osinte-kfreebsd-gnu.ads
     -----------
     -- Stack --
     -----------
-@@ -419,31 +436,25 @@
+@@ -419,31 +436,25 @@ package System.OS_Interface is
     PTHREAD_PRIO_PROTECT : constant := 2;
     PTHREAD_PRIO_INHERIT : constant := 1;
  
@@ -288,7 +288,7 @@ Index: b/src/gcc/ada/s-osinte-kfreebsd-gnu.ads
  
     type struct_sched_param is record
        sched_priority : int;  --  scheduling priority
-@@ -570,8 +581,8 @@
+@@ -570,8 +581,8 @@ private
     --  #define sa_handler __sigaction_u._handler
     --  #define sa_sigaction __sigaction_u._sigaction
  
@@ -299,7 +299,7 @@ Index: b/src/gcc/ada/s-osinte-kfreebsd-gnu.ads
     --  sigcontext type is opaque, so it is architecturally neutral.
     --  It is always passed as an access type, so define it as an empty record
     --  since the contents are not used anywhere.
-@@ -588,9 +599,6 @@
+@@ -588,9 +599,6 @@ private
     end record;
     pragma Convention (C, timespec);
  
@@ -313,7 +313,7 @@ Index: b/src/gcc/ada/gsocket.h
 ===================================================================
 --- a/src/gcc/ada/gsocket.h
 +++ b/src/gcc/ada/gsocket.h
-@@ -231,7 +231,7 @@
+@@ -241,7 +241,7 @@
  # endif
  #endif
  
@@ -326,7 +326,7 @@ Index: b/src/gcc/ada/s-oscons-tmplt.c
 ===================================================================
 --- a/src/gcc/ada/s-oscons-tmplt.c
 +++ b/src/gcc/ada/s-oscons-tmplt.c
-@@ -1420,7 +1420,7 @@
+@@ -1446,7 +1446,7 @@ CND(CLOCK_FASTEST, "Fastest clock")
  #endif
  CND(CLOCK_THREAD_CPUTIME_ID, "Thread CPU clock")
  
diff --git a/debian/patches/ada-mips.diff b/debian/patches/ada-mips.diff
index f9f46da..25e3f12 100644
--- a/debian/patches/ada-mips.diff
+++ b/debian/patches/ada-mips.diff
@@ -4,7 +4,7 @@ Index: b/src/gcc/ada/gcc-interface/Makefile.in
 ===================================================================
 --- a/src/gcc/ada/gcc-interface/Makefile.in
 +++ b/src/gcc/ada/gcc-interface/Makefile.in
-@@ -1809,10 +1809,15 @@ ifeq ($(strip $(filter-out mips linux%,$
+@@ -1772,10 +1772,15 @@ ifeq ($(strip $(filter-out mips linux%,$
    s-taprop.adb<s-taprop-linux.adb \
    s-tasinf.ads<s-tasinf-linux.ads \
    s-tasinf.adb<s-tasinf-linux.adb \
diff --git a/debian/patches/ada-ppc64.diff b/debian/patches/ada-ppc64.diff
index 1233e4a..524ecdb 100644
--- a/debian/patches/ada-ppc64.diff
+++ b/debian/patches/ada-ppc64.diff
@@ -6,7 +6,7 @@ Index: b/src/gcc/ada/gcc-interface/Makefile.in
 ===================================================================
 --- a/src/gcc/ada/gcc-interface/Makefile.in
 +++ b/src/gcc/ada/gcc-interface/Makefile.in
-@@ -1945,9 +1945,14 @@ ifeq ($(strip $(filter-out powerpc% linu
+@@ -1908,9 +1908,14 @@ ifeq ($(strip $(filter-out powerpc% linu
      LIBGNAT_TARGET_PAIRS_64 = \
      system.ads<system-linux-ppc64.ads
  
diff --git a/debian/patches/ada-revert-pr63225.diff b/debian/patches/ada-revert-pr63225.diff
index 045f5f3..5355777 100644
--- a/debian/patches/ada-revert-pr63225.diff
+++ b/debian/patches/ada-revert-pr63225.diff
@@ -1,11 +1,13 @@
 # DP: Revert the changes made to allow bootstrapping with -fno-inline.
 # DP: We allow inlining during bootstrap and this change breaks aliversion compatibility
-# DP: with earlier uploads of libgnatvsn4.9.  This patch shall be removed in the next
+# DP: with earlier uploads of libgnatvsn5.  This patch shall be removed in the next
 # DP: major version of GNAT.
 
+Index: b/src/gcc/ada/uintp.adb
+===================================================================
 --- a/src/gcc/ada/uintp.adb
 +++ b/src/gcc/ada/uintp.adb
-@@ -171,6 +171,22 @@
+@@ -171,6 +171,22 @@ package body Uintp is
     --  If Discard_Quotient is True, Quotient is set to No_Uint
     --  If Discard_Remainder is True, Remainder is set to No_Uint
  
@@ -28,9 +30,11 @@
     ------------
     -- Direct --
     ------------
+Index: b/src/gcc/ada/uintp.ads
+===================================================================
 --- a/src/gcc/ada/uintp.ads
 +++ b/src/gcc/ada/uintp.ads
-@@ -90,18 +90,6 @@
+@@ -90,18 +90,6 @@ package Uintp is
     Uint_Minus_80  : constant Uint;
     Uint_Minus_128 : constant Uint;
  
@@ -49,7 +53,7 @@
     -----------------
     -- Subprograms --
     -----------------
-@@ -264,22 +252,6 @@
+@@ -264,22 +252,6 @@ package Uintp is
     --  function is used for capacity checks, and it can be one bit off
     --  without affecting its usage.
  
@@ -72,7 +76,7 @@
     ---------------------
     -- Output Routines --
     ---------------------
-@@ -522,6 +494,18 @@
+@@ -527,6 +499,18 @@ private
     --  UI_Vector is defined for this purpose and some internal subprograms
     --  used for converting from one to the other are defined.
  
diff --git a/debian/patches/alpha-no-ev4-directive.diff b/debian/patches/alpha-no-ev4-directive.diff
index 0c21c65..53e535d 100644
--- a/debian/patches/alpha-no-ev4-directive.diff
+++ b/debian/patches/alpha-no-ev4-directive.diff
@@ -8,7 +8,7 @@ Index: b/src/gcc/config/alpha/alpha.c
 ===================================================================
 --- a/src/gcc/config/alpha/alpha.c
 +++ b/src/gcc/config/alpha/alpha.c
-@@ -9426,7 +9426,7 @@ alpha_file_start (void)
+@@ -9539,7 +9539,7 @@ alpha_file_start (void)
      fputs ("\t.set nomacro\n", asm_out_file);
    if (TARGET_SUPPORT_ARCH | TARGET_BWX | TARGET_MAX | TARGET_FIX | TARGET_CIX)
      {
@@ -17,7 +17,7 @@ Index: b/src/gcc/config/alpha/alpha.c
  
        if (alpha_cpu == PROCESSOR_EV6 || TARGET_FIX || TARGET_CIX)
  	arch = "ev6";
-@@ -9436,10 +9436,9 @@ alpha_file_start (void)
+@@ -9549,10 +9549,9 @@ alpha_file_start (void)
  	arch = "ev56";
        else if (alpha_cpu == PROCESSOR_EV5)
  	arch = "ev5";
diff --git a/debian/patches/arm-multilib-defaults.diff b/debian/patches/arm-multilib-defaults.diff
index be54bac..caa4439 100644
--- a/debian/patches/arm-multilib-defaults.diff
+++ b/debian/patches/arm-multilib-defaults.diff
@@ -4,7 +4,7 @@ Index: b/src/gcc/config.gcc
 ===================================================================
 --- a/src/gcc/config.gcc
 +++ b/src/gcc/config.gcc
-@@ -3521,10 +3521,18 @@ case "${target}" in
+@@ -3607,10 +3607,18 @@ case "${target}" in
  		fi
  
  		case "$with_float" in
@@ -25,7 +25,7 @@ Index: b/src/gcc/config.gcc
  		*)
  			echo "Unknown floating point type used in --with-float=$with_float" 1>&2
  			exit 1
-@@ -3561,6 +3569,9 @@ case "${target}" in
+@@ -3644,6 +3652,9 @@ case "${target}" in
  		"" \
  		| arm | thumb )
  			#OK
@@ -39,7 +39,7 @@ Index: b/src/gcc/config/arm/linux-eabi.h
 ===================================================================
 --- a/src/gcc/config/arm/linux-eabi.h
 +++ b/src/gcc/config/arm/linux-eabi.h
-@@ -43,7 +43,21 @@
+@@ -34,7 +34,21 @@
     target hardware.  If you override this to use the hard-float ABI then
     change the setting of GLIBC_DYNAMIC_LINKER_DEFAULT as well.  */
  #undef  TARGET_DEFAULT_FLOAT_ABI
@@ -61,7 +61,7 @@ Index: b/src/gcc/config/arm/linux-eabi.h
  
  /* We default to the "aapcs-linux" ABI so that enums are int-sized by
     default.  */
-@@ -86,6 +100,28 @@
+@@ -77,6 +91,28 @@
      %{mfloat-abi=soft*:" GLIBC_DYNAMIC_LINKER_SOFT_FLOAT "} \
      %{!mfloat-abi=*:" GLIBC_DYNAMIC_LINKER_DEFAULT "}"
  
diff --git a/debian/patches/config-ml-trunk.diff b/debian/patches/config-ml-trunk.diff
deleted file mode 100644
index 2dd9429..0000000
--- a/debian/patches/config-ml-trunk.diff
+++ /dev/null
@@ -1,167 +0,0 @@
-# DP: - Disable some biarch libraries for biarch builds.
-# DP: - Fix multilib builds on kernels which don't support all multilibs.
-
-Index: b/src/config-ml.in
-===================================================================
---- a/src/config-ml.in
-+++ b/src/config-ml.in
-@@ -475,6 +475,25 @@ powerpc*-*-* | rs6000*-*-*)
- 	;;
- esac
- 
-+if [ -z "$biarch_multidir_names" ]; then
-+  biarch_multidir_names="libiberty libstdc++-v3 libgfortran libmudflap libssp libffi libobjc libgomp"
-+  echo "WARNING: biarch_multidir_names is unset. Use default value:"
-+  echo "  $biarch_multidir_names"
-+fi
-+ml_srcbase=`basename $ml_realsrcdir`
-+old_multidirs="${multidirs}"
-+multidirs=""
-+for x in ${old_multidirs}; do
-+    case " $x " in
-+	" 32 "|" n32 "|" x32 "|" 64 "|" hf "|" sf ")
-+	case "$biarch_multidir_names" in
-+	    *"$ml_srcbase"*) multidirs="${multidirs} ${x}" ;;
-+	esac
-+	;;
-+	*) multidirs="${multidirs} ${x}" ;;
-+    esac
-+done
-+
- # Remove extraneous blanks from multidirs.
- # Tests like `if [ -n "$multidirs" ]' require it.
- multidirs=`echo "$multidirs" | sed -e 's/^[ ][ ]*//' -e 's/[ ][ ]*$//' -e 's/[ ][ ]*/ /g'`
-@@ -662,6 +681,35 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
- 
-   for ml_dir in ${multidirs}; do
- 
-+    # a native build fails if the running kernel doesn't support the multilib
-+    # variant; force cross compilation for these cases.
-+    ml_host_arg=
-+    case "${host}" in
-+    i[34567]86-*-linux*)
-+        case "${ml_dir}" in
-+	  64) ml_host_arg="--host=x86_64-linux-gnu";;
-+	  x32) ml_host_arg="--host=x86_64-linux-gnux32";;
-+	esac
-+	;;
-+    powerpc-*-linux*)
-+	case "${ml_dir}" in
-+	  64) ml_host_arg="--host=powerpc64-linux-gnu"
-+	esac
-+	;;
-+    s390-*-linux*)
-+	case "${ml_dir}" in
-+	  64) ml_host_arg="--host=s390x-linux-gnu"
-+	esac
-+	;;
-+    x86_64-*-linux*)
-+	case "${ml_dir}" in
-+	  x32) ml_host_arg="--host=x86_64-linux-gnux32"
-+	esac
-+    esac
-+    if [ -n "${ml_host_arg}" ]; then
-+       ml_host_arg="${ml_host_arg} --with-default-host-alias=${host_alias}"
-+    fi
-+
-     if [ "${ml_verbose}" = --verbose ]; then
-       echo "Running configure in multilib subdir ${ml_dir}"
-       echo "pwd: `${PWDCMD-pwd}`"
-@@ -866,9 +914,20 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
- 	fi
-     fi
- 
-+    ml_configure_args=
-+    for arg in ${ac_configure_args}
-+    do
-+      case $arg in
-+      *CC=*)  ml_configure_args=${ml_config_env} ;;
-+      *CXX=*) ml_configure_args=${ml_config_env} ;;
-+      *GCJ=*) ml_configure_args=${ml_config_env} ;;
-+      *) ;;
-+      esac
-+    done
-+
-     if eval ${ml_config_env} ${ml_config_shell} ${ml_recprog} \
- 	--with-multisubdir=${ml_dir} --with-multisrctop=${multisrctop} \
--	"${ac_configure_args}" ${ml_config_env} ${ml_srcdiroption} ; then
-+	"${ac_configure_args}" ${ml_configure_args} ${ml_config_env} ${ml_srcdiroption} ; then
-       true
-     else
-       exit 1
-Index: b/src/libstdc++-v3/include/Makefile.am
-===================================================================
---- a/src/libstdc++-v3/include/Makefile.am
-+++ b/src/libstdc++-v3/include/Makefile.am
-@@ -847,8 +847,9 @@ c_compatibility_headers_extra =
- endif
- 
- host_srcdir = ${glibcxx_srcdir}/$(OS_INC_SRCDIR)
--host_builddir = ./${host_alias}/bits
--host_installdir = ${gxx_include_dir}/${host_alias}$(MULTISUBDIR)/bits
-+default_host_alias = @default_host_alias@
-+host_builddir = ./${default_host_alias}/bits
-+host_installdir = ${gxx_include_dir}/${default_host_alias}$(MULTISUBDIR)/bits
- host_headers = \
- 	${host_srcdir}/ctype_base.h \
- 	${host_srcdir}/ctype_inline.h \
-@@ -1074,6 +1075,7 @@ stamp-profile-impl: ${profile_impl_heade
- stamp-${host_alias}:
- 	@-mkdir -p ${host_builddir}
- 	@-mkdir -p ${host_builddir}/../ext
-+	@test ${default_host_alias} = ${host_alias} || ln -sf ${default_host_alias} ${host_alias}
- 	@$(STAMP) stamp-${host_alias}
- 
- # Host includes static.
-Index: b/src/libstdc++-v3/include/Makefile.in
-===================================================================
---- a/src/libstdc++-v3/include/Makefile.in
-+++ b/src/libstdc++-v3/include/Makefile.in
-@@ -205,6 +205,7 @@ builddir = @builddir@
- check_msgfmt = @check_msgfmt@
- datadir = @datadir@
- datarootdir = @datarootdir@
-+default_host_alias = @default_host_alias@
- docdir = @docdir@
- dvidir = @dvidir@
- enable_shared = @enable_shared@
-@@ -1108,8 +1109,8 @@ profile_impl_headers = \
- # For --enable-cheaders=c_std
- @GLIBCXX_C_HEADERS_COMPATIBILITY_TRUE@c_compatibility_headers_extra = ${c_compatibility_headers}
- host_srcdir = ${glibcxx_srcdir}/$(OS_INC_SRCDIR)
--host_builddir = ./${host_alias}/bits
--host_installdir = ${gxx_include_dir}/${host_alias}$(MULTISUBDIR)/bits
-+host_builddir = ./${default_host_alias}/bits
-+host_installdir = ${gxx_include_dir}/${default_host_alias}$(MULTISUBDIR)/bits
- host_headers = \
- 	${host_srcdir}/ctype_base.h \
- 	${host_srcdir}/ctype_inline.h \
-@@ -1493,6 +1494,7 @@ stamp-profile-impl: ${profile_impl_heade
- stamp-${host_alias}:
- 	@-mkdir -p ${host_builddir}
- 	@-mkdir -p ${host_builddir}/../ext
-+	@test ${default_host_alias} = ${host_alias} || ln -sf ${default_host_alias} ${host_alias}
- 	@$(STAMP) stamp-${host_alias}
- 
- # Host includes static.
-Index: b/src/libstdc++-v3/configure.ac
-===================================================================
---- a/src/libstdc++-v3/configure.ac
-+++ b/src/libstdc++-v3/configure.ac
-@@ -476,6 +476,16 @@ else
-   multilib_arg=
- fi
- 
-+AC_ARG_WITH(default-host-alias,
-+[AS_HELP_STRING([--with-default-host-alias=TRIPLET],
-+                [specifies host triplet used for the default multilib build])],
-+[case "${withval}" in
-+yes)    AC_MSG_ERROR(bad value ${withval} given for default host triplet) ;;
-+no)     default_host_alias='${host_alias}' ;;
-+*)      default_host_alias=${withval} ;;
-+esac],[default_host_alias='${host_alias}'])
-+AC_SUBST(default_host_alias)
-+
- # Export all the install information.
- GLIBCXX_EXPORT_INSTALL_INFO
- 
diff --git a/debian/patches/config-ml.diff b/debian/patches/config-ml.diff
index 4826fc6..66a8c34 100644
--- a/debian/patches/config-ml.diff
+++ b/debian/patches/config-ml.diff
@@ -5,7 +5,7 @@ Index: b/src/config-ml.in
 ===================================================================
 --- a/src/config-ml.in
 +++ b/src/config-ml.in
-@@ -467,6 +467,25 @@ powerpc*-*-* | rs6000*-*-*)
+@@ -475,6 +475,25 @@ powerpc*-*-* | rs6000*-*-*)
  	;;
  esac
  
@@ -31,7 +31,7 @@ Index: b/src/config-ml.in
  # Remove extraneous blanks from multidirs.
  # Tests like `if [ -n "$multidirs" ]' require it.
  multidirs=`echo "$multidirs" | sed -e 's/^[ ][ ]*//' -e 's/[ ][ ]*$//' -e 's/[ ][ ]*/ /g'`
-@@ -654,6 +673,35 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
+@@ -662,6 +681,35 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
  
    for ml_dir in ${multidirs}; do
  
@@ -67,7 +67,7 @@ Index: b/src/config-ml.in
      if [ "${ml_verbose}" = --verbose ]; then
        echo "Running configure in multilib subdir ${ml_dir}"
        echo "pwd: `${PWDCMD-pwd}`"
-@@ -858,9 +906,20 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
+@@ -866,9 +914,20 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
  	fi
      fi
  
@@ -84,8 +84,8 @@ Index: b/src/config-ml.in
 +
      if eval ${ml_config_env} ${ml_config_shell} ${ml_recprog} \
  	--with-multisubdir=${ml_dir} --with-multisrctop=${multisrctop} \
--	${ac_configure_args} ${ml_config_env} ${ml_srcdiroption} ; then
-+	${ac_configure_args} ${ml_configure_args} ${ml_host_arg} ${ml_srcdiroption} ; then
+-	"${ac_configure_args}" ${ml_config_env} ${ml_srcdiroption} ; then
++	"${ac_configure_args}" ${ml_configure_args} ${ml_config_env} ${ml_srcdiroption} ; then
        true
      else
        exit 1
@@ -93,7 +93,7 @@ Index: b/src/libstdc++-v3/include/Makefile.am
 ===================================================================
 --- a/src/libstdc++-v3/include/Makefile.am
 +++ b/src/libstdc++-v3/include/Makefile.am
-@@ -844,8 +844,9 @@ c_compatibility_headers_extra =
+@@ -859,8 +859,9 @@ c_compatibility_headers_extra =
  endif
  
  host_srcdir = ${glibcxx_srcdir}/$(OS_INC_SRCDIR)
@@ -105,7 +105,7 @@ Index: b/src/libstdc++-v3/include/Makefile.am
  host_headers = \
  	${host_srcdir}/ctype_base.h \
  	${host_srcdir}/ctype_inline.h \
-@@ -1071,6 +1072,7 @@ stamp-profile-impl: ${profile_impl_heade
+@@ -1086,6 +1087,7 @@ stamp-profile-impl: ${profile_impl_heade
  stamp-${host_alias}:
  	@-mkdir -p ${host_builddir}
  	@-mkdir -p ${host_builddir}/../ext
@@ -125,7 +125,7 @@ Index: b/src/libstdc++-v3/include/Makefile.in
  docdir = @docdir@
  dvidir = @dvidir@
  enable_shared = @enable_shared@
-@@ -1105,8 +1106,8 @@ profile_impl_headers = \
+@@ -1121,8 +1122,8 @@ profile_impl_headers = \
  # For --enable-cheaders=c_std
  @GLIBCXX_C_HEADERS_COMPATIBILITY_TRUE@c_compatibility_headers_extra = ${c_compatibility_headers}
  host_srcdir = ${glibcxx_srcdir}/$(OS_INC_SRCDIR)
@@ -136,7 +136,7 @@ Index: b/src/libstdc++-v3/include/Makefile.in
  host_headers = \
  	${host_srcdir}/ctype_base.h \
  	${host_srcdir}/ctype_inline.h \
-@@ -1490,6 +1491,7 @@ stamp-profile-impl: ${profile_impl_heade
+@@ -1506,6 +1507,7 @@ stamp-profile-impl: ${profile_impl_heade
  stamp-${host_alias}:
  	@-mkdir -p ${host_builddir}
  	@-mkdir -p ${host_builddir}/../ext
@@ -148,7 +148,7 @@ Index: b/src/libstdc++-v3/configure.ac
 ===================================================================
 --- a/src/libstdc++-v3/configure.ac
 +++ b/src/libstdc++-v3/configure.ac
-@@ -476,6 +476,16 @@ else
+@@ -482,6 +482,16 @@ else
    multilib_arg=
  fi
  
diff --git a/debian/patches/g++-multiarch-incdir.diff b/debian/patches/g++-multiarch-incdir.diff
index e6e88d1..620f07e 100644
--- a/debian/patches/g++-multiarch-incdir.diff
+++ b/debian/patches/g++-multiarch-incdir.diff
@@ -5,7 +5,7 @@ Index: b/src/libstdc++-v3/include/Makefile.am
 ===================================================================
 --- a/src/libstdc++-v3/include/Makefile.am
 +++ b/src/libstdc++-v3/include/Makefile.am
-@@ -846,7 +846,7 @@ endif
+@@ -861,7 +861,7 @@ endif
  host_srcdir = ${glibcxx_srcdir}/$(OS_INC_SRCDIR)
  default_host_alias = @default_host_alias@
  host_builddir = ./${default_host_alias}/bits
@@ -18,7 +18,7 @@ Index: b/src/libstdc++-v3/include/Makefile.in
 ===================================================================
 --- a/src/libstdc++-v3/include/Makefile.in
 +++ b/src/libstdc++-v3/include/Makefile.in
-@@ -1107,7 +1107,7 @@ profile_impl_headers = \
+@@ -1123,7 +1123,7 @@ profile_impl_headers = \
  @GLIBCXX_C_HEADERS_COMPATIBILITY_TRUE@c_compatibility_headers_extra = ${c_compatibility_headers}
  host_srcdir = ${glibcxx_srcdir}/$(OS_INC_SRCDIR)
  host_builddir = ./${default_host_alias}/bits
@@ -31,7 +31,7 @@ Index: b/src/gcc/Makefile.in
 ===================================================================
 --- a/src/gcc/Makefile.in
 +++ b/src/gcc/Makefile.in
-@@ -1107,6 +1107,7 @@ FLAGS_TO_PASS = \
+@@ -1112,6 +1112,7 @@ FLAGS_TO_PASS = \
  	"prefix=$(prefix)" \
  	"local_prefix=$(local_prefix)" \
  	"gxx_include_dir=$(gcc_gxx_include_dir)" \
@@ -39,7 +39,7 @@ Index: b/src/gcc/Makefile.in
  	"build_tooldir=$(build_tooldir)" \
  	"gcc_tooldir=$(gcc_tooldir)" \
  	"bindir=$(bindir)" \
-@@ -1553,6 +1554,14 @@ ifneq ($(xmake_file),)
+@@ -1588,6 +1589,14 @@ ifneq ($(xmake_file),)
  include $(xmake_file)
  endif
  
@@ -54,7 +54,7 @@ Index: b/src/gcc/Makefile.in
  # all-tree.def includes all the tree.def files.
  all-tree.def: s-alltree; @true
  s-alltree: Makefile
-@@ -2510,7 +2519,7 @@ PREPROCESSOR_DEFINES = \
+@@ -2588,7 +2597,7 @@ PREPROCESSOR_DEFINES = \
    -DFIXED_INCLUDE_DIR=\"$(libsubdir)/include-fixed\" \
    -DGPLUSPLUS_INCLUDE_DIR=\"$(gcc_gxx_include_dir)\" \
    -DGPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT=$(gcc_gxx_include_dir_add_sysroot) \
diff --git a/debian/patches/gcc-as-needed.diff b/debian/patches/gcc-as-needed.diff
index 3ab6d3c..61d9330 100644
--- a/debian/patches/gcc-as-needed.diff
+++ b/debian/patches/gcc-as-needed.diff
@@ -4,7 +4,7 @@ Index: b/src/gcc/config/aarch64/aarch64-linux.h
 ===================================================================
 --- a/src/gcc/config/aarch64/aarch64-linux.h
 +++ b/src/gcc/config/aarch64/aarch64-linux.h
-@@ -27,6 +27,7 @@
+@@ -33,6 +33,7 @@
  
  #define LINUX_TARGET_LINK_SPEC  "%{h*}		\
     --hash-style=gnu				\
@@ -55,7 +55,7 @@ Index: b/src/gcc/config/rs6000/linux64.h
 ===================================================================
 --- a/src/gcc/config/rs6000/linux64.h
 +++ b/src/gcc/config/rs6000/linux64.h
-@@ -417,11 +417,11 @@ extern int dot_symbols;
+@@ -396,11 +396,11 @@ extern int dot_symbols;
  					   " -m elf64ppc")
  #endif
  
@@ -73,7 +73,7 @@ Index: b/src/gcc/config/rs6000/sysv4.h
 ===================================================================
 --- a/src/gcc/config/rs6000/sysv4.h
 +++ b/src/gcc/config/rs6000/sysv4.h
-@@ -773,7 +773,7 @@ ENDIAN_SELECT(" -mbig", " -mlittle", DEF
+@@ -774,7 +774,7 @@ ENDIAN_SELECT(" -mbig", " -mlittle", DEF
  #define GNU_USER_DYNAMIC_LINKER \
    CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER)
  
@@ -136,26 +136,14 @@ Index: b/src/gcc/config/mips/gnu-user.h
 ===================================================================
 --- a/src/gcc/config/mips/gnu-user.h
 +++ b/src/gcc/config/mips/gnu-user.h
-@@ -56,6 +56,7 @@ along with GCC; see the file COPYING3.
+@@ -55,6 +55,7 @@ along with GCC; see the file COPYING3.
  #undef GNU_USER_TARGET_LINK_SPEC
- #define GNU_USER_TARGET_LINK_SPEC \
-  "%(endian_spec) \
-+ -as-needed \
-   %{shared:-shared} \
-   %{!shared: \
-     %{!static: \
-Index: b/src/gcc/config/mips/gnu-user64.h
-===================================================================
---- a/src/gcc/config/mips/gnu-user64.h
-+++ b/src/gcc/config/mips/gnu-user64.h
-@@ -34,6 +34,7 @@ along with GCC; see the file COPYING3.
  #define GNU_USER_TARGET_LINK_SPEC "\
- %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
- %{shared} \
+   %{G*} %{EB} %{EL} %{mips*} %{shared} \
 + -as-needed \
-  %(endian_spec) \
    %{!shared: \
      %{!static: \
+       %{rdynamic:-export-dynamic} \
 Index: b/src/libjava/Makefile.am
 ===================================================================
 --- a/src/libjava/Makefile.am
diff --git a/debian/patches/gcc-auto-build.diff b/debian/patches/gcc-auto-build.diff
index 2fa4095..9a6fffd 100644
--- a/debian/patches/gcc-auto-build.diff
+++ b/debian/patches/gcc-auto-build.diff
@@ -4,7 +4,7 @@ Index: b/src/gcc/configure.ac
 ===================================================================
 --- a/src/gcc/configure.ac
 +++ b/src/gcc/configure.ac
-@@ -1536,7 +1536,7 @@ else
+@@ -1628,7 +1628,7 @@ else
  	# Clearing GMPINC is necessary to prevent host headers being
  	# used by the build compiler.  Defining GENERATOR_FILE stops
  	# system.h from including gmp.h.
diff --git a/debian/patches/gcc-base-version.diff b/debian/patches/gcc-base-version.diff
index 20c1fe4..12d6008 100644
--- a/debian/patches/gcc-base-version.diff
+++ b/debian/patches/gcc-base-version.diff
@@ -1,29 +1,29 @@
-# DP: Set base version to 4.9, introduce full version 4.9.x.
+# DP: Set base version to 5, introduce full version 5.x.y.
 
 Index: b/src/gcc/BASE-VER
 ===================================================================
 --- a/src/gcc/BASE-VER
 +++ b/src/gcc/BASE-VER
 @@ -1 +1 @@
--4.9.2
-+4.9
+-5.0.0
++5
 Index: b/src/gcc/FULL-VER
 ===================================================================
 --- /dev/null
 +++ b/src/gcc/FULL-VER
 @@ -0,0 +1 @@
-+4.9.2
++5.0.0
 Index: b/src/gcc/Makefile.in
 ===================================================================
 --- a/src/gcc/Makefile.in
 +++ b/src/gcc/Makefile.in
-@@ -810,11 +810,13 @@
+@@ -811,11 +811,13 @@ GTM_H     = tm.h      $(tm_file_list) in
  TM_H      = $(GTM_H) insn-flags.h $(OPTIONS_H)
  
  # Variables for version information.
 -BASEVER     := $(srcdir)/BASE-VER  # 4.x.y
-+FULLVER     := $(srcdir)/FULL-VER  # 4.x.y
-+BASEVER     := $(srcdir)/BASE-VER  # 4.x
++FULLVER     := $(srcdir)/FULL-VER  # 5.x.y
++BASEVER     := $(srcdir)/BASE-VER  # 5.x
  DEVPHASE    := $(srcdir)/DEV-PHASE # experimental, prerelease, ""
  DATESTAMP   := $(srcdir)/DATESTAMP # YYYYMMDD or empty
  REVISION    := $(srcdir)/REVISION  # [BRANCH revision XXXXXX]
@@ -32,7 +32,7 @@ Index: b/src/gcc/Makefile.in
  BASEVER_c   := $(shell cat $(BASEVER))
  DEVPHASE_c  := $(shell cat $(DEVPHASE))
  DATESTAMP_c := $(shell cat $(DATESTAMP))
-@@ -833,7 +835,7 @@
+@@ -834,7 +836,7 @@ version     := $(BASEVER_c)
  # development phase collapsed to the empty string in release mode
  # (i.e. if DEVPHASE_c is empty).  The space immediately after the
  # comma in the $(if ...) constructs is significant - do not remove it.
@@ -41,7 +41,7 @@ Index: b/src/gcc/Makefile.in
  DEVPHASE_s  := "\"$(if $(DEVPHASE_c), ($(DEVPHASE_c)))\""
  DATESTAMP_s := "\"$(if $(DEVPHASE_c), $(DATESTAMP_c))\""
  PKGVERSION_s:= "\"@PKGVERSION@\""
-@@ -1924,8 +1926,8 @@
+@@ -1962,8 +1964,8 @@ default-c.o: config/default-c.c
  
  # Files used by all variants of C and some other languages.
  
@@ -52,17 +52,17 @@ Index: b/src/gcc/Makefile.in
  
  # Language-independent files.
  
-@@ -1933,7 +1935,8 @@
+@@ -1971,7 +1973,8 @@ DRIVER_DEFINES = \
    -DSTANDARD_STARTFILE_PREFIX=\"$(unlibsubdir)/\" \
    -DSTANDARD_EXEC_PREFIX=\"$(libdir)/gcc/\" \
    -DSTANDARD_LIBEXEC_PREFIX=\"$(libexecdir)/gcc/\" \
 -  -DDEFAULT_TARGET_VERSION=\"$(version)\" \
 +  -DDEFAULT_TARGET_VERSION=\"$(BASEVER_c)\" \
 +  -DDEFAULT_TARGET_FULL_VERSION=\"$(FULLVER_c)\" \
+   -DDEFAULT_REAL_TARGET_MACHINE=\"$(real_target_noncanonical)\" \
    -DDEFAULT_TARGET_MACHINE=\"$(target_noncanonical)\" \
    -DSTANDARD_BINDIR_PREFIX=\"$(bindir)/\" \
-   -DTOOLDIR_BASE_PREFIX=\"$(libsubdir_to_prefix)$(prefix_to_exec_prefix)\" \
-@@ -1981,20 +1984,20 @@
+@@ -2021,20 +2024,20 @@ s-options-h: optionlist $(srcdir)/opt-fu
  
  dumpvers: dumpvers.c
  
@@ -89,7 +89,7 @@ Index: b/src/gcc/Makefile.in
  	echo "#define BUILDING_GCC_VERSION (BUILDING_GCC_MAJOR * 1000 + BUILDING_GCC_MINOR)" >> bversion.h
  	$(STAMP) s-bversion
  
-@@ -2323,9 +2326,9 @@
+@@ -2382,9 +2385,9 @@ build/%.o :  # dependencies provided by
  ## build/version.o is compiled by the $(COMPILER_FOR_BUILD) but needs
  ## several C macro definitions, just like version.o
  build/version.o:  version.c version.h \
@@ -101,7 +101,7 @@ Index: b/src/gcc/Makefile.in
  	-DREVISION=$(REVISION_s) \
  	-DDEVPHASE=$(DEVPHASE_s) -DPKGVERSION=$(PKGVERSION_s) \
  	-DBUGURL=$(BUGURL_s) -o $@ $<
-@@ -2518,8 +2521,8 @@
+@@ -2595,8 +2598,8 @@ PREPROCESSOR_DEFINES = \
    -DSTANDARD_EXEC_PREFIX=\"$(libdir)/gcc/\" \
    @TARGET_SYSTEM_ROOT_DEFINE@
  
@@ -112,7 +112,7 @@ Index: b/src/gcc/Makefile.in
  
  CFLAGS-cppdefault.o += $(PREPROCESSOR_DEFINES)
  
-@@ -2535,8 +2538,8 @@
+@@ -2612,8 +2615,8 @@ build/gcov-iov$(build_exeext): build/gco
  		build/gcov-iov.o -o $@
  
  gcov-iov.h: s-iov
@@ -123,7 +123,7 @@ Index: b/src/gcc/Makefile.in
  	    > tmp-gcov-iov.h
  	$(SHELL) $(srcdir)/../move-if-change tmp-gcov-iov.h gcov-iov.h
  	$(STAMP) s-iov
-@@ -2797,8 +2800,8 @@
+@@ -2890,8 +2893,8 @@ TEXI_GCCINSTALL_FILES = install.texi ins
  TEXI_CPPINT_FILES = cppinternals.texi gcc-common.texi gcc-vers.texi
  
  # gcc-vers.texi is generated from the version files.
@@ -134,42 +134,17 @@ Index: b/src/gcc/Makefile.in
  	 if [ "$(DEVPHASE_c)" = "experimental" ]; \
  	 then echo "@set DEVELOPMENT"; \
  	 else echo "@clear DEVELOPMENT"; \
-Index: b/src/libjava/Makefile.am
-===================================================================
---- a/src/libjava/Makefile.am
-+++ b/src/libjava/Makefile.am
-@@ -780,7 +780,7 @@
- install-data-local:
- 	$(PRE_INSTALL)
- ## Install the .pc file.
--	@pc_version=`echo $(GCJVERSION) | sed -e 's/[.][^.]*$$//'`; \
-+	@pc_version=$(GCJVERSION); \
- 	file="libgcj-$${pc_version}.pc"; \
- 	$(mkinstalldirs) $(DESTDIR)$(pkgconfigdir); \
- 	echo "  $(INSTALL_DATA) libgcj.pc $(DESTDIR)$(pkgconfigdir)/$$file"; \
-Index: b/src/libjava/Makefile.in
-===================================================================
---- a/src/libjava/Makefile.in
-+++ b/src/libjava/Makefile.in
-@@ -12457,7 +12457,7 @@
- @BUILD_ECJ1_TRUE@	mv $(DESTDIR)$(libexecsubdir)/`echo ecjx | sed 's,^.*/,,;$(transform);s/$$/$(EXEEXT)/'` $(DESTDIR)$(libexecsubdir)/ecj1$(host_exeext)
- install-data-local:
- 	$(PRE_INSTALL)
--	@pc_version=`echo $(GCJVERSION) | sed -e 's/[.][^.]*$$//'`; \
-+	@pc_version=$(GCJVERSION); \
- 	file="libgcj-$${pc_version}.pc"; \
- 	$(mkinstalldirs) $(DESTDIR)$(pkgconfigdir); \
- 	echo "  $(INSTALL_DATA) libgcj.pc $(DESTDIR)$(pkgconfigdir)/$$file"; \
 Index: b/src/libjava/testsuite/lib/libjava.exp
 ===================================================================
 --- a/src/libjava/testsuite/lib/libjava.exp
 +++ b/src/libjava/testsuite/lib/libjava.exp
-@@ -177,7 +177,7 @@
+@@ -179,7 +179,8 @@ proc libjava_init { args } {
  
      set text [eval exec "$GCJ_UNDER_TEST -B$specdir -v 2>@ stdout"]
      regexp " version \[^\n\r\]*" $text version
 -    set libjava_version [lindex $version 1]
-+    set libjava_version 4.9
++    # FIXME: Still needed?
++    #set libjava_version 5
  
      verbose "version: $libjava_version"
  
@@ -177,7 +152,7 @@ Index: b/src/gcc/gcc.c
 ===================================================================
 --- a/src/gcc/gcc.c
 +++ b/src/gcc/gcc.c
-@@ -152,7 +152,8 @@
+@@ -152,7 +152,8 @@ static const char *compiler_version;
  
  /* The target version.  */
  
@@ -187,30 +162,30 @@ Index: b/src/gcc/gcc.c
  
  /* The target machine.  */
  
-@@ -4058,7 +4059,7 @@
+@@ -4251,7 +4252,7 @@ process_command (unsigned int decoded_op
+      running, or, if that is not available, the configured prefix.  */
    tooldir_prefix
      = concat (gcc_exec_prefix ? gcc_exec_prefix : standard_exec_prefix,
- 	      spec_machine, dir_separator_str,
--	      spec_version, dir_separator_str, tooldir_prefix2, NULL);
-+	      base_version, dir_separator_str, tooldir_prefix2, NULL);
+-	      spec_host_machine, dir_separator_str, spec_version,
++	      spec_host_machine, dir_separator_str, base_version,
+ 	      accel_dir_suffix, dir_separator_str, tooldir_prefix2, NULL);
    free (tooldir_prefix2);
  
-   add_prefix (&exec_prefixes,
-@@ -6465,7 +6466,7 @@
+@@ -7102,7 +7103,7 @@ driver::set_up_specs () const
+ 
    /* Read specs from a file if there is one.  */
  
-   machine_suffix = concat (spec_machine, dir_separator_str,
--			   spec_version, dir_separator_str, NULL);
-+			   base_version, dir_separator_str, NULL);
+-  machine_suffix = concat (spec_host_machine, dir_separator_str, spec_version,
++  machine_suffix = concat (spec_host_machine, dir_separator_str, base_version,
+ 			   accel_dir_suffix, dir_separator_str, NULL);
    just_machine_suffix = concat (spec_machine, dir_separator_str, NULL);
  
-   specs_file = find_a_file (&startfile_prefixes, "specs", R_OK, true);
-@@ -6664,7 +6665,7 @@
+@@ -7307,7 +7308,7 @@ driver::set_up_specs () const
    /* If we have a GCC_EXEC_PREFIX envvar, modify it for cpp's sake.  */
    if (gcc_exec_prefix)
-     gcc_exec_prefix = concat (gcc_exec_prefix, spec_machine, dir_separator_str,
--			      spec_version, dir_separator_str, NULL);
-+			      base_version, dir_separator_str, NULL);
+     gcc_exec_prefix = concat (gcc_exec_prefix, spec_host_machine,
+-			      dir_separator_str, spec_version,
++			      dir_separator_str, base_version,
+ 			      accel_dir_suffix, dir_separator_str, NULL);
  
    /* Now we have the specs.
-      Set the `valid' bits for switches that match anything in any spec.  */
diff --git a/debian/patches/gcc-driver-extra-langs.diff b/debian/patches/gcc-driver-extra-langs.diff
index 64a06ea..12ed81d 100644
--- a/debian/patches/gcc-driver-extra-langs.diff
+++ b/debian/patches/gcc-driver-extra-langs.diff
@@ -9,10 +9,10 @@ Index: b/src/gcc/Makefile.in
 ===================================================================
 --- a/src/gcc/Makefile.in
 +++ b/src/gcc/Makefile.in
-@@ -536,8 +536,8 @@
- 		      guality.exp \
- 		      struct-layout-1.exp,stackalign.exp \
- 		      $(dg_target_exps)
+@@ -531,8 +531,8 @@ lang_checks_parallelized=
+ # It doesn't make sense to try e.g. 128 goals for small testsuites
+ # like objc or go.
+ check_gcc_parallelize=10000
 -lang_opt_files=@lang_opt_files@ $(srcdir)/c-family/c.opt $(srcdir)/common.opt
 -lang_specs_files=@lang_specs_files@
 +lang_opt_files=$(sort @lang_opt_files@ $(srcdir)/c-family/c.opt $(srcdir)/common.opt $(foreach lang,$(subst ada,ada/gcc-interface,$(debian_extra_langs)),$(srcdir)/$(lang)/lang.opt))
diff --git a/debian/patches/gcc-gfdl-build.diff b/debian/patches/gcc-gfdl-build.diff
index 819b413..0ece101 100644
--- a/debian/patches/gcc-gfdl-build.diff
+++ b/debian/patches/gcc-gfdl-build.diff
@@ -4,7 +4,7 @@ Index: b/src/gcc/Makefile.in
 ===================================================================
 --- a/src/gcc/Makefile.in
 +++ b/src/gcc/Makefile.in
-@@ -2202,30 +2202,8 @@ s-tm-texi: $(srcdir)/doc/../doc/tm.texi
+@@ -2241,30 +2241,8 @@ s-tm-texi: $(srcdir)/doc/../doc/tm.texi
  # \r is not portable to Solaris tr, therefore we have a special
  # case for ASCII.  We use \r for other encodings like EBCDIC.
  s-tm-texi: build/genhooks$(build_exeext) $(srcdir)/doc/tm.texi.in
@@ -35,5 +35,5 @@ Index: b/src/gcc/Makefile.in
 +	cat $(srcdir)/doc/tm.texi.in > tmp-tm.texi
 +	$(STAMP) $@
  
- GTFILES = $(CPP_ID_DATA_H) $(srcdir)/input.h $(srcdir)/coretypes.h \
-   $(host_xm_file_list) \
+ gimple-match.c: s-match gimple-match-head.c ; @true
+ generic-match.c: s-match generic-match-head.c ; @true
diff --git a/debian/patches/gcc-hash-style-gnu.diff b/debian/patches/gcc-hash-style-gnu.diff
index 7f67144..854349c 100644
--- a/debian/patches/gcc-hash-style-gnu.diff
+++ b/debian/patches/gcc-hash-style-gnu.diff
@@ -64,7 +64,7 @@ Index: b/src/gcc/config/rs6000/linux64.h
 ===================================================================
 --- a/src/gcc/config/rs6000/linux64.h
 +++ b/src/gcc/config/rs6000/linux64.h
-@@ -406,11 +406,11 @@ extern int dot_symbols;
+@@ -396,11 +396,11 @@ extern int dot_symbols;
  					   " -m elf64ppc")
  #endif
  
@@ -82,7 +82,7 @@ Index: b/src/gcc/config/rs6000/sysv4.h
 ===================================================================
 --- a/src/gcc/config/rs6000/sysv4.h
 +++ b/src/gcc/config/rs6000/sysv4.h
-@@ -773,7 +773,7 @@ ENDIAN_SELECT(" -mbig", " -mlittle", DEF
+@@ -774,7 +774,7 @@ ENDIAN_SELECT(" -mbig", " -mlittle", DEF
  #define GNU_USER_DYNAMIC_LINKER \
    CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER)
  
@@ -158,7 +158,7 @@ Index: b/src/gcc/config/aarch64/aarch64-linux.h
 ===================================================================
 --- a/src/gcc/config/aarch64/aarch64-linux.h
 +++ b/src/gcc/config/aarch64/aarch64-linux.h
-@@ -26,6 +26,7 @@
+@@ -32,6 +32,7 @@
  #define CPP_SPEC "%{pthread:-D_REENTRANT}"
  
  #define LINUX_TARGET_LINK_SPEC  "%{h*}		\
diff --git a/debian/patches/gcc-ice-apport.diff b/debian/patches/gcc-ice-apport.diff
index 8c100c4..a86db9e 100644
--- a/debian/patches/gcc-ice-apport.diff
+++ b/debian/patches/gcc-ice-apport.diff
@@ -5,20 +5,20 @@ Index: b/src/gcc/gcc.c
 ===================================================================
 --- a/src/gcc/gcc.c
 +++ b/src/gcc/gcc.c
-@@ -6319,6 +6319,16 @@ retry_ice (const char *prog, const char
- 	      fnotice (stderr, "Preprocessed source stored into %s file,"
- 			       " please attach this to your bugreport.\n",
- 		       temp_filenames[attempt * 2]);
+@@ -6518,6 +6518,16 @@ do_report_bug (const char **new_argv, co
+     {
+       fnotice (stderr, "Preprocessed source stored into %s file,"
+ 	       " please attach this to your bugreport.\n", *out_file);
 +	      if (!getenv ("GCC_NOAPPORT")
 +		  && !access ("/usr/share/apport/gcc_ice_hook", R_OK | X_OK))
 +		{
-+		  char *cmd = XNEWVEC (char, 50 + strlen (temp_filenames[attempt * 2])
++		  char *cmd = XNEWVEC (char, 50 + strlen (*out_file)
 +				             + strlen (new_argv[0]));
 +		  sprintf (cmd, "/usr/share/apport/gcc_ice_hook %s %s",
-+			   new_argv[0], temp_filenames[attempt * 2]);
++			   new_argv[0], *out_file);
 +		  system (cmd);
 +		  free (cmd);
 +		}
- 	      /* Make sure it is not deleted.  */
- 	      free (temp_filenames[attempt * 2]);
- 	      temp_filenames[attempt * 2] = NULL;
+       /* Make sure it is not deleted.  */
+       free (*out_file);
+       *out_file = NULL;
diff --git a/debian/patches/gcc-ice-hack.diff b/debian/patches/gcc-ice-hack.diff
deleted file mode 100644
index bcd75ca..0000000
--- a/debian/patches/gcc-ice-hack.diff
+++ /dev/null
@@ -1,315 +0,0 @@
-# DP: Retry the build on an ice, save the calling options and preprocessed
-# DP: source when the ice is reproducible.
-
-2004-01-23  Jakub Jelinek  <jakub@redhat.com>
-
-	* gcc.c (execute): Don't free first string early, but at the end
-	of the function.  Call retry_ice if compiler exited with
-	ICE_EXIT_CODE.
-	(retry_ice): New function.
-	* diagnostic.c (diagnostic_count_diagnostic,
-	diagnostic_action_after_output, error_recursion): Exit with
-	ICE_EXIT_CODE instead of FATAL_EXIT_CODE.
-
-#--- a/src/gcc/Makefile.in
-#+++ b/src/gcc/Makefile.in
-#@@ -181,6 +181,8 @@ SYSCALLS.c.X-warn = -Wno-strict-prototypes -Wno-error
-# dfp.o-warn = -Wno-error
-# # mips-tfile.c contains -Wcast-qual warnings.
-# mips-tfile.o-warn = -Wno-error
-#+# gcc-ice-hack
-#+gcc.o-warn = -Wno-error
-# 
-# # All warnings have to be shut off in stage1 if the compiler used then
-# # isn't gcc; configure determines that.  WARN_CFLAGS will be either
-Index: b/src/gcc/gcc.c
-===================================================================
---- a/src/gcc/gcc.c
-+++ b/src/gcc/gcc.c
-@@ -252,6 +252,9 @@ static void init_gcc_specs (struct obsta
- #if defined(HAVE_TARGET_OBJECT_SUFFIX) || defined(HAVE_TARGET_EXECUTABLE_SUFFIX)
- static const char *convert_filename (const char *, int, int);
- #endif
-+#if !(defined (__MSDOS__) || defined (OS2) || defined (VMS))
-+static void retry_ice (const char *prog, const char **argv);
-+#endif
- 
- static const char *getenv_spec_function (int, const char **);
- static const char *if_exists_spec_function (int, const char **);
-@@ -2798,7 +2801,7 @@ execute (void)
- 	    }
- 	}
- 
--      if (string != commands[i].prog)
-+      if (i && string != commands[i].prog)
- 	free (CONST_CAST (char *, string));
-     }
- 
-@@ -2851,6 +2854,16 @@ execute (void)
- 	else if (WIFEXITED (status)
- 		 && WEXITSTATUS (status) >= MIN_FATAL_STATUS)
- 	  {
-+#if !(defined (__MSDOS__) || defined (OS2) || defined (VMS))
-+	    /* For ICEs in cc1, cc1obj, cc1plus see if it is
-+	       reproducible or not.  */
-+	    const char *p;
-+	    if (WEXITSTATUS (status) == ICE_EXIT_CODE
-+		&& i == 0
-+		&& (p = strrchr (commands[0].argv[0], DIR_SEPARATOR))
-+		&& ! strncmp (p + 1, "cc1", 3))
-+	      retry_ice (commands[0].prog, commands[0].argv);
-+#endif
- 	    if (WEXITSTATUS (status) > greatest_status)
- 	      greatest_status = WEXITSTATUS (status);
- 	    ret_code = -1;
-@@ -2908,6 +2921,9 @@ execute (void)
- 	  }
-       }
- 
-+    if (commands[0].argv[0] != commands[0].prog)
-+      free (CONST_CAST (char *, commands[0].argv[0]));
-+
-     return ret_code;
-   }
- }
-@@ -6099,6 +6115,227 @@ give_switch (int switchnum, int omit_fir
-   switches[switchnum].validated = true;
- }
- 
-+#if !(defined (__MSDOS__) || defined (OS2) || defined (VMS))
-+#define RETRY_ICE_ATTEMPTS 2
-+
-+static void
-+retry_ice (const char *prog, const char **argv)
-+{
-+  int nargs, out_arg = -1, quiet = 0, attempt;
-+  int pid, retries, sleep_interval;
-+  const char **new_argv;
-+  char *temp_filenames[RETRY_ICE_ATTEMPTS * 2 + 2];
-+
-+  if (gcc_input_filename == NULL || ! strcmp (gcc_input_filename, "-"))
-+    return;
-+
-+  for (nargs = 0; argv[nargs] != NULL; ++nargs)
-+    /* Only retry compiler ICEs, not preprocessor ones.  */
-+    if (! strcmp (argv[nargs], "-E"))
-+      return;
-+    else if (argv[nargs][0] == '-' && argv[nargs][1] == 'o')
-+      {
-+	if (out_arg == -1)
-+	  out_arg = nargs;
-+	else
-+	  return;
-+      }
-+    /* If the compiler is going to output any time information,
-+       it might varry between invocations.  */
-+    else if (! strcmp (argv[nargs], "-quiet"))
-+      quiet = 1;
-+    else if (! strcmp (argv[nargs], "-ftime-report"))
-+      return;
-+
-+  if (out_arg == -1 || !quiet)
-+    return;
-+
-+  memset (temp_filenames, '\0', sizeof (temp_filenames));
-+  new_argv = XALLOCAVEC (const char *, nargs + 3);
-+  memcpy (new_argv, argv, (nargs + 1) * sizeof (const char *));
-+  new_argv[nargs++] = "-frandom-seed=0";
-+  new_argv[nargs] = NULL;
-+  if (new_argv[out_arg][2] == '\0')
-+    new_argv[out_arg + 1] = "-";
-+  else
-+    new_argv[out_arg] = "-o-";
-+
-+  for (attempt = 0; attempt < RETRY_ICE_ATTEMPTS + 1; ++attempt)
-+    {
-+      int fd = -1;
-+      int status;
-+
-+      temp_filenames[attempt * 2] = make_temp_file (".out");
-+      temp_filenames[attempt * 2 + 1] = make_temp_file (".err");
-+
-+      if (attempt == RETRY_ICE_ATTEMPTS)
-+        {
-+	  int i;
-+	  int fd1, fd2;
-+	  struct stat st1, st2;
-+	  size_t n, len;
-+	  char *buf;
-+
-+	  buf = XNEWVEC (char, 8192);
-+
-+	  for (i = 0; i < 2; ++i)
-+	    {
-+	      fd1 = open (temp_filenames[i], O_RDONLY);
-+	      fd2 = open (temp_filenames[2 + i], O_RDONLY);
-+
-+	      if (fd1 < 0 || fd2 < 0)
-+		{
-+		  i = -1;
-+		  close (fd1);
-+		  close (fd2);
-+		  break;
-+		}
-+
-+	      if (fstat (fd1, &st1) < 0 || fstat (fd2, &st2) < 0)
-+		{
-+		  i = -1;
-+		  close (fd1);
-+		  close (fd2);
-+		  break;
-+		}
-+
-+	      if (st1.st_size != st2.st_size)
-+		{
-+		  close (fd1);
-+		  close (fd2);
-+		  break;
-+		}
-+
-+	      len = 0;
-+	      for (n = st1.st_size; n; n -= len)
-+		{
-+		  len = n;
-+		  if (len > 4096)
-+		    len = 4096;
-+
-+		  if (read (fd1, buf, len) != (int) len
-+		      || read (fd2, buf + 4096, len) != (int) len)
-+		    {
-+		      i = -1;
-+		      break;
-+		    }
-+
-+		  if (memcmp (buf, buf + 4096, len) != 0)
-+		    break;
-+		}
-+
-+	      close (fd1);
-+	      close (fd2);
-+
-+	      if (n)
-+		break;
-+	    }
-+
-+	  free (buf);
-+	  if (i == -1)
-+	    break;
-+
-+	  if (i != 2)
-+	    {
-+	      fnotice (stderr, "The bug is not reproducible, so it is"
-+			       " likely a hardware or OS problem.\n");
-+	      break;
-+	    }
-+
-+          fd = open (temp_filenames[attempt * 2], O_RDWR);
-+	  if (fd < 0)
-+	    break;
-+	  write (fd, "//", 2);
-+	  for (i = 0; i < nargs; i++)
-+	    {
-+	      write (fd, " ", 1);
-+	      write (fd, new_argv[i], strlen (new_argv[i]));
-+	    }
-+	  write (fd, "\n", 1);
-+	  new_argv[nargs] = "-E";
-+	  new_argv[nargs + 1] = NULL;
-+        }
-+
-+      /* Fork a subprocess; wait and retry if it fails.  */
-+      sleep_interval = 1;
-+      pid = -1;
-+      for (retries = 0; retries < 4; retries++)
-+	{
-+	  pid = fork ();
-+	  if (pid >= 0)
-+	    break;
-+	  sleep (sleep_interval);
-+	  sleep_interval *= 2;
-+	}
-+
-+      if (pid < 0)
-+	break;
-+      else if (pid == 0)
-+	{
-+	  if (attempt != RETRY_ICE_ATTEMPTS)
-+	    fd = open (temp_filenames[attempt * 2], O_RDWR);
-+	  if (fd < 0)
-+	    exit (-1);
-+	  if (fd != 1)
-+	    {
-+	      close (1);
-+	      dup (fd);
-+	      close (fd);
-+	    }
-+
-+	  fd = open (temp_filenames[attempt * 2 + 1], O_RDWR);
-+	  if (fd < 0)
-+	    exit (-1);
-+	  if (fd != 2)
-+	    {
-+	      close (2);
-+	      dup (fd);
-+	      close (fd);
-+	    }
-+
-+	  if (prog == new_argv[0])
-+	    execvp (prog, CONST_CAST2 (char *const *, const char **, new_argv));
-+	  else
-+	    execv (new_argv[0], CONST_CAST2 (char *const *, const char **, new_argv));
-+	  exit (-1);
-+	}
-+
-+      if (waitpid (pid, &status, 0) < 0)
-+	break;
-+
-+      if (attempt < RETRY_ICE_ATTEMPTS
-+	  && (! WIFEXITED (status) || WEXITSTATUS (status) != ICE_EXIT_CODE))
-+	{
-+	  fnotice (stderr, "The bug is not reproducible, so it is"
-+			   " likely a hardware or OS problem.\n");
-+	  break;
-+	}
-+      else if (attempt == RETRY_ICE_ATTEMPTS)
-+	{
-+	  close (fd);
-+	  if (WIFEXITED (status)
-+	      && WEXITSTATUS (status) == SUCCESS_EXIT_CODE)
-+	    {
-+	      fnotice (stderr, "Preprocessed source stored into %s file,"
-+			       " please attach this to your bugreport.\n",
-+		       temp_filenames[attempt * 2]);
-+	      /* Make sure it is not deleted.  */
-+	      free (temp_filenames[attempt * 2]);
-+	      temp_filenames[attempt * 2] = NULL;
-+	      break;
-+	    }
-+	}
-+    }
-+
-+  for (attempt = 0; attempt < RETRY_ICE_ATTEMPTS * 2 + 2; attempt++)
-+    if (temp_filenames[attempt])
-+      {
-+	unlink (temp_filenames[attempt]);
-+	free (temp_filenames[attempt]);
-+      }
-+}
-+#endif
-+
- /* Search for a file named NAME trying various prefixes including the
-    user's -B prefix and some standard ones.
-    Return the absolute file name found.  If nothing is found, return NAME.  */
-Index: b/src/gcc/diagnostic.c
-===================================================================
---- a/src/gcc/diagnostic.c
-+++ b/src/gcc/diagnostic.c
-@@ -492,7 +492,7 @@ diagnostic_action_after_output (diagnost
- 	real_abort ();
-       diagnostic_finish (context);
-       fnotice (stderr, "compilation terminated.\n");
--      exit (FATAL_EXIT_CODE);
-+      exit (ICE_EXIT_CODE);
- 
-     default:
-       gcc_unreachable ();
diff --git a/debian/patches/gcc-linaro-doc.diff b/debian/patches/gcc-linaro-doc.diff
index 2d05f8a..d2cb221 100644
--- a/debian/patches/gcc-linaro-doc.diff
+++ b/debian/patches/gcc-linaro-doc.diff
@@ -1,449 +1,2 @@
-# DP: Changes for the Linaro 4.9-2015.01 release (documentation).
+# DP: Changes for the Linaro 5-2015.xx release (documentation).
 
---- a/src/gcc/doc/extend.texi
-+++ b/src/gcc/doc/extend.texi
-@@ -9109,13 +9109,14 @@
- instructions, but allow the compiler to schedule those calls.
- 
- @menu
-+* AArch64 Built-in Functions::
- * Alpha Built-in Functions::
- * Altera Nios II Built-in Functions::
- * ARC Built-in Functions::
- * ARC SIMD Built-in Functions::
- * ARM iWMMXt Built-in Functions::
--* ARM NEON Intrinsics::
--* ARM ACLE Intrinsics::
-+* ARM C Language Extensions (ACLE)::
-+* ARM Floating Point Status and Control Intrinsics::
- * AVR Built-in Functions::
- * Blackfin Built-in Functions::
- * FR-V Built-in Functions::
-@@ -9141,6 +9142,18 @@
- * TILEPro Built-in Functions::
- @end menu
- 
-+@node AArch64 Built-in Functions
-+@subsection AArch64 Built-in Functions
-+
-+These built-in functions are available for the AArch64 family of
-+processors.
-+@smallexample
-+unsigned int __builtin_aarch64_get_fpcr ()
-+void __builtin_aarch64_set_fpcr (unsigned int)
-+unsigned int __builtin_aarch64_get_fpsr ()
-+void __builtin_aarch64_set_fpsr (unsigned int)
-+@end smallexample
-+
- @node Alpha Built-in Functions
- @subsection Alpha Built-in Functions
- 
-@@ -9904,19 +9917,41 @@
- long long __builtin_arm_wzero ()
- @end smallexample
- 
--@node ARM NEON Intrinsics
--@subsection ARM NEON Intrinsics
- 
--These built-in intrinsics for the ARM Advanced SIMD extension are available
--when the @option{-mfpu=neon} switch is used:
-+@node ARM C Language Extensions (ACLE)
-+@subsection ARM C Language Extensions (ACLE)
- 
--@include arm-neon-intrinsics.texi
-+GCC implements extensions for C as described in the ARM C Language
-+Extensions (ACLE) specification, which can be found at
-+@uref{http://infocenter.arm.com/help/topic/com.arm.doc.ihi0053c/IHI0053C_acle_2_0.pdf}.
- 
--@node ARM ACLE Intrinsics
--@subsection ARM ACLE Intrinsics
-+As a part of ACLE, GCC implements extensions for Advanced SIMD as described in
-+the ARM C Language Extensions Specification.  The complete list of Advanced SIMD
-+intrinsics can be found at
-+@uref{http://infocenter.arm.com/help/topic/com.arm.doc.ihi0073a/IHI0073A_arm_neon_intrinsics_ref.pdf}.
-+The built-in intrinsics for the Advanced SIMD extension are available when
-+NEON is enabled.
- 
--@include arm-acle-intrinsics.texi
-+Currently, ARM and AArch64 back-ends do not support ACLE 2.0 fully.  Both
-+back-ends support CRC32 intrinsics from @file{arm_acle.h}.  The ARM backend's
-+16-bit floating-point Advanded SIMD Intrinsics currently comply to ACLE v1.1.
-+AArch64's backend does not have support for 16-bit floating point Advanced SIMD
-+Intrinsics yet.
- 
-+See @ref{ARM Options} and @ref{AArch64 Options} for more information on the
-+availability of extensions.
-+
-+@node ARM Floating Point Status and Control Intrinsics
-+@subsection ARM Floating Point Status and Control Intrinsics
-+
-+These built-in functions are available for the ARM family of
-+processors with floating-point unit.
-+
-+@smallexample
-+unsigned int __builtin_arm_get_fpscr ()
-+void __builtin_arm_set_fpscr (unsigned int)
-+@end smallexample
-+
- @node AVR Built-in Functions
- @subsection AVR Built-in Functions
- 
---- a/src/gcc/doc/aarch64-acle-intrinsics.texi
-+++ b/src/gcc/doc/aarch64-acle-intrinsics.texi
-@@ -0,0 +1,55 @@
-+@c Copyright (C) 2014 Free Software Foundation, Inc.
-+@c This is part of the GCC manual.
-+@c For copying conditions, see the file gcc.texi.
-+
-+@subsubsection CRC32 intrinsics
-+
-+These intrinsics are available when the CRC32 architecture extension is
-+specified, e.g. when the @option{-march=armv8-a+crc} switch is used, or when
-+the target processor specified with @option{-mcpu} supports it.
-+
-+@itemize @bullet
-+@item uint32_t __crc32b (uint32_t, uint8_t)
-+@*@emph{Form of expected instruction(s):} @code{crc32b @var{w0}, @var{w1}, @var{w2}}
-+@end itemize
-+
-+
-+@itemize @bullet
-+@item uint32_t __crc32h (uint32_t, uint16_t)
-+@*@emph{Form of expected instruction(s):} @code{crc32h @var{w0}, @var{w1}, @var{w2}}
-+@end itemize
-+
-+
-+@itemize @bullet
-+@item uint32_t __crc32w (uint32_t, uint32_t)
-+@*@emph{Form of expected instruction(s):} @code{crc32w @var{w0}, @var{w1}, @var{w2}}
-+@end itemize
-+
-+
-+@itemize @bullet
-+@item uint32_t __crc32d (uint32_t, uint64_t)
-+@*@emph{Form of expected instruction(s):} @code{crc32x @var{w0}, @var{w1}, @var{x2}}
-+@end itemize
-+
-+@itemize @bullet
-+@item uint32_t __crc32cb (uint32_t, uint8_t)
-+@*@emph{Form of expected instruction(s):} @code{crc32cb @var{w0}, @var{w1}, @var{w2}}
-+@end itemize
-+
-+
-+@itemize @bullet
-+@item uint32_t __crc32ch (uint32_t, uint16_t)
-+@*@emph{Form of expected instruction(s):} @code{crc32ch @var{w0}, @var{w1}, @var{w2}}
-+@end itemize
-+
-+
-+@itemize @bullet
-+@item uint32_t __crc32cw (uint32_t, uint32_t)
-+@*@emph{Form of expected instruction(s):} @code{crc32cw @var{w0}, @var{w1}, @var{w2}}
-+@end itemize
-+
-+
-+@itemize @bullet
-+@item uint32_t __crc32cd (uint32_t, uint64_t)
-+@*@emph{Form of expected instruction(s):} @code{crc32cx @var{w0}, @var{w1}, @var{x2}}
-+@end itemize
---- a/src/gcc/doc/tm.texi
-+++ b/src/gcc/doc/tm.texi
-@@ -1342,27 +1342,6 @@
- The default is to use @code{word_mode}.
- @end deftypefn
- 
--@defmac ROUND_TOWARDS_ZERO
--If defined, this macro should be true if the prevailing rounding
--mode is towards zero.
--
--Defining this macro only affects the way @file{libgcc.a} emulates
--floating-point arithmetic.
--
--Not defining this macro is equivalent to returning zero.
--@end defmac
--
--@defmac LARGEST_EXPONENT_IS_NORMAL (@var{size})
--This macro should return true if floats with @var{size}
--bits do not have a NaN or infinity representation, but use the largest
--exponent for normal numbers instead.
--
--Defining this macro only affects the way @file{libgcc.a} emulates
--floating-point arithmetic.
--
--The default definition of this macro returns false for all sizes.
--@end defmac
--
- @deftypefn {Target Hook} bool TARGET_MS_BITFIELD_LAYOUT_P (const_tree @var{record_type})
- This target hook returns @code{true} if bit-fields in the given
- @var{record_type} are to be laid out following the rules of Microsoft
-@@ -6311,13 +6290,40 @@
- If you don't define this, a reasonable default is used.
- @end defmac
- 
--@defmac MOVE_BY_PIECES_P (@var{size}, @var{alignment})
--A C expression used to determine whether @code{move_by_pieces} will be used to
--copy a chunk of memory, or whether some other block move mechanism
--will be used.  Defaults to 1 if @code{move_by_pieces_ninsns} returns less
--than @code{MOVE_RATIO}.
--@end defmac
-+@deftypefn {Target Hook} bool TARGET_USE_BY_PIECES_INFRASTRUCTURE_P (unsigned HOST_WIDE_INT @var{size}, unsigned int @var{alignment}, enum by_pieces_operation @var{op}, bool @var{speed_p})
-+GCC will attempt several strategies when asked to copy between
-+two areas of memory, or to set, clear or store to memory, for example
-+when copying a @code{struct}. The @code{by_pieces} infrastructure
-+implements such memory operations as a sequence of load, store or move
-+insns.  Alternate strategies are to expand the
-+@code{movmem} or @code{setmem} optabs, to emit a library call, or to emit
-+unit-by-unit, loop-based operations.
- 
-+This target hook should return true if, for a memory operation with a
-+given @var{size} and @var{alignment}, using the @code{by_pieces}
-+infrastructure is expected to result in better code generation.
-+Both @var{size} and @var{alignment} are measured in terms of storage
-+units.
-+
-+The parameter @var{op} is one of: @code{CLEAR_BY_PIECES},
-+@code{MOVE_BY_PIECES}, @code{SET_BY_PIECES}, @code{STORE_BY_PIECES}.
-+These describe the type of memory operation under consideration.
-+
-+The parameter @var{speed_p} is true if the code is currently being
-+optimized for speed rather than size.
-+
-+Returning true for higher values of @var{size} can improve code generation
-+for speed if the target does not provide an implementation of the
-+@code{movmem} or @code{setmem} standard names, if the @code{movmem} or
-+@code{setmem} implementation would be more expensive than a sequence of
-+insns, or if the overhead of a library call would dominate that of
-+the body of the memory operation.
-+
-+Returning true for higher values of @code{size} may also cause an increase
-+in code size, for example where the number of insns emitted to perform a
-+move would be greater than that of a library call.
-+@end deftypefn
-+
- @defmac MOVE_MAX_PIECES
- A C expression used by @code{move_by_pieces} to determine the largest unit
- a load or store used to copy memory is.  Defaults to @code{MOVE_MAX}.
-@@ -6335,13 +6341,6 @@
- If you don't define this, a reasonable default is used.
- @end defmac
- 
--@defmac CLEAR_BY_PIECES_P (@var{size}, @var{alignment})
--A C expression used to determine whether @code{clear_by_pieces} will be used
--to clear a chunk of memory, or whether some other block clear mechanism
--will be used.  Defaults to 1 if @code{move_by_pieces_ninsns} returns less
--than @code{CLEAR_RATIO}.
--@end defmac
--
- @defmac SET_RATIO (@var{speed})
- The threshold of number of scalar move insns, @emph{below} which a sequence
- of insns should be generated to set memory to a constant value, instead of
-@@ -6355,24 +6354,6 @@
- If you don't define this, it defaults to the value of @code{MOVE_RATIO}.
- @end defmac
- 
--@defmac SET_BY_PIECES_P (@var{size}, @var{alignment})
--A C expression used to determine whether @code{store_by_pieces} will be
--used to set a chunk of memory to a constant value, or whether some
--other mechanism will be used.  Used by @code{__builtin_memset} when
--storing values other than constant zero.
--Defaults to 1 if @code{move_by_pieces_ninsns} returns less
--than @code{SET_RATIO}.
--@end defmac
--
--@defmac STORE_BY_PIECES_P (@var{size}, @var{alignment})
--A C expression used to determine whether @code{store_by_pieces} will be
--used to set a chunk of memory to a constant string value, or whether some
--other mechanism will be used.  Used by @code{__builtin_strcpy} when
--called with a constant source string.
--Defaults to 1 if @code{move_by_pieces_ninsns} returns less
--than @code{MOVE_RATIO}.
--@end defmac
--
- @defmac USE_LOAD_POST_INCREMENT (@var{mode})
- A C expression used to determine whether a load postincrement is a good
- thing to use for a given mode.  Defaults to the value of
---- a/src/gcc/doc/tm.texi.in
-+++ b/src/gcc/doc/tm.texi.in
-@@ -1256,27 +1256,6 @@
- 
- @hook TARGET_UNWIND_WORD_MODE
- 
--@defmac ROUND_TOWARDS_ZERO
--If defined, this macro should be true if the prevailing rounding
--mode is towards zero.
--
--Defining this macro only affects the way @file{libgcc.a} emulates
--floating-point arithmetic.
--
--Not defining this macro is equivalent to returning zero.
--@end defmac
--
--@defmac LARGEST_EXPONENT_IS_NORMAL (@var{size})
--This macro should return true if floats with @var{size}
--bits do not have a NaN or infinity representation, but use the largest
--exponent for normal numbers instead.
--
--Defining this macro only affects the way @file{libgcc.a} emulates
--floating-point arithmetic.
--
--The default definition of this macro returns false for all sizes.
--@end defmac
--
- @hook TARGET_MS_BITFIELD_LAYOUT_P
- 
- @hook TARGET_DECIMAL_FLOAT_SUPPORTED_P
-@@ -4810,12 +4789,7 @@
- If you don't define this, a reasonable default is used.
- @end defmac
- 
--@defmac MOVE_BY_PIECES_P (@var{size}, @var{alignment})
--A C expression used to determine whether @code{move_by_pieces} will be used to
--copy a chunk of memory, or whether some other block move mechanism
--will be used.  Defaults to 1 if @code{move_by_pieces_ninsns} returns less
--than @code{MOVE_RATIO}.
--@end defmac
-+@hook TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
- 
- @defmac MOVE_MAX_PIECES
- A C expression used by @code{move_by_pieces} to determine the largest unit
-@@ -4834,13 +4808,6 @@
- If you don't define this, a reasonable default is used.
- @end defmac
- 
--@defmac CLEAR_BY_PIECES_P (@var{size}, @var{alignment})
--A C expression used to determine whether @code{clear_by_pieces} will be used
--to clear a chunk of memory, or whether some other block clear mechanism
--will be used.  Defaults to 1 if @code{move_by_pieces_ninsns} returns less
--than @code{CLEAR_RATIO}.
--@end defmac
--
- @defmac SET_RATIO (@var{speed})
- The threshold of number of scalar move insns, @emph{below} which a sequence
- of insns should be generated to set memory to a constant value, instead of
-@@ -4854,24 +4821,6 @@
- If you don't define this, it defaults to the value of @code{MOVE_RATIO}.
- @end defmac
- 
--@defmac SET_BY_PIECES_P (@var{size}, @var{alignment})
--A C expression used to determine whether @code{store_by_pieces} will be
--used to set a chunk of memory to a constant value, or whether some
--other mechanism will be used.  Used by @code{__builtin_memset} when
--storing values other than constant zero.
--Defaults to 1 if @code{move_by_pieces_ninsns} returns less
--than @code{SET_RATIO}.
--@end defmac
--
--@defmac STORE_BY_PIECES_P (@var{size}, @var{alignment})
--A C expression used to determine whether @code{store_by_pieces} will be
--used to set a chunk of memory to a constant string value, or whether some
--other mechanism will be used.  Used by @code{__builtin_strcpy} when
--called with a constant source string.
--Defaults to 1 if @code{move_by_pieces_ninsns} returns less
--than @code{MOVE_RATIO}.
--@end defmac
--
- @defmac USE_LOAD_POST_INCREMENT (@var{mode})
- A C expression used to determine whether a load postincrement is a good
- thing to use for a given mode.  Defaults to the value of
---- a/src/gcc/doc/invoke.texi
-+++ b/src/gcc/doc/invoke.texi
-@@ -10145,6 +10145,18 @@
- E.g. to disable inline code use
- @option{--param asan-instrumentation-with-call-threshold=0}.
- 
-+@item max-fsm-thread-path-insns
-+Maximum number of instructions to copy when duplicating blocks on a
-+finite state automaton jump thread path.  The default is 100.
-+
-+@item max-fsm-thread-length
-+Maximum number of basic blocks on a finite state automaton jump thread
-+path.  The default is 10.
-+
-+@item max-fsm-thread-paths
-+Maximum number of new jump thread paths to create for a finite state
-+automaton.  The default is 50.
-+
- @end table
- @end table
- 
-@@ -11450,7 +11462,7 @@
- @opindex mtune
- Specify the name of the target processor for which GCC should tune the
- performance of the code.  Permissible values for this option are:
--@samp{generic}, @samp{cortex-a53}, @samp{cortex-a57}.
-+@samp{generic}, @samp{cortex-a53}, @samp{cortex-a57}, @samp{thunderx}.
- 
- Additionally, this option can specify that GCC should tune the performance
- of the code for a big.LITTLE system.  The only permissible value is
-@@ -12324,7 +12336,8 @@
- @samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8}, @samp{cortex-a9},
- @samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a53}, @samp{cortex-a57},
- @samp{cortex-r4},
--@samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-m4},
-+@samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-m7},
-+@samp{cortex-m4},
- @samp{cortex-m3},
- @samp{cortex-m1},
- @samp{cortex-m0},
-@@ -12378,6 +12391,7 @@
- @samp{vfpv3-fp16}, @samp{vfpv3-d16}, @samp{vfpv3-d16-fp16}, @samp{vfpv3xd},
- @samp{vfpv3xd-fp16}, @samp{neon}, @samp{neon-fp16}, @samp{vfpv4},
- @samp{vfpv4-d16}, @samp{fpv4-sp-d16}, @samp{neon-vfpv4},
-+@samp{fpv5-d16}, @samp{fpv5-sp-d16},
- @samp{fp-armv8}, @samp{neon-fp-armv8}, and @samp{crypto-neon-fp-armv8}.
- 
- If @option{-msoft-float} is specified this specifies the format of
---- a/src/gcc/doc/md.texi
-+++ b/src/gcc/doc/md.texi
-@@ -5319,10 +5319,18 @@
- The @code{ffs} built-in function of C always uses the mode which
- corresponds to the C data type @code{int}.
- 
-+@cindex @code{clrsb@var{m}2} instruction pattern
-+@item @samp{clrsb@var{m}2}
-+Count leading redundant sign bits.
-+Store into operand 0 the number of redundant sign bits in operand 1, starting
-+at the most significant bit position.
-+A redundant sign bit is defined as any sign bit after the first. As such,
-+this count will be one less than the count of leading sign bits.
-+
- @cindex @code{clz@var{m}2} instruction pattern
- @item @samp{clz@var{m}2}
--Store into operand 0 the number of leading 0-bits in @var{x}, starting
--at the most significant bit position.  If @var{x} is 0, the
-+Store into operand 0 the number of leading 0-bits in operand 1, starting
-+at the most significant bit position.  If operand 1 is 0, the
- @code{CLZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
- the result is undefined or has a useful value.
- @var{m} is the mode of operand 0; operand 1's mode is
-@@ -5331,8 +5339,8 @@
- 
- @cindex @code{ctz@var{m}2} instruction pattern
- @item @samp{ctz@var{m}2}
--Store into operand 0 the number of trailing 0-bits in @var{x}, starting
--at the least significant bit position.  If @var{x} is 0, the
-+Store into operand 0 the number of trailing 0-bits in operand 1, starting
-+at the least significant bit position.  If operand 1 is 0, the
- @code{CTZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
- the result is undefined or has a useful value.
- @var{m} is the mode of operand 0; operand 1's mode is
-@@ -5341,7 +5349,7 @@
- 
- @cindex @code{popcount@var{m}2} instruction pattern
- @item @samp{popcount@var{m}2}
--Store into operand 0 the number of 1-bits in @var{x}.  @var{m} is the
-+Store into operand 0 the number of 1-bits in operand 1.  @var{m} is the
- mode of operand 0; operand 1's mode is specified by the instruction
- pattern, and the compiler will convert the operand to that mode before
- generating the instruction.
-@@ -5348,8 +5356,8 @@
- 
- @cindex @code{parity@var{m}2} instruction pattern
- @item @samp{parity@var{m}2}
--Store into operand 0 the parity of @var{x}, i.e.@: the number of 1-bits
--in @var{x} modulo 2.  @var{m} is the mode of operand 0; operand 1's mode
-+Store into operand 0 the parity of operand 1, i.e.@: the number of 1-bits
-+in operand 1 modulo 2.  @var{m} is the mode of operand 0; operand 1's mode
- is specified by the instruction pattern, and the compiler will convert
- the operand to that mode before generating the instruction.
- 
diff --git a/debian/patches/gcc-linaro.diff b/debian/patches/gcc-linaro.diff
index e7d7c84..b363b1f 100644
--- a/debian/patches/gcc-linaro.diff
+++ b/debian/patches/gcc-linaro.diff
@@ -1,48934 +1,6 @@
-# DP: Changes for the Linaro 4.9-2015.01 release.
+# DP: Changes for the Linaro 5-2015.xx release.
 
-LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@219502 \
-    svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@219643 \
+LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-5-branch@219502 \
+    svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-5-branch@219643 \
  | filterdiff --remove-timestamps --addoldprefix=a/src/ --addnewprefix=b/src/
 
---- a/src/libitm/ChangeLog.linaro
-+++ b/src/libitm/ChangeLog.linaro
-@@ -0,0 +1,68 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-10-03  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r213035.
-+	2014-07-24  Richard Henderson  <rth@redhat.com>
-+
-+	* config/aarch64/sjlj.S (_ITM_beginTransaction): Use post-inc
-+	addressing mode in epilogue.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-26  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r210615.
-+	2014-05-19  Richard Henderson  <rth@redhat.com>
-+
-+	* config/aarch64/sjlj.S: New file.
-+	* config/aarch64/target.h: New file.
-+	* configure.tgt: Enable aarch64.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/libgomp/ChangeLog.linaro
-+++ b/src/libgomp/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/libquadmath/ChangeLog.linaro
-+++ b/src/libquadmath/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/libsanitizer/ChangeLog.linaro
-+++ b/src/libsanitizer/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/zlib/ChangeLog.linaro
-+++ b/src/zlib/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/libstdc++-v3/ChangeLog.linaro
-+++ b/src/libstdc++-v3/ChangeLog.linaro
-@@ -0,0 +1,70 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r216444.
-+	2014-10-19  Maxim Kuvyrkov  <maxim.kuvyrkov@linaro.org>
-+
-+	* testsuite/lib/libstdc++.exp (v3-copy-file): New proc split from ...
-+	(v3-copy-files): ... this.  Update.
-+	(check_v3_target_fileio): Fix race on cin_unget-1.txt file.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-10-06  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215101.
-+	2014-09-10  Tony Wang  <tony.wang@arm.com>
-+
-+	PR target/56846
-+	* libsupc++/eh_personality.cc (PERSONALITY_FUNCTION):
-+	Return with CONTINUE_UNWINDING when the state pattern
-+	contains: _US_VIRTUAL_UNWIND_FRAME | _US_FORCE_UNWIND
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/libstdc++-v3/testsuite/lib/libstdc++.exp
-+++ b/src/libstdc++-v3/testsuite/lib/libstdc++.exp
-@@ -63,19 +63,24 @@
-     verbose "++ $var is $val" $n
- }
- 
-+# Copy file to the target.
-+proc v3-copy-file {src dst} {
-+    if { [catch { set symlink [file readlink $src] } x] } then {
-+	remote_download target $src $dst
-+    } else {
-+	if { [regexp "^/" "$symlink"] } then {
-+	    remote_download target $symlink $dst
-+	} else {
-+	    set dirname [file dirname $f]
-+	    remote_download target $dirname/$symlink $dst
-+	}
-+    }
-+}
-+
- # Called by v3-init below.  "Static" to this file.
- proc v3-copy-files {srcfiles} {
-     foreach f $srcfiles {
--        if { [catch { set symlink [file readlink $f] } x] } then {
--	    remote_download target $f
--        } else {
--            if { [regexp "^/" "$symlink"] } then {
--		remote_download target $symlink
--            } else {
--                set dirname [file dirname $f]
--		remote_download target $dirname/$symlink
--            }
--        }
-+	v3-copy-file $f [file tail $f]
-     }
- }
- 
-@@ -681,8 +686,8 @@
- 	# the file functions
- 	set src fileio[pid].cc
- 	set exe fileio[pid].x
--	set testfile "cin_unget-1.txt"
--	v3-copy-files "$srcdir/data/$testfile"
-+	set testfile "cin_unget-1.[pid].txt"
-+	v3-copy-file "$srcdir/data/cin_unget-1.txt" "$testfile"
- 
- 	set f [open $src "w"]
- 	puts $f "#include <sys/types.h>"
---- a/src/configure.ac
-+++ b/src/configure.ac
-@@ -331,7 +331,8 @@
-     if test "$is_elf" = "yes"; then
-       # Check for target supported by gold.
-       case "${target}" in
--        i?86-*-* | x86_64-*-* | sparc*-*-* | powerpc*-*-* | arm*-*-* | tilegx*-*-*)
-+        i?86-*-* | x86_64-*-* | sparc*-*-* | powerpc*-*-* | arm*-*-* \
-+        | aarch64*-*-* | tilegx*-*-*)
- 	  configdirs="$configdirs gold"
- 	  if test x${ENABLE_GOLD} = xdefault; then
- 	    default_ld=gold
---- a/src/intl/ChangeLog.linaro
-+++ b/src/intl/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/ChangeLog.linaro
-+++ b/src/ChangeLog.linaro
-@@ -0,0 +1,59 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215865.
-+	2014-10-03  Jing Yu  <jingyu@google.com>
-+
-+	* configure.ac: Add aarch64 to list of targets that support gold.
-+	* configure: Regenerate.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/boehm-gc/ChangeLog.linaro
-+++ b/src/boehm-gc/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/include/ChangeLog.linaro
-+++ b/src/include/ChangeLog.linaro
-@@ -0,0 +1,58 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-23  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209649.
-+	2014-04-22  Yufeng Zhang  <yufeng.zhang@arm.com>
-+
-+	* longlong.h: Merge from glibc.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/include/longlong.h
-+++ b/src/include/longlong.h
-@@ -1,5 +1,5 @@
- /* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
--   Copyright (C) 1991-2013 Free Software Foundation, Inc.
-+   Copyright (C) 1991-2014 Free Software Foundation, Inc.
- 
-    This file is part of the GNU C Library.
- 
-@@ -122,6 +122,22 @@
- #define __AND_CLOBBER_CC , "cc"
- #endif /* __GNUC__ < 2 */
- 
-+#if defined (__aarch64__)
-+
-+#if W_TYPE_SIZE == 32
-+#define count_leading_zeros(COUNT, X)	((COUNT) = __builtin_clz (X))
-+#define count_trailing_zeros(COUNT, X)   ((COUNT) = __builtin_ctz (X))
-+#define COUNT_LEADING_ZEROS_0 32
-+#endif /* W_TYPE_SIZE == 32 */
-+
-+#if W_TYPE_SIZE == 64
-+#define count_leading_zeros(COUNT, X)	((COUNT) = __builtin_clzll (X))
-+#define count_trailing_zeros(COUNT, X)   ((COUNT) = __builtin_ctzll (X))
-+#define COUNT_LEADING_ZEROS_0 64
-+#endif /* W_TYPE_SIZE == 64 */
-+
-+#endif /* __aarch64__ */
-+
- #if defined (__alpha) && W_TYPE_SIZE == 64
- #define umul_ppmm(ph, pl, m0, m1) \
-   do {									\
---- a/src/libiberty/ChangeLog.linaro
-+++ b/src/libiberty/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/lto-plugin/ChangeLog.linaro
-+++ b/src/lto-plugin/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/contrib/regression/ChangeLog.linaro
-+++ b/src/contrib/regression/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/contrib/ChangeLog.linaro
-+++ b/src/contrib/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/contrib/reghunt/ChangeLog.linaro
-+++ b/src/contrib/reghunt/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/libatomic/ChangeLog.linaro
-+++ b/src/libatomic/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/config/ChangeLog.linaro
-+++ b/src/config/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/libbacktrace/ChangeLog.linaro
-+++ b/src/libbacktrace/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/libjava/libltdl/ChangeLog.linaro
-+++ b/src/libjava/libltdl/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/libjava/ChangeLog.linaro
-+++ b/src/libjava/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/libjava/classpath/ChangeLog.linaro
-+++ b/src/libjava/classpath/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/gnattools/ChangeLog.linaro
-+++ b/src/gnattools/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/maintainer-scripts/ChangeLog.linaro
-+++ b/src/maintainer-scripts/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/configure
-+++ b/src/configure
-@@ -2971,7 +2971,8 @@
-     if test "$is_elf" = "yes"; then
-       # Check for target supported by gold.
-       case "${target}" in
--        i?86-*-* | x86_64-*-* | sparc*-*-* | powerpc*-*-* | arm*-*-* | tilegx*-*-*)
-+        i?86-*-* | x86_64-*-* | sparc*-*-* | powerpc*-*-* | arm*-*-* \
-+        | aarch64*-*-* | tilegx*-*-*)
- 	  configdirs="$configdirs gold"
- 	  if test x${ENABLE_GOLD} = xdefault; then
- 	    default_ld=gold
---- a/src/libgcc/config.host
-+++ b/src/libgcc/config.host
-@@ -316,13 +316,15 @@
- case ${host} in
- aarch64*-*-elf)
- 	extra_parts="$extra_parts crtbegin.o crtend.o crti.o crtn.o"
-+	extra_parts="$extra_parts crtfastmath.o"
- 	tmake_file="${tmake_file} ${cpu_type}/t-aarch64"
--	tmake_file="${tmake_file} ${cpu_type}/t-softfp t-softfp"
-+	tmake_file="${tmake_file} ${cpu_type}/t-softfp t-softfp t-crtfm"
- 	;;
- aarch64*-*-linux*)
-+	extra_parts="$extra_parts crtfastmath.o"
- 	md_unwind_header=aarch64/linux-unwind.h
- 	tmake_file="${tmake_file} ${cpu_type}/t-aarch64"
--	tmake_file="${tmake_file} ${cpu_type}/t-softfp t-softfp"
-+	tmake_file="${tmake_file} ${cpu_type}/t-softfp t-softfp t-crtfm"
- 	;;
- alpha*-*-linux*)
- 	tmake_file="${tmake_file} alpha/t-alpha alpha/t-ieee t-crtfm alpha/t-linux"
---- a/src/libgcc/ChangeLog.linaro
-+++ b/src/libgcc/ChangeLog.linaro
-@@ -0,0 +1,69 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215013.
-+	2014-09-08  Joseph Myers  <joseph@codesourcery.com>
-+
-+	* fp-bit.c (pack_d, unpack_d): Remove LARGEST_EXPONENT_IS_NORMAL
-+	and ROUND_TOWARDS_ZERO conditionals.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-10-06  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215086.
-+	2014-09-09  Marcus Shawcroft  <marcus.shawcroft@arm.com>
-+	Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
-+
-+	* config.host (aarch64*): Include crtfastmath.o and
-+	t-crtfm.
-+	* config/aarch64/crtfastmath.c: New file.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/libgcc/config/aarch64/crtfastmath.c
-+++ b/src/libgcc/config/aarch64/crtfastmath.c
-@@ -0,0 +1,36 @@
-+/*
-+ * Copyright (C) 2014 Free Software Foundation, Inc.
-+ *
-+ * This file is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 3, or (at your option) any
-+ * later version.
-+ *
-+ * This file is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ *
-+ * Under Section 7 of GPL version 3, you are granted additional
-+ * permissions described in the GCC Runtime Library Exception, version
-+ * 3.1, as published by the Free Software Foundation.
-+ *
-+ * You should have received a copy of the GNU General Public License and
-+ * a copy of the GCC Runtime Library Exception along with this program;
-+ * see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
-+ * <http://www.gnu.org/licenses/>.
-+ */
-+
-+#define _FPU_FPCR_FZ 0x1000000
-+
-+#define _FPU_SETCW(fpcr)				   \
-+  {							   \
-+    __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (fpcr)); \
-+  }
-+
-+static void __attribute__((constructor))
-+set_fast_math (void)
-+{
-+  /* Flush to zero, round to nearest, IEEE exceptions disabled.  */
-+  _FPU_SETCW (_FPU_FPCR_FZ);
-+}
---- a/src/libgcc/config/arm/bpabi-v6m.S
-+++ b/src/libgcc/config/arm/bpabi-v6m.S
-@@ -148,7 +148,7 @@
- 	mov r0, sp
- 	push {r0, lr}
- 	ldr r0, [sp, #8]
--	bl SYM(__gnu_uldivmod_helper)
-+	bl SYM(__udivmoddi4)
- 	ldr r3, [sp, #4]
- 	mov lr, r3
- 	add sp, sp, #8
---- a/src/libgcc/config/arm/bpabi.c
-+++ b/src/libgcc/config/arm/bpabi.c
-@@ -26,9 +26,6 @@
- extern unsigned long long __udivdi3 (unsigned long long, 
- 				     unsigned long long);
- extern long long __gnu_ldivmod_helper (long long, long long, long long *);
--extern unsigned long long __gnu_uldivmod_helper (unsigned long long, 
--						 unsigned long long, 
--						 unsigned long long *);
- 
- 
- long long
-@@ -43,14 +40,3 @@
-   return quotient;
- }
- 
--unsigned long long
--__gnu_uldivmod_helper (unsigned long long a, 
--		       unsigned long long b,
--		       unsigned long long *remainder)
--{
--  unsigned long long quotient;
--
--  quotient = __udivdi3 (a, b);
--  *remainder = a - b * quotient;
--  return quotient;
--}
---- a/src/libgcc/config/arm/bpabi.S
-+++ b/src/libgcc/config/arm/bpabi.S
-@@ -22,6 +22,8 @@
-    see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
-    <http://www.gnu.org/licenses/>.  */
- 
-+	.cfi_sections .debug_frame
-+
- #ifdef __ARM_EABI__
- /* Some attributes that are common to all routines in this file.  */
- 	/* Tag_ABI_align_needed: This code does not require 8-byte
-@@ -120,49 +122,137 @@
- #endif
- .endm
- 
-+/* we can use STRD/LDRD on v5TE and later, and any Thumb-2 architecture. */
-+#if (defined(__ARM_EABI__)                                            \
-+     && (defined(__thumb2__)                                          \
-+         || (__ARM_ARCH >= 5 && defined(__TARGET_FEATURE_DSP))))
-+#define CAN_USE_LDRD 1
-+#else
-+#define CAN_USE_LDRD 0
-+#endif
-+
-+/* set up stack from for call to __udivmoddi4. At the end of the macro the
-+   stack is arranged as follows:
-+		sp+12	/ space for remainder
-+		sp+8	\ (written by __udivmoddi4)
-+		sp+4	lr
-+		sp+0	sp+8 [rp (remainder pointer) argument for __udivmoddi4]
-+
-+ */
-+.macro push_for_divide fname
-+#if defined(__thumb2__) && CAN_USE_LDRD
-+	sub	ip, sp, #8
-+	strd	ip, lr, [sp, #-16]!
-+#else
-+	sub	sp, sp, #8
-+	do_push	{sp, lr}
-+#endif
-+	.cfi_adjust_cfa_offset 16
-+	.cfi_offset 14, -12
-+.endm
-+
-+/* restore stack */
-+.macro pop_for_divide
-+	ldr	lr, [sp, #4]
-+#if CAN_USE_LDRD
-+	ldrd	r2, r3, [sp, #8]
-+	add	sp, sp, #16
-+#else
-+	add	sp, sp, #8
-+	do_pop	{r2, r3}
-+#endif
-+	.cfi_restore 14
-+	.cfi_adjust_cfa_offset 0
-+.endm
-+
- #ifdef L_aeabi_ldivmod
- 
-+/* Perform 64 bit signed division.
-+   Inputs:
-+	r0:r1	numerator
-+	r2:r3	denominator
-+   Outputs:
-+	r0:r1	quotient
-+	r2:r3	remainder
-+ */
- ARM_FUNC_START aeabi_ldivmod
--	cfi_start	__aeabi_ldivmod, LSYM(Lend_aeabi_ldivmod)
--	test_div_by_zero signed
-+	.cfi_startproc
-+	test_div_by_zero	signed
- 
--	sub sp, sp, #8
--#if defined(__thumb2__)
--	mov ip, sp
--	push {ip, lr}
--#else
--	do_push {sp, lr}
--#endif
--98:	cfi_push 98b - __aeabi_ldivmod, 0xe, -0xc, 0x10
--	bl SYM(__gnu_ldivmod_helper) __PLT__
--	ldr lr, [sp, #4]
--	add sp, sp, #8
--	do_pop {r2, r3}
-+	push_for_divide	__aeabi_ldivmod
-+	cmp	xxh, #0
-+	blt	1f
-+	cmp	yyh, #0
-+	blt	2f
-+	/* arguments in (r0:r1), (r2:r3) and *sp */
-+	bl	SYM(__udivmoddi4) __PLT__
-+	.cfi_remember_state
-+	pop_for_divide
- 	RET
--	cfi_end	LSYM(Lend_aeabi_ldivmod)
-+
-+1: /* xxh:xxl is negative */
-+	.cfi_restore_state
-+	negs	xxl, xxl
-+	sbc	xxh, xxh, xxh, lsl #1	/* Thumb-2 has no RSC, so use X - 2X */
-+	cmp	yyh, #0
-+	blt	3f
-+	/* arguments in (r0:r1), (r2:r3) and *sp */
-+	bl	SYM(__udivmoddi4) __PLT__
-+	.cfi_remember_state
-+	pop_for_divide
-+	negs	xxl, xxl
-+	sbc	xxh, xxh, xxh, lsl #1	/* Thumb-2 has no RSC, so use X - 2X */
-+	negs	yyl, yyl
-+	sbc	yyh, yyh, yyh, lsl #1	/* Thumb-2 has no RSC, so use X - 2X */
-+	RET
-+
-+2: /* only yyh:yyl is negative */
-+	.cfi_restore_state
-+	negs	yyl, yyl
-+	sbc	yyh, yyh, yyh, lsl #1	/* Thumb-2 has no RSC, so use X - 2X */
-+	/* arguments in (r0:r1), (r2:r3) and *sp */
-+	bl	SYM(__udivmoddi4) __PLT__
-+	.cfi_remember_state
-+	pop_for_divide
-+	negs	xxl, xxl
-+	sbc	xxh, xxh, xxh, lsl #1	/* Thumb-2 has no RSC, so use X - 2X */
-+	RET
-+
-+3: /* both xxh:xxl and yyh:yyl are negative */
-+	.cfi_restore_state
-+	negs	yyl, yyl
-+	sbc	yyh, yyh, yyh, lsl #1	/* Thumb-2 has no RSC, so use X - 2X */
-+	/* arguments in (r0:r1), (r2:r3) and *sp */
-+	bl	SYM(__udivmoddi4) __PLT__
-+	pop_for_divide
-+	negs	yyl, yyl
-+	sbc	yyh, yyh, yyh, lsl #1	/* Thumb-2 has no RSC, so use X - 2X */
-+	RET
-+
-+	.cfi_endproc
- 	
- #endif /* L_aeabi_ldivmod */
- 
- #ifdef L_aeabi_uldivmod
- 
-+/* Perform 64 bit signed division.
-+   Inputs:
-+	r0:r1	numerator
-+	r2:r3	denominator
-+   Outputs:
-+	r0:r1	quotient
-+	r2:r3	remainder
-+ */
- ARM_FUNC_START aeabi_uldivmod
--	cfi_start	__aeabi_uldivmod, LSYM(Lend_aeabi_uldivmod)
--	test_div_by_zero unsigned
-+	.cfi_startproc
-+	test_div_by_zero	unsigned
- 
--	sub sp, sp, #8
--#if defined(__thumb2__)
--	mov ip, sp
--	push {ip, lr}
--#else
--	do_push {sp, lr}
--#endif
--98:	cfi_push 98b - __aeabi_uldivmod, 0xe, -0xc, 0x10
--	bl SYM(__gnu_uldivmod_helper) __PLT__
--	ldr lr, [sp, #4]
--	add sp, sp, #8
--	do_pop {r2, r3}
-+	push_for_divide	__aeabi_uldivmod
-+	/* arguments in (r0:r1), (r2:r3) and *sp */
-+	bl	SYM(__udivmoddi4) __PLT__
-+	pop_for_divide
- 	RET
--	cfi_end	LSYM(Lend_aeabi_uldivmod)
-+	.cfi_endproc
- 
- #endif /* L_aeabi_divmod */
- 	
---- a/src/libgcc/config/libbid/ChangeLog.linaro
-+++ b/src/libgcc/config/libbid/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/libgcc/fp-bit.c
-+++ b/src/libgcc/fp-bit.c
-@@ -202,17 +202,9 @@
-   int sign = src->sign;
-   int exp = 0;
- 
--  if (LARGEST_EXPONENT_IS_NORMAL (FRAC_NBITS) && (isnan (src) || isinf (src)))
-+  if (isnan (src))
-     {
--      /* We can't represent these values accurately.  By using the
--	 largest possible magnitude, we guarantee that the conversion
--	 of infinity is at least as big as any finite number.  */
-       exp = EXPMAX;
--      fraction = ((fractype) 1 << FRACBITS) - 1;
--    }
--  else if (isnan (src))
--    {
--      exp = EXPMAX;
-       /* Restore the NaN's payload.  */
-       fraction >>= NGARDS;
-       fraction &= QUIET_NAN - 1;
-@@ -291,8 +283,7 @@
- 	  fraction >>= NGARDS;
- #endif /* NO_DENORMALS */
- 	}
--      else if (!LARGEST_EXPONENT_IS_NORMAL (FRAC_NBITS)
--	       && __builtin_expect (src->normal_exp > EXPBIAS, 0))
-+      else if (__builtin_expect (src->normal_exp > EXPBIAS, 0))
- 	{
- 	  exp = EXPMAX;
- 	  fraction = 0;
-@@ -300,35 +291,25 @@
-       else
- 	{
- 	  exp = src->normal_exp + EXPBIAS;
--	  if (!ROUND_TOWARDS_ZERO)
-+	  /* IF the gard bits are the all zero, but the first, then we're
-+	     half way between two numbers, choose the one which makes the
-+	     lsb of the answer 0.  */
-+	  if ((fraction & GARDMASK) == GARDMSB)
- 	    {
--	      /* IF the gard bits are the all zero, but the first, then we're
--		 half way between two numbers, choose the one which makes the
--		 lsb of the answer 0.  */
--	      if ((fraction & GARDMASK) == GARDMSB)
--		{
--		  if (fraction & (1 << NGARDS))
--		    fraction += GARDROUND + 1;
--		}
--	      else
--		{
--		  /* Add a one to the guards to round up */
--		  fraction += GARDROUND;
--		}
--	      if (fraction >= IMPLICIT_2)
--		{
--		  fraction >>= 1;
--		  exp += 1;
--		}
-+	      if (fraction & (1 << NGARDS))
-+		fraction += GARDROUND + 1;
- 	    }
--	  fraction >>= NGARDS;
--
--	  if (LARGEST_EXPONENT_IS_NORMAL (FRAC_NBITS) && exp > EXPMAX)
-+	  else
- 	    {
--	      /* Saturate on overflow.  */
--	      exp = EXPMAX;
--	      fraction = ((fractype) 1 << FRACBITS) - 1;
-+	      /* Add a one to the guards to round up */
-+	      fraction += GARDROUND;
- 	    }
-+	  if (fraction >= IMPLICIT_2)
-+	    {
-+	      fraction >>= 1;
-+	      exp += 1;
-+	    }
-+	  fraction >>= NGARDS;
- 	}
-     }
- 
-@@ -556,8 +537,7 @@
- 	  dst->fraction.ll = fraction;
- 	}
-     }
--  else if (!LARGEST_EXPONENT_IS_NORMAL (FRAC_NBITS)
--	   && __builtin_expect (exp == EXPMAX, 0))
-+  else if (__builtin_expect (exp == EXPMAX, 0))
-     {
-       /* Huge exponent*/
-       if (fraction == 0)
-@@ -915,7 +895,7 @@
-       low <<= 1;
-     }
- 
--  if (!ROUND_TOWARDS_ZERO && (high & GARDMASK) == GARDMSB)
-+  if ((high & GARDMASK) == GARDMSB)
-     {
-       if (high & (1 << NGARDS))
- 	{
-@@ -1035,7 +1015,7 @@
- 	numerator *= 2;
-       }
- 
--    if (!ROUND_TOWARDS_ZERO && (quotient & GARDMASK) == GARDMSB)
-+    if ((quotient & GARDMASK) == GARDMSB)
-       {
- 	if (quotient & (1 << NGARDS))
- 	  {
---- a/src/libdecnumber/ChangeLog.linaro
-+++ b/src/libdecnumber/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/gcc/LINARO-VERSION
-+++ b/src/gcc/LINARO-VERSION
-@@ -0,0 +1 @@
-+4.9-2015.01
---- a/src/gcc/ira-conflicts.c
-+++ b/src/gcc/ira-conflicts.c
-@@ -774,6 +774,27 @@
- 				temp_hard_reg_set);
- 	    }
- 
-+	  /* Now we deal with paradoxical subreg cases where certain registers
-+	     cannot be accessed in the widest mode.  */
-+	  enum machine_mode outer_mode = ALLOCNO_WMODE (a);
-+	  enum machine_mode inner_mode = ALLOCNO_MODE (a);
-+	  if (GET_MODE_SIZE (outer_mode) > GET_MODE_SIZE (inner_mode))
-+	    {
-+	      enum reg_class aclass = ALLOCNO_CLASS (a);
-+	      for (int j = ira_class_hard_regs_num[aclass] - 1; j >= 0; --j)
-+		{
-+		   int inner_regno = ira_class_hard_regs[aclass][j];
-+		   int outer_regno = simplify_subreg_regno (inner_regno,
-+							    inner_mode, 0,
-+							    outer_mode);
-+		   if (outer_regno < 0
-+		       || !in_hard_reg_set_p (reg_class_contents[aclass],
-+					      outer_mode, outer_regno))
-+		     SET_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj),
-+				       inner_regno);
-+		}
-+	    }
-+
- 	  if (ALLOCNO_CALLS_CROSSED_NUM (a) != 0)
- 	    {
- 	      int regno;
---- a/src/gcc/targhooks.c
-+++ b/src/gcc/targhooks.c
-@@ -1357,7 +1357,62 @@
- #endif
- }
- 
-+/* For hooks which use the MOVE_RATIO macro, this gives the legacy default
-+   behaviour.  SPEED_P is true if we are compiling for speed.  */
-+
-+static unsigned int
-+get_move_ratio (bool speed_p ATTRIBUTE_UNUSED)
-+{
-+  unsigned int move_ratio;
-+#ifdef MOVE_RATIO
-+  move_ratio = (unsigned int) MOVE_RATIO (speed_p);
-+#else
-+#if defined (HAVE_movmemqi) || defined (HAVE_movmemhi) || defined (HAVE_movmemsi) || defined (HAVE_movmemdi) || defined (HAVE_movmemti)
-+  move_ratio = 2;
-+#else /* No movmem patterns, pick a default.  */
-+  move_ratio = ((speed_p) ? 15 : 3);
-+#endif
-+#endif
-+  return move_ratio;
-+}
-+
-+/* Return TRUE if the move_by_pieces/set_by_pieces infrastructure should be
-+   used; return FALSE if the movmem/setmem optab should be expanded, or
-+   a call to memcpy emitted.  */
-+
- bool
-+default_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size,
-+					unsigned int alignment,
-+					enum by_pieces_operation op,
-+					bool speed_p)
-+{
-+  unsigned int max_size = 0;
-+  unsigned int ratio = 0;
-+
-+  switch (op)
-+    {
-+      case CLEAR_BY_PIECES:
-+	max_size = STORE_MAX_PIECES;
-+	ratio = CLEAR_RATIO (speed_p);
-+	break;
-+      case MOVE_BY_PIECES:
-+	max_size = MOVE_MAX_PIECES;
-+	ratio = get_move_ratio (speed_p);
-+	break;
-+      case SET_BY_PIECES:
-+	max_size = STORE_MAX_PIECES;
-+	ratio = SET_RATIO (speed_p);
-+	break;
-+      case STORE_BY_PIECES:
-+	max_size = STORE_MAX_PIECES;
-+	ratio = get_move_ratio (speed_p);
-+	break;
-+    }
-+
-+  return move_by_pieces_ninsns (size, alignment, max_size + 1) < ratio;
-+}
-+
-+bool
- default_profile_before_prologue (void)
- {
- #ifdef PROFILE_BEFORE_PROLOGUE
---- a/src/gcc/targhooks.h
-+++ b/src/gcc/targhooks.h
-@@ -177,6 +177,11 @@
- extern int default_register_move_cost (enum machine_mode, reg_class_t,
- 				       reg_class_t);
- 
-+extern bool default_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT,
-+						    unsigned int,
-+						    enum by_pieces_operation,
-+						    bool);
-+
- extern bool default_profile_before_prologue (void);
- extern reg_class_t default_preferred_reload_class (rtx, reg_class_t);
- extern reg_class_t default_preferred_output_reload_class (rtx, reg_class_t);
---- a/src/gcc/cppbuiltin.c
-+++ b/src/gcc/cppbuiltin.c
-@@ -53,18 +53,41 @@
-     *patchlevel = s_patchlevel;
- }
- 
-+/* Parse a LINAROVER version string of the format "M.m-year.month[-spin][~dev]"
-+   to create Linaro release number YYYYMM and spin version.  */
-+static void
-+parse_linarover (int *release, int *spin)
-+{
-+  static int s_year = -1, s_month, s_spin;
- 
-+  if (s_year == -1)
-+    if (sscanf (LINAROVER, "%*[^-]-%d.%d-%d", &s_year, &s_month, &s_spin) != 3)
-+      {
-+	sscanf (LINAROVER, "%*[^-]-%d.%d", &s_year, &s_month);
-+	s_spin = 0;
-+      }
-+
-+  if (release)
-+    *release = s_year * 100 + s_month;
-+
-+  if (spin)
-+    *spin = s_spin;
-+}
-+
- /* Define __GNUC__, __GNUC_MINOR__, __GNUC_PATCHLEVEL__ and __VERSION__.  */
- static void
- define__GNUC__ (cpp_reader *pfile)
- {
--  int major, minor, patchlevel;
-+  int major, minor, patchlevel, linaro_release, linaro_spin;
- 
-   parse_basever (&major, &minor, &patchlevel);
-+  parse_linarover (&linaro_release, &linaro_spin);
-   cpp_define_formatted (pfile, "__GNUC__=%d", major);
-   cpp_define_formatted (pfile, "__GNUC_MINOR__=%d", minor);
-   cpp_define_formatted (pfile, "__GNUC_PATCHLEVEL__=%d", patchlevel);
-   cpp_define_formatted (pfile, "__VERSION__=\"%s\"", version_string);
-+  cpp_define_formatted (pfile, "__LINARO_RELEASE__=%d", linaro_release);
-+  cpp_define_formatted (pfile, "__LINARO_SPIN__=%d", linaro_spin);
-   cpp_define_formatted (pfile, "__ATOMIC_RELAXED=%d", MEMMODEL_RELAXED);
-   cpp_define_formatted (pfile, "__ATOMIC_SEQ_CST=%d", MEMMODEL_SEQ_CST);
-   cpp_define_formatted (pfile, "__ATOMIC_ACQUIRE=%d", MEMMODEL_ACQUIRE);
---- a/src/gcc/tree-ssa-threadupdate.c
-+++ b/src/gcc/tree-ssa-threadupdate.c
-@@ -156,8 +156,9 @@
- 		       bool registering)
- {
-   fprintf (dump_file,
--	   "  %s jump thread: (%d, %d) incoming edge; ",
-+	   "  %s%s jump thread: (%d, %d) incoming edge; ",
- 	   (registering ? "Registering" : "Cancelling"),
-+	   (path[0]->type == EDGE_FSM_THREAD ? " FSM": ""),
- 	   path[0]->e->src->index, path[0]->e->dest->index);
- 
-   for (unsigned int i = 1; i < path.length (); i++)
-@@ -1622,6 +1623,155 @@
-   return false;
- }
- 
-+/* Verify that the REGION is a Single Entry Multiple Exits region: make sure no
-+   edge other than ENTRY is entering the REGION.  */
-+
-+DEBUG_FUNCTION void
-+verify_seme (edge entry, basic_block *region, unsigned n_region)
-+{
-+  bitmap bbs = BITMAP_ALLOC (NULL);
-+
-+  for (unsigned i = 0; i < n_region; i++)
-+    bitmap_set_bit (bbs, region[i]->index);
-+
-+  for (unsigned i = 0; i < n_region; i++)
-+    {
-+      edge e;
-+      edge_iterator ei;
-+      basic_block bb = region[i];
-+
-+      /* All predecessors other than ENTRY->src should be in the region.  */
-+      for (ei = ei_start (bb->preds); (e = ei_safe_edge (ei)); ei_next (&ei))
-+	if (e != entry)
-+	  gcc_assert (bitmap_bit_p (bbs, e->src->index));
-+    }
-+
-+  BITMAP_FREE (bbs);
-+}
-+
-+/* Duplicates a Single Entry Multiple Exit REGION (set of N_REGION basic
-+   blocks).  The ENTRY edge is redirected to the duplicate of the region.  If
-+   REGION is not a Single Entry region, ignore any incoming edges other than
-+   ENTRY: this makes the copied region a Single Entry region.
-+
-+   Remove the last conditional statement in the last basic block in the REGION,
-+   and create a single fallthru edge pointing to the same destination as the
-+   EXIT edge.
-+
-+   The new basic blocks are stored to REGION_COPY in the same order as they had
-+   in REGION, provided that REGION_COPY is not NULL.
-+
-+   Returns false if it is unable to copy the region, true otherwise.  */
-+
-+static bool
-+duplicate_seme_region (edge entry, edge exit,
-+		       basic_block *region, unsigned n_region,
-+		       basic_block *region_copy)
-+{
-+  unsigned i;
-+  bool free_region_copy = false, copying_header = false;
-+  struct loop *loop = entry->dest->loop_father;
-+  edge exit_copy;
-+  edge redirected;
-+  int total_freq = 0, entry_freq = 0;
-+  gcov_type total_count = 0, entry_count = 0;
-+
-+  if (!can_copy_bbs_p (region, n_region))
-+    return false;
-+
-+  /* Some sanity checking.  Note that we do not check for all possible
-+     missuses of the functions.  I.e. if you ask to copy something weird,
-+     it will work, but the state of structures probably will not be
-+     correct.  */
-+  for (i = 0; i < n_region; i++)
-+    {
-+      /* We do not handle subloops, i.e. all the blocks must belong to the
-+	 same loop.  */
-+      if (region[i]->loop_father != loop)
-+	return false;
-+    }
-+
-+  initialize_original_copy_tables ();
-+
-+  if (copying_header)
-+    set_loop_copy (loop, loop_outer (loop));
-+  else
-+    set_loop_copy (loop, loop);
-+
-+  if (!region_copy)
-+    {
-+      region_copy = XNEWVEC (basic_block, n_region);
-+      free_region_copy = true;
-+    }
-+
-+  if (entry->dest->count)
-+    {
-+      total_count = entry->dest->count;
-+      entry_count = entry->count;
-+      /* Fix up corner cases, to avoid division by zero or creation of negative
-+	 frequencies.  */
-+      if (entry_count > total_count)
-+	entry_count = total_count;
-+    }
-+  else
-+    {
-+      total_freq = entry->dest->frequency;
-+      entry_freq = EDGE_FREQUENCY (entry);
-+      /* Fix up corner cases, to avoid division by zero or creation of negative
-+	 frequencies.  */
-+      if (total_freq == 0)
-+	total_freq = 1;
-+      else if (entry_freq > total_freq)
-+	entry_freq = total_freq;
-+    }
-+
-+  copy_bbs (region, n_region, region_copy, &exit, 1, &exit_copy, loop,
-+	    split_edge_bb_loc (entry), 0);
-+  if (total_count)
-+    {
-+      scale_bbs_frequencies_gcov_type (region, n_region,
-+				       total_count - entry_count,
-+				       total_count);
-+      scale_bbs_frequencies_gcov_type (region_copy, n_region, entry_count,
-+				       total_count);
-+    }
-+  else
-+    {
-+      scale_bbs_frequencies_int (region, n_region, total_freq - entry_freq,
-+				 total_freq);
-+      scale_bbs_frequencies_int (region_copy, n_region, entry_freq, total_freq);
-+    }
-+
-+#ifdef ENABLE_CHECKING
-+  /* Make sure no edge other than ENTRY is entering the copied region.  */
-+  verify_seme (entry, region_copy, n_region);
-+#endif
-+
-+  /* Remove the last branch in the jump thread path.  */
-+  remove_ctrl_stmt_and_useless_edges (region_copy[n_region - 1], exit->dest);
-+  edge e = make_edge (region_copy[n_region - 1], exit->dest, EDGE_FALLTHRU);
-+
-+  if (e) {
-+    rescan_loop_exit (e, true, false);
-+    e->probability = REG_BR_PROB_BASE;
-+    e->count = region_copy[n_region - 1]->count;
-+  }
-+
-+  /* Redirect the entry and add the phi node arguments.  */
-+  redirected = redirect_edge_and_branch (entry, get_bb_copy (entry->dest));
-+  gcc_assert (redirected != NULL);
-+  flush_pending_stmts (entry);
-+
-+  /* Add the other PHI node arguments.  */
-+  add_phi_args_after_copy (region_copy, n_region, NULL);
-+
-+  if (free_region_copy)
-+    free (region_copy);
-+
-+  free_original_copy_tables ();
-+  return true;
-+}
-+
- /* Walk through all blocks and thread incoming edges to the appropriate
-    outgoing edge for each edge pair recorded in THREADED_EDGES.
- 
-@@ -1651,6 +1801,57 @@
-   threaded_blocks = BITMAP_ALLOC (NULL);
-   memset (&thread_stats, 0, sizeof (thread_stats));
- 
-+  /* Jump-thread all FSM threads before other jump-threads.  */
-+  for (i = 0; i < paths.length ();)
-+    {
-+      vec<jump_thread_edge *> *path = paths[i];
-+      edge entry = (*path)[0]->e;
-+
-+      if ((*path)[0]->type != EDGE_FSM_THREAD
-+	  /* Do not jump-thread twice from the same block.  */
-+	  || bitmap_bit_p (threaded_blocks, entry->src->index)) {
-+	i++;
-+	continue;
-+      }
-+
-+      unsigned len = path->length ();
-+      edge exit = (*path)[len - 1]->e;
-+      basic_block *region = XNEWVEC (basic_block, len - 1);
-+
-+      for (unsigned int j = 0; j < len - 1; j++)
-+	region[j] = (*path)[j]->e->dest;
-+
-+      if (duplicate_seme_region (entry, exit, region, len - 1, NULL))
-+	{
-+	  /* We do not update dominance info.  */
-+	  free_dominance_info (CDI_DOMINATORS);
-+	  bitmap_set_bit (threaded_blocks, entry->src->index);
-+	  retval = true;
-+	}
-+
-+      delete_jump_thread_path (path);
-+      paths.unordered_remove (i);
-+    }
-+
-+  /* Remove from PATHS all the jump-threads starting with an edge already
-+     jump-threaded.  */
-+  for (i = 0; i < paths.length ();)
-+    {
-+      vec<jump_thread_edge *> *path = paths[i];
-+      edge entry = (*path)[0]->e;
-+
-+      /* Do not jump-thread twice from the same block.  */
-+      if (bitmap_bit_p (threaded_blocks, entry->src->index))
-+	{
-+	  delete_jump_thread_path (path);
-+	  paths.unordered_remove (i);
-+	}
-+      else
-+	i++;
-+    }
-+
-+  bitmap_clear (threaded_blocks);
-+
-   mark_threaded_blocks (threaded_blocks);
- 
-   initialize_original_copy_tables ();
---- a/src/gcc/tree-ssa-threadupdate.h
-+++ b/src/gcc/tree-ssa-threadupdate.h
-@@ -26,6 +26,7 @@
- enum jump_thread_edge_type
- {
-   EDGE_START_JUMP_THREAD,
-+  EDGE_FSM_THREAD,
-   EDGE_COPY_SRC_BLOCK,
-   EDGE_COPY_SRC_JOINER_BLOCK,
-   EDGE_NO_COPY_SRC_BLOCK
---- a/src/gcc/c-family/ChangeLog.linaro
-+++ b/src/gcc/c-family/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/gcc/java/ChangeLog.linaro
-+++ b/src/gcc/java/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/gcc/c/c-parser.c
-+++ b/src/gcc/c/c-parser.c
-@@ -4210,7 +4210,8 @@
- 		  init.original_type = NULL;
- 		  c_parser_error (parser, "expected identifier");
- 		  c_parser_skip_until_found (parser, CPP_COMMA, NULL);
--		  process_init_element (init, false, braced_init_obstack);
-+		  process_init_element (input_location, init, false,
-+					braced_init_obstack);
- 		  return;
- 		}
- 	    }
-@@ -4342,7 +4343,8 @@
- 		  init.original_type = NULL;
- 		  c_parser_error (parser, "expected %<=%>");
- 		  c_parser_skip_until_found (parser, CPP_COMMA, NULL);
--		  process_init_element (init, false, braced_init_obstack);
-+		  process_init_element (input_location, init, false,
-+					braced_init_obstack);
- 		  return;
- 		}
- 	    }
-@@ -4363,11 +4365,12 @@
- {
-   struct c_expr init;
-   gcc_assert (!after || c_dialect_objc ());
-+  location_t loc = c_parser_peek_token (parser)->location;
-+
-   if (c_parser_next_token_is (parser, CPP_OPEN_BRACE) && !after)
-     init = c_parser_braced_init (parser, NULL_TREE, true);
-   else
-     {
--      location_t loc = c_parser_peek_token (parser)->location;
-       init = c_parser_expr_no_commas (parser, after);
-       if (init.value != NULL_TREE
- 	  && TREE_CODE (init.value) != STRING_CST
-@@ -4374,7 +4377,7 @@
- 	  && TREE_CODE (init.value) != COMPOUND_LITERAL_EXPR)
- 	init = convert_lvalue_to_rvalue (loc, init, true, true);
-     }
--  process_init_element (init, false, braced_init_obstack);
-+  process_init_element (loc, init, false, braced_init_obstack);
- }
- 
- /* Parse a compound statement (possibly a function body) (C90 6.6.2,
---- a/src/gcc/c/c-typeck.c
-+++ b/src/gcc/c/c-typeck.c
-@@ -102,8 +102,8 @@
- static char *print_spelling (char *);
- static void warning_init (int, const char *);
- static tree digest_init (location_t, tree, tree, tree, bool, bool, int);
--static void output_init_element (tree, tree, bool, tree, tree, int, bool,
--				 struct obstack *);
-+static void output_init_element (location_t, tree, tree, bool, tree, tree, int,
-+				 bool, struct obstack *);
- static void output_pending_init_elements (int, struct obstack *);
- static int set_designator (int, struct obstack *);
- static void push_range_stack (tree, struct obstack *);
-@@ -7187,13 +7187,15 @@
- 	  if ((TREE_CODE (constructor_type) == RECORD_TYPE
- 	       || TREE_CODE (constructor_type) == UNION_TYPE)
- 	      && constructor_fields == 0)
--	    process_init_element (pop_init_level (1, braced_init_obstack),
-+	    process_init_element (input_location,
-+				  pop_init_level (1, braced_init_obstack),
- 				  true, braced_init_obstack);
- 	  else if (TREE_CODE (constructor_type) == ARRAY_TYPE
- 		   && constructor_max_index
- 		   && tree_int_cst_lt (constructor_max_index,
- 				       constructor_index))
--	    process_init_element (pop_init_level (1, braced_init_obstack),
-+	    process_init_element (input_location,
-+				  pop_init_level (1, braced_init_obstack),
- 				  true, braced_init_obstack);
- 	  else
- 	    break;
-@@ -7393,10 +7395,9 @@
-       /* When we come to an explicit close brace,
- 	 pop any inner levels that didn't have explicit braces.  */
-       while (constructor_stack->implicit)
--	{
--	  process_init_element (pop_init_level (1, braced_init_obstack),
--				true, braced_init_obstack);
--	}
-+	process_init_element (input_location,
-+			      pop_init_level (1, braced_init_obstack),
-+			      true, braced_init_obstack);
-       gcc_assert (!constructor_range_stack);
-     }
- 
-@@ -7574,10 +7575,9 @@
-       /* Designator list starts at the level of closest explicit
- 	 braces.  */
-       while (constructor_stack->implicit)
--	{
--	  process_init_element (pop_init_level (1, braced_init_obstack),
--				true, braced_init_obstack);
--	}
-+	process_init_element (input_location,
-+			      pop_init_level (1, braced_init_obstack),
-+			      true, braced_init_obstack);
-       constructor_designated = 1;
-       return 0;
-     }
-@@ -8197,9 +8197,9 @@
-    existing initializer.  */
- 
- static void
--output_init_element (tree value, tree origtype, bool strict_string, tree type,
--		     tree field, int pending, bool implicit,
--		     struct obstack * braced_init_obstack)
-+output_init_element (location_t loc, tree value, tree origtype,
-+		     bool strict_string, tree type, tree field, int pending,
-+		     bool implicit, struct obstack * braced_init_obstack)
- {
-   tree semantic_type = NULL_TREE;
-   bool maybe_const = true;
-@@ -8297,8 +8297,8 @@
- 
-   if (semantic_type)
-     value = build1 (EXCESS_PRECISION_EXPR, semantic_type, value);
--  value = digest_init (input_location, type, value, origtype, npc,
--      		       strict_string, require_constant_value);
-+  value = digest_init (loc, type, value, origtype, npc, strict_string,
-+		       require_constant_value);
-   if (value == error_mark_node)
-     {
-       constructor_erroneous = 1;
-@@ -8425,8 +8425,8 @@
- 	{
- 	  if (tree_int_cst_equal (elt->purpose,
- 				  constructor_unfilled_index))
--	    output_init_element (elt->value, elt->origtype, true,
--				 TREE_TYPE (constructor_type),
-+	    output_init_element (input_location, elt->value, elt->origtype,
-+				 true, TREE_TYPE (constructor_type),
- 				 constructor_unfilled_index, 0, false,
- 				 braced_init_obstack);
- 	  else if (tree_int_cst_lt (constructor_unfilled_index,
-@@ -8480,8 +8480,8 @@
- 	  if (tree_int_cst_equal (elt_bitpos, ctor_unfilled_bitpos))
- 	    {
- 	      constructor_unfilled_fields = elt->purpose;
--	      output_init_element (elt->value, elt->origtype, true,
--				   TREE_TYPE (elt->purpose),
-+	      output_init_element (input_location, elt->value, elt->origtype,
-+				   true, TREE_TYPE (elt->purpose),
- 				   elt->purpose, 0, false,
- 				   braced_init_obstack);
- 	    }
-@@ -8554,7 +8554,7 @@
-    existing initializer.  */
- 
- void
--process_init_element (struct c_expr value, bool implicit,
-+process_init_element (location_t loc, struct c_expr value, bool implicit,
- 		      struct obstack * braced_init_obstack)
- {
-   tree orig_value = value.value;
-@@ -8598,7 +8598,7 @@
-       if ((TREE_CODE (constructor_type) == RECORD_TYPE
- 	   || TREE_CODE (constructor_type) == UNION_TYPE)
- 	  && constructor_fields == 0)
--	process_init_element (pop_init_level (1, braced_init_obstack),
-+	process_init_element (loc, pop_init_level (1, braced_init_obstack),
- 			      true, braced_init_obstack);
-       else if ((TREE_CODE (constructor_type) == ARRAY_TYPE
- 	        || TREE_CODE (constructor_type) == VECTOR_TYPE)
-@@ -8605,7 +8605,7 @@
- 	       && constructor_max_index
- 	       && tree_int_cst_lt (constructor_max_index,
- 				   constructor_index))
--	process_init_element (pop_init_level (1, braced_init_obstack),
-+	process_init_element (loc, pop_init_level (1, braced_init_obstack),
- 			      true, braced_init_obstack);
-       else
- 	break;
-@@ -8683,7 +8683,7 @@
- 	  if (value.value)
- 	    {
- 	      push_member_name (constructor_fields);
--	      output_init_element (value.value, value.original_type,
-+	      output_init_element (loc, value.value, value.original_type,
- 				   strict_string, fieldtype,
- 				   constructor_fields, 1, implicit,
- 				   braced_init_obstack);
-@@ -8775,7 +8775,7 @@
- 	  if (value.value)
- 	    {
- 	      push_member_name (constructor_fields);
--	      output_init_element (value.value, value.original_type,
-+	      output_init_element (loc, value.value, value.original_type,
- 				   strict_string, fieldtype,
- 				   constructor_fields, 1, implicit,
- 				   braced_init_obstack);
-@@ -8827,7 +8827,7 @@
- 	  if (value.value)
- 	    {
- 	      push_array_bounds (tree_to_uhwi (constructor_index));
--	      output_init_element (value.value, value.original_type,
-+	      output_init_element (loc, value.value, value.original_type,
- 				   strict_string, elttype,
- 				   constructor_index, 1, implicit,
- 				   braced_init_obstack);
-@@ -8862,7 +8862,7 @@
- 	    {
- 	      if (TREE_CODE (value.value) == VECTOR_CST)
- 		elttype = TYPE_MAIN_VARIANT (constructor_type);
--	      output_init_element (value.value, value.original_type,
-+	      output_init_element (loc, value.value, value.original_type,
- 				   strict_string, elttype,
- 				   constructor_index, 1, implicit,
- 				   braced_init_obstack);
-@@ -8891,7 +8891,7 @@
-       else
- 	{
- 	  if (value.value)
--	    output_init_element (value.value, value.original_type,
-+	    output_init_element (loc, value.value, value.original_type,
- 				 strict_string, constructor_type,
- 				 NULL_TREE, 1, implicit,
- 				 braced_init_obstack);
-@@ -8910,8 +8910,8 @@
- 	  while (constructor_stack != range_stack->stack)
- 	    {
- 	      gcc_assert (constructor_stack->implicit);
--	      process_init_element (pop_init_level (1,
--						    braced_init_obstack),
-+	      process_init_element (loc,
-+				    pop_init_level (1, braced_init_obstack),
- 				    true, braced_init_obstack);
- 	    }
- 	  for (p = range_stack;
-@@ -8919,7 +8919,8 @@
- 	       p = p->prev)
- 	    {
- 	      gcc_assert (constructor_stack->implicit);
--	      process_init_element (pop_init_level (1, braced_init_obstack),
-+	      process_init_element (loc,
-+				    pop_init_level (1, braced_init_obstack),
- 				    true, braced_init_obstack);
- 	    }
- 
---- a/src/gcc/c/c-tree.h
-+++ b/src/gcc/c/c-tree.h
-@@ -612,7 +612,8 @@
- extern struct c_expr pop_init_level (int, struct obstack *);
- extern void set_init_index (tree, tree, struct obstack *);
- extern void set_init_label (tree, struct obstack *);
--extern void process_init_element (struct c_expr, bool, struct obstack *);
-+extern void process_init_element (location_t, struct c_expr, bool,
-+				  struct obstack *);
- extern tree build_compound_literal (location_t, tree, tree, bool);
- extern void check_compound_literal_type (location_t, struct c_type_name *);
- extern tree c_start_case (location_t, location_t, tree);
---- a/src/gcc/c/ChangeLog.linaro
-+++ b/src/gcc/c/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/gcc/target.def
-+++ b/src/gcc/target.def
-@@ -3039,6 +3039,43 @@
-  int, (enum machine_mode mode, reg_class_t rclass, bool in),
-  default_memory_move_cost)
- 
-+DEFHOOK
-+(use_by_pieces_infrastructure_p,
-+ "GCC will attempt several strategies when asked to copy between\n\
-+two areas of memory, or to set, clear or store to memory, for example\n\
-+when copying a @code{struct}. The @code{by_pieces} infrastructure\n\
-+implements such memory operations as a sequence of load, store or move\n\
-+insns.  Alternate strategies are to expand the\n\
-+@code{movmem} or @code{setmem} optabs, to emit a library call, or to emit\n\
-+unit-by-unit, loop-based operations.\n\
-+\n\
-+This target hook should return true if, for a memory operation with a\n\
-+given @var{size} and @var{alignment}, using the @code{by_pieces}\n\
-+infrastructure is expected to result in better code generation.\n\
-+Both @var{size} and @var{alignment} are measured in terms of storage\n\
-+units.\n\
-+\n\
-+The parameter @var{op} is one of: @code{CLEAR_BY_PIECES},\n\
-+@code{MOVE_BY_PIECES}, @code{SET_BY_PIECES}, @code{STORE_BY_PIECES}.\n\
-+These describe the type of memory operation under consideration.\n\
-+\n\
-+The parameter @var{speed_p} is true if the code is currently being\n\
-+optimized for speed rather than size.\n\
-+\n\
-+Returning true for higher values of @var{size} can improve code generation\n\
-+for speed if the target does not provide an implementation of the\n\
-+@code{movmem} or @code{setmem} standard names, if the @code{movmem} or\n\
-+@code{setmem} implementation would be more expensive than a sequence of\n\
-+insns, or if the overhead of a library call would dominate that of\n\
-+the body of the memory operation.\n\
-+\n\
-+Returning true for higher values of @code{size} may also cause an increase\n\
-+in code size, for example where the number of insns emitted to perform a\n\
-+move would be greater than that of a library call.",
-+ bool, (unsigned HOST_WIDE_INT size, unsigned int alignment,
-+        enum by_pieces_operation op, bool speed_p),
-+ default_use_by_pieces_infrastructure_p)
-+
- /* True for MODE if the target expects that registers in this mode will
-    be allocated to registers in a small register class.  The compiler is
-    allowed to use registers explicitly used in the rtl as spill registers
---- a/src/gcc/optabs.c
-+++ b/src/gcc/optabs.c
-@@ -4234,7 +4234,7 @@
- 	    y = const0_rtx;
- 	}
- 
--      *pmode = word_mode;
-+      *pmode = ret_mode;
-       prepare_cmp_insn (x, y, comparison, NULL_RTX, unsignedp, methods,
- 			ptest, pmode);
-     }
---- a/src/gcc/defaults.h
-+++ b/src/gcc/defaults.h
-@@ -914,14 +914,6 @@
- #define PREFERRED_DEBUGGING_TYPE NO_DEBUG
- #endif
- 
--#ifndef LARGEST_EXPONENT_IS_NORMAL
--#define LARGEST_EXPONENT_IS_NORMAL(SIZE) 0
--#endif
--
--#ifndef ROUND_TOWARDS_ZERO
--#define ROUND_TOWARDS_ZERO 0
--#endif
--
- #ifndef FLOAT_LIB_COMPARE_RETURNS_BOOL
- #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) false
- #endif
-@@ -1065,6 +1057,15 @@
- #define MOVE_MAX_PIECES   MOVE_MAX
- #endif
- 
-+/* STORE_MAX_PIECES is the number of bytes at a time that we can
-+   store efficiently.  Due to internal GCC limitations, this is
-+   MOVE_MAX_PIECES limited by the number of bytes GCC can represent
-+   for an immediate constant.  */
-+
-+#ifndef STORE_MAX_PIECES
-+#define STORE_MAX_PIECES  MIN (MOVE_MAX_PIECES, 2 * sizeof (HOST_WIDE_INT))
-+#endif
-+
- #ifndef MAX_MOVE_MAX
- #define MAX_MOVE_MAX MOVE_MAX
- #endif
---- a/src/gcc/target.h
-+++ b/src/gcc/target.h
-@@ -78,6 +78,17 @@
-   SWITCH_TYPE_LINE_END		/* Please emit a line terminator.  */
- };
- 
-+/* Types of memory operation understood by the "by_pieces" infrastructure.
-+   Used by the TARGET_USE_BY_PIECES_INFRASTRUCTURE_P target hook.  */
-+
-+enum by_pieces_operation
-+{
-+  CLEAR_BY_PIECES,
-+  MOVE_BY_PIECES,
-+  SET_BY_PIECES,
-+  STORE_BY_PIECES
-+};
-+
- typedef int (* print_switch_fn_type) (print_switch_type, const char *);
- 
- /* An example implementation for ELF targets.  Defined in varasm.c  */
---- a/src/gcc/configure
-+++ b/src/gcc/configure
-@@ -1686,7 +1686,8 @@
-                           use sysroot as the system root during the build
-   --with-sysroot[=DIR]    search for usr/lib, usr/include, et al, within DIR
-   --with-specs=SPECS      add SPECS to driver command-line processing
--  --with-pkgversion=PKG   Use PKG in the version string in place of "GCC"
-+  --with-pkgversion=PKG   Use PKG in the version string in place of "Linaro
-+                          GCC `cat $srcdir/LINARO-VERSION`"
-   --with-bugurl=URL       Direct users to URL to report a bug
-   --with-multilib-list    select multilibs (AArch64, SH and x86-64 only)
-   --with-gnu-ld           assume the C compiler uses GNU ld default=no
-@@ -7231,7 +7232,7 @@
-       *)   PKGVERSION="($withval) " ;;
-      esac
- else
--  PKGVERSION="(GCC) "
-+  PKGVERSION="(Linaro GCC `cat $srcdir/LINARO-VERSION`) "
- 
- fi
- 
-@@ -17936,7 +17937,7 @@
-   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
-   lt_status=$lt_dlunknown
-   cat > conftest.$ac_ext <<_LT_EOF
--#line 17939 "configure"
-+#line 17940 "configure"
- #include "confdefs.h"
- 
- #if HAVE_DLFCN_H
-@@ -18042,7 +18043,7 @@
-   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
-   lt_status=$lt_dlunknown
-   cat > conftest.$ac_ext <<_LT_EOF
--#line 18045 "configure"
-+#line 18046 "configure"
- #include "confdefs.h"
- 
- #if HAVE_DLFCN_H
---- a/src/gcc/lra-eliminations.c
-+++ b/src/gcc/lra-eliminations.c
-@@ -1164,7 +1164,9 @@
- 		     ep->from, ep->to);
- 	  /* If after processing RTL we decides that SP can be used as
- 	     a result of elimination, it can not be changed.  */
--	  gcc_assert (ep->to_rtx != stack_pointer_rtx);
-+	  gcc_assert ((ep->to_rtx != stack_pointer_rtx)
-+		      || (ep->from < FIRST_PSEUDO_REGISTER
-+			  && fixed_regs [ep->from]));
- 	  /* Mark that is not eliminable anymore.  */
- 	  elimination_map[ep->from] = NULL;
- 	  for (ep1 = ep + 1; ep1 < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep1++)
---- a/src/gcc/objc/ChangeLog.linaro
-+++ b/src/gcc/objc/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/gcc/ChangeLog.linaro
-+++ b/src/gcc/ChangeLog.linaro
-@@ -0,0 +1,3211 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+	* LINARO-VERSION: Update.
-+
-+2015-01-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Fix Linaro PR #902
-+
-+	Partial Backport from trunk r211798.
-+	2014-06-18  Radovan Obradovic  <robradovic@mips.com>
-+		    Tom de Vries  <tom@codesourcery.com>
-+
-+	* config/arm/arm.c (arm_emit_call_insn): Add IP and CC clobbers to
-+	CALL_INSN_FUNCTION_USAGE.
-+
-+	Backport from trunk r209800.
-+	2014-04-25  Tom de Vries  <tom@codesourcery.com>
-+
-+	* expr.c (clobber_reg_mode): New function.
-+	* expr.h (clobber_reg): New function.
-+
-+2015-01-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r211783.
-+	2014-06-18  Charles Baylis  <charles.baylis@linaro.org>
-+
-+	* config/arm/arm.c (neon_vector_mem_operand): Allow register
-+	POST_MODIFY for neon loads and stores.
-+	(arm_print_operand): Output post-index register for neon loads and
-+	stores.
-+
-+2015-01-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r218451.
-+	2014-12-06  James Greenhalgh  <james.greenhalgh@arm.com>
-+		    Sebastian Pop  <s.pop@samsung.com>
-+		    Brian Rzycki  <b.rzycki@samsung.com>
-+
-+	PR tree-optimization/54742
-+	* params.def (max-fsm-thread-path-insns, max-fsm-thread-length,
-+	max-fsm-thread-paths): New.
-+
-+	* doc/invoke.texi (max-fsm-thread-path-insns, max-fsm-thread-length,
-+	max-fsm-thread-paths): Documented.
-+
-+	* tree-cfg.c (split_edge_bb_loc): Export.
-+	* tree-cfg.h (split_edge_bb_loc): Declared extern.
-+
-+	* tree-ssa-threadedge.c (simplify_control_stmt_condition): Restore the
-+	original value of cond when simplification fails.
-+	(fsm_find_thread_path): New.
-+	(fsm_find_control_statement_thread_paths): New.
-+	(thread_through_normal_block): Call find_control_statement_thread_paths.
-+
-+	* tree-ssa-threadupdate.c (dump_jump_thread_path): Pretty print
-+	EDGE_FSM_THREAD.
-+	(verify_seme): New.
-+	(duplicate_seme_region): New.
-+	(thread_through_all_blocks): Generate code for EDGE_FSM_THREAD edges
-+	calling duplicate_seme_region.
-+
-+	* tree-ssa-threadupdate.h (jump_thread_edge_type): Add EDGE_FSM_THREAD.
-+
-+2015-01-13  Michael Collison  <michael.collison@linaro.org>
-+
-+	Backport from trunk r217394.
-+	2014-11-11  Andrew Pinski  <apinski@cavium.com>
-+
-+	Bug target/61997
-+	* config.gcc (aarch64*-*-*): Set target_gtfiles to include
-+	aarch64-builtins.c.
-+	* config/aarch64/aarch64-builtins.c: Include gt-aarch64-builtins.h
-+	at the end of the file.
-+
-+2015-01-13  Michael Collison  <michael.collison@linaro.org>
-+
-+	Backport from trunk r216267, r216547, r216548, r217072, r217192, r217405,
-+	r217406, r217768.
-+	2014-11-19  Renlin Li  <renlin.li@arm.com>
-+
-+	* config/aarch64/aarch64.h (TARGET_CPU_CPP_BUILTINS): Define __ARM_FP_FAST,
-+	__ARM_FEATURE_FMA, __ARM_FP, __ARM_FEATURE_NUMERIC_MAXMIN, __ARM_NEON_FP.
-+
-+	2014-11-12  Tejas Belagod  <tejas.belagod@arm.com>
-+
-+	* Makefile.in (TEXI_GCC_FILES): Remove arm-acle-intrinsics.texi,
-+	arm-neon-intrinsics.texi, aarch64-acle-intrinsics.texi.
-+	* doc/aarch64-acle-intrinsics.texi: Remove.
-+	* doc/arm-acle-intrinsics.texi: Remove.
-+	* doc/arm-neon-intrinsics.texi: Remove.
-+	* doc/extend.texi: Consolidate sections AArch64 intrinsics,
-+	ARM NEON Intrinsics, ARM ACLE Intrinsics into one ARM C Language
-+	Extension section. Add references to public ACLE specification.
-+
-+	2014-11-06  Renlin Li  <renlin.li@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_architecture_version): New.
-+	(processor): New architecture_version field.
-+	(aarch64_override_options): Initialize aarch64_architecture_version.
-+	* config/aarch64/aarch64.h (TARGET_CPU_CPP_BUILTINS): Define __ARM_ARCH,
-+	__ARM_ARCH_PROFILE, aarch64_arch_name macro.
-+
-+	2014-11-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
-+
-+	* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Fix typo in definition
-+	of __ARM_FEATURE_IDIV.
-+
-+	2014-10-22  Jiong Wang <jiong.wang@arm.com>
-+
-+	* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Add missing '\'.
-+
-+	2014-10-22  Renlin Li <renlin.li@arm.com>
-+
-+	* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Define
-+	__ARM_FEATURE_IDIV__.
-+
-+	2014-10-15  Renlin Li <renlin.li@arm.com>
-+
-+	* config/aarch64/aarch64.h (TARGET_CPU_CPP_BUILTINS): Define
-+	__ARM_BIG_ENDIAN, __ARM_SIZEOF_MINIMAL_ENUM. Add __ARM_64BIT_STATE,
-+	__ARM_ARCH_ISA_A64, __ARM_FEATURE_CLZ, __ARM_FEATURE_IDIV,
-+	__ARM_FEATURE_UNALIGNED, __ARM_PCS_AAPCS64, __ARM_SIZEOF_WCHAR_T.
-+
-+2015-01-13  Michael Collison  <michael.collison@linaro.org>
-+
-+	Backport from trunk r211789, r211790, r211791, r211792, r211793, r211794,
-+	r211795, r211796, r211797.
-+	2014-06-18  Charles Baylis  <charles.baylis@linaro.org>
-+
-+	* config/arm/bpabi.c (__gnu_uldivmod_helper): Remove.
-+
-+	2014-06-18  Charles Baylis  <charles.baylis@linaro.org>
-+
-+	* config/arm/bpabi-v6m.S (__aeabi_uldivmod): Perform division using
-+	__udivmoddi4.
-+
-+	2014-06-18  Charles Baylis  <charles.baylis@linaro.org>
-+
-+	* config/arm/bpabi.S (__aeabi_ldivmod, __aeabi_uldivmod,
-+	push_for_divide, pop_for_divide): Use .cfi_* directives for DWARF
-+	annotations. Fix DWARF information.
-+
-+	2014-06-18  Charles Baylis  <charles.baylis@linaro.org>
-+
-+	* config/arm/bpabi.S (__aeabi_ldivmod): Perform division using
-+	__udivmoddi4, and fixups for negative operands.
-+
-+	2014-06-18  Charles Baylis  <charles.baylis@linaro.org>
-+
-+	* config/arm/bpabi.S (__aeabi_ldivmod): Optimise stack manipulation.
-+
-+	2014-06-18  Charles Baylis  <charles.baylis@linaro.org>
-+
-+	* config/arm/bpabi.S (__aeabi_uldivmod): Perform division using call
-+	to __udivmoddi4.
-+
-+	2014-06-18  Charles Baylis  <charles.baylis@linaro.org>
-+
-+	* config/arm/bpabi.S (__aeabi_uldivmod): Optimise stack pointer
-+	manipulation.
-+
-+	2014-06-18  Charles Baylis  <charles.baylis@linaro.org>
-+
-+	* config/arm/bpabi.S (__aeabi_uldivmod, __aeabi_ldivmod): Add comment
-+	describing register usage on function entry and exit.
-+
-+	2014-06-18  Charles Baylis  <charles.baylis@linaro.org>
-+
-+	* config/arm/bpabi.S (__aeabi_uldivmod): Fix whitespace.
-+	(__aeabi_ldivmod): Fix whitespace.
-+
-+2015-01-13  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r217593.
-+	2014-11-14  Andrew Pinski  <apinski@cavium.com>
-+
-+	* config/aarch64/aarch64-cores.def (thunderx): Change the scheduler
-+	over to thunderx.
-+	* config/aarch64/aarch64.md: Include thunderx.md.
-+	(generic_sched): Set to no for thunderx.
-+	* config/aarch64/thunderx.md: New file.
-+
-+2015-01-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r217717.
-+	2014-11-18  Felix Yang  <felix.yang@huawei.com>
-+
-+	* config/aarch64/aarch64.c (doloop_end): New pattern.
-+	* config/aarch64/aarch64.md (TARGET_CAN_USE_DOLOOP_P): Implement.
-+
-+2015-01-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r217661.
-+	2014-11-17  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/aarch64/aarch64-cores.def (cortex-a53): Remove
-+	AARCH64_FL_CRYPTO from feature flags.
-+	(cortex-a57): Likewise.
-+	(cortex-a57.cortex-a53): Likewise.
-+
-+2015-01-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r218319.
-+	2014-12-03  Andrew Stubbs  <ams@codesourcery.com>
-+
-+	Revert:
-+
-+	2014-09-17  Andrew Stubbs  <ams@codesourcery.com>
-+
-+	* config/arm/arm.c (arm_option_override): Reject -mfpu=neon
-+	when architecture is older than ARMv7.
-+
-+2015-01-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r217691.
-+	2014-11-18  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* lra-eliminations.c (update_reg_eliminate): Relax gcc_assert for fixed
-+	registers.
-+
-+2015-01-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215503.
-+	2014-09-23  Wilco Dijkstra  <wdijkstr@arm.com>
-+
-+	* common/config/aarch64/aarch64-common.c:
-+	(default_options aarch_option_optimization_table):
-+	Default to -fsched-pressure.
-+
-+2015-01-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r211132.
-+	2014-06-02  Tom de Vries  <tom@codesourcery.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_float_const_representable_p): Handle
-+	case that x has VOIDmode.
-+
-+2015-01-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209620.
-+	2014-04-22  Vidya Praveen  <vidyapraveen@arm.com>
-+
-+	* aarch64.md (float<GPI:mode><GPF:mode>2): Remove.
-+	(floatuns<GPI:mode><GPF:mode>2): Remove.
-+	(<optab><fcvt_target><GPF:mode>2): New pattern for equal width float
-+	and floatuns conversions.
-+	(<optab><fcvt_iesize><GPF:mode>2): New pattern for inequal width float
-+	and floatuns conversions.
-+	* iterators.md (fcvt_target, FCVT_TARGET): Support SF and DF modes.
-+	(w1,w2): New mode attributes for inequal width conversions.
-+ 
-+2015-01-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r217362, r217546.
-+	2014-11-14  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
-+
-+	PR target/63724
-+        * config/aarch64/aarch64.c (aarch64_expand_mov_immediate): Split out
-+        numerical immediate handling to...
-+        (aarch64_internal_mov_immediate): ...this. New.
-+        (aarch64_rtx_costs): Use aarch64_internal_mov_immediate.
-+        (aarch64_mov_operand_p): Relax predicate.
-+        * config/aarch64/aarch64.md (mov<mode>:GPI): Do not expand CONST_INTs.
-+        (*movsi_aarch64): Turn into define_insn_and_split and new alternative
-+        for 'n'.
-+        (*movdi_aarch64): Likewise.
-+
-+	2014-11-11  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* config/aarch64/aarch64-simd.md
-+	(aarch64_simd_bsl<mode>_internal): Remove float cases, canonicalize.
-+	(aarch64_simd_bsl<mode>): Add gen_lowpart expressions where we
-+	are punning between float vectors and integer vectors.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	* LINARO-VERSION: Bump version.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+	* LINARO-VERSION: Update.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r217079, r217080.
-+	2014-11-04  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	config/arm/neon.md (reduc_smin_<mode> *2): Rename to...
-+	(reduc_smin_scal_<mode> *2): ...this; extract scalar result.
-+	(reduc_smax_<mode> *2): Rename to...
-+	(reduc_smax_scal_<mode> *2): ...this; extract scalar result.
-+	(reduc_umin_<mode> *2): Rename to...
-+	(reduc_umin_scal_<mode> *2): ...this; extract scalar result.
-+	(reduc_umax_<mode> *2): Rename to...
-+	(reduc_umax_scal_<mode> *2): ...this; extract scalar result.
-+
-+	2014-11-04  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	config/arm/neon.md (reduc_plus_*): Rename to...
-+	(reduc_plus_scal_*): ...this; reduce to temp and extract scalar result.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Fix Backport from trunk r216524 (committed at r218379).
-+	Add missing file: config/aarch64/aarch64-cost-tables.h
-+
-+	* config/aarch64/aarch64-cost-tables.h: New file.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r217076.
-+	2014-11-04  Michael Collison <michael.collison@linaro.org>
-+
-+	* config/aarch64/iterators.md (lconst_atomic): New mode attribute
-+	to support constraints for CONST_INT in atomic operations.
-+	* config/aarch64/atomics.md
-+	(atomic_<atomic_optab><mode>): Use lconst_atomic constraint.
-+	(atomic_nand<mode>): Likewise.
-+	(atomic_fetch_<atomic_optab><mode>): Likewise.
-+	(atomic_fetch_nand<mode>): Likewise.
-+	(atomic_<atomic_optab>_fetch<mode>): Likewise.
-+	(atomic_nand_fetch<mode>): Likewise.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r217026.
-+	2014-11-03  Zhenqiang Chen  <zhenqiang.chen@arm.com>
-+
-+	* ifcvt.c (noce_emit_cmove, noce_get_alt_condition, noce_get_condition):
-+	Allow CC mode if HAVE_cbranchcc4.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r217014.
-+	2014-11-02  Michael Collison  <michael.collison@linaro.org>
-+
-+	* config/arm/arm.h (CLZ_DEFINED_VALUE_AT_ZERO) : Update
-+	to support vector modes.
-+	(CTZ_DEFINED_VALUE_AT_ZERO): Ditto.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r216996, r216998, r216999, r217001, r217002, r217003,
-+	r217004, r217742.
-+	2014-11-18  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	PR target/63937
-+	* target.def (use_by_pieces_infrastructure_p): Take unsigned
-+	HOST_WIDE_INT as the size parameter.
-+	* targhooks.c (default_use_by_pieces_infrastructure_p): Likewise.
-+	* targhooks.h (default_use_by_pieces_infrastructure_p): Likewise.
-+	* config/arc/arc.c (arc_use_by_pieces_infrastructure_p)): Likewise.
-+	* config/mips/mips.c (mips_use_by_pieces_infrastructure_p)): Likewise.
-+	* config/s390/s390.c (s390_use_by_pieces_infrastructure_p)): Likewise.
-+	* config/sh/sh.c (sh_use_by_pieces_infrastructure_p)): Likewise.
-+	* config/aarch64/aarch64.c
-+	(aarch64_use_by_pieces_infrastructure_p)): Likewise.
-+	* doc/tm.texi: Regenerate.
-+
-+	2014-11-01  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* doc/tm.texi.in (MOVE_BY_PIECES_P): Remove.
-+	(CLEAR_BY_PIECES_P): Likewise.
-+	(SET_BY_PIECES_P): Likewise.
-+	(STORE_BY_PIECES_P): Likewise.
-+	* doc/tm.texi: Regenerate.
-+	* system.h: Poison MOVE_BY_PIECES_P, CLEAR_BY_PIECES_P,
-+	SET_BY_PIECES_P, STORE_BY_PIECES_P.
-+	* expr.c (MOVE_BY_PIECES_P): Remove.
-+	(CLEAR_BY_PIECES_P): Likewise.
-+	(SET_BY_PIECES_P): Likewise.
-+	(STORE_BY_PIECES_P): Likewise.
-+	(can_move_by_pieces): Rewrite in terms of
-+	targetm.use_by_pieces_infrastructure_p.
-+	(emit_block_move_hints): Likewise.
-+	(can_store_by_pieces): Likewise.
-+	(store_by_pieces): Likewise.
-+	(clear_storage_hints): Likewise.
-+	(emit_push_insn): Likewise.
-+	(expand_constructor): Likewise.
-+
-+	2014-11-01  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* config/aarch64/aarch64.c
-+	(aarch64_use_by_pieces_infrastructre_p): New.
-+	(TARGET_USE_BY_PIECES_INFRASTRUCTURE): Likewise.
-+	* config/aarch64/aarch64.h (STORE_BY_PIECES_P): Delete.
-+
-+	2014-11-01  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* config/mips/mips.h (MOVE_BY_PIECES_P): Remove.
-+	(STORE_BY_PIECES_P): Likewise.
-+	* config/mips/mips.c (TARGET_USE_BY_PIECES_INFRASTRUCTURE_P): New.
-+	(mips_move_by_pieces_p): Rename to...
-+	(mips_use_by_pieces_infrastructure_p): ...this, use new hook
-+	parameters, use the default hook implementation as a
-+	fall-back.
-+
-+	2014-11-01  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* config/sh/sh.c (TARGET_USE_BY_PIECES_INFRASTRUCTURE_P): New.
-+	(sh_use_by_pieces_infrastructure_p): Likewise.
-+	* config/sh/sh.h (MOVE_BY_PIECES_P): Remove.
-+	(STORE_BY_PIECES_P): Likewise.
-+	(SET_BY_PIECES_P): Likewise.
-+
-+	2014-11-01  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* config/arc/arc.c (TARGET_USE_BY_PIECES_INFRASTRUCTURE_P): New.
-+	(arc_use_by_pieces_infrastructure_p): Likewise.
-+	* confir/arc/arc.h (MOVE_BY_PIECES_P): Delete.
-+	(CAN_MOVE_BY_PIECES): Likewise.
-+
-+	2014-11-01  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* config/s390/s390.c (s390_use_by_pieces_infrastructure_p): New.
-+	(TARGET_USE_BY_PIECES_INFRASTRUCTURE_P): Likewise.
-+	* config/s390/s390.h (MOVE_BY_PIECES_P): Remove.
-+	(CLEAR_BY_PIECES): Likewise.
-+	(SET_BY_PIECES): Likewise.
-+	(STORE_BY_PIECES): Likewise.
-+
-+	2014-11-01  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* target.def (use_by_pieces_infrastructure_p): New.
-+	* doc/tm.texi.in (MOVE_BY_PIECES_P): Describe that this macro
-+	is deprecated.
-+	(STORE_BY_PIECES_P): Likewise.
-+	(CLEAR_BY_PIECES_P): Likewise.
-+	(SET_BY_PIECES_P): Likewise.
-+	(TARGET_MOVE_BY_PIECES_PROFITABLE_P): Add hook.
-+	* doc/tm.texi: Regenerate.
-+	* expr.c (MOVE_BY_PIECES_P): Rewrite in terms of
-+	TARGET_USE_BY_PIECES_INFRASTRUCTURE_P.
-+	(STORE_BY_PIECES_P): Likewise.
-+	(CLEAR_BY_PIECES_P): Likewise.
-+	(SET_BY_PIECES_P): Likewise.
-+	(STORE_MAX_PIECES): Move to...
-+	* defaults.h (STORE_MAX_PIECES): ...here.
-+	* targhooks.c (get_move_ratio): New.
-+	(default_use_by_pieces_infrastructure_p): Likewise.
-+	* targhooks.h (default_use_by_pieces_infrastructure_p): New.
-+	* target.h (by_pieces_operation): New.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r216765.
-+	2014-10-27  Jiong Wang <jiong.wang@arm.com>
-+
-+	PR target/63442
-+	* optabs.c (prepare_cmp_insn): Use "ret_mode" instead of "word_mode".
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r216630.
-+	2014-10-24  Felix Yang  <felix.yang@huawei.com>
-+	Jiji Jiang  <jiangjiji@huawei.com>
-+
-+	PR target/63173
-+	* config/aarch64/arm_neon.h (__LD2R_FUNC): Remove macro.
-+	(__LD3R_FUNC): Ditto.
-+	(__LD4R_FUNC): Ditto.
-+	(vld2_dup_s8, vld2_dup_s16, vld2_dup_s32, vld2_dup_f32, vld2_dup_f64,
-+	 vld2_dup_u8, vld2_dup_u16, vld2_dup_u32, vld2_dup_p8, vld2_dup_p16
-+	 vld2_dup_s64, vld2_dup_u64, vld2q_dup_s8, vld2q_dup_p8, 
-+	 vld2q_dup_s16, vld2q_dup_p16, vld2q_dup_s32, vld2q_dup_s64, 
-+	 vld2q_dup_u8, vld2q_dup_u16, vld2q_dup_u32, vld2q_dup_u64 
-+	 vld2q_dup_f32, vld2q_dup_f64): Rewrite using builtin functions.
-+	(vld3_dup_s64, vld3_dup_u64, vld3_dup_f64, vld3_dup_s8 
-+	 vld3_dup_p8, vld3_dup_s16, vld3_dup_p16, vld3_dup_s32 
-+	 vld3_dup_u8, vld3_dup_u16, vld3_dup_u32, vld3_dup_f32
-+	 vld3q_dup_s8, vld3q_dup_p8, vld3q_dup_s16, vld3q_dup_p16 
-+	 vld3q_dup_s32, vld3q_dup_s64, vld3q_dup_u8, vld3q_dup_u16 
-+	 vld3q_dup_u32, vld3q_dup_u64, vld3q_dup_f32, vld3q_dup_f64): Likewise.
-+	(vld4_dup_s64, vld4_dup_u64, vld4_dup_f64, vld4_dup_s8 
-+	 vld4_dup_p8, vld4_dup_s16, vld4_dup_p16, vld4_dup_s32 
-+	 vld4_dup_u8, vld4_dup_u16, vld4_dup_u32, vld4_dup_f32 
-+	 vld4q_dup_s8, vld4q_dup_p8, vld4q_dup_s16, vld4q_dup_p16 
-+	 vld4q_dup_s32, vld4q_dup_s64, vld4q_dup_u8, vld4q_dup_u16 
-+	 vld4q_dup_u32, vld4q_dup_u64, vld4q_dup_f32, vld4q_dup_f64): Likewise.
-+	* config/aarch64/aarch64.md (define_c_enum "unspec"): Add
-+	UNSPEC_LD2_DUP, UNSPEC_LD3_DUP, UNSPEC_LD4_DUP.
-+	* config/aarch64/aarch64-simd-builtins.def (ld2r, ld3r, ld4r): New
-+	builtins.
-+	* config/aarch64/aarch64-simd.md (aarch64_simd_ld2r<mode>): New pattern.
-+	(aarch64_simd_ld3r<mode>): Likewise.
-+	(aarch64_simd_ld4r<mode>): Likewise.
-+	(aarch64_ld2r<mode>): New expand.
-+	(aarch64_ld3r<mode>): Likewise.
-+	(aarch64_ld4r<mode>): Likewise.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r217971.
-+	2014-11-22  Uros Bizjak  <ubizjak@gmail.com>
-+
-+	* params.def (PARAM_MAX_COMPLETELY_PEELED_INSNS): Increase to 200.
-+	* config/i386/i386.c (ix86_option_override_internal): Do not increase
-+	PARAM_MAX_COMPLETELY_PEELED_INSNS.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r216524.
-+	2014-10-21  Andrew Pinski  <apinski@cavium.com>
-+
-+	* doc/invoke.texi (AARCH64/mtune): Document thunderx as an
-+	available option also.
-+	* config/aarch64/aarch64-cost-tables.h: New file.
-+	* config/aarch64/aarch64-cores.def (thunderx): New core.
-+	* config/aarch64/aarch64-tune.md: Regenerate.
-+	* config/aarch64/aarch64.c: Include aarch64-cost-tables.h instead
-+	of config/arm/aarch-cost-tables.h.
-+	(thunderx_regmove_cost): New variable.
-+	(thunderx_tunings): New variable.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r216336.
-+	2014-10-16  Richard Earnshaw  <rearnsha@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_legitimize_address): New function.
-+	(TARGET_LEGITIMIZE_ADDRESS): Redefine.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r216253.
-+	2014-10-15  Renlin Li <renlin.li@arm.com>
-+
-+	* config/aarch64/aarch64.h (ARM_DEFAULT_PCS, arm_pcs_variant): Delete.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215711.
-+	2014-09-30  Terry Guo  <terry.guo@arm.com>
-+
-+	* config/arm/arm-cores.def (cortex-m7): New core name.
-+	* config/arm/arm-fpus.def (fpv5-sp-d16): New fpu name.
-+	(fpv5-d16): Ditto.
-+	* config/arm/arm-tables.opt: Regenerated.
-+	* config/arm/arm-tune.md: Regenerated.
-+	* config/arm/arm.h (TARGET_VFP5): New macro.
-+	* config/arm/bpabi.h (BE8_LINK_SPEC): Include cortex-m7.
-+	* config/arm/vfp.md (<vrint_pattern><SDF:mode>2,
-+	smax<mode>3, smin<mode>3): Enabled for FPU FPv5.
-+	* doc/invoke.texi: Document new cpu and fpu names.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215707, r215842.
-+	2014-10-03  David Sherwood  <david.sherwood@arm.com>
-+
-+	* ira-int.h (ira_allocno): Mark hard_regno as signed.
-+
-+	2014-09-30  David Sherwood  <david.sherwood@arm.com>
-+
-+	* ira-int.h (ira_allocno): Add "wmode" field.
-+	* ira-build.c (create_insn_allocnos): Add new "parent" function
-+	parameter.
-+	* ira-conflicts.c (ira_build_conflicts): Add conflicts for registers
-+	that cannot be accessed in wmode.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215540.
-+	2014-09-24  Zhenqiang Chen  <zhenqiang.chen@arm.com>
-+
-+	PR rtl-optimization/63210
-+	* ira-color.c (assign_hard_reg): Ignore conflict cost if the
-+	HARD_REGNO is not available for CONFLICT_A.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215046.
-+	2014-09-09  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	PR target/61749
-+	* config/aarch64/aarch64-builtins.c (aarch64_types_quadop_qualifiers):
-+	Use qualifier_immediate for last operand.  Rename to...
-+	(aarch64_types_ternop_lane_qualifiers): ... This.
-+	(TYPES_QUADOP): Rename to...
-+	(TYPES_TERNOP_LANE): ... This.
-+	(aarch64_simd_expand_args): Return const0_rtx when encountering user
-+	error.  Change return of 0 to return of NULL_RTX.
-+	(aarch64_crc32_expand_builtin): Likewise.
-+	(aarch64_expand_builtin): Return NULL_RTX instead of 0.
-+	ICE when expanding unknown builtin.
-+	* config/aarch64/aarch64-simd-builtins.def (sqdmlal_lane): Use
-+	TERNOP_LANE qualifiers.
-+	(sqdmlsl_lane): Likewise.
-+	(sqdmlal_laneq): Likewise.
-+	(sqdmlsl_laneq): Likewise.
-+	(sqdmlal2_lane): Likewise.
-+	(sqdmlsl2_lane): Likewise.
-+	(sqdmlal2_laneq): Likewise.
-+	(sqdmlsl2_laneq): Likewise.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215013.
-+	2014-09-08  Joseph Myers  <joseph@codesourcery.com>
-+
-+	* defaults.h (LARGEST_EXPONENT_IS_NORMAL, ROUND_TOWARDS_ZERO):
-+	Remove.
-+	* doc/tm.texi.in (ROUND_TOWARDS_ZERO, LARGEST_EXPONENT_IS_NORMAL):
-+	Remove.
-+	* doc/tm.texi: Regenerate.
-+	* system.h (LARGEST_EXPONENT_IS_NORMAL, ROUND_TOWARDS_ZERO):
-+	Poison.
-+	* config/arm/arm.h (LARGEST_EXPONENT_IS_NORMAL): Remove.
-+	* config/cris/cris.h (__make_dp): Remove.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r214952.
-+	2014-09-05  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* config/aarch64/arm_neon.h (__GET_HIGH): New macro.
-+	(vget_high_f32, vget_high_f64, vget_high_p8, vget_high_p16,
-+	vget_high_s8, vget_high_s16, vget_high_s32, vget_high_s64,
-+	vget_high_u8, vget_high_u16, vget_high_u32, vget_high_u64):
-+	Remove temporary __asm__ and reimplement.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r214948, r214949.
-+	2014-09-05  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* config/aarch64/aarch64-builtins.c (aarch64_fold_builtin): Remove code
-+	handling cmge, cmgt, cmeq, cmtst.
-+
-+	* config/aarch64/aarch64-simd-builtins.def (cmeq, cmge, cmgt, cmle,
-+	cmlt, cmgeu, cmgtu, cmtst): Remove.
-+
-+	* config/aarch64/arm_neon.h (vceq_*, vceqq_*, vceqz_*, vceqzq_*,
-+	vcge_*, vcgeq_*, vcgez_*, vcgezq_*, vcgt_*, vcgtq_*, vcgtz_*,
-+	vcgtzq_*, vcle_*, vcleq_*, vclez_*, vclezq_*, vclt_*, vcltq_*,
-+	vcltz_*, vcltzq_*, vtst_*, vtstq_*): Use gcc vector extensions.
-+
-+	2014-09-05  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* config/aarch64/aarch64-builtins.c (aarch64_types_cmtst_qualifiers,
-+	TYPES_TST): Define.
-+	(aarch64_fold_builtin): Update pattern for cmtst.
-+
-+	* config/aarch64/aarch64-protos.h (aarch64_const_vec_all_same_int_p):
-+	Declare.
-+
-+	* config/aarch64/aarch64-simd-builtins.def (cmtst): Update qualifiers.
-+
-+	* config/aarch64/aarch64-simd.md (aarch64_vcond_internal<mode><mode>):
-+	Switch operands, separate out more cases, refactor.
-+
-+	(aarch64_cmtst<mode>): Rewrite pattern to match (plus ... -1).
-+
-+	* config/aarch64.c (aarch64_const_vec_all_same_int_p): Take single
-+	argument; rename old version to...
-+	(aarch64_const_vec_all_same_in_range_p): ...this.
-+	(aarch64_print_operand, aarch64_simd_shift_imm_p): Follow renaming.
-+
-+	* config/aarch64/predicates.md (aarch64_simd_imm_minus_one): Define.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r214008.
-+	2014-08-15  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_expand_mov_immediate): Move
-+	one_match > zero_match case to just before simple_sequence.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r213382.
-+	2014-07-31  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* config/aarch64/arm_neon.h (vpadd_<suf><8,16,32,64>): Move to
-+	correct alphabetical position.
-+	(vpaddd_f64): Rewrite using builtins.
-+	(vpaddd_s64): Move to correct alphabetical position.
-+	(vpaddd_u64): New.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r210735, r215206, r215207, r215208.
-+	2014-09-12  Wilco Dijkstra  <wilco.dijkstra@arm.com>
-+
-+	* gcc/config/aarch64/aarch64.c (cortexa57_regmove_cost): New cost table
-+	for A57.
-+	(cortexa53_regmove_cost): New cost table for A53.  Increase GP2FP/FP2GP
-+	cost to spilling from integer to FP registers.
-+
-+	2014-09-12  Wilco Dijkstra  <wilco.dijkstra@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_register_move_cost): Fix Q register
-+	move handling.
-+	(generic_regmove_cost): Undo raised FP2FP move cost as Q register moves
-+	are now handled correctly.
-+
-+	2014-09-12  Wilco Dijkstra  <wilco.dijkstra@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_register_move_cost): Add cost
-+	handling of CALLER_SAVE_REGS and POINTER_REGS.
-+
-+	2014-05-22  Kugan Vivekanandarajah  <kuganv@linaro.org>
-+
-+	* config/aarch64/aarch64.c (aarch64_regno_regclass) : Change CORE_REGS
-+	to GENERAL_REGS.
-+	(aarch64_secondary_reload) : LikeWise.
-+	(aarch64_class_max_nregs) : Remove CORE_REGS.
-+	* config/aarch64/aarch64.h (enum reg_class) : Remove CORE_REGS.
-+	(REG_CLASS_NAMES) : Likewise.
-+	(REG_CLASS_CONTENTS) : LikeWise.
-+	(INDEX_REG_CLASS) : Change CORE_REGS to GENERAL_REGS.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	* LINARO-VERSION: Bump version.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+	* LINARO-VERSION: Update.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Add Linaro release macros (Linaro only patch.)
-+
-+	* Makefile.in (LINAROVER, LINAROVER_C, LINAROVER_S): Define.
-+	(CFLAGS-cppbuiltin.o): Add LINAROVER macro definition.
-+	(cppbuiltin.o): Depend on $(LINAROVER).
-+	* cppbuiltin.c (parse_linarover): New.
-+	(define_GNUC__): Define __LINARO_RELEASE__ and __LINARO_SPIN__ macros.
-+
-+2014-11-13  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r216229, r216230.
-+	2014-10-14  Andrew Pinski  <apinski@cavium.com>
-+
-+	* explow.c (convert_memory_address_addr_space): Rename to ...
-+	(convert_memory_address_addr_space_1): This.  Add in_const argument.
-+	Inside a CONST RTL, permute the conversion and addition of constant
-+	for zero and sign extended pointers.
-+	(convert_memory_address_addr_space): New function.
-+
-+	2014-10-14  Andrew Pinski  <apinski@cavium.com>
-+
-+	Revert:
-+	2011-08-19  H.J. Lu  <hongjiu.lu@intel.com>
-+
-+        PR middle-end/49721
-+        * explow.c (convert_memory_address_addr_space): Also permute the
-+        conversion and addition of constant for zero-extend.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	* LINARO-VERSION: Bump version.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+	* LINARO-VERSION: Update.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	* LINARO-VERSION: Bump version.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+	* LINARO-VERSION: Update.
-+
-+2014-10-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Revert:
-+	2014-10-08  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215206, r215207, r215208.
-+	2014-09-12  Wilco Dijkstra  <wilco.dijkstra@arm.com>
-+
-+	* gcc/config/aarch64/aarch64.c (cortexa57_regmove_cost): New cost table
-+	for A57.
-+	(cortexa53_regmove_cost): New cost table for A53.  Increase GP2FP/FP2GP
-+	cost to spilling from integer to FP registers.
-+
-+	2014-09-12  Wilco Dijkstra  <wilco.dijkstra@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_register_move_cost): Fix Q register
-+	move handling.
-+	(generic_regmove_cost): Undo raised FP2FP move cost as Q register moves
-+	are now handled correctly.
-+
-+	2014-09-12  Wilco Dijkstra  <wilco.dijkstra@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_register_move_cost): Add cost
-+	handling of CALLER_SAVE_REGS and POINTER_REGS.
-+
-+2014-10-08  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r214825, r214826.
-+	2014-09-02  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	PR target/62275
-+	* config/arm/neon.md
-+	(neon_vcvt<NEON_VCVT:nvrint_variant><su_optab><VCVTF:mode>
-+	<v_cmp_result>): New pattern.
-+	* config/arm/iterators.md (NEON_VCVT): New int iterator.
-+	* config/arm/arm_neon_builtins.def (vcvtav2sf, vcvtav4sf, vcvtauv2sf,
-+	vcvtauv4sf, vcvtpv2sf, vcvtpv4sf, vcvtpuv2sf, vcvtpuv4sf, vcvtmv2sf,
-+	vcvtmv4sf, vcvtmuv2sf, vcvtmuv4sf): New builtin definitions.
-+	* config/arm/arm.c (arm_builtin_vectorized_function): Handle
-+	BUILT_IN_LROUNDF, BUILT_IN_LFLOORF, BUILT_IN_LCEILF.
-+
-+	2014-09-02  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	PR target/62275
-+	* config/arm/iterators.md (FIXUORS): New code iterator.
-+	(VCVT): New int iterator.
-+	(su_optab): New code attribute.
-+	(su): Likewise.
-+	* config/arm/vfp.md (l<vrint_pattern><su_optab><mode>si2): New pattern.
-+
-+2014-10-08  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215471.
-+	2014-09-22  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* config/aarch64/geniterators.sh: New.
-+	* config/aarch64/iterators.md (VDQF_DF): New.
-+	* config/aarch64/t-aarch64: Generate aarch64-builtin-iterators.h.
-+	* config/aarch64/aarch64-builtins.c (BUILTIN_*) Remove.
-+
-+2014-10-08  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215206, r215207, r215208.
-+	2014-09-12  Wilco Dijkstra  <wilco.dijkstra@arm.com>
-+
-+	* gcc/config/aarch64/aarch64.c (cortexa57_regmove_cost): New cost table
-+	for A57.
-+	(cortexa53_regmove_cost): New cost table for A53.  Increase GP2FP/FP2GP
-+	cost to spilling from integer to FP registers.
-+
-+	2014-09-12  Wilco Dijkstra  <wilco.dijkstra@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_register_move_cost): Fix Q register
-+	move handling.
-+	(generic_regmove_cost): Undo raised FP2FP move cost as Q register moves
-+	are now handled correctly.
-+
-+	2014-09-12  Wilco Dijkstra  <wilco.dijkstra@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_register_move_cost): Add cost
-+	handling of CALLER_SAVE_REGS and POINTER_REGS.
-+
-+2014-10-07  Yvan Roux  <yvan.roux@linaro.org>
-+ 
-+	Backport from trunk r214824.
-+	2014-09-02  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/aarch64/predicates.md (aarch64_comparison_operation):
-+	New special predicate.
-+	* config/aarch64/aarch64.md (*csinc2<mode>_insn): Use
-+	aarch64_comparison_operation instead of matching an operator.
-+	Update operand numbers.
-+	(csinc3<mode>_insn): Likewise.
-+	(*csinv3<mode>_insn): Likewise.
-+	(*csneg3<mode>_insn): Likewise.
-+	(ffs<mode>2): Update gen_csinc3<mode>_insn callsite.
-+	* config/aarch64/aarch64.c (aarch64_get_condition_code):
-+	Return -1 instead of aborting on invalid condition codes.
-+	(aarch64_print_operand): Update aarch64_get_condition_code callsites
-+	to assert that the returned condition code is valid.
-+	* config/aarch64/aarch64-protos.h (aarch64_get_condition_code): Export.
-+
-+2014-10-07  Venkataramanan Kumar  <venkataramanan.kumar@linaro.org>
-+
-+	Backport from trunk r209643, r211881.
-+	2014-06-22  Richard Henderson  <rth@redhat.com>
-+
-+	PR target/61565
-+	* compare-elim.c (struct comparison): Add eh_note.
-+	(find_comparison_dom_walker::before_dom_children): Don't eliminate
-+	a redundant comparison in a different EH region.  Purge EH edges if
-+	necessary.
-+
-+	2014-04-22  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
-+
-+	* config/aarch64/aarch64.c (TARGET_FLAGS_REGNUM): Define.
-+
-+2014-10-06  Charles Baylis  <charles.baylis@linaro.org>
-+
-+	Backport from trunk r214945.
-+	2014-09-05  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* config/aarch64/aarch64-builtins.c (aarch64_simd_expand_args): Replace
-+	varargs with pointer parameter.
-+	(aarch64_simd_expand_builtin): pass pointer into previous.
-+
-+2014-10-06  Kugan Vivekanandarajah  <kugan.vivekanandarajah@linaro.org>
-+
-+	Backport from trunk r214944.
-+	2014-09-05  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/arm/cortex-a53.md (cortex_a53_alu_shift): Add alu_ext,
-+	alus_ext.
-+
-+2014-10-06  Venkataramanan Kumar  <venkataramanan.kumar@linaro.org>
-+
-+	Backport from trunk r214943.
-+	2014-09-05  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* config/aarch64/aarch64-simd.md (aarch64_rbit<mode>): New pattern.
-+	* config/aarch64/aarch64-simd-builtins.def (rbit): New builtin.
-+	* config/aarch64/arm_neon.h (vrbit_s8, vrbit_u8, vrbitq_s8, vrbitq_u8):
-+	Replace temporary asm with call to builtin.
-+	(vrbit_p8, vrbitq_p8): New functions.
-+
-+2014-10-06  Michael Collison  <michael.collison@linaro.org>
-+
-+	Backport from trunk r214886.
-+	2014-09-03  Richard Henderson  <rth@redhat.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_popwb_single_reg): Remove.
-+	(aarch64_popwb_pair_reg): Remove.
-+	(aarch64_set_frame_expr): Remove.
-+	(aarch64_restore_callee_saves): Add CFI_OPS argument; fill it with
-+	the restore ops performed by the insns generated.
-+	(aarch64_expand_epilogue): Attach CFI_OPS to the stack deallocation
-+	insn.  Perform the calls_eh_return addition later; do not attempt to
-+	preserve the CFA in that case.  Don't use aarch64_set_frame_expr.
-+	(aarch64_expand_prologue): Use REG_CFA_ADJUST_CFA directly, or no
-+	special markup at all.  Load cfun->machine->frame.hard_fp_offset
-+	into a local variable.
-+	(aarch64_frame_pointer_required): Don't check calls_alloca.
-+
-+2014-10-06  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215385.
-+	2014-09-19  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* config/aarch64/aarch64.md (stack_protect_test_<mode>): Mark
-+	scratch register as written.
-+
-+2014-10-06  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215346.
-+	2014-09-18  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/arm/neon.md (*movmisalign<mode>_neon_load): Change type
-+	to neon_load1_1reg<q>.
-+
-+2014-10-06  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215321.
-+	2014-09-17  Andrew Stubbs  <ams@codesourcery.com>
-+
-+	* config/arm/arm.c (arm_option_override): Reject -mfpu=neon
-+	when architecture is older than ARMv7.
-+
-+2014-10-06  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215260.
-+	2014-09-14  David Sherwood  <david.sherwood@arm.com>
-+
-+	* gcc.target/aarch64/vdup_lane_2.c (force_simd): Emit simd mov.
-+
-+2014-10-06  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215205.
-+	2014-09-12  Wilco Dijkstra  <wilco.dijkstra@arm.com>
-+
-+	* gcc/ree.c (combine_reaching_defs): Ensure inserted copy don't change
-+	the number of hard registers.
-+
-+2014-10-06  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215136.
-+	2014-09-10  Xinliang David Li  <davidxl@google.com>
-+
-+	PR target/63209
-+	* config/arm/arm.md (movcond_addsi): Handle case where source
-+	and target operands are the same.
-+
-+2014-10-06  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215086.
-+	2014-09-09  Marcus Shawcroft  <marcus.shawcroft@arm.com>
-+	Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
-+
-+	 * config/aarch64/aarch64-elf-raw.h (ENDFILE_SPEC): Add crtfastmath.o.
-+         * config/aarch64/aarch64-linux.h (GNU_USER_TARGET_MATH_ENDFILE_SPEC):
-+	Define.
-+        (ENDFILE_SPEC): Define and use GNU_USER_TARGET_MATH_ENDFILE_SPEC.
-+
-+2014-10-06  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215067.
-+	2014-09-09  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* config/arm/arm.c (NEON_COPYSIGNF): New enum.
-+	(arm_init_neon_builtins): Support NEON_COPYSIGNF.
-+	(arm_builtin_vectorized_function): Likewise.
-+	* config/arm/arm_neon_builtins.def: New macro for copysignf.
-+	* config/arm/neon.md (neon_copysignf<mode>): New pattern for vector
-+	copysignf.
-+
-+2014-10-03  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215050, r215051, r215052, r215053, r215054,
-+	r215055, r215056.
-+	2014-09-09  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/arm/arm.md (vfp_pop_multiple_with_writeback): Use vldm
-+	mnemonic instead of fldmfdd.
-+	* config/arm/arm.c (vfp_output_fstmd): Rename to...
-+	(vfp_output_vstmd): ... This.  Convert output to UAL syntax.
-+	Output vpush when address register is SP.
-+	* config/arm/arm-protos.h (vfp_output_fstmd): Rename to...
-+	(vfp_output_vstmd): ... This.
-+	* config/arm/vfp.md (push_multi_vfp): Update call to
-+	vfp_output_vstmd.
-+
-+	2014-09-09  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/arm/vfp.md (*movcc_vfp): Use UAL syntax.
-+
-+	2014-09-09  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/arm/vfp.md (*sqrtsf2_vfp): Use UAL assembly syntax.
-+	(*sqrtdf2_vfp): Likewise.
-+	(*cmpsf_vfp): Likewise.
-+	(*cmpsf_trap_vfp): Likewise.
-+	(*cmpdf_vfp): Likewise.
-+	(*cmpdf_trap_vfp): Likewise.
-+
-+	2014-09-09  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/arm/vfp.md (*extendsfdf2_vfp): Use UAL assembly syntax.
-+	(*truncdfsf2_vfp): Likewise.
-+	(*truncsisf2_vfp): Likewise.
-+	(*truncsidf2_vfp): Likewise.
-+	(fixuns_truncsfsi2): Likewise.
-+	(fixuns_truncdfsi2): Likewise.
-+	(*floatsisf2_vfp): Likewise.
-+	(*floatsidf2_vfp): Likewise.
-+	(floatunssisf2): Likewise.
-+	(floatunssidf2): Likewise.
-+
-+	2014-09-09  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/arm/vfp.md (*mulsf3_vfp): Use UAL assembly syntax.
-+	(*muldf3_vfp): Likewise.
-+	(*mulsf3negsf_vfp): Likewise.
-+	(*muldf3negdf_vfp): Likewise.
-+	(*mulsf3addsf_vfp): Likewise.
-+	(*muldf3adddf_vfp): Likewise.
-+	(*mulsf3subsf_vfp): Likewise.
-+	(*muldf3subdf_vfp): Likewise.
-+	(*mulsf3negsfaddsf_vfp): Likewise.
-+	(*fmuldf3negdfadddf_vfp): Likewise.
-+	(*mulsf3negsfsubsf_vfp): Likewise.
-+	(*muldf3negdfsubdf_vfp): Likewise.
-+
-+	2014-09-09  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/arm/vfp.md (*abssf2_vfp): Use UAL assembly syntax.
-+	(*absdf2_vfp): Likewise.
-+	(*negsf2_vfp): Likewise.
-+	(*negdf2_vfp): Likewise.
-+	(*addsf3_vfp): Likewise.
-+	(*adddf3_vfp): Likewise.
-+	(*subsf3_vfp): Likewise.
-+	(*subdf3_vfp): Likewise.
-+	(*divsf3_vfp): Likewise.
-+	(*divdf3_vfp): Likewise.
-+
-+	2014-09-09  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/arm/arm.c (output_move_vfp): Use UAL syntax for load/store
-+	multiple.
-+	(arm_print_operand): Don't convert real values to decimal
-+	representation in default case.
-+	(fp_immediate_constant): Delete.
-+	* config/arm/arm-protos.h (fp_immediate_constant): Likewise.
-+	* config/arm/vfp.md (*arm_movsi_vfp): Convert to VFP moves to UAL
-+	syntax.
-+	(*thumb2_movsi_vfp): Likewise.
-+	(*movdi_vfp): Likewise.
-+	(*movdi_vfp_cortexa8): Likewise.
-+	(*movhf_vfp_neon): Likewise.
-+	(*movhf_vfp): Likewise.
-+	(*movsf_vfp): Likewise.
-+	(*thumb2_movsf_vfp): Likewise.
-+	(*movdf_vfp): Likewise.
-+	(*thumb2_movdf_vfp): Likewise.
-+	(*movsfcc_vfp): Likewise.
-+	(*thumb2_movsfcc_vfp): Likewise.
-+	(*movdfcc_vfp): Likewise.
-+	(*thumb2_movdfcc_vfp): Likewise.
-+
-+2014-10-03  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r214959.
-+	2014-09-05  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/arm/cortex-a53.md (cortex_a53_fpalu): Add f_rints, f_rintd,
-+	f_minmaxs, f_minmaxd types.
-+
-+2014-10-03  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r214947.
-+	2014-09-05  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers):
-+	Remove qualifier_const_pointer, update comment.
-+
-+2014-10-03  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r214940.
-+	2014-09-05  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* config/aarch64/aarch64.md (sibcall_value_insn): Give operand 1
-+	DImode.
-+
-+2014-10-03  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r213090.
-+	2014-07-26  Andrew Pinski  <apinski@cavium.com>
-+
-+	* config/aarch64/aarch64.md (*extr_insv_lower_reg<mode>): Remove +
-+	from the read only register.
-+
-+2014-09-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	* LINARO-VERSION: Bump version.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+	* LINARO-VERSION: Update.
-+
-+2014-09-09  Venkataramanan Kumar  <venkataramanan.kumar@linaro.org>
-+
-+	Backport from trunk r215004.
-+	2014-09-07 Venkataramanan Kumar <venkataramanan.kumar@linaro.org>
-+
-+	PR target/63190
-+	* config/aarch64/aarch64.md (stack_protect_test_<mode>) Add register
-+	constraint for operand0 and remove write only modifier from operand3.
-+
-+2014-09-09  Michael Collison  <michael.collison@linaro.org>
-+
-+	Backport from trunk r212178
-+	2014-06-30  Joseph Myers  <joseph@codesourcery.com>
-+
-+	* var-tracking.c (add_stores): Return instead of asserting if old
-+	and new values for conditional store are the same.
-+
-+2014-09-03  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Revert:
-+	2014-09-03  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r213712.
-+	2014-08-07  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/aarch64/aarch64.md (absdi2): Set simd attribute.
-+	(aarch64_reload_mov<mode>): Predicate on TARGET_FLOAT.
-+	(aarch64_movdi_<mode>high): Likewise.
-+	(aarch64_mov<mode>high_di): Likewise.
-+	(aarch64_movdi_<mode>low): Likewise.
-+	(aarch64_mov<mode>low_di): Likewise.
-+	(aarch64_movtilow_tilow): Likewise.
-+	Add comment explaining usage of fp,simd attributes and of
-+	TARGET_FLOAT and TARGET_SIMD.
-+
-+2014-09-03  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r213712.
-+	2014-08-07  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/aarch64/aarch64.md (absdi2): Set simd attribute.
-+	(aarch64_reload_mov<mode>): Predicate on TARGET_FLOAT.
-+	(aarch64_movdi_<mode>high): Likewise.
-+	(aarch64_mov<mode>high_di): Likewise.
-+	(aarch64_movdi_<mode>low): Likewise.
-+	(aarch64_mov<mode>low_di): Likewise.
-+	(aarch64_movtilow_tilow): Likewise.
-+	Add comment explaining usage of fp,simd attributes and of
-+	TARGET_FLOAT and TARGET_SIMD.
-+
-+2014-09-03  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r214526.
-+	2014-08-26  Joseph Myers  <joseph@codesourcery.com>
-+
-+	PR target/60606
-+	PR target/61330
-+	* varasm.c (make_decl_rtl): Clear DECL_ASSEMBLER_NAME and
-+	DECL_HARD_REGISTER and return for invalid register specifications.
-+	* cfgexpand.c (expand_one_var): If expand_one_hard_reg_var clears
-+	DECL_HARD_REGISTER, call expand_one_error_var.
-+	* config/arm/arm.c (arm_hard_regno_mode_ok): Do not allow
-+	CC_REGNUM with non-MODE_CC modes.
-+	(arm_regno_class): Return NO_REGS for PC_REGNUM.
-+
-+2014-09-03  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r214503.
-+	2014-08-26  Evandro Menezes <e.menezes@samsung.com>
-+
-+	* config/arm/aarch64/aarch64.c (generic_addrcost_table): Delete
-+	qi cost; add di cost.
-+	(cortexa57_addrcost_table): Likewise.
-+
-+2014-09-03  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r213659.
-+	2014-08-06  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_evpc_dup): Enable for bigendian.
-+	(aarch64_expand_vec_perm_const): Check for dup before zip.
-+
-+2014-09-02  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r213651.
-+	2014-08-06  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_classify_address): Use REG_P and
-+	CONST_INT_P instead of GET_CODE and compare.
-+	(aarch64_select_cc_mode): Likewise.
-+	(aarch64_print_operand): Likewise.
-+	(aarch64_rtx_costs): Likewise.
-+	(aarch64_simd_valid_immediate): Likewise.
-+	(aarch64_simd_check_vect_par_cnst_half): Likewise.
-+	(aarch64_simd_emit_pair_result_insn): Likewise.
-+
-+2014-08-29  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r212978.
-+	2014-07-24  Andreas Schwab  <schwab@suse.de>
-+
-+	* lib/target-supports.exp (check_effective_target_arm_nothumb):
-+	Also check for __arm__.
-+
-+2014-08-29  Christophe Lyon  <christophe.lyon@linaro.org>
-+
-+	Fix backport from trunk 211440:
-+	* config.gcc (aarch64*-*-*): Restore need_64bit_hwint=yes.
-+
-+	This is necessary to build aarch64* compilers on i686 host.
-+
-+2014-08-26  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r213627.
-+	2014-08-05  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* config/aarch64/aarch64-builtins.c
-+	(aarch64_simd_builtin_type_mode): Delete.
-+	(v8qi_UP): Remap to V8QImode.
-+	(v4hi_UP): Remap to V4HImode.
-+	(v2si_UP): Remap to V2SImode.
-+	(v2sf_UP): Remap to V2SFmode.
-+	(v1df_UP): Remap to V1DFmode.
-+	(di_UP): Remap to DImode.
-+	(df_UP): Remap to DFmode.
-+	(v16qi_UP):V16QImode.
-+	(v8hi_UP): Remap to V8HImode.
-+	(v4si_UP): Remap to V4SImode.
-+	(v4sf_UP): Remap to V4SFmode.
-+	(v2di_UP): Remap to V2DImode.
-+	(v2df_UP): Remap to V2DFmode.
-+	(ti_UP): Remap to TImode.
-+	(ei_UP): Remap to EImode.
-+	(oi_UP): Remap to OImode.
-+	(ci_UP): Map to CImode.
-+	(xi_UP): Remap to XImode.
-+	(si_UP): Remap to SImode.
-+	(sf_UP): Remap to SFmode.
-+	(hi_UP): Remap to HImode.
-+	(qi_UP): Remap to QImode.
-+	(aarch64_simd_builtin_datum): Make mode a machine_mode.
-+	(VAR1): Build builtin name.
-+	(aarch64_init_simd_builtins): Remove dead code.
-+
-+2014-08-26  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r213713.
-+	2014-08-07  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/arm/arm.md (*cmov<mode>): Set type attribute to fcsel.
-+	* config/arm/types.md (f_sels, f_seld): Delete.
-+
-+2014-08-26  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r213711.
-+	2014-08-07  Ian Bolton  <ian.bolton@arm.com>
-+		    Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_expand_mov_immediate):
-+	Use MOVN when one of the half-words is 0xffff.
-+
-+2014-08-26  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r213632.
-+	2014-08-05  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/arm/cortex-a15.md (cortex_a15_alu_shift): Add crc type
-+	to reservation.
-+	* config/arm/cortex-a53.md (cortex_a53_alu_shift): Likewise.
-+
-+2014-08-26  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r213630.
-+	2014-08-05  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/arm/arm.md (clzsi2): Set predicable_short_it attr to no.
-+	(rbitsi2): Likewise.
-+	(*arm_rev): Set predicable and predicable_short_it attributes.
-+
-+2014-08-26  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r213557.
-+	2014-08-04  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+		    James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* doc/md.texi (clrsb): Document.
-+	(clz): Change reference to x into operand 1.
-+	(ctz): Likewise.
-+	(popcount): Likewise.
-+
-+2014-08-26  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r213551, r213556.
-+	2014-08-04  Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
-+		    Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* sched-deps.c (try_group_insn): Generalise macro fusion hook usage
-+	to any two insns.  Update comment.  Rename to sched_macro_fuse_insns.
-+	(sched_analyze_insn): Update use of try_group_insn to
-+	sched_macro_fuse_insns.
-+	* config/i386/i386.c (ix86_macro_fusion_pair_p): Reject 2nd
-+	arguments that are not conditional jumps.
-+
-+2014-08-26  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r213490.
-+	2014-08-01  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* config/aarch64/aarch64-simd-builtins.def (dup_lane, get_lane): Delete.
-+
-+2014-08-26  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r213488.
-+	2014-08-01  Jiong Wang <jiong.wang@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_classify_address): Accept all offset
-+	for frame access when strict_p is false.
-+
-+2014-08-26  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r213485, r213486, r213487.
-+	2014-08-01  Renlin Li <renlin.li@arm.com>
-+		    Jiong Wang <jiong.wang@arm.com>
-+
-+	* config/aarch64/aarch64.c (offset_7bit_signed_scaled_p): Rename to
-+	aarch64_offset_7bit_signed_scaled_p, remove static and use it.
-+	* config/aarch64/aarch64-protos.h (aarch64_offset_7bit_signed_scaled_p):
-+	Declaration.
-+	* config/aarch64/predicates.md (aarch64_mem_pair_offset): Define new
-+	predicate.
-+	* config/aarch64/aarch64.md (loadwb_pair, storewb_pair): Use
-+	aarch64_mem_pair_offset.
-+
-+	2014-08-01  Jiong Wang <jiong.wang@arm.com>
-+
-+	* config/aarch64/aarch64.md (loadwb_pair<GPI:mode>_<P:mode>): Fix
-+	offset.
-+	(loadwb_pair<GPI:mode>_<P:mode>): Likewise.
-+	* config/aarch64/aarch64.c (aarch64_gen_loadwb_pair): Likewise.
-+
-+2014-08-26  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r213379.
-+	2014-07-31  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* config/aarch64/aarch64-builtins.c
-+	(aarch64_gimple_fold_builtin): Don't fold reduction operations for
-+	BYTES_BIG_ENDIAN.
-+
-+2014-08-26  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r213378.
-+	2014-07-31  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_simd_vect_par_cnst_half): Vary
-+	the generated mask based on BYTES_BIG_ENDIAN.
-+	(aarch64_simd_check_vect_par_cnst_half): New.
-+	* config/aarch64/aarch64-protos.h
-+	(aarch64_simd_check_vect_par_cnst_half): New.
-+	* config/aarch64/predicates.md (vect_par_cnst_hi_half): Refactor
-+	the check out to aarch64_simd_check_vect_par_cnst_half.
-+	(vect_par_cnst_lo_half): Likewise.
-+	* config/aarch64/aarch64-simd.md
-+	(aarch64_simd_move_hi_quad_<mode>): Always use vec_par_cnst_lo_half.
-+	(move_hi_quad_<mode>): Always generate a low mask.
-+
-+2014-08-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r212927, r213304.
-+	2014-07-30  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* config/arm/arm.c (arm_get_frame_offsets): Adjust condition for
-+	Thumb2.
-+
-+	2014-07-23  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* config/arm/arm.c (arm_get_frame_offsets): If both r3 and other
-+	callee-saved registers are available for padding purpose
-+	and r3 is not mandatory, then prefer use those callee-saved
-+	instead of r3.
-+
-+2014-08-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r211717, r213692.
-+	2014-08-07  Kugan Vivekanandarajah  <kuganv@linaro.org>
-+
-+	* config/arm/arm.c (bdesc_2arg): Fix typo.
-+	(arm_atomic_assign_expand_fenv): Remove The default implementation.
-+
-+	2014-06-17  Kugan Vivekanandarajah  <kuganv@linaro.org>
-+
-+	* config/arm/arm.c (arm_atomic_assign_expand_fenv): call
-+	default_atomic_assign_expand_fenv for !TARGET_HARD_FLOAT.
-+	(arm_init_builtins) : Initialize builtins __builtins_arm_set_fpscr and
-+	__builtins_arm_get_fpscr only when TARGET_HARD_FLOAT.
-+	* config/arm/vfp.md (set_fpscr): Make pattern conditional on
-+	TARGET_HARD_FLOAT.
-+	(get_fpscr) : Likewise.
-+
-+2014-08-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r212989, r213628.
-+	2014-08-05  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* convert.c (convert_to_integer): Guard transformation to lrint by
-+	-fno-math-errno.
-+
-+	2014-07-24  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	PR middle-end/61876
-+	* convert.c (convert_to_integer): Do not convert BUILT_IN_ROUND and cast
-+	when flag_errno_math is on.
-+
-+2014-08-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	* LINARO-VERSION: Bump version.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+	* LINARO-VERSION: Update.
-+
-+2014-08-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r212912, r212913.
-+	2014-07-22  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_rtx_costs): Handle CLRSB, CLZ.
-+	(case UNSPEC): Handle UNSPEC_RBIT.
-+
-+	2014-07-22  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/aarch64/aarch64.md: Delete UNSPEC_CLS.
-+	(clrsb<mode>2): Use clrsb RTL code instead of UNSPEC_CLS.
-+
-+2014-08-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r213555.
-+	2014-08-04  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	PR target/61713
-+	* gcc/optabs.c (expand_atomic_test_and_set): Do not try to emit
-+	move to subtarget in serial version if result is ignored.
-+
-+2014-08-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r213376.
-+	2014-07-31  Charles Baylis  <charles.baylis@linaro.org>
-+
-+	PR target/61948
-+	* config/arm/neon.md (ashldi3_neon): Don't emit arm_ashldi3_1bit unless
-+	constraints are satisfied.
-+	(<shift>di3_neon): Likewise.
-+
-+2014-08-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r211270, r211271, r211273, r211275, r212943,
-+	r212945, r212946, r212947, r212949, r212950, r212951, r212952, r212954,
-+	r212955, r212956, r212957, r212958, r212976, r212996, r212997, r212999,
-+	r213000.
-+	2014-07-24  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_popwb_single_reg): New function.
-+	(aarch64_expand_epilogue): Optimize epilogue when !frame_pointer_needed.
-+
-+	2014-07-24  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_pushwb_single_reg): New function.
-+	(aarch64_expand_prologue): Optimize prologue when !frame_pointer_needed.
-+
-+	2014-07-24  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_restore_callee_saves)
-+	(aarch64_save_callee_saves): New parameter "skip_wb".
-+	(aarch64_expand_prologue, aarch64_expand_epilogue): Update call site.
-+
-+	2014-07-24  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* config/aarch64/aarch64.h (frame): New fields "wb_candidate1" and
-+	"wb_candidate2".
-+	* config/aarch64/aarch64.c (aarch64_layout_frame): Initialize above.
-+
-+	2014-07-24  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_expand_epilogue): Don't
-+	subtract outgoing area size when restoring stack_pointer_rtx.
-+
-+	2014-07-23  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_popwb_pair_reg)
-+	(aarch64_gen_loadwb_pair): New helper function.
-+	(aarch64_expand_epilogue): Simplify code using new helper functions.
-+	* config/aarch64/aarch64.md (loadwb_pair<GPF:mode>_<P:mode>): Define.
-+
-+	2014-07-23  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_pushwb_pair_reg)
-+	(aarch64_gen_storewb_pair): New helper function.
-+	(aarch64_expand_prologue): Simplify code using new helper functions.
-+	* config/aarch64/aarch64.md (storewb_pair<GPF:mode>_<P:mode>): Define.
-+
-+	2014-07-23  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* config/aarch64/aarch64.md: (aarch64_save_or_restore_callee_saves):
-+	Rename to aarch64_save_callee_saves, remove restore code.
-+	(aarch64_restore_callee_saves): New function.
-+
-+	2014-07-23  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_save_or_restore_fprs): Deleted.
-+	(aarch64_save_callee_saves): New function to handle reg save
-+	for both core and vectore regs.
-+
-+	2014-07-23  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_gen_load_pair)
-+	(aarch64_gen_store_pair): New helper function.
-+	(aarch64_save_or_restore_callee_save_registers)
-+	(aarch64_save_or_restore_fprs): Use new helper functions.
-+
-+	2014-07-23  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_next_callee_save): New function.
-+	(aarch64_save_or_restore_callee_save_registers)
-+	(aarch64_save_or_restore_fprs): Use aarch64_next_callee_save.
-+
-+	2014-07-23  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* config/aarch64/aarch64.c
-+	(aarch64_save_or_restore_callee_save_registers)
-+	(aarch64_save_or_restore_fprs): Hoist calculation of register rtx.
-+
-+	2014-07-23  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* config/aarch64/aarch64.c
-+	(aarch64_save_or_restore_callee_save_registers)
-+	(aarch64_save_or_restore_fprs): Remove 'increment'.
-+
-+	2014-07-23  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* config/aarch64/aarch64.c
-+	(aarch64_save_or_restore_callee_save_registers)
-+	(aarch64_save_or_restore_fprs): Use register offset in
-+	cfun->machine->frame.reg_offset.
-+
-+	2014-07-23  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* config/aarch64/aarch64.c
-+	(aarch64_save_or_restore_callee_save_registers)
-+	(aarch64_save_or_restore_fprs): Remove base_rtx.
-+
-+	2014-07-23  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* config/aarch64/aarch64.c
-+	(aarch64_save_or_restore_callee_save_registers): Rename 'offset'
-+	to 'start_offset'.  Remove local variable 'start_offset'.
-+
-+	2014-07-23  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_save_or_restore_fprs): Change
-+	type to HOST_WIDE_INT.
-+
-+	2014-07-23  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_expand_prologue)
-+	(aarch64_save_or_restore_fprs)
-+	(aarch64_save_or_restore_callee_save_registers): GNU-Stylize code.
-+
-+	2014-06-05  Marcus Shawcroft  <marcus.shawcroft@arm.com>
-+
-+	* config/aarch64/aarch64.h (aarch64_frame): Add hard_fp_offset and
-+	frame_size.
-+	* config/aarch64/aarch64.c (aarch64_layout_frame): Initialize
-+	aarch64_frame hard_fp_offset and frame_size.
-+	(aarch64_expand_prologue): Use aarch64_frame hard_fp_offset and
-+	frame_size; remove original_frame_size.
-+	(aarch64_expand_epilogue, aarch64_final_eh_return_addr): Likewise.
-+	(aarch64_initial_elimination_offset): Remove frame_size and
-+	offset.  Use aarch64_frame frame_size.
-+
-+	2014-06-05  Marcus Shawcroft  <marcus.shawcroft@arm.com>
-+		    Jiong Wang  <jiong.wang@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_layout_frame): Correct
-+	initialization of R30 offset.  Update offset.  Iterate core
-+	regisers upto X30.  Remove X29, X30 specific code.
-+
-+	2014-06-05  Marcus Shawcroft  <marcus.shawcroft@arm.com>
-+		    Jiong Wang  <jiong.wang@arm.com>
-+
-+	* config/aarch64/aarch64.c (SLOT_NOT_REQUIRED, SLOT_REQUIRED): Define.
-+	(aarch64_layout_frame): Use SLOT_NOT_REQUIRED and SLOT_REQUIRED.
-+	(aarch64_register_saved_on_entry): Adjust test.
-+
-+	2014-06-05  Marcus Shawcroft  <marcus.shawcroft@arm.com>
-+
-+	* config/aarch64/aarch64.h (machine_function): Move
-+	saved_varargs_size from here...
-+	(aarch64_frameGTY): ... to here.
-+
-+	* config/aarch64/aarch64.c (aarch64_expand_prologue)
-+	(aarch64_expand_epilogue, aarch64_final_eh_return_addr)
-+	(aarch64_initial_elimination_offset)
-+	(aarch64_setup_incoming_varargs): Adjust location of
-+	saved_varargs_size.
-+
-+2014-08-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r212753.
-+	2014-07-17  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_frint_unspec_p): New function.
-+	(aarch64_rtx_costs): Handle FIX, UNSIGNED_FIX, UNSPEC.
-+
-+2014-08-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r212752.
-+	2014-07-17  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/aarch64/arm_neon.h (vmlal_high_lane_s16): Fix type.
-+	(vmlal_high_lane_s32): Likewise.
-+	(vmlal_high_lane_u16): Likewise.
-+	(vmlal_high_lane_u32): Likewise.
-+	(vmlsl_high_lane_s16): Likewise.
-+	(vmlsl_high_lane_s32): Likewise.
-+	(vmlsl_high_lane_u16): Likewise.
-+	(vmlsl_high_lane_u32): Likewise.
-+
-+2014-08-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r212512.
-+	2014-07-14  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/arm/cortex-a15.md (cortex_a15_alu): Handle clz, rbit.
-+	* config/arm/cortex-a5.md (cortex_a5_alu): Likewise.
-+	* config/arm/cortex-a53.md (cortex_a53_alu): Likewise.
-+	* config/arm/cortex-a7.md (cortex_a7_alu_reg): Likewise.
-+	* config/arm/cortex-a9.md (cortex_a9_dp): Likewise.
-+	* config/arm/cortex-m4.md (cortex_m4_alu): Likewise.
-+	* config/arm/cortex-r4.md (cortex_r4_alu): Likewise.
-+
-+2014-08-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r212358.
-+	2014-07-08  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/arm/arm.c (cortexa5_extra_costs): New table.
-+	(arm_cortex_a5_tune): Use cortexa5_extra_costs.
-+
-+2014-08-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r212296.
-+	2014-07-04  Tom de Vries  <tom@codesourcery.com>
-+
-+	* config/aarch64/aarch64-simd.md
-+	(define_insn "vec_unpack_trunc_<mode>"): Fix constraint.
-+
-+2014-08-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r212142, r212225.
-+	2014-07-02  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_expand_vec_perm): Delete unused
-+	variable i.
-+
-+	2014-06-30  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* config/aarch64/aarch64-simd.md (vec_perm): Enable for bigendian.
-+	* config/aarch64/aarch64.c (aarch64_expand_vec_perm): Remove assert
-+	against bigendian and adjust indices.
-+
-+2014-08-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r211779.
-+	2014-06-18  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/arm/arm_neon.h (vadd_f32): Change #ifdef to __FAST_MATH.
-+
-+2014-07-30  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r211503.
-+	2014-06-12  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* config/aarch64/arm_neon.h (vmlaq_n_f64, vmlsq_n_f64, vrsrtsq_f64,
-+	vcge_p8, vcgeq_p8, vcgez_p8, vcgez_u8, vcgez_u16, vcgez_u32, vcgez_u64,
-+	vcgezq_p8, vcgezq_u8, vcgezq_u16, vcgezq_u32, vcgezq_u64, vcgezd_u64,
-+	vcgt_p8, vcgtq_p8, vcgtz_p8, vcgtz_u8, vcgtz_u16, vcgtz_u32, vcgtz_u64,
-+	vcgtzq_p8, vcgtzq_u8, vcgtzq_u16, vcgtzq_u32, vcgtzq_u64, vcgtzd_u64,
-+	vcle_p8, vcleq_p8, vclez_p8, vclez_u64, vclezq_p8, vclezd_u64, vclt_p8,
-+	vcltq_p8, vcltz_p8, vcltzq_p8, vcltzd_u64): Remove functions as they are
-+	not in the spec.
-+
-+2014-07-30  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r211140.
-+	2014-06-02  Marcus Shawcroft  <marcus.shawcroft@arm.com>
-+
-+	* config/aarch64/aarch64.md (set_fpcr): Drop ISB after FPCR write.
-+
-+2014-07-29  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	* LINARO-VERSION: Bump version.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+	* LINARO-VERSION: Update.
-+
-+2014-07-20  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Revert:
-+	2014-07-16  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r211129.
-+	2014-06-02  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
-+
-+	PR target/61154
-+	* config/arm/arm.h (TARGET_SUPPORTS_WIDE_INT): Define.
-+	* config/arm/arm.md (mov64 splitter): Replace const_double_operand
-+	with immediate_operand.
-+
-+2014-07-19  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	* LINARO-VERSION: Bump version.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+	* LINARO-VERSION: Update.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r211887, r211899.
-+	2014-06-23  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* config/aarch64/aarch64.md (addsi3_aarch64): Set "simd" attr to
-+	"yes" where needed.
-+
-+	2014-06-23  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* config/aarch64/aarch64.md (*addsi3_aarch64): Add alternative in
-+	vector registers.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r211440.
-+	2014-06-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config.gcc (aarch64*-*-*): Add arm_acle.h to extra headers.
-+	* Makefile.in (TEXI_GCC_FILES): Add aarch64-acle-intrinsics.texi to
-+	dependencies.
-+	* config/aarch64/aarch64-builtins.c (AARCH64_CRC32_BUILTINS): Define.
-+	(aarch64_crc_builtin_datum): New struct.
-+	(aarch64_crc_builtin_data): New.
-+	(aarch64_init_crc32_builtins): New function.
-+	(aarch64_init_builtins): Initialise CRC32 builtins when appropriate.
-+	(aarch64_crc32_expand_builtin): New.
-+	(aarch64_expand_builtin): Add CRC32 builtin expansion case.
-+	* config/aarch64/aarch64.h (TARGET_CPU_CPP_BUILTINS): Define
-+	__ARM_FEATURE_CRC32 when appropriate.
-+	(TARGET_CRC32): Define.
-+	* config/aarch64/aarch64.md (UNSPEC_CRC32B, UNSPEC_CRC32H,
-+	UNSPEC_CRC32W, UNSPEC_CRC32X, UNSPEC_CRC32CB, UNSPEC_CRC32CH,
-+	UNSPEC_CRC32CW, UNSPEC_CRC32CX): New unspec values.
-+	(aarch64_<crc_variant>): New pattern.
-+	* config/aarch64/arm_acle.h: New file.
-+	* config/aarch64/iterators.md (CRC): New int iterator.
-+	(crc_variant, crc_mode): New int attributes.
-+	* doc/aarch64-acle-intrinsics.texi: New file.
-+	* doc/extend.texi (aarch64): Document aarch64 ACLE intrinsics.
-+	Include aarch64-acle-intrinsics.texi.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r211174.
-+	2014-06-03  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* config/aarch64/aarch64-simd.md (aarch64_rev<REVERSE:rev-op><mode>):
-+	New pattern.
-+	* config/aarch64/aarch64.c (aarch64_evpc_rev): New function.
-+	(aarch64_expand_vec_perm_const_1): Add call to aarch64_evpc_rev.
-+	* config/aarch64/iterators.md (REVERSE): New iterator.
-+	(UNSPEC_REV64, UNSPEC_REV32, UNSPEC_REV16): New enum elements.
-+	(rev_op): New int_attribute.
-+	* config/aarch64/arm_neon.h (vrev16_p8, vrev16_s8, vrev16_u8,
-+	vrev16q_p8, vrev16q_s8, vrev16q_u8, vrev32_p8, vrev32_p16, vrev32_s8,
-+	vrev32_s16, vrev32_u8, vrev32_u16, vrev32q_p8, vrev32q_p16, vrev32q_s8,
-+	vrev32q_s16, vrev32q_u8, vrev32q_u16, vrev64_f32, vrev64_p8,
-+	vrev64_p16, vrev64_s8, vrev64_s16, vrev64_s32, vrev64_u8, vrev64_u16,
-+	vrev64_u32, vrev64q_f32, vrev64q_p8, vrev64q_p16, vrev64q_s8,
-+	vrev64q_s16, vrev64q_s32, vrev64q_u8, vrev64q_u16, vrev64q_u32):
-+	Replace temporary __asm__ with __builtin_shuffle.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r210216, r210218, r210219.
-+	2014-05-08  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
-+
-+	* config/arm/arm_neon.h: Update comment.
-+	* config/arm/neon-docgen.ml: Delete.
-+	* config/arm/neon-gen.ml: Delete.
-+	* doc/arm-neon-intrinsics.texi: Update comment.
-+
-+	2014-05-08  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
-+
-+	* config/arm/arm_neon_builtins.def (vadd, vsub): Only define the v2sf
-+	and v4sf versions.
-+	(vand, vorr, veor, vorn, vbic): Remove.
-+	* config/arm/neon.md (neon_vadd, neon_vsub, neon_vadd_unspec): Adjust
-+	iterator.
-+	(neon_vsub_unspec): Likewise.
-+	(neon_vorr, neon_vand, neon_vbic, neon_veor, neon_vorn): Remove.
-+
-+	2014-05-08  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
-+
-+	* config/arm/arm_neon.h (vadd_s8): GNU C implementation
-+	(vadd_s16): Likewise.
-+	(vadd_s32): Likewise.
-+	(vadd_f32): Likewise.
-+	(vadd_u8): Likewise.
-+	(vadd_u16): Likewise.
-+	(vadd_u32): Likewise.
-+	(vadd_s64): Likewise.
-+	(vadd_u64): Likewise.
-+	(vaddq_s8): Likewise.
-+	(vaddq_s16): Likewise.
-+	(vaddq_s32): Likewise.
-+	(vaddq_s64): Likewise.
-+	(vaddq_f32): Likewise.
-+	(vaddq_u8): Likewise.
-+	(vaddq_u16): Likewise.
-+	(vaddq_u32): Likewise.
-+	(vaddq_u64): Likewise.
-+	(vmul_s8): Likewise.
-+	(vmul_s16): Likewise.
-+	(vmul_s32): Likewise.
-+	(vmul_f32): Likewise.
-+	(vmul_u8): Likewise.
-+	(vmul_u16): Likewise.
-+	(vmul_u32): Likewise.
-+	(vmul_p8): Likewise.
-+	(vmulq_s8): Likewise.
-+	(vmulq_s16): Likewise.
-+	(vmulq_s32): Likewise.
-+	(vmulq_f32): Likewise.
-+	(vmulq_u8): Likewise.
-+	(vmulq_u16): Likewise.
-+	(vmulq_u32): Likewise.
-+	(vsub_s8): Likewise.
-+	(vsub_s16): Likewise.
-+	(vsub_s32): Likewise.
-+	(vsub_f32): Likewise.
-+	(vsub_u8): Likewise.
-+	(vsub_u16): Likewise.
-+	(vsub_u32): Likewise.
-+	(vsub_s64): Likewise.
-+	(vsub_u64): Likewise.
-+	(vsubq_s8): Likewise.
-+	(vsubq_s16): Likewise.
-+	(vsubq_s32): Likewise.
-+	(vsubq_s64): Likewise.
-+	(vsubq_f32): Likewise.
-+	(vsubq_u8): Likewise.
-+	(vsubq_u16): Likewise.
-+	(vsubq_u32): Likewise.
-+	(vsubq_u64): Likewise.
-+	(vand_s8): Likewise.
-+	(vand_s16): Likewise.
-+	(vand_s32): Likewise.
-+	(vand_u8): Likewise.
-+	(vand_u16): Likewise.
-+	(vand_u32): Likewise.
-+	(vand_s64): Likewise.
-+	(vand_u64): Likewise.
-+	(vandq_s8): Likewise.
-+	(vandq_s16): Likewise.
-+	(vandq_s32): Likewise.
-+	(vandq_s64): Likewise.
-+	(vandq_u8): Likewise.
-+	(vandq_u16): Likewise.
-+	(vandq_u32): Likewise.
-+	(vandq_u64): Likewise.
-+	(vorr_s8): Likewise.
-+	(vorr_s16): Likewise.
-+	(vorr_s32): Likewise.
-+	(vorr_u8): Likewise.
-+	(vorr_u16): Likewise.
-+	(vorr_u32): Likewise.
-+	(vorr_s64): Likewise.
-+	(vorr_u64): Likewise.
-+	(vorrq_s8): Likewise.
-+	(vorrq_s16): Likewise.
-+	(vorrq_s32): Likewise.
-+	(vorrq_s64): Likewise.
-+	(vorrq_u8): Likewise.
-+	(vorrq_u16): Likewise.
-+	(vorrq_u32): Likewise.
-+	(vorrq_u64): Likewise.
-+	(veor_s8): Likewise.
-+	(veor_s16): Likewise.
-+	(veor_s32): Likewise.
-+	(veor_u8): Likewise.
-+	(veor_u16): Likewise.
-+	(veor_u32): Likewise.
-+	(veor_s64): Likewise.
-+	(veor_u64): Likewise.
-+	(veorq_s8): Likewise.
-+	(veorq_s16): Likewise.
-+	(veorq_s32): Likewise.
-+	(veorq_s64): Likewise.
-+	(veorq_u8): Likewise.
-+	(veorq_u16): Likewise.
-+	(veorq_u32): Likewise.
-+	(veorq_u64): Likewise.
-+	(vbic_s8): Likewise.
-+	(vbic_s16): Likewise.
-+	(vbic_s32): Likewise.
-+	(vbic_u8): Likewise.
-+	(vbic_u16): Likewise.
-+	(vbic_u32): Likewise.
-+	(vbic_s64): Likewise.
-+	(vbic_u64): Likewise.
-+	(vbicq_s8): Likewise.
-+	(vbicq_s16): Likewise.
-+	(vbicq_s32): Likewise.
-+	(vbicq_s64): Likewise.
-+	(vbicq_u8): Likewise.
-+	(vbicq_u16): Likewise.
-+	(vbicq_u32): Likewise.
-+	(vbicq_u64): Likewise.
-+	(vorn_s8): Likewise.
-+	(vorn_s16): Likewise.
-+	(vorn_s32): Likewise.
-+	(vorn_u8): Likewise.
-+	(vorn_u16): Likewise.
-+	(vorn_u32): Likewise.
-+	(vorn_s64): Likewise.
-+	(vorn_u64): Likewise.
-+	(vornq_s8): Likewise.
-+	(vornq_s16): Likewise.
-+	(vornq_s32): Likewise.
-+	(vornq_s64): Likewise.
-+	(vornq_u8): Likewise.
-+	(vornq_u16): Likewise.
-+	(vornq_u32): Likewise.
-+	(vornq_u64): Likewise.
-+
-+2014-07-16  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r210151.
-+	2014-05-07  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* config/aarch64/arm_neon.h (vtrn1_f32, vtrn1_p8, vtrn1_p16, vtrn1_s8,
-+	vtrn1_s16, vtrn1_s32, vtrn1_u8, vtrn1_u16, vtrn1_u32, vtrn1q_f32,
-+	vtrn1q_f64, vtrn1q_p8, vtrn1q_p16, vtrn1q_s8, vtrn1q_s16, vtrn1q_s32,
-+	vtrn1q_s64, vtrn1q_u8, vtrn1q_u16, vtrn1q_u32, vtrn1q_u64, vtrn2_f32,
-+	vtrn2_p8, vtrn2_p16, vtrn2_s8, vtrn2_s16, vtrn2_s32, vtrn2_u8,
-+	vtrn2_u16, vtrn2_u32, vtrn2q_f32, vtrn2q_f64, vtrn2q_p8, vtrn2q_p16,
-+	vtrn2q_s8, vtrn2q_s16, vtrn2q_s32, vtrn2q_s64, vtrn2q_u8, vtrn2q_u16,
-+	vtrn2q_u32, vtrn2q_u64): Replace temporary asm with __builtin_shuffle.
-+
-+2014-07-16  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209794.
-+	2014-04-25  Marek Polacek  <polacek@redhat.com>
-+
-+	PR c/60114
-+	* c-parser.c (c_parser_initelt): Pass input_location to
-+	process_init_element.
-+	(c_parser_initval): Pass loc to process_init_element.
-+	* c-tree.h (process_init_element): Adjust declaration.
-+	* c-typeck.c (push_init_level): Pass input_location to
-+	process_init_element.
-+	(pop_init_level): Likewise.
-+	(set_designator): Likewise.
-+	(output_init_element): Add location_t parameter.  Pass loc to
-+	digest_init.
-+	(output_pending_init_elements): Pass input_location to
-+	output_init_element.
-+	(process_init_element): Add location_t parameter.  Pass loc to
-+	output_init_element.
-+
-+2014-07-16  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r211771.
-+	2014-06-18  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* genattrtab.c (n_bypassed): New variable.
-+	(process_bypasses): Initialise n_bypassed.
-+	Count number of bypassed reservations.
-+	(make_automaton_attrs): Allocate space for bypassed reservations
-+	rather than number of bypasses.
-+
-+2014-07-16  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r210861.
-+	2014-05-23  Jiong Wang   <jiong.wang@arm.com>
-+
-+	* config/aarch64/predicates.md (aarch64_call_insn_operand): New
-+	predicate.
-+	* config/aarch64/constraints.md ("Ucs", "Usf"):  New constraints.
-+	* config/aarch64/aarch64.md (*sibcall_insn, *sibcall_value_insn):
-+	Adjust for tailcalling through registers.
-+	* config/aarch64/aarch64.h (enum reg_class): New caller save
-+	register class.
-+	(REG_CLASS_NAMES): Likewise.
-+	(REG_CLASS_CONTENTS): Likewise.
-+	* config/aarch64/aarch64.c (aarch64_function_ok_for_sibcall):
-+	Allow tailcalling without decls.
-+
-+2014-07-16  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r211314.
-+	2014-06-06  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* config/aarch64/aarch64-protos.h (aarch64_expand_movmem): New.
-+	* config/aarch64/aarch64.c (aarch64_move_pointer): New.
-+	(aarch64_progress_pointer): Likewise.
-+	(aarch64_copy_one_part_and_move_pointers): Likewise.
-+	(aarch64_expand_movmen): Likewise.
-+	* config/aarch64/aarch64.h (MOVE_RATIO): Set low.
-+	* config/aarch64/aarch64.md (movmem<mode>): New.
-+
-+2014-07-16  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r211185, 211186.
-+	2014-06-03  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* gcc/config/aarch64/aarch64-builtins.c
-+	(aarch64_types_binop_uus_qualifiers,
-+	aarch64_types_shift_to_unsigned_qualifiers,
-+	aarch64_types_unsigned_shiftacc_qualifiers): Define.
-+	* gcc/config/aarch64/aarch64-simd-builtins.def (uqshl, uqrshl, uqadd,
-+	uqsub, usqadd, usra_n, ursra_n, uqshrn_n, uqrshrn_n, usri_n, usli_n,
-+	sqshlu_n, uqshl_n): Update qualifiers.
-+	* gcc/config/aarch64/arm_neon.h (vqadd_u8, vqadd_u16, vqadd_u32,
-+	vqadd_u64, vqaddq_u8, vqaddq_u16, vqaddq_u32, vqaddq_u64, vqsub_u8,
-+	vqsub_u16, vqsub_u32, vqsub_u64, vqsubq_u8, vqsubq_u16, vqsubq_u32,
-+	vqsubq_u64, vqaddb_u8, vqaddh_u16, vqadds_u32, vqaddd_u64, vqrshl_u8,
-+	vqrshl_u16, vqrshl_u32, vqrshl_u64, vqrshlq_u8, vqrshlq_u16,
-+	vqrshlq_u32, vqrshlq_u64, vqrshlb_u8, vqrshlh_u16, vqrshls_u32,
-+	vqrshld_u64, vqrshrn_n_u16, vqrshrn_n_u32, vqrshrn_n_u64,
-+	vqrshrnh_n_u16, vqrshrns_n_u32, vqrshrnd_n_u64, vqshl_u8, vqshl_u16,
-+	vqshl_u32, vqshl_u64, vqshlq_u8, vqshlq_u16, vqshlq_u32, vqshlq_u64,
-+	vqshlb_u8, vqshlh_u16, vqshls_u32, vqshld_u64, vqshl_n_u8, vqshl_n_u16,
-+	vqshl_n_u32, vqshl_n_u64, vqshlq_n_u8, vqshlq_n_u16, vqshlq_n_u32,
-+	vqshlq_n_u64, vqshlb_n_u8, vqshlh_n_u16, vqshls_n_u32, vqshld_n_u64,
-+	vqshlu_n_s8, vqshlu_n_s16, vqshlu_n_s32, vqshlu_n_s64, vqshluq_n_s8,
-+	vqshluq_n_s16, vqshluq_n_s32, vqshluq_n_s64, vqshlub_n_s8,
-+	vqshluh_n_s16, vqshlus_n_s32, vqshlud_n_s64, vqshrn_n_u16,
-+	vqshrn_n_u32, vqshrn_n_u64, vqshrnh_n_u16, vqshrns_n_u32,
-+	vqshrnd_n_u64, vqsubb_u8, vqsubh_u16, vqsubs_u32, vqsubd_u64,
-+	vrsra_n_u8, vrsra_n_u16, vrsra_n_u32, vrsra_n_u64, vrsraq_n_u8,
-+	vrsraq_n_u16, vrsraq_n_u32, vrsraq_n_u64, vrsrad_n_u64, vsli_n_u8,
-+	vsli_n_u16, vsli_n_u32,vsli_n_u64, vsliq_n_u8, vsliq_n_u16,
-+	vsliq_n_u32, vsliq_n_u64, vslid_n_u64, vsqadd_u8, vsqadd_u16,
-+	vsqadd_u32, vsqadd_u64, vsqaddq_u8, vsqaddq_u16, vsqaddq_u32,
-+	vsqaddq_u64, vsqaddb_u8, vsqaddh_u16, vsqadds_u32, vsqaddd_u64,
-+	vsra_n_u8, vsra_n_u16, vsra_n_u32, vsra_n_u64, vsraq_n_u8,
-+	vsraq_n_u16, vsraq_n_u32, vsraq_n_u64, vsrad_n_u64, vsri_n_u8,
-+	vsri_n_u16, vsri_n_u32, vsri_n_u64, vsriq_n_u8, vsriq_n_u16,
-+	vsriq_n_u32, vsriq_n_u64, vsrid_n_u64): Remove casts.
-+
-+	2014-06-03  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* gcc/config/aarch64/aarch64-builtins.c
-+	(aarch64_types_binop_ssu_qualifiers): New static data.
-+	(TYPES_BINOP_SSU): Define.
-+	* gcc/config/aarch64/aarch64-simd-builtins.def (suqadd, ushl, urshl,
-+	urshr_n, ushll_n): Use appropriate unsigned qualifiers.	47
-+	* gcc/config/aarch64/arm_neon.h (vrshl_u8, vrshl_u16, vrshl_u32,
-+	vrshl_u64, vrshlq_u8, vrshlq_u16, vrshlq_u32, vrshlq_u64, vrshld_u64,
-+	vrshr_n_u8, vrshr_n_u16, vrshr_n_u32, vrshr_n_u64, vrshrq_n_u8,	50
-+	vrshrq_n_u16, vrshrq_n_u32, vrshrq_n_u64, vrshrd_n_u64, vshll_n_u8,
-+	vshll_n_u16, vshll_n_u32, vuqadd_s8, vuqadd_s16, vuqadd_s32,	52
-+	vuqadd_s64, vuqaddq_s8, vuqaddq_s16, vuqaddq_s32, vuqaddq_s64,	53
-+	vuqaddb_s8, vuqaddh_s16, vuqadds_s32, vuqaddd_s64): Add signedness
-+	suffix to builtin function name, remove cast.	55
-+	(vshl_s8, vshl_s16, vshl_s32, vshl_s64, vshl_u8, vshl_u16, vshl_u32,
-+	vshl_u64, vshlq_s8, vshlq_s16, vshlq_s32, vshlq_s64, vshlq_u8,	57
-+	vshlq_u16, vshlq_u32, vshlq_u64, vshld_s64, vshld_u64): Remove cast.
-+
-+2014-07-16  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r211408, 211416.
-+	2014-06-10  Marcus Shawcroft  <marcus.shawcroft@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_save_or_restore_fprs): Fix
-+	REG_CFA_RESTORE mode.
-+
-+	2014-06-10  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_save_or_restore_fprs)
-+	(aarch64_save_or_restore_callee_save_registers): Fix layout.
-+
-+2014-07-16  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r211418.
-+	2014-06-10  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/aarch64/aarch64-simd.md (move_lo_quad_<mode>):
-+	Change second alternative type to f_mcr.
-+	* config/aarch64/aarch64.md (*movsi_aarch64): Change 11th
-+	and 12th alternatives' types to f_mcr and f_mrc.
-+	(*movdi_aarch64): Same for 12th and 13th alternatives.
-+	(*movsf_aarch64): Change 9th alternatives' type to mov_reg.
-+	(aarch64_movtilow_tilow): Change type to fmov.
-+
-+2014-07-16  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r211371.
-+	2014-06-09  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
-+
-+	* config/arm/arm-modes.def: Remove XFmode.
-+
-+2014-07-16  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r211268.
-+	2014-06-05  Marcus Shawcroft  <marcus.shawcroft@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_expand_prologue): Update stack
-+	layout comment.
-+
-+2014-07-16  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r211129.
-+	2014-06-02  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
-+
-+	PR target/61154
-+	* config/arm/arm.h (TARGET_SUPPORTS_WIDE_INT): Define.
-+	* config/arm/arm.md (mov64 splitter): Replace const_double_operand
-+	with immediate_operand.
-+
-+2014-07-16  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r211073.
-+	2014-05-30  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/arm/thumb2.md (*thumb2_movhi_insn): Set type of movw
-+	to mov_imm.
-+	* config/arm/vfp.md (*thumb2_movsi_vfp): Likewise.
-+
-+2014-07-16  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r211050.
-+	2014-05-29  Richard Earnshaw <rearnsha@arm.com>
-+	Richard Sandiford  <rdsandiford@googlemail.com>
-+
-+	* arm/iterators.md (shiftable_ops): New code iterator.
-+	(t2_binop0, arith_shift_insn): New code attributes.
-+	* arm/predicates.md (shift_nomul_operator): New predicate.
-+	* arm/arm.md (insn_enabled): Delete.
-+	(enabled): Remove insn_enabled test.
-+	(*arith_shiftsi): Delete.  Replace with ...
-+	(*<arith_shift_insn>_multsi): ... new pattern.
-+	(*<arith_shift_insn>_shiftsi): ... new pattern.
-+	* config/arm/arm.c (arm_print_operand): Handle operand format 'b'.
-+
-+2014-07-16  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r210996.
-+	2014-05-27  Andrew Pinski  <apinski@cavium.com>
-+
-+	* config/aarch64/aarch64.md (stack_protect_set_<mode>):
-+	Use <w> for the register in assembly template.
-+	(stack_protect_test): Use the mode of operands[0] for the
-+	result.
-+	(stack_protect_test_<mode>): Use <w> for the register
-+	in assembly template.
-+
-+2014-07-16  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r210967.
-+	2014-05-27  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/arm/neon.md (neon_bswap<mode>): New pattern.
-+	* config/arm/arm.c (neon_itype): Add NEON_BSWAP.
-+	(arm_init_neon_builtins): Handle NEON_BSWAP.
-+	Define required type nodes.
-+	(arm_expand_neon_builtin): Handle NEON_BSWAP.
-+	(arm_builtin_vectorized_function): Handle BUILTIN_BSWAP builtins.
-+	* config/arm/arm_neon_builtins.def (bswap): Define builtins.
-+	* config/arm/iterators.md (VDQHSD): New mode iterator.
-+
-+2014-07-16  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r210471.
-+	2014-05-15  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/arm/arm.c (arm_option_override): Use the SCHED_PRESSURE_MODEL
-+	enum name for PARAM_SCHED_PRESSURE_ALGORITHM.
-+
-+2014-07-16  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r210369.
-+	2014-05-13  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/arm/arm.c (neon_itype): Remove NEON_RESULTPAIR.
-+	(arm_init_neon_builtins): Remove handling of NEON_RESULTPAIR.
-+	Remove associated type declarations and initialisations.
-+	(arm_expand_neon_builtin): Likewise.
-+	(neon_emit_pair_result_insn): Delete.
-+	* config/arm/arm_neon_builtins (vtrn, vzip, vuzp): Delete.
-+	* config/arm/neon.md (neon_vtrn<mode>): Delete.
-+	(neon_vzip<mode>): Likewise.
-+	(neon_vuzp<mode>): Likewise.
-+
-+2014-07-16  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r211058, 211177.
-+	2014-05-29  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* config/aarch64/aarch64-builtins.c (aarch64_types_binopv_qualifiers,
-+	TYPES_BINOPV): New static data.
-+	* config/aarch64/aarch64-simd-builtins.def (im_lane_bound): New builtin.
-+	* config/aarch64/aarch64-simd.md (aarch64_ext, aarch64_im_lane_boundsi):
-+	New patterns.
-+	* config/aarch64/aarch64.c (aarch64_expand_vec_perm_const_1): Match
-+	patterns for EXT.
-+	(aarch64_evpc_ext): New function.
-+
-+	* config/aarch64/iterators.md (UNSPEC_EXT): New enum element.
-+
-+	* config/aarch64/arm_neon.h (vext_f32, vext_f64, vext_p8, vext_p16,
-+	vext_s8, vext_s16, vext_s32, vext_s64, vext_u8, vext_u16, vext_u32,
-+	vext_u64, vextq_f32, vextq_f64, vextq_p8, vextq_p16, vextq_s8,
-+	vextq_s16, vextq_s32, vextq_s64, vextq_u8, vextq_u16, vextq_u32,
-+	vextq_u64): Replace __asm with __builtin_shuffle and im_lane_boundsi.
-+
-+	2014-06-03  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_evpc_ext): allow and handle
-+	location == 0.
-+
-+2014-07-16  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209797.
-+	2014-04-25  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/arm/aarch-common.c (aarch_rev16_shright_mask_imm_p):
-+	Use HOST_WIDE_INT_C for mask literal.
-+	(aarch_rev16_shleft_mask_imm_p): Likewise.
-+
-+2014-07-16  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r211148.
-+	2014-06-02  Andrew Pinski  <apinski@cavium.com>
-+
-+	* config/aarch64/aarch64-linux.h (GLIBC_DYNAMIC_LINKER):
-+	/lib/ld-linux32-aarch64.so.1 is used for ILP32.
-+	(LINUX_TARGET_LINK_SPEC): Update linker script for ILP32.
-+	file whose name depends on -mabi= and -mbig-endian.
-+	* config/aarch64/t-aarch64-linux (MULTILIB_OSDIRNAMES): Handle LP64
-+	better and handle ilp32 too.
-+	(MULTILIB_OPTIONS): Delete.
-+	(MULTILIB_DIRNAMES): Delete.
-+
-+2014-07-16  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r210828, r211103.
-+	2014-05-31  Kugan Vivekanandarajah  <kuganv@linaro.org>
-+
-+	* config/arm/arm.c (TARGET_ATOMIC_ASSIGN_EXPAND_FENV): New define.
-+	(arm_builtins) : Add ARM_BUILTIN_GET_FPSCR and ARM_BUILTIN_SET_FPSCR.
-+	(bdesc_2arg) : Add description for builtins __builtins_arm_set_fpscr
-+	and __builtins_arm_get_fpscr.
-+	(arm_init_builtins) : Initialize builtins __builtins_arm_set_fpscr and
-+	__builtins_arm_get_fpscr.
-+	(arm_expand_builtin) : Expand builtins __builtins_arm_set_fpscr and
-+	__builtins_arm_ldfpscr.
-+	(arm_atomic_assign_expand_fenv): New function.
-+	* config/arm/vfp.md (set_fpscr): New pattern.
-+	(get_fpscr) : Likewise.
-+	* config/arm/unspecs.md (unspecv): Add VUNSPEC_GET_FPSCR and
-+	VUNSPEC_SET_FPSCR.
-+	* doc/extend.texi (AARCH64 Built-in Functions) : Document
-+	__builtins_arm_set_fpscr, __builtins_arm_get_fpscr.
-+
-+	2014-05-23  Kugan Vivekanandarajah  <kuganv@linaro.org>
-+
-+	* config/aarch64/aarch64.c (TARGET_ATOMIC_ASSIGN_EXPAND_FENV): New
-+	define.
-+	* config/aarch64/aarch64-protos.h (aarch64_atomic_assign_expand_fenv):
-+	New function declaration.
-+	* config/aarch64/aarch64-builtins.c (aarch64_builtins) : Add
-+	AARCH64_BUILTIN_GET_FPCR, AARCH64_BUILTIN_SET_FPCR.
-+	AARCH64_BUILTIN_GET_FPSR and AARCH64_BUILTIN_SET_FPSR.
-+	(aarch64_init_builtins) : Initialize builtins
-+	__builtins_aarch64_set_fpcr, __builtins_aarch64_get_fpcr.
-+	__builtins_aarch64_set_fpsr and __builtins_aarch64_get_fpsr.
-+	(aarch64_expand_builtin) : Expand builtins __builtins_aarch64_set_fpcr
-+	__builtins_aarch64_get_fpcr, __builtins_aarch64_get_fpsr,
-+	and __builtins_aarch64_set_fpsr.
-+	(aarch64_atomic_assign_expand_fenv): New function.
-+	* config/aarch64/aarch64.md (set_fpcr): New pattern.
-+	(get_fpcr) : Likewise.
-+	(set_fpsr) : Likewise.
-+	(get_fpsr) : Likewise.
-+	(unspecv): Add UNSPECV_GET_FPCR and UNSPECV_SET_FPCR, UNSPECV_GET_FPSR
-+	 and UNSPECV_SET_FPSR.
-+	* doc/extend.texi (AARCH64 Built-in Functions) : Document
-+	__builtins_aarch64_set_fpcr, __builtins_aarch64_get_fpcr.
-+	__builtins_aarch64_set_fpsr and __builtins_aarch64_get_fpsr.
-+
-+2014-07-16  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r210355.
-+	2014-05-13  Ian Bolton  <ian.bolton@arm.com>
-+
-+	* config/aarch64/aarch64-protos.h
-+	(aarch64_hard_regno_caller_save_mode): New prototype.
-+	* config/aarch64/aarch64.c (aarch64_hard_regno_caller_save_mode):
-+	New function.
-+	* config/aarch64/aarch64.h (HARD_REGNO_CALLER_SAVE_MODE): New macro.
-+
-+2014-07-16  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209943.
-+	2014-04-30  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* config/aarch64/arm_neon.h (vuzp1_f32, vuzp1_p8, vuzp1_p16, vuzp1_s8,
-+	vuzp1_s16, vuzp1_s32, vuzp1_u8, vuzp1_u16, vuzp1_u32, vuzp1q_f32,
-+	vuzp1q_f64, vuzp1q_p8, vuzp1q_p16, vuzp1q_s8, vuzp1q_s16, vuzp1q_s32,
-+	vuzp1q_s64, vuzp1q_u8, vuzp1q_u16, vuzp1q_u32, vuzp1q_u64, vuzp2_f32,
-+	vuzp2_p8, vuzp2_p16, vuzp2_s8, vuzp2_s16, vuzp2_s32, vuzp2_u8,
-+	vuzp2_u16, vuzp2_u32, vuzp2q_f32, vuzp2q_f64, vuzp2q_p8, vuzp2q_p16,
-+	vuzp2q_s8, vuzp2q_s16, vuzp2q_s32, vuzp2q_s64, vuzp2q_u8, vuzp2q_u16,
-+	vuzp2q_u32, vuzp2q_u64): Replace temporary asm with __builtin_shuffle.
-+
-+2014-06-26  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	* LINARO-VERSION: Bump version.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+	* LINARO-VERSION: Update.
-+
-+2014-06-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Revert:
-+	2014-05-23  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209643.
-+	2014-04-22  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
-+
-+	* config/aarch64/aarch64.c (TARGET_FLAGS_REGNUM): Define.
-+
-+2014-06-13  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r210493, 210494, 210495, 210496, 210497, 210498,
-+	210499, 210500, 210501, 210502, 210503, 210504, 210505, 210506, 210507,
-+	210508, 210509, 210510, 210512, 211205, 211206.
-+	2014-05-16  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* config/aarch64/aarch64-protos.h (scale_addr_mode_cost): New.
-+	(cpu_addrcost_table): Use it.
-+	* config/aarch64/aarch64.c (generic_addrcost_table): Initialize it.
-+	(aarch64_address_cost): Rewrite using aarch64_classify_address,
-+	move it.
-+
-+	2014-05-16  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* config/aarch64/aarch64.c (cortexa57_addrcost_table): New.
-+	(cortexa57_vector_cost): Likewise.
-+	(cortexa57_tunings): Use them.
-+
-+	2014-05-16  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_rtx_costs_wrapper): New.
-+	(TARGET_RTX_COSTS): Call it.
-+
-+	2014-05-16  James Greenhalgh  <james.greenhalgh@arm.com>
-+		    Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_build_constant): Conditionally
-+	emit instructions, return number of instructions which would
-+	be emitted.
-+	(aarch64_add_constant): Update call to aarch64_build_constant.
-+	(aarch64_output_mi_thunk): Likewise.
-+	(aarch64_rtx_costs): Estimate cost of a CONST_INT, cost
-+	a CONST_DOUBLE.
-+
-+	2014-05-16  James Greenhalgh  <james.greenhalgh@arm.com>
-+		    Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_strip_shift_or_extend): Rename
-+	to...
-+	(aarch64_strip_extend): ...this, don't strip shifts, check RTX is
-+	well formed.
-+	(aarch64_rtx_mult_cost): New.
-+	(aarch64_rtx_costs): Use it, refactor as appropriate.
-+
-+	2014-05-16  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_rtx_costs): Set default costs.
-+
-+	2014-05-16  James Greenhalgh  <james.greenhalgh@arm.com>
-+		    Philip Tomsich  <philipp.tomsich@theobroma-systems.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_rtx_costs): Improve costing
-+	for SET RTX.
-+
-+	2014-05-16  James Greenhalgh  <james.greenhalgh@arm.com>
-+		    Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_rtx_costs): Use address
-+	costs when costing loads and stores to memory.
-+
-+	2014-05-16  James Greenhalgh  <james.greenhalgh@arm.com>
-+		    Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_rtx_costs): Improve cost for
-+	logical operations.
-+
-+	2014-05-16  James Greenhalgh  <james.greenhalgh@arm.com>
-+		    Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_rtx_costs): Cost
-+	ZERO_EXTEND and SIGN_EXTEND better.
-+
-+	2014-05-16  James Greenhalgh  <james.greenhalgh@arm.com>
-+		    Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_rtx_costs): Improve costs for
-+	rotates and shifts.
-+
-+	2014-03-16  James Greenhalgh  <james.greenhalgh@arm.com>
-+		    Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_rtx_arith_op_extract_p): New.
-+	(aarch64_rtx_costs): Improve costs for SIGN/ZERO_EXTRACT.
-+
-+	2014-05-16  James Greenhalgh  <james.greenhalgh@arm.com>
-+		    Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_rtx_costs): Improve costs for
-+	DIV/MOD.
-+
-+	2014-05-16  James Greenhalgh  <james.greenhalgh@arm.com>
-+		    Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_rtx_costs): Cost comparison
-+	operators.
-+
-+	2014-05-16  James Greenhalgh  <james.greenhalgh@arm.com>
-+		    Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_rtx_costs): Cost FMA,
-+	FLOAT_EXTEND, FLOAT_TRUNCATE, ABS, SMAX, and SMIN.
-+
-+	2014-05-16  James Greenhalgh  <james.greenhalgh@arm.com>
-+		    Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_rtx_costs): Cost TRUNCATE.
-+
-+	2014-05-16  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_rtx_costs): Cost SYMBOL_REF,
-+	HIGH, LO_SUM.
-+
-+	2014-05-16  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_rtx_costs): Handle the case
-+	where we were unable to cost an RTX.
-+
-+	2014-05-16  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_rtx_mult_cost): Fix FNMUL case.
-+
-+	2014-06-03  Andrew Pinski  <apinski@cavium.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_if_then_else_costs): New function.
-+	(aarch64_rtx_costs): Use aarch64_if_then_else_costs.
-+
-+	2014-06-03  Andrew Pinski  <apinski@cavium.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_if_then_else_costs): Allow non
-+	comparisons for OP0.
-+
-+2014-06-13  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	* LINARO-VERSION: Bump version.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+	* LINARO-VERSION: Update.
-+
-+2014-06-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r211211.
-+	2014-06-04  Bin Cheng  <bin.cheng@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_classify_address)
-+	(aarch64_legitimize_reload_address): Support full addressing modes
-+	for vector modes.
-+	* config/aarch64/aarch64.md (mov<mode>, movmisalign<mode>)
-+	(*aarch64_simd_mov<mode>, *aarch64_simd_mov<mode>): Relax predicates.
-+
-+2014-05-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209906.
-+	2014-04-29  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* config/aarch64/arm_neon.h (vzip1_f32, vzip1_p8, vzip1_p16, vzip1_s8,
-+	vzip1_s16, vzip1_s32, vzip1_u8, vzip1_u16, vzip1_u32, vzip1q_f32,
-+	vzip1q_f64, vzip1q_p8, vzip1q_p16, vzip1q_s8, vzip1q_s16, vzip1q_s32,
-+	vzip1q_s64, vzip1q_u8, vzip1q_u16, vzip1q_u32, vzip1q_u64, vzip2_f32,
-+	vzip2_p8, vzip2_p16, vzip2_s8, vzip2_s16, vzip2_s32, vzip2_u8,
-+	vzip2_u16, vzip2_u32, vzip2q_f32, vzip2q_f64, vzip2q_p8, vzip2q_p16,
-+	vzip2q_s8, vzip2q_s16, vzip2q_s32, vzip2q_s64, vzip2q_u8, vzip2q_u16,
-+	vzip2q_u32, vzip2q_u64): Replace inline __asm__ with __builtin_shuffle.
-+
-+2014-05-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209897.
-+	2014-04-29  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* calls.c (initialize_argument_information): Always treat
-+	PUSH_ARGS_REVERSED as 1, simplify code accordingly.
-+	(expand_call): Likewise.
-+	(emit_library_call_calue_1): Likewise.
-+	* expr.c (PUSH_ARGS_REVERSED): Do not define.
-+	(emit_push_insn): Always treat PUSH_ARGS_REVERSED as 1, simplify
-+	code accordingly.
-+
-+2014-05-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209880.
-+	2014-04-28  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* config/aarch64/aarch64-builtins.c
-+	(aarch64_types_storestruct_lane_qualifiers): New.
-+	(TYPES_STORESTRUCT_LANE): Likewise.
-+	* config/aarch64/aarch64-simd-builtins.def (st2_lane): New.
-+	(st3_lane): Likewise.
-+	(st4_lane): Likewise.
-+	* config/aarch64/aarch64-simd.md (vec_store_lanesoi_lane<mode>): New.
-+	(vec_store_lanesci_lane<mode>): Likewise.
-+	(vec_store_lanesxi_lane<mode>): Likewise.
-+		(aarch64_st2_lane<VQ:mode>): Likewise.
-+	(aarch64_st3_lane<VQ:mode>): Likewise.
-+	(aarch64_st4_lane<VQ:mode>): Likewise.
-+	* config/aarch64/aarch64.md (unspec): Add UNSPEC_ST{2,3,4}_LANE.
-+	* config/aarch64/arm_neon.h
-+		(__ST2_LANE_FUNC): Rewrite using builtins, update use points to
-+	use new macro arguments.
-+	(__ST3_LANE_FUNC): Likewise.
-+	(__ST4_LANE_FUNC): Likewise.
-+	* config/aarch64/iterators.md (V_TWO_ELEM): New.
-+	(V_THREE_ELEM): Likewise.
-+	(V_FOUR_ELEM): Likewise.
-+
-+2014-05-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209878.
-+	2014-04-28  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* config/aarch64/aarch64-protos.h (aarch64_modes_tieable_p): New.
-+	* config/aarch64/aarch64.c
-+	(aarch64_cannot_change_mode_class): Weaken conditions.
-+	(aarch64_modes_tieable_p): New.
-+	* config/aarch64/aarch64.h (MODES_TIEABLE_P): Use it.
-+
-+2014-05-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209808.
-+	2014-04-25  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* config/arm/predicates.md (call_insn_operand): Add long_call check.
-+	* config/arm/arm.md (sibcall, sibcall_value): Force the address to
-+	reg for long_call.
-+	* config/arm/arm.c (arm_function_ok_for_sibcall): Remove long_call
-+	restriction.
-+
-+2014-05-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209806.
-+	2014-04-25  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/arm/arm.c (arm_cortex_a8_tune): Initialise
-+	T16-related fields.
-+
-+2014-05-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209742, 209749.
-+	2014-04-24  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_evpc_tbl): Enable for bigendian.
-+
-+	2014-04-24  Tejas Belagod  <tejas.belagod@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_evpc_tbl): Reverse order of elements
-+	for big-endian.
-+
-+2014-05-23  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209736.
-+	2014-04-24  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/aarch64/aarch64-builtins.c
-+	(aarch64_builtin_vectorized_function): Handle BUILT_IN_BSWAP16,
-+	BUILT_IN_BSWAP32, BUILT_IN_BSWAP64.
-+	* config/aarch64/aarch64-simd.md (bswap<mode>): New pattern.
-+	* config/aarch64/aarch64-simd-builtins.def: Define vector bswap
-+	builtins.
-+	* config/aarch64/iterator.md (VDQHSD): New mode iterator.
-+	(Vrevsuff): New mode attribute.
-+
-+2014-05-23  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209712.
-+	2014-04-23 Venkataramanan Kumar  <venkataramanan.kumar@linaro.org>
-+
-+	* config/aarch64/aarch64.md (stack_protect_set, stack_protect_test)
-+	(stack_protect_set_<mode>, stack_protect_test_<mode>): Add
-+	machine descriptions for Stack Smashing Protector.
-+
-+2014-05-23  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209711.
-+	2014-04-23  Richard Earnshaw  <rearnsha@arm.com>
-+
-+	* aarch64.md (<optab>_rol<mode>3): New pattern.
-+	(<optab>_rolsi3_uxtw): Likewise.
-+	* aarch64.c (aarch64_strip_shift): Handle ROTATE and ROTATERT.
-+
-+2014-05-23  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209710.
-+	2014-04-23  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* config/arm/arm.c (arm_cortex_a57_tune): Initialize all fields.
-+	(arm_cortex_a12_tune): Likewise.
-+
-+2014-05-23  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209706.
-+	2014-04-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_rtx_costs): Handle BSWAP.
-+
-+2014-05-23  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209701, 209702, 209703, 209704, 209705.
-+	2014-04-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/arm/arm.md (arm_rev16si2): New pattern.
-+	(arm_rev16si2_alt): Likewise.
-+	* config/arm/arm.c (arm_new_rtx_costs): Handle rev16 case.
-+
-+	2014-04-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+	* config/aarch64/aarch64.md (rev16<mode>2): New pattern.
-+	(rev16<mode>2_alt): Likewise.
-+	* config/aarch64/aarch64.c (aarch64_rtx_costs): Handle rev16 case.
-+	* config/arm/aarch-common.c (aarch_rev16_shright_mask_imm_p): New.
-+	(aarch_rev16_shleft_mask_imm_p): Likewise.
-+	(aarch_rev16_p_1): Likewise.
-+	(aarch_rev16_p): Likewise.
-+	* config/arm/aarch-common-protos.h (aarch_rev16_p): Declare extern.
-+	(aarch_rev16_shright_mask_imm_p): Likewise.
-+	(aarch_rev16_shleft_mask_imm_p): Likewise.
-+
-+	2014-04-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/arm/aarch-common-protos.h (alu_cost_table): Add rev field.
-+	* config/arm/aarch-cost-tables.h (generic_extra_costs): Specify
-+	rev cost.
-+	(cortex_a53_extra_costs): Likewise.
-+	(cortex_a57_extra_costs): Likewise.
-+	* config/arm/arm.c (cortexa9_extra_costs): Likewise.
-+	(cortexa7_extra_costs): Likewise.
-+	(cortexa8_extra_costs): Likewise.
-+	(cortexa12_extra_costs): Likewise.
-+	(cortexa15_extra_costs): Likewise.
-+	(v7m_extra_costs): Likewise.
-+	(arm_new_rtx_costs): Handle BSWAP.
-+
-+	2013-04-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/arm/arm.c (cortexa8_extra_costs): New table.
-+	(arm_cortex_a8_tune): New tuning struct.
-+	* config/arm/arm-cores.def (cortex-a8): Use cortex_a8 tuning struct.
-+
-+	2014-04-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/arm/arm.c (arm_new_rtx_costs): Handle FMA.
-+
-+2014-05-23  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209659.
-+	2014-04-22  Richard Henderson  <rth@redhat.com>
-+
-+	* config/aarch64/aarch64 (addti3, subti3): New expanders.
-+	(add<GPI>3_compare0): Remove leading * from name.
-+	(add<GPI>3_carryin): Likewise.
-+	(sub<GPI>3_compare0): Likewise.
-+	(sub<GPI>3_carryin): Likewise.
-+	(<su_optab>mulditi3): New expander.
-+	(multi3): New expander.
-+	(madd<GPI>): Remove leading * from name.
-+
-+2014-05-23  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209645.
-+	2014-04-22  Andrew Pinski  <apinski@cavium.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_load_symref_appropriately):
-+	Handle TLS for ILP32.
-+	* config/aarch64/aarch64.md (tlsie_small): Rename to ...
-+	(tlsie_small_<mode>): this and handle PTR.
-+	(tlsie_small_sidi): New pattern.
-+	(tlsle_small): Change to an expand to handle ILP32.
-+	(tlsle_small_<mode>): New pattern.
-+	(tlsdesc_small): Rename to ...
-+	(tlsdesc_small_<mode>): this and handle PTR.
-+
-+2014-05-23  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209643.
-+	2014-04-22  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
-+
-+	* config/aarch64/aarch64.c (TARGET_FLAGS_REGNUM): Define.
-+
-+2014-05-23  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209641, 209642.
-+	2014-04-22  Alex Velenko  <Alex.Velenko@arm.com>
-+
-+	* config/aarch64/aarch64-builtins.c (TYPES_REINTERP): Removed.
-+	(aarch64_types_signed_unsigned_qualifiers): Qualifier added.
-+	(aarch64_types_signed_poly_qualifiers): Likewise.
-+	(aarch64_types_unsigned_signed_qualifiers): Likewise.
-+	(aarch64_types_poly_signed_qualifiers): Likewise.
-+	(TYPES_REINTERP_SS): Type macro added.
-+	(TYPES_REINTERP_SU): Likewise.
-+	(TYPES_REINTERP_SP): Likewise.
-+	(TYPES_REINTERP_US): Likewise.
-+	(TYPES_REINTERP_PS): Likewise.
-+	(aarch64_fold_builtin): New expression folding added.
-+	* config/aarch64/aarch64-simd-builtins.def (REINTERP):
-+	Declarations removed.
-+	(REINTERP_SS): Declarations added.
-+	(REINTERP_US): Likewise.
-+	(REINTERP_PS): Likewise.
-+	(REINTERP_SU): Likewise.
-+	(REINTERP_SP): Likewise.
-+	* config/aarch64/arm_neon.h (vreinterpret_p8_f64): Implemented.
-+	(vreinterpretq_p8_f64): Likewise.
-+	(vreinterpret_p16_f64): Likewise.
-+	(vreinterpretq_p16_f64): Likewise.
-+	(vreinterpret_f32_f64): Likewise.
-+	(vreinterpretq_f32_f64): Likewise.
-+	(vreinterpret_f64_f32): Likewise.
-+	(vreinterpret_f64_p8): Likewise.
-+	(vreinterpret_f64_p16): Likewise.
-+	(vreinterpret_f64_s8): Likewise.
-+	(vreinterpret_f64_s16): Likewise.
-+	(vreinterpret_f64_s32): Likewise.
-+	(vreinterpret_f64_s64): Likewise.
-+	(vreinterpret_f64_u8): Likewise.
-+	(vreinterpret_f64_u16): Likewise.
-+	(vreinterpret_f64_u32): Likewise.
-+	(vreinterpret_f64_u64): Likewise.
-+	(vreinterpretq_f64_f32): Likewise.
-+	(vreinterpretq_f64_p8): Likewise.
-+	(vreinterpretq_f64_p16): Likewise.
-+	(vreinterpretq_f64_s8): Likewise.
-+	(vreinterpretq_f64_s16): Likewise.
-+	(vreinterpretq_f64_s32): Likewise.
-+	(vreinterpretq_f64_s64): Likewise.
-+	(vreinterpretq_f64_u8): Likewise.
-+	(vreinterpretq_f64_u16): Likewise.
-+	(vreinterpretq_f64_u32): Likewise.
-+	(vreinterpretq_f64_u64): Likewise.
-+	(vreinterpret_s64_f64): Likewise.
-+	(vreinterpretq_s64_f64): Likewise.
-+	(vreinterpret_u64_f64): Likewise.
-+	(vreinterpretq_u64_f64): Likewise.
-+	(vreinterpret_s8_f64): Likewise.
-+	(vreinterpretq_s8_f64): Likewise.
-+	(vreinterpret_s16_f64): Likewise.
-+	(vreinterpretq_s16_f64): Likewise.
-+	(vreinterpret_s32_f64): Likewise.
-+	(vreinterpretq_s32_f64): Likewise.
-+	(vreinterpret_u8_f64): Likewise.
-+	(vreinterpretq_u8_f64): Likewise.
-+	(vreinterpret_u16_f64): Likewise.
-+	(vreinterpretq_u16_f64): Likewise.
-+	(vreinterpret_u32_f64): Likewise.
-+	(vreinterpretq_u32_f64): Likewise.
-+
-+	2014-04-22  Alex Velenko  <Alex.Velenko@arm.com>
-+
-+	* config/aarch64/aarch64/aarch64-builtins.c (TYPES_REINTERP): Removed.
-+	* config/aarch64/aarch64/aarch64-simd-builtins.def (REINTERP): Removed.
-+	(vreinterpret_p8_s8): Likewise.
-+	* config/aarch64/aarch64/arm_neon.h (vreinterpret_p8_s8): Uses cast.
-+	(vreinterpret_p8_s16): Likewise.
-+	(vreinterpret_p8_s32): Likewise.
-+	(vreinterpret_p8_s64): Likewise.
-+	(vreinterpret_p8_f32): Likewise.
-+	(vreinterpret_p8_u8): Likewise.
-+	(vreinterpret_p8_u16): Likewise.
-+	(vreinterpret_p8_u32): Likewise.
-+	(vreinterpret_p8_u64): Likewise.
-+	(vreinterpret_p8_p16): Likewise.
-+	(vreinterpretq_p8_s8): Likewise.
-+	(vreinterpretq_p8_s16): Likewise.
-+	(vreinterpretq_p8_s32): Likewise.
-+	(vreinterpretq_p8_s64): Likewise.
-+	(vreinterpretq_p8_f32): Likewise.
-+	(vreinterpretq_p8_u8): Likewise.
-+	(vreinterpretq_p8_u16): Likewise.
-+	(vreinterpretq_p8_u32): Likewise.
-+	(vreinterpretq_p8_u64): Likewise.
-+	(vreinterpretq_p8_p16): Likewise.
-+	(vreinterpret_p16_s8): Likewise.
-+	(vreinterpret_p16_s16): Likewise.
-+	(vreinterpret_p16_s32): Likewise.
-+	(vreinterpret_p16_s64): Likewise.
-+	(vreinterpret_p16_f32): Likewise.
-+	(vreinterpret_p16_u8): Likewise.
-+	(vreinterpret_p16_u16): Likewise.
-+	(vreinterpret_p16_u32): Likewise.
-+	(vreinterpret_p16_u64): Likewise.
-+	(vreinterpret_p16_p8): Likewise.
-+	(vreinterpretq_p16_s8): Likewise.
-+	(vreinterpretq_p16_s16): Likewise.
-+	(vreinterpretq_p16_s32): Likewise.
-+	(vreinterpretq_p16_s64): Likewise.
-+	(vreinterpretq_p16_f32): Likewise.
-+	(vreinterpretq_p16_u8): Likewise.
-+	(vreinterpretq_p16_u16): Likewise.
-+	(vreinterpretq_p16_u32): Likewise.
-+	(vreinterpretq_p16_u64): Likewise.
-+	(vreinterpretq_p16_p8): Likewise.
-+	(vreinterpret_f32_s8): Likewise.
-+	(vreinterpret_f32_s16): Likewise.
-+	(vreinterpret_f32_s32): Likewise.
-+	(vreinterpret_f32_s64): Likewise.
-+	(vreinterpret_f32_u8): Likewise.
-+	(vreinterpret_f32_u16): Likewise.
-+	(vreinterpret_f32_u32): Likewise.
-+	(vreinterpret_f32_u64): Likewise.
-+	(vreinterpret_f32_p8): Likewise.
-+	(vreinterpret_f32_p16): Likewise.
-+	(vreinterpretq_f32_s8): Likewise.
-+	(vreinterpretq_f32_s16): Likewise.
-+	(vreinterpretq_f32_s32): Likewise.
-+	(vreinterpretq_f32_s64): Likewise.
-+	(vreinterpretq_f32_u8): Likewise.
-+	(vreinterpretq_f32_u16): Likewise.
-+	(vreinterpretq_f32_u32): Likewise.
-+	(vreinterpretq_f32_u64): Likewise.
-+	(vreinterpretq_f32_p8): Likewise.
-+	(vreinterpretq_f32_p16): Likewise.
-+	(vreinterpret_s64_s8): Likewise.
-+	(vreinterpret_s64_s16): Likewise.
-+	(vreinterpret_s64_s32): Likewise.
-+	(vreinterpret_s64_f32): Likewise.
-+	(vreinterpret_s64_u8): Likewise.
-+	(vreinterpret_s64_u16): Likewise.
-+	(vreinterpret_s64_u32): Likewise.
-+	(vreinterpret_s64_u64): Likewise.
-+	(vreinterpret_s64_p8): Likewise.
-+	(vreinterpret_s64_p16): Likewise.
-+	(vreinterpretq_s64_s8): Likewise.
-+	(vreinterpretq_s64_s16): Likewise.
-+	(vreinterpretq_s64_s32): Likewise.
-+	(vreinterpretq_s64_f32): Likewise.
-+	(vreinterpretq_s64_u8): Likewise.
-+	(vreinterpretq_s64_u16): Likewise.
-+	(vreinterpretq_s64_u32): Likewise.
-+	(vreinterpretq_s64_u64): Likewise.
-+	(vreinterpretq_s64_p8): Likewise.
-+	(vreinterpretq_s64_p16): Likewise.
-+	(vreinterpret_u64_s8): Likewise.
-+	(vreinterpret_u64_s16): Likewise.
-+	(vreinterpret_u64_s32): Likewise.
-+	(vreinterpret_u64_s64): Likewise.
-+	(vreinterpret_u64_f32): Likewise.
-+	(vreinterpret_u64_u8): Likewise.
-+	(vreinterpret_u64_u16): Likewise.
-+	(vreinterpret_u64_u32): Likewise.
-+	(vreinterpret_u64_p8): Likewise.
-+	(vreinterpret_u64_p16): Likewise.
-+	(vreinterpretq_u64_s8): Likewise.
-+	(vreinterpretq_u64_s16): Likewise.
-+	(vreinterpretq_u64_s32): Likewise.
-+	(vreinterpretq_u64_s64): Likewise.
-+	(vreinterpretq_u64_f32): Likewise.
-+	(vreinterpretq_u64_u8): Likewise.
-+	(vreinterpretq_u64_u16): Likewise.
-+	(vreinterpretq_u64_u32): Likewise.
-+	(vreinterpretq_u64_p8): Likewise.
-+	(vreinterpretq_u64_p16): Likewise.
-+	(vreinterpret_s8_s16): Likewise.
-+	(vreinterpret_s8_s32): Likewise.
-+	(vreinterpret_s8_s64): Likewise.
-+	(vreinterpret_s8_f32): Likewise.
-+	(vreinterpret_s8_u8): Likewise.
-+	(vreinterpret_s8_u16): Likewise.
-+	(vreinterpret_s8_u32): Likewise.
-+	(vreinterpret_s8_u64): Likewise.
-+	(vreinterpret_s8_p8): Likewise.
-+	(vreinterpret_s8_p16): Likewise.
-+	(vreinterpretq_s8_s16): Likewise.
-+	(vreinterpretq_s8_s32): Likewise.
-+	(vreinterpretq_s8_s64): Likewise.
-+	(vreinterpretq_s8_f32): Likewise.
-+	(vreinterpretq_s8_u8): Likewise.
-+	(vreinterpretq_s8_u16): Likewise.
-+	(vreinterpretq_s8_u32): Likewise.
-+	(vreinterpretq_s8_u64): Likewise.
-+	(vreinterpretq_s8_p8): Likewise.
-+	(vreinterpretq_s8_p16): Likewise.
-+	(vreinterpret_s16_s8): Likewise.
-+	(vreinterpret_s16_s32): Likewise.
-+	(vreinterpret_s16_s64): Likewise.
-+	(vreinterpret_s16_f32): Likewise.
-+	(vreinterpret_s16_u8): Likewise.
-+	(vreinterpret_s16_u16): Likewise.
-+	(vreinterpret_s16_u32): Likewise.
-+	(vreinterpret_s16_u64): Likewise.
-+	(vreinterpret_s16_p8): Likewise.
-+	(vreinterpret_s16_p16): Likewise.
-+	(vreinterpretq_s16_s8): Likewise.
-+	(vreinterpretq_s16_s32): Likewise.
-+	(vreinterpretq_s16_s64): Likewise.
-+	(vreinterpretq_s16_f32): Likewise.
-+	(vreinterpretq_s16_u8): Likewise.
-+	(vreinterpretq_s16_u16): Likewise.
-+	(vreinterpretq_s16_u32): Likewise.
-+	(vreinterpretq_s16_u64): Likewise.
-+	(vreinterpretq_s16_p8): Likewise.
-+	(vreinterpretq_s16_p16): Likewise.
-+	(vreinterpret_s32_s8): Likewise.
-+	(vreinterpret_s32_s16): Likewise.
-+	(vreinterpret_s32_s64): Likewise.
-+	(vreinterpret_s32_f32): Likewise.
-+	(vreinterpret_s32_u8): Likewise.
-+	(vreinterpret_s32_u16): Likewise.
-+	(vreinterpret_s32_u32): Likewise.
-+	(vreinterpret_s32_u64): Likewise.
-+	(vreinterpret_s32_p8): Likewise.
-+	(vreinterpret_s32_p16): Likewise.
-+	(vreinterpretq_s32_s8): Likewise.
-+	(vreinterpretq_s32_s16): Likewise.
-+	(vreinterpretq_s32_s64): Likewise.
-+	(vreinterpretq_s32_f32): Likewise.
-+	(vreinterpretq_s32_u8): Likewise.
-+	(vreinterpretq_s32_u16): Likewise.
-+	(vreinterpretq_s32_u32): Likewise.
-+	(vreinterpretq_s32_u64): Likewise.
-+	(vreinterpretq_s32_p8): Likewise.
-+	(vreinterpretq_s32_p16): Likewise.
-+	(vreinterpret_u8_s8): Likewise.
-+	(vreinterpret_u8_s16): Likewise.
-+	(vreinterpret_u8_s32): Likewise.
-+	(vreinterpret_u8_s64): Likewise.
-+	(vreinterpret_u8_f32): Likewise.
-+	(vreinterpret_u8_u16): Likewise.
-+	(vreinterpret_u8_u32): Likewise.
-+	(vreinterpret_u8_u64): Likewise.
-+	(vreinterpret_u8_p8): Likewise.
-+	(vreinterpret_u8_p16): Likewise.
-+	(vreinterpretq_u8_s8): Likewise.
-+	(vreinterpretq_u8_s16): Likewise.
-+	(vreinterpretq_u8_s32): Likewise.
-+	(vreinterpretq_u8_s64): Likewise.
-+	(vreinterpretq_u8_f32): Likewise.
-+	(vreinterpretq_u8_u16): Likewise.
-+	(vreinterpretq_u8_u32): Likewise.
-+	(vreinterpretq_u8_u64): Likewise.
-+	(vreinterpretq_u8_p8): Likewise.
-+	(vreinterpretq_u8_p16): Likewise.
-+	(vreinterpret_u16_s8): Likewise.
-+	(vreinterpret_u16_s16): Likewise.
-+	(vreinterpret_u16_s32): Likewise.
-+	(vreinterpret_u16_s64): Likewise.
-+	(vreinterpret_u16_f32): Likewise.
-+	(vreinterpret_u16_u8): Likewise.
-+	(vreinterpret_u16_u32): Likewise.
-+	(vreinterpret_u16_u64): Likewise.
-+	(vreinterpret_u16_p8): Likewise.
-+	(vreinterpret_u16_p16): Likewise.
-+	(vreinterpretq_u16_s8): Likewise.
-+	(vreinterpretq_u16_s16): Likewise.
-+	(vreinterpretq_u16_s32): Likewise.
-+	(vreinterpretq_u16_s64): Likewise.
-+	(vreinterpretq_u16_f32): Likewise.
-+	(vreinterpretq_u16_u8): Likewise.
-+	(vreinterpretq_u16_u32): Likewise.
-+	(vreinterpretq_u16_u64): Likewise.
-+	(vreinterpretq_u16_p8): Likewise.
-+	(vreinterpretq_u16_p16): Likewise.
-+	(vreinterpret_u32_s8): Likewise.
-+	(vreinterpret_u32_s16): Likewise.
-+	(vreinterpret_u32_s32): Likewise.
-+	(vreinterpret_u32_s64): Likewise.
-+	(vreinterpret_u32_f32): Likewise.
-+	(vreinterpret_u32_u8): Likewise.
-+	(vreinterpret_u32_u16): Likewise.
-+	(vreinterpret_u32_u64): Likewise.
-+	(vreinterpret_u32_p8): Likewise.
-+	(vreinterpret_u32_p16): Likewise.
-+	(vreinterpretq_u32_s8): Likewise.
-+	(vreinterpretq_u32_s16): Likewise.
-+	(vreinterpretq_u32_s32): Likewise.
-+	(vreinterpretq_u32_s64): Likewise.
-+	(vreinterpretq_u32_f32): Likewise.
-+	(vreinterpretq_u32_u8): Likewise.
-+	(vreinterpretq_u32_u16): Likewise.
-+	(vreinterpretq_u32_u64): Likewise.
-+	(vreinterpretq_u32_p8): Likewise.
-+	(vreinterpretq_u32_p16): Likewise.
-+
-+2014-05-23  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209640.
-+	2014-04-22  Alex Velenko  <Alex.Velenko@arm.com>
-+
-+	* gcc/config/aarch64/aarch64-simd.md (aarch64_s<optab><mode>):
-+	Pattern extended.
-+	* config/aarch64/aarch64-simd-builtins.def (sqneg): Iterator
-+	extended.
-+	(sqabs): Likewise.
-+	* config/aarch64/arm_neon.h (vqneg_s64): New intrinsic.
-+	(vqnegd_s64): Likewise.
-+	(vqabs_s64): Likewise.
-+	(vqabsd_s64): Likewise.
-+
-+2014-05-23  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209627, 209636.
-+	2014-04-22  Renlin  <renlin.li@arm.com>
-+		    Jiong Wang  <jiong.wang@arm.com>
-+
-+	* config/aarch64/aarch64.h (aarch64_frame): Delete "fp_lr_offset".
-+	* config/aarch64/aarch64.c (aarch64_layout_frame)
-+	(aarch64_initial_elimination_offset): Likewise.
-+
-+	2014-04-22  Marcus Shawcroft  <marcus.shawcroft@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_initial_elimination_offset):
-+	Fix indentation.
-+
-+2014-05-23  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209618.
-+	2014-04-22  Renlin Li  <Renlin.Li@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_print_operand_address): Adjust
-+	the output asm format.
-+
-+2014-05-23  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209617.
-+	2014-04-22  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* config/aarch64/aarch64-simd.md
-+	(aarch64_cm<optab>di): Always split.
-+	(*aarch64_cm<optab>di): New.
-+	(aarch64_cmtstdi): Always split.
-+	(*aarch64_cmtstdi): New.
-+
-+2014-05-23  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209615.
-+	2014-04-22  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
-+
-+	* config/arm/arm.c (arm_hard_regno_mode_ok): Loosen
-+	restrictions on core registers for DImode values in Thumb2.
-+
-+2014-05-23  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209613, r209614.
-+	2014-04-22  Ian Bolton  <ian.bolton@arm.com>
-+
-+	* config/arm/arm.md (*anddi_notdi_zesidi): New pattern.
-+	* config/arm/thumb2.md (*iordi_notdi_zesidi): New pattern.
-+
-+	2014-04-22  Ian Bolton  <ian.bolton@arm.com>
-+
-+	* config/arm/thumb2.md (*iordi_notdi_di): New pattern.
-+	(*iordi_notzesidi_di): Likewise.
-+	(*iordi_notsesidi_di): Likewise.
-+
-+2014-05-23  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209561.
-+	2014-04-22  Ian Bolton  <ian.bolton@arm.com>
-+
-+	* config/arm/arm-protos.h (tune_params): New struct members.
-+	* config/arm/arm.c: Initialise tune_params per processor.
-+	(thumb2_reorg): Suppress conversion from t32 to t16 when optimizing
-+	for speed, based on new tune_params.
-+
-+2014-05-23  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209559.
-+	2014-04-22  Alex Velenko  <Alex.Velenko@arm.com>
-+
-+	* config/aarch64/aarch64-builtins.c (BUILTIN_VDQF_DF): Macro
-+	added.
-+	* config/aarch64/aarch64-simd-builtins.def (frintn): Use added
-+	macro.
-+	* config/aarch64/aarch64-simd.md (<frint_pattern>): Comment
-+	corrected.
-+	* config/aarch64/aarch64.md (<frint_pattern>): Likewise.
-+	* config/aarch64/arm_neon.h (vrnd_f64): Added.
-+	(vrnda_f64): Likewise.
-+	(vrndi_f64): Likewise.
-+	(vrndm_f64): Likewise.
-+	(vrndn_f64): Likewise.
-+	(vrndp_f64): Likewise.
-+	(vrndx_f64): Likewise.
-+
-+2014-05-23  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209419.
-+	2014-04-15  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	PR rtl-optimization/60663
-+	* config/arm/arm.c (arm_new_rtx_costs): Improve ASM_OPERANDS case,
-+	avoid 0 cost.
-+
-+2014-05-23  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209457.
-+	2014-04-16  Andrew  Pinski  <apinski@cavium.com>
-+
-+	* config/host-linux.c (TRY_EMPTY_VM_SPACE): Change aarch64 ilp32
-+	definition.
-+
-+2014-05-19  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	* LINARO-VERSION: Bump version.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+	* LINARO-VERSION: Update.
-+
-+2014-05-13  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209889.
-+	2014-04-29  Zhenqiang Chen  <zhenqiang.chen@linaro.org>
-+
-+	* config/aarch64/aarch64.md (mov<mode>cc): New for GPF.
-+
-+2014-05-13  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209556.
-+	2014-04-22  Zhenqiang Chen  <zhenqiang.chen@linaro.org>
-+
-+	* config/arm/arm.c (arm_print_operand, thumb_exit): Make sure
-+	GET_MODE_SIZE argument is enum machine_mode.
-+
-+2014-04-28  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	* LINARO-VERSION: Bump version.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
-+	* LINARO-VERSION: New file.
-+	* configure.ac: Add Linaro version string.
---- a/src/gcc/testsuite/gcc.target/arm/pr44788.c
-+++ b/src/gcc/testsuite/gcc.target/arm/pr44788.c
-@@ -2,6 +2,8 @@
- /* { dg-require-effective-target arm_thumb2_ok } */
- /* { dg-options "-Os -fno-strict-aliasing -fPIC -mthumb -march=armv7-a -mfpu=vfp3 -mfloat-abi=softfp" } */
- 
-+extern void foo (float *);
-+
- void joint_decode(float* mlt_buffer1, int t) {
-     int i;
-     float decode_buffer[1060];
---- a/src/gcc/testsuite/gcc.target/arm/vect-rounding-floorf.c
-+++ b/src/gcc/testsuite/gcc.target/arm/vect-rounding-floorf.c
-@@ -5,8 +5,11 @@
- 
- #define N 32
- 
-+float __attribute__((aligned(16))) input[N];
-+float __attribute__((aligned(16))) output[N];
-+
- void
--foo (float *output, float *input)
-+foo ()
- {
-   int i = 0;
-   /* Vectorizable.  */
---- a/src/gcc/testsuite/gcc.target/arm/vect-lceilf_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/vect-lceilf_1.c
-@@ -0,0 +1,21 @@
-+/* { dg-do compile } */
-+/* { dg-require-effective-target arm_v8_neon_ok } */
-+/* { dg-options "-O2 -ffast-math -ftree-vectorize -fdump-tree-vect-all" } */
-+/* { dg-add-options arm_v8_neon } */
-+
-+#define N 32
-+
-+float __attribute__((aligned(16))) input[N];
-+int __attribute__((aligned(16))) output[N];
-+
-+void
-+foo ()
-+{
-+  int i = 0;
-+  /* Vectorizable.  */
-+  for (i = 0; i < N; i++)
-+    output[i] = __builtin_lceilf (input[i]);
-+}
-+
-+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
-+/* { dg-final { cleanup-tree-dump "vect" } } */
---- a/src/gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c
-+++ b/src/gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c
-@@ -3,7 +3,7 @@
- /* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */
- /* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
- 
--extern void baz (float);
-+extern void bar (float);
- 
- void
- foo (float *p, float a, int n)
-@@ -13,4 +13,4 @@
-   while (n--);
- }
- 
--/* { dg-final { scan-assembler "fldmdbs" } } */
-+/* { dg-final { scan-assembler "vldmdb.32" } } */
---- a/src/gcc/testsuite/gcc.target/arm/pr60606-4.c
-+++ b/src/gcc/testsuite/gcc.target/arm/pr60606-4.c
-@@ -0,0 +1,9 @@
-+/* { dg-do compile } */
-+/* { dg-options "-O" } */
-+
-+int
-+f (void)
-+{
-+  register unsigned int r[50] asm ("r1"); /* { dg-error "suitable for a register" } */
-+  return r[1];
-+}
---- a/src/gcc/testsuite/gcc.target/arm/iordi3-opt.c
-+++ b/src/gcc/testsuite/gcc.target/arm/iordi3-opt.c
-@@ -1,4 +1,4 @@
--/* { dg-do compile } */
-+/* { dg-do compile { target { arm_arm_ok || arm_thumb2_ok} } } */
- /* { dg-options "-O1" } */
- 
- unsigned long long or64 (unsigned long long input)
---- a/src/gcc/testsuite/gcc.target/arm/pr58784.c
-+++ b/src/gcc/testsuite/gcc.target/arm/pr58784.c
-@@ -11,6 +11,9 @@
-     char stepsRemoved;
-     ptp_tlv_t tlv[1];
- } ptp_message_announce_t;
-+
-+extern void f (ptp_message_announce_t *);
-+
- int ptplib_send_announce(int sequenceId, int i)
- {
-     ptp_message_announce_t tx_packet;
---- a/src/gcc/testsuite/gcc.target/arm/iordi_notdi-1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/iordi_notdi-1.c
-@@ -0,0 +1,65 @@
-+/* { dg-do run } */
-+/* { dg-options "-O2 -fno-inline --save-temps" } */
-+
-+extern void abort (void);
-+
-+typedef long long s64int;
-+typedef int s32int;
-+typedef unsigned long long u64int;
-+typedef unsigned int u32int;
-+
-+s64int
-+iordi_di_notdi (s64int a, s64int b)
-+{
-+  return (a | ~b);
-+}
-+
-+s64int
-+iordi_di_notzesidi (s64int a, u32int b)
-+{
-+  return (a | ~(u64int) b);
-+}
-+
-+s64int
-+iordi_notdi_zesidi (s64int a, u32int b)
-+{
-+  return (~a | (u64int) b);
-+}
-+
-+s64int
-+iordi_di_notsesidi (s64int a, s32int b)
-+{
-+  return (a | ~(s64int) b);
-+}
-+
-+int main ()
-+{
-+  s64int a64 = 0xdeadbeef00000000ll;
-+  s64int b64 = 0x000000004f4f0112ll;
-+  s64int c64 = 0xdeadbeef000f0000ll;
-+
-+  u32int c32 = 0x01124f4f;
-+  s32int d32 = 0xabbaface;
-+
-+  s64int z = iordi_di_notdi (a64, b64);
-+  if (z != 0xffffffffb0b0feedll)
-+    abort ();
-+
-+  z = iordi_di_notzesidi (a64, c32);
-+  if (z != 0xfffffffffeedb0b0ll)
-+    abort ();
-+
-+  z = iordi_notdi_zesidi (c64, c32);
-+  if (z != 0x21524110fff2ffffll)
-+    abort ();
-+
-+  z = iordi_di_notsesidi (a64, d32);
-+  if (z != 0xdeadbeef54450531ll)
-+    abort ();
-+
-+  return 0;
-+}
-+
-+/* { dg-final { scan-assembler-times "orn\t" 6 { target arm_thumb2 } } } */
-+
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/vfp-ldmias.c
-+++ b/src/gcc/testsuite/gcc.target/arm/vfp-ldmias.c
-@@ -3,7 +3,7 @@
- /* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */
- /* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
- 
--extern void baz (float);
-+extern void bar (float);
- 
- void
- foo (float *p, float a, int n)
-@@ -13,4 +13,4 @@
-   while (n--);
- }
- 
--/* { dg-final { scan-assembler "fldmias" } } */
-+/* { dg-final { scan-assembler "vldmia.32" } } */
---- a/src/gcc/testsuite/gcc.target/arm/cold-lc.c
-+++ b/src/gcc/testsuite/gcc.target/arm/cold-lc.c
-@@ -7,6 +7,7 @@
-     struct task_struct *task;
- };
- extern struct thread_info *current_thread_info (void);
-+extern int show_stack (struct task_struct *, unsigned long *);
- 
- void dump_stack (void)
- {
---- a/src/gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c
-+++ b/src/gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c
-@@ -13,4 +13,4 @@
-   while (n--);
- }
- 
--/* { dg-final { scan-assembler "fldmdbd" } } */
-+/* { dg-final { scan-assembler "vldmdb.64" } } */
---- a/src/gcc/testsuite/gcc.target/arm/vfp-stmdbs.c
-+++ b/src/gcc/testsuite/gcc.target/arm/vfp-stmdbs.c
-@@ -12,4 +12,4 @@
-   while (n--);
- }
- 
--/* { dg-final { scan-assembler "fstmdbs" } } */
-+/* { dg-final { scan-assembler "vstmdb.32" } } */
---- a/src/gcc/testsuite/gcc.target/arm/vfp-ldmiad.c
-+++ b/src/gcc/testsuite/gcc.target/arm/vfp-ldmiad.c
-@@ -13,4 +13,4 @@
-   while (n--);
- }
- 
--/* { dg-final { scan-assembler "fldmiad" } } */
-+/* { dg-final { scan-assembler "vldmia.64" } } */
---- a/src/gcc/testsuite/gcc.target/arm/vfp-stmias.c
-+++ b/src/gcc/testsuite/gcc.target/arm/vfp-stmias.c
-@@ -12,4 +12,4 @@
-   while (n--);
- }
- 
--/* { dg-final { scan-assembler "fstmias" } } */
-+/* { dg-final { scan-assembler "vstmia.32" } } */
---- a/src/gcc/testsuite/gcc.target/arm/vfp-stmdbd.c
-+++ b/src/gcc/testsuite/gcc.target/arm/vfp-stmdbd.c
-@@ -12,4 +12,4 @@
-   while (n--);
- }
- 
--/* { dg-final { scan-assembler "fstmdbd" } } */
-+/* { dg-final { scan-assembler "vstmdb.64" } } */
---- a/src/gcc/testsuite/gcc.target/arm/lceil-vcvt_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/lceil-vcvt_1.c
-@@ -0,0 +1,21 @@
-+/* { dg-do compile } */
-+/* { dg-require-effective-target arm_v8_vfp_ok } */
-+/* { dg-options "-O2 -march=armv8-a" } */
-+/* { dg-add-options arm_v8_vfp } */
-+
-+int
-+foofloat (float x)
-+{
-+  return __builtin_lceilf (x);
-+}
-+
-+/* { dg-final { scan-assembler-times "vcvtp.s32.f32\ts\[0-9\]+, s\[0-9\]+" 1 } } */
-+
-+
-+int
-+foodouble (double x)
-+{
-+  return __builtin_lceil (x);
-+}
-+
-+/* { dg-final { scan-assembler-times "vcvtp.s32.f64\ts\[0-9\]+, d\[0-9\]+" 1 } } */
---- a/src/gcc/testsuite/gcc.target/arm/vfp-stmiad.c
-+++ b/src/gcc/testsuite/gcc.target/arm/vfp-stmiad.c
-@@ -12,4 +12,4 @@
-   while (n--);
- }
- 
--/* { dg-final { scan-assembler "fstmiad" } } */
-+/* { dg-final { scan-assembler "vstmia.64" } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vzips16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vzips16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vzips16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vzips16.x"
-+
-+/* { dg-final { scan-assembler-times "vzip\.16\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vtrns16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vtrns16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vtrns16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vtrns16.x"
-+
-+/* { dg-final { scan-assembler-times "vtrn\.16\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vexts64_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vexts64_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vexts64' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/ext_s64.x"
-+
-+/* Don't scan assembler for vext - it can be optimized into a move from r0.  */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vzipu16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vzipu16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vzipu16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vzipu16.x"
-+
-+/* { dg-final { scan-assembler-times "vzip\.16\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vzipqs8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vzipqs8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vzipQs8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vzipqs8.x"
-+
-+/* { dg-final { scan-assembler-times "vzip\.8\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vextQu8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vextQu8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vextQu8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/extq_u8.x"
-+
-+/* { dg-final { scan-assembler-times "vext\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 15 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vtrnu16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vtrnu16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vtrnu16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vtrnu16.x"
-+
-+/* { dg-final { scan-assembler-times "vtrn\.16\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vtrnqs8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vtrnqs8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vtrnQs8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vtrnqs8.x"
-+
-+/* { dg-final { scan-assembler-times "vtrn\.8\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vtrnqf32_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vtrnqf32_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vtrnQf32' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vtrnqf32.x"
-+
-+/* { dg-final { scan-assembler-times "vtrn\.32\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vextu64_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vextu64_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vextu64' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/ext_u64.x"
-+
-+/* Don't scan assembler for vext - it can be optimized into a move from r0.  */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev64qp8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev64qp8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev64q_p8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev64qp8.x"
-+
-+/* { dg-final { scan-assembler "vrev64\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vuzpqp8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vuzpqp8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vuzpQp8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vuzpqp8.x"
-+
-+/* { dg-final { scan-assembler-times "vuzp\.8\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev32p8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev32p8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev32p8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev32p8.x"
-+
-+/* { dg-final { scan-assembler "vrev32\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vextu8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vextu8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vextu8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/ext_u8.x"
-+
-+/* { dg-final { scan-assembler-times "vext\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 7 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vextQs64_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vextQs64_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vextQs64' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/extq_s64.x"
-+
-+/* { dg-final { scan-assembler-times "vext\.64\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev64qp16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev64qp16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev64q_p16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev64qp16.x"
-+
-+/* { dg-final { scan-assembler "vrev64\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vtrnqs16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vtrnqs16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vtrnQs16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vtrnqs16.x"
-+
-+/* { dg-final { scan-assembler-times "vtrn\.16\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vtrns8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vtrns8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vtrns8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vtrns8.x"
-+
-+/* { dg-final { scan-assembler-times "vtrn\.8\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev64qs32_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev64qs32_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev64q_s32' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev64qs32.x"
-+
-+/* { dg-final { scan-assembler "vrev64\.32\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vextQu64_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vextQu64_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vextQu64' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/extq_u64.x"
-+
-+/* { dg-final { scan-assembler-times "vext\.64\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vtrnqu16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vtrnqu16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vtrnQu16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vtrnqu16.x"
-+
-+/* { dg-final { scan-assembler-times "vtrn\.16\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev64s8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev64s8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev64s8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev64s8.x"
-+
-+/* { dg-final { scan-assembler "vrev64\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev64qu32_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev64qu32_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev64q_u32' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev64qu32.x"
-+
-+/* { dg-final { scan-assembler "vrev64\.32\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vuzpqp16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vuzpqp16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vuzpQp16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vuzpqp16.x"
-+
-+/* { dg-final { scan-assembler-times "vuzp\.16\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vextp16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vextp16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vextp16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/ext_p16.x"
-+
-+/* { dg-final { scan-assembler-times "vext\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 3 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vuzpqs32_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vuzpqs32_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vuzpQs32' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vuzpqs32.x"
-+
-+/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vexts32_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vexts32_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vexts32' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/ext_s32.x"
-+
-+/* { dg-final { scan-assembler-times "vext\.32\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vuzpqu32_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vuzpqu32_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vuzpQu32' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vuzpqu32.x"
-+
-+/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vuzps8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vuzps8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vuzps8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vuzps8.x"
-+
-+/* { dg-final { scan-assembler-times "vuzp\.8\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vextu32_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vextu32_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vextu32' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/ext_u32.x"
-+
-+/* { dg-final { scan-assembler-times "vext\.32\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev32s16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev32s16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev32s16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev32s16.x"
-+
-+/* { dg-final { scan-assembler "vrev32\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vzipqp8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vzipqp8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vzipQp8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vzipqp8.x"
-+
-+/* { dg-final { scan-assembler-times "vzip\.8\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vtrnqp8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vtrnqp8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vtrnQp8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vtrnqp8.x"
-+
-+/* { dg-final { scan-assembler-times "vtrn\.8\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev32qs8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev32qs8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev32q_s8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev32qs8.x"
-+
-+/* { dg-final { scan-assembler "vrev32\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev32u16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev32u16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev32u16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev32u16.x"
-+
-+/* { dg-final { scan-assembler "vrev32\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev64p16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev64p16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev64p16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev64p16.x"
-+
-+/* { dg-final { scan-assembler "vrev64\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev64s32_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev64s32_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev64s32' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev64s32.x"
-+
-+/* { dg-final { scan-assembler "vrev64\.32\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev16qs8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev16qs8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev16q_s8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev16qs8.x"
-+
-+/* { dg-final { scan-assembler "vrev16\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/simd.exp
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/simd.exp
-@@ -0,0 +1,35 @@
-+# Copyright (C) 1997-2014 Free Software Foundation, Inc.
-+
-+# This program is free software; you can redistribute it and/or modify
-+# it under the terms of the GNU General Public License as published by
-+# the Free Software Foundation; either version 3 of the License, or
-+# (at your option) any later version.
-+#
-+# This program is distributed in the hope that it will be useful,
-+# but WITHOUT ANY WARRANTY; without even the implied warranty of
-+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+# GNU General Public License for more details.
-+#
-+# You should have received a copy of the GNU General Public License
-+# along with GCC; see the file COPYING3.  If not see
-+# <http://www.gnu.org/licenses/>.
-+
-+# GCC testsuite that uses the `dg.exp' driver.
-+
-+# Exit immediately if this isn't an ARM target.
-+if ![istarget arm*-*-*] then {
-+  return
-+}
-+
-+# Load support procs.
-+load_lib gcc-dg.exp
-+
-+# Initialize `dg'.
-+dg-init
-+
-+# Main loop.
-+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
-+	"" ""
-+
-+# All done.
-+dg-finish
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev64u32_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev64u32_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev64u32' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev64u32.x"
-+
-+/* { dg-final { scan-assembler "vrev64\.32\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev64qu8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev64qu8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev64q_u8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev64qu8.x"
-+
-+/* { dg-final { scan-assembler "vrev64\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vuzpp16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vuzpp16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vuzpp16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vuzpp16.x"
-+
-+/* { dg-final { scan-assembler-times "vuzp\.16\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vuzps32_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vuzps32_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vuzps32' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vuzps32.x"
-+
-+/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vuzpu32_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vuzpu32_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vuzpu32' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vuzpu32.x"
-+
-+/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vextQp16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vextQp16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vextQp16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/extq_p16.x"
-+
-+/* { dg-final { scan-assembler-times "vext\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 7 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vextQs32_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vextQs32_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vextQs32' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/extq_s32.x"
-+
-+/* { dg-final { scan-assembler-times "vext\.32\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 3 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev32qp16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev32qp16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev32q_p16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev32qp16.x"
-+
-+/* { dg-final { scan-assembler "vrev32\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vzipqp16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vzipqp16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vzipQp16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vzipqp16.x"
-+
-+/* { dg-final { scan-assembler-times "vzip\.16\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vzipqs32_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vzipqs32_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vzipQs32' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vzipqs32.x"
-+
-+/* { dg-final { scan-assembler-times "vzip\.32\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vextQu32_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vextQu32_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vextQu32' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/extq_u32.x"
-+
-+/* { dg-final { scan-assembler-times "vext\.32\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 3 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vtrnp8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vtrnp8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vtrnp8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vtrnp8.x"
-+
-+/* { dg-final { scan-assembler-times "vtrn\.8\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vuzpqu8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vuzpqu8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vuzpQu8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vuzpqu8.x"
-+
-+/* { dg-final { scan-assembler-times "vuzp\.8\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vzips8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vzips8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vzips8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vzips8.x"
-+
-+/* { dg-final { scan-assembler-times "vzip\.8\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vzipqu32_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vzipqu32_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vzipQu32' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vzipqu32.x"
-+
-+/* { dg-final { scan-assembler-times "vzip\.32\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev16s8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev16s8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev16s8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev16s8.x"
-+
-+/* { dg-final { scan-assembler "vrev16\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev32u8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev32u8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev32u8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev32u8.x"
-+
-+/* { dg-final { scan-assembler "vrev32\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev64p8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev64p8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev64p8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev64p8.x"
-+
-+/* { dg-final { scan-assembler "vrev64\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vuzpp8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vuzpp8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vuzpp8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vuzpp8.x"
-+
-+/* { dg-final { scan-assembler-times "vuzp\.8\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vzipp16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vzipp16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vzipp16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vzipp16.x"
-+
-+/* { dg-final { scan-assembler-times "vzip\.16\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vzips32_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vzips32_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vzips32' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vzips32.x"
-+
-+/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vextp64_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vextp64_1.c
-@@ -0,0 +1,26 @@
-+/* Test the `vextp64' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_crypto_ok } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+/* { dg-add-options arm_crypto } */
-+
-+#include "arm_neon.h"
-+
-+extern void abort (void);
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  poly64x1_t in1 = {0};
-+  poly64x1_t in2 = {1};
-+  poly64x1_t actual = vext_p64 (in1, in2, 0);
-+  if (actual != in1)
-+    abort ();
-+
-+  return 0;
-+}
-+
-+/* Don't scan assembler for vext - it can be optimized into a move from r0.
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev32qp8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev32qp8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev32q_p8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev32qp8.x"
-+
-+/* { dg-final { scan-assembler "vrev32\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vtrnp16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vtrnp16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vtrnp16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vtrnp16.x"
-+
-+/* { dg-final { scan-assembler-times "vtrn\.16\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vtrns32_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vtrns32_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vtrns32' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vtrns32.x"
-+
-+/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vextQs8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vextQs8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vextQs8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/extq_s8.x"
-+
-+/* { dg-final { scan-assembler-times "vext\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 15 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev16qp8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev16qp8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev16q_p8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev16qp8.x"
-+
-+/* { dg-final { scan-assembler "vrev16\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vzipu32_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vzipu32_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vzipu32' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vzipu32.x"
-+
-+/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vtrnu32_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vtrnu32_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vtrnu32' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vtrnu32.x"
-+
-+/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vzipqu8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vzipqu8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vzipQu8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vzipqu8.x"
-+
-+/* { dg-final { scan-assembler-times "vzip\.8\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vtrnqu8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vtrnqu8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vtrnQu8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vtrnqu8.x"
-+
-+/* { dg-final { scan-assembler-times "vtrn\.8\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev64qf32_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev64qf32_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev64q_f32' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev64qf32.x"
-+
-+/* { dg-final { scan-assembler "vrev64\.32\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vuzpqf32_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vuzpqf32_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vuzpQf32' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vuzpqf32.x"
-+
-+/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vzipp8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vzipp8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vzipp8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vzipp8.x"
-+
-+/* { dg-final { scan-assembler-times "vzip\.8\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vextf32_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vextf32_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vextf32' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/ext_f32.x"
-+
-+/* { dg-final { scan-assembler-times "vext\.32\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vextQp64_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vextQp64_1.c
-@@ -0,0 +1,33 @@
-+/* Test the `vextQp64' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_crypto_ok } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+/* { dg-add-options arm_crypto } */
-+
-+#include "arm_neon.h"
-+
-+extern void abort (void);
-+
-+poly64x2_t
-+test_vextq_p64_1 (poly64x2_t a, poly64x2_t b)
-+{
-+  return vextq_p64(a, b, 1);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i, off;
-+  poly64x2_t in1 = {0, 1};
-+  poly64x2_t in2 = {2, 3};
-+  poly64x2_t actual = test_vextq_p64_1 (in1, in2);
-+  for (i = 0; i < 2; i++)
-+    if (actual[i] != i + 1)
-+      abort ();
-+
-+  return 0;
-+}
-+
-+/* { dg-final { scan-assembler-times "vext\.64\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vexts8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vexts8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vexts8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/ext_s8.x"
-+
-+/* { dg-final { scan-assembler-times "vext\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 7 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev16p8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev16p8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev16p8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev16p8.x"
-+
-+/* { dg-final { scan-assembler "vrev16\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vtrnqp16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vtrnqp16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vtrnQp16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vtrnqp16.x"
-+
-+/* { dg-final { scan-assembler-times "vtrn\.16\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vtrnqs32_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vtrnqs32_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vtrnQs32' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vtrnqs32.x"
-+
-+/* { dg-final { scan-assembler-times "vtrn\.32\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vtrnqu32_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vtrnqu32_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vtrnQu32' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vtrnqu32.x"
-+
-+/* { dg-final { scan-assembler-times "vtrn\.32\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vtrnu8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vtrnu8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vtrnu8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vtrnu8.x"
-+
-+/* { dg-final { scan-assembler-times "vtrn\.8\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev64q_s16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev64qs16.x"
-+
-+/* { dg-final { scan-assembler "vrev64\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev64f32_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev64f32_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev64f32' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev64f32.x"
-+
-+/* { dg-final { scan-assembler "vrev64\.32\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev64u8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev64u8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev64u8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev64u8.x"
-+
-+/* { dg-final { scan-assembler "vrev64\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev64qu16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev64qu16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev64q_u16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev64qu16.x"
-+
-+/* { dg-final { scan-assembler "vrev64\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev32p16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev32p16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev32p16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev32p16.x"
-+
-+/* { dg-final { scan-assembler "vrev32\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vextQp8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vextQp8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vextQp8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/extq_p8.x"
-+
-+/* { dg-final { scan-assembler-times "vext\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 15 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vuzpf32_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vuzpf32_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vuzpf32' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vuzpf32.x"
-+
-+/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vuzpqs16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vuzpqs16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vuzpQs16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vuzpqs16.x"
-+
-+/* { dg-final { scan-assembler-times "vuzp\.16\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vexts16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vexts16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vexts16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/ext_s16.x"
-+
-+/* { dg-final { scan-assembler-times "vext\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 3 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vuzpqu16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vuzpqu16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vuzpQu16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vuzpqu16.x"
-+
-+/* { dg-final { scan-assembler-times "vuzp\.16\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vuzpu8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vuzpu8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vuzpu8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vuzpu8.x"
-+
-+/* { dg-final { scan-assembler-times "vuzp\.8\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vextQf32_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vextQf32_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vextQf32' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/extq_f32.x"
-+
-+/* { dg-final { scan-assembler-times "vext\.32\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 3 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vextu16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vextu16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vextu16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/ext_u16.x"
-+
-+/* { dg-final { scan-assembler-times "vext\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 3 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vzipqf32_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vzipqf32_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vzipQf32' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vzipqf32.x"
-+
-+/* { dg-final { scan-assembler-times "vzip\.32\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev32qu8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev32qu8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev32q_u8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev32qu8.x"
-+
-+/* { dg-final { scan-assembler "vrev32\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev64s16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev64s16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev64s16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev64s16.x"
-+
-+/* { dg-final { scan-assembler "vrev64\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev16qu8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev16qu8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev16q_u8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev16qu8.x"
-+
-+/* { dg-final { scan-assembler "vrev16\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev64u16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev64u16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev64u16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev64u16.x"
-+
-+/* { dg-final { scan-assembler "vrev64\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev64qs8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev64qs8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev64q_s8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev64qs8.x"
-+
-+/* { dg-final { scan-assembler "vrev64\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vextp8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vextp8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vextp8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/ext_p8.x"
-+
-+/* { dg-final { scan-assembler-times "vext\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 7 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vuzps16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vuzps16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vuzps16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vuzps16.x"
-+
-+/* { dg-final { scan-assembler-times "vuzp\.16\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vuzpqs8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vuzpqs8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vuzpQs8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vuzpqs8.x"
-+
-+/* { dg-final { scan-assembler-times "vuzp\.8\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vuzpu16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vuzpu16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vuzpu16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vuzpu16.x"
-+
-+/* { dg-final { scan-assembler-times "vuzp\.16\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vextQs16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vextQs16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vextQs16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/extq_s16.x"
-+
-+/* { dg-final { scan-assembler-times "vext\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 7 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev32s8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev32s8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev32s8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev32s8.x"
-+
-+/* { dg-final { scan-assembler "vrev32\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev32qs16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev32qs16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev32q_s16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev32qs16.x"
-+
-+/* { dg-final { scan-assembler "vrev32\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vextQu16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vextQu16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vextQu16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/extq_u16.x"
-+
-+/* { dg-final { scan-assembler-times "vext\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 7 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vzipf32_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vzipf32_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vzipf32' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vzipf32.x"
-+
-+/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vzipqs16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vzipqs16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vzipQs16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vzipqs16.x"
-+
-+/* { dg-final { scan-assembler-times "vzip\.16\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vtrnf32_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vtrnf32_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vtrnf32' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vtrnf32.x"
-+
-+/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev32qu16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev32qu16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev32q_u16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev32qu16.x"
-+
-+/* { dg-final { scan-assembler "vrev32\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vzipqu16_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vzipqu16_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vzipQu16' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vzipqu16.x"
-+
-+/* { dg-final { scan-assembler-times "vzip\.16\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vzipu8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vzipu8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vzipu8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -O1 -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vzipu8.x"
-+
-+/* { dg-final { scan-assembler-times "vzip\.8\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/simd/vrev16u8_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/simd/vrev16u8_1.c
-@@ -0,0 +1,12 @@
-+/* Test the `vrev16u8' ARM Neon intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+/* { dg-add-options arm_neon } */
-+
-+#include "arm_neon.h"
-+#include "../../aarch64/simd/vrev16u8.x"
-+
-+/* { dg-final { scan-assembler "vrev16\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/vect-lfloorf_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/vect-lfloorf_1.c
-@@ -0,0 +1,21 @@
-+/* { dg-do compile } */
-+/* { dg-require-effective-target arm_v8_neon_ok } */
-+/* { dg-options "-O2 -ffast-math -ftree-vectorize -fdump-tree-vect-all" } */
-+/* { dg-add-options arm_v8_neon } */
-+
-+#define N 32
-+
-+float __attribute__((aligned(16))) input[N];
-+int __attribute__((aligned(16))) output[N];
-+
-+void
-+foo ()
-+{
-+  int i = 0;
-+  /* Vectorizable.  */
-+  for (i = 0; i < N; i++)
-+    output[i] = __builtin_lfloorf (input[i]);
-+}
-+
-+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
-+/* { dg-final { cleanup-tree-dump "vect" } } */
---- a/src/gcc/testsuite/gcc.target/arm/pr51835.c
-+++ b/src/gcc/testsuite/gcc.target/arm/pr51835.c
-@@ -13,5 +13,5 @@
-   return (unsigned int)d;
- }
- 
--/* { dg-final { scan-assembler-times "fmrrd\[\\t \]+r0,\[\\t \]*r1,\[\\t \]*d0" 2 { target { arm_little_endian } } } } */
--/* { dg-final { scan-assembler-times "fmrrd\[\\t \]+r1,\[\\t \]*r0,\[\\t \]*d0" 2 { target { ! arm_little_endian } } } } */
-+/* { dg-final { scan-assembler-times "vmov\[\\t \]+r0,\[\\t \]*r1,\[\\t \]*d0" 2 { target { arm_little_endian } } } } */
-+/* { dg-final { scan-assembler-times "vmov\[\\t \]+r1,\[\\t \]*r0,\[\\t \]*d0" 2 { target { ! arm_little_endian } } } } */
---- a/src/gcc/testsuite/gcc.target/arm/20031108-1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/20031108-1.c
-@@ -20,6 +20,9 @@
- 
- Rec_Pointer Ptr_Glob;
- 
-+extern int Proc_7 (int, int, int *);
-+
-+void
- Proc_1 (Ptr_Val_Par)
-     Rec_Pointer Ptr_Val_Par;
- {
---- a/src/gcc/testsuite/gcc.target/arm/neon-modes-2.c
-+++ b/src/gcc/testsuite/gcc.target/arm/neon-modes-2.c
-@@ -11,6 +11,8 @@
- 
- #define MANY(A) A (0), A (1), A (2), A (3), A (4), A (5)
- 
-+extern void foo (int *, int *);
-+
- void
- bar (uint32_t *ptr, int y)
- {
---- a/src/gcc/testsuite/gcc.target/arm/vect-rounding-roundf.c
-+++ b/src/gcc/testsuite/gcc.target/arm/vect-rounding-roundf.c
-@@ -5,8 +5,11 @@
- 
- #define N 32
- 
-+float __attribute__((aligned(16))) input[N];
-+float __attribute__((aligned(16))) output[N];
-+
- void
--foo (float *output, float *input)
-+foo ()
- {
-   int i = 0;
-   /* Vectorizable.  */
---- a/src/gcc/testsuite/gcc.target/arm/pr43920-2.c
-+++ b/src/gcc/testsuite/gcc.target/arm/pr43920-2.c
-@@ -4,6 +4,8 @@
- 
- #include <stdio.h>
- 
-+extern int lseek(int, long, int);
-+
- int getFileStartAndLength (int fd, int *start_, size_t *length_)
- {
-       int start, end;
---- a/src/gcc/testsuite/gcc.target/arm/xordi3-opt.c
-+++ b/src/gcc/testsuite/gcc.target/arm/xordi3-opt.c
-@@ -1,4 +1,4 @@
--/* { dg-do compile } */
-+/* { dg-do compile { target { arm_arm_ok || arm_thumb2_ok} } } */
- /* { dg-options "-O1" } */
- 
- unsigned long long xor64 (unsigned long long input)
---- a/src/gcc/testsuite/gcc.target/arm/vect-lroundf_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/vect-lroundf_1.c
-@@ -0,0 +1,21 @@
-+/* { dg-do compile } */
-+/* { dg-require-effective-target arm_v8_neon_ok } */
-+/* { dg-options "-O2 -ffast-math -ftree-vectorize -fdump-tree-vect-all" } */
-+/* { dg-add-options arm_v8_neon } */
-+
-+#define N 32
-+
-+float __attribute__((aligned(16))) input[N];
-+int __attribute__((aligned(16))) output[N];
-+
-+void
-+foo ()
-+{
-+  int i = 0;
-+  /* Vectorizable.  */
-+  for (i = 0; i < N; i++)
-+    output[i] = __builtin_lroundf (input[i]);
-+}
-+
-+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
-+/* { dg-final { cleanup-tree-dump "vect" } } */
---- a/src/gcc/testsuite/gcc.target/arm/tail-long-call.c
-+++ b/src/gcc/testsuite/gcc.target/arm/tail-long-call.c
-@@ -0,0 +1,12 @@
-+/* { dg-skip-if "need at least armv5te" { *-*-* } { "-march=armv[234]*" "-mthumb" } { "" } } */
-+/* { dg-options "-O2 -march=armv5te -marm" } */
-+/* { dg-final { scan-assembler "bx" } } */
-+/* { dg-final { scan-assembler-not "blx" } } */
-+
-+int lcal (int) __attribute__ ((long_call));
-+
-+int
-+dec (int a)
-+{
-+  return lcal (a);
-+}
---- a/src/gcc/testsuite/gcc.target/arm/vect-rounding-btruncf.c
-+++ b/src/gcc/testsuite/gcc.target/arm/vect-rounding-btruncf.c
-@@ -5,8 +5,11 @@
- 
- #define N 32
- 
-+float __attribute__((aligned(16))) input[N];
-+float __attribute__((aligned(16))) output[N];
-+
- void
--foo (float *output, float *input)
-+foo ()
- {
-   int i = 0;
-   /* Vectorizable.  */
---- a/src/gcc/testsuite/gcc.target/arm/pr61948.c
-+++ b/src/gcc/testsuite/gcc.target/arm/pr61948.c
-@@ -0,0 +1,16 @@
-+/* PR target/61948 */
-+/* { dg-do compile } */
-+/* { dg-require-effective-target arm_neon_ok } */
-+/* { dg-require-effective-target arm_thumb2_ok } */
-+/* { dg-options "-O2 -mthumb" } */
-+/* { dg-add-options arm_neon } */
-+
-+long long f (long long *c)
-+{
-+  long long t = c[0];
-+  asm ("nop" : : : "r0", "r3", "r4", "r5",
-+		   "r6", "r7", "r8", "r9",
-+		   "r10", "r11", "r12", "memory");
-+  return t >> 1;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/arm/pr51968.c
-+++ b/src/gcc/testsuite/gcc.target/arm/pr51968.c
-@@ -1,6 +1,6 @@
- /* PR target/51968 */
- /* { dg-do compile } */
--/* { dg-options "-O2 -march=armv7-a -mfloat-abi=softfp -mfpu=neon" } */
-+/* { dg-options "-O2 -Wno-implicit-function-declaration -march=armv7-a -mfloat-abi=softfp -mfpu=neon" } */
- /* { dg-require-effective-target arm_neon_ok } */
- 
- typedef __builtin_neon_qi int8x8_t __attribute__ ((__vector_size__ (8)));
---- a/src/gcc/testsuite/gcc.target/arm/lround-vcvt_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/lround-vcvt_1.c
-@@ -0,0 +1,21 @@
-+/* { dg-do compile } */
-+/* { dg-require-effective-target arm_v8_vfp_ok } */
-+/* { dg-options "-O2 -march=armv8-a -ffast-math" } */
-+/* { dg-add-options arm_v8_vfp } */
-+
-+int
-+foofloat (float x)
-+{
-+  return __builtin_lroundf (x);
-+}
-+
-+/* { dg-final { scan-assembler-times "vcvta.s32.f32\ts\[0-9\]+, s\[0-9\]+" 1 } } */
-+
-+
-+int
-+foodouble (double x)
-+{
-+  return __builtin_lround (x);
-+}
-+
-+/* { dg-final { scan-assembler-times "vcvta.s32.f64\ts\[0-9\]+, d\[0-9\]+" 1 } } */
---- a/src/gcc/testsuite/gcc.target/arm/pr60650.c
-+++ b/src/gcc/testsuite/gcc.target/arm/pr60650.c
-@@ -20,6 +20,10 @@
- int a, c, d;
- long long e;
- 
-+extern int foo1 (struct btrfs_root *, int, int, int);
-+extern int foo2 (struct btrfs_root *, int, int);
-+
-+int
- truncate_one_csum (struct btrfs_root *p1, long long p2, long long p3)
- {
-   int f, g, i = p1->fs_info->sb->s_blocksize_bits;
---- a/src/gcc/testsuite/gcc.target/arm/vfp-1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/vfp-1.c
-@@ -11,40 +11,40 @@
- 
- void test_sf() {
-   /* abssf2_vfp */
--  /* { dg-final { scan-assembler "fabss" } } */
-+  /* { dg-final { scan-assembler "vabs.f32" } } */
-   f1 = fabsf (f1);
-   /* negsf2_vfp */
--  /* { dg-final { scan-assembler "fnegs" } } */
-+  /* { dg-final { scan-assembler "vneg.f32" } } */
-   f1 = -f1;
-   /* addsf3_vfp */
--  /* { dg-final { scan-assembler "fadds" } } */
-+  /* { dg-final { scan-assembler "vadd.f32" } } */
-   f1 = f2 + f3;
-   /* subsf3_vfp */
--  /* { dg-final { scan-assembler "fsubs" } } */
-+  /* { dg-final { scan-assembler "vsub.f32" } } */
-   f1 = f2 - f3;
-   /* divsf3_vfp */
--  /* { dg-final { scan-assembler "fdivs" } } */
-+  /* { dg-final { scan-assembler "vdiv.f32" } } */
-   f1 = f2 / f3;
-   /* mulsf3_vfp */
--  /* { dg-final { scan-assembler "fmuls" } } */
-+  /* { dg-final { scan-assembler "vmul.f32" } } */
-   f1 = f2 * f3;
-   /* mulsf3negsf_vfp */
--  /* { dg-final { scan-assembler "fnmuls" } } */
-+  /* { dg-final { scan-assembler "vnmul.f32" } } */
-   f1 = -f2 * f3;
-   /* mulsf3addsf_vfp */
--  /* { dg-final { scan-assembler "fmacs" } } */
-+  /* { dg-final { scan-assembler "vmla.f32" } } */
-   f1 = f2 * f3 + f1;
-   /* mulsf3subsf_vfp */
--  /* { dg-final { scan-assembler "fmscs" } } */
-+  /* { dg-final { scan-assembler "vnmls.f32" } } */
-   f1 = f2 * f3 - f1;
-   /* mulsf3negsfaddsf_vfp */
--  /* { dg-final { scan-assembler "fnmacs" } } */
-+  /* { dg-final { scan-assembler "vmls.f32" } } */
-   f1 = f2 - f3 * f1;
-   /* mulsf3negsfsubsf_vfp */
--  /* { dg-final { scan-assembler "fnmscs" } } */
-+  /* { dg-final { scan-assembler "vnmla.f32" } } */
-   f1 = -f2 * f3 - f1;
-   /* sqrtsf2_vfp */
--  /* { dg-final { scan-assembler "fsqrts" } } */
-+  /* { dg-final { scan-assembler "vsqrt.f32" } } */
-   f1 = sqrtf (f1);
- }
- 
-@@ -52,40 +52,40 @@
- 
- void test_df() {
-   /* absdf2_vfp */
--  /* { dg-final { scan-assembler "fabsd" } } */
-+  /* { dg-final { scan-assembler "vabs.f64" } } */
-   d1 = fabs (d1);
-   /* negdf2_vfp */
--  /* { dg-final { scan-assembler "fnegd" } } */
-+  /* { dg-final { scan-assembler "vneg.f64" } } */
-   d1 = -d1;
-   /* adddf3_vfp */
--  /* { dg-final { scan-assembler "faddd" } } */
-+  /* { dg-final { scan-assembler "vadd.f64" } } */
-   d1 = d2 + d3;
-   /* subdf3_vfp */
--  /* { dg-final { scan-assembler "fsubd" } } */
-+  /* { dg-final { scan-assembler "vsub.f64" } } */
-   d1 = d2 - d3;
-   /* divdf3_vfp */
--  /* { dg-final { scan-assembler "fdivd" } } */
-+  /* { dg-final { scan-assembler "vdiv.f64" } } */
-   d1 = d2 / d3;
-   /* muldf3_vfp */
--  /* { dg-final { scan-assembler "fmuld" } } */
-+  /* { dg-final { scan-assembler "vmul.f64" } } */
-   d1 = d2 * d3;
-   /* muldf3negdf_vfp */
--  /* { dg-final { scan-assembler "fnmuld" } } */
-+  /* { dg-final { scan-assembler "vnmul.f64" } } */
-   d1 = -d2 * d3;
-   /* muldf3adddf_vfp */
--  /* { dg-final { scan-assembler "fmacd" } } */
-+  /* { dg-final { scan-assembler "vmla.f64" } } */
-   d1 = d2 * d3 + d1;
-   /* muldf3subdf_vfp */
--  /* { dg-final { scan-assembler "fmscd" } } */
-+  /* { dg-final { scan-assembler "vnmls.f64" } } */
-   d1 = d2 * d3 - d1;
-   /* muldf3negdfadddf_vfp */
--  /* { dg-final { scan-assembler "fnmacd" } } */
-+  /* { dg-final { scan-assembler "vmls.f64" } } */
-   d1 = d2 - d3 * d1;
-   /* muldf3negdfsubdf_vfp */
--  /* { dg-final { scan-assembler "fnmscd" } } */
-+  /* { dg-final { scan-assembler "vnmla.f64" } } */
-   d1 = -d2 * d3 - d1;
-   /* sqrtdf2_vfp */
--  /* { dg-final { scan-assembler "fsqrtd" } } */
-+  /* { dg-final { scan-assembler "vsqrt.f64" } } */
-   d1 = sqrt (d1);
- }
- 
-@@ -94,46 +94,46 @@
- 
- void test_convert () {
-   /* extendsfdf2_vfp */
--  /* { dg-final { scan-assembler "fcvtds" } } */
-+  /* { dg-final { scan-assembler "vcvt.f64.f32" } } */
-   d1 = f1;
-   /* truncdfsf2_vfp */
--  /* { dg-final { scan-assembler "fcvtsd" } } */
-+  /* { dg-final { scan-assembler "vcvt.f32.f64" } } */
-   f1 = d1;
-   /* truncsisf2_vfp */
--  /* { dg-final { scan-assembler "ftosizs" } } */
-+  /* { dg-final { scan-assembler "vcvt.s32.f32" } } */
-   i1 = f1;
-   /* truncsidf2_vfp */
--  /* { dg-final { scan-assembler "ftosizd" } } */
-+  /* { dg-final { scan-assembler "vcvt.s32.f64" } } */
-   i1 = d1;
-   /* fixuns_truncsfsi2 */
--  /* { dg-final { scan-assembler "ftouizs" } } */
-+  /* { dg-final { scan-assembler "vcvt.u32.f32" } } */
-   u1 = f1;
-   /* fixuns_truncdfsi2 */
--  /* { dg-final { scan-assembler "ftouizd" } } */
-+  /* { dg-final { scan-assembler "vcvt.u32.f64" } } */
-   u1 = d1;
-   /* floatsisf2_vfp */
--  /* { dg-final { scan-assembler "fsitos" } } */
-+  /* { dg-final { scan-assembler "vcvt.f32.s32" } } */
-   f1 = i1;
-   /* floatsidf2_vfp */
--  /* { dg-final { scan-assembler "fsitod" } } */
-+  /* { dg-final { scan-assembler "vcvt.f64.s32" } } */
-   d1 = i1;
-   /* floatunssisf2 */
--  /* { dg-final { scan-assembler "fuitos" } } */
-+  /* { dg-final { scan-assembler "vcvt.f32.u32" } } */
-   f1 = u1;
-   /* floatunssidf2 */
--  /* { dg-final { scan-assembler "fuitod" } } */
-+  /* { dg-final { scan-assembler "vcvt.f64.u32" } } */
-   d1 = u1;
- }
- 
- void test_ldst (float f[], double d[]) {
--  /* { dg-final { scan-assembler "flds.+ \\\[r0, #1020\\\]" } } */
--  /* { dg-final { scan-assembler "flds.+ \\\[r\[0-9\], #-1020\\\]" { target { arm32 && { ! arm_thumb2_ok } } } } } */
-+  /* { dg-final { scan-assembler "vldr.32.+ \\\[r0, #1020\\\]" } } */
-+  /* { dg-final { scan-assembler "vldr.32.+ \\\[r\[0-9\], #-1020\\\]" { target { arm32 && { ! arm_thumb2_ok } } } } } */
-   /* { dg-final { scan-assembler "add.+ r0, #1024" } } */
--  /* { dg-final { scan-assembler "fsts.+ \\\[r\[0-9\]\\\]\n" } } */
-+  /* { dg-final { scan-assembler "vstr.32.+ \\\[r\[0-9\]\\\]\n" } } */
-   f[256] = f[255] + f[-255];
- 
--  /* { dg-final { scan-assembler "fldd.+ \\\[r1, #1016\\\]" } } */
--  /* { dg-final { scan-assembler "fldd.+ \\\[r\[1-9\], #-1016\\\]" { target { arm32 && { ! arm_thumb2_ok } } } } } */
--  /* { dg-final { scan-assembler "fstd.+ \\\[r1, #256\\\]" } } */
-+  /* { dg-final { scan-assembler "vldr.64.+ \\\[r1, #1016\\\]" } } */
-+  /* { dg-final { scan-assembler "vldr.64.+ \\\[r\[1-9\], #-1016\\\]" { target { arm32 && { ! arm_thumb2_ok } } } } } */
-+  /* { dg-final { scan-assembler "vstr.64.+ \\\[r1, #256\\\]" } } */
-   d[32] = d[127] + d[-127];
- }
---- a/src/gcc/testsuite/gcc.target/arm/vect-copysignf.c
-+++ b/src/gcc/testsuite/gcc.target/arm/vect-copysignf.c
-@@ -0,0 +1,36 @@
-+/* { dg-do run } */
-+/* { dg-require-effective-target arm_neon_hw } */
-+/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-details" } */
-+/* { dg-add-options "arm_neon" } */
-+
-+extern void abort ();
-+
-+#define N 16
-+float a[N] = {-0.1f, -3.2f, -6.3f, -9.4f,
-+	      -12.5f, -15.6f, -18.7f, -21.8f,
-+	      24.9f, 27.1f, 30.2f, 33.3f,
-+	      36.4f, 39.5f, 42.6f, 45.7f};
-+float b[N] = {-1.2f, 3.4f, -5.6f, 7.8f,
-+	      -9.0f, 1.0f, -2.0f, 3.0f,
-+	      -4.0f, -5.0f, 6.0f, 7.0f,
-+	      -8.0f, -9.0f, 10.0f, 11.0f};
-+float r[N];
-+
-+int
-+main (void)
-+{
-+  int i;
-+
-+  for (i = 0; i < N; i++)
-+    r[i] = __builtin_copysignf (a[i], b[i]);
-+
-+  /* check results:  */
-+  for (i = 0; i < N; i++)
-+    if (r[i] != __builtin_copysignf (a[i], b[i]))
-+      abort ();
-+
-+  return 0;
-+}
-+
-+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
-+/* { dg-final { cleanup-tree-dump "vect" } } */
---- a/src/gcc/testsuite/gcc.target/arm/rev16.c
-+++ b/src/gcc/testsuite/gcc.target/arm/rev16.c
-@@ -0,0 +1,35 @@
-+/* { dg-options "-O2" } */
-+/* { dg-do run } */
-+
-+extern void abort (void);
-+
-+typedef unsigned int __u32;
-+
-+__u32
-+__rev16_32_alt (__u32 x)
-+{
-+  return (((__u32)(x) & (__u32)0xff00ff00UL) >> 8)
-+         | (((__u32)(x) & (__u32)0x00ff00ffUL) << 8);
-+}
-+
-+__u32
-+__rev16_32 (__u32 x)
-+{
-+  return (((__u32)(x) & (__u32)0x00ff00ffUL) << 8)
-+         | (((__u32)(x) & (__u32)0xff00ff00UL) >> 8);
-+}
-+
-+int
-+main (void)
-+{
-+  volatile __u32 in32 = 0x12345678;
-+  volatile __u32 expected32 = 0x34127856;
-+
-+  if (__rev16_32 (in32) != expected32)
-+    abort ();
-+
-+  if (__rev16_32_alt (in32) != expected32)
-+    abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/arm/anddi_notdi-1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/anddi_notdi-1.c
-@@ -0,0 +1,65 @@
-+/* { dg-do run } */
-+/* { dg-options "-O2 -fno-inline --save-temps" } */
-+
-+extern void abort (void);
-+
-+typedef long long s64int;
-+typedef int s32int;
-+typedef unsigned long long u64int;
-+typedef unsigned int u32int;
-+
-+s64int
-+anddi_di_notdi (s64int a, s64int b)
-+{
-+  return (a & ~b);
-+}
-+
-+s64int
-+anddi_di_notzesidi (s64int a, u32int b)
-+{
-+  return (a & ~(u64int) b);
-+}
-+
-+s64int
-+anddi_notdi_zesidi (s64int a, u32int b)
-+{
-+  return (~a & (u64int) b);
-+}
-+
-+s64int
-+anddi_di_notsesidi (s64int a, s32int b)
-+{
-+  return (a & ~(s64int) b);
-+}
-+
-+int main ()
-+{
-+  s64int a64 = 0xdeadbeef0000ffffll;
-+  s64int b64 = 0x000000005f470112ll;
-+  s64int c64 = 0xdeadbeef300f0000ll;
-+
-+  u32int c32 = 0x01124f4f;
-+  s32int d32 = 0xabbaface;
-+
-+  s64int z = anddi_di_notdi (c64, b64);
-+  if (z != 0xdeadbeef20080000ll)
-+    abort ();
-+
-+  z = anddi_di_notzesidi (a64, c32);
-+  if (z != 0xdeadbeef0000b0b0ll)
-+    abort ();
-+
-+  z = anddi_notdi_zesidi (c64, c32);
-+  if (z != 0x0000000001104f4fll)
-+    abort ();
-+
-+  z = anddi_di_notsesidi (a64, d32);
-+  if (z != 0x0000000000000531ll)
-+    abort ();
-+
-+  return 0;
-+}
-+
-+/* { dg-final { scan-assembler-times "bic\t" 6 } } */
-+
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/arm/pr63210.c
-+++ b/src/gcc/testsuite/gcc.target/arm/pr63210.c
-@@ -0,0 +1,12 @@
-+/* { dg-do assemble } */
-+/* { dg-options "-mthumb -Os " }  */
-+/* { dg-require-effective-target arm_thumb1_ok } */
-+
-+int foo1 (int c);
-+int foo2 (int c);
-+
-+int test (int c)
-+{
-+  return (foo1 (c) || foo2 (c));
-+}
-+/* { dg-final { object-size text <= 28 } } */
---- a/src/gcc/testsuite/gcc.target/arm/pr60606-2.c
-+++ b/src/gcc/testsuite/gcc.target/arm/pr60606-2.c
-@@ -0,0 +1,10 @@
-+/* { dg-do compile } */
-+/* { dg-options "-O" } */
-+
-+int
-+f (void)
-+{
-+  register unsigned pc asm ("pc"); /* { dg-error "not general enough" } */
-+  
-+  return pc > 0x12345678;
-+}
---- a/src/gcc/testsuite/gcc.target/arm/vect-rounding-ceilf.c
-+++ b/src/gcc/testsuite/gcc.target/arm/vect-rounding-ceilf.c
-@@ -5,8 +5,11 @@
- 
- #define N 32
- 
-+float __attribute__((aligned(16))) input[N];
-+float __attribute__((aligned(16))) output[N];
-+
- void
--foo (float *output, float *input)
-+foo ()
- {
-   int i = 0;
-   /* Vectorizable.  */
---- a/src/gcc/testsuite/gcc.target/arm/pr60650-2.c
-+++ b/src/gcc/testsuite/gcc.target/arm/pr60650-2.c
-@@ -4,17 +4,19 @@
- int a, h, j;
- long long d, e, i;
- int f;
-+int
- fn1 (void *p1, int p2)
- {
-     switch (p2)
-     case 8:
- {
--    register b = *(long long *) p1, c asm ("r2");
-+    register int b = *(long long *) p1, c asm ("r2");
-     asm ("%0": "=r" (a), "=r" (c):"r" (b), "r" (0));
-     *(long long *) p1 = c;
-     }
- }
- 
-+int
- fn2 ()
- {
-     int k;
-@@ -27,8 +29,8 @@
-         case 0:
-         (
-         {
--            register l asm ("r4");
--            register m asm ("r0");
-+            register int l asm ("r4");
-+            register int m asm ("r0");
-             asm ("  .err  .endif\n\t": "=r" (h), "=r" (j):"r" (m),
-             "r"
-             (l));;
---- a/src/gcc/testsuite/gcc.target/arm/pr55642.c
-+++ b/src/gcc/testsuite/gcc.target/arm/pr55642.c
-@@ -2,6 +2,8 @@
- /* { dg-do compile } */
- /* { dg-require-effective-target arm_thumb2_ok } */
- 
-+extern int abs (int);
-+
- int
- foo (int v)
- {
---- a/src/gcc/testsuite/gcc.target/arm/lfloor-vcvt_1.c
-+++ b/src/gcc/testsuite/gcc.target/arm/lfloor-vcvt_1.c
-@@ -0,0 +1,21 @@
-+/* { dg-do compile } */
-+/* { dg-require-effective-target arm_v8_vfp_ok } */
-+/* { dg-options "-O2 -march=armv8-a" } */
-+/* { dg-add-options arm_v8_vfp } */
-+
-+int
-+foofloat (float x)
-+{
-+  return __builtin_lfloorf (x);
-+}
-+
-+/* { dg-final { scan-assembler-times "vcvtm.s32.f32\ts\[0-9\]+, s\[0-9\]+" 1 } } */
-+
-+
-+int
-+foodouble (double x)
-+{
-+  return __builtin_lfloor (x);
-+}
-+
-+/* { dg-final { scan-assembler-times "vcvtm.s32.f64\ts\[0-9\]+, d\[0-9\]+" 1 } } */
---- a/src/gcc/testsuite/gcc.target/arm/pr60606-3.c
-+++ b/src/gcc/testsuite/gcc.target/arm/pr60606-3.c
-@@ -0,0 +1,9 @@
-+/* { dg-do compile } */
-+/* { dg-options "-O" } */
-+
-+int
-+f (void)
-+{
-+  register unsigned int r asm ("cc"); /* { dg-error "not general enough|suitable for data type" } */
-+  return r;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/test_frame_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_1.c
-@@ -0,0 +1,19 @@
-+/* Verify:
-+     * -fomit-frame-pointer.
-+     * withoug outgoing.
-+     * total frame size <= 256.
-+     * number of callee-save reg == 1.
-+     * optimized code should use "str !" for stack adjustment.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-O2 -fomit-frame-pointer --save-temps" } */
-+
-+#include "test_frame_common.h"
-+
-+t_frame_pattern (test1, 200, )
-+t_frame_run (test1)
-+
-+/* { dg-final { scan-assembler-times "str\tx30, \\\[sp, -\[0-9\]+\\\]!" 2 } } */
-+/* { dg-final { scan-assembler-times "ldr\tx30, \\\[sp\\\], \[0-9\]+" 3 } } */
-+
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/test_frame_9.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_9.c
-@@ -0,0 +1,17 @@
-+/* Verify:
-+     * -fomit-frame-pointer.
-+     * with outgoing.
-+     * total frame size > 512.
-+       area except outgoing <= 512
-+     * number of callee-saved reg = 1.
-+     * Split stack adjustment into two subtractions.
-+       the first subtractions couldn't be optimized
-+       into "str !" as it's > 256.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-O2 -fomit-frame-pointer" } */
-+
-+#include "test_frame_common.h"
-+
-+t_frame_pattern_outgoing (test9, 480, , 24, a[8], a[9], a[10])
-+t_frame_run (test9)
---- a/src/gcc/testsuite/gcc.target/aarch64/vldN_lane_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/vldN_lane_1.c
-@@ -0,0 +1,97 @@
-+/* { dg-do run } */
-+/* { dg-options "-O3 -fno-inline" } */
-+
-+#include <arm_neon.h>
-+
-+extern void abort (void);
-+
-+#define VARIANTS(VARIANT, STRUCT)	\
-+VARIANT (uint8, , 8, _u8, 6, STRUCT)	\
-+VARIANT (uint16, , 4, _u16, 3, STRUCT)	\
-+VARIANT (uint32, , 2, _u32, 1, STRUCT)	\
-+VARIANT (uint64, , 1, _u64, 0, STRUCT)	\
-+VARIANT (int8, , 8, _s8, 5, STRUCT)	\
-+VARIANT (int16, , 4, _s16, 2, STRUCT)	\
-+VARIANT (int32, , 2, _s32, 0, STRUCT)	\
-+VARIANT (int64, , 1, _s64, 0, STRUCT)	\
-+VARIANT (poly8, , 8, _p8, 7, STRUCT)	\
-+VARIANT (poly16, , 4, _p16, 1, STRUCT)	\
-+VARIANT (float32, , 2, _f32, 1, STRUCT)	\
-+VARIANT (float64, , 1, _f64, 0, STRUCT)	\
-+VARIANT (uint8, q, 16, _u8, 14, STRUCT)	\
-+VARIANT (uint16, q, 8, _u16, 4, STRUCT)	\
-+VARIANT (uint32, q, 4, _u32, 3, STRUCT)	\
-+VARIANT (uint64, q, 2, _u64, 0, STRUCT)	\
-+VARIANT (int8, q, 16, _s8, 13, STRUCT)	\
-+VARIANT (int16, q, 8, _s16, 6, STRUCT)	\
-+VARIANT (int32, q, 4, _s32, 2, STRUCT)	\
-+VARIANT (int64, q, 2, _s64, 1, STRUCT)	\
-+VARIANT (poly8, q, 16, _p8, 12, STRUCT)	\
-+VARIANT (poly16, q, 8, _p16, 5, STRUCT)	\
-+VARIANT (float32, q, 4, _f32, 1, STRUCT)\
-+VARIANT (float64, q, 2, _f64, 0, STRUCT)
-+
-+#define TESTMETH(BASE, Q, ELTS, SUFFIX, LANE, STRUCT)			\
-+int									\
-+test_vld##STRUCT##Q##_lane##SUFFIX (const BASE##_t *data,		\
-+				     const BASE##_t *overwrite)		\
-+{									\
-+  BASE##x##ELTS##x##STRUCT##_t vectors;					\
-+  BASE##_t temp[ELTS];							\
-+  int i,j;								\
-+  for (i = 0; i < STRUCT; i++, data += ELTS)				\
-+    vectors.val[i] = vld1##Q##SUFFIX (data);				\
-+  vectors = vld##STRUCT##Q##_lane##SUFFIX (overwrite, vectors, LANE);	\
-+  while (--i >= 0)							\
-+    {									\
-+      vst1##Q##SUFFIX (temp, vectors.val[i]);				\
-+      data -= ELTS; /* Point at value loaded before vldN_lane.  */	\
-+      for (j = 0; j < ELTS; j++)					\
-+        if (temp[j] != (j == LANE ? overwrite[i] : data[j]))		\
-+          return 1;							\
-+    }									\
-+  return 0;								\
-+}
-+
-+
-+/* Tests of vld2_dup and vld2q_dup.  */
-+VARIANTS (TESTMETH, 2)
-+/* Tests of vld3_dup and vld3q_dup.  */
-+VARIANTS (TESTMETH, 3)
-+/* Tests of vld4_dup and vld4q_dup.  */
-+VARIANTS (TESTMETH, 4)
-+
-+#define CHECK(BASE, Q, ELTS, SUFFIX, LANE, STRUCT)			\
-+  if (test_vld##STRUCT##Q##_lane##SUFFIX ((const BASE##_t *)orig_data,	\
-+						BASE##_data) != 0)	\
-+    abort ();
-+
-+int
-+main (int argc, char **argv)
-+{
-+  /* Original data for all vector formats.  */
-+  uint64_t orig_data[8] = {0x1234567890abcdefULL, 0x13579bdf02468aceULL,
-+			   0x012389ab4567cdefULL, 0xfeeddadacafe0431ULL,
-+			   0x1032547698badcfeULL, 0xbadbadbadbad0badULL,
-+			   0x0102030405060708ULL, 0x0f0e0d0c0b0a0908ULL};
-+
-+  /* Data with which vldN_lane will overwrite some of previous.  */
-+  uint8_t uint8_data[4] = { 7, 11, 13, 17 };
-+  uint16_t uint16_data[4] = { 257, 263, 269, 271 };
-+  uint32_t uint32_data[4] = { 65537, 65539, 65543, 65551 };
-+  uint64_t uint64_data[4] = { 0xdeadbeefcafebabeULL, 0x0123456789abcdefULL,
-+			      0xfedcba9876543210LL, 0xdeadbabecafebeefLL };
-+  int8_t int8_data[4] = { -1, 3, -5, 7 };
-+  int16_t int16_data[4] = { 257, -259, 261, -263 };
-+  int32_t int32_data[4] = { 123456789, -987654321, -135792468, 975318642 };
-+  int64_t *int64_data = (int64_t *)uint64_data;
-+  poly8_t poly8_data[4] = { 0, 7, 13, 18, };
-+  poly16_t poly16_data[4] = { 11111, 2222, 333, 44 };
-+  float32_t float32_data[4] = { 3.14159, 2.718, 1.414, 100.0 };
-+  float64_t float64_data[4] = { 1.010010001, 12345.6789, -9876.54321, 1.618 };
-+
-+  VARIANTS (CHECK, 2);
-+  VARIANTS (CHECK, 3);
-+  VARIANTS (CHECK, 4);
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/vldN_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/vldN_1.c
-@@ -0,0 +1,79 @@
-+/* { dg-do run } */
-+/* { dg-options "-O3" } */
-+
-+#include <arm_neon.h>
-+
-+extern void abort (void);
-+
-+#define TESTMETH(BASE, ELTS, STRUCT, SUFFIX)	\
-+int __attribute__ ((noinline))			\
-+test_vld##STRUCT##SUFFIX ()			\
-+{						\
-+  BASE##_t data[ELTS * STRUCT];			\
-+  BASE##_t temp[ELTS];				\
-+  BASE##x##ELTS##x##STRUCT##_t vectors;		\
-+  int i,j;					\
-+  for (i = 0; i < STRUCT * ELTS; i++)		\
-+    data [i] = (BASE##_t) 2*i + 1;		\
-+  asm volatile ("" : : : "memory");		\
-+  vectors = vld##STRUCT##SUFFIX (data);		\
-+  for (i = 0; i < STRUCT; i++)			\
-+    {						\
-+      vst1##SUFFIX (temp, vectors.val[i]);	\
-+      asm volatile ("" : : : "memory");		\
-+      for (j = 0; j < ELTS; j++)		\
-+        if (temp[j] != data[i + STRUCT*j])	\
-+          return 1;				\
-+    }						\
-+  return 0;					\
-+}
-+
-+#define VARIANTS(VARIANT, STRUCT)	\
-+VARIANT (uint8, 8, STRUCT, _u8)		\
-+VARIANT (uint16, 4, STRUCT, _u16)	\
-+VARIANT (uint32, 2, STRUCT, _u32)	\
-+VARIANT (uint64, 1, STRUCT, _u64)	\
-+VARIANT (int8, 8, STRUCT, _s8)		\
-+VARIANT (int16, 4, STRUCT, _s16)	\
-+VARIANT (int32, 2, STRUCT, _s32)	\
-+VARIANT (int64, 1, STRUCT, _s64)	\
-+VARIANT (poly8, 8, STRUCT, _p8)		\
-+VARIANT (poly16, 4, STRUCT, _p16)	\
-+VARIANT (float32, 2, STRUCT, _f32)	\
-+VARIANT (float64, 1, STRUCT, _f64)	\
-+VARIANT (uint8, 16, STRUCT, q_u8)	\
-+VARIANT (uint16, 8, STRUCT, q_u16)	\
-+VARIANT (uint32, 4, STRUCT, q_u32)	\
-+VARIANT (uint64, 2, STRUCT, q_u64)	\
-+VARIANT (int8, 16, STRUCT, q_s8)	\
-+VARIANT (int16, 8, STRUCT, q_s16)	\
-+VARIANT (int32, 4, STRUCT, q_s32)	\
-+VARIANT (int64, 2, STRUCT, q_s64)	\
-+VARIANT (poly8, 16, STRUCT, q_p8)	\
-+VARIANT (poly16, 8, STRUCT, q_p16)	\
-+VARIANT (float32, 4, STRUCT, q_f32)	\
-+VARIANT (float64, 2, STRUCT, q_f64)
-+
-+/* Tests of vld2 and vld2q.  */
-+VARIANTS (TESTMETH, 2)
-+
-+/* Tests of vld3 and vld3q.  */
-+VARIANTS (TESTMETH, 3)
-+
-+/* Tests of vld4 and vld4q.  */
-+VARIANTS (TESTMETH, 4)
-+
-+#define CHECK(BASE, ELTS, STRUCT, SUFFIX)	\
-+  if (test_vld##STRUCT##SUFFIX () != 0)		\
-+    abort ();
-+
-+int
-+main (int argc, char **argv)
-+{
-+  VARIANTS (CHECK, 2)
-+  VARIANTS (CHECK, 3)
-+  VARIANTS (CHECK, 4)
-+
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/vqabs_s64_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/vqabs_s64_1.c
-@@ -0,0 +1,54 @@
-+/* Test vqabs_s64 intrinsics work correctly.  */
-+/* { dg-do run } */
-+/* { dg-options "--save-temps" } */
-+
-+#include <arm_neon.h>
-+
-+extern void abort (void);
-+
-+int __attribute__ ((noinline))
-+test_vqabs_s64 (int64x1_t passed, int64_t expected)
-+{
-+  return vget_lane_s64 (vqabs_s64 (passed), 0) != expected;
-+}
-+
-+int __attribute__ ((noinline))
-+test_vqabsd_s64 (int64_t passed, int64_t expected)
-+{
-+  return vqabsd_s64 (passed) != expected;
-+}
-+
-+/* { dg-final { scan-assembler-times "sqabs\\td\[0-9\]+, d\[0-9\]+" 2 } } */
-+
-+int
-+main (int argc, char **argv)
-+{
-+  /* Basic test.  */
-+  if (test_vqabs_s64 (vcreate_s64 (-1), 1))
-+    abort ();
-+  if (test_vqabsd_s64 (-1, 1))
-+    abort ();
-+
-+  /* Getting absolute value of min int64_t.
-+     Note, exact result cannot be represented in int64_t,
-+     so max int64_t is expected.  */
-+  if (test_vqabs_s64 (vcreate_s64 (0x8000000000000000), 0x7fffffffffffffff))
-+    abort ();
-+  if (test_vqabsd_s64 (0x8000000000000000, 0x7fffffffffffffff))
-+    abort ();
-+
-+  /* Another input that gets max int64_t.  */
-+  if (test_vqabs_s64 (vcreate_s64 (0x8000000000000001), 0x7fffffffffffffff))
-+    abort ();
-+  if (test_vqabsd_s64 (0x8000000000000001, 0x7fffffffffffffff))
-+    abort ();
-+
-+  /* Checking that large positive numbers stay the same.  */
-+  if (test_vqabs_s64 (vcreate_s64 (0x7fffffffffffffff), 0x7fffffffffffffff))
-+    abort ();
-+  if (test_vqabsd_s64 (0x7fffffffffffffff, 0x7fffffffffffffff))
-+    abort ();
-+
-+  return 0;
-+}
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/acle/acle.exp
-+++ b/src/gcc/testsuite/gcc.target/aarch64/acle/acle.exp
-@@ -0,0 +1,35 @@
-+# Copyright (C) 2014 Free Software Foundation, Inc.
-+
-+# This program is free software; you can redistribute it and/or modify
-+# it under the terms of the GNU General Public License as published by
-+# the Free Software Foundation; either version 3 of the License, or
-+# (at your option) any later version.
-+#
-+# This program is distributed in the hope that it will be useful,
-+# but WITHOUT ANY WARRANTY; without even the implied warranty of
-+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+# GNU General Public License for more details.
-+#
-+# You should have received a copy of the GNU General Public License
-+# along with GCC; see the file COPYING3.  If not see
-+# <http://www.gnu.org/licenses/>.
-+
-+# GCC testsuite that uses the `dg.exp' driver.
-+
-+# Exit immediately if this isn't an AArch64 target.
-+if ![istarget aarch64*-*-*] then {
-+  return
-+}
-+
-+# Load support procs.
-+load_lib gcc-dg.exp
-+
-+# Initialize `dg'.
-+dg-init
-+
-+# Main loop.
-+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
-+	"" ""
-+
-+# All done.
-+dg-finish
---- a/src/gcc/testsuite/gcc.target/aarch64/acle/crc32b.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/acle/crc32b.c
-@@ -0,0 +1,15 @@
-+/* Test the crc32b ACLE intrinsic.  */
-+
-+/* { dg-do assemble } */
-+/* { dg-options "-save-temps -O2 -march=armv8-a+crc" } */
-+
-+#include "arm_acle.h"
-+
-+uint32_t
-+test_crc32b (uint32_t arg0, uint8_t arg1)
-+{
-+  return __crc32b (arg0, arg1);
-+}
-+
-+/* { dg-final { scan-assembler "crc32b\tw..?, w..?, w..?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/acle/crc32d.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/acle/crc32d.c
-@@ -0,0 +1,15 @@
-+/* Test the crc32d ACLE intrinsic.  */
-+
-+/* { dg-do assemble } */
-+/* { dg-options "-save-temps -O2 -march=armv8-a+crc" } */
-+
-+#include "arm_acle.h"
-+
-+uint32_t
-+test_crc32d (uint32_t arg0, uint64_t arg1)
-+{
-+  return __crc32d (arg0, arg1);
-+}
-+
-+/* { dg-final { scan-assembler "crc32x\tw..?, w..?, x..?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/acle/crc32cb.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/acle/crc32cb.c
-@@ -0,0 +1,15 @@
-+/* Test the crc32cb ACLE intrinsic.  */
-+
-+/* { dg-do assemble } */
-+/* { dg-options "-save-temps -O2 -march=armv8-a+crc" } */
-+
-+#include "arm_acle.h"
-+
-+uint32_t
-+test_crc32cb (uint32_t arg0, uint8_t arg1)
-+{
-+  return __crc32cb (arg0, arg1);
-+}
-+
-+/* { dg-final { scan-assembler "crc32cb\tw..?, w..?, w..?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/acle/crc32cd.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/acle/crc32cd.c
-@@ -0,0 +1,15 @@
-+/* Test the crc32cd ACLE intrinsic.  */
-+
-+/* { dg-do assemble } */
-+/* { dg-options "-save-temps -O2 -march=armv8-a+crc" } */
-+
-+#include "arm_acle.h"
-+
-+uint32_t
-+test_crc32cd (uint32_t arg0, uint64_t arg1)
-+{
-+  return __crc32cd (arg0, arg1);
-+}
-+
-+/* { dg-final { scan-assembler "crc32cx\tw..?, w..?, x..?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/acle/crc32w.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/acle/crc32w.c
-@@ -0,0 +1,15 @@
-+/* Test the crc32w ACLE intrinsic.  */
-+
-+/* { dg-do assemble } */
-+/* { dg-options "-save-temps -O2 -march=armv8-a+crc" } */
-+
-+#include "arm_acle.h"
-+
-+uint32_t
-+test_crc32w (uint32_t arg0, uint32_t arg1)
-+{
-+  return __crc32w (arg0, arg1);
-+}
-+
-+/* { dg-final { scan-assembler "crc32w\tw..?, w..?, w..?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/acle/crc32h.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/acle/crc32h.c
-@@ -0,0 +1,15 @@
-+/* Test the crc32h ACLE intrinsic.  */
-+
-+/* { dg-do assemble } */
-+/* { dg-options "-save-temps -O2 -march=armv8-a+crc" } */
-+
-+#include "arm_acle.h"
-+
-+uint32_t
-+test_crc32h (uint32_t arg0, uint16_t arg1)
-+{
-+  return __crc32h (arg0, arg1);
-+}
-+
-+/* { dg-final { scan-assembler "crc32h\tw..?, w..?, w..?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/acle/crc32cw.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/acle/crc32cw.c
-@@ -0,0 +1,15 @@
-+/* Test the crc32cw ACLE intrinsic.  */
-+
-+/* { dg-do assemble } */
-+/* { dg-options "-save-temps -O2 -march=armv8-a+crc" } */
-+
-+#include "arm_acle.h"
-+
-+uint32_t
-+test_crc32cw (uint32_t arg0, uint32_t arg1)
-+{
-+  return __crc32cw (arg0, arg1);
-+}
-+
-+/* { dg-final { scan-assembler "crc32cw\tw..?, w..?, w..?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/acle/crc32ch.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/acle/crc32ch.c
-@@ -0,0 +1,15 @@
-+/* Test the crc32ch ACLE intrinsic.  */
-+
-+/* { dg-do assemble } */
-+/* { dg-options "-save-temps -O2 -march=armv8-a+crc" } */
-+
-+#include "arm_acle.h"
-+
-+uint32_t
-+test_crc32ch (uint32_t arg0, uint16_t arg1)
-+{
-+  return __crc32ch (arg0, arg1);
-+}
-+
-+/* { dg-final { scan-assembler "crc32ch\tw..?, w..?, w..?\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/test_frame_13.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_13.c
-@@ -0,0 +1,18 @@
-+/* Verify:
-+     * without outgoing.
-+     * total frame size > 512.
-+     * number of callee-save reg >= 2.
-+     * split the stack adjustment into two substractions,
-+       the second could be optimized into "stp !".  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-O2 --save-temps" } */
-+
-+#include "test_frame_common.h"
-+
-+t_frame_pattern (test13, 700, )
-+t_frame_run (test13)
-+
-+/* { dg-final { scan-assembler-times "sub\tsp, sp, #\[0-9\]+" 1 } } */
-+/* { dg-final { scan-assembler-times "stp\tx29, x30, \\\[sp, -\[0-9\]+\\\]!" 2 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/test_frame_2.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_2.c
-@@ -0,0 +1,20 @@
-+/* Verify:
-+     * -fomit-frame-pointer.
-+     * without outgoing.
-+     * total frame size <= 256.
-+     * number of callee-save regs >= 2.
-+     * optimized code should use "stp !" for stack adjustment.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-O2 -fomit-frame-pointer --save-temps" } */
-+
-+#include "test_frame_common.h"
-+
-+t_frame_pattern (test2, 200, "x19")
-+t_frame_run (test2)
-+
-+
-+/* { dg-final { scan-assembler-times "stp\tx19, x30, \\\[sp, -\[0-9\]+\\\]!" 1 } } */
-+/* { dg-final { scan-assembler-times "ldp\tx19, x30, \\\[sp\\\], \[0-9\]+" 2 } } */
-+
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/legitimize_stack_var_before_reload_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/legitimize_stack_var_before_reload_1.c
-@@ -0,0 +1,21 @@
-+/* { dg-do compile } */
-+/* { dg-options "-O2 -fdump-rtl-expand" } */
-+
-+extern void initialize_array (unsigned char *, int);
-+
-+int
-+test15 (void)
-+{
-+  unsigned char a[480];
-+
-+  initialize_array (a, 480);
-+
-+  if (a[0] == 0x10)
-+    return 1;
-+
-+  return 0;
-+}
-+
-+/* { dg-final { scan-rtl-dump "\\(mem\[^\\n\]*\\(plus\[^\\n\]*virtual-stack-vars" "expand" } } */
-+
-+/* { dg-final { cleanup-rtl-dump "expand" } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/vreinterpret_f64_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/vreinterpret_f64_1.c
-@@ -0,0 +1,596 @@
-+/* Test vreinterpret_f64_* and vreinterpret_*_f64 intrinsics work correctly.  */
-+/* { dg-do run } */
-+/* { dg-options "-O3" } */
-+
-+#include <arm_neon.h>
-+
-+extern void abort (void);
-+
-+#define ABS(a) __builtin_fabs (a)
-+#define ISNAN(a) __builtin_isnan (a)
-+
-+#define DOUBLE_EQUALS(a, b, epsilon)		\
-+(						\
-+ ((a) == (b))					\
-+  || (ISNAN (a) && ISNAN (b))			\
-+  || (ABS (a - b) < epsilon)			\
-+)
-+
-+/* Pi accurate up to 16 digits.
-+   Further digits are a closest binary approximation.  */
-+#define PI_F64 3.14159265358979311599796346854
-+/* Hex representation in Double (IEEE754 Double precision 64-bit) is:
-+   0x400921FB54442D18.  */
-+
-+/* E accurate up to 16 digits.
-+   Further digits are a closest binary approximation.  */
-+#define E_F64 2.71828182845904509079559829843
-+/* Hex representation in Double (IEEE754 Double precision 64-bit) is:
-+   0x4005BF0A8B145769.  */
-+
-+float32x2_t __attribute__ ((noinline))
-+wrap_vreinterpret_f32_f64 (float64x1_t __a)
-+{
-+  return vreinterpret_f32_f64 (__a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vreinterpret_f32_f64 ()
-+{
-+  float64x1_t a;
-+  float32x2_t b;
-+  float64_t c[1] = { PI_F64 };
-+  /* Values { 0x54442D18, 0x400921FB } reinterpreted as f32.  */
-+  float32_t d[2] = { 3.3702805504E12, 2.1426990032196044921875E0 };
-+  float32_t e[2];
-+  int i;
-+
-+  a = vld1_f64 (c);
-+  b = wrap_vreinterpret_f32_f64 (a);
-+  vst1_f32 (e, b);
-+  for (i = 0; i < 2; i++)
-+    if (!DOUBLE_EQUALS (d[i], e[i], __FLT_EPSILON__))
-+      return 1;
-+  return 0;
-+};
-+
-+int8x8_t __attribute__ ((noinline))
-+wrap_vreinterpret_s8_f64 (float64x1_t __a)
-+{
-+  return vreinterpret_s8_f64 (__a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vreinterpret_s8_f64 ()
-+{
-+  float64x1_t a;
-+  int8x8_t b;
-+  float64_t c[1] = { PI_F64 };
-+  int8_t d[8] = { 0x18, 0x2D, 0x44, 0x54, 0xFB, 0x21, 0x09, 0x40 };
-+  int8_t e[8];
-+  int i;
-+
-+  a = vld1_f64 (c);
-+  b = wrap_vreinterpret_s8_f64 (a);
-+  vst1_s8 (e, b);
-+  for (i = 0; i < 8; i++)
-+    if (d[i] != e[i])
-+      return 1;
-+  return 0;
-+};
-+
-+int16x4_t __attribute__ ((noinline))
-+wrap_vreinterpret_s16_f64 (float64x1_t __a)
-+{
-+  return vreinterpret_s16_f64 (__a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vreinterpret_s16_f64 ()
-+{
-+  float64x1_t a;
-+  int16x4_t b;
-+  float64_t c[1] = { PI_F64 };
-+  int16_t d[4] = { 0x2D18, 0x5444, 0x21FB, 0x4009 };
-+  int16_t e[4];
-+  int i;
-+
-+  a = vld1_f64 (c);
-+  b = wrap_vreinterpret_s16_f64 (a);
-+  vst1_s16 (e, b);
-+  for (i = 0; i < 4; i++)
-+    if (d[i] != e[i])
-+      return 1;
-+  return 0;
-+};
-+
-+int32x2_t __attribute__ ((noinline))
-+wrap_vreinterpret_s32_f64 (float64x1_t __a)
-+{
-+  return vreinterpret_s32_f64 (__a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vreinterpret_s32_f64 ()
-+{
-+  float64x1_t a;
-+  int32x2_t b;
-+  float64_t c[1] = { PI_F64 };
-+  int32_t d[2] = { 0x54442D18, 0x400921FB };
-+  int32_t e[2];
-+  int i;
-+
-+  a = vld1_f64 (c);
-+  b = wrap_vreinterpret_s32_f64 (a);
-+  vst1_s32 (e, b);
-+  for (i = 0; i < 2; i++)
-+    if (d[i] != e[i])
-+      return 1;
-+  return 0;
-+};
-+
-+int64x1_t __attribute__ ((noinline))
-+wrap_vreinterpret_s64_f64 (float64x1_t __a)
-+{
-+  return vreinterpret_s64_f64 (__a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vreinterpret_s64_f64 ()
-+{
-+  float64x1_t a;
-+  int64x1_t b;
-+  float64_t c[1] = { PI_F64 };
-+  int64_t d[1] = { 0x400921FB54442D18 };
-+  int64_t e[1];
-+  int i;
-+
-+  a = vld1_f64 (c);
-+  b = wrap_vreinterpret_s64_f64 (a);
-+  vst1_s64 (e, b);
-+  if (d[0] != e[0])
-+    return 1;
-+  return 0;
-+};
-+
-+float32x4_t __attribute__ ((noinline))
-+wrap_vreinterpretq_f32_f64 (float64x2_t __a)
-+{
-+  return vreinterpretq_f32_f64 (__a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vreinterpretq_f32_f64 ()
-+{
-+  float64x2_t a;
-+  float32x4_t b;
-+  float64_t c[2] = { PI_F64, E_F64 };
-+
-+  /* Values corresponding to f32 reinterpret of
-+     { 0x54442D18, 0x400921FB, 0x8B145769, 0x4005BF0A }.  */
-+  float32_t d[4] = { 3.3702805504E12,
-+		     2.1426990032196044921875E0,
-+		     -2.8569523269651966444143014594E-32,
-+		     2.089785099029541015625E0 };
-+  float32_t e[4];
-+  int i;
-+
-+  a = vld1q_f64 (c);
-+  b = wrap_vreinterpretq_f32_f64 (a);
-+  vst1q_f32 (e, b);
-+  for (i = 0; i < 4; i++)
-+    {
-+      if (!DOUBLE_EQUALS (d[i], e[i], __FLT_EPSILON__))
-+	return 1;
-+    }
-+  return 0;
-+};
-+
-+int8x16_t __attribute__ ((noinline))
-+wrap_vreinterpretq_s8_f64 (float64x2_t __a)
-+{
-+  return vreinterpretq_s8_f64 (__a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vreinterpretq_s8_f64 ()
-+{
-+  float64x2_t a;
-+  int8x16_t b;
-+  float64_t c[2] = { PI_F64, E_F64 };
-+  int8_t d[16] = { 0x18, 0x2D, 0x44, 0x54, 0xFB, 0x21, 0x09, 0x40,
-+		   0x69, 0x57, 0x14, 0x8B, 0x0A, 0xBF, 0x05, 0x40 };
-+  int8_t e[16];
-+  int i;
-+
-+  a = vld1q_f64 (c);
-+  b = wrap_vreinterpretq_s8_f64 (a);
-+  vst1q_s8 (e, b);
-+  for (i = 0; i < 16; i++)
-+    if (d[i] != e[i])
-+      return 1;
-+  return 0;
-+};
-+
-+int16x8_t __attribute__ ((noinline))
-+wrap_vreinterpretq_s16_f64 (float64x2_t __a)
-+{
-+  return vreinterpretq_s16_f64 (__a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vreinterpretq_s16_f64 ()
-+{
-+  float64x2_t a;
-+  int16x8_t b;
-+  float64_t c[2] = { PI_F64, E_F64 };
-+  int16_t d[8] = { 0x2D18, 0x5444, 0x21FB, 0x4009,
-+		   0x5769, 0x8B14, 0xBF0A, 0x4005 };
-+  int16_t e[8];
-+  int i;
-+
-+  a = vld1q_f64 (c);
-+  b = wrap_vreinterpretq_s16_f64 (a);
-+  vst1q_s16 (e, b);
-+  for (i = 0; i < 8; i++)
-+    if (d[i] != e[i])
-+      return 1;
-+  return 0;
-+};
-+
-+int32x4_t __attribute__ ((noinline))
-+wrap_vreinterpretq_s32_f64 (float64x2_t __a)
-+{
-+  return vreinterpretq_s32_f64 (__a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vreinterpretq_s32_f64 ()
-+{
-+  float64x2_t a;
-+  int32x4_t b;
-+  float64_t c[2] = { PI_F64, E_F64 };
-+  int32_t d[4] = { 0x54442D18, 0x400921FB, 0x8B145769, 0x4005BF0A };
-+  int32_t e[4];
-+  int i;
-+
-+  a = vld1q_f64 (c);
-+  b = wrap_vreinterpretq_s32_f64 (a);
-+  vst1q_s32 (e, b);
-+  for (i = 0; i < 4; i++)
-+    if (d[i] != e[i])
-+      return 1;
-+  return 0;
-+};
-+
-+int64x2_t __attribute__ ((noinline))
-+wrap_vreinterpretq_s64_f64 (float64x2_t __a)
-+{
-+  return vreinterpretq_s64_f64 (__a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vreinterpretq_s64_f64 ()
-+{
-+  float64x2_t a;
-+  int64x2_t b;
-+  float64_t c[2] = { PI_F64, E_F64 };
-+  int64_t d[2] = { 0x400921FB54442D18, 0x4005BF0A8B145769 };
-+  int64_t e[2];
-+  int i;
-+
-+  a = vld1q_f64 (c);
-+  b = wrap_vreinterpretq_s64_f64 (a);
-+  vst1q_s64 (e, b);
-+  for (i = 0; i < 2; i++)
-+    if (d[i] != e[i])
-+      return 1;
-+  return 0;
-+};
-+
-+float64x1_t __attribute__ ((noinline))
-+wrap_vreinterpret_f64_f32 (float32x2_t __a)
-+{
-+  return vreinterpret_f64_f32 (__a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vreinterpret_f64_f32 ()
-+{
-+  float32x2_t a;
-+  float64x1_t b;
-+  /* Values { 0x54442D18, 0x400921FB } reinterpreted as f32.  */
-+  float32_t c[2] = { 3.3702805504E12, 2.1426990032196044921875E0 };
-+  float64_t d[1] = { PI_F64 };
-+  float64_t e[1];
-+  int i;
-+
-+  a = vld1_f32 (c);
-+  b = wrap_vreinterpret_f64_f32 (a);
-+  vst1_f64 (e, b);
-+  if (!DOUBLE_EQUALS (d[0], e[0], __DBL_EPSILON__))
-+    return 1;
-+  return 0;
-+};
-+
-+float64x1_t __attribute__ ((noinline))
-+wrap_vreinterpret_f64_s8 (int8x8_t __a)
-+{
-+  return vreinterpret_f64_s8 (__a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vreinterpret_f64_s8 ()
-+{
-+  int8x8_t a;
-+  float64x1_t b;
-+  int8_t c[8] = { 0x18, 0x2D, 0x44, 0x54, 0xFB, 0x21, 0x09, 0x40 };
-+  float64_t d[1] = { PI_F64 };
-+  float64_t e[1];
-+  int i;
-+
-+  a = vld1_s8 (c);
-+  b = wrap_vreinterpret_f64_s8 (a);
-+  vst1_f64 (e, b);
-+  if (!DOUBLE_EQUALS (d[0], e[0], __DBL_EPSILON__))
-+    return 1;
-+  return 0;
-+};
-+
-+float64x1_t __attribute__ ((noinline))
-+wrap_vreinterpret_f64_s16 (int16x4_t __a)
-+{
-+  return vreinterpret_f64_s16 (__a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vreinterpret_f64_s16 ()
-+{
-+  int16x4_t a;
-+  float64x1_t b;
-+  int16_t c[4] = { 0x2D18, 0x5444, 0x21FB, 0x4009 };
-+  float64_t d[1] = { PI_F64 };
-+  float64_t e[1];
-+  int i;
-+
-+  a = vld1_s16 (c);
-+  b = wrap_vreinterpret_f64_s16 (a);
-+  vst1_f64 (e, b);
-+  if (!DOUBLE_EQUALS (d[0], e[0], __DBL_EPSILON__))
-+    return 1;
-+  return 0;
-+};
-+
-+float64x1_t __attribute__ ((noinline))
-+wrap_vreinterpret_f64_s32 (int32x2_t __a)
-+{
-+  return vreinterpret_f64_s32 (__a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vreinterpret_f64_s32 ()
-+{
-+  int32x2_t a;
-+  float64x1_t b;
-+  int32_t c[2] = { 0x54442D18, 0x400921FB };
-+  float64_t d[1] = { PI_F64 };
-+  float64_t e[1];
-+  int i;
-+
-+  a = vld1_s32 (c);
-+  b = wrap_vreinterpret_f64_s32 (a);
-+  vst1_f64 (e, b);
-+  if (!DOUBLE_EQUALS (d[0], e[0], __DBL_EPSILON__))
-+    return 1;
-+  return 0;
-+};
-+
-+float64x1_t __attribute__ ((noinline))
-+wrap_vreinterpret_f64_s64 (int64x1_t __a)
-+{
-+  return vreinterpret_f64_s64 (__a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vreinterpret_f64_s64 ()
-+{
-+  int64x1_t a;
-+  float64x1_t b;
-+  int64_t c[1] = { 0x400921FB54442D18 };
-+  float64_t d[1] = { PI_F64 };
-+  float64_t e[1];
-+
-+  a = vld1_s64 (c);
-+  b = wrap_vreinterpret_f64_s64 (a);
-+  vst1_f64 (e, b);
-+  if (!DOUBLE_EQUALS (d[0], e[0], __DBL_EPSILON__))
-+    return 1;
-+  return 0;
-+};
-+
-+float64x2_t __attribute__ ((noinline))
-+wrap_vreinterpretq_f64_f32 (float32x4_t __a)
-+{
-+  return vreinterpretq_f64_f32 (__a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vreinterpretq_f64_f32 ()
-+{
-+  float32x4_t a;
-+  float64x2_t b;
-+  /* Values corresponding to f32 reinterpret of
-+     { 0x54442D18, 0x400921FB, 0x8B145769, 0x4005BF0A }.  */
-+  float32_t c[4] = { 3.3702805504E12,
-+		     2.1426990032196044921875E0,
-+		     -2.8569523269651966444143014594E-32,
-+		     2.089785099029541015625E0 };
-+
-+  float64_t d[2] = { PI_F64, E_F64 };
-+  float64_t e[2];
-+  int i;
-+
-+  a = vld1q_f32 (c);
-+  b = wrap_vreinterpretq_f64_f32 (a);
-+  vst1q_f64 (e, b);
-+  for (i = 0; i < 2; i++)
-+    if (!DOUBLE_EQUALS (d[i], e[i], __DBL_EPSILON__))
-+      return 1;
-+  return 0;
-+};
-+
-+float64x2_t __attribute__ ((noinline))
-+wrap_vreinterpretq_f64_s8 (int8x16_t __a)
-+{
-+  return vreinterpretq_f64_s8 (__a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vreinterpretq_f64_s8 ()
-+{
-+  int8x16_t a;
-+  float64x2_t b;
-+  int8_t c[16] = { 0x18, 0x2D, 0x44, 0x54, 0xFB, 0x21, 0x09, 0x40,
-+		   0x69, 0x57, 0x14, 0x8B, 0x0A, 0xBF, 0x05, 0x40 };
-+  float64_t d[2] = { PI_F64, E_F64 };
-+  float64_t e[2];
-+  int i;
-+
-+  a = vld1q_s8 (c);
-+  b = wrap_vreinterpretq_f64_s8 (a);
-+  vst1q_f64 (e, b);
-+  for (i = 0; i < 2; i++)
-+    if (!DOUBLE_EQUALS (d[i], e[i], __DBL_EPSILON__))
-+      return 1;
-+  return 0;
-+};
-+
-+float64x2_t __attribute__ ((noinline))
-+wrap_vreinterpretq_f64_s16 (int16x8_t __a)
-+{
-+  return vreinterpretq_f64_s16 (__a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vreinterpretq_f64_s16 ()
-+{
-+  int16x8_t a;
-+  float64x2_t b;
-+  int16_t c[8] = { 0x2D18, 0x5444, 0x21FB, 0x4009,
-+		   0x5769, 0x8B14, 0xBF0A, 0x4005 };
-+  float64_t d[2] = { PI_F64, E_F64 };
-+  float64_t e[2];
-+  int i;
-+
-+  a = vld1q_s16 (c);
-+  b = wrap_vreinterpretq_f64_s16 (a);
-+  vst1q_f64 (e, b);
-+  for (i = 0; i < 2; i++)
-+    if (!DOUBLE_EQUALS (d[i], e[i], __DBL_EPSILON__))
-+      return 1;
-+  return 0;
-+};
-+
-+float64x2_t __attribute__ ((noinline))
-+wrap_vreinterpretq_f64_s32 (int32x4_t __a)
-+{
-+  return vreinterpretq_f64_s32 (__a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vreinterpretq_f64_s32 ()
-+{
-+  int32x4_t a;
-+  float64x2_t b;
-+  int32_t c[4] = { 0x54442D18, 0x400921FB, 0x8B145769, 0x4005BF0A };
-+  float64_t d[2] = { PI_F64, E_F64 };
-+  float64_t e[2];
-+  int i;
-+
-+  a = vld1q_s32 (c);
-+  b = wrap_vreinterpretq_f64_s32 (a);
-+  vst1q_f64 (e, b);
-+  for (i = 0; i < 2; i++)
-+    if (!DOUBLE_EQUALS (d[i], e[i], __DBL_EPSILON__))
-+      return 1;
-+  return 0;
-+};
-+
-+float64x2_t __attribute__ ((noinline))
-+wrap_vreinterpretq_f64_s64 (int64x2_t __a)
-+{
-+  return vreinterpretq_f64_s64 (__a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vreinterpretq_f64_s64 ()
-+{
-+  int64x2_t a;
-+  float64x2_t b;
-+  int64_t c[2] = { 0x400921FB54442D18, 0x4005BF0A8B145769 };
-+  float64_t d[2] = { PI_F64, E_F64 };
-+  float64_t e[2];
-+  int i;
-+
-+  a = vld1q_s64 (c);
-+  b = wrap_vreinterpretq_f64_s64 (a);
-+  vst1q_f64 (e, b);
-+  for (i = 0; i < 2; i++)
-+    if (!DOUBLE_EQUALS (d[i], e[i], __DBL_EPSILON__))
-+      return 1;
-+  return 0;
-+};
-+
-+int
-+main (int argc, char **argv)
-+{
-+  if (test_vreinterpret_f32_f64 ())
-+    abort ();
-+
-+  if (test_vreinterpret_s8_f64 ())
-+    abort ();
-+  if (test_vreinterpret_s16_f64 ())
-+    abort ();
-+  if (test_vreinterpret_s32_f64 ())
-+    abort ();
-+  if (test_vreinterpret_s64_f64 ())
-+    abort ();
-+
-+  if (test_vreinterpretq_f32_f64 ())
-+    abort ();
-+
-+  if (test_vreinterpretq_s8_f64 ())
-+    abort ();
-+  if (test_vreinterpretq_s16_f64 ())
-+    abort ();
-+  if (test_vreinterpretq_s32_f64 ())
-+    abort ();
-+  if (test_vreinterpretq_s64_f64 ())
-+    abort ();
-+
-+  if (test_vreinterpret_f64_f32 ())
-+    abort ();
-+
-+  if (test_vreinterpret_f64_s8 ())
-+    abort ();
-+  if (test_vreinterpret_f64_s16 ())
-+    abort ();
-+  if (test_vreinterpret_f64_s32 ())
-+    abort ();
-+  if (test_vreinterpret_f64_s64 ())
-+    abort ();
-+
-+  if (test_vreinterpretq_f64_f32 ())
-+    abort ();
-+
-+  if (test_vreinterpretq_f64_s8 ())
-+    abort ();
-+  if (test_vreinterpretq_f64_s16 ())
-+    abort ();
-+  if (test_vreinterpretq_f64_s32 ())
-+    abort ();
-+  if (test_vreinterpretq_f64_s64 ())
-+    abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/test_fp_attribute_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/test_fp_attribute_1.c
-@@ -21,6 +21,6 @@
-   leaf ();
- }
- 
--/* { dg-final { scan-assembler-times "str\tx30, \\\[sp\\\]" 2 } } */
-+/* { dg-final { scan-assembler-times "str\tx30, \\\[sp, -\[0-9\]+\\\]!" 2 } } */
- 
- /* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/vect.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/vect.x
-@@ -2,6 +2,7 @@
- typedef unsigned int *__restrict__ pRUINT;
- typedef long long *__restrict__ pRINT64;
- typedef unsigned long long *__restrict__ pRUINT64;
-+extern int abs (int j);
- 
- void test_orn (pRUINT a, pRUINT b, pRUINT c)
- {
---- a/src/gcc/testsuite/gcc.target/aarch64/test_frame_14.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_14.c
-@@ -0,0 +1,12 @@
-+/* Verify:
-+     * with outgoing.
-+     * total frame size > 512.
-+     * number of callee-save reg >= 2.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-O2" } */
-+
-+#include "test_frame_common.h"
-+
-+t_frame_pattern_outgoing (test14, 700, , 8, a[8])
-+t_frame_run (test14)
---- a/src/gcc/testsuite/gcc.target/aarch64/test_frame_3.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_3.c
-@@ -0,0 +1,14 @@
-+/* Verify:
-+     * -fomit-frame-pointer.
-+     * without outgoing.
-+     * total frame size <= 512 but > 256.
-+     * number of callee-save reg == 1.
-+     * we can't use "str !" to optimize stack adjustment.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-O2 -fomit-frame-pointer" } */
-+
-+#include "test_frame_common.h"
-+
-+t_frame_pattern (test3, 400, )
-+t_frame_run (test3)
---- a/src/gcc/testsuite/gcc.target/aarch64/pic-constantpool1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/pic-constantpool1.c
-@@ -2,10 +2,13 @@
- /* { dg-do compile } */
- 
- extern int __finite (double __value) __attribute__ ((__nothrow__)) __attribute__ ((__const__));
-+extern int __finitef (float __value) __attribute__ ((__nothrow__)) __attribute__ ((__const__));
-+extern int __signbit (double __value) __attribute__ ((__nothrow__)) __attribute__ ((__const__));
-+extern int __signbitf (float __value) __attribute__ ((__nothrow__)) __attribute__ ((__const__));
- int
- __ecvt_r (value, ndigit, decpt, sign, buf, len)
-      double value;
--     int ndigit, *decpt, *sign;
-+     int ndigit, *decpt, *sign, len;
-      char *buf;
- {
-   if ((sizeof (value) == sizeof (float) ? __finitef (value) : __finite (value)) && value != 0.0)
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_s64.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_s64.c
-@@ -0,0 +1,27 @@
-+/* Test the vpaddd_s64 AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -O3" } */
-+
-+#include "arm_neon.h"
-+
-+#define SIZE 6
-+
-+extern void abort (void);
-+
-+int64_t in[SIZE] = { -4l, 4l, -2l, 2l, -1l, 1l };
-+
-+int
-+main (void)
-+{
-+  int i;
-+
-+  for (i = 0; i < SIZE / 2; ++i)
-+    if (vpaddd_s64 (vld1q_s64 (in + 2 * i)) != 0)
-+      abort ();
-+
-+  return 0;
-+}
-+
-+/* { dg-final { scan-assembler "addp\[ \t\]+\[dD\]\[0-9\]+, v\[0-9\].2d+\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/extq_s16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/extq_s16.x
-@@ -0,0 +1,114 @@
-+extern void abort (void);
-+
-+int16x8_t
-+test_vextq_s16_1 (int16x8_t a, int16x8_t b)
-+{
-+  return vextq_s16 (a, b, 1);
-+}
-+
-+int16x8_t
-+test_vextq_s16_2 (int16x8_t a, int16x8_t b)
-+{
-+  return vextq_s16 (a, b, 2);
-+}
-+
-+int16x8_t
-+test_vextq_s16_3 (int16x8_t a, int16x8_t b)
-+{
-+  return vextq_s16 (a, b, 3);
-+}
-+
-+int16x8_t
-+test_vextq_s16_4 (int16x8_t a, int16x8_t b)
-+{
-+  return vextq_s16 (a, b, 4);
-+}
-+
-+int16x8_t
-+test_vextq_s16_5 (int16x8_t a, int16x8_t b)
-+{
-+  return vextq_s16 (a, b, 5);
-+}
-+
-+int16x8_t
-+test_vextq_s16_6 (int16x8_t a, int16x8_t b)
-+{
-+  return vextq_s16 (a, b, 6);
-+}
-+
-+int16x8_t
-+test_vextq_s16_7 (int16x8_t a, int16x8_t b)
-+{
-+  return vextq_s16 (a, b, 7);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i, off;
-+  int16_t arr1[] = {0, 1, 2, 3, 4, 5, 6, 7};
-+  int16x8_t in1 = vld1q_s16 (arr1);
-+  int16_t arr2[] = {8, 9, 10, 11, 12, 13, 14, 15};
-+  int16x8_t in2 = vld1q_s16 (arr2);
-+  int16_t exp[8];
-+  int16x8_t expected;
-+  int16x8_t actual = test_vextq_s16_1 (in1, in2);
-+
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 1;
-+  expected = vld1q_s16 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_s16_2 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 2;
-+  expected = vld1q_s16 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_s16_3 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 3;
-+  expected = vld1q_s16 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_s16_4 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 4;
-+  expected = vld1q_s16 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_s16_5 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 5;
-+  expected = vld1q_s16 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_s16_6 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 6;
-+  expected = vld1q_s16 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_s16_7 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 7;
-+  expected = vld1q_s16 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_u64.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_u64.c
-@@ -0,0 +1,27 @@
-+/* Test the vpaddd_u64 AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -O3" } */
-+
-+#include "arm_neon.h"
-+
-+#define SIZE 6
-+
-+extern void abort (void);
-+
-+uint64_t in[SIZE] = { 4ul, 4ul, 2ul, 2ul, 1ul, 1ul };
-+
-+int
-+main (void)
-+{
-+  int i;
-+
-+  for (i = 0; i < SIZE / 2; ++i)
-+    if (vpaddd_u64 (vld1q_u64 (in + 2 * i)) != 2 * in[2 * i])
-+      abort ();
-+
-+  return 0;
-+}
-+
-+/* { dg-final { scan-assembler "addp\[ \t\]+\[dD\]\[0-9\]+, v\[0-9\].2d+\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/ext_u8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/ext_u8.x
-@@ -0,0 +1,114 @@
-+extern void abort (void);
-+
-+uint8x8_t
-+test_vext_u8_1 (uint8x8_t a, uint8x8_t b)
-+{
-+  return vext_u8 (a, b, 1);
-+}
-+
-+uint8x8_t
-+test_vext_u8_2 (uint8x8_t a, uint8x8_t b)
-+{
-+  return vext_u8 (a, b, 2);
-+}
-+
-+uint8x8_t
-+test_vext_u8_3 (uint8x8_t a, uint8x8_t b)
-+{
-+  return vext_u8 (a, b, 3);
-+}
-+
-+uint8x8_t
-+test_vext_u8_4 (uint8x8_t a, uint8x8_t b)
-+{
-+  return vext_u8 (a, b, 4);
-+}
-+
-+uint8x8_t
-+test_vext_u8_5 (uint8x8_t a, uint8x8_t b)
-+{
-+  return vext_u8 (a, b, 5);
-+}
-+
-+uint8x8_t
-+test_vext_u8_6 (uint8x8_t a, uint8x8_t b)
-+{
-+  return vext_u8 (a, b, 6);
-+}
-+
-+uint8x8_t
-+test_vext_u8_7 (uint8x8_t a, uint8x8_t b)
-+{
-+  return vext_u8 (a, b, 7);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i, off;
-+  uint8_t arr1[] = {0, 1, 2, 3, 4, 5, 6, 7};
-+  uint8x8_t in1 = vld1_u8 (arr1);
-+  uint8_t arr2[] = {8, 9, 10, 11, 12, 13, 14, 15};
-+  uint8x8_t in2 = vld1_u8 (arr2);
-+  uint8_t exp[8];
-+  uint8x8_t expected;
-+  uint8x8_t actual = test_vext_u8_1 (in1, in2);
-+
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 1;
-+  expected = vld1_u8 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vext_u8_2 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 2;
-+  expected = vld1_u8 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vext_u8_3 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 3;
-+  expected = vld1_u8 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vext_u8_4 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 4;
-+  expected = vld1_u8 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vext_u8_5 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 5;
-+  expected = vld1_u8 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vext_u8_6 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 6;
-+  expected = vld1_u8 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vext_u8_7 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 7;
-+  expected = vld1_u8 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/extq_u16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/extq_u16.x
-@@ -0,0 +1,114 @@
-+extern void abort (void);
-+
-+uint16x8_t
-+test_vextq_u16_1 (uint16x8_t a, uint16x8_t b)
-+{
-+  return vextq_u16 (a, b, 1);
-+}
-+
-+uint16x8_t
-+test_vextq_u16_2 (uint16x8_t a, uint16x8_t b)
-+{
-+  return vextq_u16 (a, b, 2);
-+}
-+
-+uint16x8_t
-+test_vextq_u16_3 (uint16x8_t a, uint16x8_t b)
-+{
-+  return vextq_u16 (a, b, 3);
-+}
-+
-+uint16x8_t
-+test_vextq_u16_4 (uint16x8_t a, uint16x8_t b)
-+{
-+  return vextq_u16 (a, b, 4);
-+}
-+
-+uint16x8_t
-+test_vextq_u16_5 (uint16x8_t a, uint16x8_t b)
-+{
-+  return vextq_u16 (a, b, 5);
-+}
-+
-+uint16x8_t
-+test_vextq_u16_6 (uint16x8_t a, uint16x8_t b)
-+{
-+  return vextq_u16 (a, b, 6);
-+}
-+
-+uint16x8_t
-+test_vextq_u16_7 (uint16x8_t a, uint16x8_t b)
-+{
-+  return vextq_u16 (a, b, 7);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i, off;
-+  uint16_t arr1[] = {0, 1, 2, 3, 4, 5, 6, 7};
-+  uint16x8_t in1 = vld1q_u16 (arr1);
-+  uint16_t arr2[] = {8, 9, 10, 11, 12, 13, 14, 15};
-+  uint16x8_t in2 = vld1q_u16 (arr2);
-+  uint16_t exp[8];
-+  uint16x8_t expected;
-+  uint16x8_t actual = test_vextq_u16_1 (in1, in2);
-+
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 1;
-+  expected = vld1q_u16 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_u16_2 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 2;
-+  expected = vld1q_u16 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_u16_3 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 3;
-+  expected = vld1q_u16 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_u16_4 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 4;
-+  expected = vld1q_u16 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_u16_5 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 5;
-+  expected = vld1q_u16 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_u16_6 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 6;
-+  expected = vld1q_u16 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_u16_7 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 7;
-+  expected = vld1q_u16 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzips16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzips16_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vzip_s16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vzips16.x"
-+
-+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqs16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqs16.x
-@@ -0,0 +1,26 @@
-+extern void abort (void);
-+
-+int16x8x2_t
-+test_vuzpqs16 (int16x8_t _a, int16x8_t _b)
-+{
-+  return vuzpq_s16 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  int16_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
-+  int16_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
-+  int16x8x2_t result = test_vuzpqs16 (vld1q_s16 (first), vld1q_s16 (second));
-+  int16_t exp1[] = {1, 3, 5, 7, 9, 11, 13, 15};
-+  int16_t exp2[] = {2, 4, 6, 8, 10, 12, 14, 16};
-+  int16x8_t expect1 = vld1q_s16 (exp1);
-+  int16x8_t expect2 = vld1q_s16 (exp2);
-+
-+  for (i = 0; i < 8; i++)
-+    if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqs8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqs8_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vzipq_s8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vzipqs8.x"
-+
-+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qp8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qp8_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev64q_p8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev64qp8.x"
-+
-+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.16b, ?v\[0-9\]+.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnu16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnu16_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vtrn_u16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vtrnu16.x"
-+
-+/* { dg-final { scan-assembler-times "trn1\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "trn2\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqu16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqu16.x
-@@ -0,0 +1,26 @@
-+extern void abort (void);
-+
-+uint16x8x2_t
-+test_vuzpqu16 (uint16x8_t _a, uint16x8_t _b)
-+{
-+  return vuzpq_u16 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  uint16_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
-+  uint16_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
-+  uint16x8x2_t result = test_vuzpqu16 (vld1q_u16 (first), vld1q_u16 (second));
-+  uint16_t exp1[] = {1, 3, 5, 7, 9, 11, 13, 15};
-+  uint16_t exp2[] = {2, 4, 6, 8, 10, 12, 14, 16};
-+  uint16x8_t expect1 = vld1q_u16 (exp1);
-+  uint16x8_t expect2 = vld1q_u16 (exp2);
-+
-+  for (i = 0; i < 8; i++)
-+    if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpu8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpu8.x
-@@ -0,0 +1,26 @@
-+extern void abort (void);
-+
-+uint8x8x2_t
-+test_vuzpu8 (uint8x8_t _a, uint8x8_t _b)
-+{
-+  return vuzp_u8 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  uint8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
-+  uint8_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
-+  uint8x8x2_t result = test_vuzpu8 (vld1_u8 (first), vld1_u8 (second));
-+  uint8_t exp1[] = {1, 3, 5, 7, 9, 11, 13, 15};
-+  uint8_t exp2[] = {2, 4, 6, 8, 10, 12, 14, 16};
-+  uint8x8_t expect1 = vld1_u8 (exp1);
-+  uint8x8_t expect2 = vld1_u8 (exp2);
-+
-+  for (i = 0; i < 8; i++)
-+    if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/ext_u16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/ext_u16_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vextu16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+
-+#include "arm_neon.h"
-+#include "ext_u16.x"
-+
-+/* { dg-final { scan-assembler-times "ext\[ \t\]+\[vV\]\[0-9\]+\.8\[bB\], ?\[vV\]\[0-9\]+\.8\[bB\], ?\[vV\]\[0-9\]+\.8\[bB\], ?#\[0-9\]+\(?:.2\)?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 3 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/extq_u8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/extq_u8_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vextQu8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+
-+#include "arm_neon.h"
-+#include "extq_u8.x"
-+
-+/* { dg-final { scan-assembler-times "ext\[ \t\]+\[vV\]\[0-9\]+\.16\[bB\], ?\[vV\]\[0-9\]+\.16\[bB\], ?\[vV\]\[0-9\]+\.16\[bB\], ?#?\[0-9\]+\(?:.2\)?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 15 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qu8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qu8.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+uint8x16_t
-+test_vrev64qu8 (uint8x16_t _arg)
-+{
-+  return vrev64q_u8 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  uint8x16_t inorder = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
-+  uint8x16_t reversed = test_vrev64qu8 (inorder);
-+  uint8x16_t expected = {8, 7, 6, 5, 4, 3, 2, 1, 16, 15, 14, 13, 12, 11, 10, 9};
-+
-+  for (i = 0; i < 16; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32p8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32p8_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev32_p8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev32p8.x"
-+
-+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.8b, ?v\[0-9\]+.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzps32.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzps32.x
-@@ -0,0 +1,26 @@
-+extern void abort (void);
-+
-+int32x2x2_t
-+test_vuzps32 (int32x2_t _a, int32x2_t _b)
-+{
-+  return vuzp_s32 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  int32_t first[] = {1, 2};
-+  int32_t second[] = {3, 4};
-+  int32x2x2_t result = test_vuzps32 (vld1_s32 (first), vld1_s32 (second));
-+  int32_t exp1[] = {1, 3};
-+  int32_t exp2[] = {2, 4};
-+  int32x2_t expect1 = vld1_s32 (exp1);
-+  int32x2_t expect2 = vld1_s32 (exp2);
-+
-+  for (i = 0; i < 2; i++)
-+    if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/ext_s64.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/ext_s64.x
-@@ -0,0 +1,17 @@
-+extern void abort (void);
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i, off;
-+  int64_t arr1[] = {0};
-+  int64x1_t in1 = vld1_s64 (arr1);
-+  int64_t arr2[] = {1};
-+  int64x1_t in2 = vld1_s64 (arr2);
-+  int64x1_t actual = vext_s64 (in1, in2, 0);
-+  if (actual != in1)
-+    abort ();
-+
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpu32.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpu32.x
-@@ -0,0 +1,26 @@
-+extern void abort (void);
-+
-+uint32x2x2_t
-+test_vuzpu32 (uint32x2_t _a, uint32x2_t _b)
-+{
-+  return vuzp_u32 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  uint32_t first[] = {1, 2};
-+  uint32_t second[] = {3, 4};
-+  uint32x2x2_t result = test_vuzpu32 (vld1_u32 (first), vld1_u32 (second));
-+  uint32_t exp1[] = {1, 3};
-+  uint32_t exp2[] = {2, 4};
-+  uint32x2_t expect1 = vld1_u32 (exp1);
-+  uint32x2_t expect2 = vld1_u32 (exp2);
-+
-+  for (i = 0; i < 2; i++)
-+    if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/ext_u64.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/ext_u64.x
-@@ -0,0 +1,17 @@
-+extern void abort (void);
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i, off;
-+  uint64_t arr1[] = {0};
-+  uint64x1_t in1 = vld1_u64 (arr1);
-+  uint64_t arr2[] = {1};
-+  uint64x1_t in2 = vld1_u64 (arr2);
-+  uint64x1_t actual = vext_u64 (in1, in2, 0);
-+  if (actual != in1)
-+    abort ();
-+
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrns8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrns8_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vtrn_s8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vtrns8.x"
-+
-+/* { dg-final { scan-assembler-times "trn1\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "trn2\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs16_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vtrnq_s16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vtrnqs16.x"
-+
-+/* { dg-final { scan-assembler-times "trn1\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "trn2\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qs32_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qs32_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev64q_s32' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev64qs32.x"
-+
-+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.4s, ?v\[0-9\]+.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64s8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64s8_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev64_s8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev64s8.x"
-+
-+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.8b, ?v\[0-9\]+.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqs16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqs16.x
-@@ -0,0 +1,27 @@
-+extern void abort (void);
-+
-+int16x8x2_t
-+test_vzipqs16 (int16x8_t _a, int16x8_t _b)
-+{
-+  return vzipq_s16 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  int16_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
-+  int16_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
-+  int16x8x2_t result = test_vzipqs16 (vld1q_s16 (first), vld1q_s16 (second));
-+  int16x8_t res1 = result.val[0], res2 = result.val[1];
-+  int16_t exp1[] = {1, 9, 2, 10, 3, 11, 4, 12};
-+  int16_t exp2[] = {5, 13, 6, 14, 7, 15, 8, 16};
-+  int16x8_t expected1 = vld1q_s16 (exp1);
-+  int16x8_t expected2 = vld1q_s16 (exp2);
-+
-+  for (i = 0; i < 8; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzipf32.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzipf32.x
-@@ -0,0 +1,27 @@
-+extern void abort (void);
-+
-+float32x2x2_t
-+test_vzipf32 (float32x2_t _a, float32x2_t _b)
-+{
-+  return vzip_f32 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  float32_t first[] = {1, 2};
-+  float32_t second[] = {3, 4};
-+  float32x2x2_t result = test_vzipf32 (vld1_f32 (first), vld1_f32 (second));
-+  float32x2_t res1 = result.val[0], res2 = result.val[1];
-+  float32_t exp1[] = {1, 3};
-+  float32_t exp2[] = {2, 4};
-+  float32x2_t expected1 = vld1_f32 (exp1);
-+  float32x2_t expected2 = vld1_f32 (exp2);
-+
-+  for (i = 0; i < 2; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzipu8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzipu8.x
-@@ -0,0 +1,27 @@
-+extern void abort (void);
-+
-+uint8x8x2_t
-+test_vzipu8 (uint8x8_t _a, uint8x8_t _b)
-+{
-+  return vzip_u8 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  uint8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
-+  uint8_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
-+  uint8x8x2_t result = test_vzipu8 (vld1_u8 (first), vld1_u8 (second));
-+  uint8x8_t res1 = result.val[0], res2 = result.val[1];
-+  uint8_t exp1[] = {1, 9, 2, 10, 3, 11, 4, 12};
-+  uint8_t exp2[] = {5, 13, 6, 14, 7, 15, 8, 16};
-+  uint8x8_t expected1 = vld1_u8 (exp1);
-+  uint8x8_t expected2 = vld1_u8 (exp2);
-+
-+  for (i = 0; i < 8; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqu16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqu16.x
-@@ -0,0 +1,27 @@
-+extern void abort (void);
-+
-+uint16x8x2_t
-+test_vzipqu16 (uint16x8_t _a, uint16x8_t _b)
-+{
-+  return vzipq_u16 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  uint16_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
-+  uint16_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
-+  uint16x8x2_t result = test_vzipqu16 (vld1q_u16 (first), vld1q_u16 (second));
-+  uint16x8_t res1 = result.val[0], res2 = result.val[1];
-+  uint16_t exp1[] = {1, 9, 2, 10, 3, 11, 4, 12};
-+  uint16_t exp2[] = {5, 13, 6, 14, 7, 15, 8, 16};
-+  uint16x8_t expected1 = vld1q_u16 (exp1);
-+  uint16x8_t expected2 = vld1q_u16 (exp2);
-+
-+  for (i = 0; i < 8; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/extq_s16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/extq_s16_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vextQs16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+
-+#include "arm_neon.h"
-+#include "extq_s16.x"
-+
-+/* { dg-final { scan-assembler-times "ext\[ \t\]+\[vV\]\[0-9\]+\.16\[bB\], ?\[vV\]\[0-9\]+\.16\[bB\], ?\[vV\]\[0-9\]+\.16\[bB\], ?#\[0-9\]+\(?:.2\)?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 7 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqp16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqp16_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vuzpq_p16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vuzpqp16.x"
-+
-+/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/ext_p8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/ext_p8.x
-@@ -0,0 +1,114 @@
-+extern void abort (void);
-+
-+poly8x8_t
-+test_vext_p8_1 (poly8x8_t a, poly8x8_t b)
-+{
-+  return vext_p8 (a, b, 1);
-+}
-+
-+poly8x8_t
-+test_vext_p8_2 (poly8x8_t a, poly8x8_t b)
-+{
-+  return vext_p8 (a, b, 2);
-+}
-+
-+poly8x8_t
-+test_vext_p8_3 (poly8x8_t a, poly8x8_t b)
-+{
-+  return vext_p8 (a, b, 3);
-+}
-+
-+poly8x8_t
-+test_vext_p8_4 (poly8x8_t a, poly8x8_t b)
-+{
-+  return vext_p8 (a, b, 4);
-+}
-+
-+poly8x8_t
-+test_vext_p8_5 (poly8x8_t a, poly8x8_t b)
-+{
-+  return vext_p8 (a, b, 5);
-+}
-+
-+poly8x8_t
-+test_vext_p8_6 (poly8x8_t a, poly8x8_t b)
-+{
-+  return vext_p8 (a, b, 6);
-+}
-+
-+poly8x8_t
-+test_vext_p8_7 (poly8x8_t a, poly8x8_t b)
-+{
-+  return vext_p8 (a, b, 7);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i, off;
-+  poly8_t arr1[] = {0, 1, 2, 3, 4, 5, 6, 7};
-+  poly8x8_t in1 = vld1_p8 (arr1);
-+  poly8_t arr2[] = {8, 9, 10, 11, 12, 13, 14, 15};
-+  poly8x8_t in2 = vld1_p8 (arr2);
-+  poly8_t exp[8];
-+  poly8x8_t expected;
-+  poly8x8_t actual = test_vext_p8_1 (in1, in2);
-+
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 1;
-+  expected = vld1_p8 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vext_p8_2 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 2;
-+  expected = vld1_p8 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vext_p8_3 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 3;
-+  expected = vld1_p8 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vext_p8_4 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 4;
-+  expected = vld1_p8 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vext_p8_5 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 5;
-+  expected = vld1_p8 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vext_p8_6 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 6;
-+  expected = vld1_p8 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vext_p8_7 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 7;
-+  expected = vld1_p8 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqu32_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqu32_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vuzpq_u32' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vuzpqu32.x"
-+
-+/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32s16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32s16_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev32_s16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev32s16.x"
-+
-+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.4h, ?v\[0-9\]+.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpp8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpp8.x
-@@ -0,0 +1,26 @@
-+extern void abort (void);
-+
-+poly8x8x2_t
-+test_vuzpp8 (poly8x8_t _a, poly8x8_t _b)
-+{
-+  return vuzp_p8 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  poly8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
-+  poly8_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
-+  poly8x8x2_t result = test_vuzpp8 (vld1_p8 (first), vld1_p8 (second));
-+  poly8_t exp1[] = {1, 3, 5, 7, 9, 11, 13, 15};
-+  poly8_t exp2[] = {2, 4, 6, 8, 10, 12, 14, 16};
-+  poly8x8_t expect1 = vld1_p8 (exp1);
-+  poly8x8_t expect2 = vld1_p8 (exp2);
-+
-+  for (i = 0; i < 8; i++)
-+    if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqp8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqp8_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vzipq_p8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vzipqp8.x"
-+
-+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32qs8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32qs8_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev32q_s8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev32qs8.x"
-+
-+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.16b, ?v\[0-9\]+.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64s32_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64s32_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev64_s32' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev64s32.x"
-+
-+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.2s, ?v\[0-9\]+.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/simd.exp
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/simd.exp
-@@ -0,0 +1,45 @@
-+#  Specific regression driver for AArch64 SIMD instructions.
-+#  Copyright (C) 2014 Free Software Foundation, Inc.
-+#  Contributed by ARM Ltd.
-+#
-+#  This file is part of GCC.
-+#
-+#  GCC is free software; you can redistribute it and/or modify it
-+#  under the terms of the GNU General Public License as published by
-+#  the Free Software Foundation; either version 3, or (at your option)
-+#  any later version.
-+#
-+#  GCC is distributed in the hope that it will be useful, but
-+#  WITHOUT ANY WARRANTY; without even the implied warranty of
-+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+#  General Public License for more details.
-+#
-+#  You should have received a copy of the GNU General Public License
-+#  along with GCC; see the file COPYING3.  If not see
-+#  <http://www.gnu.org/licenses/>.  */
-+
-+# GCC testsuite that uses the `dg.exp' driver.
-+
-+# Exit immediately if this isn't an AArch64 target.
-+if {![istarget aarch64*-*-*] } then {
-+  return
-+}
-+
-+# Load support procs.
-+load_lib gcc-dg.exp
-+
-+# If a testcase doesn't have special options, use these.
-+global DEFAULT_CFLAGS
-+if ![info exists DEFAULT_CFLAGS] then {
-+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
-+}
-+
-+# Initialize `dg'.
-+dg-init
-+
-+# Main loop.
-+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
-+	"" $DEFAULT_CFLAGS
-+
-+# All done.
-+dg-finish
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrns16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrns16.x
-@@ -0,0 +1,27 @@
-+extern void abort (void);
-+
-+int16x4x2_t
-+test_vtrns16 (int16x4_t _a, int16x4_t _b)
-+{
-+  return vtrn_s16 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  int16_t first[] = {1, 2, 3, 4};
-+  int16_t second[] = {5, 6, 7, 8};
-+  int16x4x2_t result = test_vtrns16 (vld1_s16 (first), vld1_s16 (second));
-+  int16x4_t res1 = result.val[0], res2 = result.val[1];
-+  int16_t exp1[] = {1, 5, 3, 7};
-+  int16_t exp2[] = {2, 6, 4, 8};
-+  int16x4_t expected1 = vld1_s16 (exp1);
-+  int16x4_t expected2 = vld1_s16 (exp2);
-+
-+  for (i = 0; i < 4; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qu8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qu8_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev64q_u8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev64qu8.x"
-+
-+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.16b, ?v\[0-9\]+.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qp8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qp8.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+poly8x16_t
-+test_vrev64qp8 (poly8x16_t _arg)
-+{
-+  return vrev64q_p8 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  poly8x16_t inorder = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
-+  poly8x16_t reversed = test_vrev64qp8 (inorder);
-+  poly8x16_t expected = {8, 7, 6, 5, 4, 3, 2, 1, 16, 15, 14, 13, 12, 11, 10, 9};
-+
-+  for (i = 0; i < 16; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnu16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnu16.x
-@@ -0,0 +1,27 @@
-+extern void abort (void);
-+
-+uint16x4x2_t
-+test_vtrnu16 (uint16x4_t _a, uint16x4_t _b)
-+{
-+  return vtrn_u16 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  uint16_t first[] = {1, 2, 3, 4};
-+  uint16_t second[] = {5, 6, 7, 8};
-+  uint16x4x2_t result = test_vtrnu16 (vld1_u16 (first), vld1_u16 (second));
-+  uint16x4_t res1 = result.val[0], res2 = result.val[1];
-+  uint16_t exp1[] = {1, 5, 3, 7};
-+  uint16_t exp2[] = {2, 6, 4, 8};
-+  uint16x4_t expected1 = vld1_u16 (exp1);
-+  uint16x4_t expected2 = vld1_u16 (exp2);
-+
-+  for (i = 0; i < 4; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/ext_p16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/ext_p16.x
-@@ -0,0 +1,58 @@
-+extern void abort (void);
-+
-+poly16x4_t
-+test_vext_p16_1 (poly16x4_t a, poly16x4_t b)
-+{
-+  return vext_p16 (a, b, 1);
-+}
-+
-+poly16x4_t
-+test_vext_p16_2 (poly16x4_t a, poly16x4_t b)
-+{
-+  return vext_p16 (a, b, 2);
-+}
-+
-+poly16x4_t
-+test_vext_p16_3 (poly16x4_t a, poly16x4_t b)
-+{
-+  return vext_p16 (a, b, 3);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i, off;
-+  poly16_t arr1[] = {0, 1, 2, 3};
-+  poly16x4_t in1 = vld1_p16 (arr1);
-+  poly16_t arr2[] = {4, 5, 6, 7};
-+  poly16x4_t in2 = vld1_p16 (arr2);
-+  poly16_t exp[4];
-+  poly16x4_t expected;
-+  poly16x4_t actual = test_vext_p16_1 (in1, in2);
-+
-+  for (i = 0; i < 4; i++)
-+    exp[i] = i + 1;
-+  expected = vld1_p16 (exp);
-+  for (i = 0; i < 4; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vext_p16_2 (in1, in2);
-+  for (i = 0; i < 4; i++)
-+    exp[i] = i + 2;
-+  expected = vld1_p16 (exp);
-+  for (i = 0; i < 4; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vext_p16_3 (in1, in2);
-+  for (i = 0; i < 4; i++)
-+    exp[i] = i + 3;
-+  expected = vld1_p16 (exp);
-+  for (i = 0; i < 4; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpp16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpp16_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vuzp_p16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vuzpp16.x"
-+
-+/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqu8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqu8.x
-@@ -0,0 +1,29 @@
-+extern void abort (void);
-+
-+uint8x16x2_t
-+test_vzipqu8 (uint8x16_t _a, uint8x16_t _b)
-+{
-+  return vzipq_u8 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  uint8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
-+  uint8_t second[] =
-+      {17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32};
-+  uint8x16x2_t result = test_vzipqu8 (vld1q_u8 (first), vld1q_u8 (second));
-+  uint8x16_t res1 = result.val[0], res2 = result.val[1];
-+  uint8_t exp1[] = {1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23, 8, 24};
-+  uint8_t exp2[] =
-+      {9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31, 16, 32};
-+  uint8x16_t expected1 = vld1q_u8 (exp1);
-+  uint8x16_t expected2 = vld1q_u8 (exp2);
-+
-+  for (i = 0; i < 16; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/ext_u64_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/ext_u64_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vextu64' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+
-+#include "arm_neon.h"
-+#include "ext_u64.x"
-+
-+/* Do not scan-assembler.  An EXT instruction could be emitted, but would merely
-+   return its first argument, so it is legitimate to optimize it out.  */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpu32_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpu32_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vuzp_u32' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vuzpu32.x"
-+
-+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32qp16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32qp16_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev32q_p16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev32qp16.x"
-+
-+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.8h, ?v\[0-9\]+.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/extq_f32.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/extq_f32.x
-@@ -0,0 +1,58 @@
-+extern void abort (void);
-+
-+float32x4_t
-+test_vextq_f32_1 (float32x4_t a, float32x4_t b)
-+{
-+  return vextq_f32 (a, b, 1);
-+}
-+
-+float32x4_t
-+test_vextq_f32_2 (float32x4_t a, float32x4_t b)
-+{
-+  return vextq_f32 (a, b, 2);
-+}
-+
-+float32x4_t
-+test_vextq_f32_3 (float32x4_t a, float32x4_t b)
-+{
-+  return vextq_f32 (a, b, 3);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i, off;
-+  float32_t arr1[] = {0, 1, 2, 3};
-+  float32x4_t in1 = vld1q_f32 (arr1);
-+  float32_t arr2[] = {4, 5, 6, 7};
-+  float32x4_t in2 = vld1q_f32 (arr2);
-+  float32_t exp[4];
-+  float32x4_t expected;
-+  float32x4_t actual = test_vextq_f32_1 (in1, in2);
-+
-+  for (i = 0; i < 4; i++)
-+    exp[i] = i + 1;
-+  expected = vld1q_f32 (exp);
-+  for (i = 0; i < 4; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_f32_2 (in1, in2);
-+  for (i = 0; i < 4; i++)
-+    exp[i] = i + 2;
-+  expected = vld1q_f32 (exp);
-+  for (i = 0; i < 4; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_f32_3 (in1, in2);
-+  for (i = 0; i < 4; i++)
-+    exp[i] = i + 3;
-+  expected = vld1q_f32 (exp);
-+  for (i = 0; i < 4; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqp16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqp16_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vzipq_p16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vzipqp16.x"
-+
-+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnp8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnp8_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vtrn_p8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vtrnp8.x"
-+
-+/* { dg-final { scan-assembler-times "trn1\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "trn2\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/extq_u8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/extq_u8.x
-@@ -0,0 +1,227 @@
-+extern void abort (void);
-+
-+uint8x16_t
-+test_vextq_u8_1 (uint8x16_t a, uint8x16_t b)
-+{
-+  return vextq_u8 (a, b, 1);
-+}
-+
-+uint8x16_t
-+test_vextq_u8_2 (uint8x16_t a, uint8x16_t b)
-+{
-+  return vextq_u8 (a, b, 2);
-+}
-+
-+uint8x16_t
-+test_vextq_u8_3 (uint8x16_t a, uint8x16_t b)
-+{
-+  return vextq_u8 (a, b, 3);
-+}
-+
-+uint8x16_t
-+test_vextq_u8_4 (uint8x16_t a, uint8x16_t b)
-+{
-+  return vextq_u8 (a, b, 4);
-+}
-+
-+uint8x16_t
-+test_vextq_u8_5 (uint8x16_t a, uint8x16_t b)
-+{
-+  return vextq_u8 (a, b, 5);
-+}
-+
-+uint8x16_t
-+test_vextq_u8_6 (uint8x16_t a, uint8x16_t b)
-+{
-+  return vextq_u8 (a, b, 6);
-+}
-+
-+uint8x16_t
-+test_vextq_u8_7 (uint8x16_t a, uint8x16_t b)
-+{
-+  return vextq_u8 (a, b, 7);
-+}
-+
-+uint8x16_t
-+test_vextq_u8_8 (uint8x16_t a, uint8x16_t b)
-+{
-+  return vextq_u8 (a, b, 8);
-+}
-+
-+uint8x16_t
-+test_vextq_u8_9 (uint8x16_t a, uint8x16_t b)
-+{
-+  return vextq_u8 (a, b, 9);
-+}
-+
-+uint8x16_t
-+test_vextq_u8_10 (uint8x16_t a, uint8x16_t b)
-+{
-+  return vextq_u8 (a, b, 10);
-+}
-+
-+uint8x16_t
-+test_vextq_u8_11 (uint8x16_t a, uint8x16_t b)
-+{
-+  return vextq_u8 (a, b, 11);
-+}
-+
-+uint8x16_t
-+test_vextq_u8_12 (uint8x16_t a, uint8x16_t b)
-+{
-+  return vextq_u8 (a, b, 12);
-+}
-+
-+uint8x16_t
-+test_vextq_u8_13 (uint8x16_t a, uint8x16_t b)
-+{
-+  return vextq_u8 (a, b, 13);
-+}
-+
-+uint8x16_t
-+test_vextq_u8_14 (uint8x16_t a, uint8x16_t b)
-+{
-+  return vextq_u8 (a, b, 14);
-+}
-+
-+uint8x16_t
-+test_vextq_u8_15 (uint8x16_t a, uint8x16_t b)
-+{
-+  return vextq_u8 (a, b, 15);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  uint8_t arr1[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
-+  uint8x16_t in1 = vld1q_u8 (arr1);
-+  uint8_t arr2[] =
-+      {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31};
-+  uint8x16_t in2 = vld1q_u8 (arr2);
-+  uint8_t exp[16];
-+  uint8x16_t expected;
-+  uint8x16_t actual = test_vextq_u8_1 (in1, in2);
-+
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 1;
-+  expected = vld1q_u8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_u8_2 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 2;
-+  expected = vld1q_u8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_u8_3 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 3;
-+  expected = vld1q_u8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_u8_4 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 4;
-+  expected = vld1q_u8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_u8_5 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 5;
-+  expected = vld1q_u8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_u8_6 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 6;
-+  expected = vld1q_u8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_u8_7 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 7;
-+  expected = vld1q_u8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_u8_8 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 8;
-+  expected = vld1q_u8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_u8_9 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 9;
-+  expected = vld1q_u8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_u8_10 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 10;
-+  expected = vld1q_u8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_u8_11 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 11;
-+  expected = vld1q_u8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_u8_12 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 12;
-+  expected = vld1q_u8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_u8_13 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 13;
-+  expected = vld1q_u8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_u8_14 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 14;
-+  expected = vld1q_u8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_u8_15 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 15;
-+  expected = vld1q_u8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqu32_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqu32_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vzipq_u32' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vzipqu32.x"
-+
-+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64p8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64p8_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev64_p8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev64p8.x"
-+
-+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.8b, ?v\[0-9\]+.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32u8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32u8_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev32_u8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev32u8.x"
-+
-+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.8b, ?v\[0-9\]+.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev16s8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev16s8_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev16_s8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev16s8.x"
-+
-+/* { dg-final { scan-assembler-times "rev16\[ \t\]+v\[0-9\]+.8b, ?v\[0-9\]+.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqf32.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqf32.x
-@@ -0,0 +1,26 @@
-+extern void abort (void);
-+
-+float32x4x2_t
-+test_vuzpqf32 (float32x4_t _a, float32x4_t _b)
-+{
-+  return vuzpq_f32 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  float32_t first[] = {1, 2, 3, 4};
-+  float32_t second[] = {5, 6, 7, 8};
-+  float32x4x2_t result = test_vuzpqf32 (vld1q_f32 (first), vld1q_f32 (second));
-+  float32_t exp1[] = {1, 3, 5, 7};
-+  float32_t exp2[] = {2, 4, 6, 8};
-+  float32x4_t expect1 = vld1q_f32 (exp1);
-+  float32x4_t expect2 = vld1q_f32 (exp2);
-+
-+  for (i = 0; i < 4; i++)
-+    if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzipp8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzipp8.x
-@@ -0,0 +1,27 @@
-+extern void abort (void);
-+
-+poly8x8x2_t
-+test_vzipp8 (poly8x8_t _a, poly8x8_t _b)
-+{
-+  return vzip_p8 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  poly8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
-+  poly8_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
-+  poly8x8x2_t result = test_vzipp8 (vld1_p8 (first), vld1_p8 (second));
-+  poly8x8_t res1 = result.val[0], res2 = result.val[1];
-+  poly8_t exp1[] = {1, 9, 2, 10, 3, 11, 4, 12};
-+  poly8_t exp2[] = {5, 13, 6, 14, 7, 15, 8, 16};
-+  poly8x8_t expected1 = vld1_p8 (exp1);
-+  poly8x8_t expected2 = vld1_p8 (exp2);
-+
-+  for (i = 0; i < 8; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs32.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs32.x
-@@ -0,0 +1,27 @@
-+extern void abort (void);
-+
-+int32x4x2_t
-+test_vtrnqs32 (int32x4_t _a, int32x4_t _b)
-+{
-+  return vtrnq_s32 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  int32_t first[] = {1, 2, 3, 4};
-+  int32_t second[] = {5, 6, 7, 8};
-+  int32x4x2_t result = test_vtrnqs32 (vld1q_s32 (first), vld1q_s32 (second));
-+  int32x4_t res1 = result.val[0], res2 = result.val[1];
-+  int32_t exp1[] = {1, 5, 3, 7};
-+  int32_t exp2[] = {2, 6, 4, 8};
-+  int32x4_t expected1 = vld1q_s32 (exp1);
-+  int32x4_t expected2 = vld1q_s32 (exp2);
-+
-+  for (i = 0; i < 4; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/int_comparisons_2.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/int_comparisons_2.c
-@@ -0,0 +1,131 @@
-+/* { dg-do run } */
-+/* { dg-options "-O2 -fno-inline" } */
-+/* Stops the test_xxx methods being inlined into main, thus preventing constant
-+   propagation.  */
-+
-+#include "int_comparisons.x"
-+
-+extern void abort (void);
-+
-+#define CHECK2(R0, R1) if (res[0] != R0 || res[1] != R1) abort ()
-+
-+#define TEST2(BASETYPE, SUFFIX, RESTYPE, ST1_SUFFIX) {			\
-+  BASETYPE##_t _a[2] = {2, 3};						\
-+  BASETYPE##x2_t a = vld1##SUFFIX (_a);					\
-+  BASETYPE##_t _b[2] = {1, 3};						\
-+  BASETYPE##x2_t b = vld1##SUFFIX (_b);					\
-+  RESTYPE res[2];							\
-+  vst1##ST1_SUFFIX (res, test_vclt##SUFFIX (a, b)); CHECK2 (0, 0);	\
-+  vst1##ST1_SUFFIX (res, test_vclt##SUFFIX (b, a)); CHECK2 (-1, 0);	\
-+  vst1##ST1_SUFFIX (res, test_vcle##SUFFIX (a, b)); CHECK2 (0, -1);	\
-+  vst1##ST1_SUFFIX (res, test_vcle##SUFFIX (b, a)); CHECK2 (-1, -1);	\
-+  vst1##ST1_SUFFIX (res, test_vceq##SUFFIX (a, b)); CHECK2 (0, -1);	\
-+  vst1##ST1_SUFFIX (res, test_vcge##SUFFIX (a, b)); CHECK2 (-1, -1);	\
-+  vst1##ST1_SUFFIX (res, test_vcge##SUFFIX (b, a)); CHECK2 (0, -1);	\
-+  vst1##ST1_SUFFIX (res, test_vcgt##SUFFIX (a, b)); CHECK2 (-1, 0);	\
-+  vst1##ST1_SUFFIX (res, test_vcgt##SUFFIX (b, a)); CHECK2 (0, 0);	\
-+  vst1##ST1_SUFFIX (res, test_vtst##SUFFIX (a, b)); CHECK2 (0, -1);	\
-+  vst1##ST1_SUFFIX (res, test_vtst##SUFFIX (a + 1, b)); CHECK2 (-1, 0); \
-+}
-+
-+#define CHECK4(T, R0, R1, R2, R3)		\
-+  if (res[0] != (T)R0 || res[1] != (T)R1	\
-+      || res[2] != (T)R2 || res[3] != (T)R3) abort ()
-+
-+#define TEST4(BASETYPE, SUFFIX, RESTYPE, ST1_SUFFIX) {	\
-+  BASETYPE##_t _a[4] = {1, 2, 3, 4};			\
-+  BASETYPE##x4_t a = vld1##SUFFIX (_a);			\
-+  BASETYPE##_t _b[4] = {4, 2, 1, 3};			\
-+  BASETYPE##x4_t b = vld1##SUFFIX (_b);			\
-+  RESTYPE res[4];					\
-+  vst1##ST1_SUFFIX (res, test_vclt##SUFFIX (a, b));	\
-+  CHECK4 (RESTYPE, -1, 0, 0, 0);			\
-+  vst1##ST1_SUFFIX (res, test_vcle##SUFFIX (a, b));	\
-+  CHECK4 (RESTYPE, -1, -1, 0, 0);			\
-+  vst1##ST1_SUFFIX (res, test_vceq##SUFFIX (a, b));	\
-+  CHECK4 (RESTYPE, 0, -1, 0, 0);			\
-+  vst1##ST1_SUFFIX (res, test_vcge##SUFFIX (a, b));	\
-+  CHECK4 (RESTYPE, 0, -1, -1, -1);			\
-+  vst1##ST1_SUFFIX (res, test_vcgt##SUFFIX (a, b));	\
-+  CHECK4 (RESTYPE, 0, 0, -1, -1);			\
-+  vst1##ST1_SUFFIX (res, test_vtst##SUFFIX (a, b));	\
-+  CHECK4 (RESTYPE, 0, -1, -1, 0);			\
-+}
-+
-+#define CHECK8(T, R0, R1, R2, R3, R4, R5, R6, R7)			       \
-+  if (res[0] != (T)R0 || res[1] != (T)R1 || res[2] != (T)R2 || res[3] != (T)R3 \
-+      || res[4] != (T)R4 || res[5] != (T)R5 || res[6] != (T)R6		       \
-+      || res[7] != (T)R7) abort ()
-+
-+#define TEST8(BASETYPE, SUFFIX, RESTYPE, ST1_SUFFIX) {	\
-+  BASETYPE##_t _a[8] = {1, 2, 3, 4, 5, 6, 7, 8};	\
-+  BASETYPE##x8_t a = vld1##SUFFIX (_a);			\
-+  BASETYPE##_t _b[8] = {4, 2, 1, 3, 2, 6, 8, 9};	\
-+  BASETYPE##x8_t b = vld1##SUFFIX (_b);			\
-+  RESTYPE res[8];					\
-+  vst1##ST1_SUFFIX (res, test_vclt##SUFFIX (a, b));	\
-+  CHECK8 (RESTYPE, -1, 0, 0, 0, 0, 0, -1, -1);		\
-+  vst1##ST1_SUFFIX (res, test_vcle##SUFFIX (a, b));	\
-+  CHECK8 (RESTYPE, -1, -1, 0, 0, 0, -1, -1, -1);	\
-+  vst1##ST1_SUFFIX (res, test_vceq##SUFFIX (a, b));	\
-+  CHECK8 (RESTYPE, 0, -1, 0, 0, 0, -1, 0, 0);		\
-+  vst1##ST1_SUFFIX (res, test_vcge##SUFFIX (a, b));	\
-+  CHECK8 (RESTYPE, 0, -1, -1, -1, -1, -1, 0, 0);	\
-+  vst1##ST1_SUFFIX (res, test_vcgt##SUFFIX (a, b));	\
-+  CHECK8 (RESTYPE, 0, 0, -1, -1, -1, 0, 0, 0);		\
-+  vst1##ST1_SUFFIX (res, test_vtst##SUFFIX (a, b));	\
-+  CHECK8 (RESTYPE, 0, -1, -1, 0, 0, -1, 0, -1);		\
-+}
-+
-+/* 16-way tests use same 8 values twice.  */
-+#define CHECK16(T, R0, R1, R2, R3, R4, R5, R6, R7)			       \
-+  if (res[0] != (T)R0 || res[1] != (T)R1 || res[2] != (T)R2 || res[3] != (T)R3 \
-+      || res[4] != (T)R4 || res[5] != (T)R5 || res[6] != (T)R6		       \
-+      || res[7] != (T)R7 || res[8] != (T)R0 || res[9] != (T)R1		       \
-+      || res[10] != (T)R2 || res[11] != (T)R3 || res[12] != (T)R4	       \
-+      || res[13] != (T)R5 || res[14] != (T)R6 || res[15] != (T)R7) abort ()
-+
-+#define TEST16(BASETYPE, SUFFIX, RESTYPE, ST1_SUFFIX) {			  \
-+  BASETYPE##_t _a[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8}; \
-+  BASETYPE##x16_t a = vld1##SUFFIX (_a);				  \
-+  BASETYPE##_t _b[16] = {4, 2, 1, 3, 2, 6, 8, 9, 4, 2, 1, 3, 2, 6, 8, 9}; \
-+  BASETYPE##x16_t b = vld1##SUFFIX (_b);				  \
-+  RESTYPE res[16];							  \
-+  vst1##ST1_SUFFIX (res, test_vclt##SUFFIX (a, b));			  \
-+  CHECK16 (RESTYPE, -1, 0, 0, 0, 0, 0, -1, -1);				  \
-+  vst1##ST1_SUFFIX (res, test_vcle##SUFFIX (a, b));			  \
-+  CHECK16 (RESTYPE, -1, -1, 0, 0, 0, -1, -1, -1);			  \
-+  vst1##ST1_SUFFIX (res, test_vceq##SUFFIX (a, b));			  \
-+  CHECK16 (RESTYPE, 0, -1, 0, 0, 0, -1, 0, 0);				  \
-+  vst1##ST1_SUFFIX (res, test_vcge##SUFFIX (a, b));			  \
-+  CHECK16 (RESTYPE, 0, -1, -1, -1, -1, -1, 0, 0);			  \
-+  vst1##ST1_SUFFIX (res, test_vcgt##SUFFIX (a, b));			  \
-+  CHECK16 (RESTYPE, 0, 0, -1, -1, -1, 0, 0, 0);				  \
-+  vst1##ST1_SUFFIX (res, test_vtst##SUFFIX (a, b));			  \
-+  CHECK16 (RESTYPE, 0, -1, -1, 0, 0, -1, 0, -1);			  \
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  TEST2 (int32, _s32, uint32_t, _u32);
-+  TEST2 (uint32, _u32, uint32_t, _u32);
-+  TEST2 (int64, q_s64, uint64_t, q_u64);
-+  TEST2 (uint64, q_u64, uint64_t, q_u64);
-+
-+  TEST4 (int16, _s16, uint16_t, _u16);
-+  TEST4 (uint16, _u16, uint16_t, _u16);
-+  TEST4 (int32, q_s32, uint32_t, q_u32);
-+  TEST4 (uint32, q_u32, uint32_t, q_u32);
-+
-+  TEST8 (int8, _s8, uint8_t, _u8);
-+  TEST8 (uint8, _u8, uint8_t, _u8);
-+  TEST8 (int16, q_s16, uint16_t, q_u16);
-+  TEST8 (uint16, q_u16, uint16_t, q_u16);
-+
-+  TEST16 (int8, q_s8, uint8_t, q_u8);
-+  TEST16 (uint8, q_u8, uint8_t, q_u8);
-+
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu32.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu32.x
-@@ -0,0 +1,27 @@
-+extern void abort (void);
-+
-+uint32x4x2_t
-+test_vtrnqu32 (uint32x4_t _a, uint32x4_t _b)
-+{
-+  return vtrnq_u32 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  uint32_t first[] = {1, 2, 3, 4};
-+  uint32_t second[] = {5, 6, 7, 8};
-+  uint32x4x2_t result = test_vtrnqu32 (vld1q_u32 (first), vld1q_u32 (second));
-+  uint32x4_t res1 = result.val[0], res2 = result.val[1];
-+  uint32_t exp1[] = {1, 5, 3, 7};
-+  uint32_t exp2[] = {2, 6, 4, 8};
-+  uint32x4_t expected1 = vld1q_u32 (exp1);
-+  uint32x4_t expected2 = vld1q_u32 (exp2);
-+
-+  for (i = 0; i < 4; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qs32.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qs32.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+int32x4_t
-+test_vrev64qs32 (int32x4_t _arg)
-+{
-+  return vrev64q_s32 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  int32x4_t inorder = {1, 2, 3, 4};
-+  int32x4_t reversed = test_vrev64qs32 (inorder);
-+  int32x4_t expected = {2, 1, 4, 3};
-+
-+  for (i = 0; i < 4; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnu8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnu8.x
-@@ -0,0 +1,27 @@
-+extern void abort (void);
-+
-+uint8x8x2_t
-+test_vtrnu8 (uint8x8_t _a, uint8x8_t _b)
-+{
-+  return vtrn_u8 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  uint8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
-+  uint8_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
-+  uint8x8x2_t result = test_vtrnu8 (vld1_u8 (first), vld1_u8 (second));
-+  uint8x8_t res1 = result.val[0], res2 = result.val[1];
-+  uint8_t exp1[] = {1, 9, 3, 11, 5, 13, 7, 15};
-+  uint8_t exp2[] = {2, 10, 4, 12, 6, 14, 8, 16};
-+  uint8x8_t expected1 = vld1_u8 (exp1);
-+  uint8x8_t expected2 = vld1_u8 (exp2);
-+
-+  for (i = 0; i < 8; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qu32.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qu32.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+uint32x4_t
-+test_vrev64qu32 (uint32x4_t _arg)
-+{
-+  return vrev64q_u32 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  uint32x4_t inorder = {1, 2, 3, 4};
-+  uint32x4_t reversed = test_vrev64qu32 (inorder);
-+  uint32x4_t expected = {2, 1, 4, 3};
-+
-+  for (i = 0; i < 4; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/extq_s64_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/extq_s64_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vextQs64' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+
-+#include "arm_neon.h"
-+#include "extq_s64.x"
-+
-+/* { dg-final { scan-assembler-times "ext\[ \t\]+\[vV\]\[0-9\]+\.16\[bB\], ?\[vV\]\[0-9\]+\.16\[bB\], ?\[vV\]\[0-9\]+\.16\[bB\], ?#\[0-9\]+\(?:.8\)?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/ext_s8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/ext_s8.x
-@@ -0,0 +1,114 @@
-+extern void abort (void);
-+
-+int8x8_t
-+test_vext_s8_1 (int8x8_t a, int8x8_t b)
-+{
-+  return vext_s8 (a, b, 1);
-+}
-+
-+int8x8_t
-+test_vext_s8_2 (int8x8_t a, int8x8_t b)
-+{
-+  return vext_s8 (a, b, 2);
-+}
-+
-+int8x8_t
-+test_vext_s8_3 (int8x8_t a, int8x8_t b)
-+{
-+  return vext_s8 (a, b, 3);
-+}
-+
-+int8x8_t
-+test_vext_s8_4 (int8x8_t a, int8x8_t b)
-+{
-+  return vext_s8 (a, b, 4);
-+}
-+
-+int8x8_t
-+test_vext_s8_5 (int8x8_t a, int8x8_t b)
-+{
-+  return vext_s8 (a, b, 5);
-+}
-+
-+int8x8_t
-+test_vext_s8_6 (int8x8_t a, int8x8_t b)
-+{
-+  return vext_s8 (a, b, 6);
-+}
-+
-+int8x8_t
-+test_vext_s8_7 (int8x8_t a, int8x8_t b)
-+{
-+  return vext_s8 (a, b, 7);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i, off;
-+  int8_t arr1[] = {0, 1, 2, 3, 4, 5, 6, 7};
-+  int8x8_t in1 = vld1_s8 (arr1);
-+  int8_t arr2[] = {8, 9, 10, 11, 12, 13, 14, 15};
-+  int8x8_t in2 = vld1_s8 (arr2);
-+  int8_t exp[8];
-+  int8x8_t expected;
-+  int8x8_t actual = test_vext_s8_1 (in1, in2);
-+
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 1;
-+  expected = vld1_s8 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vext_s8_2 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 2;
-+  expected = vld1_s8 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vext_s8_3 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 3;
-+  expected = vld1_s8 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vext_s8_4 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 4;
-+  expected = vld1_s8 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vext_s8_5 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 5;
-+  expected = vld1_s8 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vext_s8_6 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 6;
-+  expected = vld1_s8 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vext_s8_7 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 7;
-+  expected = vld1_s8 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzips32_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzips32_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vzip_s32' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vzips32.x"
-+
-+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnp16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnp16_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vtrn_p16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vtrnp16.x"
-+
-+/* { dg-final { scan-assembler-times "trn1\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "trn2\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32qp8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32qp8_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev32q_p8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev32qp8.x"
-+
-+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.16b, ?v\[0-9\]+.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnu32_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnu32_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vtrn_u32' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vtrnu32.x"
-+
-+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzps8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzps8.x
-@@ -0,0 +1,26 @@
-+extern void abort (void);
-+
-+int8x8x2_t
-+test_vuzps8 (int8x8_t _a, int8x8_t _b)
-+{
-+  return vuzp_s8 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  int8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
-+  int8_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
-+  int8x8x2_t result = test_vuzps8 (vld1_s8 (first), vld1_s8 (second));
-+  int8_t exp1[] = {1, 3, 5, 7, 9, 11, 13, 15};
-+  int8_t exp2[] = {2, 4, 6, 8, 10, 12, 14, 16};
-+  int8x8_t expect1 = vld1_s8 (exp1);
-+  int8x8_t expect2 = vld1_s8 (exp2);
-+
-+  for (i = 0; i < 8; i++)
-+    if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqu8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqu8_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vzipq_u8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vzipqu8.x"
-+
-+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqp8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqp8.x
-@@ -0,0 +1,29 @@
-+extern void abort (void);
-+
-+poly8x16x2_t
-+test_vzipqp8 (poly8x16_t _a, poly8x16_t _b)
-+{
-+  return vzipq_p8 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  poly8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
-+  poly8_t second[] =
-+      {17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32};
-+  poly8x16x2_t result = test_vzipqp8 (vld1q_p8 (first), vld1q_p8 (second));
-+  poly8x16_t res1 = result.val[0], res2 = result.val[1];
-+  poly8_t exp1[] = {1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23, 8, 24};
-+  poly8_t exp2[] =
-+      {9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31, 16, 32};
-+  poly8x16_t expected1 = vld1q_p8 (exp1);
-+  poly8x16_t expected2 = vld1q_p8 (exp2);
-+
-+  for (i = 0; i < 16; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/ext_p16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/ext_p16_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vextp16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+
-+#include "arm_neon.h"
-+#include "ext_p16.x"
-+
-+/* { dg-final { scan-assembler-times "ext\[ \t\]+\[vV\]\[0-9\]+\.8\[bB\], ?\[vV\]\[0-9\]+\.8\[bB\], ?\[vV\]\[0-9\]+\.8\[bB\], ?#\[0-9\]+\(?:.2\)?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 3 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32s16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32s16.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+int16x4_t
-+test_vrev32s16 (int16x4_t _arg)
-+{
-+  return vrev32_s16 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  int16x4_t inorder = {1, 2, 3, 4};
-+  int16x4_t reversed = test_vrev32s16 (inorder);
-+  int16x4_t expected = {2, 1, 4, 3};
-+
-+  for (i = 0; i < 4; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32u16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32u16.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+uint16x4_t
-+test_vrev32u16 (uint16x4_t _arg)
-+{
-+  return vrev32_u16 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  uint16x4_t inorder = {1, 2, 3, 4};
-+  uint16x4_t reversed = test_vrev32u16 (inorder);
-+  uint16x4_t expected = {2, 1, 4, 3};
-+
-+  for (i = 0; i < 4; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64p16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64p16.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+poly16x4_t
-+test_vrev64p16 (poly16x4_t _arg)
-+{
-+  return vrev64_p16 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  poly16x4_t inorder = {1, 2, 3, 4};
-+  poly16x4_t reversed = test_vrev64p16 (inorder);
-+  poly16x4_t expected = {4, 3, 2, 1};
-+
-+  for (i = 0; i < 4; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qf32_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qf32_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev64q_f32' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev64qf32.x"
-+
-+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.4s, ?v\[0-9\]+.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqf32.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqf32.x
-@@ -0,0 +1,27 @@
-+extern void abort (void);
-+
-+float32x4x2_t
-+test_vzipqf32 (float32x4_t _a, float32x4_t _b)
-+{
-+  return vzipq_f32 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  float32_t first[] = {1, 2, 3, 4};
-+  float32_t second[] = {5, 6, 7, 8};
-+  float32x4x2_t result = test_vzipqf32 (vld1q_f32 (first), vld1q_f32 (second));
-+  float32x4_t res1 = result.val[0], res2 = result.val[1];
-+  float32_t exp1[] = {1, 5, 2, 6};
-+  float32_t exp2[] = {3, 7, 4, 8};
-+  float32x4_t expected1 = vld1q_f32 (exp1);
-+  float32x4_t expected2 = vld1q_f32 (exp2);
-+
-+  for (i = 0; i < 4; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/ext_u32_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/ext_u32_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vextu32' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+
-+#include "arm_neon.h"
-+#include "ext_u32.x"
-+
-+/* { dg-final { scan-assembler-times "ext\[ \t\]+\[vV\]\[0-9\]+\.8\[bB\], ?\[vV\]\[0-9\]+\.8\[bB\], ?\[vV\]\[0-9\]+\.8\[bB\], ?#\[0-9\]+\(?:.4)?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/extq_p8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/extq_p8.x
-@@ -0,0 +1,227 @@
-+extern void abort (void);
-+
-+poly8x16_t
-+test_vextq_p8_1 (poly8x16_t a, poly8x16_t b)
-+{
-+  return vextq_p8 (a, b, 1);
-+}
-+
-+poly8x16_t
-+test_vextq_p8_2 (poly8x16_t a, poly8x16_t b)
-+{
-+  return vextq_p8 (a, b, 2);
-+}
-+
-+poly8x16_t
-+test_vextq_p8_3 (poly8x16_t a, poly8x16_t b)
-+{
-+  return vextq_p8 (a, b, 3);
-+}
-+
-+poly8x16_t
-+test_vextq_p8_4 (poly8x16_t a, poly8x16_t b)
-+{
-+  return vextq_p8 (a, b, 4);
-+}
-+
-+poly8x16_t
-+test_vextq_p8_5 (poly8x16_t a, poly8x16_t b)
-+{
-+  return vextq_p8 (a, b, 5);
-+}
-+
-+poly8x16_t
-+test_vextq_p8_6 (poly8x16_t a, poly8x16_t b)
-+{
-+  return vextq_p8 (a, b, 6);
-+}
-+
-+poly8x16_t
-+test_vextq_p8_7 (poly8x16_t a, poly8x16_t b)
-+{
-+  return vextq_p8 (a, b, 7);
-+}
-+
-+poly8x16_t
-+test_vextq_p8_8 (poly8x16_t a, poly8x16_t b)
-+{
-+  return vextq_p8 (a, b, 8);
-+}
-+
-+poly8x16_t
-+test_vextq_p8_9 (poly8x16_t a, poly8x16_t b)
-+{
-+  return vextq_p8 (a, b, 9);
-+}
-+
-+poly8x16_t
-+test_vextq_p8_10 (poly8x16_t a, poly8x16_t b)
-+{
-+  return vextq_p8 (a, b, 10);
-+}
-+
-+poly8x16_t
-+test_vextq_p8_11 (poly8x16_t a, poly8x16_t b)
-+{
-+  return vextq_p8 (a, b, 11);
-+}
-+
-+poly8x16_t
-+test_vextq_p8_12 (poly8x16_t a, poly8x16_t b)
-+{
-+  return vextq_p8 (a, b, 12);
-+}
-+
-+poly8x16_t
-+test_vextq_p8_13 (poly8x16_t a, poly8x16_t b)
-+{
-+  return vextq_p8 (a, b, 13);
-+}
-+
-+poly8x16_t
-+test_vextq_p8_14 (poly8x16_t a, poly8x16_t b)
-+{
-+  return vextq_p8 (a, b, 14);
-+}
-+
-+poly8x16_t
-+test_vextq_p8_15 (poly8x16_t a, poly8x16_t b)
-+{
-+  return vextq_p8 (a, b, 15);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  poly8_t arr1[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
-+  poly8x16_t in1 = vld1q_p8 (arr1);
-+  poly8_t arr2[] =
-+      {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31};
-+  poly8x16_t in2 = vld1q_p8 (arr2);
-+  poly8_t exp[16];
-+  poly8x16_t expected;
-+  poly8x16_t actual = test_vextq_p8_1 (in1, in2);
-+
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 1;
-+  expected = vld1q_p8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_p8_2 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 2;
-+  expected = vld1q_p8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_p8_3 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 3;
-+  expected = vld1q_p8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_p8_4 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 4;
-+  expected = vld1q_p8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_p8_5 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 5;
-+  expected = vld1q_p8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_p8_6 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 6;
-+  expected = vld1q_p8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_p8_7 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 7;
-+  expected = vld1q_p8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_p8_8 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 8;
-+  expected = vld1q_p8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_p8_9 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 9;
-+  expected = vld1q_p8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_p8_10 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 10;
-+  expected = vld1q_p8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_p8_11 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 11;
-+  expected = vld1q_p8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_p8_12 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 12;
-+  expected = vld1q_p8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_p8_13 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 13;
-+  expected = vld1q_p8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_p8_14 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 14;
-+  expected = vld1q_p8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_p8_15 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 15;
-+  expected = vld1q_p8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qs8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qs8.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+int8x16_t
-+test_vrev64qs8 (int8x16_t _arg)
-+{
-+  return vrev64q_s8 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  int8x16_t inorder = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
-+  int8x16_t reversed = test_vrev64qs8 (inorder);
-+  int8x16_t expected = {8, 7, 6, 5, 4, 3, 2, 1, 16, 15, 14, 13, 12, 11, 10, 9};
-+
-+  for (i = 0; i < 16; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev16p8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev16p8_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev16_p8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev16p8.x"
-+
-+/* { dg-final { scan-assembler-times "rev16\[ \t\]+v\[0-9\]+.8b, ?v\[0-9\]+.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs32_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs32_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vtrnq_s32' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vtrnqs32.x"
-+
-+/* { dg-final { scan-assembler-times "trn1\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "trn2\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzps16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzps16.x
-@@ -0,0 +1,26 @@
-+extern void abort (void);
-+
-+int16x4x2_t
-+test_vuzps16 (int16x4_t _a, int16x4_t _b)
-+{
-+  return vuzp_s16 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  int16_t first[] = {1, 2, 3, 4};
-+  int16_t second[] = {5, 6, 7, 8};
-+  int16x4x2_t result = test_vuzps16 (vld1_s16 (first), vld1_s16 (second));
-+  int16_t exp1[] = {1, 3, 5, 7};
-+  int16_t exp2[] = {2, 4, 6, 8};
-+  int16x4_t expect1 = vld1_s16 (exp1);
-+  int16x4_t expect2 = vld1_s16 (exp2);
-+
-+  for (i = 0; i < 4; i++)
-+    if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpu16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpu16.x
-@@ -0,0 +1,26 @@
-+extern void abort (void);
-+
-+uint16x4x2_t
-+test_vuzpu16 (uint16x4_t _a, uint16x4_t _b)
-+{
-+  return vuzp_u16 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  uint16_t first[] = {1, 2, 3, 4};
-+  uint16_t second[] = {5, 6, 7, 8};
-+  uint16x4x2_t result = test_vuzpu16 (vld1_u16 (first), vld1_u16 (second));
-+  uint16_t exp1[] = {1, 3, 5, 7};
-+  uint16_t exp2[] = {2, 4, 6, 8};
-+  uint16x4_t expect1 = vld1_u16 (exp1);
-+  uint16x4_t expect2 = vld1_u16 (exp2);
-+
-+  for (i = 0; i < 4; i++)
-+    if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnu8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnu8_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vtrn_u8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vtrnu8.x"
-+
-+/* { dg-final { scan-assembler-times "trn1\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "trn2\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnp8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnp8.x
-@@ -0,0 +1,27 @@
-+extern void abort (void);
-+
-+poly8x8x2_t
-+test_vtrnp8 (poly8x8_t _a, poly8x8_t _b)
-+{
-+  return vtrn_p8 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  poly8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
-+  poly8_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
-+  poly8x8x2_t result = test_vtrnp8 (vld1_p8 (first), vld1_p8 (second));
-+  poly8x8_t res1 = result.val[0], res2 = result.val[1];
-+  poly8_t exp1[] = {1, 9, 3, 11, 5, 13, 7, 15};
-+  poly8_t exp2[] = {2, 10, 4, 12, 6, 14, 8, 16};
-+  poly8x8_t expected1 = vld1_p8 (exp1);
-+  poly8x8_t expected2 = vld1_p8 (exp2);
-+
-+  for (i = 0; i < 8; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32qs16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32qs16.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+int16x8_t
-+test_vrev32qs16 (int16x8_t _arg)
-+{
-+  return vrev32q_s16 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  int16x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
-+  int16x8_t reversed = test_vrev32qs16 (inorder);
-+  int16x8_t expected = {2, 1, 4, 3, 6, 5, 8, 7};
-+
-+  for (i = 0; i < 8; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64f32_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64f32_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev64_f32' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev64f32.x"
-+
-+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.2s, ?v\[0-9\]+.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzips8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzips8.x
-@@ -0,0 +1,27 @@
-+extern void abort (void);
-+
-+int8x8x2_t
-+test_vzips8 (int8x8_t _a, int8x8_t _b)
-+{
-+  return vzip_s8 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  int8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
-+  int8_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
-+  int8x8x2_t result = test_vzips8 (vld1_s8 (first), vld1_s8 (second));
-+  int8x8_t res1 = result.val[0], res2 = result.val[1];
-+  int8_t exp1[] = {1, 9, 2, 10, 3, 11, 4, 12};
-+  int8_t exp2[] = {5, 13, 6, 14, 7, 15, 8, 16};
-+  int8x8_t expected1 = vld1_s8 (exp1);
-+  int8x8_t expected2 = vld1_s8 (exp2);
-+
-+  for (i = 0; i < 8; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/extq_s32_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/extq_s32_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vextQs32' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+
-+#include "arm_neon.h"
-+#include "extq_s32.x"
-+
-+/* { dg-final { scan-assembler-times "ext\[ \t\]+\[vV\]\[0-9\]+\.16\[bB\], ?\[vV\]\[0-9\]+\.16\[bB\], ?\[vV\]\[0-9\]+\.16\[bB\], ?#\[0-9\]+\(?:.4)?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 3 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32qu16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32qu16.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+uint16x8_t
-+test_vrev32qu16 (uint16x8_t _arg)
-+{
-+  return vrev32q_u16 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  uint16x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
-+  uint16x8_t reversed = test_vrev32qu16 (inorder);
-+  uint16x8_t expected = {2, 1, 4, 3, 6, 5, 8, 7};
-+
-+  for (i = 0; i < 8; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qu16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qu16_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev64q_u16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev64qu16.x"
-+
-+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.8h, ?v\[0-9\]+.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64u8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64u8_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev64_u8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev64u8.x"
-+
-+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.8b, ?v\[0-9\]+.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnf32.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnf32.x
-@@ -0,0 +1,27 @@
-+extern void abort (void);
-+
-+float32x2x2_t
-+test_vtrnf32 (float32x2_t _a, float32x2_t _b)
-+{
-+  return vtrn_f32 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  float32_t first[] = {1, 2};
-+  float32_t second[] = {3, 4};
-+  float32x2x2_t result = test_vtrnf32 (vld1_f32 (first), vld1_f32 (second));
-+  float32x2_t res1 = result.val[0], res2 = result.val[1];
-+  float32_t exp1[] = {1, 3};
-+  float32_t exp2[] = {2, 4};
-+  float32x2_t expected1 = vld1_f32 (exp1);
-+  float32x2_t expected2 = vld1_f32 (exp2);
-+
-+  for (i = 0; i < 2; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/ext_s8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/ext_s8_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vexts8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+
-+#include "arm_neon.h"
-+#include "ext_s8.x"
-+
-+/* { dg-final { scan-assembler-times "ext\[ \t\]+\[vV\]\[0-9\]+\.8\[bB\], ?\[vV\]\[0-9\]+\.8\[bB\], ?\[vV\]\[0-9\]+\.8\[bB\], ?#?\[0-9\]+\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 7 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev16u8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev16u8.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+uint8x8_t
-+test_vrev16u8 (uint8x8_t _arg)
-+{
-+  return vrev16_u8 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  uint8x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
-+  uint8x8_t reversed = test_vrev16u8 (inorder);
-+  uint8x8_t expected = {2, 1, 4, 3, 6, 5, 8, 7};
-+
-+  for (i = 0; i < 8; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqs16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqs16_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vuzpq_s16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vuzpqs16.x"
-+
-+/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/extq_s64.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/extq_s64.x
-@@ -0,0 +1,30 @@
-+extern void abort (void);
-+
-+int64x2_t
-+test_vextq_s64_1 (int64x2_t a, int64x2_t b)
-+{
-+  return vextq_s64 (a, b, 1);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i, off;
-+  int64_t arr1[] = {0, 1};
-+  int64x2_t in1 = vld1q_s64 (arr1);
-+  int64_t arr2[] = {2, 3};
-+  int64x2_t in2 = vld1q_s64 (arr2);
-+  int64_t exp[2];
-+  int64x2_t expected;
-+  int64x2_t actual = test_vextq_s64_1 (in1, in2);
-+
-+  for (i = 0; i < 2; i++)
-+    exp[i] = i + 1;
-+  expected = vld1q_s64 (exp);
-+  for (i = 0; i < 2; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzipp16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzipp16.x
-@@ -0,0 +1,27 @@
-+extern void abort (void);
-+
-+poly16x4x2_t
-+test_vzipp16 (poly16x4_t _a, poly16x4_t _b)
-+{
-+  return vzip_p16 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  poly16_t first[] = {1, 2, 3, 4};
-+  poly16_t second[] = {5, 6, 7, 8};
-+  poly16x4x2_t result = test_vzipp16 (vld1_p16 (first), vld1_p16 (second));
-+  poly16x4_t res1 = result.val[0], res2 = result.val[1];
-+  poly16_t exp1[] = {1, 5, 2, 6};
-+  poly16_t exp2[] = {3, 7, 4, 8};
-+  poly16x4_t expected1 = vld1_p16 (exp1);
-+  poly16x4_t expected2 = vld1_p16 (exp2);
-+
-+  for (i = 0; i < 4; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/extq_u64.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/extq_u64.x
-@@ -0,0 +1,30 @@
-+extern void abort (void);
-+
-+uint64x2_t
-+test_vextq_u64_1 (uint64x2_t a, uint64x2_t b)
-+{
-+  return vextq_u64 (a, b, 1);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i, off;
-+  uint64_t arr1[] = {0, 1};
-+  uint64x2_t in1 = vld1q_u64 (arr1);
-+  uint64_t arr2[] = {2, 3};
-+  uint64x2_t in2 = vld1q_u64 (arr2);
-+  uint64_t exp[2];
-+  uint64x2_t expected;
-+  uint64x2_t actual = test_vextq_u64_1 (in1, in2);
-+
-+  for (i = 0; i < 2; i++)
-+    exp[i] = i + 1;
-+  expected = vld1q_u64 (exp);
-+  for (i = 0; i < 2; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32qu8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32qu8_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev32q_u8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev32qu8.x"
-+
-+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.16b, ?v\[0-9\]+.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64u16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64u16_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev64_u16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev64u16.x"
-+
-+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.4h, ?v\[0-9\]+.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqs8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqs8.x
-@@ -0,0 +1,29 @@
-+extern void abort (void);
-+
-+int8x16x2_t
-+test_vzipqs8 (int8x16_t _a, int8x16_t _b)
-+{
-+  return vzipq_s8 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  int8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
-+  int8_t second[] =
-+      {17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32};
-+  int8x16x2_t result = test_vzipqs8 (vld1q_s8 (first), vld1q_s8 (second));
-+  int8x16_t res1 = result.val[0], res2 = result.val[1];
-+  int8_t exp1[] = {1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23, 8, 24};
-+  int8_t exp2[] =
-+      {9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31, 16, 32};
-+  int8x16_t expected1 = vld1q_s8 (exp1);
-+  int8x16_t expected2 = vld1q_s8 (exp2);
-+
-+  for (i = 0; i < 16; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu8.x
-@@ -0,0 +1,28 @@
-+extern void abort (void);
-+
-+uint8x16x2_t
-+test_vtrnqu8 (uint8x16_t _a, uint8x16_t _b)
-+{
-+  return vtrnq_u8 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  uint8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
-+  uint8_t second[] =
-+      {17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32};
-+  uint8x16x2_t result = test_vtrnqu8 (vld1q_u8 (first), vld1q_u8 (second));
-+  uint8x16_t res1 = result.val[0], res2 = result.val[1];
-+  uint8_t exp1[] = {1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31};
-+  uint8_t exp2[] = {2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30, 16, 32};
-+  uint8x16_t expected1 = vld1q_u8 (exp1);
-+  uint8x16_t expected2 = vld1q_u8 (exp2);
-+
-+  for (i = 0; i < 16; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/ext_s32.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/ext_s32.x
-@@ -0,0 +1,30 @@
-+extern void abort (void);
-+
-+int32x2_t
-+test_vext_s32_1 (int32x2_t a, int32x2_t b)
-+{
-+  return vext_s32 (a, b, 1);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i, off;
-+  int32_t arr1[] = {0, 1};
-+  int32x2_t in1 = vld1_s32 (arr1);
-+  int32_t arr2[] = {2, 3};
-+  int32x2_t in2 = vld1_s32 (arr2);
-+  int32_t exp[2];
-+  int32x2_t expected;
-+  int32x2_t actual = test_vext_s32_1 (in1, in2);
-+
-+  for (i = 0; i < 2; i++)
-+    exp[i] = i + 1;
-+  expected = vld1_s32 (exp);
-+  for (i = 0; i < 2; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzps16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzps16_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vuzp_s16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vuzps16.x"
-+
-+/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/ext_u32.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/ext_u32.x
-@@ -0,0 +1,30 @@
-+extern void abort (void);
-+
-+uint32x2_t
-+test_vext_u32_1 (uint32x2_t a, uint32x2_t b)
-+{
-+  return vext_u32 (a, b, 1);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i, off;
-+  uint32_t arr1[] = {0, 1};
-+  uint32x2_t in1 = vld1_u32 (arr1);
-+  uint32_t arr2[] = {2, 3};
-+  uint32x2_t in2 = vld1_u32 (arr2);
-+  uint32_t exp[2];
-+  uint32x2_t expected;
-+  uint32x2_t actual = test_vext_u32_1 (in1, in2);
-+
-+  for (i = 0; i < 2; i++)
-+    exp[i] = i + 1;
-+  expected = vld1_u32 (exp);
-+  for (i = 0; i < 2; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqs8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqs8_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vuzpq_s8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vuzpqs8.x"
-+
-+/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/extq_s8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/extq_s8.x
-@@ -0,0 +1,227 @@
-+extern void abort (void);
-+
-+int8x16_t
-+test_vextq_s8_1 (int8x16_t a, int8x16_t b)
-+{
-+  return vextq_s8 (a, b, 1);
-+}
-+
-+int8x16_t
-+test_vextq_s8_2 (int8x16_t a, int8x16_t b)
-+{
-+  return vextq_s8 (a, b, 2);
-+}
-+
-+int8x16_t
-+test_vextq_s8_3 (int8x16_t a, int8x16_t b)
-+{
-+  return vextq_s8 (a, b, 3);
-+}
-+
-+int8x16_t
-+test_vextq_s8_4 (int8x16_t a, int8x16_t b)
-+{
-+  return vextq_s8 (a, b, 4);
-+}
-+
-+int8x16_t
-+test_vextq_s8_5 (int8x16_t a, int8x16_t b)
-+{
-+  return vextq_s8 (a, b, 5);
-+}
-+
-+int8x16_t
-+test_vextq_s8_6 (int8x16_t a, int8x16_t b)
-+{
-+  return vextq_s8 (a, b, 6);
-+}
-+
-+int8x16_t
-+test_vextq_s8_7 (int8x16_t a, int8x16_t b)
-+{
-+  return vextq_s8 (a, b, 7);
-+}
-+
-+int8x16_t
-+test_vextq_s8_8 (int8x16_t a, int8x16_t b)
-+{
-+  return vextq_s8 (a, b, 8);
-+}
-+
-+int8x16_t
-+test_vextq_s8_9 (int8x16_t a, int8x16_t b)
-+{
-+  return vextq_s8 (a, b, 9);
-+}
-+
-+int8x16_t
-+test_vextq_s8_10 (int8x16_t a, int8x16_t b)
-+{
-+  return vextq_s8 (a, b, 10);
-+}
-+
-+int8x16_t
-+test_vextq_s8_11 (int8x16_t a, int8x16_t b)
-+{
-+  return vextq_s8 (a, b, 11);
-+}
-+
-+int8x16_t
-+test_vextq_s8_12 (int8x16_t a, int8x16_t b)
-+{
-+  return vextq_s8 (a, b, 12);
-+}
-+
-+int8x16_t
-+test_vextq_s8_13 (int8x16_t a, int8x16_t b)
-+{
-+  return vextq_s8 (a, b, 13);
-+}
-+
-+int8x16_t
-+test_vextq_s8_14 (int8x16_t a, int8x16_t b)
-+{
-+  return vextq_s8 (a, b, 14);
-+}
-+
-+int8x16_t
-+test_vextq_s8_15 (int8x16_t a, int8x16_t b)
-+{
-+  return vextq_s8 (a, b, 15);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  int8_t arr1[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
-+  int8x16_t in1 = vld1q_s8 (arr1);
-+  int8_t arr2[] =
-+      {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31};
-+  int8x16_t in2 = vld1q_s8 (arr2);
-+  int8_t exp[16];
-+  int8x16_t expected;
-+  int8x16_t actual = test_vextq_s8_1 (in1, in2);
-+
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 1;
-+  expected = vld1q_s8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_s8_2 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 2;
-+  expected = vld1q_s8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_s8_3 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 3;
-+  expected = vld1q_s8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_s8_4 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 4;
-+  expected = vld1q_s8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_s8_5 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 5;
-+  expected = vld1q_s8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_s8_6 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 6;
-+  expected = vld1q_s8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_s8_7 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 7;
-+  expected = vld1q_s8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_s8_8 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 8;
-+  expected = vld1q_s8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_s8_9 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 9;
-+  expected = vld1q_s8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_s8_10 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 10;
-+  expected = vld1q_s8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_s8_11 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 11;
-+  expected = vld1q_s8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_s8_12 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 12;
-+  expected = vld1q_s8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_s8_13 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 13;
-+  expected = vld1q_s8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_s8_14 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 14;
-+  expected = vld1q_s8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_s8_15 (in1, in2);
-+  for (i = 0; i < 16; i++)
-+    exp[i] = i + 15;
-+  expected = vld1q_s8 (exp);
-+  for (i = 0; i < 16; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/extq_f64_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/extq_f64_1.c
-@@ -0,0 +1,36 @@
-+/* Test the `vextq_f64' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+
-+#include "arm_neon.h"
-+extern void abort (void);
-+#include <stdio.h>
-+
-+float64x2_t
-+test_vextq_f64_1 (float64x2_t a, float64x2_t b)
-+{
-+  return vextq_f64 (a, b, 1);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i, off;
-+  float64_t arr1[] = {0, 1};
-+  float64x2_t in1 = vld1q_f64 (arr1);
-+  float64_t arr2[] = {2, 3};
-+  float64x2_t in2 = vld1q_f64 (arr2);
-+  float64_t exp[] = {1, 2};
-+  float64x2_t expected = vld1q_f64 (exp);
-+  float64x2_t actual = test_vextq_f64_1 (in1, in2);
-+
-+  for (i = 0; i < 2; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  return 0;
-+}
-+
-+/* { dg-final { scan-assembler-times "ext\[ \t\]+\[vV\]\[0-9\]+\.16\[bB\], ?\[vV\]\[0-9\]+\.16\[bB\], ?\[vV\]\[0-9\]+\.16\[bB\], ?#\[0-9\]+\(?:.8\)?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_f64.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_f64.c
-@@ -0,0 +1,27 @@
-+/* Test the vpaddd_f64 AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -O3" } */
-+
-+#include "arm_neon.h"
-+
-+#define SIZE 6
-+
-+extern void abort (void);
-+
-+float64_t in[SIZE] = { -4.0, 4.0, -2.0, 2.0, -1.0, 1.0 };
-+
-+int
-+main (void)
-+{
-+  int i;
-+
-+  for (i = 0; i < SIZE / 2; ++i)
-+    if (vpaddd_f64 (vld1q_f64 (in + 2 * i)) != 0.0)
-+      abort ();
-+
-+  return 0;
-+}
-+
-+/* { dg-final { scan-assembler "faddp\[ \t\]+\[dD\]\[0-9\]+, v\[0-9\].2d+\n" } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32qs16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32qs16_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev32q_s16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev32qs16.x"
-+
-+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.8h, ?v\[0-9\]+.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqs16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqs16_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vzipq_s16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vzipqs16.x"
-+
-+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzipf32_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzipf32_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vzip_f32' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vzipf32.x"
-+
-+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev16p8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev16p8.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+poly8x8_t
-+test_vrev16p8 (poly8x8_t _arg)
-+{
-+  return vrev16_p8 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  poly8x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
-+  poly8x8_t reversed = test_vrev16p8 (inorder);
-+  poly8x8_t expected = {2, 1, 4, 3, 6, 5, 8, 7};
-+
-+  for (i = 0; i < 8; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev16u8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev16u8_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev16_u8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev16u8.x"
-+
-+/* { dg-final { scan-assembler-times "rev16\[ \t\]+v\[0-9\]+.8b, ?v\[0-9\]+.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/ext_p8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/ext_p8_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vextp8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+
-+#include "arm_neon.h"
-+#include "ext_p8.x"
-+
-+/* { dg-final { scan-assembler-times "ext\[ \t\]+\[vV\]\[0-9\]+\.8\[bB\], ?\[vV\]\[0-9\]+\.8\[bB\], ?\[vV\]\[0-9\]+\.8\[bB\], ?#?\[0-9\]+\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 7 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrns8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrns8.x
-@@ -0,0 +1,27 @@
-+extern void abort (void);
-+
-+int8x8x2_t
-+test_vtrns8 (int8x8_t _a, int8x8_t _b)
-+{
-+  return vtrn_s8 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  int8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
-+  int8_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
-+  int8x8x2_t result = test_vtrns8 (vld1_s8 (first), vld1_s8 (second));
-+  int8x8_t res1 = result.val[0], res2 = result.val[1];
-+  int8_t exp1[] = {1, 9, 3, 11, 5, 13, 7, 15};
-+  int8_t exp2[] = {2, 10, 4, 12, 6, 14, 8, 16};
-+  int8x8_t expected1 = vld1_s8 (exp1);
-+  int8x8_t expected2 = vld1_s8 (exp2);
-+
-+  for (i = 0; i < 8; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs16.x
-@@ -0,0 +1,27 @@
-+extern void abort (void);
-+
-+int16x8x2_t
-+test_vtrnqs16 (int16x8_t _a, int16x8_t _b)
-+{
-+  return vtrnq_s16 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  int16_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
-+  int16_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
-+  int16x8x2_t result = test_vtrnqs16 (vld1q_s16 (first), vld1q_s16 (second));
-+  int16x8_t res1 = result.val[0], res2 = result.val[1];
-+  int16_t exp1[] = {1, 9, 3, 11, 5, 13, 7, 15};
-+  int16_t exp2[] = {2, 10, 4, 12, 6, 14, 8, 16};
-+  int16x8_t expected1 = vld1q_s16 (exp1);
-+  int16x8_t expected2 = vld1q_s16 (exp2);
-+
-+  for (i = 0; i < 8; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu16.x
-@@ -0,0 +1,27 @@
-+extern void abort (void);
-+
-+uint16x8x2_t
-+test_vtrnqu16 (uint16x8_t _a, uint16x8_t _b)
-+{
-+  return vtrnq_u16 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  uint16_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
-+  uint16_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
-+  uint16x8x2_t result = test_vtrnqu16 (vld1q_u16 (first), vld1q_u16 (second));
-+  uint16x8_t res1 = result.val[0], res2 = result.val[1];
-+  uint16_t exp1[] = {1, 9, 3, 11, 5, 13, 7, 15};
-+  uint16_t exp2[] = {2, 10, 4, 12, 6, 14, 8, 16};
-+  uint16x8_t expected1 = vld1q_u16 (exp1);
-+  uint16x8_t expected2 = vld1q_u16 (exp2);
-+
-+  for (i = 0; i < 8; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/extq_p16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/extq_p16.x
-@@ -0,0 +1,114 @@
-+extern void abort (void);
-+
-+poly16x8_t
-+test_vextq_p16_1 (poly16x8_t a, poly16x8_t b)
-+{
-+  return vextq_p16 (a, b, 1);
-+}
-+
-+poly16x8_t
-+test_vextq_p16_2 (poly16x8_t a, poly16x8_t b)
-+{
-+  return vextq_p16 (a, b, 2);
-+}
-+
-+poly16x8_t
-+test_vextq_p16_3 (poly16x8_t a, poly16x8_t b)
-+{
-+  return vextq_p16 (a, b, 3);
-+}
-+
-+poly16x8_t
-+test_vextq_p16_4 (poly16x8_t a, poly16x8_t b)
-+{
-+  return vextq_p16 (a, b, 4);
-+}
-+
-+poly16x8_t
-+test_vextq_p16_5 (poly16x8_t a, poly16x8_t b)
-+{
-+  return vextq_p16 (a, b, 5);
-+}
-+
-+poly16x8_t
-+test_vextq_p16_6 (poly16x8_t a, poly16x8_t b)
-+{
-+  return vextq_p16 (a, b, 6);
-+}
-+
-+poly16x8_t
-+test_vextq_p16_7 (poly16x8_t a, poly16x8_t b)
-+{
-+  return vextq_p16 (a, b, 7);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i, off;
-+  poly16_t arr1[] = {0, 1, 2, 3, 4, 5, 6, 7};
-+  poly16x8_t in1 = vld1q_p16 (arr1);
-+  poly16_t arr2[] = {8, 9, 10, 11, 12, 13, 14, 15};
-+  poly16x8_t in2 = vld1q_p16 (arr2);
-+  poly16_t exp[8];
-+  poly16x8_t expected;
-+  poly16x8_t actual = test_vextq_p16_1 (in1, in2);
-+
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 1;
-+  expected = vld1q_p16 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_p16_2 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 2;
-+  expected = vld1q_p16 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_p16_3 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 3;
-+  expected = vld1q_p16 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_p16_4 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 4;
-+  expected = vld1q_p16 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_p16_5 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 5;
-+  expected = vld1q_p16 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_p16_6 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 6;
-+  expected = vld1q_p16 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_p16_7 (in1, in2);
-+  for (i = 0; i < 8; i++)
-+    exp[i] = i + 7;
-+  expected = vld1q_p16 (exp);
-+  for (i = 0; i < 8; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qs16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qs16.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+int16x8_t
-+test_vrev64qs16 (int16x8_t _arg)
-+{
-+  return vrev64q_s16 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  int16x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
-+  int16x8_t reversed = test_vrev64qs16 (inorder);
-+  int16x8_t expected = {4, 3, 2, 1, 8, 7, 6, 5};
-+
-+  for (i = 0; i < 8; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qu16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qu16.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+uint16x8_t
-+test_vrev64qu16 (uint16x8_t _arg)
-+{
-+  return vrev64q_u16 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  uint16x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
-+  uint16x8_t reversed = test_vrev64qu16 (inorder);
-+  uint16x8_t expected = {4, 3, 2, 1, 8, 7, 6, 5};
-+
-+  for (i = 0; i < 8; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64u8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64u8.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+uint8x8_t
-+test_vrev64u8 (uint8x8_t _arg)
-+{
-+  return vrev64_u8 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  uint8x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
-+  uint8x8_t reversed = test_vrev64u8 (inorder);
-+  uint8x8_t expected = {8, 7, 6, 5, 4, 3, 2, 1};
-+
-+  for (i = 0; i < 8; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqp16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqp16.x
-@@ -0,0 +1,26 @@
-+extern void abort (void);
-+
-+poly16x8x2_t
-+test_vuzpqp16 (poly16x8_t _a, poly16x8_t _b)
-+{
-+  return vuzpq_p16 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  poly16_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
-+  poly16_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
-+  poly16x8x2_t result = test_vuzpqp16 (vld1q_p16 (first), vld1q_p16 (second));
-+  poly16_t exp1[] = {1, 3, 5, 7, 9, 11, 13, 15};
-+  poly16_t exp2[] = {2, 4, 6, 8, 10, 12, 14, 16};
-+  poly16x8_t expect1 = vld1q_p16 (exp1);
-+  poly16x8_t expect2 = vld1q_p16 (exp2);
-+
-+  for (i = 0; i < 8; i++)
-+    if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrns16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrns16_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vtrn_s16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vtrns16.x"
-+
-+/* { dg-final { scan-assembler-times "trn1\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "trn2\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpf32.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpf32.x
-@@ -0,0 +1,26 @@
-+extern void abort (void);
-+
-+float32x2x2_t
-+test_vuzpf32 (float32x2_t _a, float32x2_t _b)
-+{
-+  return vuzp_f32 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  float32_t first[] = {1, 2};
-+  float32_t second[] = {3, 4};
-+  float32x2x2_t result = test_vuzpf32 (vld1_f32 (first), vld1_f32 (second));
-+  float32_t exp1[] = {1, 3};
-+  float32_t exp2[] = {2, 4};
-+  float32x2_t expect1 = vld1_f32 (exp1);
-+  float32x2_t expect2 = vld1_f32 (exp2);
-+
-+  for (i = 0; i < 2; i++)
-+    if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzipu16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzipu16_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vzip_u16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vzipu16.x"
-+
-+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqf32_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqf32_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vtrnq_f32' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vtrnqf32.x"
-+
-+/* { dg-final { scan-assembler-times "trn1\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "trn2\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs8_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vtrnq_s8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vtrnqs8.x"
-+
-+/* { dg-final { scan-assembler-times "trn1\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "trn2\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqp8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqp8.x
-@@ -0,0 +1,28 @@
-+extern void abort (void);
-+
-+poly8x16x2_t
-+test_vtrnqp8 (poly8x16_t _a, poly8x16_t _b)
-+{
-+  return vtrnq_p8 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  poly8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
-+  poly8_t second[] =
-+      {17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32};
-+  poly8x16x2_t result = test_vtrnqp8 (vld1q_p8 (first), vld1q_p8 (second));
-+  poly8x16_t res1 = result.val[0], res2 = result.val[1];
-+  poly8_t exp1[] = {1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31};
-+  poly8_t exp2[] = {2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30, 16, 32};
-+  poly8x16_t expected1 = vld1q_p8 (exp1);
-+  poly8x16_t expected2 = vld1q_p8 (exp2);
-+
-+  for (i = 0; i < 16; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64s32.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64s32.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+int32x2_t
-+test_vrev64s32 (int32x2_t _arg)
-+{
-+  return vrev64_s32 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  int32x2_t inorder = {1, 2};
-+  int32x2_t reversed = test_vrev64s32 (inorder);
-+  int32x2_t expected = {2, 1};
-+
-+  for (i = 0; i < 2; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/ext_s16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/ext_s16_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vexts16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+
-+#include "arm_neon.h"
-+#include "ext_s16.x"
-+
-+/* { dg-final { scan-assembler-times "ext\[ \t\]+\[vV\]\[0-9\]+\.8\[bB\], ?\[vV\]\[0-9\]+\.8\[bB\], ?\[vV\]\[0-9\]+\.8\[bB\], ?#\[0-9\]+\(?:.2\)?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 3 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32qu8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32qu8.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+uint8x16_t
-+test_vrev32qu8 (uint8x16_t _arg)
-+{
-+  return vrev32q_u8 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  uint8x16_t inorder = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
-+  uint8x16_t reversed = test_vrev32qu8 (inorder);
-+  uint8x16_t expected = {4, 3, 2, 1, 8, 7, 6, 5, 12, 11, 10, 9, 16, 15, 14, 13};
-+
-+  for (i = 0; i < 16; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64u32.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64u32.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+uint32x2_t
-+test_vrev64u32 (uint32x2_t _arg)
-+{
-+  return vrev64_u32 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  uint32x2_t inorder = {1, 2};
-+  uint32x2_t reversed = test_vrev64u32 (inorder);
-+  uint32x2_t expected = {2, 1};
-+
-+  for (i = 0; i < 2; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/extq_f32_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/extq_f32_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vextQf32' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+
-+#include "arm_neon.h"
-+#include "extq_f32.x"
-+
-+/* { dg-final { scan-assembler-times "ext\[ \t\]+\[vV\]\[0-9\]+\.16\[bB\], ?\[vV\]\[0-9\]+\.16\[bB\], ?\[vV\]\[0-9\]+\.16\[bB\], ?#\[0-9\]+\(?:.4)?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 3 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev16qu8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev16qu8.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+uint8x16_t
-+test_vrev16qu8 (uint8x16_t _arg)
-+{
-+  return vrev16q_u8 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  uint8x16_t inorder = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
-+  uint8x16_t reversed = test_vrev16qu8 (inorder);
-+  uint8x16_t expected = {2, 1, 4, 3, 6, 5, 8, 7, 10, 9, 12, 11, 14, 13, 16, 15};
-+
-+  for (i = 0; i < 16; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqp8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqp8_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vuzpq_p8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vuzpqp8.x"
-+
-+/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qp16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qp16_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev64q_p16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev64qp16.x"
-+
-+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.8h, ?v\[0-9\]+.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqp16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqp16.x
-@@ -0,0 +1,27 @@
-+extern void abort (void);
-+
-+poly16x8x2_t
-+test_vzipqp16 (poly16x8_t _a, poly16x8_t _b)
-+{
-+  return vzipq_p16 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  poly16_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
-+  poly16_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
-+  poly16x8x2_t result = test_vzipqp16 (vld1q_p16 (first), vld1q_p16 (second));
-+  poly16x8_t res1 = result.val[0], res2 = result.val[1];
-+  poly16_t exp1[] = {1, 9, 2, 10, 3, 11, 4, 12};
-+  poly16_t exp2[] = {5, 13, 6, 14, 7, 15, 8, 16};
-+  poly16x8_t expected1 = vld1q_p16 (exp1);
-+  poly16x8_t expected2 = vld1q_p16 (exp2);
-+
-+  for (i = 0; i < 8; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu16_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vtrnq_u16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vtrnqu16.x"
-+
-+/* { dg-final { scan-assembler-times "trn1\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "trn2\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qu32_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qu32_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev64q_u32' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev64qu32.x"
-+
-+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.4s, ?v\[0-9\]+.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqu8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqu8.x
-@@ -0,0 +1,27 @@
-+extern void abort (void);
-+
-+uint8x16x2_t
-+test_vuzpqu8 (uint8x16_t _a, uint8x16_t _b)
-+{
-+  return vuzpq_u8 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  uint8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
-+  uint8_t second[] =
-+      {17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32};
-+  uint8x16x2_t result = test_vuzpqu8 (vld1q_u8 (first), vld1q_u8 (second));
-+  uint8_t exp1[] = {1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31};
-+  uint8_t exp2[] = {2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32};
-+  uint8x16_t expect1 = vld1q_u8 (exp1);
-+  uint8x16_t expect2 = vld1q_u8 (exp2);
-+
-+  for (i = 0; i < 16; i++)
-+    if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64p8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64p8.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+poly8x8_t
-+test_vrev64p8 (poly8x8_t _arg)
-+{
-+  return vrev64_p8 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  poly8x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
-+  poly8x8_t reversed = test_vrev64p8 (inorder);
-+  poly8x8_t expected = {8, 7, 6, 5, 4, 3, 2, 1};
-+
-+  for (i = 0; i < 8; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32u8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32u8.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+uint8x8_t
-+test_vrev32u8 (uint8x8_t _arg)
-+{
-+  return vrev32_u8 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  uint8x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
-+  uint8x8_t reversed = test_vrev32u8 (inorder);
-+  uint8x8_t expected = {4, 3, 2, 1, 8, 7, 6, 5};
-+
-+  for (i = 0; i < 8; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev16s8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev16s8.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+int8x8_t
-+test_vrev16s8 (int8x8_t _arg)
-+{
-+  return vrev16_s8 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  int8x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
-+  int8x8_t reversed = test_vrev16s8 (inorder);
-+  int8x8_t expected = {2, 1, 4, 3, 6, 5, 8, 7};
-+
-+  for (i = 0; i < 8; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/ext_u8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/ext_u8_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vextu8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+
-+#include "arm_neon.h"
-+#include "ext_u8.x"
-+
-+/* { dg-final { scan-assembler-times "ext\[ \t\]+\[vV\]\[0-9\]+\.8\[bB\], ?\[vV\]\[0-9\]+\.8\[bB\], ?\[vV\]\[0-9\]+\.8\[bB\], ?#?\[0-9\]+\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 7 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/extq_u16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/extq_u16_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vextQu16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+
-+#include "arm_neon.h"
-+#include "extq_u16.x"
-+
-+/* { dg-final { scan-assembler-times "ext\[ \t\]+\[vV\]\[0-9\]+\.16\[bB\], ?\[vV\]\[0-9\]+\.16\[bB\], ?\[vV\]\[0-9\]+\.16\[bB\], ?#\[0-9\]+\(?:.2\)?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 7 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/int_comparisons.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/int_comparisons.x
-@@ -0,0 +1,68 @@
-+/*  test_vcXXX wrappers for all the vcXXX (vector compare) and vtst intrinsics
-+    in arm_neon.h (excluding the 64x1 variants as these generally produce scalar
-+    not vector ops).  */
-+#include "arm_neon.h"
-+
-+#define DONT_FORCE(X)
-+
-+#define FORCE_SIMD(V1)   asm volatile ("mov %d0, %1.d[0]"       \
-+           : "=w"(V1)                                           \
-+           : "w"(V1)                                            \
-+           : /* No clobbers */);
-+
-+#define OP1(SIZE, OP, BASETYPE, SUFFIX, FORCE) uint##SIZE##_t	\
-+test_v##OP##SUFFIX (BASETYPE##SIZE##_t a)			\
-+{								\
-+  uint##SIZE##_t res;						\
-+  FORCE (a);							\
-+  res = v##OP##SUFFIX (a);					\
-+  FORCE (res);							\
-+  return res;							\
-+}
-+
-+#define OP2(SIZE, OP, BASETYPE, SUFFIX, FORCE) uint##SIZE##_t	\
-+test_v##OP##SUFFIX (BASETYPE##SIZE##_t a, BASETYPE##SIZE##_t b) \
-+{								\
-+  uint##SIZE##_t res;						\
-+  FORCE (a);							\
-+  FORCE (b);							\
-+  res = v##OP##SUFFIX (a, b);					\
-+  FORCE (res);							\
-+  return res;							\
-+}
-+
-+#define UNSIGNED_OPS(SIZE, BASETYPE, SUFFIX, FORCE) \
-+OP2 (SIZE, tst, BASETYPE, SUFFIX, FORCE) \
-+OP1 (SIZE, ceqz, BASETYPE, SUFFIX, FORCE) \
-+OP2 (SIZE, ceq, BASETYPE, SUFFIX, FORCE) \
-+OP2 (SIZE, cge, BASETYPE, SUFFIX, FORCE) \
-+OP2 (SIZE, cgt, BASETYPE, SUFFIX, FORCE) \
-+OP2 (SIZE, cle, BASETYPE, SUFFIX, FORCE) \
-+OP2 (SIZE, clt, BASETYPE, SUFFIX, FORCE)
-+
-+#define ALL_OPS(SIZE, BASETYPE, SUFFIX, FORCE) \
-+OP1 (SIZE, cgez, BASETYPE, SUFFIX, FORCE) \
-+OP1 (SIZE, cgtz, BASETYPE, SUFFIX, FORCE) \
-+OP1 (SIZE, clez, BASETYPE, SUFFIX, FORCE) \
-+OP1 (SIZE, cltz, BASETYPE, SUFFIX, FORCE) \
-+UNSIGNED_OPS (SIZE, BASETYPE, SUFFIX, FORCE)
-+
-+ALL_OPS (8x8, int, _s8, DONT_FORCE)
-+ALL_OPS (16x4, int, _s16, DONT_FORCE)
-+ALL_OPS (32x2, int, _s32, DONT_FORCE)
-+ALL_OPS (64x1, int, _s64, DONT_FORCE)
-+ALL_OPS (64, int, d_s64, FORCE_SIMD)
-+ALL_OPS (8x16, int, q_s8, DONT_FORCE)
-+ALL_OPS (16x8, int, q_s16, DONT_FORCE)
-+ALL_OPS (32x4, int, q_s32, DONT_FORCE)
-+ALL_OPS (64x2, int, q_s64, DONT_FORCE)
-+UNSIGNED_OPS (8x8, uint, _u8, DONT_FORCE)
-+UNSIGNED_OPS (16x4, uint, _u16, DONT_FORCE)
-+UNSIGNED_OPS (32x2, uint, _u32, DONT_FORCE)
-+UNSIGNED_OPS (64x1, uint, _u64, DONT_FORCE)
-+UNSIGNED_OPS (64, uint, d_u64, FORCE_SIMD)
-+UNSIGNED_OPS (8x16, uint, q_u8, DONT_FORCE)
-+UNSIGNED_OPS (16x8, uint, q_u16, DONT_FORCE)
-+UNSIGNED_OPS (32x4, uint, q_u32, DONT_FORCE)
-+UNSIGNED_OPS (64x2, uint, q_u64, DONT_FORCE)
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqs32_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqs32_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vuzpq_s32' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vuzpqs32.x"
-+
-+/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzps8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzps8_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vuzp_s8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vuzps8.x"
-+
-+/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqp8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqp8_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vtrnq_p8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vtrnqp8.x"
-+
-+/* { dg-final { scan-assembler-times "trn1\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "trn2\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64p16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64p16_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev64_p16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev64p16.x"
-+
-+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.4h, ?v\[0-9\]+.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32u16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32u16_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev32_u16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev32u16.x"
-+
-+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.4h, ?v\[0-9\]+.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32qp8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32qp8.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+poly8x16_t
-+test_vrev32qp8 (poly8x16_t _arg)
-+{
-+  return vrev32q_p8 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  poly8x16_t inorder = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
-+  poly8x16_t reversed = test_vrev32qp8 (inorder);
-+  poly8x16_t expected = {4, 3, 2, 1, 8, 7, 6, 5, 12, 11, 10, 9, 16, 15, 14, 13};
-+
-+  for (i = 0; i < 16; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev16qs8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev16qs8_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev16q_s8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev16qs8.x"
-+
-+/* { dg-final { scan-assembler-times "rev16\[ \t\]+v\[0-9\]+.16b, ?v\[0-9\]+.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnp16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnp16.x
-@@ -0,0 +1,27 @@
-+extern void abort (void);
-+
-+poly16x4x2_t
-+test_vtrnp16 (poly16x4_t _a, poly16x4_t _b)
-+{
-+  return vtrn_p16 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  poly16_t first[] = {1, 2, 3, 4};
-+  poly16_t second[] = {5, 6, 7, 8};
-+  poly16x4x2_t result = test_vtrnp16 (vld1_p16 (first), vld1_p16 (second));
-+  poly16x4_t res1 = result.val[0], res2 = result.val[1];
-+  poly16_t exp1[] = {1, 5, 3, 7};
-+  poly16_t exp2[] = {2, 6, 4, 8};
-+  poly16x4_t expected1 = vld1_p16 (exp1);
-+  poly16x4_t expected2 = vld1_p16 (exp2);
-+
-+  for (i = 0; i < 4; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzips32.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzips32.x
-@@ -0,0 +1,27 @@
-+extern void abort (void);
-+
-+int32x2x2_t
-+test_vzips32 (int32x2_t _a, int32x2_t _b)
-+{
-+  return vzip_s32 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  int32_t first[] = {1, 2};
-+  int32_t second[] = {3, 4};
-+  int32x2x2_t result = test_vzips32 (vld1_s32 (first), vld1_s32 (second));
-+  int32x2_t res1 = result.val[0], res2 = result.val[1];
-+  int32_t exp1[] = {1, 3};
-+  int32_t exp2[] = {2, 4};
-+  int32x2_t expected1 = vld1_s32 (exp1);
-+  int32x2_t expected2 = vld1_s32 (exp2);
-+
-+  for (i = 0; i < 2; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64u32_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64u32_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev64_u32' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev64u32.x"
-+
-+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.2s, ?v\[0-9\]+.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev16qp8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev16qp8.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+poly8x16_t
-+test_vrev16qp8 (poly8x16_t _arg)
-+{
-+  return vrev16q_p8 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  poly8x16_t inorder = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
-+  poly8x16_t reversed = test_vrev16qp8 (inorder);
-+  poly8x16_t expected = {2, 1, 4, 3, 6, 5, 8, 7, 10, 9, 12, 11, 14, 13, 16, 15};
-+
-+  for (i = 0; i < 16; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzipu32.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzipu32.x
-@@ -0,0 +1,27 @@
-+extern void abort (void);
-+
-+uint32x2x2_t
-+test_vzipu32 (uint32x2_t _a, uint32x2_t _b)
-+{
-+  return vzip_u32 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  uint32_t first[] = {1, 2};
-+  uint32_t second[] = {3, 4};
-+  uint32x2x2_t result = test_vzipu32 (vld1_u32 (first), vld1_u32 (second));
-+  uint32x2_t res1 = result.val[0], res2 = result.val[1];
-+  uint32_t exp1[] = {1, 3};
-+  uint32_t exp2[] = {2, 4};
-+  uint32x2_t expected1 = vld1_u32 (exp1);
-+  uint32x2_t expected2 = vld1_u32 (exp2);
-+
-+  for (i = 0; i < 2; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqf32.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqf32.x
-@@ -0,0 +1,27 @@
-+extern void abort (void);
-+
-+float32x4x2_t
-+test_vtrnqf32 (float32x4_t _a, float32x4_t _b)
-+{
-+  return vtrnq_f32 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  float32_t first[] = {1, 2, 3, 4};
-+  float32_t second[] = {5, 6, 7, 8};
-+  float32x4x2_t result = test_vtrnqf32 (vld1q_f32 (first), vld1q_f32 (second));
-+  float32x4_t res1 = result.val[0], res2 = result.val[1];
-+  float32_t exp1[] = {1, 5, 3, 7};
-+  float32_t exp2[] = {2, 6, 4, 8};
-+  float32x4_t expected1 = vld1q_f32 (exp1);
-+  float32x4_t expected2 = vld1q_f32 (exp2);
-+
-+  for (i = 0; i < 4; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs8.x
-@@ -0,0 +1,28 @@
-+extern void abort (void);
-+
-+int8x16x2_t
-+test_vtrnqs8 (int8x16_t _a, int8x16_t _b)
-+{
-+  return vtrnq_s8 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  int8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
-+  int8_t second[] =
-+      {17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32};
-+  int8x16x2_t result = test_vtrnqs8 (vld1q_s8 (first), vld1q_s8 (second));
-+  int8x16_t res1 = result.val[0], res2 = result.val[1];
-+  int8_t exp1[] = {1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31};
-+  int8_t exp2[] = {2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30, 16, 32};
-+  int8x16_t expected1 = vld1q_s8 (exp1);
-+  int8x16_t expected2 = vld1q_s8 (exp2);
-+
-+  for (i = 0; i < 16; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/ext_s64_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/ext_s64_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vexts64' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+
-+#include "arm_neon.h"
-+#include "ext_s64.x"
-+
-+/* Do not scan-assembler.  An EXT instruction could be emitted, but would merely
-+   return its first argument, so it is legitimate to optimize it out.  */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzps32_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzps32_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vuzp_s32' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vuzps32.x"
-+
-+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qf32.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qf32.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+float32x4_t
-+test_vrev64qf32 (float32x4_t _arg)
-+{
-+  return vrev64q_f32 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  float32x4_t inorder = {1, 2, 3, 4};
-+  float32x4_t reversed = test_vrev64qf32 (inorder);
-+  float32x4_t expected = {2, 1, 4, 3};
-+
-+  for (i = 0; i < 4; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/ext_s16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/ext_s16.x
-@@ -0,0 +1,58 @@
-+extern void abort (void);
-+
-+int16x4_t
-+test_vext_s16_1 (int16x4_t a, int16x4_t b)
-+{
-+  return vext_s16 (a, b, 1);
-+}
-+
-+int16x4_t
-+test_vext_s16_2 (int16x4_t a, int16x4_t b)
-+{
-+  return vext_s16 (a, b, 2);
-+}
-+
-+int16x4_t
-+test_vext_s16_3 (int16x4_t a, int16x4_t b)
-+{
-+  return vext_s16 (a, b, 3);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i, off;
-+  int16_t arr1[] = {0, 1, 2, 3};
-+  int16x4_t in1 = vld1_s16 (arr1);
-+  int16_t arr2[] = {4, 5, 6, 7};
-+  int16x4_t in2 = vld1_s16 (arr2);
-+  int16_t exp[4];
-+  int16x4_t expected;
-+  int16x4_t actual = test_vext_s16_1 (in1, in2);
-+
-+  for (i = 0; i < 4; i++)
-+    exp[i] = i + 1;
-+  expected = vld1_s16 (exp);
-+  for (i = 0; i < 4; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vext_s16_2 (in1, in2);
-+  for (i = 0; i < 4; i++)
-+    exp[i] = i + 2;
-+  expected = vld1_s16 (exp);
-+  for (i = 0; i < 4; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vext_s16_3 (in1, in2);
-+  for (i = 0; i < 4; i++)
-+    exp[i] = i + 3;
-+  expected = vld1_s16 (exp);
-+  for (i = 0; i < 4; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/ext_u16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/ext_u16.x
-@@ -0,0 +1,58 @@
-+extern void abort (void);
-+
-+uint16x4_t
-+test_vext_u16_1 (uint16x4_t a, uint16x4_t b)
-+{
-+  return vext_u16 (a, b, 1);
-+}
-+
-+uint16x4_t
-+test_vext_u16_2 (uint16x4_t a, uint16x4_t b)
-+{
-+  return vext_u16 (a, b, 2);
-+}
-+
-+uint16x4_t
-+test_vext_u16_3 (uint16x4_t a, uint16x4_t b)
-+{
-+  return vext_u16 (a, b, 3);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i, off;
-+  uint16_t arr1[] = {0, 1, 2, 3};
-+  uint16x4_t in1 = vld1_u16 (arr1);
-+  uint16_t arr2[] = {4, 5, 6, 7};
-+  uint16x4_t in2 = vld1_u16 (arr2);
-+  uint16_t exp[4];
-+  uint16x4_t expected;
-+  uint16x4_t actual = test_vext_u16_1 (in1, in2);
-+
-+  for (i = 0; i < 4; i++)
-+    exp[i] = i + 1;
-+  expected = vld1_u16 (exp);
-+  for (i = 0; i < 4; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vext_u16_2 (in1, in2);
-+  for (i = 0; i < 4; i++)
-+    exp[i] = i + 2;
-+  expected = vld1_u16 (exp);
-+  for (i = 0; i < 4; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vext_u16_3 (in1, in2);
-+  for (i = 0; i < 4; i++)
-+    exp[i] = i + 3;
-+  expected = vld1_u16 (exp);
-+  for (i = 0; i < 4; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqs32_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqs32_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vzipq_s32' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vzipqs32.x"
-+
-+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqp8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqp8.x
-@@ -0,0 +1,27 @@
-+extern void abort (void);
-+
-+poly8x16x2_t
-+test_vuzpqp8 (poly8x16_t _a, poly8x16_t _b)
-+{
-+  return vuzpq_p8 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  poly8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
-+  poly8_t second[] =
-+      {17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32};
-+  poly8x16x2_t result = test_vuzpqp8 (vld1q_p8 (first), vld1q_p8 (second));
-+  poly8_t exp1[] = {1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31};
-+  poly8_t exp2[] = {2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32};
-+  poly8x16_t expect1 = vld1q_p8 (exp1);
-+  poly8x16_t expect2 = vld1q_p8 (exp2);
-+
-+  for (i = 0; i < 16; i++)
-+    if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqu8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqu8_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vuzpq_u8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vuzpqu8.x"
-+
-+/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzips8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzips8_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vzip_s8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vzips8.x"
-+
-+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32p8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32p8.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+poly8x8_t
-+test_vrev32p8 (poly8x8_t _arg)
-+{
-+  return vrev32_p8 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  poly8x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
-+  poly8x8_t reversed = test_vrev32p8 (inorder);
-+  poly8x8_t expected = {4, 3, 2, 1, 8, 7, 6, 5};
-+
-+  for (i = 0; i < 8; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64s8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64s8.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+int8x8_t
-+test_vrev64s8 (int8x8_t _arg)
-+{
-+  return vrev64_s8 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  int8x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
-+  int8x8_t reversed = test_vrev64s8 (inorder);
-+  int8x8_t expected = {8, 7, 6, 5, 4, 3, 2, 1};
-+
-+  for (i = 0; i < 8; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpp8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpp8_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vuzp_p8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vuzpp8.x"
-+
-+/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/extq_s32.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/extq_s32.x
-@@ -0,0 +1,58 @@
-+extern void abort (void);
-+
-+int32x4_t
-+test_vextq_s32_1 (int32x4_t a, int32x4_t b)
-+{
-+  return vextq_s32 (a, b, 1);
-+}
-+
-+int32x4_t
-+test_vextq_s32_2 (int32x4_t a, int32x4_t b)
-+{
-+  return vextq_s32 (a, b, 2);
-+}
-+
-+int32x4_t
-+test_vextq_s32_3 (int32x4_t a, int32x4_t b)
-+{
-+  return vextq_s32 (a, b, 3);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i, off;
-+  int32_t arr1[] = {0, 1, 2, 3};
-+  int32x4_t in1 = vld1q_s32 (arr1);
-+  int32_t arr2[] = {4, 5, 6, 7};
-+  int32x4_t in2 = vld1q_s32 (arr2);
-+  int32_t exp[4];
-+  int32x4_t expected;
-+  int32x4_t actual = test_vextq_s32_1 (in1, in2);
-+
-+  for (i = 0; i < 4; i++)
-+    exp[i] = i + 1;
-+  expected = vld1q_s32 (exp);
-+  for (i = 0; i < 4; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_s32_2 (in1, in2);
-+  for (i = 0; i < 4; i++)
-+    exp[i] = i + 2;
-+  expected = vld1q_s32 (exp);
-+  for (i = 0; i < 4; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_s32_3 (in1, in2);
-+  for (i = 0; i < 4; i++)
-+    exp[i] = i + 3;
-+  expected = vld1q_s32 (exp);
-+  for (i = 0; i < 4; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/extq_u32.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/extq_u32.x
-@@ -0,0 +1,58 @@
-+extern void abort (void);
-+
-+uint32x4_t
-+test_vextq_u32_1 (uint32x4_t a, uint32x4_t b)
-+{
-+  return vextq_u32 (a, b, 1);
-+}
-+
-+uint32x4_t
-+test_vextq_u32_2 (uint32x4_t a, uint32x4_t b)
-+{
-+  return vextq_u32 (a, b, 2);
-+}
-+
-+uint32x4_t
-+test_vextq_u32_3 (uint32x4_t a, uint32x4_t b)
-+{
-+  return vextq_u32 (a, b, 3);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i, off;
-+  uint32_t arr1[] = {0, 1, 2, 3};
-+  uint32x4_t in1 = vld1q_u32 (arr1);
-+  uint32_t arr2[] = {4, 5, 6, 7};
-+  uint32x4_t in2 = vld1q_u32 (arr2);
-+  uint32_t exp[4];
-+  uint32x4_t expected;
-+  uint32x4_t actual = test_vextq_u32_1 (in1, in2);
-+
-+  for (i = 0; i < 4; i++)
-+    exp[i] = i + 1;
-+  expected = vld1q_u32 (exp);
-+  for (i = 0; i < 4; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_u32_2 (in1, in2);
-+  for (i = 0; i < 4; i++)
-+    exp[i] = i + 2;
-+  expected = vld1q_u32 (exp);
-+  for (i = 0; i < 4; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  actual = test_vextq_u32_3 (in1, in2);
-+  for (i = 0; i < 4; i++)
-+    exp[i] = i + 3;
-+  expected = vld1q_u32 (exp);
-+  for (i = 0; i < 4; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/extq_u64_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/extq_u64_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vextQu64' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+
-+#include "arm_neon.h"
-+#include "extq_u64.x"
-+
-+/* { dg-final { scan-assembler-times "ext\[ \t\]+\[vV\]\[0-9\]+\.16\[bB\], ?\[vV\]\[0-9\]+\.16\[bB\], ?\[vV\]\[0-9\]+\.16\[bB\], ?#\[0-9\]+\(?:.8\)?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzipp16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzipp16_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vzip_p16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vzipp16.x"
-+
-+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrns32_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrns32_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vtrn_s32' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vtrns32.x"
-+
-+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev16qp8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev16qp8_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev16q_p8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev16qp8.x"
-+
-+/* { dg-final { scan-assembler-times "rev16\[ \t\]+v\[0-9\]+.16b, ?v\[0-9\]+.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqs32.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqs32.x
-@@ -0,0 +1,26 @@
-+extern void abort (void);
-+
-+int32x4x2_t
-+test_vuzpqs32 (int32x4_t _a, int32x4_t _b)
-+{
-+  return vuzpq_s32 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  int32_t first[] = {1, 2, 3, 4};
-+  int32_t second[] = {5, 6, 7, 8};
-+  int32x4x2_t result = test_vuzpqs32 (vld1q_s32 (first), vld1q_s32 (second));
-+  int32_t exp1[] = {1, 3, 5, 7};
-+  int32_t exp2[] = {2, 4, 6, 8};
-+  int32x4_t expect1 = vld1q_s32 (exp1);
-+  int32x4_t expect2 = vld1q_s32 (exp2);
-+
-+  for (i = 0; i < 4; i++)
-+    if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzipu32_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzipu32_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vzip_u32' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vzipu32.x"
-+
-+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32p16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32p16.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+poly16x4_t
-+test_vrev32p16 (poly16x4_t _arg)
-+{
-+  return vrev32_p16 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  poly16x4_t inorder = {1, 2, 3, 4};
-+  poly16x4_t reversed = test_vrev32p16 (inorder);
-+  poly16x4_t expected = {2, 1, 4, 3};
-+
-+  for (i = 0; i < 4; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqu32.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqu32.x
-@@ -0,0 +1,26 @@
-+extern void abort (void);
-+
-+uint32x4x2_t
-+test_vuzpqu32 (uint32x4_t _a, uint32x4_t _b)
-+{
-+  return vuzpq_u32 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  uint32_t first[] = {1, 2, 3, 4};
-+  uint32_t second[] = {5, 6, 7, 8};
-+  uint32x4x2_t result = test_vuzpqu32 (vld1q_u32 (first), vld1q_u32 (second));
-+  uint32_t exp1[] = {1, 3, 5, 7};
-+  uint32_t exp2[] = {2, 4, 6, 8};
-+  uint32x4_t expect1 = vld1q_u32 (exp1);
-+  uint32x4_t expect2 = vld1q_u32 (exp2);
-+
-+  for (i = 0; i < 4; i++)
-+    if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrbit_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrbit_1.c
-@@ -0,0 +1,56 @@
-+/* { dg-do run } */
-+/* { dg-options "-O2 --save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+
-+extern void abort (void);
-+
-+uint64_t in1 = 0x0123456789abcdefULL;
-+uint64_t expected1 = 0x80c4a2e691d5b3f7ULL;
-+
-+#define TEST8(BASETYPE, SUFFIX)						\
-+void test8_##SUFFIX ()							\
-+{									\
-+  BASETYPE##8x8_t out = vrbit_##SUFFIX (vcreate_##SUFFIX (in1));	\
-+  uint64_t res = vget_lane_u64 (vreinterpret_u64_##SUFFIX (out), 0);	\
-+  if (res != expected1) abort ();					\
-+}
-+
-+uint64_t in2 = 0xdeadbeefcafebabeULL;
-+uint64_t expected2 = 0x7bb57df7537f5d7dULL;
-+
-+#define TEST16(BASETYPE, SUFFIX)					\
-+void test16_##SUFFIX ()							\
-+{									\
-+  BASETYPE##8x16_t in = vcombine_##SUFFIX (vcreate_##SUFFIX (in1),	\
-+					   vcreate_##SUFFIX (in2));	\
-+  uint64x2_t res = vreinterpretq_u64_##SUFFIX (vrbitq_##SUFFIX (in));	\
-+  uint64_t res1 = vgetq_lane_u64 (res, 0);				\
-+  uint64_t res2 = vgetq_lane_u64 (res, 1);				\
-+  if (res1 != expected1 || res2 != expected2) abort ();			\
-+}
-+
-+TEST8 (poly, p8);
-+TEST8 (int, s8);
-+TEST8 (uint, u8);
-+
-+TEST16 (poly, p8);
-+TEST16 (int, s8);
-+TEST16 (uint, u8);
-+
-+int
-+main (int argc, char **argv)
-+{
-+  test8_p8 ();
-+  test8_s8 ();
-+  test8_u8 ();
-+  test16_p8 ();
-+  test16_s8 ();
-+  test16_u8 ();
-+  return 0;
-+}
-+
-+/* { dg-final { scan-assembler-times "rbit\[ \t\]+\[vV\]\[0-9\]+\.8\[bB\], ?\[vV\]\[0-9\]+\.8\[bB\]" 3 } } */
-+/* { dg-final { scan-assembler-times "rbit\[ \t\]+\[vV\]\[0-9\]+\.16\[bB\], ?\[vV\]\[0-9\]+\.16\[bB\]" 3 } } */
-+
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/ext_s32_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/ext_s32_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vexts32' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+
-+#include "arm_neon.h"
-+#include "ext_s32.x"
-+
-+/* { dg-final { scan-assembler-times "ext\[ \t\]+\[vV\]\[0-9\]+\.8\[bB\], ?\[vV\]\[0-9\]+\.8\[bB\], ?\[vV\]\[0-9\]+\.8\[bB\], ?#\[0-9\]+\(?:.4)?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu8_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vtrnq_u8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vtrnqu8.x"
-+
-+/* { dg-final { scan-assembler-times "trn1\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "trn2\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32qs8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32qs8.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+int8x16_t
-+test_vrev32qs8 (int8x16_t _arg)
-+{
-+  return vrev32q_s8 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  int8x16_t inorder = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
-+  int8x16_t reversed = test_vrev32qs8 (inorder);
-+  int8x16_t expected = {4, 3, 2, 1, 8, 7, 6, 5, 12, 11, 10, 9, 16, 15, 14, 13};
-+
-+  for (i = 0; i < 16; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev16qs8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev16qs8.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+int8x16_t
-+test_vrev16qs8 (int8x16_t _arg)
-+{
-+  return vrev16q_s8 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  int8x16_t inorder = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
-+  int8x16_t reversed = test_vrev16qs8 (inorder);
-+  int8x16_t expected = {2, 1, 4, 3, 6, 5, 8, 7, 10, 9, 12, 11, 14, 13, 16, 15};
-+
-+  for (i = 0; i < 16; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64s16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64s16.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+int16x4_t
-+test_vrev64s16 (int16x4_t _arg)
-+{
-+  return vrev64_s16 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  int16x4_t inorder = {1, 2, 3, 4};
-+  int16x4_t reversed = test_vrev64s16 (inorder);
-+  int16x4_t expected = {4, 3, 2, 1};
-+
-+  for (i = 0; i < 4; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/extq_s8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/extq_s8_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vextQs8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+
-+#include "arm_neon.h"
-+#include "extq_s8.x"
-+
-+/* { dg-final { scan-assembler-times "ext\[ \t\]+\[vV\]\[0-9\]+\.16\[bB\], ?\[vV\]\[0-9\]+\.16\[bB\], ?\[vV\]\[0-9\]+\.16\[bB\], ?#?\[0-9\]+\(?:.2\)?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 15 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64u16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64u16.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+uint16x4_t
-+test_vrev64u16 (uint16x4_t _arg)
-+{
-+  return vrev64_u16 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  uint16x4_t inorder = {1, 2, 3, 4};
-+  uint16x4_t reversed = test_vrev64u16 (inorder);
-+  uint16x4_t expected = {4, 3, 2, 1};
-+
-+  for (i = 0; i < 4; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpp16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpp16.x
-@@ -0,0 +1,26 @@
-+extern void abort (void);
-+
-+poly16x4x2_t
-+test_vuzpp16 (poly16x4_t _a, poly16x4_t _b)
-+{
-+  return vuzp_p16 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  poly16_t first[] = {1, 2, 3, 4};
-+  poly16_t second[] = {5, 6, 7, 8};
-+  poly16x4x2_t result = test_vuzpp16 (vld1_p16 (first), vld1_p16 (second));
-+  poly16_t exp1[] = {1, 3, 5, 7};
-+  poly16_t exp2[] = {2, 4, 6, 8};
-+  poly16x4_t expect1 = vld1_p16 (exp1);
-+  poly16x4_t expect2 = vld1_p16 (exp2);
-+
-+  for (i = 0; i < 4; i++)
-+    if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqf32_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqf32_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vuzpq_f32' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vuzpqf32.x"
-+
-+/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzipp8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzipp8_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vzip_p8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vzipp8.x"
-+
-+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqp16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqp16_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vtrnq_p16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vtrnqp16.x"
-+
-+/* { dg-final { scan-assembler-times "trn1\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "trn2\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32qp16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32qp16.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+poly16x8_t
-+test_vrev32qp16 (poly16x8_t _arg)
-+{
-+  return vrev32q_p16 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  poly16x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
-+  poly16x8_t reversed = test_vrev32qp16 (inorder);
-+  poly16x8_t expected = {2, 1, 4, 3, 6, 5, 8, 7};
-+
-+  for (i = 0; i < 8; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu32_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu32_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vtrnq_u32' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vtrnqu32.x"
-+
-+/* { dg-final { scan-assembler-times "trn1\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "trn2\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqs8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqs8.x
-@@ -0,0 +1,27 @@
-+extern void abort (void);
-+
-+int8x16x2_t
-+test_vuzpqs8 (int8x16_t _a, int8x16_t _b)
-+{
-+  return vuzpq_s8 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  int8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
-+  int8_t second[] =
-+      {17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32};
-+  int8x16x2_t result = test_vuzpqs8 (vld1q_s8 (first), vld1q_s8 (second));
-+  int8_t exp1[] = {1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31};
-+  int8_t exp2[] = {2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32};
-+  int8x16_t expect1 = vld1q_s8 (exp1);
-+  int8x16_t expect2 = vld1q_s8 (exp2);
-+
-+  for (i = 0; i < 16; i++)
-+    if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqs32.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqs32.x
-@@ -0,0 +1,27 @@
-+extern void abort (void);
-+
-+int32x4x2_t
-+test_vzipqs32 (int32x4_t _a, int32x4_t _b)
-+{
-+  return vzipq_s32 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  int32_t first[] = {1, 2, 3, 4};
-+  int32_t second[] = {5, 6, 7, 8};
-+  int32x4x2_t result = test_vzipqs32 (vld1q_s32 (first), vld1q_s32 (second));
-+  int32x4_t res1 = result.val[0], res2 = result.val[1];
-+  int32_t exp1[] = {1, 5, 2, 6};
-+  int32_t exp2[] = {3, 7, 4, 8};
-+  int32x4_t expected1 = vld1q_s32 (exp1);
-+  int32x4_t expected2 = vld1q_s32 (exp2);
-+
-+  for (i = 0; i < 4; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qs16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qs16_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev64q_s16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev64qs16.x"
-+
-+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.8h, ?v\[0-9\]+.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32s8.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32s8.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+int8x8_t
-+test_vrev32s8 (int8x8_t _arg)
-+{
-+  return vrev32_s8 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  int8x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
-+  int8x8_t reversed = test_vrev32s8 (inorder);
-+  int8x8_t expected = {4, 3, 2, 1, 8, 7, 6, 5};
-+
-+  for (i = 0; i < 8; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/extq_p16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/extq_p16_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vextQp16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+
-+#include "arm_neon.h"
-+#include "extq_p16.x"
-+
-+/* { dg-final { scan-assembler-times "ext\[ \t\]+\[vV\]\[0-9\]+\.16\[bB\], ?\[vV\]\[0-9\]+\.16\[bB\], ?\[vV\]\[0-9\]+\.16\[bB\], ?#\[0-9\]+\(?:.2\)?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 7 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqu32.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqu32.x
-@@ -0,0 +1,27 @@
-+extern void abort (void);
-+
-+uint32x4x2_t
-+test_vzipqu32 (uint32x4_t _a, uint32x4_t _b)
-+{
-+  return vzipq_u32 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  uint32_t first[] = {1, 2, 3, 4};
-+  uint32_t second[] = {5, 6, 7, 8};
-+  uint32x4x2_t result = test_vzipqu32 (vld1q_u32 (first), vld1q_u32 (second));
-+  uint32x4_t res1 = result.val[0], res2 = result.val[1];
-+  uint32_t exp1[] = {1, 5, 2, 6};
-+  uint32_t exp2[] = {3, 7, 4, 8};
-+  uint32x4_t expected1 = vld1q_u32 (exp1);
-+  uint32x4_t expected2 = vld1q_u32 (exp2);
-+
-+  for (i = 0; i < 4; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/extq_u32_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/extq_u32_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vextQu32' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+
-+#include "arm_neon.h"
-+#include "extq_u32.x"
-+
-+/* { dg-final { scan-assembler-times "ext\[ \t\]+\[vV\]\[0-9\]+\.16\[bB\], ?\[vV\]\[0-9\]+\.16\[bB\], ?\[vV\]\[0-9\]+\.16\[bB\], ?#\[0-9\]+\(?:.4)?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 3 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32p16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32p16_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev32_p16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev32p16.x"
-+
-+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.4h, ?v\[0-9\]+.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/ext_f32.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/ext_f32.x
-@@ -0,0 +1,30 @@
-+extern void abort (void);
-+
-+float32x2_t
-+test_vext_f32_1 (float32x2_t a, float32x2_t b)
-+{
-+  return vext_f32 (a, b, 1);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i, off;
-+  float32_t arr1[] = {0, 1};
-+  float32x2_t in1 = vld1_f32 (arr1);
-+  float32_t arr2[] = {2, 3};
-+  float32x2_t in2 = vld1_f32 (arr2);
-+  float32_t exp[2];
-+  float32x2_t expected;
-+  float32x2_t actual = test_vext_f32_1 (in1, in2);
-+
-+  for (i = 0; i < 2; i++)
-+    exp[i] = i + 1;
-+  expected = vld1_f32 (exp);
-+  for (i = 0; i < 2; i++)
-+    if (actual[i] != expected[i])
-+      abort ();
-+
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/ext_f64_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/ext_f64_1.c
-@@ -0,0 +1,25 @@
-+/* Test the `vextf64' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+
-+#include "arm_neon.h"
-+
-+extern void abort (void);
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i, off;
-+  float64x1_t in1 = {0};
-+  float64x1_t in2 = {1};
-+  float64x1_t actual = vext_f64 (in1, in2, 0);
-+  if (actual != in1)
-+    abort ();
-+
-+  return 0;
-+}
-+
-+/* Do not scan-assembler.  An EXT instruction could be emitted, but would merely
-+   return its first argument, so it is legitimate to optimize it out.  */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpf32_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpf32_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vuzp_f32' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vuzpf32.x"
-+
-+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqu16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpqu16_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vuzpq_u16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vuzpqu16.x"
-+
-+/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpu8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpu8_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vuzp_u8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vuzpu8.x"
-+
-+/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqf32_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqf32_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vzipq_f32' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vzipqf32.x"
-+
-+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64s16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64s16_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev64_s16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev64s16.x"
-+
-+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.4h, ?v\[0-9\]+.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrns32.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrns32.x
-@@ -0,0 +1,27 @@
-+extern void abort (void);
-+
-+int32x2x2_t
-+test_vtrns32 (int32x2_t _a, int32x2_t _b)
-+{
-+  return vtrn_s32 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  int32_t first[] = {1, 2};
-+  int32_t second[] = {3, 4};
-+  int32x2x2_t result = test_vtrns32 (vld1_s32 (first), vld1_s32 (second));
-+  int32x2_t res1 = result.val[0], res2 = result.val[1];
-+  int32_t exp1[] = {1, 3};
-+  int32_t exp2[] = {2, 4};
-+  int32x2_t expected1 = vld1_s32 (exp1);
-+  int32x2_t expected2 = vld1_s32 (exp2);
-+
-+  for (i = 0; i < 2; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev16qu8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev16qu8_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev16q_u8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev16qu8.x"
-+
-+/* { dg-final { scan-assembler-times "rev16\[ \t\]+v\[0-9\]+.16b, ?v\[0-9\]+.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzips16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzips16.x
-@@ -0,0 +1,27 @@
-+extern void abort (void);
-+
-+int16x4x2_t
-+test_vzips16 (int16x4_t _a, int16x4_t _b)
-+{
-+  return vzip_s16 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  int16_t first[] = {1, 2, 3, 4};
-+  int16_t second[] = {5, 6, 7, 8};
-+  int16x4x2_t result = test_vzips16 (vld1_s16 (first), vld1_s16 (second));
-+  int16x4_t res1 = result.val[0], res2 = result.val[1];
-+  int16_t exp1[] = {1, 5, 2, 6};
-+  int16_t exp2[] = {3, 7, 4, 8};
-+  int16x4_t expected1 = vld1_s16 (exp1);
-+  int16x4_t expected2 = vld1_s16 (exp2);
-+
-+  for (i = 0; i < 4; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qs8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qs8_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev64q_s8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev64qs8.x"
-+
-+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.16b, ?v\[0-9\]+.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/extq_p8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/extq_p8_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vextQp8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+
-+#include "arm_neon.h"
-+#include "extq_p8.x"
-+
-+/* { dg-final { scan-assembler-times "ext\[ \t\]+\[vV\]\[0-9\]+\.16\[bB\], ?\[vV\]\[0-9\]+\.16\[bB\], ?\[vV\]\[0-9\]+\.16\[bB\], ?#?\[0-9\]+\(?:.2\)?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 15 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnu32.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnu32.x
-@@ -0,0 +1,27 @@
-+extern void abort (void);
-+
-+uint32x2x2_t
-+test_vtrnu32 (uint32x2_t _a, uint32x2_t _b)
-+{
-+  return vtrn_u32 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  uint32_t first[] = {1, 2};
-+  uint32_t second[] = {3, 4};
-+  uint32x2x2_t result = test_vtrnu32 (vld1_u32 (first), vld1_u32 (second));
-+  uint32x2_t res1 = result.val[0], res2 = result.val[1];
-+  uint32_t exp1[] = {1, 3};
-+  uint32_t exp2[] = {2, 4};
-+  uint32x2_t expected1 = vld1_u32 (exp1);
-+  uint32x2_t expected2 = vld1_u32 (exp2);
-+
-+  for (i = 0; i < 2; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzipu16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzipu16.x
-@@ -0,0 +1,27 @@
-+extern void abort (void);
-+
-+uint16x4x2_t
-+test_vzipu16 (uint16x4_t _a, uint16x4_t _b)
-+{
-+  return vzip_u16 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  uint16_t first[] = {1, 2, 3, 4};
-+  uint16_t second[] = {5, 6, 7, 8};
-+  uint16x4x2_t result = test_vzipu16 (vld1_u16 (first), vld1_u16 (second));
-+  uint16x4_t res1 = result.val[0], res2 = result.val[1];
-+  uint16_t exp1[] = {1, 5, 2, 6};
-+  uint16_t exp2[] = {3, 7, 4, 8};
-+  uint16x4_t expected1 = vld1_u16 (exp1);
-+  uint16x4_t expected2 = vld1_u16 (exp2);
-+
-+  for (i = 0; i < 4; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpu16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vuzpu16_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vuzp_u16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vuzpu16.x"
-+
-+/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32s8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32s8_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev32_s8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev32s8.x"
-+
-+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.8b, ?v\[0-9\]+.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnf32_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnf32_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vtrn_f32' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vtrnf32.x"
-+
-+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32qu16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev32qu16_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vrev32q_u16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vrev32qu16.x"
-+
-+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.8h, ?v\[0-9\]+.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqu16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzipqu16_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vzipq_u16' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vzipqu16.x"
-+
-+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vzipu8_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vzipu8_1.c
-@@ -0,0 +1,11 @@
-+/* Test the `vzip_u8' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline" } */
-+
-+#include <arm_neon.h>
-+#include "vzipu8.x"
-+
-+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqp16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vtrnqp16.x
-@@ -0,0 +1,27 @@
-+extern void abort (void);
-+
-+poly16x8x2_t
-+test_vtrnqp16 (poly16x8_t _a, poly16x8_t _b)
-+{
-+  return vtrnq_p16 (_a, _b);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  poly16_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
-+  poly16_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
-+  poly16x8x2_t result = test_vtrnqp16 (vld1q_p16 (first), vld1q_p16 (second));
-+  poly16x8_t res1 = result.val[0], res2 = result.val[1];
-+  poly16_t exp1[] = {1, 9, 3, 11, 5, 13, 7, 15};
-+  poly16_t exp2[] = {2, 10, 4, 12, 6, 14, 8, 16};
-+  poly16x8_t expected1 = vld1q_p16 (exp1);
-+  poly16x8_t expected2 = vld1q_p16 (exp2);
-+
-+  for (i = 0; i < 8; i++)
-+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
-+      abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/int_comparisons_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/int_comparisons_1.c
-@@ -0,0 +1,47 @@
-+/* { dg-do compile } */
-+/* { dg-options "-O3 -fno-inline" } */
-+
-+/* Scan-assembler test, so, incorporate as little other code as possible.  */
-+
-+#include "arm_neon.h"
-+#include "int_comparisons.x"
-+
-+/* Operations on all 18 integer types:  (q?)_[su](8|16|32|64), d_[su]64.
-+   (d?)_[us]64 generate regs of form 'd0' rather than e.g. 'v0.2d'.  */
-+/* { dg-final { scan-assembler-times "\[ \t\]cmeq\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]*v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]*#?0" 14 } } */
-+/* { dg-final { scan-assembler-times "\[ \t\]cmeq\[ \t\]+d\[0-9\]+,\[ \t\]*d\[0-9\]+,\[ \t\]*#?0" 4 } } */
-+/* { dg-final { scan-assembler-times "\[ \t\]cmeq\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]*v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\]" 14 } } */
-+/* { dg-final { scan-assembler-times "\[ \t\]cmeq\[ \t\]+d\[0-9\]+,\[ \t\]*d\[0-9\]+,\[ \t\]+d\[0-9\]+" 4 } } */
-+/* { dg-final { scan-assembler-times "\[ \t\]cmtst\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]*v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\]" 14 } } */
-+/* { dg-final { scan-assembler-times "\[ \t\]cmtst\[ \t\]+d\[0-9\]+,\[ \t\]*d\[0-9\]+,\[ \t\]+d\[0-9\]+" 4 } } */
-+
-+/* vcge + vcle both implemented with cmge (signed) or cmhs (unsigned).  */
-+/* { dg-final { scan-assembler-times "\[ \t\]cmge\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]*v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\]" 14 } } */
-+/* { dg-final { scan-assembler-times "\[ \t\]cmge\[ \t\]+d\[0-9\]+,\[ \t\]*d\[0-9\]+,\[ \t\]+d\[0-9\]+" 4 } } */
-+/* { dg-final { scan-assembler-times "\[ \t\]cmhs\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]*v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\]" 14 } } */
-+/* { dg-final { scan-assembler-times "\[ \t\]cmhs\[ \t\]+d\[0-9\]+,\[ \t\]*d\[0-9\]+,\[ \t\]+d\[0-9\]+" 4 } } */
-+
-+/* vcgt + vclt both implemented with cmgt (signed) or cmhi (unsigned).  */
-+/* { dg-final { scan-assembler-times "\[ \t\]cmgt\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]*v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\]" 14 } } */
-+/* { dg-final { scan-assembler-times "\[ \t\]cmgt\[ \t\]+d\[0-9\]+,\[ \t\]*d\[0-9\]+,\[ \t\]+d\[0-9\]+" 4 } } */
-+/* { dg-final { scan-assembler-times "\[ \t\]cmhi\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]*v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\]" 14 } } */
-+/* { dg-final { scan-assembler-times "\[ \t\]cmhi\[ \t\]+d\[0-9\]+,\[ \t\]*d\[0-9\]+,\[ \t\]+d\[0-9\]+" 4 } } */
-+
-+/* Comparisons against immediate zero, on the 8 signed integer types only.  */
-+
-+/* { dg-final { scan-assembler-times "\[ \t\]cmge\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]*v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]*#?0" 7 } } */
-+/*  For int64_t and int64x1_t, combine_simplify_rtx failure of
-+    https://gcc.gnu.org/ml/gcc/2014-06/msg00253.html
-+    prevents generation of cmge....#0, instead producing mvn + sshr.  */
-+/* { #dg-final { scan-assembler-times "\[ \t\]cmge\[ \t\]+d\[0-9\]+,\[ \t\]*d\[0-9\]+,\[ \t\]*#?0" 2 } } */
-+/* { dg-final { scan-assembler-times "\[ \t\]cmgt\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]*v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]*#?0" 7 } } */
-+/* { dg-final { scan-assembler-times "\[ \t\]cmgt\[ \t\]+d\[0-9\]+,\[ \t\]*d\[0-9\]+,\[ \t\]*#?0" 2 } } */
-+/* { dg-final { scan-assembler-times "\[ \t\]cmle\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]*v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]*#?0" 7 } } */
-+/* { dg-final { scan-assembler-times "\[ \t\]cmle\[ \t\]+d\[0-9\]+,\[ \t\]*d\[0-9\]+,\[ \t\]*#?0" 2 } } */
-+/* { dg-final { scan-assembler-times "\[ \t\]cmlt\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]*v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]*#?0" 7 } } */
-+/* For int64_t and int64x1_t, cmlt ... #0 and sshr ... #63 are equivalent,
-+   so allow either.  cmgez issue above results in extra 2 * sshr....63.  */
-+/* { dg-final { scan-assembler-times "\[ \t\](?:cmlt|sshr)\[ \t\]+d\[0-9\]+,\[ \t\]*d\[0-9\]+,\[ \t\]*#?(?:0|63)" 4 } } */
-+
-+// All should have been compiled into single insns without inverting result:
-+/* { dg-final { scan-assembler-not "\[ \t\]not\[ \t\]" } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qp16.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64qp16.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+poly16x8_t
-+test_vrev64qp16 (poly16x8_t _arg)
-+{
-+  return vrev64q_p16 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  poly16x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
-+  poly16x8_t reversed = test_vrev64qp16 (inorder);
-+  poly16x8_t expected = {4, 3, 2, 1, 8, 7, 6, 5};
-+
-+  for (i = 0; i < 8; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/ext_f32_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/ext_f32_1.c
-@@ -0,0 +1,10 @@
-+/* Test the `vextf32' AArch64 SIMD intrinsic.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -O3 -fno-inline" } */
-+
-+#include "arm_neon.h"
-+#include "ext_f32.x"
-+
-+/* { dg-final { scan-assembler-times "ext\[ \t\]+\[vV\]\[0-9\]+\.8\[bB\], ?\[vV\]\[0-9\]+\.8\[bB\], ?\[vV\]\[0-9\]+\.8\[bB\], ?#\[0-9\]+\(?:.4)?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64f32.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vrev64f32.x
-@@ -0,0 +1,22 @@
-+extern void abort (void);
-+
-+float32x2_t
-+test_vrev64f32 (float32x2_t _arg)
-+{
-+  return vrev64_f32 (_arg);
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  int i;
-+  float32x2_t inorder = {1, 2};
-+  float32x2_t reversed = test_vrev64f32 (inorder);
-+  float32x2_t expected = {2, 1};
-+
-+  for (i = 0; i < 2; i++)
-+    if (reversed[i] != expected[i])
-+      abort ();
-+  return 0;
-+}
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/vdup_lane_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/vdup_lane_1.c
-@@ -0,0 +1,430 @@
-+/* Test vdup_lane intrinsics work correctly.  */
-+/* { dg-do run } */
-+/* { dg-options "--save-temps -O1" } */
-+
-+#include <arm_neon.h>
-+
-+extern void abort (void);
-+
-+float32x2_t __attribute__ ((noinline))
-+wrap_vdup_lane_f32_0 (float32x2_t a)
-+{
-+  return vdup_lane_f32 (a, 0);
-+}
-+
-+float32x2_t __attribute__ ((noinline))
-+wrap_vdup_lane_f32_1 (float32x2_t a)
-+{
-+  return vdup_lane_f32 (a, 1);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdup_lane_f32 ()
-+{
-+  float32x2_t a;
-+  float32x2_t b;
-+  int i;
-+  float32_t c[2] = { 0.0 , 3.14 };
-+  float32_t d[2];
-+
-+  a = vld1_f32 (c);
-+  b = wrap_vdup_lane_f32_0 (a);
-+  vst1_f32 (d, b);
-+  for (i = 0; i < 2; i++)
-+    if (c[0] != d[i])
-+      return 1;
-+
-+  b = wrap_vdup_lane_f32_1 (a);
-+  vst1_f32 (d, b);
-+  for (i = 0; i < 2; i++)
-+    if (c[1] != d[i])
-+      return 1;
-+  return 0;
-+}
-+
-+float32x4_t __attribute__ ((noinline))
-+wrap_vdupq_lane_f32_0 (float32x2_t a)
-+{
-+  return vdupq_lane_f32 (a, 0);
-+}
-+
-+float32x4_t __attribute__ ((noinline))
-+wrap_vdupq_lane_f32_1 (float32x2_t a)
-+{
-+  return vdupq_lane_f32 (a, 1);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdupq_lane_f32 ()
-+{
-+  float32x2_t a;
-+  float32x4_t b;
-+  int i;
-+  float32_t c[2] = { 0.0 , 3.14 };
-+  float32_t d[4];
-+
-+  a = vld1_f32 (c);
-+  b = wrap_vdupq_lane_f32_0 (a);
-+  vst1q_f32 (d, b);
-+  for (i = 0; i < 4; i++)
-+    if (c[0] != d[i])
-+      return 1;
-+
-+  b = wrap_vdupq_lane_f32_1 (a);
-+  vst1q_f32 (d, b);
-+  for (i = 0; i < 4; i++)
-+    if (c[1] != d[i])
-+      return 1;
-+  return 0;
-+}
-+
-+int8x8_t __attribute__ ((noinline))
-+wrap_vdup_lane_s8_0 (int8x8_t a)
-+{
-+  return vdup_lane_s8 (a, 0);
-+}
-+
-+int8x8_t __attribute__ ((noinline))
-+wrap_vdup_lane_s8_1 (int8x8_t a)
-+{
-+  return vdup_lane_s8 (a, 1);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdup_lane_s8 ()
-+{
-+  int8x8_t a;
-+  int8x8_t b;
-+  int i;
-+  /* Only two first cases are interesting.  */
-+  int8_t c[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
-+  int8_t d[8];
-+
-+  a = vld1_s8 (c);
-+  b = wrap_vdup_lane_s8_0 (a);
-+  vst1_s8 (d, b);
-+  for (i = 0; i < 8; i++)
-+    if (c[0] != d[i])
-+      return 1;
-+
-+  b = wrap_vdup_lane_s8_1 (a);
-+  vst1_s8 (d, b);
-+  for (i = 0; i < 8; i++)
-+    if (c[1] != d[i])
-+      return 1;
-+  return 0;
-+}
-+
-+int8x16_t __attribute__ ((noinline))
-+wrap_vdupq_lane_s8_0 (int8x8_t a)
-+{
-+  return vdupq_lane_s8 (a, 0);
-+}
-+
-+int8x16_t __attribute__ ((noinline))
-+wrap_vdupq_lane_s8_1 (int8x8_t a)
-+{
-+  return vdupq_lane_s8 (a, 1);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdupq_lane_s8 ()
-+{
-+  int8x8_t a;
-+  int8x16_t b;
-+  int i;
-+  /* Only two first cases are interesting.  */
-+  int8_t c[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
-+  int8_t d[16];
-+
-+  a = vld1_s8 (c);
-+  b = wrap_vdupq_lane_s8_0 (a);
-+  vst1q_s8 (d, b);
-+  for (i = 0; i < 16; i++)
-+    if (c[0] != d[i])
-+      return 1;
-+
-+  b = wrap_vdupq_lane_s8_1 (a);
-+  vst1q_s8 (d, b);
-+  for (i = 0; i < 16; i++)
-+    if (c[1] != d[i])
-+      return 1;
-+  return 0;
-+}
-+
-+int16x4_t __attribute__ ((noinline))
-+wrap_vdup_lane_s16_0 (int16x4_t a)
-+{
-+  return vdup_lane_s16 (a, 0);
-+}
-+
-+int16x4_t __attribute__ ((noinline))
-+wrap_vdup_lane_s16_1 (int16x4_t a)
-+{
-+  return vdup_lane_s16 (a, 1);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdup_lane_s16 ()
-+{
-+  int16x4_t a;
-+  int16x4_t b;
-+  int i;
-+  /* Only two first cases are interesting.  */
-+  int16_t c[4] = { 0, 1, 2, 3 };
-+  int16_t d[4];
-+
-+  a = vld1_s16 (c);
-+  b = wrap_vdup_lane_s16_0 (a);
-+  vst1_s16 (d, b);
-+  for (i = 0; i < 4; i++)
-+    if (c[0] != d[i])
-+      return 1;
-+
-+  b = wrap_vdup_lane_s16_1 (a);
-+  vst1_s16 (d, b);
-+  for (i = 0; i < 4; i++)
-+    if (c[1] != d[i])
-+      return 1;
-+  return 0;
-+}
-+
-+int16x8_t __attribute__ ((noinline))
-+wrap_vdupq_lane_s16_0 (int16x4_t a)
-+{
-+  return vdupq_lane_s16 (a, 0);
-+}
-+
-+int16x8_t __attribute__ ((noinline))
-+wrap_vdupq_lane_s16_1 (int16x4_t a)
-+{
-+  return vdupq_lane_s16 (a, 1);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdupq_lane_s16 ()
-+{
-+  int16x4_t a;
-+  int16x8_t b;
-+  int i;
-+  /* Only two first cases are interesting.  */
-+  int16_t c[4] = { 0, 1, 2, 3 };
-+  int16_t d[8];
-+
-+  a = vld1_s16 (c);
-+  b = wrap_vdupq_lane_s16_0 (a);
-+  vst1q_s16 (d, b);
-+  for (i = 0; i < 8; i++)
-+    if (c[0] != d[i])
-+      return 1;
-+
-+  b = wrap_vdupq_lane_s16_1 (a);
-+  vst1q_s16 (d, b);
-+  for (i = 0; i < 8; i++)
-+    if (c[1] != d[i])
-+      return 1;
-+  return 0;
-+}
-+
-+int32x2_t __attribute__ ((noinline))
-+wrap_vdup_lane_s32_0 (int32x2_t a)
-+{
-+  return vdup_lane_s32 (a, 0);
-+}
-+
-+int32x2_t __attribute__ ((noinline))
-+wrap_vdup_lane_s32_1 (int32x2_t a)
-+{
-+  return vdup_lane_s32 (a, 1);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdup_lane_s32 ()
-+{
-+  int32x2_t a;
-+  int32x2_t b;
-+  int i;
-+  int32_t c[2] = { 0, 1 };
-+  int32_t d[2];
-+
-+  a = vld1_s32 (c);
-+  b = wrap_vdup_lane_s32_0 (a);
-+  vst1_s32 (d, b);
-+  for (i = 0; i < 2; i++)
-+    if (c[0] != d[i])
-+      return 1;
-+
-+  b = wrap_vdup_lane_s32_1 (a);
-+  vst1_s32 (d, b);
-+  for (i = 0; i < 2; i++)
-+    if (c[1] != d[i])
-+      return 1;
-+  return 0;
-+}
-+
-+int32x4_t __attribute__ ((noinline))
-+wrap_vdupq_lane_s32_0 (int32x2_t a)
-+{
-+  return vdupq_lane_s32 (a, 0);
-+}
-+
-+int32x4_t __attribute__ ((noinline))
-+wrap_vdupq_lane_s32_1 (int32x2_t a)
-+{
-+  return vdupq_lane_s32 (a, 1);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdupq_lane_s32 ()
-+{
-+  int32x2_t a;
-+  int32x4_t b;
-+  int i;
-+  int32_t c[2] = { 0, 1 };
-+  int32_t d[4];
-+
-+  a = vld1_s32 (c);
-+  b = wrap_vdupq_lane_s32_0 (a);
-+  vst1q_s32 (d, b);
-+  for (i = 0; i < 4; i++)
-+    if (c[0] != d[i])
-+      return 1;
-+
-+  b = wrap_vdupq_lane_s32_1 (a);
-+  vst1q_s32 (d, b);
-+  for (i = 0; i < 4; i++)
-+    if (c[1] != d[i])
-+      return 1;
-+  return 0;
-+}
-+
-+int64x1_t __attribute__ ((noinline))
-+wrap_vdup_lane_s64_0 (int64x1_t a)
-+{
-+  return vdup_lane_s64 (a, 0);
-+}
-+
-+int64x1_t __attribute__ ((noinline))
-+wrap_vdup_lane_s64_1 (int64x1_t a)
-+{
-+  return vdup_lane_s64 (a, 1);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdup_lane_s64 ()
-+{
-+  int64x1_t a;
-+  int64x1_t b;
-+  int64_t c[1];
-+  int64_t d[1];
-+
-+  c[0] = 0;
-+  a = vld1_s64 (c);
-+  b = wrap_vdup_lane_s64_0 (a);
-+  vst1_s64 (d, b);
-+  if (c[0] != d[0])
-+    return 1;
-+
-+  c[0] = 1;
-+  a = vld1_s64 (c);
-+  b = wrap_vdup_lane_s64_1 (a);
-+  vst1_s64 (d, b);
-+  if (c[0] != d[0])
-+    return 1;
-+  return 0;
-+}
-+
-+int64x2_t __attribute__ ((noinline))
-+wrap_vdupq_lane_s64_0 (int64x1_t a)
-+{
-+  return vdupq_lane_s64 (a, 0);
-+}
-+
-+int64x2_t __attribute__ ((noinline))
-+wrap_vdupq_lane_s64_1 (int64x1_t a)
-+{
-+  return vdupq_lane_s64 (a, 1);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdupq_lane_s64 ()
-+{
-+  int64x1_t a;
-+  int64x2_t b;
-+  int i;
-+  int64_t c[1];
-+  int64_t d[2];
-+
-+  c[0] = 0;
-+  a = vld1_s64 (c);
-+  b = wrap_vdupq_lane_s64_0 (a);
-+  vst1q_s64 (d, b);
-+  for (i = 0; i < 2; i++)
-+    if (c[0] != d[i])
-+      return 1;
-+
-+  c[0] = 1;
-+  a = vld1_s64 (c);
-+  b = wrap_vdupq_lane_s64_1 (a);
-+  vst1q_s64 (d, b);
-+  for (i = 0; i < 2; i++)
-+    if (c[0] != d[i])
-+      return 1;
-+  return 0;
-+}
-+
-+int
-+main ()
-+{
-+
-+  if (test_vdup_lane_f32 ())
-+    abort ();
-+  if (test_vdup_lane_s8 ())
-+    abort ();
-+  if (test_vdup_lane_s16 ())
-+    abort ();
-+  if (test_vdup_lane_s32 ())
-+    abort ();
-+  if (test_vdup_lane_s64 ())
-+    abort ();
-+  if (test_vdupq_lane_f32 ())
-+    abort ();
-+  if (test_vdupq_lane_s8 ())
-+    abort ();
-+  if (test_vdupq_lane_s16 ())
-+    abort ();
-+  if (test_vdupq_lane_s32 ())
-+    abort ();
-+  if (test_vdupq_lane_s64 ())
-+    abort ();
-+
-+  return 0;
-+}
-+
-+/* Asm check for test_vdup_lane_s8.  */
-+/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.8b, v\[0-9\]+\.b\\\[0\\\]" 1 } } */
-+/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.8b, v\[0-9\]+\.b\\\[1\\\]" 1 } } */
-+
-+/* Asm check for test_vdupq_lane_s8.  */
-+/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.16b, v\[0-9\]+\.b\\\[0\\\]" 1 } } */
-+/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.16b, v\[0-9\]+\.b\\\[1\\\]" 1 } } */
-+
-+/* Asm check for test_vdup_lane_s16.  */
-+/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.4h, v\[0-9\]+\.h\\\[0\\\]" 1 } } */
-+/* Asm check for test_vdup_lane_s16.  */
-+/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.4h, v\[0-9\]+\.h\\\[1\\\]" 1 } } */
-+
-+/* Asm check for test_vdupq_lane_s16.  */
-+/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.8h, v\[0-9\]+\.h\\\[0\\\]" 1 } } */
-+/* Asm check for test_vdupq_lane_s16.  */
-+/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.8h, v\[0-9\]+\.h\\\[1\\\]" 1 } } */
-+
-+/* Asm check for test_vdup_lane_f32 and test_vdup_lane_s32.  */
-+/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.2s, v\[0-9\]+\.s\\\[0\\\]" 2 } } */
-+/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.2s, v\[0-9\]+\.s\\\[1\\\]" 2 } } */
-+
-+/* Asm check for test_vdupq_lane_f32 and test_vdupq_lane_s32.  */
-+/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.4s, v\[0-9\]+\.s\\\[0\\\]" 2 } } */
-+/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.4s, v\[0-9\]+\.s\\\[1\\\]" 2 } } */
-+
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/test_frame_15.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_15.c
-@@ -0,0 +1,19 @@
-+/* Verify:
-+     * with outgoing.
-+     * total frame size > 512.
-+       area except outgoing <= 512
-+     * number of callee-save reg >= 2.
-+     * split the stack adjustment into two substractions,
-+       the first could be optimized into "stp !".  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-O2 --save-temps" } */
-+
-+#include "test_frame_common.h"
-+
-+t_frame_pattern_outgoing (test15, 480, , 8, a[8])
-+t_frame_run (test15)
-+
-+/* { dg-final { scan-assembler-times "sub\tsp, sp, #\[0-9\]+" 1 } } */
-+/* { dg-final { scan-assembler-times "stp\tx29, x30, \\\[sp, -\[0-9\]+\\\]!" 3 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/vbslq_u64_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/vbslq_u64_1.c
-@@ -0,0 +1,17 @@
-+/* Test if a BSL-like instruction can be generated from a C idiom.  */
-+/* { dg-do assemble } */
-+/* { dg-options "--save-temps -O3" } */
-+
-+#include <arm_neon.h>
-+
-+/* Folds to BIF.  */
-+
-+uint32x4_t
-+vbslq_dummy_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t mask)
-+{
-+  return (mask & a) | (~mask & b);
-+}
-+
-+/* { dg-final { scan-assembler-times "bif\\tv" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/vdup_n_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/vdup_n_1.c
-@@ -0,0 +1,619 @@
-+/* Test vdup_lane intrinsics work correctly.  */
-+/* { dg-do run } */
-+/* { dg-options "-O1 --save-temps" } */
-+
-+#include <arm_neon.h>
-+
-+extern void abort (void);
-+
-+float32x2_t __attribute__ ((noinline))
-+wrap_vdup_n_f32 (float32_t a)
-+{
-+  return vdup_n_f32 (a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdup_n_f32 ()
-+{
-+  float32_t a = 1.0;
-+  float32x2_t b;
-+  float32_t c[2];
-+  int i;
-+
-+  b = wrap_vdup_n_f32 (a);
-+  vst1_f32 (c, b);
-+  for (i = 0; i < 2; i++)
-+    if (a != c[i])
-+      return 1;
-+  return 0;
-+}
-+
-+float32x4_t __attribute__ ((noinline))
-+wrap_vdupq_n_f32 (float32_t a)
-+{
-+  return vdupq_n_f32 (a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdupq_n_f32 ()
-+{
-+  float32_t a = 1.0;
-+  float32x4_t b;
-+  float32_t c[4];
-+  int i;
-+
-+  b = wrap_vdupq_n_f32 (a);
-+  vst1q_f32 (c, b);
-+  for (i = 0; i < 4; i++)
-+    if (a != c[i])
-+      return 1;
-+  return 0;
-+}
-+
-+float64x1_t __attribute__ ((noinline))
-+wrap_vdup_n_f64 (float64_t a)
-+{
-+  return vdup_n_f64 (a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdup_n_f64 ()
-+{
-+  float64_t a = 1.0;
-+  float64x1_t b;
-+  float64_t c[1];
-+  int i;
-+
-+  b = wrap_vdup_n_f64 (a);
-+  vst1_f64 (c, b);
-+  for (i = 0; i < 1; i++)
-+    if (a != c[i])
-+      return 1;
-+  return 0;
-+}
-+
-+float64x2_t __attribute__ ((noinline))
-+wrap_vdupq_n_f64 (float64_t a)
-+{
-+  return vdupq_n_f64 (a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdupq_n_f64 ()
-+{
-+  float64_t a = 1.0;
-+  float64x2_t b;
-+  float64_t c[2];
-+  int i;
-+
-+  b = wrap_vdupq_n_f64 (a);
-+  vst1q_f64 (c, b);
-+  for (i = 0; i < 2; i++)
-+    if (a != c[i])
-+      return 1;
-+  return 0;
-+}
-+
-+poly8x8_t __attribute__ ((noinline))
-+wrap_vdup_n_p8 (poly8_t a)
-+{
-+  return vdup_n_p8 (a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdup_n_p8 ()
-+{
-+  poly8_t a = 1;
-+  poly8x8_t b;
-+  poly8_t c[8];
-+  int i;
-+
-+  b = wrap_vdup_n_p8 (a);
-+  vst1_p8 (c, b);
-+  for (i = 0; i < 8; i++)
-+    if (a != c[i])
-+      return 1;
-+  return 0;
-+}
-+
-+poly8x16_t __attribute__ ((noinline))
-+wrap_vdupq_n_p8 (poly8_t a)
-+{
-+  return vdupq_n_p8 (a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdupq_n_p8 ()
-+{
-+  poly8_t a = 1;
-+  poly8x16_t b;
-+  poly8_t c[16];
-+  int i;
-+
-+  b = wrap_vdupq_n_p8 (a);
-+  vst1q_p8 (c, b);
-+  for (i = 0; i < 16; i++)
-+    if (a != c[i])
-+      return 1;
-+  return 0;
-+}
-+
-+int8x8_t __attribute__ ((noinline))
-+wrap_vdup_n_s8 (int8_t a)
-+{
-+  return vdup_n_s8 (a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdup_n_s8 ()
-+{
-+  int8_t a = 1;
-+  int8x8_t b;
-+  int8_t c[8];
-+  int i;
-+
-+  b = wrap_vdup_n_s8 (a);
-+  vst1_s8 (c, b);
-+  for (i = 0; i < 8; i++)
-+    if (a != c[i])
-+      return 1;
-+  return 0;
-+}
-+
-+int8x16_t __attribute__ ((noinline))
-+wrap_vdupq_n_s8 (int8_t a)
-+{
-+  return vdupq_n_s8 (a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdupq_n_s8 ()
-+{
-+  int8_t a = 1;
-+  int8x16_t b;
-+  int8_t c[16];
-+  int i;
-+
-+  b = wrap_vdupq_n_s8 (a);
-+  vst1q_s8 (c, b);
-+  for (i = 0; i < 16; i++)
-+    if (a != c[i])
-+      return 1;
-+  return 0;
-+}
-+
-+uint8x8_t __attribute__ ((noinline))
-+wrap_vdup_n_u8 (uint8_t a)
-+{
-+  return vdup_n_u8 (a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdup_n_u8 ()
-+{
-+  uint8_t a = 1;
-+  uint8x8_t b;
-+  uint8_t c[8];
-+  int i;
-+
-+  b = wrap_vdup_n_u8 (a);
-+  vst1_u8 (c, b);
-+  for (i = 0; i < 8; i++)
-+    if (a != c[i])
-+      return 1;
-+  return 0;
-+}
-+
-+uint8x16_t __attribute__ ((noinline))
-+wrap_vdupq_n_u8 (uint8_t a)
-+{
-+  return vdupq_n_u8 (a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdupq_n_u8 ()
-+{
-+  uint8_t a = 1;
-+  uint8x16_t b;
-+  uint8_t c[16];
-+  int i;
-+
-+  b = wrap_vdupq_n_u8 (a);
-+  vst1q_u8 (c, b);
-+  for (i = 0; i < 16; i++)
-+    if (a != c[i])
-+      return 1;
-+  return 0;
-+}
-+
-+poly16x4_t __attribute__ ((noinline))
-+wrap_vdup_n_p16 (poly16_t a)
-+{
-+  return vdup_n_p16 (a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdup_n_p16 ()
-+{
-+  poly16_t a = 1;
-+  poly16x4_t b;
-+  poly16_t c[4];
-+  int i;
-+
-+  b = wrap_vdup_n_p16 (a);
-+  vst1_p16 (c, b);
-+  for (i = 0; i < 4; i++)
-+    if (a != c[i])
-+      return 1;
-+  return 0;
-+}
-+
-+poly16x8_t __attribute__ ((noinline))
-+wrap_vdupq_n_p16 (poly16_t a)
-+{
-+  return vdupq_n_p16 (a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdupq_n_p16 ()
-+{
-+  poly16_t a = 1;
-+  poly16x8_t b;
-+  poly16_t c[8];
-+  int i;
-+
-+  b = wrap_vdupq_n_p16 (a);
-+  vst1q_p16 (c, b);
-+  for (i = 0; i < 8; i++)
-+    if (a != c[i])
-+      return 1;
-+  return 0;
-+}
-+
-+int16x4_t __attribute__ ((noinline))
-+wrap_vdup_n_s16 (int16_t a)
-+{
-+  return vdup_n_s16 (a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdup_n_s16 ()
-+{
-+  int16_t a = 1;
-+  int16x4_t b;
-+  int16_t c[4];
-+  int i;
-+
-+  b = wrap_vdup_n_s16 (a);
-+  vst1_s16 (c, b);
-+  for (i = 0; i < 4; i++)
-+    if (a != c[i])
-+      return 1;
-+  return 0;
-+}
-+
-+int16x8_t __attribute__ ((noinline))
-+wrap_vdupq_n_s16 (int16_t a)
-+{
-+  return vdupq_n_s16 (a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdupq_n_s16 ()
-+{
-+  int16_t a = 1;
-+  int16x8_t b;
-+  int16_t c[8];
-+  int i;
-+
-+  b = wrap_vdupq_n_s16 (a);
-+  vst1q_s16 (c, b);
-+  for (i = 0; i < 8; i++)
-+    if (a != c[i])
-+      return 1;
-+  return 0;
-+}
-+
-+uint16x4_t __attribute__ ((noinline))
-+wrap_vdup_n_u16 (uint16_t a)
-+{
-+  return vdup_n_u16 (a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdup_n_u16 ()
-+{
-+  uint16_t a = 1;
-+  uint16x4_t b;
-+  uint16_t c[4];
-+  int i;
-+
-+  b = wrap_vdup_n_u16 (a);
-+  vst1_u16 (c, b);
-+  for (i = 0; i < 4; i++)
-+    if (a != c[i])
-+      return 1;
-+  return 0;
-+}
-+
-+uint16x8_t __attribute__ ((noinline))
-+wrap_vdupq_n_u16 (uint16_t a)
-+{
-+  return vdupq_n_u16 (a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdupq_n_u16 ()
-+{
-+  uint16_t a = 1;
-+  uint16x8_t b;
-+  uint16_t c[8];
-+  int i;
-+
-+  b = wrap_vdupq_n_u16 (a);
-+  vst1q_u16 (c, b);
-+  for (i = 0; i < 8; i++)
-+    if (a != c[i])
-+      return 1;
-+  return 0;
-+}
-+
-+int32x2_t __attribute__ ((noinline))
-+wrap_vdup_n_s32 (int32_t a)
-+{
-+  return vdup_n_s32 (a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdup_n_s32 ()
-+{
-+  int32_t a = 1;
-+  int32x2_t b;
-+  int32_t c[2];
-+  int i;
-+
-+  b = wrap_vdup_n_s32 (a);
-+  vst1_s32 (c, b);
-+  for (i = 0; i < 2; i++)
-+    if (a != c[i])
-+      return 1;
-+  return 0;
-+}
-+
-+int32x4_t __attribute__ ((noinline))
-+wrap_vdupq_n_s32 (int32_t a)
-+{
-+  return vdupq_n_s32 (a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdupq_n_s32 ()
-+{
-+  int32_t a = 1;
-+  int32x4_t b;
-+  int32_t c[4];
-+  int i;
-+
-+  b = wrap_vdupq_n_s32 (a);
-+  vst1q_s32 (c, b);
-+  for (i = 0; i < 4; i++)
-+    if (a != c[i])
-+      return 1;
-+  return 0;
-+}
-+
-+uint32x2_t __attribute__ ((noinline))
-+wrap_vdup_n_u32 (uint32_t a)
-+{
-+  return vdup_n_u32 (a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdup_n_u32 ()
-+{
-+  uint32_t a = 1;
-+  uint32x2_t b;
-+  uint32_t c[2];
-+  int i;
-+
-+  b = wrap_vdup_n_u32 (a);
-+  vst1_u32 (c, b);
-+  for (i = 0; i < 2; i++)
-+    if (a != c[i])
-+      return 1;
-+  return 0;
-+}
-+
-+uint32x4_t __attribute__ ((noinline))
-+wrap_vdupq_n_u32 (uint32_t a)
-+{
-+  return vdupq_n_u32 (a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdupq_n_u32 ()
-+{
-+  uint32_t a = 1;
-+  uint32x4_t b;
-+  uint32_t c[4];
-+  int i;
-+
-+  b = wrap_vdupq_n_u32 (a);
-+  vst1q_u32 (c, b);
-+  for (i = 0; i < 4; i++)
-+    if (a != c[i])
-+      return 1;
-+  return 0;
-+}
-+
-+int64x1_t __attribute__ ((noinline))
-+wrap_vdup_n_s64 (int64_t a)
-+{
-+  return vdup_n_s64 (a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdup_n_s64 ()
-+{
-+  int64_t a = 1;
-+  int64x1_t b;
-+  int64_t c[1];
-+  int i;
-+
-+  b = wrap_vdup_n_s64 (a);
-+  vst1_s64 (c, b);
-+  for (i = 0; i < 1; i++)
-+    if (a != c[i])
-+      return 1;
-+  return 0;
-+}
-+
-+int64x2_t __attribute__ ((noinline))
-+wrap_vdupq_n_s64 (int64_t a)
-+{
-+  return vdupq_n_s64 (a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdupq_n_s64 ()
-+{
-+  int64_t a = 1;
-+  int64x2_t b;
-+  int64_t c[2];
-+  int i;
-+
-+  b = wrap_vdupq_n_s64 (a);
-+  vst1q_s64 (c, b);
-+  for (i = 0; i < 2; i++)
-+    if (a != c[i])
-+      return 1;
-+  return 0;
-+}
-+
-+uint64x1_t __attribute__ ((noinline))
-+wrap_vdup_n_u64 (uint64_t a)
-+{
-+  return vdup_n_u64 (a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdup_n_u64 ()
-+{
-+  uint64_t a = 1;
-+  uint64x1_t b;
-+  uint64_t c[1];
-+  int i;
-+
-+  b = wrap_vdup_n_u64 (a);
-+  vst1_u64 (c, b);
-+  for (i = 0; i < 1; i++)
-+    if (a != c[i])
-+      return 1;
-+  return 0;
-+}
-+
-+uint64x2_t __attribute__ ((noinline))
-+wrap_vdupq_n_u64 (uint64_t a)
-+{
-+  return vdupq_n_u64 (a);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdupq_n_u64 ()
-+{
-+  uint64_t a = 1;
-+  uint64x2_t b;
-+  uint64_t c[2];
-+  int i;
-+
-+  b = wrap_vdupq_n_u64 (a);
-+  vst1q_u64 (c, b);
-+  for (i = 0; i < 2; i++)
-+    if (a != c[i])
-+      return 1;
-+  return 0;
-+}
-+
-+int
-+main ()
-+{
-+  if (test_vdup_n_f32 ())
-+    abort ();
-+  if (test_vdup_n_f64 ())
-+    abort ();
-+  if (test_vdup_n_p8 ())
-+    abort ();
-+  if (test_vdup_n_u8 ())
-+    abort ();
-+  if (test_vdup_n_s8 ())
-+    abort ();
-+  if (test_vdup_n_p16 ())
-+    abort ();
-+  if (test_vdup_n_s16 ())
-+    abort ();
-+  if (test_vdup_n_u16 ())
-+    abort ();
-+  if (test_vdup_n_s32 ())
-+    abort ();
-+  if (test_vdup_n_u32 ())
-+    abort ();
-+  if (test_vdup_n_s64 ())
-+    abort ();
-+  if (test_vdup_n_u64 ())
-+    abort ();
-+  if (test_vdupq_n_f32 ())
-+    abort ();
-+  if (test_vdupq_n_f64 ())
-+    abort ();
-+  if (test_vdupq_n_p8 ())
-+    abort ();
-+  if (test_vdupq_n_u8 ())
-+    abort ();
-+  if (test_vdupq_n_s8 ())
-+    abort ();
-+  if (test_vdupq_n_p16 ())
-+    abort ();
-+  if (test_vdupq_n_s16 ())
-+    abort ();
-+  if (test_vdupq_n_u16 ())
-+    abort ();
-+  if (test_vdupq_n_s32 ())
-+    abort ();
-+  if (test_vdupq_n_u32 ())
-+    abort ();
-+  if (test_vdupq_n_s64 ())
-+    abort ();
-+  if (test_vdupq_n_u64 ())
-+    abort ();
-+  return 0;
-+}
-+
-+/* No asm checks for vdup_n_f32, vdupq_n_f32, vdup_n_f64 and vdupq_n_f64.
-+   Cannot force floating point value in general purpose regester.  */
-+
-+/* Asm check for test_vdup_n_p8, test_vdup_n_s8, test_vdup_n_u8.  */
-+/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.8b, w\[0-9\]+" 3 } } */
-+
-+/* Asm check for test_vdupq_n_p8, test_vdupq_n_s8, test_vdupq_n_u8.  */
-+/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.16b, w\[0-9\]+" 3 } } */
-+
-+/* Asm check for test_vdup_n_p16, test_vdup_n_s16, test_vdup_n_u16.  */
-+/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.4h, w\[0-9\]+" 3 } } */
-+
-+/* Asm check for test_vdupq_n_p16, test_vdupq_n_s16, test_vdupq_n_u16.  */
-+/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.8h, w\[0-9\]+" 3 } } */
-+
-+/* Asm check for test_vdup_n_s32, test_vdup_n_u32.  */
-+/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.2s, w\[0-9\]+" 2 } } */
-+
-+/* Asm check for test_vdupq_n_s32, test_vdupq_n_u32.  */
-+/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.4s, w\[0-9\]+" 2 } } */
-+
-+/* Asm check for test_vdup_n_s64, test_vdup_n_u64 are left out.
-+   Attempts to make the compiler generate "dup\\td\[0-9\]+, x\[0-9\]+"
-+   are not practical.  */
-+
-+/* Asm check for test_vdupq_n_s64, test_vdupq_n_u64.  */
-+/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.2d, x\[0-9\]+" 2 } } */
-+
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/test_frame_4.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_4.c
-@@ -0,0 +1,19 @@
-+/* Verify:
-+     * -fomit-frame-pointer.
-+     * without outgoing.
-+     * total frame size <= 512 but > 256.
-+     * number of callee-save reg >= 2.
-+     * we can use "stp !" to optimize stack adjustment.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-O2 -fomit-frame-pointer --save-temps" } */
-+
-+#include "test_frame_common.h"
-+
-+t_frame_pattern (test4, 400, "x19")
-+t_frame_run (test4)
-+
-+/* { dg-final { scan-assembler-times "stp\tx19, x30, \\\[sp, -\[0-9\]+\\\]!" 1 } } */
-+/* { dg-final { scan-assembler-times "ldp\tx19, x30, \\\[sp\\\], \[0-9\]+" 2 } } */
-+
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/fcsel_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/fcsel_1.c
-@@ -0,0 +1,22 @@
-+/* { dg-do compile } */
-+/* { dg-options " -O2 " } */
-+
-+float
-+f_1 (float a, float b, float c, float d)
-+{
-+  if (a > 0.0)
-+    return c;
-+  else
-+    return 2.0;
-+}
-+
-+double
-+f_2 (double a, double b, double c, double d)
-+{
-+  if (a > b)
-+    return c;
-+  else
-+    return d;
-+}
-+
-+/* { dg-final { scan-assembler-times "\tfcsel" 2 } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/vect-fp.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fp.c
-@@ -8,11 +8,11 @@
- 
- 
- #define DEFN_SETV(type) \
--		set_vector_##type (pR##type a, type n)   \
--		{ 				         \
--		  int i;			         \
--		  for (i=0; i<16; i++)		         \
--		    a[i] = n;				 \
-+		void set_vector_##type (pR##type a, type n)   \
-+		{					      \
-+		  int i;				      \
-+		  for (i=0; i<16; i++)			      \
-+		    a[i] = n;				      \
- 		}
- 
- #define DEFN_CHECKV(type) \
---- a/src/gcc/testsuite/gcc.target/aarch64/rev16_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/rev16_1.c
-@@ -0,0 +1,59 @@
-+/* { dg-options "-O2" } */
-+/* { dg-do run } */
-+
-+extern void abort (void);
-+
-+typedef unsigned int __u32;
-+
-+__u32
-+__rev16_32_alt (__u32 x)
-+{
-+  return (((__u32)(x) & (__u32)0xff00ff00UL) >> 8)
-+         | (((__u32)(x) & (__u32)0x00ff00ffUL) << 8);
-+}
-+
-+__u32
-+__rev16_32 (__u32 x)
-+{
-+  return (((__u32)(x) & (__u32)0x00ff00ffUL) << 8)
-+         | (((__u32)(x) & (__u32)0xff00ff00UL) >> 8);
-+}
-+
-+typedef unsigned long long __u64;
-+
-+__u64
-+__rev16_64_alt (__u64 x)
-+{
-+  return (((__u64)(x) & (__u64)0xff00ff00ff00ff00UL) >> 8)
-+         | (((__u64)(x) & (__u64)0x00ff00ff00ff00ffUL) << 8);
-+}
-+
-+__u64
-+__rev16_64 (__u64 x)
-+{
-+  return (((__u64)(x) & (__u64)0x00ff00ff00ff00ffUL) << 8)
-+         | (((__u64)(x) & (__u64)0xff00ff00ff00ff00UL) >> 8);
-+}
-+
-+int
-+main (void)
-+{
-+  volatile __u32 in32 = 0x12345678;
-+  volatile __u32 expected32 = 0x34127856;
-+  volatile __u64 in64 = 0x1234567890abcdefUL;
-+  volatile __u64 expected64 = 0x34127856ab90efcdUL;
-+
-+  if (__rev16_32 (in32) != expected32)
-+    abort ();
-+
-+  if (__rev16_32_alt (in32) != expected32)
-+    abort ();
-+
-+  if (__rev16_64 (in64) != expected64)
-+    abort ();
-+
-+  if (__rev16_64_alt (in64) != expected64)
-+    abort ();
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/vget_high_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/vget_high_1.c
-@@ -0,0 +1,60 @@
-+/* { dg-do run } */
-+/* { dg-options "-O3 -std=c99" } */
-+
-+#include <arm_neon.h>
-+
-+extern void abort (void);
-+
-+#define VARIANTS(VARIANT)				\
-+VARIANT (uint8_t, 8, uint8x8_t, uint8x16_t, u8)		\
-+VARIANT (uint16_t, 4, uint16x4_t, uint16x8_t, u16)	\
-+VARIANT (uint32_t, 2, uint32x2_t, uint32x4_t, u32)	\
-+VARIANT (uint64_t, 1, uint64x1_t, uint64x2_t, u64)	\
-+VARIANT (int8_t, 8, int8x8_t, int8x16_t, s8)		\
-+VARIANT (int16_t, 4, int16x4_t, int16x8_t, s16)		\
-+VARIANT (int32_t, 2, int32x2_t, int32x4_t, s32)		\
-+VARIANT (int64_t, 1, int64x1_t, int64x2_t, s64)		\
-+VARIANT (float32_t, 2, float32x2_t, float32x4_t, f32)	\
-+VARIANT (float64_t, 1, float64x1_t, float64x2_t, f64)
-+
-+
-+#define TESTMETH(BASETYPE, NUM64, TYPE64, TYPE128, SUFFIX)	\
-+int								\
-+test_vget_low_ ##SUFFIX (BASETYPE *data)			\
-+{								\
-+  BASETYPE temp [NUM64];					\
-+  TYPE128 vec = vld1q_##SUFFIX (data);				\
-+  TYPE64 high = vget_high_##SUFFIX (vec);			\
-+  vst1_##SUFFIX (temp, high);					\
-+  for (int i = 0; i < NUM64; i++)				\
-+    if (temp[i] != data[i + NUM64])				\
-+      return 1;							\
-+  return 0;							\
-+}
-+
-+VARIANTS (TESTMETH)
-+
-+#define CHECK(BASETYPE, NUM64, TYPE64, TYPE128, SUFFIX)		\
-+  if (test_vget_low_##SUFFIX (BASETYPE ## _ ## data) != 0)	\
-+    abort ();
-+
-+int
-+main (int argc, char **argv)
-+{
-+  uint8_t uint8_t_data[16] =
-+      { 1, 2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47 };
-+  uint16_t uint16_t_data[8] = { 1, 22, 333, 4444, 55555, 6666, 777, 88 };
-+  uint32_t uint32_t_data[4] = { 65537, 11, 70000, 23 };
-+  uint64_t uint64_t_data[2] = { 0xdeadbeefcafebabeULL, 0x0123456789abcdefULL };
-+  int8_t int8_t_data[16] =
-+      { -1, -3, -5, -7, 9, -11, -13, 15, -17, -19, 21, -23, 25, 27, -29, -31 };
-+  int16_t int16_t_data[8] = { -17, 19, 3, -999, 44048, 505, 9999, 1000};
-+  int32_t int32_t_data[4] = { 123456789, -987654321, -135792468, 975318642 };
-+  int64_t int64_t_data[2] = {0xfedcba9876543210LL, 0xdeadbabecafebeefLL };
-+  float32_t float32_t_data[4] = { 3.14159, 2.718, 1.414, 100.0 };
-+  float64_t float64_t_data[2] = { 1.01001000100001, 12345.6789 };
-+
-+  VARIANTS (CHECK);
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/vldN_dup_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/vldN_dup_1.c
-@@ -0,0 +1,84 @@
-+/* { dg-do run } */
-+/* { dg-options "-O3 -fno-inline" } */
-+
-+#include <arm_neon.h>
-+
-+extern void abort (void);
-+
-+#define VARIANTS(VARIANT, STRUCT)	\
-+VARIANT (uint8, , 8, _u8, STRUCT)	\
-+VARIANT (uint16, , 4, _u16, STRUCT)	\
-+VARIANT (uint32, , 2, _u32, STRUCT)	\
-+VARIANT (uint64, , 1, _u64, STRUCT)	\
-+VARIANT (int8, , 8, _s8, STRUCT)	\
-+VARIANT (int16, , 4, _s16, STRUCT)	\
-+VARIANT (int32, , 2, _s32, STRUCT)	\
-+VARIANT (int64, , 1, _s64, STRUCT)	\
-+VARIANT (poly8, , 8, _p8, STRUCT)	\
-+VARIANT (poly16, , 4, _p16, STRUCT)	\
-+VARIANT (float32, , 2, _f32, STRUCT)	\
-+VARIANT (float64, , 1, _f64, STRUCT)	\
-+VARIANT (uint8, q, 16, _u8, STRUCT)	\
-+VARIANT (uint16, q, 8, _u16, STRUCT)	\
-+VARIANT (uint32, q, 4, _u32, STRUCT)	\
-+VARIANT (uint64, q, 2, _u64, STRUCT)	\
-+VARIANT (int8, q, 16, _s8, STRUCT)	\
-+VARIANT (int16, q, 8, _s16, STRUCT)	\
-+VARIANT (int32, q, 4, _s32, STRUCT)	\
-+VARIANT (int64, q, 2, _s64, STRUCT)	\
-+VARIANT (poly8, q, 16, _p8, STRUCT)	\
-+VARIANT (poly16, q, 8, _p16, STRUCT)	\
-+VARIANT (float32, q, 4, _f32, STRUCT)	\
-+VARIANT (float64, q, 2, _f64, STRUCT)
-+
-+#define TESTMETH(BASE, Q, ELTS, SUFFIX, STRUCT)	\
-+int								\
-+test_vld##STRUCT##Q##_dup##SUFFIX (const BASE##_t *data)	\
-+{								\
-+  BASE##_t temp[ELTS];						\
-+  BASE##x##ELTS##x##STRUCT##_t vectors =			\
-+			   vld##STRUCT##Q##_dup##SUFFIX (data); \
-+  int i,j;							\
-+  for (i = 0; i < STRUCT; i++)					\
-+    {								\
-+      vst1##Q##SUFFIX (temp, vectors.val[i]);			\
-+      for (j = 0; j < ELTS; j++)				\
-+        if (temp[j] != data[i])					\
-+          return 1;						\
-+    }								\
-+  return 0;							\
-+}
-+
-+/* Tests of vld2_dup and vld2q_dup.  */
-+VARIANTS (TESTMETH, 2)
-+/* Tests of vld3_dup and vld3q_dup.  */
-+VARIANTS (TESTMETH, 3)
-+/* Tests of vld4_dup and vld4q_dup.  */
-+VARIANTS (TESTMETH, 4)
-+
-+#define CHECK(BASE, Q, ELTS, SUFFIX, STRUCT)			\
-+  if (test_vld##STRUCT##Q##_dup##SUFFIX (BASE ##_data) != 0)	\
-+    abort ();
-+
-+int
-+main (int argc, char **argv)
-+{
-+  uint8_t uint8_data[4] = { 7, 11, 13, 17 };
-+  uint16_t uint16_data[4] = { 257, 263, 269, 271 };
-+  uint32_t uint32_data[4] = { 65537, 65539, 65543, 65551 };
-+  uint64_t uint64_data[4] = { 0xdeadbeefcafebabeULL, 0x0123456789abcdefULL,
-+			      0xfedcba9876543210LL, 0xdeadbabecafebeefLL };
-+  int8_t int8_data[4] = { -1, 3, -5, 7 };
-+  int16_t int16_data[4] = { 257, -259, 261, -263 };
-+  int32_t int32_data[4] = { 123456789, -987654321, -135792468, 975318642 };
-+  int64_t *int64_data = (int64_t *)uint64_data;
-+  poly8_t poly8_data[4] = { 0, 7, 13, 18, };
-+  poly16_t poly16_data[4] = { 11111, 2222, 333, 44 };
-+  float32_t float32_data[4] = { 3.14159, 2.718, 1.414, 100.0 };
-+  float64_t float64_data[4] = { 1.010010001, 12345.6789, -9876.54321, 1.618 };
-+
-+  VARIANTS (CHECK, 2);
-+  VARIANTS (CHECK, 3);
-+  VARIANTS (CHECK, 4);
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/vdup_lane_2.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/vdup_lane_2.c
-@@ -0,0 +1,343 @@
-+/* Test vdup_lane intrinsics work correctly.  */
-+/* { dg-do run } */
-+/* { dg-options "-O1 --save-temps" } */
-+
-+#include <arm_neon.h>
-+
-+#define force_simd(V1) asm volatile ("mov %d0, %1.d[0]" \
-+         : "=w"(V1)                                     \
-+         : "w"(V1)                                      \
-+         : /* No clobbers */)
-+
-+extern void abort (void);
-+
-+float32_t __attribute__ ((noinline))
-+wrap_vdups_lane_f32_0 (float32x2_t dummy, float32x2_t a)
-+{
-+  return vdups_lane_f32 (a, 0);
-+}
-+
-+float32_t __attribute__ ((noinline))
-+wrap_vdups_lane_f32_1 (float32x2_t a)
-+{
-+  return vdups_lane_f32 (a, 1);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdups_lane_f32 ()
-+{
-+  float32x2_t a;
-+  float32_t b;
-+  float32_t c[2] = { 0.0, 1.0 };
-+
-+  a = vld1_f32 (c);
-+  b = wrap_vdups_lane_f32_0 (a, a);
-+  if (c[0] != b)
-+    return 1;
-+  b = wrap_vdups_lane_f32_1 (a);
-+  if (c[1] != b)
-+    return 1;
-+  return 0;
-+}
-+
-+float64_t __attribute__ ((noinline))
-+wrap_vdupd_lane_f64_0 (float64x1_t dummy, float64x1_t a)
-+{
-+  return vdupd_lane_f64 (a, 0);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdupd_lane_f64 ()
-+{
-+  float64x1_t a;
-+  float64_t b;
-+  float64_t c[1] = { 0.0 };
-+  a = vld1_f64 (c);
-+  b = wrap_vdupd_lane_f64_0 (a, a);
-+  if (c[0] != b)
-+    return 1;
-+  return 0;
-+}
-+
-+int8_t __attribute__ ((noinline))
-+wrap_vdupb_lane_s8_0 (int8x8_t dummy, int8x8_t a)
-+{
-+  int8_t result = vdupb_lane_s8 (a, 0);
-+  force_simd (result);
-+  return result;
-+}
-+
-+int8_t __attribute__ ((noinline))
-+wrap_vdupb_lane_s8_1 (int8x8_t a)
-+{
-+  int8_t result = vdupb_lane_s8 (a, 1);
-+  force_simd (result);
-+  return result;
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdupb_lane_s8 ()
-+{
-+  int8x8_t a;
-+  int8_t b;
-+  int8_t c[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
-+
-+  a = vld1_s8 (c);
-+  b = wrap_vdupb_lane_s8_0 (a, a);
-+  if (c[0] != b)
-+    return 1;
-+  b = wrap_vdupb_lane_s8_1 (a);
-+  if (c[1] != b)
-+    return 1;
-+
-+  return 0;
-+}
-+
-+uint8_t __attribute__ ((noinline))
-+wrap_vdupb_lane_u8_0 (uint8x8_t dummy, uint8x8_t a)
-+{
-+  uint8_t result = vdupb_lane_u8 (a, 0);
-+  force_simd (result);
-+  return result;
-+}
-+
-+uint8_t __attribute__ ((noinline))
-+wrap_vdupb_lane_u8_1 (uint8x8_t a)
-+{
-+  uint8_t result = vdupb_lane_u8 (a, 1);
-+  force_simd (result);
-+  return result;
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdupb_lane_u8 ()
-+{
-+  uint8x8_t a;
-+  uint8_t b;
-+  uint8_t c[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
-+
-+  a = vld1_u8 (c);
-+  b = wrap_vdupb_lane_u8_0 (a, a);
-+  if (c[0] != b)
-+    return 1;
-+  b = wrap_vdupb_lane_u8_1 (a);
-+  if (c[1] != b)
-+    return 1;
-+  return 0;
-+}
-+
-+int16_t __attribute__ ((noinline))
-+wrap_vduph_lane_s16_0 (int16x4_t dummy, int16x4_t a)
-+{
-+  int16_t result = vduph_lane_s16 (a, 0);
-+  force_simd (result);
-+  return result;
-+}
-+
-+int16_t __attribute__ ((noinline))
-+wrap_vduph_lane_s16_1 (int16x4_t a)
-+{
-+  int16_t result = vduph_lane_s16 (a, 1);
-+  force_simd (result);
-+  return result;
-+}
-+
-+int __attribute__ ((noinline))
-+test_vduph_lane_s16 ()
-+{
-+  int16x4_t a;
-+  int16_t b;
-+  int16_t c[4] = { 0, 1, 2, 3 };
-+
-+  a = vld1_s16 (c);
-+  b = wrap_vduph_lane_s16_0 (a, a);
-+  if (c[0] != b)
-+    return 1;
-+  b = wrap_vduph_lane_s16_1 (a);
-+  if (c[1] != b)
-+    return 1;
-+  return 0;
-+}
-+
-+uint16_t __attribute__ ((noinline))
-+wrap_vduph_lane_u16_0 (uint16x4_t dummy, uint16x4_t a)
-+{
-+  uint16_t result = vduph_lane_u16 (a, 0);
-+  force_simd (result);
-+  return result;
-+}
-+
-+uint16_t __attribute__ ((noinline))
-+wrap_vduph_lane_u16_1 (uint16x4_t a)
-+{
-+  uint16_t result = vduph_lane_u16 (a, 1);
-+  force_simd (result);
-+  return result;
-+}
-+
-+int __attribute__ ((noinline))
-+test_vduph_lane_u16 ()
-+{
-+  uint16x4_t a;
-+  uint16_t b;
-+  uint16_t c[4] = { 0, 1, 2, 3 };
-+
-+  a = vld1_u16 (c);
-+  b = wrap_vduph_lane_u16_0 (a, a);
-+  if (c[0] != b)
-+    return 1;
-+  b = wrap_vduph_lane_u16_1 (a);
-+  if (c[1] != b)
-+    return 1;
-+  return 0;
-+}
-+
-+int32_t __attribute__ ((noinline))
-+wrap_vdups_lane_s32_0 (int32x2_t dummy, int32x2_t a)
-+{
-+  int32_t result = vdups_lane_s32 (a, 0);
-+  force_simd (result);
-+  return result;
-+}
-+
-+int32_t __attribute__ ((noinline))
-+wrap_vdups_lane_s32_1 (int32x2_t a)
-+{
-+  int32_t result = vdups_lane_s32 (a, 1);
-+  force_simd (result);
-+  return result;
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdups_lane_s32 ()
-+{
-+  int32x2_t a;
-+  int32_t b;
-+  int32_t c[2] = { 0, 1 };
-+
-+  a = vld1_s32 (c);
-+  b = wrap_vdups_lane_s32_0 (vcreate_s32 (0), a);
-+  if (c[0] != b)
-+    return 1;
-+  b = wrap_vdups_lane_s32_1 (a);
-+  if (c[1] != b)
-+    return 1;
-+  return 0;
-+}
-+
-+uint32_t __attribute__ ((noinline))
-+wrap_vdups_lane_u32_0 (uint32x2_t dummy, uint32x2_t a)
-+{
-+  uint32_t result = vdups_lane_u32 (a, 0);
-+  force_simd (result);
-+  return result;
-+}
-+
-+uint32_t __attribute__ ((noinline))
-+wrap_vdups_lane_u32_1 (uint32x2_t a)
-+{
-+  uint32_t result = vdups_lane_u32 (a, 1);
-+  force_simd (result);
-+  return result;
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdups_lane_u32 ()
-+{
-+  uint32x2_t a;
-+  uint32_t b;
-+  uint32_t c[2] = { 0, 1 };
-+  a = vld1_u32 (c);
-+  b = wrap_vdups_lane_u32_0 (a, a);
-+  if (c[0] != b)
-+    return 1;
-+  b = wrap_vdups_lane_u32_1 (a);
-+  if (c[1] != b)
-+    return 1;
-+  return 0;
-+}
-+
-+uint64_t __attribute__ ((noinline))
-+wrap_vdupd_lane_u64_0 (uint64x1_t dummy, uint64x1_t a)
-+{
-+  return vdupd_lane_u64 (a, 0);;
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdupd_lane_u64 ()
-+{
-+  uint64x1_t a;
-+  uint64_t b;
-+  uint64_t c[1] = { 0 };
-+
-+  a = vld1_u64 (c);
-+  b = wrap_vdupd_lane_u64_0 (a, a);
-+  if (c[0] != b)
-+    return 1;
-+  return 0;
-+}
-+
-+int64_t __attribute__ ((noinline))
-+wrap_vdupd_lane_s64_0 (uint64x1_t dummy, int64x1_t a)
-+{
-+  return vdupd_lane_u64 (a, 0);
-+}
-+
-+int __attribute__ ((noinline))
-+test_vdupd_lane_s64 ()
-+{
-+  int64x1_t a;
-+  int64_t b;
-+  int64_t c[1] = { 0 };
-+
-+  a = vld1_s64 (c);
-+  b = wrap_vdupd_lane_s64_0 (a, a);
-+  if (c[0] != b)
-+    return 1;
-+  return 0;
-+}
-+
-+int
-+main ()
-+{
-+  if (test_vdups_lane_f32 ())
-+    abort ();
-+  if (test_vdupd_lane_f64 ())
-+    abort ();
-+  if (test_vdupb_lane_s8 ())
-+    abort ();
-+  if (test_vdupb_lane_u8 ())
-+    abort ();
-+  if (test_vduph_lane_s16 ())
-+    abort ();
-+  if (test_vduph_lane_u16 ())
-+    abort ();
-+  if (test_vdups_lane_s32 ())
-+    abort ();
-+  if (test_vdups_lane_u32 ())
-+    abort ();
-+  if (test_vdupd_lane_s64 ())
-+    abort ();
-+  if (test_vdupd_lane_u64 ())
-+    abort ();
-+  return 0;
-+}
-+
-+/* Asm check for vdupb_lane_s8, vdupb_lane_u8.  */
-+/* { dg-final { scan-assembler-not "dup\\tb\[0-9\]+, v\[0-9\]+\.b\\\[0\\\]" } } */
-+/* { dg-final { scan-assembler-times "dup\\tb\[0-9\]+, v\[0-9\]+\.b\\\[1\\\]" 2 } } */
-+
-+/* Asm check for vduph_lane_h16, vduph_lane_h16.  */
-+/* { dg-final { scan-assembler-not "dup\\th\[0-9\]+, v\[0-9\]+\.h\\\[0\\\]" } } */
-+/* { dg-final { scan-assembler-times "dup\\th\[0-9\]+, v\[0-9\]+\.h\\\[1\\\]" 2 } } */
-+
-+/* Asm check for vdups_lane_f32, vdups_lane_s32, vdups_lane_u32.  */
-+/* Can't generate "dup s<n>, v<m>[0]" for vdups_lane_s32 and vdups_lane_u32.  */
-+/* { dg-final { scan-assembler-times "dup\\ts\[0-9\]+, v\[0-9\]+\.s\\\[0\\\]" 1} } */
-+/* { dg-final { scan-assembler-times "dup\\ts\[0-9\]+, v\[0-9\]+\.s\\\[1\\\]" 3 } } */
-+
-+/* Asm check for vdupd_lane_f64, vdupd_lane_s64, vdupd_lane_u64.  */
-+/* Attempts to make the compiler generate vdupd are not practical.  */
-+/* { dg-final { scan-assembler-not "dup\\td\[0-9\]+, v\[0-9\]+\.d\\\[0\\\]" } }
-+
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/vbslq_u64_2.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/vbslq_u64_2.c
-@@ -0,0 +1,22 @@
-+/* Test vbslq_u64 can be folded.  */
-+/* { dg-do assemble } */
-+/* { dg-options "--save-temps -O3" } */
-+#include <arm_neon.h>
-+
-+/* Folds to BIC.  */
-+
-+int32x4_t
-+half_fold_int (uint32x4_t mask)
-+{
-+  int32x4_t a = {0, 0, 0, 0};
-+  int32x4_t b = {2, 4, 8, 16};
-+  return vbslq_s32 (mask, a, b);
-+}
-+
-+/* { dg-final { scan-assembler-not "bsl\\tv" } } */
-+/* { dg-final { scan-assembler-not "bit\\tv" } } */
-+/* { dg-final { scan-assembler-not "bif\\tv" } } */
-+/* { dg-final { scan-assembler "bic\\tv" } } */
-+
-+/* { dg-final { cleanup-saved-temps } } */
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/vdup_n_2.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/vdup_n_2.c
-@@ -0,0 +1,28 @@
-+/* { dg-do run } */
-+/* { dg-options "-O2 -fno-inline --save-temps" } */
-+
-+extern void abort (void);
-+
-+typedef float float32x2_t __attribute__ ((__vector_size__ ((8))));
-+typedef unsigned int uint32x2_t __attribute__ ((__vector_size__ ((8))));
-+
-+float32x2_t
-+test_dup_1 (float32x2_t in)
-+{
-+  return __builtin_shuffle (in, (uint32x2_t) {1, 1});
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  float32x2_t test = {2.718, 3.141};
-+  float32x2_t res = test_dup_1 (test);
-+  if (res[0] != test[1] || res[1] != test[1])
-+    abort ();
-+  return 0;
-+}
-+
-+/* { dg-final { scan-assembler-times "\[ \t\]*dup\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.s\\\[\[01\]\\\]" 1 } } */
-+/* { dg-final { scan-assembler-not "zip" } } */
-+/* { dg-final { cleanup-saved-temps } } */
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/test_frame_5.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_5.c
-@@ -0,0 +1,13 @@
-+/* Verify:
-+     * -fomit-frame-pointer.
-+     * with outgoing.
-+     * total frame size <= 512.
-+     * one subtraction of the whole frame size.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-O2 -fomit-frame-pointer" } */
-+
-+#include "test_frame_common.h"
-+
-+t_frame_pattern_outgoing (test5, 300, "x19", 8, a[8])
-+t_frame_run (test5)
---- a/src/gcc/testsuite/gcc.target/aarch64/vld1-vst1_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/vld1-vst1_1.c
-@@ -5,48 +5,54 @@
- 
- extern void abort (void);
- 
--int __attribute__ ((noinline))
--test_vld1_vst1 ()
--{
--  int8x8_t a;
--  int8x8_t b;
--  int i = 0;
--  int8_t c[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
--  int8_t d[8];
--  a = vld1_s8 (c);
--  asm volatile ("":::"memory");
--  vst1_s8 (d, a);
--  asm volatile ("":::"memory");
--  for (; i < 8; i++)
--    if (c[i] != d[i])
--      return 1;
--  return 0;
-+#define TESTMETH(TYPE, NUM, BASETYPE, SUFFIX)	\
-+int __attribute__ ((noinline))			\
-+test_vld1_vst1##SUFFIX ()			\
-+{						\
-+  TYPE vec;					\
-+  int i = 0;					\
-+  BASETYPE src[NUM];				\
-+  BASETYPE dest[NUM];				\
-+  for (i = 0; i < NUM; i++)			\
-+    src[i] = 2*i + 1;				\
-+  asm volatile ("":::"memory");			\
-+  vec = vld1 ## SUFFIX (src);			\
-+  asm volatile ("":::"memory");			\
-+  vst1 ## SUFFIX (dest, vec);			\
-+  asm volatile ("":::"memory");			\
-+  for (i = 0; i < NUM; i++)			\
-+    if (src[i] != dest[i])			\
-+      return 1;					\
-+  return 0;					\
- }
- 
--int __attribute__ ((noinline))
--test_vld1q_vst1q ()
--{
--  int16x8_t a;
--  int16x8_t b;
--  int i = 0;
--  int16_t c[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
--  int16_t d[8];
--  a = vld1q_s16 (c);
--  asm volatile ("":::"memory");
--  vst1q_s16 (d, a);
--  asm volatile ("":::"memory");
--  for (; i < 8; i++)
--    if (c[i] != d[i])
--      return 1;
--  return 0;
--}
-+#define VARIANTS(THING)			\
-+THING (int8x8_t, 8, int8_t, _s8)	\
-+THING (uint8x8_t, 8, uint8_t, _u8)	\
-+THING (int16x4_t, 4, int16_t, _s16)	\
-+THING (uint16x4_t, 4, uint16_t, _u16)	\
-+THING (int32x2_t, 2, int32_t, _s32)	\
-+THING (uint32x2_t, 2, uint32_t, _u32)	\
-+THING (float32x2_t, 2, float32_t, _f32) \
-+THING (int8x16_t, 16, int8_t, q_s8)	\
-+THING (uint8x16_t, 16, uint8_t, q_u8)	\
-+THING (int16x8_t, 8, int16_t, q_s16)	\
-+THING (uint16x8_t, 8, uint16_t, q_u16)	\
-+THING (int32x4_t, 4, int32_t, q_s32)	\
-+THING (uint32x4_t, 4, uint32_t, q_u32)	\
-+THING (int64x2_t, 2, int64_t, q_s64)	\
-+THING (uint64x2_t, 2, uint64_t, q_u64)	\
-+THING (float64x2_t, 2, float64_t, q_f64)
- 
-+VARIANTS (TESTMETH)
-+
-+#define DOTEST(TYPE, NUM, BASETYPE, SUFFIX)	\
-+  if (test_vld1_vst1##SUFFIX ())		\
-+    abort ();
-+
- int
- main ()
- {
--  if (test_vld1_vst1 ())
--    abort ();
--  if (test_vld1q_vst1q ())
--    abort ();
-+  VARIANTS (DOTEST);
-   return 0;
- }
---- a/src/gcc/testsuite/gcc.target/aarch64/cvtf_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/cvtf_1.c
-@@ -0,0 +1,95 @@
-+/* { dg-do run } */
-+/* { dg-options "-save-temps -fno-inline -O1" } */
-+
-+#define FCVTDEF(ftype,itype) \
-+void \
-+cvt_##itype##_to_##ftype (itype a, ftype b)\
-+{\
-+  ftype c;\
-+  c = (ftype) a;\
-+  if ( (c - b) > 0.00001) abort();\
-+}
-+
-+#define force_simd_for_float(v) asm volatile ("mov %s0, %1.s[0]" :"=w" (v) :"w" (v) :)
-+#define force_simd_for_double(v) asm volatile ("mov %d0, %1.d[0]" :"=w" (v) :"w" (v) :)
-+
-+#define FCVTDEF_SISD(ftype,itype) \
-+void \
-+cvt_##itype##_to_##ftype##_sisd (itype a, ftype b)\
-+{\
-+  ftype c;\
-+  force_simd_for_##ftype(a);\
-+  c = (ftype) a;\
-+  if ( (c - b) > 0.00001) abort();\
-+}
-+
-+#define FCVT(ftype,itype,ival,fval) cvt_##itype##_to_##ftype (ival, fval);
-+#define FCVT_SISD(ftype,itype,ival,fval) cvt_##itype##_to_##ftype##_sisd (ival, fval);
-+
-+typedef int int32_t;
-+typedef unsigned int uint32_t;
-+typedef long long int int64_t;
-+typedef unsigned long long int uint64_t;
-+
-+extern void abort();
-+
-+FCVTDEF (float, int32_t)
-+/* { dg-final { scan-assembler "scvtf\ts\[0-9\]+,\ w\[0-9\]+" } } */
-+FCVTDEF (float, uint32_t)
-+/* { dg-final { scan-assembler "ucvtf\ts\[0-9\]+,\ w\[0-9\]+" } } */
-+FCVTDEF (double, int32_t)
-+/* "scvtf\td\[0-9\]+,\ w\[0-9\]+" */
-+FCVTDEF (double, uint32_t)
-+/* "ucvtf\td\[0-9\]+,\ w\[0-9\]+" */
-+FCVTDEF (float, int64_t)
-+/* "scvtf\ts\[0-9\]+,\ x\[0-9\]+" */
-+FCVTDEF (float, uint64_t)
-+/* "ucvtf\ts\[0-9\]+,\ x\[0-9\]+" */
-+FCVTDEF (double, int64_t)
-+/* { dg-final { scan-assembler "scvtf\td\[0-9\]+,\ x\[0-9\]+" } } */
-+FCVTDEF (double, uint64_t)
-+/* { dg-final { scan-assembler "ucvtf\td\[0-9\]+,\ x\[0-9\]+" } } */
-+FCVTDEF_SISD (float, int32_t)
-+/* { dg-final { scan-assembler "scvtf\ts\[0-9\]+,\ s\[0-9\]+" } } */
-+FCVTDEF_SISD (double, int64_t)
-+/* { dg-final { scan-assembler "scvtf\td\[0-9\]+,\ d\[0-9\]+" } } */
-+FCVTDEF_SISD (float, uint32_t)
-+/* { dg-final { scan-assembler "ucvtf\ts\[0-9\]+,\ s\[0-9\]+" } } */
-+FCVTDEF_SISD (double, uint64_t)
-+/* { dg-final { scan-assembler "ucvtf\td\[0-9\]+,\ d\[0-9\]+" } } */
-+FCVTDEF_SISD (float, int64_t)
-+/* { dg-final { scan-assembler-times "scvtf\ts\[0-9\]+,\ x\[0-9\]+" 2 } } */
-+FCVTDEF_SISD (float, uint64_t)
-+/* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\]+,\ x\[0-9\]+" 2 } } */
-+FCVTDEF_SISD (double, int32_t)
-+/* { dg-final { scan-assembler-times "scvtf\td\[0-9\]+,\ w\[0-9\]+" 2 } } */
-+FCVTDEF_SISD (double, uint32_t)
-+/* { dg-final { scan-assembler-times "ucvtf\td\[0-9\]+,\ w\[0-9\]+" 2 } } */
-+
-+int32_t ival = -1234;
-+int64_t llival = -13031303L;
-+uint32_t uival = 1234;
-+uint64_t ullival = 13031303L;
-+
-+int main ()
-+{
-+  float x;
-+  double y;
-+
-+  FCVT (float, int32_t, ival, -1234.0);
-+  FCVT (float, uint32_t, uival, 1234.0);
-+  FCVT (float, int64_t, llival, -13031303.0);
-+  FCVT (float, uint64_t, ullival, 13031303.0);
-+  FCVT (double, int32_t, ival, -1234.0);
-+  FCVT (double, uint32_t, uival, 1234.0);
-+  FCVT (double, int64_t, llival, -13031303.0);
-+  FCVT (double, uint64_t, ullival, 13031303.0);
-+  FCVT_SISD (float, int32_t, ival, -1234.0);
-+  FCVT_SISD (double, int64_t, llival, -13031303.0);
-+  FCVT_SISD (float, uint32_t, uival, 1234.0);
-+  FCVT_SISD (double, uint64_t, ullival, 13031303.0);
-+
-+  return 0;
-+}
-+
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/reload-valid-spoff.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/reload-valid-spoff.c
-@@ -17,6 +17,11 @@
- };
- typedef struct _IO_FILE FILE;
- extern char *fgets (char *__restrict __s, int __n, FILE *__restrict __stream);
-+extern void *memset (void *s, int c, size_t n);
-+extern void *memcpy (void *dest, const void *src, size_t n);
-+extern int fprintf (FILE *stream, const char *format, ...);
-+extern char * safe_strncpy (char *dst, const char *src, size_t size);
-+extern size_t strlen (const char *s);
- extern struct _IO_FILE *stderr;
- extern int optind;
- struct aftype {
---- a/src/gcc/testsuite/gcc.target/aarch64/tail_indirect_call_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/tail_indirect_call_1.c
-@@ -0,0 +1,18 @@
-+/* { dg-do compile } */
-+/* { dg-options "-O2" } */
-+
-+typedef void FP (int);
-+
-+/* { dg-final { scan-assembler "br" } } */
-+/* { dg-final { scan-assembler-not "blr" } } */
-+void
-+f1 (FP fp, int n)
-+{
-+  (fp) (n);
-+}
-+
-+void
-+f2 (int n, FP fp)
-+{
-+  (fp) (n);
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/vqdml_lane_intrinsics-bad_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/vqdml_lane_intrinsics-bad_1.c
-@@ -0,0 +1,54 @@
-+/* { dg-do compile } */
-+
-+#include "arm_neon.h"
-+
-+int32x4_t
-+foo (int32x4_t a, int16x4_t b, int16x4_t c, int d)
-+{
-+  return vqdmlal_lane_s16 (a, b, c, d);
-+}
-+
-+int32x4_t
-+foo1 (int32x4_t a, int16x4_t b, int16x8_t c, int d)
-+{
-+  return vqdmlal_laneq_s16 (a, b, c, d);
-+}
-+
-+int32x4_t
-+foo2 (int32x4_t a, int16x4_t b, int16x4_t c, int d)
-+{
-+  return vqdmlsl_lane_s16 (a, b, c, d);
-+}
-+
-+int32x4_t
-+foo3 (int32x4_t a, int16x4_t b, int16x8_t c, int d)
-+{
-+  return vqdmlsl_laneq_s16 (a, b, c, d);
-+}
-+
-+int32x4_t
-+foo4 (int32x4_t a, int16x8_t b, int16x4_t c, int d)
-+{
-+  return vqdmlal_high_lane_s16 (a, b, c, d);
-+}
-+
-+int32x4_t
-+foo5 (int32x4_t a, int16x8_t b, int16x4_t c, int d)
-+{
-+  return vqdmlsl_high_lane_s16 (a, b, c, d);
-+}
-+
-+int32x4_t
-+foo6 (int32x4_t a, int16x8_t b, int16x8_t c, int d)
-+{
-+  return vqdmlal_high_laneq_s16 (a, b, c, d);
-+}
-+
-+int32x4_t
-+foo7 (int32x4_t a, int16x8_t b, int16x8_t c, int d)
-+{
-+  return vqdmlsl_high_laneq_s16 (a, b, c, d);
-+}
-+
-+
-+/* { dg-excess-errors "incompatible type for argument" } */
---- a/src/gcc/testsuite/gcc.target/aarch64/test_frame_6.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_6.c
-@@ -0,0 +1,20 @@
-+/* Verify:
-+     * -fomit-frame-pointer.
-+     * without outgoing.
-+     * total frame size > 512.
-+     * number of callee-saved reg == 1.
-+     * split stack adjustment into two subtractions.
-+       the second subtraction should use "str !".  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-O2 -fomit-frame-pointer --save-temps" } */
-+
-+#include "test_frame_common.h"
-+
-+t_frame_pattern (test6, 700, )
-+t_frame_run (test6)
-+
-+/* { dg-final { scan-assembler-times "str\tx30, \\\[sp, -\[0-9\]+\\\]!" 2 } } */
-+/* { dg-final { scan-assembler-times "ldr\tx30, \\\[sp\\\], \[0-9\]+" 3 } } */
-+
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/test_frame_common.h
-+++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_common.h
-@@ -0,0 +1,94 @@
-+extern void abort ();
-+
-+#define CVT(v) ((unsigned char)(v))
-+
-+static void __attribute__((noinline))
-+check_args_8 (int a0, int a1, int a2, int a3, int a4, int a5, int a6, int a7,
-+	      int a8)
-+{
-+  if (a0 != 0
-+      || a1 != 1
-+      || a2 != 2
-+      || a3 != 3
-+      || a4 != 4
-+      || a5 != 5
-+      || a6 != 6
-+      || a7 != 7
-+      || a8 != 8)
-+    abort ();
-+}
-+
-+static void __attribute__((noinline))
-+check_args_24 (int a0, int a1, int a2, int a3, int a4, int a5, int a6, int a7,
-+	       int a8, int a9, int a10)
-+{
-+  if (a0 != 0
-+      || a1 != 1
-+      || a2 != 2
-+      || a3 != 3
-+      || a4 != 4
-+      || a5 != 5
-+      || a6 != 6
-+      || a7 != 7
-+      || a8 != 8
-+      || a9 != 9
-+      || a10 != 10)
-+    abort ();
-+}
-+
-+void __attribute__ ((noinline))
-+initialize_array (unsigned char *a, int len)
-+{
-+  int i;
-+
-+  for (i = 0; i < (len / 2); i++)
-+    {
-+      a[i] = i;
-+      a[len - i - 1] = i;
-+    }
-+
-+  return;
-+}
-+
-+#define t_frame_pattern(name, local_size, callee_saved)\
-+int \
-+name (void)\
-+{\
-+  unsigned char a[local_size];\
-+  initialize_array (a, local_size); \
-+  __asm__ ("":::callee_saved); \
-+  if (a[0] != a[local_size - 1] \
-+      || a[0] != 0) \
-+    return 0; \
-+  if (a[local_size / 2 - 1] != a[local_size / 2] \
-+      || a[local_size / 2 - 1] != CVT (local_size / 2 - 1)) \
-+    return 0; \
-+  return 1; \
-+}
-+
-+#define t_frame_pattern_outgoing(name, local_size, callee_saved, out_going_num, ...)\
-+int \
-+name (void)\
-+{\
-+  unsigned char a[local_size];\
-+  initialize_array (a, local_size); \
-+  __asm__ ("":::callee_saved); \
-+  if (a[0] != a[local_size - 1] \
-+      || a[0] != 0) \
-+    return 0; \
-+  if (a[local_size / 2 - 1] != a[local_size / 2] \
-+      || a[local_size / 2 - 1] != CVT (local_size / 2 - 1)) \
-+    return 0; \
-+  check_args_ ## out_going_num (a[0], a[1], a[2], a[3], a[4], a[5], a[6],\
-+				a[7], __VA_ARGS__); \
-+  return 1; \
-+}
-+
-+#define t_frame_run(name) \
-+int \
-+main (int argc, char **argv) \
-+{\
-+  if (!name ())\
-+    abort ();\
-+  return 0;\
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/vstN_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/vstN_1.c
-@@ -0,0 +1,76 @@
-+/* { dg-do run } */
-+/* { dg-options "-O3" } */
-+
-+#include <arm_neon.h>
-+
-+extern void abort (void);
-+
-+#define TESTMETH(BASE, ELTS, STRUCT, SUFFIX)		\
-+int __attribute__ ((noinline))				\
-+test_vst##STRUCT##SUFFIX ()				\
-+{							\
-+  BASE##_t src[ELTS * STRUCT];				\
-+  BASE##_t dest[ELTS * STRUCT];				\
-+  BASE##x##ELTS##x##STRUCT##_t vectors;			\
-+  int i,j;						\
-+  for (i = 0; i < STRUCT * ELTS; i++)			\
-+    src [i] = (BASE##_t) 2*i + 1;			\
-+  for (i = 0; i < STRUCT; i++)				\
-+    vectors.val[i] = vld1##SUFFIX (&src[i*ELTS]);	\
-+  asm volatile ("" : : : "memory");			\
-+  vst##STRUCT##SUFFIX (dest, vectors);			\
-+  asm volatile ("" : : : "memory");			\
-+  for (i = 0; i < STRUCT; i++)				\
-+    {							\
-+      for (j = 0; j < ELTS; j++)			\
-+        if (src[i*ELTS + j] != dest[i + STRUCT*j])	\
-+          return 1;					\
-+    }							\
-+  return 0;						\
-+}
-+
-+#define VARIANTS(VARIANT, STRUCT)	\
-+VARIANT (uint8, 8, STRUCT, _u8)		\
-+VARIANT (uint16, 4, STRUCT, _u16)	\
-+VARIANT (uint32, 2, STRUCT, _u32)	\
-+VARIANT (uint64, 1, STRUCT, _u64)	\
-+VARIANT (int8, 8, STRUCT, _s8)		\
-+VARIANT (int16, 4, STRUCT, _s16)	\
-+VARIANT (int32, 2, STRUCT, _s32)	\
-+VARIANT (int64, 1, STRUCT, _s64)	\
-+VARIANT (poly8, 8, STRUCT, _p8)		\
-+VARIANT (poly16, 4, STRUCT, _p16)	\
-+VARIANT (float32, 2, STRUCT, _f32)	\
-+VARIANT (float64, 1, STRUCT, _f64)	\
-+VARIANT (uint8, 16, STRUCT, q_u8)	\
-+VARIANT (uint16, 8, STRUCT, q_u16)	\
-+VARIANT (uint32, 4, STRUCT, q_u32)	\
-+VARIANT (uint64, 2, STRUCT, q_u64)	\
-+VARIANT (int8, 16, STRUCT, q_s8)	\
-+VARIANT (int16, 8, STRUCT, q_s16)	\
-+VARIANT (int32, 4, STRUCT, q_s32)	\
-+VARIANT (int64, 2, STRUCT, q_s64)	\
-+VARIANT (poly8, 16, STRUCT, q_p8)	\
-+VARIANT (poly16, 8, STRUCT, q_p16)	\
-+VARIANT (float32, 4, STRUCT, q_f32)	\
-+VARIANT (float64, 2, STRUCT, q_f64)
-+
-+/* Tests of vst2 and vst2q.  */
-+VARIANTS (TESTMETH, 2)
-+/* Tests of vst3 and vst3q.  */
-+VARIANTS (TESTMETH, 3)
-+/* Tests of vst4 and vst4q.  */
-+VARIANTS (TESTMETH, 4)
-+
-+#define CHECK(BASE, ELTS, STRUCT, SUFFIX)	\
-+  if (test_vst##STRUCT##SUFFIX () != 0)		\
-+    abort ();
-+
-+int
-+main (int argc, char **argv)
-+{
-+  VARIANTS (CHECK, 2)
-+  VARIANTS (CHECK, 3)
-+  VARIANTS (CHECK, 4)
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin.c
-@@ -8,11 +8,11 @@
- #include "vect-fmaxv-fminv.x"
- 
- #define DEFN_SETV(type) \
--		set_vector_##type (pR##type a, type n)   \
--		{ 				         \
--		  int i;			         \
--		  for (i=0; i<16; i++)		         \
--		    a[i] = n;				 \
-+		void set_vector_##type (pR##type a, type n)   \
-+		{					      \
-+		  int i;				      \
-+		  for (i=0; i<16; i++)			      \
-+		    a[i] = n;				      \
- 		}
- 
- #define DEFN_CHECKV(type) \
---- a/src/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c
-@@ -193,7 +193,6 @@
-   return b;
- }
- /* { dg-final { scan-assembler "sshr\td\[0-9\]+,\ d\[0-9\]+,\ 63" } } */
--/* { dg-final { scan-assembler "shl\td\[0-9\]+,\ d\[0-9\]+,\ 1" } } */
- 
- Int32x1
- test_corners_sisd_si (Int32x1 b)
-@@ -207,7 +206,6 @@
-   return b;
- }
- /* { dg-final { scan-assembler "sshr\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 31" } } */
--/* { dg-final { scan-assembler "shl\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 1" } } */
- 
- 
- 
---- a/src/gcc/testsuite/gcc.target/aarch64/vbslq_f64_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/vbslq_f64_1.c
-@@ -0,0 +1,21 @@
-+/* Test vbslq_f64 can be folded.  */
-+/* { dg-do assemble } */
-+/* { dg-options "--save-temps -O3" } */
-+
-+#include <arm_neon.h>
-+
-+/* Folds to ret.  */
-+
-+float32x4_t
-+fold_me (float32x4_t a, float32x4_t b)
-+{
-+  uint32x4_t mask = {-1, -1, -1, -1};
-+  return vbslq_f32 (mask, a, b);
-+}
-+
-+/* { dg-final { scan-assembler-not "bsl\\tv" } } */
-+/* { dg-final { scan-assembler-not "bit\\tv" } } */
-+/* { dg-final { scan-assembler-not "bif\\tv" } } */
-+
-+/* { dg-final { cleanup-saved-temps } } */
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/vect-ld1r.x
-+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-ld1r.x
-@@ -7,7 +7,7 @@
-     for (i = 0; i < 8 / sizeof (TYPE); i++) \
-       output[i] = *a; \
-   } \
--  foo_ ## TYPE ## _q (TYPE *a, TYPE *output) \
-+  void foo_ ## TYPE ## _q (TYPE *a, TYPE *output) \
-   { \
-     int i; \
-     for (i = 0; i < 32 / sizeof (TYPE); i++) \
---- a/src/gcc/testsuite/gcc.target/aarch64/test_frame_10.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_10.c
-@@ -0,0 +1,21 @@
-+/* Verify:
-+     * -fomit-frame-pointer.
-+     * with outgoing.
-+     * total frame size > 512.
-+       area except outgoing <= 512
-+     * number of callee-saved reg >= 2.
-+     * Split stack adjustment into two subtractions.
-+       the first subtractions could be optimized into "stp !".  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-O2 -fomit-frame-pointer --save-temps" } */
-+
-+#include "test_frame_common.h"
-+
-+t_frame_pattern_outgoing (test10, 480, "x19", 24, a[8], a[9], a[10])
-+t_frame_run (test10)
-+
-+/* { dg-final { scan-assembler-times "stp\tx19, x30, \\\[sp, -\[0-9\]+\\\]!" 1 } } */
-+/* { dg-final { scan-assembler-times "ldp\tx19, x30, \\\[sp\\\], \[0-9\]+" 1 } } */
-+
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/vrnd_f64_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/vrnd_f64_1.c
-@@ -0,0 +1,105 @@
-+/* Test vrnd_f64 works correctly.  */
-+/* { dg-do run } */
-+/* { dg-options "--save-temps" } */
-+
-+#include "arm_neon.h"
-+
-+extern void abort (void);
-+
-+/* Bit offset to round mode field in FPCR.  */
-+#define RMODE_START 22
-+
-+#define FPROUNDING_ZERO 3
-+
-+/* Set RMODE field of FPCR control register
-+   to rounding mode passed.  */
-+void __inline __attribute__ ((__always_inline__))
-+set_rounding_mode (uint32_t mode)
-+{
-+  uint32_t r;
-+
-+  /* Read current FPCR.  */
-+  asm volatile ("mrs %[r], fpcr" : [r] "=r" (r) : :);
-+
-+  /* Clear rmode.  */
-+  r &= ~(3 << RMODE_START);
-+  /* Calculate desired FPCR.  */
-+  r |= mode << RMODE_START;
-+
-+  /* Write desired FPCR back.  */
-+  asm volatile ("msr fpcr, %[r]" : : [r] "r" (r) :);
-+}
-+
-+float64x1_t __attribute__ ((noinline))
-+compare_f64 (float64x1_t passed, float64_t expected)
-+{
-+  return (__builtin_fabs (vget_lane_f64 (passed, 0) - expected)
-+	  > __DBL_EPSILON__);
-+}
-+
-+void __attribute__ ((noinline))
-+run_round_tests (float64x1_t *tests,
-+		 float64_t expectations[][6])
-+{
-+  int i;
-+
-+  for (i = 0; i < 6; i++)
-+    {
-+      if (compare_f64 (vrnd_f64 (tests[i]), expectations[0][i]))
-+	abort ();
-+      if (compare_f64 (vrndx_f64 (tests[i]), expectations[1][i]))
-+	abort ();
-+      if (compare_f64 (vrndp_f64 (tests[i]), expectations[2][i]))
-+	abort ();
-+      if (compare_f64 (vrndn_f64 (tests[i]), expectations[3][i]))
-+	abort ();
-+      if (compare_f64 (vrndm_f64 (tests[i]), expectations[4][i]))
-+	abort ();
-+      if (compare_f64 (vrndi_f64 (tests[i]), expectations[5][i]))
-+	abort ();
-+      if (compare_f64 (vrnda_f64 (tests[i]), expectations[6][i]))
-+	abort ();
-+    }
-+}
-+
-+int
-+main (int argc, char **argv)
-+{
-+  float64x1_t tests[6] =
-+    {
-+      vcreate_f64 (0x3FE0000000000000), /* Hex for: 0.5.  */
-+      vcreate_f64 (0x3FD999999999999A), /* Hex for: 0.4.  */
-+      vcreate_f64 (0x3FE3333333333333), /* Hex for: 0.6.  */
-+      vcreate_f64 (0xBFE0000000000000), /* Hex for: -0.5.  */
-+      vcreate_f64 (0xBFD999999999999A), /* Hex for: -0.4.  */
-+      vcreate_f64 (0xBFE3333333333333), /* Hex for: -0.6.  */
-+    };
-+
-+  float64_t expectations[7][6] =
-+  {
-+    { 0.0, 0.0, 0.0, 0.0, 0.0, 0.0 },    /* vrnd - round towards zero.  */
-+    { 0.0, 0.0, 0.0, 0.0, 0.0, 0.0 },    /* vrndx - round using FPCR mode.  */
-+    { 1.0, 1.0, 1.0, 0.0, 0.0, 0.0 },    /* vrndp - round to plus infinity.  */
-+    { 0.0, 0.0, 1.0, 0.0, 0.0, -1.0 },   /* vrndn - round ties to even.  */
-+    { 0.0, 0.0, 0.0, -1.0, -1.0, -1.0 }, /* vrndm - round to minus infinity.  */
-+    { 0.0, 0.0, 0.0, 0.0, 0.0, 0.0 },    /* vrndi - round using FPCR mode.  */
-+    { 1.0, 0.0, 1.0, -1.0, 0.0, -1.0 },  /* vrnda - round ties away from 0.  */
-+  };
-+
-+  /* Set floating point control register
-+     to have predictable vrndx and vrndi behaviour.  */
-+  set_rounding_mode (FPROUNDING_ZERO);
-+
-+  run_round_tests (tests, expectations);
-+
-+  return 0;
-+}
-+
-+/* { dg-final { scan-assembler-times "frintz\\td\[0-9\]+, d\[0-9\]+" 1 } } */
-+/* { dg-final { scan-assembler-times "frintx\\td\[0-9\]+, d\[0-9\]+" 1 } } */
-+/* { dg-final { scan-assembler-times "frintp\\td\[0-9\]+, d\[0-9\]+" 1 } } */
-+/* { dg-final { scan-assembler-times "frintn\\td\[0-9\]+, d\[0-9\]+" 1 } } */
-+/* { dg-final { scan-assembler-times "frintm\\td\[0-9\]+, d\[0-9\]+" 1 } } */
-+/* { dg-final { scan-assembler-times "frinti\\td\[0-9\]+, d\[0-9\]+" 1 } } */
-+/* { dg-final { scan-assembler-times "frinta\\td\[0-9\]+, d\[0-9\]+" 1 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
-@@ -305,13 +305,28 @@
-   return res;
- }
- 
--/* { dg-final { scan-assembler-times "\\taddp\\td\[0-9\]+, v\[0-9\]+\.2d" 1 } } */
-+/* { dg-final { scan-assembler-times "\\tfaddp\\td\[0-9\]+, v\[0-9\]+\.2d" 1 } } */
- 
-+float64_t
-+test_vpaddd_f64 (float64x2_t a)
-+{
-+  return vpaddd_f64 (a);
-+}
-+
-+/* { dg-final { scan-assembler-times "\\taddp\\td\[0-9\]+, v\[0-9\]+\.2d" 2 } } */
-+
-+int64_t
- test_vpaddd_s64 (int64x2_t a)
- {
-   return vpaddd_s64 (a);
- }
- 
-+uint64_t
-+test_vpaddd_u64 (uint64x2_t a)
-+{
-+  return vpaddd_u64 (a);
-+}
-+
- /* { dg-final { scan-assembler-times "\\tuqadd\\td\[0-9\]+" 1 } } */
- 
- uint64x1_t
---- a/src/gcc/testsuite/gcc.target/aarch64/test_frame_7.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_7.c
-@@ -0,0 +1,20 @@
-+/* Verify:
-+     * -fomit-frame-pointer.
-+     * without outgoing.
-+     * total frame size > 512.
-+     * number of callee-saved reg == 2.
-+     * split stack adjustment into two subtractions.
-+       the second subtraction should use "stp !".  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-O2 -fomit-frame-pointer --save-temps" } */
-+
-+#include "test_frame_common.h"
-+
-+t_frame_pattern (test7, 700, "x19")
-+t_frame_run (test7)
-+
-+/* { dg-final { scan-assembler-times "stp\tx19, x30, \\\[sp, -\[0-9\]+\\\]!" 1 } } */
-+/* { dg-final { scan-assembler-times "ldp\tx19, x30, \\\[sp\\\], \[0-9\]+" 2 } } */
-+
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/pic-symrefplus.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/pic-symrefplus.c
-@@ -34,6 +34,9 @@
-   values [];
- };
- extern const struct locale_data _nl_C_LC_TIME __attribute__ ((visibility ("hidden")));
-+extern void *memset (void *s, int c, size_t n);
-+extern size_t strlen (const char *s);
-+extern int __strncasecmp_l (const char *s1, const char *s2, size_t n, __locale_t locale);
- char *
- __strptime_internal (rp, fmt, tmp, statep , locale)
-      const char *rp;
-@@ -40,6 +43,7 @@
-      const char *fmt;
-      __locale_t locale;
-      void *statep;
-+     int tmp;
- {
-   struct locale_data *const current = locale->__locales[__LC_TIME];
-   const char *rp_backup;
-@@ -124,5 +128,9 @@
- }
- char *
- __strptime_l (buf, format, tm , locale)
-+     int buf;
-+     int format;
-+     int tm;
-+     int locale;
- {
- }
---- a/src/gcc/testsuite/gcc.target/aarch64/vbslq_f64_2.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/vbslq_f64_2.c
-@@ -0,0 +1,24 @@
-+/* Test vbslq_f64 can be folded.  */
-+/* { dg-do assemble } */
-+/* { dg-options "--save-temps -O3" } */
-+
-+#include <arm_neon.h>
-+
-+/* Should fold out one half of the BSL, leaving just a BIC.  */
-+
-+float32x4_t
-+half_fold_me (uint32x4_t mask)
-+{
-+  float32x4_t a = {0.0, 0.0, 0.0, 0.0};
-+  float32x4_t b = {2.0, 4.0, 8.0, 16.0};
-+  return vbslq_f32 (mask, a, b);
-+
-+}
-+
-+/* { dg-final { scan-assembler-not "bsl\\tv" } } */
-+/* { dg-final { scan-assembler-not "bit\\tv" } } */
-+/* { dg-final { scan-assembler-not "bif\\tv" } } */
-+/* { dg-final { scan-assembler "bic\\tv" } } */
-+
-+/* { dg-final { cleanup-saved-temps } } */
-+
---- a/src/gcc/testsuite/gcc.target/aarch64/test_frame_11.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_11.c
-@@ -0,0 +1,16 @@
-+/* Verify:
-+     * without outgoing.
-+     * total frame size <= 512.
-+     * number of callee-save reg >= 2.
-+     * optimized code should use "stp !" for stack adjustment.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-O2 --save-temps" } */
-+
-+#include "test_frame_common.h"
-+
-+t_frame_pattern (test11, 400, )
-+t_frame_run (test11)
-+
-+/* { dg-final { scan-assembler-times "stp\tx29, x30, \\\[sp, -\[0-9\]+\\\]!" 2 } } */
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/vqneg_s64_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/vqneg_s64_1.c
-@@ -0,0 +1,47 @@
-+/* Test vqneg_s64 intrinsics work correctly.  */
-+/* { dg-do run } */
-+/* { dg-options "--save-temps" } */
-+
-+#include <arm_neon.h>
-+
-+extern void abort (void);
-+
-+int __attribute__ ((noinline))
-+test_vqneg_s64 (int64x1_t passed, int64_t expected)
-+{
-+  return vget_lane_s64 (vqneg_s64 (passed), 0) != expected;
-+}
-+
-+int __attribute__ ((noinline))
-+test_vqnegd_s64 (int64_t passed, int64_t expected)
-+{
-+  return vqnegd_s64 (passed) != expected;
-+}
-+
-+/* { dg-final { scan-assembler-times "sqneg\\td\[0-9\]+, d\[0-9\]+" 2 } } */
-+
-+int
-+main (int argc, char **argv)
-+{
-+  /* Basic test.  */
-+  if (test_vqneg_s64 (vcreate_s64 (-1), 1))
-+    abort ();
-+  if (test_vqnegd_s64 (-1, 1))
-+    abort ();
-+
-+  /* Negating max int64_t.  */
-+  if (test_vqneg_s64 (vcreate_s64 (0x7fffffffffffffff), 0x8000000000000001))
-+    abort ();
-+  if (test_vqnegd_s64 (0x7fffffffffffffff, 0x8000000000000001))
-+    abort ();
-+
-+  /* Negating min int64_t.
-+     Note, exact negation cannot be represented as int64_t.  */
-+  if (test_vqneg_s64 (vcreate_s64 (0x8000000000000000), 0x7fffffffffffffff))
-+    abort ();
-+  if (test_vqnegd_s64 (0x8000000000000000, 0x7fffffffffffffff))
-+    abort ();
-+
-+  return 0;
-+}
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/vget_low_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/vget_low_1.c
-@@ -0,0 +1,60 @@
-+/* { dg-do run } */
-+/* { dg-options "-O3 -std=c99" } */
-+
-+#include <arm_neon.h>
-+
-+extern void abort (void);
-+
-+#define VARIANTS(VARIANT)				\
-+VARIANT (uint8_t, 8, uint8x8_t, uint8x16_t, u8)		\
-+VARIANT (uint16_t, 4, uint16x4_t, uint16x8_t, u16)	\
-+VARIANT (uint32_t, 2, uint32x2_t, uint32x4_t, u32)	\
-+VARIANT (uint64_t, 1, uint64x1_t, uint64x2_t, u64)	\
-+VARIANT (int8_t, 8, int8x8_t, int8x16_t, s8)		\
-+VARIANT (int16_t, 4, int16x4_t, int16x8_t, s16)		\
-+VARIANT (int32_t, 2, int32x2_t, int32x4_t, s32)		\
-+VARIANT (int64_t, 1, int64x1_t, int64x2_t, s64)		\
-+VARIANT (float32_t, 2, float32x2_t, float32x4_t, f32)	\
-+VARIANT (float64_t, 1, float64x1_t, float64x2_t, f64)
-+
-+
-+#define TESTMETH(BASETYPE, NUM64, TYPE64, TYPE128, SUFFIX)	\
-+int								\
-+test_vget_low_ ##SUFFIX (BASETYPE *data)			\
-+{								\
-+  BASETYPE temp [NUM64];					\
-+  TYPE128 vec = vld1q_##SUFFIX (data);				\
-+  TYPE64 low = vget_low_##SUFFIX (vec);				\
-+  vst1_##SUFFIX (temp, low);					\
-+  for (int i = 0; i < NUM64; i++)				\
-+    if (temp[i] != data[i])					\
-+      return 1;							\
-+  return 0;							\
-+}
-+
-+VARIANTS (TESTMETH)
-+
-+#define CHECK(BASETYPE, NUM64, TYPE64, TYPE128, SUFFIX)		\
-+  if (test_vget_low_##SUFFIX (BASETYPE ## _ ## data) != 0)	\
-+    abort ();
-+
-+int
-+main (int argc, char **argv)
-+{
-+  uint8_t uint8_t_data[16] =
-+      { 1, 2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47 };
-+  uint16_t uint16_t_data[8] = { 1, 22, 333, 4444, 55555, 6666, 777, 88 };
-+  uint32_t uint32_t_data[4] = { 65537, 11, 70000, 23 };
-+  uint64_t uint64_t_data[2] = { 0xdeadbeefcafebabeULL, 0x0123456789abcdefULL };
-+  int8_t int8_t_data[16] =
-+      { -1, -3, -5, -7, 9, -11, -13, 15, -17, -19, 21, -23, 25, 27, -29, -31 };
-+  int16_t int16_t_data[8] = { -17, 19, 3, -999, 44048, 505, 9999, 1000};
-+  int32_t int32_t_data[4] = { 123456789, -987654321, -135792468, 975318642 };
-+  int64_t int64_t_data[2] = {0xfedcba9876543210LL, 0xdeadbabecafebeefLL };
-+  float32_t float32_t_data[4] = { 3.14159, 2.718, 1.414, 100.0 };
-+  float64_t float64_t_data[2] = { 1.01001000100001, 12345.6789 };
-+
-+  VARIANTS (CHECK);
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/test_frame_8.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_8.c
-@@ -0,0 +1,18 @@
-+/* Verify:
-+     * -fomit-frame-pointer.
-+     * with outgoing.
-+     * total frame size bigger than 512.
-+     * number of callee-saved reg == 1.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-O2 -fomit-frame-pointer --save-temps" } */
-+
-+#include "test_frame_common.h"
-+
-+t_frame_pattern_outgoing (test8, 700, , 8, a[8])
-+t_frame_run (test8)
-+
-+/* { dg-final { scan-assembler-times "str\tx30, \\\[sp, -\[0-9\]+\\\]!" 3 } } */
-+/* { dg-final { scan-assembler-times "ldr\tx30, \\\[sp\\\], \[0-9\]+" 3 } } */
-+
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/gcc.target/aarch64/vset_lane_1.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/vset_lane_1.c
-@@ -0,0 +1,85 @@
-+/* { dg-do run } */
-+/* { dg-options "-O3 -fno-inline" } */
-+
-+#include <arm_neon.h>
-+
-+extern void abort (void);
-+
-+#define VARIANTS(VARIANT)			\
-+VARIANT (uint8_t, , 8, uint8x8_t, _u8, 5)	\
-+VARIANT (uint16_t, , 4, uint16x4_t, _u16, 3)	\
-+VARIANT (uint32_t, , 2, uint32x2_t, _u32, 1)	\
-+VARIANT (uint64_t, , 1, uint64x1_t, _u64, 0)	\
-+VARIANT (int8_t, , 8, int8x8_t, _s8, 6)		\
-+VARIANT (int16_t, , 4, int16x4_t, _s16, 2)	\
-+VARIANT (int32_t, , 2, int32x2_t, _s32, 0)	\
-+VARIANT (int64_t, , 1, int64x1_t, _s64, 0)	\
-+VARIANT (poly8_t, , 8, poly8x8_t, _p8, 6)	\
-+VARIANT (poly16_t, , 4, poly16x4_t, _p16, 2)	\
-+VARIANT (float32_t, , 2, float32x2_t, _f32, 1)	\
-+VARIANT (float64_t, , 1, float64x1_t, _f64, 0)	\
-+VARIANT (uint8_t, q, 16, uint8x16_t, _u8, 11)	\
-+VARIANT (uint16_t, q, 8, uint16x8_t, _u16, 7)	\
-+VARIANT (uint32_t, q, 4, uint32x4_t, _u32, 2)	\
-+VARIANT (uint64_t, q, 2, uint64x2_t, _u64, 1)	\
-+VARIANT (int8_t, q, 16, int8x16_t, _s8, 13)	\
-+VARIANT (int16_t, q, 8, int16x8_t, _s16, 5)	\
-+VARIANT (int32_t, q, 4, int32x4_t, _s32, 3)	\
-+VARIANT (int64_t, q, 2, int64x2_t, _s64, 0)	\
-+VARIANT (poly8_t, q, 16, poly8x16_t, _p8, 14)	\
-+VARIANT (poly16_t, q, 8, poly16x8_t, _p16, 6)	\
-+VARIANT (float32_t, q, 4, float32x4_t, _f32, 2) \
-+VARIANT (float64_t, q, 2, float64x2_t, _f64, 1)
-+
-+#define TESTMETH(BASETYPE, Q, NUM, TYPE, SUFFIX, INDEX)	\
-+int							\
-+test_vset_lane ##Q##SUFFIX (BASETYPE *data)		\
-+{							\
-+  BASETYPE temp [NUM];					\
-+  TYPE vec = vld1##Q##SUFFIX (data);			\
-+  TYPE vec2;						\
-+  BASETYPE changed = data[INDEX] - INDEX;		\
-+  int check;						\
-+  vec = vset##Q##_lane##SUFFIX (changed, vec, INDEX);	\
-+  asm volatile ("orr %0.16b, %1.16b, %1.16b"		\
-+		: "=w"(vec2) : "w" (vec) : );		\
-+  vst1##Q##SUFFIX (temp, vec2);				\
-+  for (check = 0; check < NUM; check++)			\
-+    {							\
-+      BASETYPE desired = data[check];			\
-+      if (check==INDEX) desired = changed;		\
-+      if (temp[check] != desired)			\
-+        return 1;					\
-+    }							\
-+  return 0;						\
-+}
-+
-+VARIANTS (TESTMETH)
-+
-+#define CHECK(BASETYPE, Q, NUM, TYPE, SUFFIX, INDEX)		\
-+  if (test_vset_lane##Q##SUFFIX (BASETYPE ## _ ## data) != 0)	\
-+    abort ();
-+
-+int
-+main (int argc, char **argv)
-+{
-+  uint8_t uint8_t_data[16] =
-+      { 1, 2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47 };
-+  uint16_t uint16_t_data[8] = { 1, 22, 333, 4444, 55555, 6666, 777, 88 };
-+  uint32_t uint32_t_data[4] = { 65537, 11, 70000, 23 };
-+  uint64_t uint64_t_data[2] = { 0xdeadbeefcafebabeULL, 0x0123456789abcdefULL };
-+  int8_t int8_t_data[16] =
-+      { -1, -3, -5, -7, 9, -11, -13, 15, -17, -19, 21, -23, 25, 27, -29, -31 };
-+  int16_t int16_t_data[8] = { -17, 19, 3, -999, 44048, 505, 9999, 1000};
-+  int32_t int32_t_data[4] = { 123456789, -987654321, -135792468, 975318642 };
-+  int64_t int64_t_data[2] = {0xfedcba9876543210LL, 0xdeadbabecafebeefLL };
-+  poly8_t poly8_t_data[16] =
-+      { 0, 7, 13, 18, 22, 25, 27, 28, 29, 31, 34, 38, 43, 49, 56, 64 };
-+  poly16_t poly16_t_data[8] = { 11111, 2222, 333, 44, 5, 65432, 54321, 43210 };
-+  float32_t float32_t_data[4] = { 3.14159, 2.718, 1.414, 100.0 };
-+  float64_t float64_t_data[2] = { 1.01001000100001, 12345.6789 };
-+
-+  VARIANTS (CHECK);
-+
-+  return 0;
-+}
---- a/src/gcc/testsuite/gcc.target/aarch64/test_frame_12.c
-+++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_12.c
-@@ -0,0 +1,19 @@
-+/* Verify:
-+     * with outgoing.
-+     * total frame size <= 512.
-+     * number of callee-save reg >= 2.  */
-+
-+/* { dg-do run } */
-+/* { dg-options "-O2 --save-temps" } */
-+
-+#include "test_frame_common.h"
-+
-+t_frame_pattern_outgoing (test12, 400, , 8, a[8])
-+t_frame_run (test12)
-+
-+/* { dg-final { scan-assembler-times "sub\tsp, sp, #\[0-9\]+" 1 } } */
-+
-+/* Check epilogue using write-back.  */
-+/* { dg-final { scan-assembler-times "ldp\tx29, x30, \\\[sp\\\], \[0-9\]+" 3 } } */
-+
-+/* { dg-final { cleanup-saved-temps } } */
---- a/src/gcc/testsuite/lib/gcc.exp
-+++ b/src/gcc/testsuite/lib/gcc.exp
-@@ -126,7 +126,9 @@
-     global GCC_UNDER_TEST
-     global TOOL_OPTIONS
-     global TEST_ALWAYS_FLAGS
--	
-+    global flags_to_postpone
-+    global board_info
-+
-     if {[target_info needs_status_wrapper] != "" && \
- 	    [target_info needs_status_wrapper] != "0" && \
- 	    [info exists gluefile] } {
-@@ -162,8 +164,26 @@
- 	set options [concat "{additional_flags=$TOOL_OPTIONS}" $options]
-     }
- 
-+    # bind_pic_locally adds -fpie/-fPIE flags to flags_to_postpone and it is
-+    # appended here to multilib_flags as it can be overridden by the latter
-+    # if it was added earlier. After the target_compile, multilib_flags is
-+    # restored to its orignal content.
-+    set tboard [target_info name]
-+    if {[board_info $tboard exists multilib_flags]} {
-+        set orig_multilib_flags "[board_info [target_info name] multilib_flags]"
-+        append board_info($tboard,multilib_flags) " $flags_to_postpone"
-+    }
-+
-     lappend options "timeout=[timeout_value]"
-     lappend options "compiler=$GCC_UNDER_TEST"
-     set options [dg-additional-files-options $options $source]
--    return [target_compile $source $dest $type $options]
-+    set return_val [target_compile $source $dest $type $options]
-+
-+    if {[board_info $tboard exists multilib_flags]} {
-+        set board_info($tboard,multilib_flags) $orig_multilib_flags
-+        set flags_to_postpone ""
-+    }
-+
-+    return $return_val
- }
-+
---- a/src/gcc/testsuite/lib/g++.exp
-+++ b/src/gcc/testsuite/lib/g++.exp
-@@ -288,6 +288,8 @@
-     global gluefile wrap_flags
-     global ALWAYS_CXXFLAGS
-     global GXX_UNDER_TEST
-+    global flags_to_postpone
-+    global board_info
- 
-     if { [target_info needs_status_wrapper] != "" && [info exists gluefile] } {
- 	lappend options "libs=${gluefile}"
-@@ -313,10 +315,25 @@
- 	exec rm -f $rponame
-     }
- 
-+    # bind_pic_locally adds -fpie/-fPIE flags to flags_to_postpone and it is
-+    # appended here to multilib_flags as it can be overridden by the latter
-+    # if it was added earlier. After the target_compile, multilib_flags is
-+    # restored to its orignal content.
-+    set tboard [target_info name]
-+    if {[board_info $tboard exists multilib_flags]} {
-+        set orig_multilib_flags "[board_info [target_info name] multilib_flags]"
-+        append board_info($tboard,multilib_flags) " $flags_to_postpone"
-+    }
-+
-     set options [dg-additional-files-options $options $source]
- 
-     set result [target_compile $source $dest $type $options]
- 
-+    if {[board_info $tboard exists multilib_flags]} {
-+        set board_info($tboard,multilib_flags) $orig_multilib_flags
-+        set flags_to_postpone ""
-+    }
-+
-     return $result
- }
- 
---- a/src/gcc/testsuite/lib/wrapper.exp
-+++ b/src/gcc/testsuite/lib/wrapper.exp
-@@ -34,9 +34,11 @@
- 	# became true for dejagnu-1.4.4.  The set of warnings and code
- 	# that gcc objects on may change, so just make sure -w is always
- 	# passed to turn off all warnings.
-+	unset_currtarget_info wrap_compile_flags
- 	set_currtarget_info wrap_compile_flags \
- 	    "$saved_wrap_compile_flags -w $flags"
- 	set result [build_wrapper $filename]
-+	unset_currtarget_info wrap_compile_flags
- 	set_currtarget_info wrap_compile_flags "$saved_wrap_compile_flags"
- 	if { $result != "" } {
- 	    set gluefile [lindex $result 0]
---- a/src/gcc/testsuite/lib/compat.exp
-+++ b/src/gcc/testsuite/lib/compat.exp
-@@ -134,7 +134,6 @@
- 		     "$options"]
-     if ![${tool}_check_compile "$testcase $testname link" "" \
- 	 $dest $comp_output] then {
--	unresolved "$testcase $testname execute $optstr"
- 	return
-     }
- 
---- a/src/gcc/testsuite/lib/gcc-defs.exp
-+++ b/src/gcc/testsuite/lib/gcc-defs.exp
-@@ -54,14 +54,19 @@
-     if { [info proc ${tool}-dg-prune] != "" } {
- 	global target_triplet
- 	set gcc_output [${tool}-dg-prune $target_triplet $gcc_output]
-+	if [string match "*::unsupported::*" $gcc_output] then {
-+	    regsub -- "::unsupported::" $gcc_output "" gcc_output
-+	    unsupported "$testcase: $gcc_output"
-+	    return 0
-+	}
-+    } else {
-+	set unsupported_message [${tool}_check_unsupported_p $gcc_output]
-+	if { $unsupported_message != "" } {
-+	    unsupported "$testcase: $unsupported_message"
-+	    return 0
-+	}
-     }
- 
--    set unsupported_message [${tool}_check_unsupported_p $gcc_output]
--    if { $unsupported_message != "" } {
--	unsupported "$testcase: $unsupported_message"
--	return 0
--    }
--
-     # remove any leftover LF/CR to make sure any output is legit
-     regsub -all -- "\[\r\n\]*" $gcc_output "" gcc_output
- 
---- a/src/gcc/testsuite/lib/gfortran.exp
-+++ b/src/gcc/testsuite/lib/gfortran.exp
-@@ -234,6 +234,8 @@
-     global gluefile wrap_flags
-     global ALWAYS_GFORTRANFLAGS
-     global GFORTRAN_UNDER_TEST
-+    global flags_to_postpone
-+    global board_info
- 
-     if { [target_info needs_status_wrapper] != "" && [info exists gluefile] } {
- 	lappend options "libs=${gluefile}"
-@@ -240,10 +242,27 @@
- 	lappend options "ldflags=${wrap_flags}"
-     }
- 
-+    # bind_pic_locally adds -fpie/-fPIE flags to flags_to_postpone and it is
-+    # appended here to multilib_flags as it can be overridden by the latter
-+    # if it was added earlier. After the target_compile, multilib_flags is
-+    # restored to its orignal content.
-+    set tboard [target_info name]
-+    if {[board_info $tboard exists multilib_flags]} {
-+        set orig_multilib_flags "[board_info [target_info name] multilib_flags]"
-+        append board_info($tboard,multilib_flags) " $flags_to_postpone"
-+    }
-+
-     lappend options "compiler=$GFORTRAN_UNDER_TEST"
-     lappend options "timeout=[timeout_value]"
- 
-     set options [concat "$ALWAYS_GFORTRANFLAGS" $options]
-     set options [dg-additional-files-options $options $source]
--    return [target_compile $source $dest $type $options]
-+    set return_val [target_compile $source $dest $type $options]
-+
-+    if {[board_info $tboard exists multilib_flags]} {
-+        set board_info($tboard,multilib_flags) $orig_multilib_flags
-+        set flags_to_postpone ""
-+    }
-+
-+    return $return_val
- }
---- a/src/gcc/testsuite/lib/target-supports.exp
-+++ b/src/gcc/testsuite/lib/target-supports.exp
-@@ -2261,7 +2261,7 @@
-     }]
- }
- 
--# Return 1 is this is an arm target using 32-bit instructions
-+# Return 1 if this is an arm target using 32-bit instructions
- proc check_effective_target_arm32 { } {
-     return [check_no_compiler_messages arm32 assembly {
- 	#if !defined(__arm__) || (defined(__thumb__) && !defined(__thumb2__))
-@@ -2270,10 +2270,10 @@
-     }]
- }
- 
--# Return 1 is this is an arm target not using Thumb
-+# Return 1 if this is an arm target not using Thumb
- proc check_effective_target_arm_nothumb { } {
-     return [check_no_compiler_messages arm_nothumb assembly {
--	#if (defined(__thumb__) || defined(__thumb2__))
-+	#if !defined(__arm__) || (defined(__thumb__) || defined(__thumb2__))
- 	#error FOO
- 	#endif
-     }]
-@@ -2394,6 +2394,7 @@
- 	foreach flags {"" "-mfloat-abi=softfp" "-mfpu=crypto-neon-fp-armv8" "-mfpu=crypto-neon-fp-armv8 -mfloat-abi=softfp"} {
- 	    if { [check_no_compiler_messages_nocache arm_crypto_ok object {
- 		#include "arm_neon.h"
-+		extern uint8x16_t vaeseq_u8 (uint8x16_t, uint8x16_t);
- 		uint8x16_t
- 		foo (uint8x16_t a, uint8x16_t b)
- 		{
-@@ -2538,6 +2539,7 @@
- 	               "-mfpu=neon-fp16 -mfloat-abi=softfp"} {
- 	    if { [check_no_compiler_messages_nocache arm_neon_fp_16_ok object {
- 		#include "arm_neon.h"
-+		extern float16x4_t vcvt_f16_f32 (float32x4_t);
- 		float16x4_t
- 		foo (float32x4_t arg)
- 		{
-@@ -2613,6 +2615,7 @@
- 	foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-vfpv4" "-mfpu=neon-vfpv4 -mfloat-abi=softfp"} {
- 	    if { [check_no_compiler_messages_nocache arm_neonv2_ok object {
- 		#include "arm_neon.h"
-+		extern float32x2_t vfma_f32 (float32x2_t, float32x2_t, float32x2_t);
- 		float32x2_t 
- 		foo (float32x2_t a, float32x2_t b, float32x2_t c)
-                 {
-@@ -3324,6 +3327,43 @@
-     return $et_vect_shift_saved
- }
- 
-+proc check_effective_target_whole_vector_shift { } {
-+    if { [istarget x86_64-*-*]
-+	 || [istarget ia64-*-*]
-+	 || ([check_effective_target_arm32]
-+	     && [check_effective_target_arm_little_endian])
-+	 || ([istarget mips*-*-*]
-+	     && [check_effective_target_mips_loongson]) } {
-+	set answer 1
-+    } else {
-+	set answer 0
-+    }
-+
-+    verbose "check_effective_target_vect_long: returning $answer" 2
-+    return $answer
-+}
-+
-+# Return 1 if the target supports vector bswap operations.
-+
-+proc check_effective_target_vect_bswap { } {
-+    global et_vect_bswap_saved
-+
-+    if [info exists et_vect_bswap_saved] {
-+	verbose "check_effective_target_vect_bswap: using cached result" 2
-+    } else {
-+	set et_vect_bswap_saved 0
-+	if { [istarget aarch64*-*-*]
-+             || ([istarget arm*-*-*]
-+                && [check_effective_target_arm_neon])
-+	   } {
-+	   set et_vect_bswap_saved 1
-+	}
-+    }
-+
-+    verbose "check_effective_target_vect_bswap: returning $et_vect_bswap_saved" 2
-+    return $et_vect_bswap_saved
-+}
-+
- # Return 1 if the target supports hardware vector shift operation for char.
- 
- proc check_effective_target_vect_shift_char { } {
-@@ -3522,8 +3562,7 @@
-     } else {
-         set et_vect_perm_saved 0
-         if { [is-effective-target arm_neon_ok]
--	     || ([istarget aarch64*-*-*]
--		 && [is-effective-target aarch64_little_endian])
-+	     || [istarget aarch64*-*-*]
- 	     || [istarget powerpc*-*-*]
-              || [istarget spu-*-*]
- 	     || [istarget i?86-*-*]
-@@ -5206,16 +5245,26 @@
-     return $flags
- }
- 
-+if {![info exists flags_to_postpone]} {
-+    set flags_to_postpone ""
-+}
-+
- # Add to FLAGS the flags needed to enable functions to bind locally
- # when using pic/PIC passes in the testsuite.
-+proc add_options_for_bind_pic_locally { flags } {
-+    global flags_to_postpone
- 
--proc add_options_for_bind_pic_locally { flags } {
-+    # Instead of returning 'flags' with the -fPIE or -fpie appended, we save it
-+    # in 'flags_to_postpone' and append it later in gcc_target_compile procedure in
-+    # order to make sure that the multilib_flags doesn't override this.
-+
-     if {[check_no_compiler_messages using_pic2 assembly {
-         #if __PIC__ != 2
-         #error FOO
-         #endif
-     }]} {
--	return "$flags -fPIE"
-+        set flags_to_postpone "-fPIE"
-+        return $flags
-     }
-     if {[check_no_compiler_messages using_pic1 assembly {
-         #if __PIC__ != 1
-@@ -5222,9 +5271,9 @@
-         #error FOO
-         #endif
-     }]} {
--	return "$flags -fpie"
-+        set flags_to_postpone "-fpie"
-+        return $flags
-     }
--
-     return $flags
- }
- 
---- a/src/gcc/testsuite/ChangeLog.linaro
-+++ b/src/gcc/testsuite/ChangeLog.linaro
-@@ -0,0 +1,1031 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2015-01-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r218451.
-+	2014-12-06  James Greenhalgh  <james.greenhalgh@arm.com>
-+		    Sebastian Pop  <s.pop@samsung.com>
-+		    Brian Rzycki  <b.rzycki@samsung.com>
-+
-+	PR tree-optimization/54742
-+	* gcc.dg/tree-ssa/ssa-dom-thread-6.c: New test.
-+	* gcc.dg/tree-ssa/ssa-dom-thread-7.c: New test.
-+
-+2015-01-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r211075.
-+	2014-04-30  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	gcc.target/arm/simd/vrev16p8_1.c: New file.
-+	gcc.target/arm/simd/vrev16qp8_1.c: New file.
-+	gcc.target/arm/simd/vrev16qs8_1.c: New file.
-+	gcc.target/arm/simd/vrev16qu8_1.c: New file.
-+	gcc.target/arm/simd/vrev16s8_1.c: New file.
-+	gcc.target/arm/simd/vrev16u8_1.c: New file.
-+	gcc.target/arm/simd/vrev32p16_1.c: New file.
-+	gcc.target/arm/simd/vrev32p8_1.c: New file.
-+	gcc.target/arm/simd/vrev32qp16_1.c: New file.
-+	gcc.target/arm/simd/vrev32qp8_1.c: New file.
-+	gcc.target/arm/simd/vrev32qs16_1.c: New file.
-+	gcc.target/arm/simd/vrev32qs8_1.c: New file.
-+	gcc.target/arm/simd/vrev32qu16_1.c: New file.
-+	gcc.target/arm/simd/vrev32qu8_1.c: New file.
-+	gcc.target/arm/simd/vrev32s16_1.c: New file.
-+	gcc.target/arm/simd/vrev32s8_1.c: New file.
-+	gcc.target/arm/simd/vrev32u16_1.c: New file.
-+	gcc.target/arm/simd/vrev32u8_1.c: New file.
-+	gcc.target/arm/simd/vrev64f32_1.c: New file.
-+	gcc.target/arm/simd/vrev64p16_1.c: New file.
-+	gcc.target/arm/simd/vrev64p8_1.c: New file.
-+	gcc.target/arm/simd/vrev64qf32_1.c: New file.
-+	gcc.target/arm/simd/vrev64qp16_1.c: New file.
-+	gcc.target/arm/simd/vrev64qp8_1.c: New file.
-+	gcc.target/arm/simd/vrev64qs16_1.c: New file.
-+	gcc.target/arm/simd/vrev64qs32_1.c: New file.
-+	gcc.target/arm/simd/vrev64qs8_1.c: New file.
-+	gcc.target/arm/simd/vrev64qu16_1.c: New file.
-+	gcc.target/arm/simd/vrev64qu32_1.c: New file.
-+	gcc.target/arm/simd/vrev64qu8_1.c: New file.
-+	gcc.target/arm/simd/vrev64s16_1.c: New file.
-+	gcc.target/arm/simd/vrev64s32_1.c: New file.
-+	gcc.target/arm/simd/vrev64s8_1.c: New file.
-+	gcc.target/arm/simd/vrev64u16_1.c: New file.
-+	gcc.target/arm/simd/vrev64u32_1.c: New file.
-+	gcc.target/arm/simd/vrev64u8_1.c: New file.
-+
-+2015-01-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209620.
-+	2014-04-22  Vidya Praveen  <vidyapraveen@arm.com>
-+
-+	* gcc.target/aarch64/cvtf_1.c: New.
-+
-+2015-01-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r217362.
-+	2014-11-11  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* gcc.target/aarch64/vbslq_f64_1.c: New.
-+	* gcc.target/aarch64/vbslq_f64_2.c: Likewise.
-+	* gcc.target/aarch64/vbslq_u64_1.c: Likewise.
-+	* gcc.target/aarch64/vbslq_u64_2.c: Likewise.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r217742.
-+	2014-11-18  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	PR target/63937
-+	* gcc.dg/memset-2.c: New.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r216638.
-+	2014-10-24  Christophe Lyon  <christophe.lyon@linaro.org>
-+
-+	* lib/wrapper.exp ({tool}_maybe_build_wrapper): Clear
-+	wrap_compile_flags before setting it.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r216544.
-+	2014-10-22  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* gcc.target/aarch64/pic-constantpool1.c: Add explicit declaration.
-+	* gcc.target/aarch64/pic-symrefplus.c: Likewise.
-+	* gcc.target/aarch64/reload-valid-spoff.c: Likewise.
-+	* gcc.target/aarch64/vect.x: Likewise.
-+	* gcc.target/aarch64/vect-ld1r.x: Add return type.
-+	* gcc.target/aarch64/vect-fmax-fmin.c: Likewise.
-+	* gcc.target/aarch64/vect-fp.c: Likewise.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r216543.
-+	2014-10-22  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* lib/compat.exp (compat-run): Remove "unresolved".
-+	* lib/gcc-defs.exp (${tools}_check_compile): Update code logic for
-+	unsupported testcase.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r216517.
-+	2014-10-21  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* gcc.target/arm/20031108-1.c (Proc_7): Add explicit declaration.
-+	(Proc_1): Add return type.
-+	* gcc.target/arm/cold-lc.c (show_stack): Add explict declaration.
-+	* gcc.target/arm/neon-modes-2.c (foo): Likewise.
-+	* gcc.target/arm/pr43920-2.c (lseek): Likewise.
-+	* gcc.target/arm/pr44788.c (foo): Likewise.
-+	* gcc.target/arm/pr55642.c (abs): Likewise.
-+	* gcc.target/arm/pr58784.c (f): Likewise.
-+	* gcc.target/arm/pr60650.c (foo1, foo2): Likewise.
-+	* gcc.target/arm/vfp-ldmdbs.c (bar): Likewise.
-+	* gcc.target/arm/vfp-ldmias.c (bar): Likewise.
-+	* gcc.target/arm/pr60650-2.c (fn1, fn2): Add return type and add type
-+	for local variables.
-+	* lib/target-supports.exp
-+	(check_effective_target_arm_crypto_ok_nocache): Add declaration for
-+	vaeseq_u8.
-+	(check_effective_target_arm_neon_fp16_ok_nocache): Add declaration for
-+	vcvt_f16_f32.
-+	(check_effective_target_arm_neonv2_ok_nocache): Add declaration for
-+	vfma_f32.
-+	* gcc.target/arm/pr51968.c: Add -Wno-implicit-function-declaration.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+ 
-+	Backport from trunk r215071.
-+	2014-09-09  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* gcc.target/aarch64/simd/int_comparisons_1.c: Tighten regexp.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215540.
-+	2014-09-24  Zhenqiang Chen  <zhenqiang.chen@arm.com>
-+
-+	* gcc.target/arm/pr63210.c: New test.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215475.
-+	2014-09-22  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* gcc.dg/vect/vect-reduc-or_1.c: New test.
-+	* gcc.dg/vect/vect-reduc-or_2.c: Likewise.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215473.
-+	2014-09-22  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* lib/target-supports.exp (check_effective_target_whole_vector_shift):
-+	New.
-+
-+	* gcc.dg/vect/vect-reduc-mul_1.c: New test.
-+	* gcc.dg/vect/vect-reduc-mul_2.c: New test.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215177.
-+	2014-09-11  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* gcc.target/aarch64/vset_lane_1.c: New test.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215129.
-+	2014-09-10  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* gcc.target/aarch64/vstN_1.c: New test.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215126.
-+	2014-09-10  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* gcc.target/aarch64/vldN_lane_1.c: New test.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215078.
-+	2014-09-09  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* gcc.target/aarch64/vldN_dup_1.c: New test.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215077.
-+	2014-09-09  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* gcc.target/aarch64/vld1-vst1_1.c: Rewrite to test all variants.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215072.
-+	2014-09-09  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* gcc.target/aarch64/vldN_1.c: New test.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215047.
-+	2014-09-09  Tony Wang  <tony.wang@arm.com>
-+
-+	* gcc.target/arm/xordi3-opt.c: Disable this
-+	test case for thumb1 target.
-+	* gcc.target/arm/iordi3-opt.c: Ditto.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215046.
-+	2014-09-09  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	PR target/61749
-+	* gcc.target/aarch64/vqdml_lane_intrinsics-bad_1.c: New test.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r214950.
-+	2014-09-05  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* gcc.target/aarch64/vget_high_1.c: New test.
-+	* gcc.target/aarch64/vget_low_1.c: Likewise.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r214948.
-+	2014-09-05  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* gcc.target/aarch64/simd/int_comparisons.x: New file.
-+	* gcc.target/aarch64/simd/int_comparisons_1.c: New test.
-+	* gcc.target/aarch64/simd/int_comparisons_2.c: Ditto.
-+
-+2014-12-04  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r213382.
-+	2014-07-31  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* gcc.target/aarch64/scalar_intrinsics.c (test_vpaddd_f64): New.
-+	(test_vpaddd_s64): Likewise.
-+	(test_vpaddd_s64): Likewise.
-+	* gcc.target/aarch64/simd/vpaddd_f64: New.
-+	* gcc.target/aarch64/simd/vpaddd_s64: New.
-+	* gcc.target/aarch64/simd/vpaddd_u64: New.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-10-08  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r214825, r214826, r215085.
-+	2014-09-09  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* gcc.target/arm/vect-lceilf_1.c: Make input and output arrays global
-+	and 16-byte aligned.
-+	* gcc.target/arm/vect-lfloorf_1.c: Likewise.
-+	* gcc.target/arm/vect-lroundf_1.c: Likewise.
-+	* gcc.target/arm/vect-rounding-btruncf.c: Likewise.
-+	* gcc.target/arm/vect-rounding-ceilf.c: Likewise.
-+	* gcc.target/arm/vect-rounding-floorf.c: Likewise.
-+	* gcc.target/arm/vect-rounding-roundf.c: Likewise.
-+
-+	2014-09-02  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	PR target/62275
-+	* gcc.target/arm/vect-lceilf_1.c: New test.
-+	* gcc.target/arm/vect-lfloorf_1.c: Likewise.
-+	* gcc.target/arm/vect-lroundf_1.c: Likewise.
-+
-+	2014-09-02  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	PR target/62275
-+	* gcc.target/arm/lceil-vcvt_1.c: New test.
-+	* gcc.target/arm/lfloor-vcvt_1.c: Likewise.
-+	* gcc.target/arm/lround-vcvt_1.c: Likewise.
-+
-+2014-10-06  Venkataramanan Kumar  <venkataramanan.kumar@linaro.org>
-+
-+	Backport from trunk r214943.
-+	2014-09-05  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* gcc.target/aarch64/simd/vrbit_1.c: New test.
-+
-+2014-10-06  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215385.
-+	2014-09-19  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* gcc.dg/ssp-3.c: New.
-+	* gcc.dg/ssp-4.c: Likewise.
-+
-+2014-10-06  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215136.
-+	2014-09-10  Xinliang David Li  <davidxl@google.com>
-+
-+	PR target/63209
-+	* gcc.c-torture/execute/pr63209.c: New test.
-+
-+2014-10-06  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215067.
-+	2014-09-09  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* gcc.target/arm/vect-copysignf.c: New testcase.
-+
-+2014-10-03  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r215050, r215051, r215052, r215053, r215054.
-+	2014-09-09  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* gcc.target/arm/vfp-1.c: Updated expected assembly.
-+
-+	2014-09-09  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* gcc.target/arm/vfp-1.c: Updated expected assembly.
-+
-+	2014-09-09  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* gcc.target/arm/vfp-1.c: Updated expected assembly.
-+
-+	2014-09-09  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* gcc.target/arm/vfp-1.c: Updated expected assembly.
-+
-+	2014-09-09  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* gcc.target/arm/pr51835.c: Update expected assembly.
-+	* gcc.target/arm/vfp-1.c: Likewise.
-+	* gcc.target/arm/vfp-ldmdbd.c: Likewise.
-+	* gcc.target/arm/vfp-ldmdbs.c: Likewise.
-+	* gcc.target/arm/vfp-ldmiad.c: Likewise.
-+	* gcc.target/arm/vfp-ldmias.c: Likewise.
-+	* gcc.target/arm/vfp-stmdbd.c: Likewise.
-+	* gcc.target/arm/vfp-stmdbs.c: Likewise.
-+	* gcc.target/arm/vfp-stmiad.c: Likewise.
-+	* gcc.target/arm/vfp-stmias.c: Likewise.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-09-03  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r214526.
-+	2014-08-26  Joseph Myers  <joseph@codesourcery.com>
-+
-+	PR target/60606
-+	PR target/61330
-+	* gcc.dg/torture/pr60606-1.c, gcc.target/arm/pr60606-2.c,
-+	gcc.target/arm/pr60606-3.c, gcc.target/arm/pr60606-4.c: New tests.
-+
-+2014-09-03  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r213659.
-+	2014-08-06  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* gcc.target/aarch64/vdup_n_2.c: New test.
-+
-+2014-08-26  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r213701.
-+	2014-08-07  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* gcc.dg/pr61756.c: Remove arm-specific dg-options.
-+
-+2014-08-26  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r213488, r213489.
-+	2014-08-01  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* gcc.target/aarch64/legitimize_stack_var_before_reload_1.c: New
-+	testcase.
-+
-+2014-08-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r212927.
-+	2014-07-23  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* gcc.dg/ira-shrinkwrap-prep-1.c (target): Add arm_nothumb.
-+	* gcc.dg/ira-shrinkwrap-prep-2.c (target): Likewise.
-+	* gcc.dg/pr10474.c (target): Likewise.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-08-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r213555.
-+	2014-08-04  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	PR target/61713
-+	* gcc.dg/pr61756.c: New test.
-+
-+2014-08-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r213376.
-+	2014-07-31  Charles Baylis  <charles.baylis@linaro.org>
-+
-+	PR target/61948
-+	* gcc.target/arm/pr61948.c: New test case.
-+
-+2014-08-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r212959, r212976, r212999, r213000.
-+	2014-07-24  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* gcc.target/aarch64/test_frame_1.c: Match optimized instruction
-+	sequences.
-+	* gcc.target/aarch64/test_frame_2.c: Likewise.
-+	* gcc.target/aarch64/test_frame_4.c: Likewise.
-+	* gcc.target/aarch64/test_frame_6.c: Likewise.
-+	* gcc.target/aarch64/test_frame_7.c: Likewise.
-+	* gcc.target/aarch64/test_frame_8.c: Likewise.
-+	* gcc.target/aarch64/test_frame_10.c: Likewise.
-+
-+	2014-07-24  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* gcc.target/aarch64/test_frame_1.c: Match optimized instruction
-+	sequences.
-+	* gcc.target/aarch64/test_frame_10.c: Likewise.
-+	* gcc.target/aarch64/test_frame_2.c: Likewise.
-+	* gcc.target/aarch64/test_frame_4.c: Likewise.
-+	* gcc.target/aarch64/test_frame_6.c: Likewise.
-+	* gcc.target/aarch64/test_frame_7.c: Likewise.
-+	* gcc.target/aarch64/test_frame_8.c: Likewise.
-+	* gcc.target/aarch64/test_fp_attribute_1.c: Likewise.
-+
-+	2014-07-24  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* gcc.target/aarch64/test_frame_12.c: Match optimized instruction
-+	sequences.
-+
-+	2014-07-23  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* gcc.target/aarch64/test_frame_common.h: New file.
-+	* gcc.target/aarch64/test_frame_1.c: Likewise.
-+	* gcc.target/aarch64/test_frame_2.c: Likewise.
-+	* gcc.target/aarch64/test_frame_3.c: Likewise.
-+	* gcc.target/aarch64/test_frame_4.c: Likewise.
-+	* gcc.target/aarch64/test_frame_5.c: Likewise.
-+	* gcc.target/aarch64/test_frame_6.c: Likewise.
-+	* gcc.target/aarch64/test_frame_7.c: Likewise.
-+	* gcc.target/aarch64/test_frame_8.c: Likewise.
-+	* gcc.target/aarch64/test_frame_9.c: Likewise.
-+	* gcc.target/aarch64/test_frame_10.c: Likewise.
-+	* gcc.target/aarch64/test_frame_11.c: Likewise.
-+	* gcc.target/aarch64/test_frame_12.c: Likewise.
-+	* gcc.target/aarch64/test_frame_13.c: Likewise.
-+	* gcc.target/aarch64/test_frame_14.c: Likewise.
-+	* gcc.target/aarch64/test_frame_15.c: Likewise.
-+
-+2014-08-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r212023, r212024.
-+	2014-06-26  Vidya Praveen  <vidyapraveen@arm.com>
-+
-+	* gcc.dg/inline-22.c: Add bind_pic_locally.
-+	* gcc.dg/inline_4.c: Ditto.
-+	* gcc.dg/fail_always_inline.c: Ditto.
-+	* g++.dg/ipa/devirt-25.C: Ditto.
-+
-+	2014-06-26  Vidya Praveen  <vidyapraveen@arm.com>
-+
-+	* lib/target-support.exp (bind_pic_locally): Save the flags to
-+	'flags_to_postpone' instead of appending to 'flags'.
-+	* lib/gcc.exp (gcc_target_compile): Append board_info's multilib_flags
-+	with flags_to_postpone and revert after target_compile.
-+	* lib/g++.exp (g++_target_compile): Ditto.
-+	* lib/gfortran.exp (gfortran_target_compile): Ditto.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r211887.
-+	2014-06-23  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* gcc.target/aarch64/scalar_shift_1.c: Fix expected assembler.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r211441.
-+	2014-06-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* gcc.target/aarch64/acle/acle.exp: New.
-+	* gcc.target/aarch64/acle/crc32b.c: New test.
-+	* gcc.target/aarch64/acle/crc32cb.c: Likewise.
-+	* gcc.target/aarch64/acle/crc32cd.c: Likewise.
-+	* gcc.target/aarch64/acle/crc32ch.c: Likewise.
-+	* gcc.target/aarch64/acle/crc32cw.c: Likewise.
-+	* gcc.target/aarch64/acle/crc32d.c: Likewise.
-+	* gcc.target/aarch64/acle/crc32h.c: Likewise.
-+	* gcc.target/aarch64/acle/crc32w.c: Likewise.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r210153.
-+	2014-05-07  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* gcc.target/aarch64/simd/vrev16p8_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev16p8.x: New file.
-+	* gcc.target/aarch64/simd/vrev16qp8_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev16qp8.x: New file.
-+	* gcc.target/aarch64/simd/vrev16qs8_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev16qs8.x: New file.
-+	* gcc.target/aarch64/simd/vrev16qu8_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev16qu8.x: New file.
-+	* gcc.target/aarch64/simd/vrev16s8_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev16s8.x: New file.
-+	* gcc.target/aarch64/simd/vrev16u8_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev16u8.x: New file.
-+	* gcc.target/aarch64/simd/vrev32p16_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev32p16.x: New file.
-+	* gcc.target/aarch64/simd/vrev32p8_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev32p8.x: New file.
-+	* gcc.target/aarch64/simd/vrev32qp16_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev32qp16.x: New file.
-+	* gcc.target/aarch64/simd/vrev32qp8_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev32qp8.x: New file.
-+	* gcc.target/aarch64/simd/vrev32qs16_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev32qs16.x: New file.
-+	* gcc.target/aarch64/simd/vrev32qs8_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev32qs8.x: New file.
-+	* gcc.target/aarch64/simd/vrev32qu16_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev32qu16.x: New file.
-+	* gcc.target/aarch64/simd/vrev32qu8_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev32qu8.x: New file.
-+	* gcc.target/aarch64/simd/vrev32s16_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev32s16.x: New file.
-+	* gcc.target/aarch64/simd/vrev32s8_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev32s8.x: New file.
-+	* gcc.target/aarch64/simd/vrev32u16_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev32u16.x: New file.
-+	* gcc.target/aarch64/simd/vrev32u8_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev32u8.x: New file.
-+	* gcc.target/aarch64/simd/vrev64f32_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev64f32.x: New file.
-+	* gcc.target/aarch64/simd/vrev64p16_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev64p16.x: New file.
-+	* gcc.target/aarch64/simd/vrev64p8_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev64p8.x: New file.
-+	* gcc.target/aarch64/simd/vrev64qf32_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev64qf32.x: New file.
-+	* gcc.target/aarch64/simd/vrev64qp16_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev64qp16.x: New file.
-+	* gcc.target/aarch64/simd/vrev64qp8_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev64qp8.x: New file.
-+	* gcc.target/aarch64/simd/vrev64qs16_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev64qs16.x: New file.
-+	* gcc.target/aarch64/simd/vrev64qs32_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev64qs32.x: New file.
-+	* gcc.target/aarch64/simd/vrev64qs8_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev64qs8.x: New file.
-+	* gcc.target/aarch64/simd/vrev64qu16_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev64qu16.x: New file.
-+	* gcc.target/aarch64/simd/vrev64qu32_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev64qu32.x: New file.
-+	* gcc.target/aarch64/simd/vrev64qu8_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev64qu8.x: New file.
-+	* gcc.target/aarch64/simd/vrev64s16_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev64s16.x: New file.
-+	* gcc.target/aarch64/simd/vrev64s32_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev64s32.x: New file.
-+	* gcc.target/aarch64/simd/vrev64s8_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev64s8.x: New file.
-+	* gcc.target/aarch64/simd/vrev64u16_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev64u16.x: New file.
-+	* gcc.target/aarch64/simd/vrev64u32_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev64u32.x: New file.
-+	* gcc.target/aarch64/simd/vrev64u8_1.c: New file.
-+	* gcc.target/aarch64/simd/vrev64u8.x: New file.
-+
-+2014-07-16  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r210148, r210151, r210422.
-+	2014-05-14  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* gcc.target/arm/simd/vtrnqf32_1.c: New file.
-+	* gcc.target/arm/simd/vtrnqp16_1.c: New file.
-+	* gcc.target/arm/simd/vtrnqp8_1.c: New file.
-+	* gcc.target/arm/simd/vtrnqs16_1.c: New file.
-+	* gcc.target/arm/simd/vtrnqs32_1.c: New file.
-+	* gcc.target/arm/simd/vtrnqs8_1.c: New file.
-+	* gcc.target/arm/simd/vtrnqu16_1.c: New file.
-+	* gcc.target/arm/simd/vtrnqu32_1.c: New file.
-+	* gcc.target/arm/simd/vtrnqu8_1.c: New file.
-+	* gcc.target/arm/simd/vtrnf32_1.c: New file.
-+	* gcc.target/arm/simd/vtrnp16_1.c: New file.
-+	* gcc.target/arm/simd/vtrnp8_1.c: New file.
-+	* gcc.target/arm/simd/vtrns16_1.c: New file.
-+	* gcc.target/arm/simd/vtrns32_1.c: New file.
-+	* gcc.target/arm/simd/vtrns8_1.c: New file.
-+	* gcc.target/arm/simd/vtrnu16_1.c: New file.
-+	* gcc.target/arm/simd/vtrnu32_1.c: New file.
-+	* gcc.target/arm/simd/vtrnu8_1.c: New file.
-+
-+	2014-05-07  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* gcc.target/aarch64/vtrns32.c: Expect zip[12] insn rather than trn[12].
-+	* gcc.target/aarch64/vtrnu32.c: Likewise.
-+	* gcc.target/aarch64/vtrnf32.c: Likewise.
-+
-+	2014-05-07  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* gcc.target/aarch64/simd/vtrnf32_1.c: New file.
-+	* gcc.target/aarch64/simd/vtrnf32.x: New file.
-+	* gcc.target/aarch64/simd/vtrnp16_1.c: New file.
-+	* gcc.target/aarch64/simd/vtrnp16.x: New file.
-+	* gcc.target/aarch64/simd/vtrnp8_1.c: New file.
-+	* gcc.target/aarch64/simd/vtrnp8.x: New file.
-+	* gcc.target/aarch64/simd/vtrnqf32_1.c: New file.
-+	* gcc.target/aarch64/simd/vtrnqf32.x: New file.
-+	* gcc.target/aarch64/simd/vtrnqp16_1.c: New file.
-+	* gcc.target/aarch64/simd/vtrnqp16.x: New file.
-+	* gcc.target/aarch64/simd/vtrnqp8_1.c: New file.
-+	* gcc.target/aarch64/simd/vtrnqp8.x: New file.
-+	* gcc.target/aarch64/simd/vtrnqs16_1.c: New file.
-+	* gcc.target/aarch64/simd/vtrnqs16.x: New file.
-+	* gcc.target/aarch64/simd/vtrnqs32_1.c: New file.
-+	* gcc.target/aarch64/simd/vtrnqs32.x: New file.
-+	* gcc.target/aarch64/simd/vtrnqs8_1.c: New file.
-+	* gcc.target/aarch64/simd/vtrnqs8.x: New file.
-+	* gcc.target/aarch64/simd/vtrnqu16_1.c: New file.
-+	* gcc.target/aarch64/simd/vtrnqu16.x: New file.
-+	* gcc.target/aarch64/simd/vtrnqu32_1.c: New file.
-+	* gcc.target/aarch64/simd/vtrnqu32.x: New file.
-+	* gcc.target/aarch64/simd/vtrnqu8_1.c: New file.
-+	* gcc.target/aarch64/simd/vtrnqu8.x: New file.
-+	* gcc.target/aarch64/simd/vtrns16_1.c: New file.
-+	* gcc.target/aarch64/simd/vtrns16.x: New file.
-+	* gcc.target/aarch64/simd/vtrns32_1.c: New file.
-+	* gcc.target/aarch64/simd/vtrns32.x: New file.
-+	* gcc.target/aarch64/simd/vtrns8_1.c: New file.
-+	* gcc.target/aarch64/simd/vtrns8.x: New file.
-+	* gcc.target/aarch64/simd/vtrnu16_1.c: New file.
-+	* gcc.target/aarch64/simd/vtrnu16.x: New file.
-+	* gcc.target/aarch64/simd/vtrnu32_1.c: New file.
-+	* gcc.target/aarch64/simd/vtrnu32.x: New file.
-+	* gcc.target/aarch64/simd/vtrnu8_1.c: New file.
-+	* gcc.target/aarch64/simd/vtrnu8.x: New file.
-+
-+2014-07-16  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209794, 209858.
-+	2014-04-25  Marek Polacek  <polacek@redhat.com>
-+
-+	PR c/60114
-+	* gcc.dg/pr60114.c: New test.
-+
-+	2014-04-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	PR c/60983
-+	* gcc.dg/pr60114.c: Use signed chars.
-+
-+2014-07-16  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r210861.
-+	2014-05-23  Jiong Wang   <jiong.wang@arm.com>
-+
-+	* gcc.target/aarch64/tail_indirect_call_1.c: New.
-+
-+2014-07-16  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r211314.
-+	2014-06-06  James Greenhalgh  <james.greenhalgh@arm.com>
-+
-+	* gcc.dg/tree-ssa/pr42585.c: Skip for AArch64.
-+	* gcc.dg/tree-ssa/sra-12.c: Likewise.
-+
-+2014-07-16  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r210967.
-+	2014-05-27  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* lib/target-supports.exp (check_effective_target_vect_bswap):
-+	Specify arm*-*-* support.
-+
-+2014-07-16  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r210152, 211059.
-+	2014-05-29  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* gcc.target/arm/simd/vextQf32_1.c: New file.
-+	* gcc.target/arm/simd/vextQp16_1.c: New file.
-+	* gcc.target/arm/simd/vextQp8_1.c: New file.
-+	* gcc.target/arm/simd/vextQs16_1.c: New file.
-+	* gcc.target/arm/simd/vextQs32_1.c: New file.
-+	* gcc.target/arm/simd/vextQs64_1.c: New file.
-+	* gcc.target/arm/simd/vextQs8_1.c: New file.
-+	* gcc.target/arm/simd/vextQu16_1.c: New file.
-+	* gcc.target/arm/simd/vextQu32_1.c: New file.
-+	* gcc.target/arm/simd/vextQu64_1.c: New file.
-+	* gcc.target/arm/simd/vextQu8_1.c: New file.
-+	* gcc.target/arm/simd/vextQp64_1.c: New file.
-+	* gcc.target/arm/simd/vextf32_1.c: New file.
-+	* gcc.target/arm/simd/vextp16_1.c: New file.
-+	* gcc.target/arm/simd/vextp8_1.c: New file.
-+	* gcc.target/arm/simd/vexts16_1.c: New file.
-+	* gcc.target/arm/simd/vexts32_1.c: New file.
-+	* gcc.target/arm/simd/vexts64_1.c: New file.
-+	* gcc.target/arm/simd/vexts8_1.c: New file.
-+	* gcc.target/arm/simd/vextu16_1.c: New file.
-+	* gcc.target/arm/simd/vextu32_1.c: New file.
-+	* gcc.target/arm/simd/vextu64_1.c: New file.
-+	* gcc.target/arm/simd/vextu8_1.c: New file.
-+	* gcc.target/arm/simd/vextp64_1.c: New file.
-+
-+	2014-05-07  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* gcc.target/aarch64/simd/ext_f32.x: New file.
-+	* gcc.target/aarch64/simd/ext_f32_1.c: New file.
-+	* gcc.target/aarch64/simd/ext_p16.x: New file.
-+	* gcc.target/aarch64/simd/ext_p16_1.c: New file.
-+	* gcc.target/aarch64/simd/ext_p8.x: New file.
-+	* gcc.target/aarch64/simd/ext_p8_1.c: New file.
-+	* gcc.target/aarch64/simd/ext_s16.x: New file.
-+	* gcc.target/aarch64/simd/ext_s16_1.c: New file.
-+	* gcc.target/aarch64/simd/ext_s32.x: New file.
-+	* gcc.target/aarch64/simd/ext_s32_1.c: New file.
-+	* gcc.target/aarch64/simd/ext_s64.x: New file.
-+	* gcc.target/aarch64/simd/ext_s64_1.c: New file.
-+	* gcc.target/aarch64/simd/ext_s8.x: New file.
-+	* gcc.target/aarch64/simd/ext_s8_1.c: New file.
-+	* gcc.target/aarch64/simd/ext_u16.x: New file.
-+	* gcc.target/aarch64/simd/ext_u16_1.c: New file.
-+	* gcc.target/aarch64/simd/ext_u32.x: New file.
-+	* gcc.target/aarch64/simd/ext_u32_1.c: New file.
-+	* gcc.target/aarch64/simd/ext_u64.x: New file.
-+	* gcc.target/aarch64/simd/ext_u64_1.c: New file.
-+	* gcc.target/aarch64/simd/ext_u8.x: New file.
-+	* gcc.target/aarch64/simd/ext_u8_1.c: New file.
-+	* gcc.target/aarch64/simd/ext_f64.c: New file.
-+	* gcc.target/aarch64/simd/extq_f32.x: New file.
-+	* gcc.target/aarch64/simd/extq_f32_1.c: New file.
-+	* gcc.target/aarch64/simd/extq_p16.x: New file.
-+	* gcc.target/aarch64/simd/extq_p16_1.c: New file.
-+	* gcc.target/aarch64/simd/extq_p8.x: New file.
-+	* gcc.target/aarch64/simd/extq_p8_1.c: New file.
-+	* gcc.target/aarch64/simd/extq_s16.x: New file.
-+	* gcc.target/aarch64/simd/extq_s16_1.c: New file.
-+	* gcc.target/aarch64/simd/extq_s32.x: New file.
-+	* gcc.target/aarch64/simd/extq_s32_1.c: New file.
-+	* gcc.target/aarch64/simd/extq_s64.x: New file.
-+	* gcc.target/aarch64/simd/extq_s64_1.c: New file.
-+	* gcc.target/aarch64/simd/extq_s8.x: New file.
-+	* gcc.target/aarch64/simd/extq_s8_1.c: New file.
-+	* gcc.target/aarch64/simd/extq_u16.x: New file.
-+	* gcc.target/aarch64/simd/extq_u16_1.c: New file.
-+	* gcc.target/aarch64/simd/extq_u32.x: New file.
-+
-+2014-07-16  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209940, r209943, r209947.
-+	2014-04-30  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* gcc.target/arm/simd/vuzpqf32_1.c: New file.
-+	* gcc.target/arm/simd/vuzpqp16_1.c: New file.
-+	* gcc.target/arm/simd/vuzpqp8_1.c: New file.
-+	* gcc.target/arm/simd/vuzpqs16_1.c: New file.
-+	* gcc.target/arm/simd/vuzpqs32_1.c: New file.
-+	* gcc.target/arm/simd/vuzpqs8_1.c: New file.
-+	* gcc.target/arm/simd/vuzpqu16_1.c: New file.
-+	* gcc.target/arm/simd/vuzpqu32_1.c: New file.
-+	* gcc.target/arm/simd/vuzpqu8_1.c: New file.
-+	* gcc.target/arm/simd/vuzpf32_1.c: New file.
-+	* gcc.target/arm/simd/vuzpp16_1.c: New file.
-+	* gcc.target/arm/simd/vuzpp8_1.c: New file.
-+	* gcc.target/arm/simd/vuzps16_1.c: New file.
-+	* gcc.target/arm/simd/vuzps32_1.c: New file.
-+	* gcc.target/arm/simd/vuzps8_1.c: New file.
-+	* gcc.target/arm/simd/vuzpu16_1.c: New file.
-+	* gcc.target/arm/simd/vuzpu32_1.c: New file.
-+	* gcc.target/arm/simd/vuzpu8_1.c: New file.
-+
-+	2014-04-30  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* gcc.target/aarch64/vuzps32_1.c: Expect zip1/2 insn rather than uzp1/2.
-+	* gcc.target/aarch64/vuzpu32_1.c: Likewise.
-+	* gcc.target/aarch64/vuzpf32_1.c: Likewise.
-+
-+	2014-04-30  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* gcc.target/aarch64/simd/vuzpf32_1.c: New file.
-+	* gcc.target/aarch64/simd/vuzpf32.x: New file.
-+	* gcc.target/aarch64/simd/vuzpp16_1.c: New file.
-+	* gcc.target/aarch64/simd/vuzpp16.x: New file.
-+	* gcc.target/aarch64/simd/vuzpp8_1.c: New file.
-+	* gcc.target/aarch64/simd/vuzpp8.x: New file.
-+	* gcc.target/aarch64/simd/vuzpqf32_1.c: New file.
-+	* gcc.target/aarch64/simd/vuzpqf32.x: New file.
-+	* gcc.target/aarch64/simd/vuzpqp16_1.c: New file.
-+	* gcc.target/aarch64/simd/vuzpqp16.x: New file.
-+	* gcc.target/aarch64/simd/vuzpqp8_1.c: New file.
-+	* gcc.target/aarch64/simd/vuzpqp8.x: New file.
-+	* gcc.target/aarch64/simd/vuzpqs16_1.c: New file.
-+	* gcc.target/aarch64/simd/vuzpqs16.x: New file.
-+	* gcc.target/aarch64/simd/vuzpqs32_1.c: New file.
-+	* gcc.target/aarch64/simd/vuzpqs32.x: New file.
-+	* gcc.target/aarch64/simd/vuzpqs8_1.c: New file.
-+	* gcc.target/aarch64/simd/vuzpqs8.x: New file.
-+	* gcc.target/aarch64/simd/vuzpqu16_1.c: New file.
-+	* gcc.target/aarch64/simd/vuzpqu16.x: New file.
-+	* gcc.target/aarch64/simd/vuzpqu32_1.c: New file.
-+	* gcc.target/aarch64/simd/vuzpqu32.x: New file.
-+	* gcc.target/aarch64/simd/vuzpqu8_1.c: New file.
-+	* gcc.target/aarch64/simd/vuzpqu8.x: New file.
-+	* gcc.target/aarch64/simd/vuzps16_1.c: New file.
-+	* gcc.target/aarch64/simd/vuzps16.x: New file.
-+	* gcc.target/aarch64/simd/vuzps32_1.c: New file.
-+	* gcc.target/aarch64/simd/vuzps32.x: New file.
-+	* gcc.target/aarch64/simd/vuzps8_1.c: New file.
-+	* gcc.target/aarch64/simd/vuzps8.x: New file.
-+	* gcc.target/aarch64/simd/vuzpu16_1.c: New file.
-+	* gcc.target/aarch64/simd/vuzpu16.x: New file.
-+	* gcc.target/aarch64/simd/vuzpu32_1.c: New file.
-+	* gcc.target/aarch64/simd/vuzpu32.x: New file.
-+	* gcc.target/aarch64/simd/vuzpu8_1.c: New file.
-+	* gcc.target/aarch64/simd/vuzpu8.x: New file.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-13  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r211206.
-+	2014-06-03  Andrew Pinski  <apinski@cavium.com>
-+
-+	* gcc.c-torture/compile/20140528-1.c: New testcase.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209908.
-+	2013-04-29  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* gcc.target/arm/simd/simd.exp: New file.
-+	* gcc.target/arm/simd/vzipqf32_1.c: New file.
-+	* gcc.target/arm/simd/vzipqp16_1.c: New file.
-+	* gcc.target/arm/simd/vzipqp8_1.c: New file.
-+	* gcc.target/arm/simd/vzipqs16_1.c: New file.
-+	* gcc.target/arm/simd/vzipqs32_1.c: New file.
-+	* gcc.target/arm/simd/vzipqs8_1.c: New file.
-+	* gcc.target/arm/simd/vzipqu16_1.c: New file.
-+	* gcc.target/arm/simd/vzipqu32_1.c: New file.
-+	* gcc.target/arm/simd/vzipqu8_1.c: New file.
-+	* gcc.target/arm/simd/vzipf32_1.c: New file.
-+	* gcc.target/arm/simd/vzipp16_1.c: New file.
-+	* gcc.target/arm/simd/vzipp8_1.c: New file.
-+	* gcc.target/arm/simd/vzips16_1.c: New file.
-+	* gcc.target/arm/simd/vzips32_1.c: New file.
-+	* gcc.target/arm/simd/vzips8_1.c: New file.
-+	* gcc.target/arm/simd/vzipu16_1.c: New file.
-+	* gcc.target/arm/simd/vzipu32_1.c: New file.
-+	* gcc.target/arm/simd/vzipu8_1.c: New file.
-+
-+2014-05-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209893.
-+	2014-04-29  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* gcc.target/aarch64/simd/simd.exp: New file.
-+	* gcc.target/aarch64/simd/vzipf32_1.c: New file.
-+	* gcc.target/aarch64/simd/vzipf32.x: New file.
-+	* gcc.target/aarch64/simd/vzipp16_1.c: New file.
-+	* gcc.target/aarch64/simd/vzipp16.x: New file.
-+	* gcc.target/aarch64/simd/vzipp8_1.c: New file.
-+	* gcc.target/aarch64/simd/vzipp8.x: New file.
-+	* gcc.target/aarch64/simd/vzipqf32_1.c: New file.
-+	* gcc.target/aarch64/simd/vzipqf32.x: New file.
-+	* gcc.target/aarch64/simd/vzipqp16_1.c: New file.
-+	* gcc.target/aarch64/simd/vzipqp16.x: New file.
-+	* gcc.target/aarch64/simd/vzipqp8_1.c: New file.
-+	* gcc.target/aarch64/simd/vzipqp8.x: New file.
-+	* gcc.target/aarch64/simd/vzipqs16_1.c: New file.
-+	* gcc.target/aarch64/simd/vzipqs16.x: New file.
-+	* gcc.target/aarch64/simd/vzipqs32_1.c: New file.
-+	* gcc.target/aarch64/simd/vzipqs32.x: New file.
-+	* gcc.target/aarch64/simd/vzipqs8_1.c: New file.
-+	* gcc.target/aarch64/simd/vzipqs8.x: New file.
-+	* gcc.target/aarch64/simd/vzipqu16_1.c: New file.
-+	* gcc.target/aarch64/simd/vzipqu16.x: New file.
-+	* gcc.target/aarch64/simd/vzipqu32_1.c: New file.
-+	* gcc.target/aarch64/simd/vzipqu32.x: New file.
-+	* gcc.target/aarch64/simd/vzipqu8_1.c: New file.
-+	* gcc.target/aarch64/simd/vzipqu8.x: New file.
-+	* gcc.target/aarch64/simd/vzips16_1.c: New file.
-+	* gcc.target/aarch64/simd/vzips16.x: New file.
-+	* gcc.target/aarch64/simd/vzips32_1.c: New file.
-+	* gcc.target/aarch64/simd/vzips32.x: New file.
-+	* gcc.target/aarch64/simd/vzips8_1.c: New file.
-+	* gcc.target/aarch64/simd/vzips8.x: New file.
-+	* gcc.target/aarch64/simd/vzipu16_1.c: New file.
-+	* gcc.target/aarch64/simd/vzipu16.x: New file.
-+	* gcc.target/aarch64/simd/vzipu32_1.c: New file.
-+	* gcc.target/aarch64/simd/vzipu32.x: New file.
-+	* gcc.target/aarch64/simd/vzipu8_1.c: New file.
-+	* gcc.target/aarch64/simd/vzipu8.x: New file.
-+
-+2014-05-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209808.
-+	2014-04-25  Jiong Wang  <jiong.wang@arm.com>
-+
-+	* gcc.target/arm/tail-long-call.c: New test.
-+
-+2014-05-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209749.
-+	2014-04-24  Alan Lawrence  <alan.lawrence@arm.com>
-+
-+	* lib/target-supports.exp (check_effective_target_vect_perm): Return
-+	true for aarch64_be.
-+
-+2014-05-23  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209736.
-+	2014-04-24  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* lib/target-supports.exp (check_effective_target_vect_bswap): New.
-+	* gcc.dg/vect/vect-bswap16: New test.
-+	* gcc.dg/vect/vect-bswap32: Likewise.
-+	* gcc.dg/vect/vect-bswap64: Likewise.
-+
-+2014-05-23  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209713.
-+	2014-04-23  Alex Velenko  <Alex.Velenko@arm.com>
-+
-+	* gcc.target/aarch64/vdup_lane_1.c: New testcase.
-+	* gcc.target/aarch64/vdup_lane_2.c: New testcase.
-+	* gcc.target/aarch64/vdup_n_1.c: New testcase.
-+
-+2014-05-23  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209704, 209705.
-+	2014-04-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* gcc.target/arm/rev16.c: New test.
-+
-+	2014-04-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* gcc.target/aarch64/rev16_1.c: New test.
-+
-+2014-05-23  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209642.
-+	2014-04-22  Alex Velenko  <Alex.Velenko@arm.com>
-+
-+	* gcc.target/aarch64/vreinterpret_f64_1.c: New.
-+
-+2014-05-23  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209640.
-+	2014-04-22  Alex Velenko  <Alex.Velenko@arm.com>
-+
-+	* gcc.target/aarch64/vqneg_s64_1.c: New testcase.
-+	* gcc.target/aarch64/vqabs_s64_1.c: New testcase.
-+
-+2014-05-23  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209613, 209614.
-+	2014-04-22  Ian Bolton  <ian.bolton@arm.com>
-+
-+	* gcc.target/arm/anddi_notdi-1.c: New test.
-+	* gcc.target/arm/iordi_notdi-1.c: New test case.
-+
-+	2014-04-22  Ian Bolton  <ian.bolton@arm.com>
-+
-+	* gcc.target/arm/iordi_notdi-1.c: New test.
-+
-+2014-05-23  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209559.
-+	2014-04-22  Alex Velenko  <Alex.Velenko@arm.com>
-+
-+	* gcc.target/aarch64/vrnd_f64_1.c : New file.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-05-13  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209889.
-+	2014-04-29  Zhenqiang Chen  <zhenqiang.chen@linaro.org>
-+
-+	* gcc.target/aarch64/fcsel_1.c: New test case.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/gcc/testsuite/gcc.c-torture/compile/20140528-1.c
-+++ b/src/gcc/testsuite/gcc.c-torture/compile/20140528-1.c
-@@ -0,0 +1,9 @@
-+unsigned f(unsigned flags, unsigned capabilities)
-+{
-+  unsigned gfp_mask;
-+  unsigned gfp_notmask = 0;
-+  gfp_mask = flags & ((1 << 25) - 1);
-+  if (!(capabilities & 0x00000001))
-+    gfp_mask |= 0x1000000u;
-+  return (gfp_mask & ~gfp_notmask);
-+}
---- a/src/gcc/testsuite/gcc.dg/fail_always_inline.c
-+++ b/src/gcc/testsuite/gcc.dg/fail_always_inline.c
-@@ -1,4 +1,5 @@
- /* { dg-do compile } */
-+/* { dg-add-options bind_pic_locally } */
- 
- extern __attribute__ ((always_inline)) void
-  bar() { } /* { dg-warning "function might not be inlinable" } */
---- a/src/gcc/testsuite/gcc.dg/ira-shrinkwrap-prep-1.c
-+++ b/src/gcc/testsuite/gcc.dg/ira-shrinkwrap-prep-1.c
-@@ -1,4 +1,4 @@
--/* { dg-do compile { target { { x86_64-*-* && lp64 } || { powerpc*-*-* && lp64 } } } } */
-+/* { dg-do compile { target { { x86_64-*-* && lp64 } || { { powerpc*-*-* && lp64 } || arm_nothumb } } } } */
- /* { dg-options "-O3 -fdump-rtl-ira -fdump-rtl-pro_and_epilogue"  } */
- 
- long __attribute__((noinline, noclone))
---- a/src/gcc/testsuite/gcc.dg/pr10474.c
-+++ b/src/gcc/testsuite/gcc.dg/pr10474.c
-@@ -1,4 +1,4 @@
--/* { dg-do compile { target { { x86_64-*-* && lp64 } || { powerpc*-*-* && lp64 } } } } */
-+/* { dg-do compile { target { { x86_64-*-* && lp64 } || { { powerpc*-*-* && lp64 } || arm_nothumb } } } } */
- /* { dg-options "-O3 -fdump-rtl-pro_and_epilogue"  } */
- 
- void f(int *i)
---- a/src/gcc/testsuite/gcc.dg/ssp-4.c
-+++ b/src/gcc/testsuite/gcc.dg/ssp-4.c
-@@ -0,0 +1,18 @@
-+/* { dg-do assemble } */
-+/* { dg-options "-fstack-protector-strong -O1 -frename-registers" } */
-+/* { dg-require-effective-target fstack_protector } */
-+
-+typedef unsigned int uint32_t;
-+struct ctx
-+{
-+  uint32_t A;
-+};
-+
-+void *
-+buffer_copy (const struct ctx *ctx, void *resbuf)
-+{
-+  uint32_t buffer[4];
-+  buffer[0] = (ctx->A);
-+  __builtin_memcpy (resbuf, buffer, sizeof (buffer));
-+  return resbuf;
-+}
---- a/src/gcc/testsuite/gcc.dg/ira-shrinkwrap-prep-2.c
-+++ b/src/gcc/testsuite/gcc.dg/ira-shrinkwrap-prep-2.c
-@@ -1,4 +1,4 @@
--/* { dg-do compile { target { { x86_64-*-* && lp64 } || { powerpc*-*-* && lp64 } } } } */
-+/* { dg-do compile { target { { x86_64-*-* && lp64 } || { { powerpc*-*-* && lp64 } || arm_nothumb } } } } */
- /* { dg-options "-O3 -fdump-rtl-ira -fdump-rtl-pro_and_epilogue"  } */
- 
- long __attribute__((noinline, noclone))
---- a/src/gcc/testsuite/gcc.dg/inline-22.c
-+++ b/src/gcc/testsuite/gcc.dg/inline-22.c
-@@ -1,5 +1,6 @@
- /* { dg-do compile } */
- /* { dg-options "-funit-at-a-time -Wno-attributes" } */
-+/* { dg-add-options bind_pic_locally } */
- /* Verify we can inline without a complete prototype and with promoted
-    arguments.  See also PR32492.  */
- __attribute__((always_inline)) void f1() {}
---- a/src/gcc/testsuite/gcc.dg/memset-2.c
-+++ b/src/gcc/testsuite/gcc.dg/memset-2.c
-@@ -0,0 +1,11 @@
-+/* PR target/63937 */
-+/* { dg-do compile { target lp64 } } */
-+/* { dg-options "-O2" } */
-+
-+void
-+foo (char *p)
-+{
-+  p = __builtin_assume_aligned (p, 64);
-+  __builtin_memset (p, 0, 0x100000001ULL);
-+}
-+
---- a/src/gcc/testsuite/gcc.dg/inline_4.c
-+++ b/src/gcc/testsuite/gcc.dg/inline_4.c
-@@ -1,5 +1,6 @@
- /* { dg-do compile } */
- /* { dg-options "-O2 -fdump-tree-optimized -fdisable-tree-einline=foo2 -fdisable-ipa-inline -Wno-attributes" } */
-+/* { dg-add-options bind_pic_locally } */
- int g;
- __attribute__((always_inline)) void bar (void)
- {
---- a/src/gcc/testsuite/gcc.dg/torture/pr60606-1.c
-+++ b/src/gcc/testsuite/gcc.dg/torture/pr60606-1.c
-@@ -0,0 +1,9 @@
-+/* { dg-do compile } */
-+/* { dg-options "-ffat-lto-objects" } */
-+
-+int
-+f (void)
-+{
-+  register unsigned int r asm ("no-such-register"); /* { dg-error "invalid register name" } */
-+  return r;
-+}
---- a/src/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-6.c
-+++ b/src/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-6.c
-@@ -0,0 +1,43 @@
-+/* { dg-do compile } */
-+/* { dg-options "-O2 -fdump-tree-dom1-details" } */
-+/* { dg-final { scan-tree-dump-times "FSM" 6 "dom1" } } */
-+/* { dg-final { cleanup-tree-dump "dom1" } } */
-+
-+int sum0, sum1, sum2, sum3;
-+int foo (char *s, char **ret)
-+{
-+  int state=0;
-+  char c;
-+
-+  for (; *s && state != 4; s++)
-+    {
-+      c = *s;
-+      if (c == '*')
-+	{
-+	  s++;
-+	  break;
-+	}
-+      switch (state)
-+	{
-+	case 0:
-+	  if (c == '+')
-+	    state = 1;
-+	  else if (c != '-')
-+	    sum0+=c;
-+	  break;
-+	case 1:
-+	  if (c == '+')
-+	    state = 2;
-+	  else if (c == '-')
-+	    state = 0;
-+	  else
-+	    sum1+=c;
-+	  break;
-+	default:
-+	  break;
-+	}
-+
-+    }
-+  *ret = s;
-+  return state;
-+}
---- a/src/gcc/testsuite/gcc.dg/tree-ssa/pr42585.c
-+++ b/src/gcc/testsuite/gcc.dg/tree-ssa/pr42585.c
-@@ -35,6 +35,6 @@
- /* Whether the structs are totally scalarized or not depends on the
-    MOVE_RATIO macro definition in the back end.  The scalarization will
-    not take place when using small values for MOVE_RATIO.  */
--/* { dg-final { scan-tree-dump-times "struct _fat_ptr _ans" 0 "optimized" { target { ! "arm*-*-* avr-*-* nds32*-*-* powerpc*-*-* s390*-*-* sh*-*-*" } } } } */
--/* { dg-final { scan-tree-dump-times "struct _fat_ptr _T2" 0 "optimized" { target { ! "arm*-*-* avr-*-* nds32*-*-* powerpc*-*-* s390*-*-* sh*-*-*" } } } } */
-+/* { dg-final { scan-tree-dump-times "struct _fat_ptr _ans" 0 "optimized" { target { ! "aarch64*-*-* arm*-*-* avr-*-* nds32*-*-* powerpc*-*-* s390*-*-* sh*-*-*" } } } } */
-+/* { dg-final { scan-tree-dump-times "struct _fat_ptr _T2" 0 "optimized" { target { ! "aarch64*-*-* arm*-*-* avr-*-* nds32*-*-* powerpc*-*-* s390*-*-* sh*-*-*" } } } } */
- /* { dg-final { cleanup-tree-dump "optimized" } } */
---- a/src/gcc/testsuite/gcc.dg/tree-ssa/sra-12.c
-+++ b/src/gcc/testsuite/gcc.dg/tree-ssa/sra-12.c
-@@ -21,5 +21,5 @@
-   *p = l;
- }
- 
--/* { dg-final { scan-tree-dump-times "l;" 0 "release_ssa" { target { ! "avr*-*-* nds32*-*-*" } } } } */
-+/* { dg-final { scan-tree-dump-times "l;" 0 "release_ssa" { target { ! "aarch64*-*-* avr*-*-* nds32*-*-*" } } } } */
- /* { dg-final { cleanup-tree-dump "release_ssa" } } */
---- a/src/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-7.c
-+++ b/src/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-7.c
-@@ -0,0 +1,127 @@
-+/* { dg-do compile } */
-+/* { dg-options "-O2 -fdump-tree-dom1-details" } */
-+/* { dg-final { scan-tree-dump-times "FSM" 19 "dom1" } } */
-+/* { dg-final { cleanup-tree-dump "dom1" } } */
-+
-+enum STATE {
-+  S0=0,
-+  SI,
-+  S1,
-+  S2,
-+  S3,
-+  S4,
-+  S5,
-+  S6
-+};
-+
-+int bar (enum STATE s);
-+
-+enum STATE foo (unsigned char **y, unsigned *c)
-+{
-+  unsigned char *x = *y;
-+  unsigned char n;
-+  enum STATE s = S0;
-+
-+  for( ; *x && s != SI; x++ )
-+    {
-+      n = *x;
-+      if (n == 'x')
-+	{
-+	  x++;
-+	  break;
-+	}
-+      switch(s)
-+	{
-+	case S0:
-+	  if(bar(n))
-+	    s = S3;
-+	  else if( n == 'a' || n == 'b' )
-+	    s = S1;
-+	  else if( n == 'c' )
-+	    s = S4;
-+	  else
-+	    {
-+	      s = SI;
-+	      c[SI]++;
-+	    }
-+	  c[S0]++;
-+	  break;
-+	case S1:
-+	  if(bar(n))
-+	    {
-+	      s = S3;
-+	      c[S1]++;
-+	    }
-+	  else if( n == 'c' )
-+	    {
-+	      s = S4;
-+	      c[S1]++;
-+	    }
-+	  else
-+	    {
-+	      s = SI;
-+	      c[S1]++;
-+	    }
-+	  break;
-+	case S3:
-+	  if( n == 'c' )
-+	    {
-+	      s = S4;
-+	      c[S3]++;
-+	    }
-+	  else if(!bar(n))
-+	    {
-+	      s = SI;
-+	      c[S3]++;
-+	    }
-+	  break;
-+	case S4:
-+	  if( n == 'E' || n == 'e' )
-+	    {
-+	      s = S2;
-+	      c[S4]++;
-+	    }
-+	  else if(!bar(n))
-+	    {
-+	      s = SI;
-+	      c[S4]++;
-+	    }
-+	  break;
-+	case S2:
-+	  if( n == 'a' || n == 'b' )
-+	    {
-+	      s = S5;
-+	      c[S2]++;
-+	    }
-+	  else
-+	    {
-+	      s = SI;
-+	      c[S2]++;
-+	    }
-+	  break;
-+	case S5:
-+	  if(bar(n))
-+	    {
-+	      s = S6;
-+	      c[S5]++;
-+	    }
-+	  else
-+	    {
-+	      s = SI;
-+	      c[S5]++;
-+	    }
-+	  break;
-+	case S6:
-+	  if(!bar(n))
-+	    {
-+	      s = SI;
-+	      c[SI]++;
-+	    }
-+	  break;
-+	default:
-+	  break;
-+	}
-+    }
-+  *y=x;
-+  return s;
-+}
---- a/src/gcc/testsuite/gcc.dg/pr60114.c
-+++ b/src/gcc/testsuite/gcc.dg/pr60114.c
-@@ -0,0 +1,31 @@
-+/* PR c/60114 */
-+/* { dg-do compile } */
-+/* { dg-options "-Wconversion" } */
-+
-+struct S { int n, u[2]; };
-+const signed char z[] = {
-+  [0] = 0x100, /* { dg-warning "9:overflow in implicit constant conversion" } */
-+  [2] = 0x101, /* { dg-warning "9:overflow in implicit constant conversion" } */
-+};
-+int A[] = {
-+            0, 0x80000000, /* { dg-warning "16:conversion of unsigned constant value to negative integer" } */
-+            0xA, 0x80000000, /* { dg-warning "18:conversion of unsigned constant value to negative integer" } */
-+            0xA, 0xA, 0x80000000 /* { dg-warning "23:conversion of unsigned constant value to negative integer" } */
-+          };
-+int *p = (int []) { 0x80000000 }; /* { dg-warning "21:conversion of unsigned constant value to negative integer" } */
-+union { int k; } u = { .k = 0x80000000 }; /* { dg-warning "29:conversion of unsigned constant value to negative integer" } */
-+typedef int H[];
-+void
-+foo (void)
-+{
-+  signed char a[][3] = { { 0x100, /* { dg-warning "28:overflow in implicit constant conversion" } */
-+                    1, 0x100 }, /* { dg-warning "24:overflow in implicit constant conversion" } */
-+                  { '\0', 0x100, '\0' } /* { dg-warning "27:overflow in implicit constant conversion" } */
-+                };
-+  (const signed char []) { 0x100 }; /* { dg-warning "28:overflow in implicit constant conversion" } */
-+  (const float []) { 1e0, 1e1, 1e100 }; /* { dg-warning "32:conversion" } */
-+  struct S s1 = { 0x80000000 }; /* { dg-warning "19:conversion of unsigned constant value to negative integer" } */
-+  struct S s2 = { .n = 0x80000000 }; /* { dg-warning "24:conversion of unsigned constant value to negative integer" } */
-+  struct S s3 = { .u[1] = 0x80000000 }; /* { dg-warning "27:conversion of unsigned constant value to negative integer" } */
-+  H h = { 1, 2, 0x80000000 }; /* { dg-warning "17:conversion of unsigned constant value to negative integer" } */
-+}
---- a/src/gcc/testsuite/gcc.dg/vect/vect-reduc-mul_1.c
-+++ b/src/gcc/testsuite/gcc.dg/vect/vect-reduc-mul_1.c
-@@ -0,0 +1,36 @@
-+/* { dg-require-effective-target vect_int_mult } */
-+/* { dg-require-effective-target whole_vector_shift } */
-+
-+/* Write a reduction loop to be reduced using vector shifts.  */
-+
-+extern void abort(void);
-+
-+unsigned char in[16];
-+
-+int
-+main (unsigned char argc, char **argv)
-+{
-+  unsigned char i = 0;
-+  unsigned char sum = 1;
-+
-+  for (i = 0; i < 16; i++)
-+    in[i] = i + i + 1;
-+
-+  /* Prevent constant propagation of the entire loop below.  */
-+  asm volatile ("" : : : "memory");
-+
-+  for (i = 0; i < 16; i++)
-+    sum *= in[i];
-+
-+  if (sum != 33)
-+    {
-+      __builtin_printf("Failed %d\n", sum);
-+      abort();
-+    }
-+
-+  return 0;
-+}
-+
-+/* { dg-final { scan-tree-dump "Reduce using vector shifts" "vect" } } */
-+/* { dg-final { cleanup-tree-dump "vect" } } */
-+
---- a/src/gcc/testsuite/gcc.dg/vect/vect-reduc-mul_2.c
-+++ b/src/gcc/testsuite/gcc.dg/vect/vect-reduc-mul_2.c
-@@ -0,0 +1,32 @@
-+/* { dg-require-effective-target vect_int_mult } */
-+/* { dg-require-effective-target whole_vector_shift } */
-+
-+/* Write a reduction loop to be reduced using vector shifts and folded.  */
-+
-+extern void abort(void);
-+
-+int
-+main (unsigned char argc, char **argv)
-+{
-+  unsigned char in[16];
-+  unsigned char i = 0;
-+  unsigned char sum = 1;
-+
-+  for (i = 0; i < 16; i++)
-+    in[i] = i + i + 1;
-+
-+  for (i = 0; i < 16; i++)
-+    sum *= in[i];
-+
-+  if (sum != 33)
-+    {
-+      __builtin_printf("Failed %d\n", sum);
-+      abort();
-+    }
-+
-+  return 0;
-+}
-+
-+/* { dg-final { scan-tree-dump "Reduce using vector shifts" "vect" } } */
-+/* { dg-final { cleanup-tree-dump "vect" } } */
-+
---- a/src/gcc/testsuite/gcc.dg/vect/vect-reduc-or_1.c
-+++ b/src/gcc/testsuite/gcc.dg/vect/vect-reduc-or_1.c
-@@ -0,0 +1,35 @@
-+/* { dg-require-effective-target whole_vector_shift } */
-+
-+/* Write a reduction loop to be reduced using vector shifts.  */
-+
-+extern void abort(void);
-+
-+unsigned char in[16] __attribute__((__aligned__(16)));
-+
-+int
-+main (unsigned char argc, char **argv)
-+{
-+  unsigned char i = 0;
-+  unsigned char sum = 1;
-+
-+  for (i = 0; i < 16; i++)
-+    in[i] = (i + i + 1) & 0xfd;
-+
-+  /* Prevent constant propagation of the entire loop below.  */
-+  asm volatile ("" : : : "memory");
-+
-+  for (i = 0; i < 16; i++)
-+    sum |= in[i];
-+
-+  if (sum != 29)
-+    {
-+      __builtin_printf("Failed %d\n", sum);
-+      abort();
-+    }
-+
-+  return 0;
-+}
-+
-+/* { dg-final { scan-tree-dump "Reduce using vector shifts" "vect" } } */
-+/* { dg-final { cleanup-tree-dump "vect" } } */
-+
---- a/src/gcc/testsuite/gcc.dg/vect/vect-bswap32.c
-+++ b/src/gcc/testsuite/gcc.dg/vect/vect-bswap32.c
-@@ -0,0 +1,44 @@
-+/* { dg-require-effective-target vect_bswap } */
-+
-+#include "tree-vect.h"
-+
-+#define N 128
-+
-+volatile int y = 0;
-+
-+static inline void
-+vfoo32 (unsigned int* a)
-+{
-+  int i = 0;
-+  for (i = 0; i < N; ++i)
-+    a[i] = __builtin_bswap32 (a[i]);
-+}
-+
-+int
-+main (void)
-+{
-+  unsigned int arr[N];
-+  unsigned int expect[N];
-+  int i;
-+
-+  for (i = 0; i < N; ++i)
-+    {
-+      arr[i] = i;
-+      expect[i] = __builtin_bswap32 (i);
-+      if (y) /* Avoid vectorisation.  */
-+        abort ();
-+    }
-+
-+  vfoo32 (arr);
-+
-+  for (i = 0; i < N; ++i)
-+    {
-+      if (arr[i] != expect[i])
-+        abort ();
-+    }
-+
-+  return 0;
-+}
-+
-+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
-+/* { dg-final { cleanup-tree-dump "vect" } } */
---- a/src/gcc/testsuite/gcc.dg/vect/vect-reduc-or_2.c
-+++ b/src/gcc/testsuite/gcc.dg/vect/vect-reduc-or_2.c
-@@ -0,0 +1,31 @@
-+/* { dg-require-effective-target whole_vector_shift } */
-+
-+/* Write a reduction loop to be reduced using vector shifts and folded.  */
-+
-+extern void abort(void);
-+
-+int
-+main (unsigned char argc, char **argv)
-+{
-+  unsigned char in[16] __attribute__((aligned(16)));
-+  unsigned char i = 0;
-+  unsigned char sum = 1;
-+
-+  for (i = 0; i < 16; i++)
-+    in[i] = (i + i + 1) & 0xfd;
-+
-+  for (i = 0; i < 16; i++)
-+    sum |= in[i];
-+
-+  if (sum != 29)
-+    {
-+      __builtin_printf("Failed %d\n", sum);
-+      abort();
-+    }
-+
-+  return 0;
-+}
-+
-+/* { dg-final { scan-tree-dump "Reduce using vector shifts" "vect" } } */
-+/* { dg-final { cleanup-tree-dump "vect" } } */
-+
---- a/src/gcc/testsuite/gcc.dg/vect/vect-bswap16.c
-+++ b/src/gcc/testsuite/gcc.dg/vect/vect-bswap16.c
-@@ -0,0 +1,44 @@
-+/* { dg-require-effective-target vect_bswap } */
-+
-+#include "tree-vect.h"
-+
-+#define N 128
-+
-+volatile int y = 0;
-+
-+static inline void
-+vfoo16 (unsigned short int* a)
-+{
-+  int i = 0;
-+  for (i = 0; i < N; ++i)
-+    a[i] = __builtin_bswap16 (a[i]);
-+}
-+
-+int
-+main (void)
-+{
-+  unsigned short arr[N];
-+  unsigned short expect[N];
-+  int i;
-+
-+  for (i = 0; i < N; ++i)
-+    {
-+      arr[i] = i;
-+      expect[i] = __builtin_bswap16 (i);
-+      if (y) /* Avoid vectorisation.  */
-+        abort ();
-+    }
-+
-+  vfoo16 (arr);
-+
-+  for (i = 0; i < N; ++i)
-+    {
-+      if (arr[i] != expect[i])
-+        abort ();
-+    }
-+
-+  return 0;
-+}
-+
-+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
-+/* { dg-final { cleanup-tree-dump "vect" } } */
---- a/src/gcc/testsuite/gcc.dg/vect/vect-bswap64.c
-+++ b/src/gcc/testsuite/gcc.dg/vect/vect-bswap64.c
-@@ -0,0 +1,44 @@
-+/* { dg-require-effective-target vect_bswap } */
-+
-+#include "tree-vect.h"
-+
-+#define N 128
-+
-+volatile int y = 0;
-+
-+static inline void
-+vfoo64 (unsigned long long* a)
-+{
-+  int i = 0;
-+  for (i = 0; i < N; ++i)
-+    a[i] = __builtin_bswap64 (a[i]);
-+}
-+
-+int
-+main (void)
-+{
-+  unsigned long long arr[N];
-+  unsigned long long expect[N];
-+  int i;
-+
-+  for (i = 0; i < N; ++i)
-+    {
-+      arr[i] = i;
-+      expect[i] = __builtin_bswap64 (i);
-+      if (y) /* Avoid vectorisation.  */
-+        abort ();
-+    }
-+
-+  vfoo64 (arr);
-+
-+  for (i = 0; i < N; ++i)
-+    {
-+      if (arr[i] != expect[i])
-+        abort ();
-+    }
-+
-+  return 0;
-+}
-+
-+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
-+/* { dg-final { cleanup-tree-dump "vect" } } */
---- a/src/gcc/testsuite/gcc.dg/ssp-3.c
-+++ b/src/gcc/testsuite/gcc.dg/ssp-3.c
-@@ -0,0 +1,16 @@
-+/* { dg-do assemble } */
-+/* { dg-options "-fstack-protector-strong -O1 -frename-registers" } */
-+/* { dg-require-effective-target fstack_protector } */
-+
-+extern int bar (const char *s, int *argc);
-+extern int baz (const char *s);
-+
-+char
-+foo (const char *s)
-+{
-+  int argc;
-+  int ret;
-+  if ( !bar (s, &argc))
-+    ret = baz (s);
-+  return *s;
-+}
---- a/src/gcc/testsuite/g++.dg/ipa/devirt-25.C
-+++ b/src/gcc/testsuite/g++.dg/ipa/devirt-25.C
-@@ -1,5 +1,6 @@
- /* { dg-do compile } */
- /* { dg-options "-O3 -fdump-ipa-cp"  } */
-+/* { dg-add-options bind_pic_locally } */
- 
- class ert_RefCounter {
-  protected:
---- a/src/gcc/objcp/ChangeLog.linaro
-+++ b/src/gcc/objcp/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/gcc/cp/ChangeLog.linaro
-+++ b/src/gcc/cp/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/gcc/compare-elim.c
-+++ b/src/gcc/compare-elim.c
-@@ -100,6 +100,9 @@
-      constants.  */
-   rtx in_a, in_b;
- 
-+  /* The REG_EH_REGION of the comparison.  */
-+  rtx eh_note;
-+
-   /* Information about how this comparison is used.  */
-   struct comparison_use uses[MAX_CMP_USE];
- 
-@@ -262,6 +265,7 @@
-   struct comparison *last_cmp;
-   rtx insn, next, last_clobber;
-   bool last_cmp_valid;
-+  bool need_purge = false;
-   bitmap killed;
- 
-   killed = BITMAP_ALLOC (NULL);
-@@ -303,44 +307,60 @@
-       if (src)
- 	{
- 	  enum machine_mode src_mode = GET_MODE (src);
-+	  rtx eh_note = NULL;
- 
--	  /* Eliminate a compare that's redundant with the previous.  */
--	  if (last_cmp_valid
--	      && rtx_equal_p (last_cmp->in_a, XEXP (src, 0))
--	      && rtx_equal_p (last_cmp->in_b, XEXP (src, 1)))
--	    {
--	      rtx flags, x;
--	      enum machine_mode new_mode
--		= targetm.cc_modes_compatible (last_cmp->orig_mode, src_mode);
-+	  if (flag_non_call_exceptions)
-+	    eh_note = find_reg_note (insn, REG_EH_REGION, NULL);
- 
--	      /* New mode is incompatible with the previous compare mode.  */
--	      if (new_mode == VOIDmode)
--		continue;
-+	  if (!last_cmp_valid)
-+	    goto dont_delete;
- 
--	      if (new_mode != last_cmp->orig_mode)
--		{
--		  flags = gen_rtx_REG (src_mode, targetm.flags_regnum);
-+	  /* Take care that it's in the same EH region.  */
-+	  if (flag_non_call_exceptions
-+	      && !rtx_equal_p (eh_note, last_cmp->eh_note))
-+	    goto dont_delete;
- 
--		  /* Generate new comparison for substitution.  */
--		  x = gen_rtx_COMPARE (new_mode, XEXP (src, 0), XEXP (src, 1));
--		  x = gen_rtx_SET (VOIDmode, flags, x);
-+	  /* Make sure the compare is redundant with the previous.  */
-+	  if (!rtx_equal_p (last_cmp->in_a, XEXP (src, 0))
-+	      || !rtx_equal_p (last_cmp->in_b, XEXP (src, 1)))
-+	    goto dont_delete;
- 
--		  if (!validate_change (last_cmp->insn,
--					&PATTERN (last_cmp->insn), x, false))
--		    continue;
-+	  /* New mode must be compatible with the previous compare mode.  */
-+	  {
-+	    enum machine_mode new_mode
-+	      = targetm.cc_modes_compatible (last_cmp->orig_mode, src_mode);
-+	    if (new_mode == VOIDmode)
-+	      goto dont_delete;
- 
--		  last_cmp->orig_mode = new_mode;
--		}
-+	    if (new_mode != last_cmp->orig_mode)
-+	      {
-+		rtx x, flags = gen_rtx_REG (src_mode, targetm.flags_regnum);
- 
--	      delete_insn (insn);
--	      continue;
--	    }
-+		/* Generate new comparison for substitution.  */
-+		x = gen_rtx_COMPARE (new_mode, XEXP (src, 0), XEXP (src, 1));
-+		x = gen_rtx_SET (VOIDmode, flags, x);
- 
-+		if (!validate_change (last_cmp->insn,
-+				      &PATTERN (last_cmp->insn), x, false))
-+		  goto dont_delete;
-+
-+		last_cmp->orig_mode = new_mode;
-+	      }
-+	  }
-+
-+	  /* All tests and substitutions succeeded!  */
-+	  if (eh_note)
-+	    need_purge = true;
-+	  delete_insn (insn);
-+	  continue;
-+
-+	dont_delete:
- 	  last_cmp = XCNEW (struct comparison);
- 	  last_cmp->insn = insn;
- 	  last_cmp->prev_clobber = last_clobber;
- 	  last_cmp->in_a = XEXP (src, 0);
- 	  last_cmp->in_b = XEXP (src, 1);
-+	  last_cmp->eh_note = eh_note;
- 	  last_cmp->orig_mode = src_mode;
- 	  all_compares.safe_push (last_cmp);
- 
-@@ -404,6 +424,11 @@
- 	    }
- 	}
-     }
-+
-+  /* If we deleted a compare with a REG_EH_REGION note, we may need to
-+     remove EH edges.  */
-+  if (need_purge)
-+    purge_dead_edges (bb);
- }
- 
- /* Find all comparisons in the function.  */
---- a/src/gcc/ira-int.h
-+++ b/src/gcc/ira-int.h
-@@ -281,6 +281,9 @@
-   /* Mode of the allocno which is the mode of the corresponding
-      pseudo-register.  */
-   ENUM_BITFIELD (machine_mode) mode : 8;
-+  /* Widest mode of the allocno which in at least one case could be
-+     for paradoxical subregs where wmode > mode.  */
-+  ENUM_BITFIELD (machine_mode) wmode : 8;
-   /* Register class which should be used for allocation for given
-      allocno.  NO_REGS means that we should use memory.  */
-   ENUM_BITFIELD (reg_class) aclass : 16;
-@@ -313,7 +316,7 @@
-      number (0, ...) - 2.  Value -1 is used for allocnos spilled by the
-      reload (at this point pseudo-register has only one allocno) which
-      did not get stack slot yet.  */
--  short int hard_regno;
-+  signed int hard_regno : 16;
-   /* Allocnos with the same regno are linked by the following member.
-      Allocnos corresponding to inner loops are first in the list (it
-      corresponds to depth-first traverse of the loops).  */
-@@ -430,6 +433,7 @@
- #define ALLOCNO_BAD_SPILL_P(A) ((A)->bad_spill_p)
- #define ALLOCNO_ASSIGNED_P(A) ((A)->assigned_p)
- #define ALLOCNO_MODE(A) ((A)->mode)
-+#define ALLOCNO_WMODE(A) ((A)->wmode)
- #define ALLOCNO_PREFS(A) ((A)->allocno_prefs)
- #define ALLOCNO_COPIES(A) ((A)->allocno_copies)
- #define ALLOCNO_HARD_REG_COSTS(A) ((A)->hard_reg_costs)
---- a/src/gcc/ira-color.c
-+++ b/src/gcc/ira-color.c
-@@ -1711,6 +1711,7 @@
-         {
- 	  ira_allocno_t conflict_a = OBJECT_ALLOCNO (conflict_obj);
- 	  enum reg_class conflict_aclass;
-+	  allocno_color_data_t data = ALLOCNO_COLOR_DATA (conflict_a);
- 
- 	  /* Reload can give another class so we need to check all
- 	     allocnos.  */
-@@ -1782,7 +1783,12 @@
- 		    hard_regno = ira_class_hard_regs[aclass][j];
- 		    ira_assert (hard_regno >= 0);
- 		    k = ira_class_hard_reg_index[conflict_aclass][hard_regno];
--		    if (k < 0)
-+		    if (k < 0
-+			   /* If HARD_REGNO is not available for CONFLICT_A,
-+			      the conflict would be ignored, since HARD_REGNO
-+			      will never be assigned to CONFLICT_A.  */
-+			|| !TEST_HARD_REG_BIT (data->profitable_hard_regs,
-+					       hard_regno))
- 		      continue;
- 		    full_costs[j] -= conflict_costs[k];
- 		  }
---- a/src/gcc/ifcvt.c
-+++ b/src/gcc/ifcvt.c
-@@ -1432,10 +1432,17 @@
-       end_sequence ();
-     }
- 
--  /* Don't even try if the comparison operands are weird.  */
-+  /* Don't even try if the comparison operands are weird
-+     except that the target supports cbranchcc4.  */
-   if (! general_operand (cmp_a, GET_MODE (cmp_a))
-       || ! general_operand (cmp_b, GET_MODE (cmp_b)))
--    return NULL_RTX;
-+    {
-+#if HAVE_cbranchcc4
-+      if (GET_MODE_CLASS (GET_MODE (cmp_a)) != MODE_CC
-+	  || cmp_b != const0_rtx)
-+#endif
-+	return NULL_RTX;
-+    }
- 
- #if HAVE_conditional_move
-   unsignedp = (code == LTU || code == GEU
-@@ -1753,7 +1760,12 @@
- {
-   rtx cond, set, insn;
-   int reverse;
-+  int allow_cc_mode = false;
-+#if HAVE_cbranchcc4
-+  allow_cc_mode = true;
-+#endif
- 
-+
-   /* If target is already mentioned in the known condition, return it.  */
-   if (reg_mentioned_p (target, if_info->cond))
-     {
-@@ -1874,7 +1886,7 @@
-     }
- 
-   cond = canonicalize_condition (if_info->jump, cond, reverse,
--				 earliest, target, false, true);
-+				 earliest, target, allow_cc_mode, true);
-   if (! cond || ! reg_mentioned_p (target, cond))
-     return NULL;
- 
-@@ -2325,6 +2337,10 @@
- {
-   rtx cond, set, tmp;
-   bool reverse;
-+  int allow_cc_mode = false;
-+#if HAVE_cbranchcc4
-+  allow_cc_mode = true;
-+#endif
- 
-   if (! any_condjump_p (jump))
-     return NULL_RTX;
-@@ -2361,7 +2377,7 @@
-   /* Otherwise, fall back on canonicalize_condition to do the dirty
-      work of manipulating MODE_CC values and COMPARE rtx codes.  */
-   tmp = canonicalize_condition (jump, cond, reverse, earliest,
--				NULL_RTX, false, true);
-+				NULL_RTX, allow_cc_mode, true);
- 
-   /* We don't handle side-effects in the condition, like handling
-      REG_INC notes and making sure no duplicate conditions are emitted.  */
---- a/src/gcc/expr.c
-+++ b/src/gcc/expr.c
-@@ -68,22 +68,6 @@
- #include "tree-ssa-address.h"
- #include "cfgexpand.h"
- 
--/* Decide whether a function's arguments should be processed
--   from first to last or from last to first.
--
--   They should if the stack and args grow in opposite directions, but
--   only if we have push insns.  */
--
--#ifdef PUSH_ROUNDING
--
--#ifndef PUSH_ARGS_REVERSED
--#if defined (STACK_GROWS_DOWNWARD) != defined (ARGS_GROW_DOWNWARD)
--#define PUSH_ARGS_REVERSED	/* If it's last to first.  */
--#endif
--#endif
--
--#endif
--
- #ifndef STACK_PUSH_CODE
- #ifdef STACK_GROWS_DOWNWARD
- #define STACK_PUSH_CODE PRE_DEC
-@@ -172,37 +156,6 @@
- static rtx const_vector_from_tree (tree);
- static void write_complex_part (rtx, rtx, bool);
- 
--/* This macro is used to determine whether move_by_pieces should be called
--   to perform a structure copy.  */
--#ifndef MOVE_BY_PIECES_P
--#define MOVE_BY_PIECES_P(SIZE, ALIGN) \
--  (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
--   < (unsigned int) MOVE_RATIO (optimize_insn_for_speed_p ()))
--#endif
--
--/* This macro is used to determine whether clear_by_pieces should be
--   called to clear storage.  */
--#ifndef CLEAR_BY_PIECES_P
--#define CLEAR_BY_PIECES_P(SIZE, ALIGN) \
--  (move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \
--   < (unsigned int) CLEAR_RATIO (optimize_insn_for_speed_p ()))
--#endif
--
--/* This macro is used to determine whether store_by_pieces should be
--   called to "memset" storage with byte values other than zero.  */
--#ifndef SET_BY_PIECES_P
--#define SET_BY_PIECES_P(SIZE, ALIGN) \
--  (move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \
--   < (unsigned int) SET_RATIO (optimize_insn_for_speed_p ()))
--#endif
--
--/* This macro is used to determine whether store_by_pieces should be
--   called to "memcpy" storage when the source is a constant string.  */
--#ifndef STORE_BY_PIECES_P
--#define STORE_BY_PIECES_P(SIZE, ALIGN) \
--  (move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \
--   < (unsigned int) MOVE_RATIO (optimize_insn_for_speed_p ()))
--#endif
- 
- /* This is run to set up which modes can be used
-    directly in memory and to initialize the block move optab.  It is run
-@@ -843,22 +796,16 @@
-   return mode;
- }
- 
--/* STORE_MAX_PIECES is the number of bytes at a time that we can
--   store efficiently.  Due to internal GCC limitations, this is
--   MOVE_MAX_PIECES limited by the number of bytes GCC can represent
--   for an immediate constant.  */
--
--#define STORE_MAX_PIECES  MIN (MOVE_MAX_PIECES, 2 * sizeof (HOST_WIDE_INT))
--
- /* Determine whether the LEN bytes can be moved by using several move
-    instructions.  Return nonzero if a call to move_by_pieces should
-    succeed.  */
- 
- int
--can_move_by_pieces (unsigned HOST_WIDE_INT len ATTRIBUTE_UNUSED,
--		    unsigned int align ATTRIBUTE_UNUSED)
-+can_move_by_pieces (unsigned HOST_WIDE_INT len,
-+		    unsigned int align)
- {
--  return MOVE_BY_PIECES_P (len, align);
-+  return targetm.use_by_pieces_infrastructure_p (len, align, MOVE_BY_PIECES,
-+						 optimize_insn_for_speed_p ());
- }
- 
- /* Generate several move instructions to copy LEN bytes from block FROM to
-@@ -1195,7 +1142,7 @@
-       set_mem_size (y, INTVAL (size));
-     }
- 
--  if (CONST_INT_P (size) && MOVE_BY_PIECES_P (INTVAL (size), align))
-+  if (CONST_INT_P (size) && can_move_by_pieces (INTVAL (size), align))
-     move_by_pieces (x, y, INTVAL (size), align, 0);
-   else if (emit_block_move_via_movmem (x, y, size, align,
- 				       expected_align, expected_size,
-@@ -2396,6 +2343,18 @@
-     = gen_rtx_EXPR_LIST (mode, gen_rtx_USE (VOIDmode, reg), *call_fusage);
- }
- 
-+/* Add a CLOBBER expression for REG to the (possibly empty) list pointed
-+   to by CALL_FUSAGE.  REG must denote a hard register.  */
-+
-+void
-+clobber_reg_mode (rtx *call_fusage, rtx reg, enum machine_mode mode)
-+{
-+  gcc_assert (REG_P (reg) && REGNO (reg) < FIRST_PSEUDO_REGISTER);
-+
-+  *call_fusage
-+    = gen_rtx_EXPR_LIST (mode, gen_rtx_CLOBBER (VOIDmode, reg), *call_fusage);
-+}
-+
- /* Add USE expressions to *CALL_FUSAGE for each of NREGS consecutive regs,
-    starting at REGNO.  All of these registers must be hard registers.  */
- 
-@@ -2498,9 +2457,11 @@
-   if (len == 0)
-     return 1;
- 
--  if (! (memsetp
--	 ? SET_BY_PIECES_P (len, align)
--	 : STORE_BY_PIECES_P (len, align)))
-+  if (!targetm.use_by_pieces_infrastructure_p (len, align,
-+					       memsetp
-+						 ? SET_BY_PIECES
-+						 : STORE_BY_PIECES,
-+					       optimize_insn_for_speed_p ()))
-     return 0;
- 
-   align = alignment_for_piecewise_move (STORE_MAX_PIECES, align);
-@@ -2576,9 +2537,13 @@
-       return to;
-     }
- 
--  gcc_assert (memsetp
--	      ? SET_BY_PIECES_P (len, align)
--	      : STORE_BY_PIECES_P (len, align));
-+  gcc_assert (targetm.use_by_pieces_infrastructure_p
-+		(len, align,
-+		 memsetp
-+		   ? SET_BY_PIECES
-+		   : STORE_BY_PIECES,
-+		 optimize_insn_for_speed_p ()));
-+
-   data.constfun = constfun;
-   data.constfundata = constfundata;
-   data.len = len;
-@@ -2815,7 +2780,9 @@
-   align = MEM_ALIGN (object);
- 
-   if (CONST_INT_P (size)
--      && CLEAR_BY_PIECES_P (INTVAL (size), align))
-+      && targetm.use_by_pieces_infrastructure_p (INTVAL (size), align,
-+						 CLEAR_BY_PIECES,
-+						 optimize_insn_for_speed_p ()))
-     clear_by_pieces (object, INTVAL (size), align);
-   else if (set_storage_via_setmem (object, size, const0_rtx, align,
- 				   expected_align, expected_size,
-@@ -4221,7 +4188,7 @@
- 	  && CONST_INT_P (size)
- 	  && skip == 0
- 	  && MEM_ALIGN (xinner) >= align
--	  && (MOVE_BY_PIECES_P ((unsigned) INTVAL (size) - used, align))
-+	  && can_move_by_pieces ((unsigned) INTVAL (size) - used, align)
- 	  /* Here we avoid the case of a structure whose weak alignment
- 	     forces many pushes of a small amount of data,
- 	     and such small pushes do rounding that causes trouble.  */
-@@ -4353,11 +4320,7 @@
-       /* Loop over all the words allocated on the stack for this arg.  */
-       /* We can do it by words, because any scalar bigger than a word
- 	 has a size a multiple of a word.  */
--#ifndef PUSH_ARGS_REVERSED
--      for (i = not_stack; i < size; i++)
--#else
-       for (i = size - 1; i >= not_stack; i--)
--#endif
- 	if (i >= not_stack + offset)
- 	  emit_push_insn (operand_subword_force (x, i, mode),
- 			  word_mode, NULL_TREE, NULL_RTX, align, 0, NULL_RTX,
-@@ -7838,7 +7801,7 @@
- 	    && ! (target != 0 && safe_from_p (target, exp, 1)))
- 		  || TREE_ADDRESSABLE (exp)
- 		  || (tree_fits_uhwi_p (TYPE_SIZE_UNIT (type))
--		      && (! MOVE_BY_PIECES_P
-+		      && (! can_move_by_pieces
- 				     (tree_to_uhwi (TYPE_SIZE_UNIT (type)),
- 				      TYPE_ALIGN (type)))
- 		      && ! mostly_zeros_p (exp))))
---- a/src/gcc/expr.h
-+++ b/src/gcc/expr.h
-@@ -346,6 +346,7 @@
- /* Mark REG as holding a parameter for the next CALL_INSN.
-    Mode is TYPE_MODE of the non-promoted parameter, or VOIDmode.  */
- extern void use_reg_mode (rtx *, rtx, enum machine_mode);
-+extern void clobber_reg_mode (rtx *, rtx, enum machine_mode);
- 
- extern rtx copy_blkmode_to_reg (enum machine_mode, tree);
- 
-@@ -356,6 +357,13 @@
-   use_reg_mode (fusage, reg, VOIDmode);
- }
- 
-+/* Mark REG as clobbered by the call with FUSAGE as CALL_INSN_FUNCTION_USAGE.  */
-+static inline void
-+clobber_reg (rtx *fusage, rtx reg)
-+{
-+  clobber_reg_mode (fusage, reg, VOIDmode);
-+}
-+
- /* Mark NREGS consecutive regs, starting at REGNO, as holding parameters
-    for the next CALL_INSN.  */
- extern void use_regs (rtx *, int, int);
---- a/src/gcc/go/ChangeLog.linaro
-+++ b/src/gcc/go/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/gcc/genattrtab.c
-+++ b/src/gcc/genattrtab.c
-@@ -4765,6 +4765,7 @@
- 
- static struct bypass_list *all_bypasses;
- static size_t n_bypasses;
-+static size_t n_bypassed;
- 
- static void
- gen_bypass_1 (const char *s, size_t len)
-@@ -4810,12 +4811,18 @@
-   struct bypass_list *b;
-   struct insn_reserv *r;
- 
-+  n_bypassed = 0;
-+
-   /* The reservation list is likely to be much longer than the bypass
-      list.  */
-   for (r = all_insn_reservs; r; r = r->next)
-     for (b = all_bypasses; b; b = b->next)
-       if (fnmatch (b->pattern, r->name, 0) == 0)
--	r->bypassed = true;
-+        {
-+          n_bypassed++;
-+          r->bypassed = true;
-+          break;
-+        }
- }
- 
- /* Check that attribute NAME is used in define_insn_reservation condition
-@@ -5074,7 +5081,7 @@
-       process_bypasses ();
- 
-       byps_exp = rtx_alloc (COND);
--      XVEC (byps_exp, 0) = rtvec_alloc (n_bypasses * 2);
-+      XVEC (byps_exp, 0) = rtvec_alloc (n_bypassed * 2);
-       XEXP (byps_exp, 1) = make_numeric_value (0);
-       for (decl = all_insn_reservs, i = 0;
- 	   decl;
---- a/src/gcc/ada/ChangeLog.linaro
-+++ b/src/gcc/ada/ChangeLog.linaro
-@@ -0,0 +1,95 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-05-13  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209653,209866,209871.
-+
-+	2014-04-28  Richard Henderson  <rth@redhat.com>
-+
-+	* gcc-interface/Makefile.in: Support aarch64-linux.
-+
-+	2014-04-28  Eric Botcazou  <ebotcazou@adacore.com>
-+
-+	* exp_dbug.ads (Get_External_Name): Add 'False' default to Has_Suffix,
-+	add 'Suffix' parameter and adjust comment.
-+	(Get_External_Name_With_Suffix): Delete.
-+	* exp_dbug.adb (Get_External_Name_With_Suffix): Merge into...
-+	(Get_External_Name): ...here.  Add 'False' default to Has_Suffix, add
-+	'Suffix' parameter.
-+	(Get_Encoded_Name): Remove 2nd argument in call to Get_External_Name.
-+	Call Get_External_Name instead of Get_External_Name_With_Suffix.
-+	(Get_Secondary_DT_External_Name): Likewise.
-+	* exp_cg.adb (Write_Call_Info): Likewise.
-+	* exp_disp.adb (Export_DT): Likewise.
-+	(Import_DT): Likewise.
-+	* comperr.ads (Compiler_Abort): Remove Code parameter and add From_GCC
-+	parameter with False default.
-+	* comperr.adb (Compiler_Abort): Likewise.  Adjust accordingly.
-+	* types.h (Fat_Pointer): Rename into...
-+	(String_Pointer): ...this.  Add comment on interfacing rules.
-+	* fe.h (Compiler_Abort): Adjust for above renaming.
-+	(Error_Msg_N): Likewise.
-+	(Error_Msg_NE): Likewise.
-+	(Get_External_Name): Likewise.  Add third parameter.
-+	(Get_External_Name_With_Suffix): Delete.
-+	* gcc-interface/decl.c (STDCALL_PREFIX): Define.
-+	(create_concat_name): Adjust call to Get_External_Name, remove call to
-+	Get_External_Name_With_Suffix, use STDCALL_PREFIX, adjust for renaming.
-+	* gcc-interface/trans.c (post_error): Likewise.
-+	(post_error_ne): Likewise.
-+	* gcc-interface/misc.c (internal_error_function): Likewise.
-+
-+	2014-04-22  Richard Henderson  <rth@redhat.com>
-+
-+	* init.c [__linux__] (HAVE_GNAT_ALTERNATE_STACK): New define.
-+	(__gnat_alternate_stack): Enable for all linux except ia64.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/gcc/common/config/aarch64/aarch64-common.c
-+++ b/src/gcc/common/config/aarch64/aarch64-common.c
-@@ -44,6 +44,8 @@
-   {
-     /* Enable section anchors by default at -O1 or higher.  */
-     { OPT_LEVELS_1_PLUS, OPT_fsection_anchors, NULL, 1 },
-+    /* Enable -fsched-pressure by default when optimizing.  */
-+    { OPT_LEVELS_1_PLUS, OPT_fsched_pressure, NULL, 1 },
-     /* Enable redundant extension instructions removal at -O2 and higher.  */
-     { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 },
-     { OPT_LEVELS_NONE, 0, NULL, 0 }
---- a/src/gcc/fortran/ChangeLog.linaro
-+++ b/src/gcc/fortran/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/gcc/configure.ac
-+++ b/src/gcc/configure.ac
-@@ -809,7 +809,7 @@
- )
- AC_SUBST(CONFIGURE_SPECS)
- 
--ACX_PKGVERSION([GCC])
-+ACX_PKGVERSION([Linaro GCC `cat $srcdir/LINARO-VERSION`])
- ACX_BUGURL([http://gcc.gnu.org/bugs.html])
- 
- # Sanity check enable_languages in case someone does not run the toplevel
---- a/src/gcc/ira-build.c
-+++ b/src/gcc/ira-build.c
-@@ -523,6 +523,7 @@
-   ALLOCNO_BAD_SPILL_P (a) = false;
-   ALLOCNO_ASSIGNED_P (a) = false;
-   ALLOCNO_MODE (a) = (regno < 0 ? VOIDmode : PSEUDO_REGNO_MODE (regno));
-+  ALLOCNO_WMODE (a) = ALLOCNO_MODE (a);
-   ALLOCNO_PREFS (a) = NULL;
-   ALLOCNO_COPIES (a) = NULL;
-   ALLOCNO_HARD_REG_COSTS (a) = NULL;
-@@ -892,6 +893,7 @@
-   parent = ALLOCNO_LOOP_TREE_NODE (a)->parent;
-   cap = ira_create_allocno (ALLOCNO_REGNO (a), true, parent);
-   ALLOCNO_MODE (cap) = ALLOCNO_MODE (a);
-+  ALLOCNO_WMODE (cap) = ALLOCNO_WMODE (a);
-   aclass = ALLOCNO_CLASS (a);
-   ira_set_allocno_class (cap, aclass);
-   ira_create_allocno_objects (cap);
-@@ -1856,9 +1858,9 @@
- 
- /* This recursive function creates allocnos corresponding to
-    pseudo-registers containing in X.  True OUTPUT_P means that X is
--   a lvalue.  */
-+   an lvalue.  PARENT corresponds to the parent expression of X.  */
- static void
--create_insn_allocnos (rtx x, bool output_p)
-+create_insn_allocnos (rtx x, rtx outer, bool output_p)
- {
-   int i, j;
-   const char *fmt;
-@@ -1873,7 +1875,15 @@
- 	  ira_allocno_t a;
- 
- 	  if ((a = ira_curr_regno_allocno_map[regno]) == NULL)
--	    a = ira_create_allocno (regno, false, ira_curr_loop_tree_node);
-+	    {
-+	      a = ira_create_allocno (regno, false, ira_curr_loop_tree_node);
-+	      if (outer != NULL && GET_CODE (outer) == SUBREG)
-+		{
-+		  enum machine_mode wmode = GET_MODE (outer);
-+		  if (GET_MODE_SIZE (wmode) > GET_MODE_SIZE (ALLOCNO_WMODE (a)))
-+		    ALLOCNO_WMODE (a) = wmode;
-+		}
-+	    }
- 
- 	  ALLOCNO_NREFS (a)++;
- 	  ALLOCNO_FREQ (a) += REG_FREQ_FROM_BB (curr_bb);
-@@ -1884,25 +1894,25 @@
-     }
-   else if (code == SET)
-     {
--      create_insn_allocnos (SET_DEST (x), true);
--      create_insn_allocnos (SET_SRC (x), false);
-+      create_insn_allocnos (SET_DEST (x), NULL, true);
-+      create_insn_allocnos (SET_SRC (x), NULL, false);
-       return;
-     }
-   else if (code == CLOBBER)
-     {
--      create_insn_allocnos (XEXP (x, 0), true);
-+      create_insn_allocnos (XEXP (x, 0), NULL, true);
-       return;
-     }
-   else if (code == MEM)
-     {
--      create_insn_allocnos (XEXP (x, 0), false);
-+      create_insn_allocnos (XEXP (x, 0), NULL, false);
-       return;
-     }
-   else if (code == PRE_DEC || code == POST_DEC || code == PRE_INC ||
- 	   code == POST_INC || code == POST_MODIFY || code == PRE_MODIFY)
-     {
--      create_insn_allocnos (XEXP (x, 0), true);
--      create_insn_allocnos (XEXP (x, 0), false);
-+      create_insn_allocnos (XEXP (x, 0), NULL, true);
-+      create_insn_allocnos (XEXP (x, 0), NULL, false);
-       return;
-     }
- 
-@@ -1910,10 +1920,10 @@
-   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
-     {
-       if (fmt[i] == 'e')
--	create_insn_allocnos (XEXP (x, i), output_p);
-+	create_insn_allocnos (XEXP (x, i), x, output_p);
-       else if (fmt[i] == 'E')
- 	for (j = 0; j < XVECLEN (x, i); j++)
--	  create_insn_allocnos (XVECEXP (x, i, j), output_p);
-+	  create_insn_allocnos (XVECEXP (x, i, j), x, output_p);
-     }
- }
- 
-@@ -1932,7 +1942,7 @@
-   ira_assert (bb != NULL);
-   FOR_BB_INSNS_REVERSE (bb, insn)
-     if (NONDEBUG_INSN_P (insn))
--      create_insn_allocnos (PATTERN (insn), false);
-+      create_insn_allocnos (PATTERN (insn), NULL, false);
-   /* It might be a allocno living through from one subloop to
-      another.  */
-   EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (bb), FIRST_PSEUDO_REGISTER, i, bi)
---- a/src/gcc/calls.c
-+++ b/src/gcc/calls.c
-@@ -1104,8 +1104,6 @@
- {
-   CUMULATIVE_ARGS *args_so_far_pnt = get_cumulative_args (args_so_far);
-   location_t loc = EXPR_LOCATION (exp);
--  /* 1 if scanning parms front to back, -1 if scanning back to front.  */
--  int inc;
- 
-   /* Count arg position in order args appear.  */
-   int argpos;
-@@ -1116,22 +1114,9 @@
-   args_size->var = 0;
- 
-   /* In this loop, we consider args in the order they are written.
--     We fill up ARGS from the front or from the back if necessary
--     so that in any case the first arg to be pushed ends up at the front.  */
-+     We fill up ARGS from the back.  */
- 
--  if (PUSH_ARGS_REVERSED)
--    {
--      i = num_actuals - 1, inc = -1;
--      /* In this case, must reverse order of args
--	 so that we compute and push the last arg first.  */
--    }
--  else
--    {
--      i = 0, inc = 1;
--    }
--
--  /* First fill in the actual arguments in the ARGS array, splitting
--     complex arguments if necessary.  */
-+  i = num_actuals - 1;
-   {
-     int j = i;
-     call_expr_arg_iterator iter;
-@@ -1140,7 +1125,7 @@
-     if (struct_value_addr_value)
-       {
- 	args[j].tree_value = struct_value_addr_value;
--	j += inc;
-+	j--;
-       }
-     FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
-       {
-@@ -1152,17 +1137,17 @@
- 	  {
- 	    tree subtype = TREE_TYPE (argtype);
- 	    args[j].tree_value = build1 (REALPART_EXPR, subtype, arg);
--	    j += inc;
-+	    j--;
- 	    args[j].tree_value = build1 (IMAGPART_EXPR, subtype, arg);
- 	  }
- 	else
- 	  args[j].tree_value = arg;
--	j += inc;
-+	j--;
-       }
-   }
- 
-   /* I counts args in order (to be) pushed; ARGPOS counts in order written.  */
--  for (argpos = 0; argpos < num_actuals; i += inc, argpos++)
-+  for (argpos = 0; argpos < num_actuals; i--, argpos++)
-     {
-       tree type = TREE_TYPE (args[i].tree_value);
-       int unsignedp;
-@@ -2952,9 +2937,8 @@
- 
-       compute_argument_addresses (args, argblock, num_actuals);
- 
--      /* If we push args individually in reverse order, perform stack alignment
--	 before the first push (the last arg).  */
--      if (PUSH_ARGS_REVERSED && argblock == 0
-+      /* Perform stack alignment before the first push (the last arg).  */
-+      if (argblock == 0
-           && adjusted_args_size.constant > reg_parm_stack_space
- 	  && adjusted_args_size.constant != unadjusted_args_size)
- 	{
-@@ -3097,12 +3081,6 @@
- 		sibcall_failure = 1;
- 	    }
- 
--      /* If we pushed args in forward order, perform stack alignment
--	 after pushing the last arg.  */
--      if (!PUSH_ARGS_REVERSED && argblock == 0)
--	anti_adjust_stack (GEN_INT (adjusted_args_size.constant
--				    - unadjusted_args_size));
--
-       /* If register arguments require space on the stack and stack space
- 	 was not preallocated, allocate stack space here for arguments
- 	 passed in registers.  */
-@@ -3152,8 +3130,7 @@
-       if (pass == 1 && (return_flags & ERF_RETURNS_ARG))
- 	{
- 	  int arg_nr = return_flags & ERF_RETURN_ARG_MASK;
--	  if (PUSH_ARGS_REVERSED)
--	    arg_nr = num_actuals - arg_nr - 1;
-+	  arg_nr = num_actuals - arg_nr - 1;
- 	  if (arg_nr >= 0
- 	      && arg_nr < num_actuals
- 	      && args[arg_nr].reg
-@@ -3597,7 +3574,6 @@
-      isn't present here, so we default to native calling abi here.  */
-   tree fndecl ATTRIBUTE_UNUSED = NULL_TREE; /* library calls default to host calling abi ? */
-   tree fntype ATTRIBUTE_UNUSED = NULL_TREE; /* library calls default to host calling abi ? */
--  int inc;
-   int count;
-   rtx argblock = 0;
-   CUMULATIVE_ARGS args_so_far_v;
-@@ -3946,22 +3922,13 @@
- 	argblock = push_block (GEN_INT (args_size.constant), 0, 0);
-     }
- 
--  /* If we push args individually in reverse order, perform stack alignment
-+  /* We push args individually in reverse order, perform stack alignment
-      before the first push (the last arg).  */
--  if (argblock == 0 && PUSH_ARGS_REVERSED)
-+  if (argblock == 0)
-     anti_adjust_stack (GEN_INT (args_size.constant
- 				- original_args_size.constant));
- 
--  if (PUSH_ARGS_REVERSED)
--    {
--      inc = -1;
--      argnum = nargs - 1;
--    }
--  else
--    {
--      inc = 1;
--      argnum = 0;
--    }
-+  argnum = nargs - 1;
- 
- #ifdef REG_PARM_STACK_SPACE
-   if (ACCUMULATE_OUTGOING_ARGS)
-@@ -3978,7 +3945,7 @@
- 
-   /* ARGNUM indexes the ARGVEC array in the order in which the arguments
-      are to be pushed.  */
--  for (count = 0; count < nargs; count++, argnum += inc)
-+  for (count = 0; count < nargs; count++, argnum--)
-     {
-       enum machine_mode mode = argvec[argnum].mode;
-       rtx val = argvec[argnum].value;
-@@ -4080,17 +4047,8 @@
- 	}
-     }
- 
--  /* If we pushed args in forward order, perform stack alignment
--     after pushing the last arg.  */
--  if (argblock == 0 && !PUSH_ARGS_REVERSED)
--    anti_adjust_stack (GEN_INT (args_size.constant
--				- original_args_size.constant));
-+  argnum = nargs - 1;
- 
--  if (PUSH_ARGS_REVERSED)
--    argnum = nargs - 1;
--  else
--    argnum = 0;
--
-   fun = prepare_call_address (NULL, fun, NULL, &call_fusage, 0, 0);
- 
-   /* Now load any reg parms into their regs.  */
-@@ -4097,7 +4055,7 @@
- 
-   /* ARGNUM indexes the ARGVEC array in the order in which the arguments
-      are to be pushed.  */
--  for (count = 0; count < nargs; count++, argnum += inc)
-+  for (count = 0; count < nargs; count++, argnum--)
-     {
-       enum machine_mode mode = argvec[argnum].mode;
-       rtx val = argvec[argnum].value;
---- a/src/gcc/cfgexpand.c
-+++ b/src/gcc/cfgexpand.c
-@@ -1292,7 +1292,12 @@
-   else if (TREE_CODE (var) == VAR_DECL && DECL_HARD_REGISTER (var))
-     {
-       if (really_expand)
--        expand_one_hard_reg_var (var);
-+	{
-+	  expand_one_hard_reg_var (var);
-+	  if (!DECL_HARD_REGISTER (var))
-+	    /* Invalid register specification.  */
-+	    expand_one_error_var (var);
-+	}
-     }
-   else if (use_register_for_decl (var))
-     {
---- a/src/gcc/explow.c
-+++ b/src/gcc/explow.c
-@@ -329,11 +329,13 @@
-    an address in the address space's address mode, or vice versa (TO_MODE says
-    which way).  We take advantage of the fact that pointers are not allowed to
-    overflow by commuting arithmetic operations over conversions so that address
--   arithmetic insns can be used.  */
-+   arithmetic insns can be used. IN_CONST is true if this conversion is inside
-+   a CONST.  */
- 
--rtx
--convert_memory_address_addr_space (enum machine_mode to_mode ATTRIBUTE_UNUSED,
--				   rtx x, addr_space_t as ATTRIBUTE_UNUSED)
-+static rtx
-+convert_memory_address_addr_space_1 (enum machine_mode to_mode ATTRIBUTE_UNUSED,
-+				     rtx x, addr_space_t as ATTRIBUTE_UNUSED,
-+				     bool in_const)
- {
- #ifndef POINTERS_EXTEND_UNSIGNED
-   gcc_assert (GET_MODE (x) == to_mode || GET_MODE (x) == VOIDmode);
-@@ -389,32 +391,29 @@
- 
-     case CONST:
-       return gen_rtx_CONST (to_mode,
--			    convert_memory_address_addr_space
--			      (to_mode, XEXP (x, 0), as));
-+			    convert_memory_address_addr_space_1
-+			      (to_mode, XEXP (x, 0), as, true));
-       break;
- 
-     case PLUS:
-     case MULT:
--      /* FIXME: For addition, we used to permute the conversion and
--	 addition operation only if one operand is a constant and
--	 converting the constant does not change it or if one operand
--	 is a constant and we are using a ptr_extend instruction
--	 (POINTERS_EXTEND_UNSIGNED < 0) even if the resulting address
--	 may overflow/underflow.  We relax the condition to include
--	 zero-extend (POINTERS_EXTEND_UNSIGNED > 0) since the other
--	 parts of the compiler depend on it.  See PR 49721.
--
-+      /* For addition we can safely permute the conversion and addition
-+	 operation if one operand is a constant and converting the constant
-+	 does not change it or if one operand is a constant and we are
-+	 using a ptr_extend instruction  (POINTERS_EXTEND_UNSIGNED < 0).
- 	 We can always safely permute them if we are making the address
--	 narrower.  */
-+	 narrower. Inside a CONST RTL, this is safe for both pointers
-+	 zero or sign extended as pointers cannot wrap. */
-       if (GET_MODE_SIZE (to_mode) < GET_MODE_SIZE (from_mode)
- 	  || (GET_CODE (x) == PLUS
- 	      && CONST_INT_P (XEXP (x, 1))
--	      && (POINTERS_EXTEND_UNSIGNED != 0
--		  || XEXP (x, 1) == convert_memory_address_addr_space
--		  			(to_mode, XEXP (x, 1), as))))
-+	      && ((in_const && POINTERS_EXTEND_UNSIGNED != 0)
-+		  || XEXP (x, 1) == convert_memory_address_addr_space_1
-+				     (to_mode, XEXP (x, 1), as, in_const)
-+                  || POINTERS_EXTEND_UNSIGNED < 0)))
- 	return gen_rtx_fmt_ee (GET_CODE (x), to_mode,
--			       convert_memory_address_addr_space
--				 (to_mode, XEXP (x, 0), as),
-+			       convert_memory_address_addr_space_1
-+				 (to_mode, XEXP (x, 0), as, in_const),
- 			       XEXP (x, 1));
-       break;
- 
-@@ -426,6 +425,18 @@
- 			x, POINTERS_EXTEND_UNSIGNED);
- #endif /* defined(POINTERS_EXTEND_UNSIGNED) */
- }
-+
-+/* Given X, a memory address in address space AS' pointer mode, convert it to
-+   an address in the address space's address mode, or vice versa (TO_MODE says
-+   which way).  We take advantage of the fact that pointers are not allowed to
-+   overflow by commuting arithmetic operations over conversions so that address
-+   arithmetic insns can be used.  */
-+
-+rtx
-+convert_memory_address_addr_space (enum machine_mode to_mode, rtx x, addr_space_t as)
-+{
-+  return convert_memory_address_addr_space_1 (to_mode, x, as, false);
-+}
- 
- /* Return something equivalent to X but valid as a memory address for something
-    of mode MODE in the named address space AS.  When X is not itself valid,
---- a/src/gcc/lto/ChangeLog.linaro
-+++ b/src/gcc/lto/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/gcc/po/ChangeLog.linaro
-+++ b/src/gcc/po/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/gcc/varasm.c
-+++ b/src/gcc/varasm.c
-@@ -1335,6 +1335,11 @@
- 	  /* As a register variable, it has no section.  */
- 	  return;
- 	}
-+      /* Avoid internal errors from invalid register
-+	 specifications.  */
-+      SET_DECL_ASSEMBLER_NAME (decl, NULL_TREE);
-+      DECL_HARD_REGISTER (decl) = 0;
-+      return;
-     }
-   /* Now handle ordinary static variables and functions (in memory).
-      Also handle vars declared register invalidly.  */
---- a/src/gcc/sched-deps.c
-+++ b/src/gcc/sched-deps.c
-@@ -2828,35 +2828,42 @@
-     sched_deps_info->finish_rhs ();
- }
- 
--/* Try to group comparison and the following conditional jump INSN if
--   they're already adjacent. This is to prevent scheduler from scheduling
--   them apart.  */
-+/* Try to group two fuseable insns together to prevent scheduler
-+   from scheduling them apart.  */
- 
- static void
--try_group_insn (rtx insn)
-+sched_macro_fuse_insns (rtx insn)
- {
--  unsigned int condreg1, condreg2;
--  rtx cc_reg_1;
-   rtx prev;
- 
--  if (!any_condjump_p (insn))
--    return;
-+  if (any_condjump_p (insn))
-+    {
-+      unsigned int condreg1, condreg2;
-+      rtx cc_reg_1;
-+      targetm.fixed_condition_code_regs (&condreg1, &condreg2);
-+      cc_reg_1 = gen_rtx_REG (CCmode, condreg1);
-+      prev = prev_nonnote_nondebug_insn (insn);
-+      if (!reg_referenced_p (cc_reg_1, PATTERN (insn))
-+          || !prev
-+          || !modified_in_p (cc_reg_1, prev))
-+        return;
-+    }
-+  else
-+    {
-+      rtx insn_set = single_set (insn);
- 
--  targetm.fixed_condition_code_regs (&condreg1, &condreg2);
--  cc_reg_1 = gen_rtx_REG (CCmode, condreg1);
--  prev = prev_nonnote_nondebug_insn (insn);
--  if (!reg_referenced_p (cc_reg_1, PATTERN (insn))
--      || !prev
--      || !modified_in_p (cc_reg_1, prev))
--    return;
-+      prev = prev_nonnote_nondebug_insn (insn);
-+      if (!prev
-+          || !insn_set
-+          || !single_set (prev)
-+          || !modified_in_p (SET_DEST (insn_set), prev))
-+        return;
- 
--  /* Different microarchitectures support macro fusions for different
--     combinations of insn pairs.  */
--  if (!targetm.sched.macro_fusion_pair_p
--      || !targetm.sched.macro_fusion_pair_p (prev, insn))
--    return;
-+    }
- 
--  SCHED_GROUP_P (insn) = 1;
-+  if (targetm.sched.macro_fusion_pair_p (prev, insn))
-+    SCHED_GROUP_P (insn) = 1;
-+
- }
- 
- /* Analyze an INSN with pattern X to find all dependencies.  */
-@@ -2885,7 +2892,7 @@
-   /* Group compare and branch insns for macro-fusion.  */
-   if (targetm.sched.macro_fusion_p
-       && targetm.sched.macro_fusion_p ())
--    try_group_insn (insn);
-+    sched_macro_fuse_insns (insn);
- 
-   if (may_trap_p (x))
-     /* Avoid moving trapping instructions across function calls that might
---- a/src/gcc/var-tracking.c
-+++ b/src/gcc/var-tracking.c
-@@ -5997,7 +5997,8 @@
-     {
-       cselib_val *oval = cselib_lookup (oloc, GET_MODE (oloc), 0, VOIDmode);
- 
--      gcc_assert (oval != v);
-+      if (oval == v)
-+	return;
-       gcc_assert (REG_P (oloc) || MEM_P (oloc));
- 
-       if (oval && !cselib_preserved_value_p (oval))
---- a/src/gcc/system.h
-+++ b/src/gcc/system.h
-@@ -830,7 +830,8 @@
- 	CAN_DEBUG_WITHOUT_FP UNLIKELY_EXECUTED_TEXT_SECTION_NAME	\
- 	HOT_TEXT_SECTION_NAME LEGITIMATE_CONSTANT_P ALWAYS_STRIP_DOTDOT	\
- 	OUTPUT_ADDR_CONST_EXTRA SMALL_REGISTER_CLASSES ASM_OUTPUT_IDENT	\
--	ASM_BYTE_OP MEMBER_TYPE_FORCES_BLK
-+	ASM_BYTE_OP MEMBER_TYPE_FORCES_BLK CLEAR_BY_PIECES_P		\
-+ 	MOVE_BY_PIECES_P SET_BY_PIECES_P STORE_BY_PIECES_P
- 
- /* Target macros only used for code built for the target, that have
-    moved to libgcc-tm.h or have never been present elsewhere.  */
-@@ -912,7 +913,8 @@
- 	USE_COMMON_FOR_ONE_ONLY IFCVT_EXTRA_FIELDS IFCVT_INIT_EXTRA_FIELDS \
- 	CASE_USE_BIT_TESTS FIXUNS_TRUNC_LIKE_FIX_TRUNC                     \
-         GO_IF_MODE_DEPENDENT_ADDRESS DELAY_SLOTS_FOR_EPILOGUE              \
--        ELIGIBLE_FOR_EPILOGUE_DELAY TARGET_C99_FUNCTIONS TARGET_HAS_SINCOS
-+        ELIGIBLE_FOR_EPILOGUE_DELAY TARGET_C99_FUNCTIONS TARGET_HAS_SINCOS \
-+	LARGEST_EXPONENT_IS_NORNAL ROUND_TOWARDS_ZERO
- 
- /* Hooks that are no longer used.  */
-  #pragma GCC poison LANG_HOOKS_FUNCTION_MARK LANG_HOOKS_FUNCTION_FREE	\
---- a/src/gcc/config.gcc
-+++ b/src/gcc/config.gcc
-@@ -312,8 +312,9 @@
- aarch64*-*-*)
- 	cpu_type=aarch64
- 	need_64bit_hwint=yes
--	extra_headers="arm_neon.h"
-+	extra_headers="arm_neon.h arm_acle.h"
- 	extra_objs="aarch64-builtins.o aarch-common.o"
-+	target_gtfiles="\$(srcdir)/config/aarch64/aarch64-builtins.c"
- 	target_has_targetm_common=yes
- 	;;
- alpha*-*-*)
---- a/src/gcc/Makefile.in
-+++ b/src/gcc/Makefile.in
-@@ -814,10 +814,12 @@
- DEVPHASE    := $(srcdir)/DEV-PHASE # experimental, prerelease, ""
- DATESTAMP   := $(srcdir)/DATESTAMP # YYYYMMDD or empty
- REVISION    := $(srcdir)/REVISION  # [BRANCH revision XXXXXX]
-+LINAROVER   := $(srcdir)/LINARO-VERSION # M.x-YYYY.MM[-S][~dev]
- 
- BASEVER_c   := $(shell cat $(BASEVER))
- DEVPHASE_c  := $(shell cat $(DEVPHASE))
- DATESTAMP_c := $(shell cat $(DATESTAMP))
-+LINAROVER_c := $(shell cat $(LINAROVER))
- 
- ifeq (,$(wildcard $(REVISION)))
- REVISION_c  :=
-@@ -838,6 +840,7 @@
- DATESTAMP_s := "\"$(if $(DEVPHASE_c), $(DATESTAMP_c))\""
- PKGVERSION_s:= "\"@PKGVERSION@\""
- BUGURL_s    := "\"@REPORT_BUGS_TO@\""
-+LINAROVER_s := "\"$(LINAROVER_c)\""
- 
- PKGVERSION  := @PKGVERSION@
- BUGURL_TEXI := @REPORT_BUGS_TEXI@
-@@ -2542,8 +2545,9 @@
-   -DSTANDARD_EXEC_PREFIX=\"$(libdir)/gcc/\" \
-   @TARGET_SYSTEM_ROOT_DEFINE@
- 
--CFLAGS-cppbuiltin.o += $(PREPROCESSOR_DEFINES) -DBASEVER=$(BASEVER_s)
--cppbuiltin.o: $(BASEVER)
-+CFLAGS-cppbuiltin.o += $(PREPROCESSOR_DEFINES) -DBASEVER=$(BASEVER_s) \
-+	-DLINAROVER=$(LINAROVER_s)
-+cppbuiltin.o: $(BASEVER) $(LINAROVER)
- 
- CFLAGS-cppdefault.o += $(PREPROCESSOR_DEFINES)
- 
-@@ -2799,8 +2803,7 @@
- 	 gcov.texi trouble.texi bugreport.texi service.texi		\
- 	 contribute.texi compat.texi funding.texi gnu.texi gpl_v3.texi	\
- 	 fdl.texi contrib.texi cppenv.texi cppopts.texi avr-mmcu.texi	\
--	 implement-c.texi implement-cxx.texi arm-neon-intrinsics.texi	\
--	 arm-acle-intrinsics.texi
-+	 implement-c.texi implement-cxx.texi
- 
- # we explicitly use $(srcdir)/doc/tm.texi here to avoid confusion with
- # the generated tm.texi; the latter might have a more recent timestamp,
---- a/src/gcc/tree-cfg.c
-+++ b/src/gcc/tree-cfg.c
-@@ -2594,7 +2594,7 @@
-    near its "logical" location.  This is of most help to humans looking
-    at debugging dumps.  */
- 
--static basic_block
-+basic_block
- split_edge_bb_loc (edge edge_in)
- {
-   basic_block dest = edge_in->dest;
---- a/src/gcc/tree-cfg.h
-+++ b/src/gcc/tree-cfg.h
-@@ -62,6 +62,7 @@
- extern tree gimple_block_label (basic_block);
- extern void add_phi_args_after_copy_bb (basic_block);
- extern void add_phi_args_after_copy (basic_block *, unsigned, edge);
-+extern basic_block split_edge_bb_loc (edge);
- extern bool gimple_duplicate_sese_region (edge, edge, basic_block *, unsigned,
- 					basic_block *, bool);
- extern bool gimple_duplicate_sese_tail (edge, edge, basic_block *, unsigned,
---- a/src/gcc/ree.c
-+++ b/src/gcc/ree.c
-@@ -794,6 +794,14 @@
-       if (!SCALAR_INT_MODE_P (GET_MODE (SET_DEST (PATTERN (cand->insn)))))
- 	return false;
- 
-+      enum machine_mode dst_mode = GET_MODE (SET_DEST (PATTERN (cand->insn)));
-+      rtx src_reg = get_extended_src_reg (SET_SRC (PATTERN (cand->insn)));
-+
-+      /* Ensure the number of hard registers of the copy match.  */
-+      if (HARD_REGNO_NREGS (REGNO (src_reg), dst_mode)
-+	  != HARD_REGNO_NREGS (REGNO (src_reg), GET_MODE (src_reg)))
-+	return false;
-+
-       /* There's only one reaching def.  */
-       rtx def_insn = state->defs_list[0];
- 
-@@ -843,7 +851,7 @@
-       start_sequence ();
-       rtx pat = PATTERN (cand->insn);
-       rtx new_dst = gen_rtx_REG (GET_MODE (SET_DEST (pat)),
--                                 REGNO (XEXP (SET_SRC (pat), 0)));
-+                                 REGNO (get_extended_src_reg (SET_SRC (pat))));
-       rtx new_src = gen_rtx_REG (GET_MODE (SET_DEST (pat)),
-                                  REGNO (SET_DEST (pat)));
-       emit_move_insn (new_dst, new_src);
---- a/src/gcc/config/s390/s390.c
-+++ b/src/gcc/config/s390/s390.c
-@@ -12066,6 +12066,18 @@
-   register_pass (&insert_pass_s390_early_mach);
- }
- 
-+/* Implement TARGET_USE_BY_PIECES_INFRASTRUCTURE_P.  */
-+
-+static bool
-+s390_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size,
-+				     unsigned int align ATTRIBUTE_UNUSED,
-+				     enum by_pieces_operation op ATTRIBUTE_UNUSED,
-+				     bool speed_p ATTRIBUTE_UNUSED)
-+{
-+  return (size == 1 || size == 2
-+	  || size == 4 || (TARGET_ZARCH && size == 8));
-+}
-+
- /* Initialize GCC target structure.  */
- 
- #undef  TARGET_ASM_ALIGNED_HI_OP
-@@ -12248,6 +12260,10 @@
- #undef TARGET_SET_UP_BY_PROLOGUE
- #define TARGET_SET_UP_BY_PROLOGUE s300_set_up_by_prologue
- 
-+#undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
-+#define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
-+  s390_use_by_pieces_infrastructure_p
-+
- struct gcc_target targetm = TARGET_INITIALIZER;
- 
- #include "gt-s390.h"
---- a/src/gcc/config/s390/s390.h
-+++ b/src/gcc/config/s390/s390.h
-@@ -752,24 +752,6 @@
- #define MOVE_MAX_PIECES (TARGET_ZARCH ? 8 : 4)
- #define MAX_MOVE_MAX 16
- 
--/* Determine whether to use move_by_pieces or block move insn.  */
--#define MOVE_BY_PIECES_P(SIZE, ALIGN)		\
--  ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4	\
--    || (TARGET_ZARCH && (SIZE) == 8) )
--
--/* Determine whether to use clear_by_pieces or block clear insn.  */
--#define CLEAR_BY_PIECES_P(SIZE, ALIGN)		\
--  ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4	\
--    || (TARGET_ZARCH && (SIZE) == 8) )
--
--/* This macro is used to determine whether store_by_pieces should be
--   called to "memcpy" storage when the source is a constant string.  */
--#define STORE_BY_PIECES_P(SIZE, ALIGN) MOVE_BY_PIECES_P (SIZE, ALIGN)
--
--/* Likewise to decide whether to "memset" storage with byte values
--   other than zero.  */
--#define SET_BY_PIECES_P(SIZE, ALIGN) STORE_BY_PIECES_P (SIZE, ALIGN)
--
- /* Don't perform CSE on function addresses.  */
- #define NO_FUNCTION_CSE
- 
---- a/src/gcc/config/i386/i386.c
-+++ b/src/gcc/config/i386/i386.c
-@@ -25796,6 +25796,9 @@
-   rtx compare_set = NULL_RTX, test_if, cond;
-   rtx alu_set = NULL_RTX, addr = NULL_RTX;
- 
-+  if (!any_condjump_p (condjmp))
-+    return false;
-+
-   if (get_attr_type (condgen) != TYPE_TEST
-       && get_attr_type (condgen) != TYPE_ICMP
-       && get_attr_type (condgen) != TYPE_INCDEC
---- a/src/gcc/config/sh/sh.c
-+++ b/src/gcc/config/sh/sh.c
-@@ -317,6 +317,10 @@
- static bool sh_legitimate_constant_p (enum machine_mode, rtx);
- static int mov_insn_size (enum machine_mode, bool);
- static int mov_insn_alignment_mask (enum machine_mode, bool);
-+static bool sh_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT,
-+					       unsigned int,
-+					       enum by_pieces_operation,
-+					       bool);
- static bool sequence_insn_p (rtx);
- static void sh_canonicalize_comparison (int *, rtx *, rtx *, bool);
- static void sh_canonicalize_comparison (enum rtx_code&, rtx&, rtx&,
-@@ -601,6 +605,10 @@
- #undef TARGET_FIXED_CONDITION_CODE_REGS
- #define TARGET_FIXED_CONDITION_CODE_REGS sh_fixed_condition_code_regs
- 
-+#undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
-+#define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
-+  sh_use_by_pieces_infrastructure_p
-+
- /* Machine-specific symbol_ref flags.  */
- #define SYMBOL_FLAG_FUNCVEC_FUNCTION	(SYMBOL_FLAG_MACH_DEP << 0)
- 
-@@ -13533,4 +13541,27 @@
-   return NULL_RTX;
- }
- 
-+/* Implement TARGET_USE_BY_PIECES_INFRASTRUCTURE_P.  */
-+
-+static bool
-+sh_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size,
-+				   unsigned int align,
-+				   enum by_pieces_operation op,
-+				   bool speed_p)
-+{
-+  switch (op)
-+    {
-+      case MOVE_BY_PIECES:
-+	return move_by_pieces_ninsns (size, align, MOVE_MAX_PIECES + 1)
-+	  < (!speed_p ? 2 : (align >= 32) ? 16 : 2);
-+      case STORE_BY_PIECES:
-+      case SET_BY_PIECES:
-+	return move_by_pieces_ninsns (size, align, STORE_MAX_PIECES + 1)
-+	  < (!speed_p ? 2 : (align >= 32) ? 16 : 2);
-+      default:
-+	return default_use_by_pieces_infrastructure_p (size, align,
-+						       op, speed_p);
-+    }
-+}
-+
- #include "gt-sh.h"
---- a/src/gcc/config/sh/sh.h
-+++ b/src/gcc/config/sh/sh.h
-@@ -1584,16 +1584,6 @@
- #define USE_STORE_PRE_DECREMENT(mode)    ((mode == SImode || mode == DImode) \
- 					  ? 0 : TARGET_SH1)
- 
--#define MOVE_BY_PIECES_P(SIZE, ALIGN) \
--  (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
--   < (optimize_size ? 2 : ((ALIGN >= 32) ? 16 : 2)))
--
--#define STORE_BY_PIECES_P(SIZE, ALIGN) \
--  (move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \
--   < (optimize_size ? 2 : ((ALIGN >= 32) ? 16 : 2)))
--
--#define SET_BY_PIECES_P(SIZE, ALIGN) STORE_BY_PIECES_P(SIZE, ALIGN)
--
- /* Macros to check register numbers against specific register classes.  */
- 
- /* These assume that REGNO is a hard or pseudo reg number.
---- a/src/gcc/config/host-linux.c
-+++ b/src/gcc/config/host-linux.c
-@@ -86,6 +86,8 @@
- # define TRY_EMPTY_VM_SPACE	0x60000000
- #elif defined(__mc68000__)
- # define TRY_EMPTY_VM_SPACE	0x40000000
-+#elif defined(__aarch64__) && defined(__ILP32__)
-+# define TRY_EMPTY_VM_SPACE	0x60000000
- #elif defined(__aarch64__)
- # define TRY_EMPTY_VM_SPACE	0x1000000000
- #elif defined(__ARM_EABI__)
---- a/src/gcc/config/cris/cris.h
-+++ b/src/gcc/config/cris/cris.h
-@@ -80,15 +80,7 @@
- /* Which CPU version this is.  The parsed and adjusted cris_cpu_str.  */
- extern int cris_cpu_version;
- 
--/* Changing the order used to be necessary to put the fourth __make_dp
--   argument (a DImode parameter) in registers, to fit with the libfunc
--   parameter passing scheme used for intrinsic functions.  FIXME: Check
--   performance.  */
--#ifdef IN_LIBGCC2
--#define __make_dp(a,b,c,d) __cris_make_dp(d,a,b,c)
--#endif
- 
--
- /* Node: Driver */
- 
- /* Also provide canonical vN definitions when user specifies an alias.  */
---- a/src/gcc/config/aarch64/geniterators.sh
-+++ b/src/gcc/config/aarch64/geniterators.sh
-@@ -0,0 +1,45 @@
-+#!/bin/sh
-+#
-+# Copyright (C) 2014 Free Software Foundation, Inc.
-+# Contributed by ARM Ltd.
-+#
-+# This file is part of GCC.
-+#
-+# GCC is free software; you can redistribute it and/or modify
-+# it under the terms of the GNU General Public License as published by
-+# the Free Software Foundation; either version 3, or (at your option)
-+# any later version.
-+#
-+# GCC is distributed in the hope that it will be useful,
-+# but WITHOUT ANY WARRANTY; without even the implied warranty of
-+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+# GNU General Public License for more details.
-+#
-+# You should have received a copy of the GNU General Public License
-+# along with GCC; see the file COPYING3.  If not see
-+# <http://www.gnu.org/licenses/>.
-+
-+# Generate aarch64-builtin-iterators.h, a file containing a series of
-+# BUILTIN_<ITERATOR> macros, which expand to VAR<N> Macros covering the
-+# same set of modes as the iterator in iterators.md
-+
-+echo "/* -*- buffer-read-only: t -*- */"
-+echo "/* Generated automatically by geniterators.sh from iterators.md.  */"
-+echo "#ifndef GCC_AARCH64_ITERATORS_H"
-+echo "#define GCC_AARCH64_ITERATORS_H"
-+
-+# Strip newlines, create records marked ITERATOR, and strip junk (anything
-+# which does not have a matching brace because it contains characters we
-+# don't want to or can't handle (e.g P, PTR iterators change depending on
-+# Pmode and ptr_mode).
-+cat $1 | tr "\n" " " \
-+       | sed 's/(define_mode_iterator \([A-Za-z0-9_]*\) \([]\[A-Z0-9 \t]*\)/\n#define BUILTIN_\1(T, N, MAP) \\ \2\n/g' \
-+       | grep '#define [A-Z0-9_(), \\]* \[[A-Z0-9[:space:]]*]' \
-+       | sed 's/\t//g' \
-+       | sed 's/  \+/ /g' \
-+       | sed 's/ \[\([A-Z0-9 ]*\)]/\n\L\1/' \
-+       | awk ' BEGIN { FS = " " ; OFS = ", "} \
-+	       /#/ { print } \
-+               ! /#/ { $1 = $1 ; printf "  VAR%d (T, N, MAP, %s)\n", NF, $0 }'
-+
-+echo "#endif /* GCC_AARCH64_ITERATORS_H  */"
---- a/src/gcc/config/aarch64/aarch64-simd.md
-+++ b/src/gcc/config/aarch64/aarch64-simd.md
-@@ -19,8 +19,8 @@
- ;; <http://www.gnu.org/licenses/>.
- 
- (define_expand "mov<mode>"
--  [(set (match_operand:VALL 0 "aarch64_simd_nonimmediate_operand" "")
--	(match_operand:VALL 1 "aarch64_simd_general_operand" ""))]
-+  [(set (match_operand:VALL 0 "nonimmediate_operand" "")
-+	(match_operand:VALL 1 "general_operand" ""))]
-   "TARGET_SIMD"
-   "
-     if (GET_CODE (operands[0]) == MEM)
-@@ -29,8 +29,8 @@
- )
- 
- (define_expand "movmisalign<mode>"
--  [(set (match_operand:VALL 0 "aarch64_simd_nonimmediate_operand" "")
--        (match_operand:VALL 1 "aarch64_simd_general_operand" ""))]
-+  [(set (match_operand:VALL 0 "nonimmediate_operand" "")
-+        (match_operand:VALL 1 "general_operand" ""))]
-   "TARGET_SIMD"
- {
-   /* This pattern is not permitted to fail during expansion: if both arguments
-@@ -91,9 +91,9 @@
- )
- 
- (define_insn "*aarch64_simd_mov<mode>"
--  [(set (match_operand:VD 0 "aarch64_simd_nonimmediate_operand"
-+  [(set (match_operand:VD 0 "nonimmediate_operand"
- 		"=w, m,  w, ?r, ?w, ?r, w")
--	(match_operand:VD 1 "aarch64_simd_general_operand"
-+	(match_operand:VD 1 "general_operand"
- 		"m,  w,  w,  w,  r,  r, Dn"))]
-   "TARGET_SIMD
-    && (register_operand (operands[0], <MODE>mode)
-@@ -119,9 +119,9 @@
- )
- 
- (define_insn "*aarch64_simd_mov<mode>"
--  [(set (match_operand:VQ 0 "aarch64_simd_nonimmediate_operand"
-+  [(set (match_operand:VQ 0 "nonimmediate_operand"
- 		"=w, m,  w, ?r, ?w, ?r, w")
--	(match_operand:VQ 1 "aarch64_simd_general_operand"
-+	(match_operand:VQ 1 "general_operand"
- 		"m,  w,  w,  w,  r,  r, Dn"))]
-   "TARGET_SIMD
-    && (register_operand (operands[0], <MODE>mode)
-@@ -286,6 +286,23 @@
-   [(set_attr "type" "neon_mul_<Vetype><q>")]
- )
- 
-+(define_insn "bswap<mode>"
-+  [(set (match_operand:VDQHSD 0 "register_operand" "=w")
-+        (bswap:VDQHSD (match_operand:VDQHSD 1 "register_operand" "w")))]
-+  "TARGET_SIMD"
-+  "rev<Vrevsuff>\\t%0.<Vbtype>, %1.<Vbtype>"
-+  [(set_attr "type" "neon_rev<q>")]
-+)
-+
-+(define_insn "aarch64_rbit<mode>"
-+  [(set (match_operand:VB 0 "register_operand" "=w")
-+	(unspec:VB [(match_operand:VB 1 "register_operand" "w")]
-+		   UNSPEC_RBIT))]
-+  "TARGET_SIMD"
-+  "rbit\\t%0.<Vbtype>, %1.<Vbtype>"
-+  [(set_attr "type" "neon_rbit")]
-+)
-+
- (define_insn "*aarch64_mul3_elt<mode>"
-  [(set (match_operand:VMUL 0 "register_operand" "=w")
-     (mult:VMUL
-@@ -954,7 +971,7 @@
-    dup\\t%d0, %1.d[0]
-    fmov\\t%d0, %1
-    dup\\t%d0, %1"
--  [(set_attr "type" "neon_dup<q>,fmov,neon_dup<q>")
-+  [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>")
-    (set_attr "simd" "yes,*,yes")
-    (set_attr "fp" "*,yes,*")
-    (set_attr "length" "4")]
-@@ -1046,7 +1063,7 @@
- 	  (match_operand:<VHALF> 1 "register_operand" "w,r")
-           (vec_select:<VHALF>
-                 (match_dup 0)
--                (match_operand:VQ 2 "vect_par_cnst_hi_half" ""))))]
-+                (match_operand:VQ 2 "vect_par_cnst_lo_half" ""))))]
-   "TARGET_SIMD && BYTES_BIG_ENDIAN"
-   "@
-    ins\\t%0.d[1], %1.d[0]
-@@ -1059,7 +1076,7 @@
-   (match_operand:<VHALF> 1 "register_operand" "")]
-  "TARGET_SIMD"
- {
--  rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, BYTES_BIG_ENDIAN);
-+  rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, false);
-   if (BYTES_BIG_ENDIAN)
-     emit_insn (gen_aarch64_simd_move_hi_quad_be_<mode> (operands[0],
- 		    operands[1], p));
-@@ -1099,7 +1116,7 @@
- ;; For quads.
- 
- (define_insn "vec_pack_trunc_<mode>"
-- [(set (match_operand:<VNARROWQ2> 0 "register_operand" "+&w")
-+ [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=&w")
-        (vec_concat:<VNARROWQ2>
- 	 (truncate:<VNARROWQ> (match_operand:VQN 1 "register_operand" "w"))
- 	 (truncate:<VNARROWQ> (match_operand:VQN 2 "register_operand" "w"))))]
-@@ -1541,7 +1558,7 @@
- )
- 
- ;; Vector versions of the floating-point frint patterns.
--;; Expands to btrunc, ceil, floor, nearbyint, rint, round.
-+;; Expands to btrunc, ceil, floor, nearbyint, rint, round, frintn.
- (define_insn "<frint_pattern><mode>2"
-   [(set (match_operand:VDQF 0 "register_operand" "=w")
- 	(unspec:VDQF [(match_operand:VDQF 1 "register_operand" "w")]
-@@ -1853,15 +1870,15 @@
- ;;     bif op0, op1, mask
- 
- (define_insn "aarch64_simd_bsl<mode>_internal"
--  [(set (match_operand:VALLDIF 0 "register_operand"		"=w,w,w")
--	(ior:VALLDIF
--	   (and:VALLDIF
--	     (match_operand:<V_cmp_result> 1 "register_operand"	" 0,w,w")
--	     (match_operand:VALLDIF 2 "register_operand"	" w,w,0"))
--	   (and:VALLDIF
-+  [(set (match_operand:VSDQ_I_DI 0 "register_operand"		"=w,w,w")
-+	(ior:VSDQ_I_DI
-+	   (and:VSDQ_I_DI
- 	     (not:<V_cmp_result>
--		(match_dup:<V_cmp_result> 1))
--	     (match_operand:VALLDIF 3 "register_operand"	" w,0,w"))
-+	       (match_operand:<V_cmp_result> 1 "register_operand"	" 0,w,w"))
-+	     (match_operand:VSDQ_I_DI 3 "register_operand"	" w,0,w"))
-+	   (and:VSDQ_I_DI
-+	     (match_dup:<V_cmp_result> 1)
-+	     (match_operand:VSDQ_I_DI 2 "register_operand"	" w,w,0"))
- 	))]
-   "TARGET_SIMD"
-   "@
-@@ -1879,9 +1896,21 @@
-  "TARGET_SIMD"
- {
-   /* We can't alias operands together if they have different modes.  */
-+  rtx tmp = operands[0];
-+  if (FLOAT_MODE_P (<MODE>mode))
-+    {
-+      operands[2] = gen_lowpart (<V_cmp_result>mode, operands[2]);
-+      operands[3] = gen_lowpart (<V_cmp_result>mode, operands[3]);
-+      tmp = gen_reg_rtx (<V_cmp_result>mode);
-+    }
-   operands[1] = gen_lowpart (<V_cmp_result>mode, operands[1]);
--  emit_insn (gen_aarch64_simd_bsl<mode>_internal (operands[0], operands[1],
--						  operands[2], operands[3]));
-+  emit_insn (gen_aarch64_simd_bsl<v_cmp_result>_internal (tmp,
-+							  operands[1],
-+							  operands[2],
-+							  operands[3]));
-+  if (tmp != operands[0])
-+    emit_move_insn (operands[0], gen_lowpart (<MODE>mode, tmp));
-+
-   DONE;
- })
- 
-@@ -1895,58 +1924,94 @@
- 	  (match_operand:VDQ 2 "nonmemory_operand")))]
-   "TARGET_SIMD"
- {
--  int inverse = 0, has_zero_imm_form = 0;
-   rtx op1 = operands[1];
-   rtx op2 = operands[2];
-   rtx mask = gen_reg_rtx (<MODE>mode);
-+  enum rtx_code code = GET_CODE (operands[3]);
- 
--  switch (GET_CODE (operands[3]))
-+  /* Switching OP1 and OP2 is necessary for NE (to output a cmeq insn),
-+     and desirable for other comparisons if it results in FOO ? -1 : 0
-+     (this allows direct use of the comparison result without a bsl).  */
-+  if (code == NE
-+      || (code != EQ
-+	  && op1 == CONST0_RTX (<V_cmp_result>mode)
-+	  && op2 == CONSTM1_RTX (<V_cmp_result>mode)))
-     {
-+      op1 = operands[2];
-+      op2 = operands[1];
-+      switch (code)
-+        {
-+        case LE: code = GT; break;
-+        case LT: code = GE; break;
-+        case GE: code = LT; break;
-+        case GT: code = LE; break;
-+        /* No case EQ.  */
-+        case NE: code = EQ; break;
-+        case LTU: code = GEU; break;
-+        case LEU: code = GTU; break;
-+        case GTU: code = LEU; break;
-+        case GEU: code = LTU; break;
-+        default: gcc_unreachable ();
-+        }
-+    }
-+
-+  /* Make sure we can handle the last operand.  */
-+  switch (code)
-+    {
-+    case NE:
-+      /* Normalized to EQ above.  */
-+      gcc_unreachable ();
-+
-     case LE:
-     case LT:
--    case NE:
--      inverse = 1;
--      /* Fall through.  */
-     case GE:
-     case GT:
-     case EQ:
--      has_zero_imm_form = 1;
--      break;
--    case LEU:
--    case LTU:
--      inverse = 1;
--      break;
-+      /* These instructions have a form taking an immediate zero.  */
-+      if (operands[5] == CONST0_RTX (<MODE>mode))
-+        break;
-+      /* Fall through, as may need to load into register.  */
-     default:
-+      if (!REG_P (operands[5]))
-+        operands[5] = force_reg (<MODE>mode, operands[5]);
-       break;
-     }
- 
--  if (!REG_P (operands[5])
--      && (operands[5] != CONST0_RTX (<MODE>mode) || !has_zero_imm_form))
--    operands[5] = force_reg (<MODE>mode, operands[5]);
--
--  switch (GET_CODE (operands[3]))
-+  switch (code)
-     {
-     case LT:
-+      emit_insn (gen_aarch64_cmlt<mode> (mask, operands[4], operands[5]));
-+      break;
-+
-     case GE:
-       emit_insn (gen_aarch64_cmge<mode> (mask, operands[4], operands[5]));
-       break;
- 
-     case LE:
-+      emit_insn (gen_aarch64_cmle<mode> (mask, operands[4], operands[5]));
-+      break;
-+
-     case GT:
-       emit_insn (gen_aarch64_cmgt<mode> (mask, operands[4], operands[5]));
-       break;
- 
-     case LTU:
-+      emit_insn (gen_aarch64_cmgtu<mode> (mask, operands[5], operands[4]));
-+      break;
-+
-     case GEU:
-       emit_insn (gen_aarch64_cmgeu<mode> (mask, operands[4], operands[5]));
-       break;
- 
-     case LEU:
-+      emit_insn (gen_aarch64_cmgeu<mode> (mask, operands[5], operands[4]));
-+      break;
-+
-     case GTU:
-       emit_insn (gen_aarch64_cmgtu<mode> (mask, operands[4], operands[5]));
-       break;
- 
--    case NE:
-+    /* NE has been normalized to EQ above.  */
-     case EQ:
-       emit_insn (gen_aarch64_cmeq<mode> (mask, operands[4], operands[5]));
-       break;
-@@ -1955,12 +2020,6 @@
-       gcc_unreachable ();
-     }
- 
--  if (inverse)
--    {
--      op1 = operands[2];
--      op2 = operands[1];
--    }
--
-     /* If we have (a = (b CMP c) ? -1 : 0);
-        Then we can simply move the generated mask.  */
- 
-@@ -2348,6 +2407,15 @@
-   DONE;
- })
- 
-+(define_expand "aarch64_reinterpretdf<mode>"
-+  [(match_operand:DF 0 "register_operand" "")
-+   (match_operand:VD_RE 1 "register_operand" "")]
-+  "TARGET_SIMD"
-+{
-+  aarch64_simd_reinterpret (operands[0], operands[1]);
-+  DONE;
-+})
-+
- (define_expand "aarch64_reinterpretv16qi<mode>"
-   [(match_operand:V16QI 0 "register_operand" "")
-    (match_operand:VQ 1 "register_operand" "")]
-@@ -2734,9 +2802,9 @@
- ;; <su>q<absneg>
- 
- (define_insn "aarch64_s<optab><mode>"
--  [(set (match_operand:VSDQ_I_BHSI 0 "register_operand" "=w")
--	(UNQOPS:VSDQ_I_BHSI
--	  (match_operand:VSDQ_I_BHSI 1 "register_operand" "w")))]
-+  [(set (match_operand:VSDQ_I 0 "register_operand" "=w")
-+	(UNQOPS:VSDQ_I
-+	  (match_operand:VSDQ_I 1 "register_operand" "w")))]
-   "TARGET_SIMD"
-   "s<optab>\\t%<v>0<Vmtype>, %<v>1<Vmtype>"
-   [(set_attr "type" "neon_<optab><q>")]
-@@ -3788,26 +3856,46 @@
- 	  )))
-      (clobber (reg:CC CC_REGNUM))]
-   "TARGET_SIMD"
--  "@
--  cm<n_optab>\t%d0, %d<cmp_1>, %d<cmp_2>
--  cm<optab>\t%d0, %d1, #0
--  #"
--  "reload_completed
--   /* We need to prevent the split from
--      happening in the 'w' constraint cases.  */
--   && GP_REGNUM_P (REGNO (operands[0]))
--   && GP_REGNUM_P (REGNO (operands[1]))"
--  [(const_int 0)]
-+  "#"
-+  "reload_completed"
-+  [(set (match_operand:DI 0 "register_operand")
-+	(neg:DI
-+	  (COMPARISONS:DI
-+	    (match_operand:DI 1 "register_operand")
-+	    (match_operand:DI 2 "aarch64_simd_reg_or_zero")
-+	  )))]
-   {
--    enum machine_mode mode = SELECT_CC_MODE (<CMP>, operands[1], operands[2]);
--    rtx cc_reg = aarch64_gen_compare_reg (<CMP>, operands[1], operands[2]);
--    rtx comparison = gen_rtx_<CMP> (mode, operands[1], operands[2]);
--    emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
--    DONE;
-+    /* If we are in the general purpose register file,
-+       we split to a sequence of comparison and store.  */
-+    if (GP_REGNUM_P (REGNO (operands[0]))
-+	&& GP_REGNUM_P (REGNO (operands[1])))
-+      {
-+	enum machine_mode mode = SELECT_CC_MODE (<CMP>, operands[1], operands[2]);
-+	rtx cc_reg = aarch64_gen_compare_reg (<CMP>, operands[1], operands[2]);
-+	rtx comparison = gen_rtx_<CMP> (mode, operands[1], operands[2]);
-+	emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
-+	DONE;
-+      }
-+    /* Otherwise, we expand to a similar pattern which does not
-+       clobber CC_REGNUM.  */
-   }
-   [(set_attr "type" "neon_compare, neon_compare_zero, multiple")]
- )
- 
-+(define_insn "*aarch64_cm<optab>di"
-+  [(set (match_operand:DI 0 "register_operand" "=w,w")
-+	(neg:DI
-+	  (COMPARISONS:DI
-+	    (match_operand:DI 1 "register_operand" "w,w")
-+	    (match_operand:DI 2 "aarch64_simd_reg_or_zero" "w,ZDz")
-+	  )))]
-+  "TARGET_SIMD && reload_completed"
-+  "@
-+  cm<n_optab>\t%d0, %d<cmp_1>, %d<cmp_2>
-+  cm<optab>\t%d0, %d1, #0"
-+  [(set_attr "type" "neon_compare, neon_compare_zero")]
-+)
-+
- ;; cm(hs|hi)
- 
- (define_insn "aarch64_cm<optab><mode>"
-@@ -3831,35 +3919,62 @@
- 	  )))
-     (clobber (reg:CC CC_REGNUM))]
-   "TARGET_SIMD"
--  "@
--  cm<n_optab>\t%d0, %d<cmp_1>, %d<cmp_2>
--  #"
--  "reload_completed
--   /* We need to prevent the split from
--      happening in the 'w' constraint cases.  */
--   && GP_REGNUM_P (REGNO (operands[0]))
--   && GP_REGNUM_P (REGNO (operands[1]))"
--  [(const_int 0)]
-+  "#"
-+  "reload_completed"
-+  [(set (match_operand:DI 0 "register_operand")
-+	(neg:DI
-+	  (UCOMPARISONS:DI
-+	    (match_operand:DI 1 "register_operand")
-+	    (match_operand:DI 2 "aarch64_simd_reg_or_zero")
-+	  )))]
-   {
--    enum machine_mode mode = CCmode;
--    rtx cc_reg = aarch64_gen_compare_reg (<CMP>, operands[1], operands[2]);
--    rtx comparison = gen_rtx_<CMP> (mode, operands[1], operands[2]);
--    emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
--    DONE;
-+    /* If we are in the general purpose register file,
-+       we split to a sequence of comparison and store.  */
-+    if (GP_REGNUM_P (REGNO (operands[0]))
-+	&& GP_REGNUM_P (REGNO (operands[1])))
-+      {
-+	enum machine_mode mode = CCmode;
-+	rtx cc_reg = aarch64_gen_compare_reg (<CMP>, operands[1], operands[2]);
-+	rtx comparison = gen_rtx_<CMP> (mode, operands[1], operands[2]);
-+	emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
-+	DONE;
-+      }
-+    /* Otherwise, we expand to a similar pattern which does not
-+       clobber CC_REGNUM.  */
-   }
--  [(set_attr "type" "neon_compare, neon_compare_zero")]
-+  [(set_attr "type" "neon_compare,multiple")]
- )
- 
-+(define_insn "*aarch64_cm<optab>di"
-+  [(set (match_operand:DI 0 "register_operand" "=w")
-+	(neg:DI
-+	  (UCOMPARISONS:DI
-+	    (match_operand:DI 1 "register_operand" "w")
-+	    (match_operand:DI 2 "aarch64_simd_reg_or_zero" "w")
-+	  )))]
-+  "TARGET_SIMD && reload_completed"
-+  "cm<n_optab>\t%d0, %d<cmp_1>, %d<cmp_2>"
-+  [(set_attr "type" "neon_compare")]
-+)
-+
- ;; cmtst
- 
-+;; Although neg (ne (and x y) 0) is the natural way of expressing a cmtst,
-+;; we don't have any insns using ne, and aarch64_vcond_internal outputs
-+;; not (neg (eq (and x y) 0))
-+;; which is rewritten by simplify_rtx as
-+;; plus (eq (and x y) 0) -1.
-+
- (define_insn "aarch64_cmtst<mode>"
-   [(set (match_operand:<V_cmp_result> 0 "register_operand" "=w")
--	(neg:<V_cmp_result>
--	  (ne:<V_cmp_result>
-+	(plus:<V_cmp_result>
-+	  (eq:<V_cmp_result>
- 	    (and:VDQ
- 	      (match_operand:VDQ 1 "register_operand" "w")
- 	      (match_operand:VDQ 2 "register_operand" "w"))
--	    (vec_duplicate:<V_cmp_result> (const_int 0)))))]
-+	    (match_operand:VDQ 3 "aarch64_simd_imm_zero"))
-+	  (match_operand:<V_cmp_result> 4 "aarch64_simd_imm_minus_one")))
-+  ]
-   "TARGET_SIMD"
-   "cmtst\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"
-   [(set_attr "type" "neon_tst<q>")]
-@@ -3875,23 +3990,44 @@
- 	    (const_int 0))))
-     (clobber (reg:CC CC_REGNUM))]
-   "TARGET_SIMD"
--  "@
--  cmtst\t%d0, %d1, %d2
--  #"
--  "reload_completed
--   /* We need to prevent the split from
--      happening in the 'w' constraint cases.  */
--   && GP_REGNUM_P (REGNO (operands[0]))
--   && GP_REGNUM_P (REGNO (operands[1]))"
--  [(const_int 0)]
-+  "#"
-+  "reload_completed"
-+  [(set (match_operand:DI 0 "register_operand")
-+	(neg:DI
-+	  (ne:DI
-+	    (and:DI
-+	      (match_operand:DI 1 "register_operand")
-+	      (match_operand:DI 2 "register_operand"))
-+	    (const_int 0))))]
-   {
--    rtx and_tree = gen_rtx_AND (DImode, operands[1], operands[2]);
--    enum machine_mode mode = SELECT_CC_MODE (NE, and_tree, const0_rtx);
--    rtx cc_reg = aarch64_gen_compare_reg (NE, and_tree, const0_rtx);
--    rtx comparison = gen_rtx_NE (mode, and_tree, const0_rtx);
--    emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
--    DONE;
-+    /* If we are in the general purpose register file,
-+       we split to a sequence of comparison and store.  */
-+    if (GP_REGNUM_P (REGNO (operands[0]))
-+	&& GP_REGNUM_P (REGNO (operands[1])))
-+      {
-+	rtx and_tree = gen_rtx_AND (DImode, operands[1], operands[2]);
-+	enum machine_mode mode = SELECT_CC_MODE (NE, and_tree, const0_rtx);
-+	rtx cc_reg = aarch64_gen_compare_reg (NE, and_tree, const0_rtx);
-+	rtx comparison = gen_rtx_NE (mode, and_tree, const0_rtx);
-+	emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
-+	DONE;
-+      }
-+    /* Otherwise, we expand to a similar pattern which does not
-+       clobber CC_REGNUM.  */
-   }
-+  [(set_attr "type" "neon_tst,multiple")]
-+)
-+
-+(define_insn "*aarch64_cmtstdi"
-+  [(set (match_operand:DI 0 "register_operand" "=w")
-+	(neg:DI
-+	  (ne:DI
-+	    (and:DI
-+	      (match_operand:DI 1 "register_operand" "w")
-+	      (match_operand:DI 2 "register_operand" "w"))
-+	    (const_int 0))))]
-+  "TARGET_SIMD"
-+  "cmtst\t%d0, %d1, %d2"
-   [(set_attr "type" "neon_tst")]
- )
- 
-@@ -3972,6 +4108,16 @@
-   [(set_attr "type" "neon_load2_2reg<q>")]
- )
- 
-+(define_insn "aarch64_simd_ld2r<mode>"
-+  [(set (match_operand:OI 0 "register_operand" "=w")
-+       (unspec:OI [(match_operand:<V_TWO_ELEM> 1 "aarch64_simd_struct_operand" "Utv")
-+                   (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) ]
-+                  UNSPEC_LD2_DUP))]
-+  "TARGET_SIMD"
-+  "ld2r\\t{%S0.<Vtype> - %T0.<Vtype>}, %1"
-+  [(set_attr "type" "neon_load2_all_lanes<q>")]
-+)
-+
- (define_insn "vec_store_lanesoi<mode>"
-   [(set (match_operand:OI 0 "aarch64_simd_struct_operand" "=Utv")
- 	(unspec:OI [(match_operand:OI 1 "register_operand" "w")
-@@ -3982,6 +4128,17 @@
-   [(set_attr "type" "neon_store2_2reg<q>")]
- )
- 
-+(define_insn "vec_store_lanesoi_lane<mode>"
-+  [(set (match_operand:<V_TWO_ELEM> 0 "aarch64_simd_struct_operand" "=Utv")
-+	(unspec:<V_TWO_ELEM> [(match_operand:OI 1 "register_operand" "w")
-+                    (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
-+		    (match_operand:SI 2 "immediate_operand" "i")]
-+                   UNSPEC_ST2_LANE))]
-+  "TARGET_SIMD"
-+  "st2\\t{%S1.<Vetype> - %T1.<Vetype>}[%2], %0"
-+  [(set_attr "type" "neon_store3_one_lane<q>")]
-+)
-+
- (define_insn "vec_load_lanesci<mode>"
-   [(set (match_operand:CI 0 "register_operand" "=w")
- 	(unspec:CI [(match_operand:CI 1 "aarch64_simd_struct_operand" "Utv")
-@@ -3992,6 +4149,16 @@
-   [(set_attr "type" "neon_load3_3reg<q>")]
- )
- 
-+(define_insn "aarch64_simd_ld3r<mode>"
-+  [(set (match_operand:CI 0 "register_operand" "=w")
-+       (unspec:CI [(match_operand:<V_THREE_ELEM> 1 "aarch64_simd_struct_operand" "Utv")
-+                   (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) ]
-+                  UNSPEC_LD3_DUP))]
-+  "TARGET_SIMD"
-+  "ld3r\\t{%S0.<Vtype> - %U0.<Vtype>}, %1"
-+  [(set_attr "type" "neon_load3_all_lanes<q>")]
-+)
-+
- (define_insn "vec_store_lanesci<mode>"
-   [(set (match_operand:CI 0 "aarch64_simd_struct_operand" "=Utv")
- 	(unspec:CI [(match_operand:CI 1 "register_operand" "w")
-@@ -4002,6 +4169,17 @@
-   [(set_attr "type" "neon_store3_3reg<q>")]
- )
- 
-+(define_insn "vec_store_lanesci_lane<mode>"
-+  [(set (match_operand:<V_THREE_ELEM> 0 "aarch64_simd_struct_operand" "=Utv")
-+	(unspec:<V_THREE_ELEM> [(match_operand:CI 1 "register_operand" "w")
-+                    (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
-+		    (match_operand:SI 2 "immediate_operand" "i")]
-+                   UNSPEC_ST3_LANE))]
-+  "TARGET_SIMD"
-+  "st3\\t{%S1.<Vetype> - %U1.<Vetype>}[%2], %0"
-+  [(set_attr "type" "neon_store3_one_lane<q>")]
-+)
-+
- (define_insn "vec_load_lanesxi<mode>"
-   [(set (match_operand:XI 0 "register_operand" "=w")
- 	(unspec:XI [(match_operand:XI 1 "aarch64_simd_struct_operand" "Utv")
-@@ -4012,6 +4190,16 @@
-   [(set_attr "type" "neon_load4_4reg<q>")]
- )
- 
-+(define_insn "aarch64_simd_ld4r<mode>"
-+  [(set (match_operand:XI 0 "register_operand" "=w")
-+       (unspec:XI [(match_operand:<V_FOUR_ELEM> 1 "aarch64_simd_struct_operand" "Utv")
-+                   (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) ]
-+                  UNSPEC_LD4_DUP))]
-+  "TARGET_SIMD"
-+  "ld4r\\t{%S0.<Vtype> - %V0.<Vtype>}, %1"
-+  [(set_attr "type" "neon_load4_all_lanes<q>")]
-+)
-+
- (define_insn "vec_store_lanesxi<mode>"
-   [(set (match_operand:XI 0 "aarch64_simd_struct_operand" "=Utv")
- 	(unspec:XI [(match_operand:XI 1 "register_operand" "w")
-@@ -4022,6 +4210,17 @@
-   [(set_attr "type" "neon_store4_4reg<q>")]
- )
- 
-+(define_insn "vec_store_lanesxi_lane<mode>"
-+  [(set (match_operand:<V_FOUR_ELEM> 0 "aarch64_simd_struct_operand" "=Utv")
-+	(unspec:<V_FOUR_ELEM> [(match_operand:XI 1 "register_operand" "w")
-+                    (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
-+		    (match_operand:SI 2 "immediate_operand" "i")]
-+                   UNSPEC_ST4_LANE))]
-+  "TARGET_SIMD"
-+  "st4\\t{%S1.<Vetype> - %V1.<Vetype>}[%2], %0"
-+  [(set_attr "type" "neon_store4_one_lane<q>")]
-+)
-+
- ;; Reload patterns for AdvSIMD register list operands.
- 
- (define_expand "mov<mode>"
-@@ -4141,6 +4340,45 @@
-   aarch64_simd_disambiguate_copy (operands, dest, src, 4);
- })
- 
-+(define_expand "aarch64_ld2r<mode>"
-+  [(match_operand:OI 0 "register_operand" "=w")
-+   (match_operand:DI 1 "register_operand" "w")
-+   (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
-+  "TARGET_SIMD"
-+{
-+  enum machine_mode mode = <V_TWO_ELEM>mode;
-+  rtx mem = gen_rtx_MEM (mode, operands[1]);
-+
-+  emit_insn (gen_aarch64_simd_ld2r<mode> (operands[0], mem));
-+  DONE;
-+})
-+
-+(define_expand "aarch64_ld3r<mode>"
-+  [(match_operand:CI 0 "register_operand" "=w")
-+   (match_operand:DI 1 "register_operand" "w")
-+   (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
-+  "TARGET_SIMD"
-+{
-+  enum machine_mode mode = <V_THREE_ELEM>mode;
-+  rtx mem = gen_rtx_MEM (mode, operands[1]);
-+
-+  emit_insn (gen_aarch64_simd_ld3r<mode> (operands[0], mem));
-+  DONE;
-+})
-+
-+(define_expand "aarch64_ld4r<mode>"
-+  [(match_operand:XI 0 "register_operand" "=w")
-+   (match_operand:DI 1 "register_operand" "w")
-+   (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
-+  "TARGET_SIMD"
-+{
-+  enum machine_mode mode = <V_FOUR_ELEM>mode;
-+  rtx mem = gen_rtx_MEM (mode, operands[1]);
-+
-+  emit_insn (gen_aarch64_simd_ld4r<mode> (operands[0],mem));
-+  DONE;
-+})
-+
- (define_insn "aarch64_ld2<mode>_dreg"
-   [(set (match_operand:OI 0 "register_operand" "=w")
- 	(subreg:OI
-@@ -4375,7 +4613,7 @@
-    (match_operand:VB 1 "register_operand")
-    (match_operand:VB 2 "register_operand")
-    (match_operand:VB 3 "register_operand")]
--  "TARGET_SIMD && !BYTES_BIG_ENDIAN"
-+  "TARGET_SIMD"
- {
-   aarch64_expand_vec_perm (operands[0], operands[1],
- 			   operands[2], operands[3]);
-@@ -4430,6 +4668,44 @@
-   [(set_attr "type" "neon_permute<q>")]
- )
- 
-+;; Note immediate (third) operand is lane index not byte index.
-+(define_insn "aarch64_ext<mode>"
-+  [(set (match_operand:VALL 0 "register_operand" "=w")
-+        (unspec:VALL [(match_operand:VALL 1 "register_operand" "w")
-+                      (match_operand:VALL 2 "register_operand" "w")
-+                      (match_operand:SI 3 "immediate_operand" "i")]
-+                     UNSPEC_EXT))]
-+  "TARGET_SIMD"
-+{
-+  operands[3] = GEN_INT (INTVAL (operands[3])
-+      * GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)));
-+  return "ext\\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>, #%3";
-+}
-+  [(set_attr "type" "neon_ext<q>")]
-+)
-+
-+;; This exists solely to check the arguments to the corresponding __builtin.
-+;; Used where we want an error for out-of-range indices which would otherwise
-+;; be silently wrapped (e.g. the mask to a __builtin_shuffle).
-+(define_expand "aarch64_im_lane_boundsi"
-+  [(match_operand:SI 0 "immediate_operand" "i")
-+   (match_operand:SI 1 "immediate_operand" "i")]
-+  "TARGET_SIMD"
-+{
-+  aarch64_simd_lane_bounds (operands[0], 0, INTVAL (operands[1]));
-+  DONE;
-+}
-+)
-+
-+(define_insn "aarch64_rev<REVERSE:rev_op><mode>"
-+  [(set (match_operand:VALL 0 "register_operand" "=w")
-+	(unspec:VALL [(match_operand:VALL 1 "register_operand" "w")]
-+                    REVERSE))]
-+  "TARGET_SIMD"
-+  "rev<REVERSE:rev_op>\\t%0.<Vtype>, %1.<Vtype>"
-+  [(set_attr "type" "neon_rev<q>")]
-+)
-+
- (define_insn "aarch64_st2<mode>_dreg"
-   [(set (match_operand:TI 0 "aarch64_simd_struct_operand" "=Utv")
- 	(unspec:TI [(match_operand:OI 1 "register_operand" "w")
-@@ -4516,6 +4792,57 @@
-   DONE;
- })
- 
-+(define_expand "aarch64_st2_lane<VQ:mode>"
-+ [(match_operand:DI 0 "register_operand" "r")
-+  (match_operand:OI 1 "register_operand" "w")
-+  (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
-+  (match_operand:SI 2 "immediate_operand")]
-+  "TARGET_SIMD"
-+{
-+  enum machine_mode mode = <V_TWO_ELEM>mode;
-+  rtx mem = gen_rtx_MEM (mode, operands[0]);
-+  operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
-+
-+  emit_insn (gen_vec_store_lanesoi_lane<VQ:mode> (mem,
-+						  operands[1],
-+						  operands[2]));
-+  DONE;
-+})
-+
-+(define_expand "aarch64_st3_lane<VQ:mode>"
-+ [(match_operand:DI 0 "register_operand" "r")
-+  (match_operand:CI 1 "register_operand" "w")
-+  (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
-+  (match_operand:SI 2 "immediate_operand")]
-+  "TARGET_SIMD"
-+{
-+  enum machine_mode mode = <V_THREE_ELEM>mode;
-+  rtx mem = gen_rtx_MEM (mode, operands[0]);
-+  operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
-+
-+  emit_insn (gen_vec_store_lanesci_lane<VQ:mode> (mem,
-+						  operands[1],
-+						  operands[2]));
-+  DONE;
-+})
-+
-+(define_expand "aarch64_st4_lane<VQ:mode>"
-+ [(match_operand:DI 0 "register_operand" "r")
-+  (match_operand:XI 1 "register_operand" "w")
-+  (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
-+  (match_operand:SI 2 "immediate_operand")]
-+  "TARGET_SIMD"
-+{
-+  enum machine_mode mode = <V_FOUR_ELEM>mode;
-+  rtx mem = gen_rtx_MEM (mode, operands[0]);
-+  operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
-+
-+  emit_insn (gen_vec_store_lanesxi_lane<VQ:mode> (mem,
-+						  operands[1],
-+						  operands[2]));
-+  DONE;
-+})
-+
- (define_expand "aarch64_st1<VALL:mode>"
-  [(match_operand:DI 0 "register_operand")
-   (match_operand:VALL 1 "register_operand")]
---- a/src/gcc/config/aarch64/predicates.md
-+++ b/src/gcc/config/aarch64/predicates.md
-@@ -26,6 +26,10 @@
- 			      && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC"))))
- )
- 
-+(define_predicate "aarch64_call_insn_operand"
-+  (ior (match_code "symbol_ref")
-+       (match_operand 0 "register_operand")))
-+
- (define_predicate "aarch64_simd_register"
-   (and (match_code "reg")
-        (ior (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_LO_REGS")
-@@ -119,6 +123,10 @@
-        (match_test "INTVAL (op) != 0
- 		    && (unsigned) exact_log2 (INTVAL (op)) < 64")))
- 
-+(define_predicate "aarch64_mem_pair_offset"
-+  (and (match_code "const_int")
-+       (match_test "aarch64_offset_7bit_signed_scaled_p (mode, INTVAL (op))")))
-+
- (define_predicate "aarch64_mem_pair_operand"
-   (and (match_code "mem")
-        (match_test "aarch64_legitimate_address_p (mode, XEXP (op, 0), PARALLEL,
-@@ -194,6 +202,18 @@
- (define_special_predicate "aarch64_comparison_operator"
-   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,ordered,unlt,unle,unge,ungt"))
- 
-+(define_special_predicate "aarch64_comparison_operation"
-+  (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,ordered,unlt,unle,unge,ungt")
-+{
-+  if (XEXP (op, 1) != const0_rtx)
-+    return false;
-+  rtx op0 = XEXP (op, 0);
-+  if (!REG_P (op0) || REGNO (op0) != CC_REGNUM)
-+    return false;
-+  return aarch64_get_condition_code (op) >= 0;
-+})
-+
-+
- ;; True if the operand is memory reference suitable for a load/store exclusive.
- (define_predicate "aarch64_sync_memory_operand"
-   (and (match_operand 0 "memory_operand")
-@@ -203,62 +223,15 @@
- (define_special_predicate "vect_par_cnst_hi_half"
-   (match_code "parallel")
- {
--  HOST_WIDE_INT count = XVECLEN (op, 0);
--  int nunits = GET_MODE_NUNITS (mode);
--  int i;
--
--  if (count < 1
--      || count != nunits / 2)
--    return false;
-- 
--  if (!VECTOR_MODE_P (mode))
--    return false;
--
--  for (i = 0; i < count; i++)
--   {
--     rtx elt = XVECEXP (op, 0, i);
--     int val;
--
--     if (GET_CODE (elt) != CONST_INT)
--       return false;
--
--     val = INTVAL (elt);
--     if (val != (nunits / 2) + i)
--       return false;
--   }
--  return true;
-+  return aarch64_simd_check_vect_par_cnst_half (op, mode, true);
- })
- 
- (define_special_predicate "vect_par_cnst_lo_half"
-   (match_code "parallel")
- {
--  HOST_WIDE_INT count = XVECLEN (op, 0);
--  int nunits = GET_MODE_NUNITS (mode);
--  int i;
--
--  if (count < 1
--      || count != nunits / 2)
--    return false;
--
--  if (!VECTOR_MODE_P (mode))
--    return false;
--
--  for (i = 0; i < count; i++)
--   {
--     rtx elt = XVECEXP (op, 0, i);
--     int val;
--
--     if (GET_CODE (elt) != CONST_INT)
--       return false;
--
--     val = INTVAL (elt);
--     if (val != i)
--       return false;
--   }
--  return true;
-+  return aarch64_simd_check_vect_par_cnst_half (op, mode, false);
- })
- 
--
- (define_special_predicate "aarch64_simd_lshift_imm"
-   (match_code "const_vector")
- {
-@@ -300,3 +273,9 @@
- {
-   return aarch64_simd_imm_zero_p (op, mode);
- })
-+
-+(define_special_predicate "aarch64_simd_imm_minus_one"
-+  (match_code "const_vector")
-+{
-+  return aarch64_const_vec_all_same_int_p (op, -1);
-+})
---- a/src/gcc/config/aarch64/arm_neon.h
-+++ b/src/gcc/config/aarch64/arm_neon.h
-@@ -2113,29 +2113,26 @@
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vqadd_u8 (uint8x8_t __a, uint8x8_t __b)
- {
--  return (uint8x8_t) __builtin_aarch64_uqaddv8qi ((int8x8_t) __a,
--						  (int8x8_t) __b);
-+  return __builtin_aarch64_uqaddv8qi_uuu (__a, __b);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vqadd_u16 (uint16x4_t __a, uint16x4_t __b)
- {
--  return (uint16x4_t) __builtin_aarch64_uqaddv4hi ((int16x4_t) __a,
--						   (int16x4_t) __b);
-+  return __builtin_aarch64_uqaddv4hi_uuu (__a, __b);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vqadd_u32 (uint32x2_t __a, uint32x2_t __b)
- {
--  return (uint32x2_t) __builtin_aarch64_uqaddv2si ((int32x2_t) __a,
--						   (int32x2_t) __b);
-+  return __builtin_aarch64_uqaddv2si_uuu (__a, __b);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vqadd_u64 (uint64x1_t __a, uint64x1_t __b)
- {
--  return (uint64x1_t) __builtin_aarch64_uqadddi ((int64x1_t) __a,
--						 (int64x1_t) __b);
-+  return (uint64x1_t) __builtin_aarch64_uqadddi_uuu ((uint64_t) __a,
-+						     (uint64_t) __b);
- }
- 
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
-@@ -2165,29 +2162,25 @@
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vqaddq_u8 (uint8x16_t __a, uint8x16_t __b)
- {
--  return (uint8x16_t) __builtin_aarch64_uqaddv16qi ((int8x16_t) __a,
--						    (int8x16_t) __b);
-+  return __builtin_aarch64_uqaddv16qi_uuu (__a, __b);
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vqaddq_u16 (uint16x8_t __a, uint16x8_t __b)
- {
--  return (uint16x8_t) __builtin_aarch64_uqaddv8hi ((int16x8_t) __a,
--						   (int16x8_t) __b);
-+  return __builtin_aarch64_uqaddv8hi_uuu (__a, __b);
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vqaddq_u32 (uint32x4_t __a, uint32x4_t __b)
- {
--  return (uint32x4_t) __builtin_aarch64_uqaddv4si ((int32x4_t) __a,
--						   (int32x4_t) __b);
-+  return __builtin_aarch64_uqaddv4si_uuu (__a, __b);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vqaddq_u64 (uint64x2_t __a, uint64x2_t __b)
- {
--  return (uint64x2_t) __builtin_aarch64_uqaddv2di ((int64x2_t) __a,
--						   (int64x2_t) __b);
-+  return __builtin_aarch64_uqaddv2di_uuu (__a, __b);
- }
- 
- __extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
-@@ -2217,29 +2210,26 @@
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vqsub_u8 (uint8x8_t __a, uint8x8_t __b)
- {
--  return (uint8x8_t) __builtin_aarch64_uqsubv8qi ((int8x8_t) __a,
--						  (int8x8_t) __b);
-+  return __builtin_aarch64_uqsubv8qi_uuu (__a, __b);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vqsub_u16 (uint16x4_t __a, uint16x4_t __b)
- {
--  return (uint16x4_t) __builtin_aarch64_uqsubv4hi ((int16x4_t) __a,
--						   (int16x4_t) __b);
-+  return __builtin_aarch64_uqsubv4hi_uuu (__a, __b);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vqsub_u32 (uint32x2_t __a, uint32x2_t __b)
- {
--  return (uint32x2_t) __builtin_aarch64_uqsubv2si ((int32x2_t) __a,
--						   (int32x2_t) __b);
-+  return __builtin_aarch64_uqsubv2si_uuu (__a, __b);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vqsub_u64 (uint64x1_t __a, uint64x1_t __b)
- {
--  return (uint64x1_t) __builtin_aarch64_uqsubdi ((int64x1_t) __a,
--						 (int64x1_t) __b);
-+  return (uint64x1_t) __builtin_aarch64_uqsubdi_uuu ((uint64_t) __a,
-+						     (uint64_t) __b);
- }
- 
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
-@@ -2269,29 +2259,25 @@
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vqsubq_u8 (uint8x16_t __a, uint8x16_t __b)
- {
--  return (uint8x16_t) __builtin_aarch64_uqsubv16qi ((int8x16_t) __a,
--						    (int8x16_t) __b);
-+  return __builtin_aarch64_uqsubv16qi_uuu (__a, __b);
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vqsubq_u16 (uint16x8_t __a, uint16x8_t __b)
- {
--  return (uint16x8_t) __builtin_aarch64_uqsubv8hi ((int16x8_t) __a,
--						   (int16x8_t) __b);
-+  return __builtin_aarch64_uqsubv8hi_uuu (__a, __b);
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vqsubq_u32 (uint32x4_t __a, uint32x4_t __b)
- {
--  return (uint32x4_t) __builtin_aarch64_uqsubv4si ((int32x4_t) __a,
--						   (int32x4_t) __b);
-+  return __builtin_aarch64_uqsubv4si_uuu (__a, __b);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vqsubq_u64 (uint64x2_t __a, uint64x2_t __b)
- {
--  return (uint64x2_t) __builtin_aarch64_uqsubv2di ((int64x2_t) __a,
--						   (int64x2_t) __b);
-+  return __builtin_aarch64_uqsubv2di_uuu (__a, __b);
- }
- 
- __extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
-@@ -2312,6 +2298,12 @@
-   return (int32x2_t) __builtin_aarch64_sqnegv2si (__a);
- }
- 
-+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
-+vqneg_s64 (int64x1_t __a)
-+{
-+  return __builtin_aarch64_sqnegdi (__a);
-+}
-+
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
- vqnegq_s8 (int8x16_t __a)
- {
-@@ -2348,6 +2340,12 @@
-   return (int32x2_t) __builtin_aarch64_sqabsv2si (__a);
- }
- 
-+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
-+vqabs_s64 (int64x1_t __a)
-+{
-+  return __builtin_aarch64_sqabsdi (__a);
-+}
-+
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
- vqabsq_s8 (int8x16_t __a)
- {
-@@ -2637,1352 +2635,1587 @@
- /* vreinterpret  */
- 
- __extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
-+vreinterpret_p8_f64 (float64x1_t __a)
-+{
-+  return __builtin_aarch64_reinterpretv8qidf_ps (__a);
-+}
-+
-+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
- vreinterpret_p8_s8 (int8x8_t __a)
- {
--  return (poly8x8_t) __builtin_aarch64_reinterpretv8qiv8qi (__a);
-+  return (poly8x8_t) __a;
- }
- 
- __extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
- vreinterpret_p8_s16 (int16x4_t __a)
- {
--  return (poly8x8_t) __builtin_aarch64_reinterpretv8qiv4hi (__a);
-+  return (poly8x8_t) __a;
- }
- 
- __extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
- vreinterpret_p8_s32 (int32x2_t __a)
- {
--  return (poly8x8_t) __builtin_aarch64_reinterpretv8qiv2si (__a);
-+  return (poly8x8_t) __a;
- }
- 
- __extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
- vreinterpret_p8_s64 (int64x1_t __a)
- {
--  return (poly8x8_t) __builtin_aarch64_reinterpretv8qidi (__a);
-+  return (poly8x8_t) __a;
- }
- 
- __extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
- vreinterpret_p8_f32 (float32x2_t __a)
- {
--  return (poly8x8_t) __builtin_aarch64_reinterpretv8qiv2sf (__a);
-+  return (poly8x8_t) __a;
- }
- 
- __extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
- vreinterpret_p8_u8 (uint8x8_t __a)
- {
--  return (poly8x8_t) __builtin_aarch64_reinterpretv8qiv8qi ((int8x8_t) __a);
-+  return (poly8x8_t) __a;
- }
- 
- __extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
- vreinterpret_p8_u16 (uint16x4_t __a)
- {
--  return (poly8x8_t) __builtin_aarch64_reinterpretv8qiv4hi ((int16x4_t) __a);
-+  return (poly8x8_t) __a;
- }
- 
- __extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
- vreinterpret_p8_u32 (uint32x2_t __a)
- {
--  return (poly8x8_t) __builtin_aarch64_reinterpretv8qiv2si ((int32x2_t) __a);
-+  return (poly8x8_t) __a;
- }
- 
- __extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
- vreinterpret_p8_u64 (uint64x1_t __a)
- {
--  return (poly8x8_t) __builtin_aarch64_reinterpretv8qidi ((int64x1_t) __a);
-+  return (poly8x8_t) __a;
- }
- 
- __extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
- vreinterpret_p8_p16 (poly16x4_t __a)
- {
--  return (poly8x8_t) __builtin_aarch64_reinterpretv8qiv4hi ((int16x4_t) __a);
-+  return (poly8x8_t) __a;
- }
- 
- __extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
-+vreinterpretq_p8_f64 (float64x2_t __a)
-+{
-+  return (poly8x16_t) __a;
-+}
-+
-+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
- vreinterpretq_p8_s8 (int8x16_t __a)
- {
--  return (poly8x16_t) __builtin_aarch64_reinterpretv16qiv16qi (__a);
-+  return (poly8x16_t) __a;
- }
- 
- __extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
- vreinterpretq_p8_s16 (int16x8_t __a)
- {
--  return (poly8x16_t) __builtin_aarch64_reinterpretv16qiv8hi (__a);
-+  return (poly8x16_t) __a;
- }
- 
- __extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
- vreinterpretq_p8_s32 (int32x4_t __a)
- {
--  return (poly8x16_t) __builtin_aarch64_reinterpretv16qiv4si (__a);
-+  return (poly8x16_t) __a;
- }
- 
- __extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
- vreinterpretq_p8_s64 (int64x2_t __a)
- {
--  return (poly8x16_t) __builtin_aarch64_reinterpretv16qiv2di (__a);
-+  return (poly8x16_t) __a;
- }
- 
- __extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
- vreinterpretq_p8_f32 (float32x4_t __a)
- {
--  return (poly8x16_t) __builtin_aarch64_reinterpretv16qiv4sf (__a);
-+  return (poly8x16_t) __a;
- }
- 
- __extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
- vreinterpretq_p8_u8 (uint8x16_t __a)
- {
--  return (poly8x16_t) __builtin_aarch64_reinterpretv16qiv16qi ((int8x16_t)
--							       __a);
-+  return (poly8x16_t) __a;
- }
- 
- __extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
- vreinterpretq_p8_u16 (uint16x8_t __a)
- {
--  return (poly8x16_t) __builtin_aarch64_reinterpretv16qiv8hi ((int16x8_t)
--							      __a);
-+  return (poly8x16_t) __a;
- }
- 
- __extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
- vreinterpretq_p8_u32 (uint32x4_t __a)
- {
--  return (poly8x16_t) __builtin_aarch64_reinterpretv16qiv4si ((int32x4_t)
--							      __a);
-+  return (poly8x16_t) __a;
- }
- 
- __extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
- vreinterpretq_p8_u64 (uint64x2_t __a)
- {
--  return (poly8x16_t) __builtin_aarch64_reinterpretv16qiv2di ((int64x2_t)
--							      __a);
-+  return (poly8x16_t) __a;
- }
- 
- __extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
- vreinterpretq_p8_p16 (poly16x8_t __a)
- {
--  return (poly8x16_t) __builtin_aarch64_reinterpretv16qiv8hi ((int16x8_t)
--							      __a);
-+  return (poly8x16_t) __a;
- }
- 
- __extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
-+vreinterpret_p16_f64 (float64x1_t __a)
-+{
-+  return __builtin_aarch64_reinterpretv4hidf_ps (__a);
-+}
-+
-+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
- vreinterpret_p16_s8 (int8x8_t __a)
- {
--  return (poly16x4_t) __builtin_aarch64_reinterpretv4hiv8qi (__a);
-+  return (poly16x4_t) __a;
- }
- 
- __extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
- vreinterpret_p16_s16 (int16x4_t __a)
- {
--  return (poly16x4_t) __builtin_aarch64_reinterpretv4hiv4hi (__a);
-+  return (poly16x4_t) __a;
- }
- 
- __extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
- vreinterpret_p16_s32 (int32x2_t __a)
- {
--  return (poly16x4_t) __builtin_aarch64_reinterpretv4hiv2si (__a);
-+  return (poly16x4_t) __a;
- }
- 
- __extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
- vreinterpret_p16_s64 (int64x1_t __a)
- {
--  return (poly16x4_t) __builtin_aarch64_reinterpretv4hidi (__a);
-+  return (poly16x4_t) __a;
- }
- 
- __extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
- vreinterpret_p16_f32 (float32x2_t __a)
- {
--  return (poly16x4_t) __builtin_aarch64_reinterpretv4hiv2sf (__a);
-+  return (poly16x4_t) __a;
- }
- 
- __extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
- vreinterpret_p16_u8 (uint8x8_t __a)
- {
--  return (poly16x4_t) __builtin_aarch64_reinterpretv4hiv8qi ((int8x8_t) __a);
-+  return (poly16x4_t) __a;
- }
- 
- __extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
- vreinterpret_p16_u16 (uint16x4_t __a)
- {
--  return (poly16x4_t) __builtin_aarch64_reinterpretv4hiv4hi ((int16x4_t) __a);
-+  return (poly16x4_t) __a;
- }
- 
- __extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
- vreinterpret_p16_u32 (uint32x2_t __a)
- {
--  return (poly16x4_t) __builtin_aarch64_reinterpretv4hiv2si ((int32x2_t) __a);
-+  return (poly16x4_t) __a;
- }
- 
- __extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
- vreinterpret_p16_u64 (uint64x1_t __a)
- {
--  return (poly16x4_t) __builtin_aarch64_reinterpretv4hidi ((int64x1_t) __a);
-+  return (poly16x4_t) __a;
- }
- 
- __extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
- vreinterpret_p16_p8 (poly8x8_t __a)
- {
--  return (poly16x4_t) __builtin_aarch64_reinterpretv4hiv8qi ((int8x8_t) __a);
-+  return (poly16x4_t) __a;
- }
- 
- __extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
-+vreinterpretq_p16_f64 (float64x2_t __a)
-+{
-+  return (poly16x8_t) __a;
-+}
-+
-+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
- vreinterpretq_p16_s8 (int8x16_t __a)
- {
--  return (poly16x8_t) __builtin_aarch64_reinterpretv8hiv16qi (__a);
-+  return (poly16x8_t) __a;
- }
- 
- __extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
- vreinterpretq_p16_s16 (int16x8_t __a)
- {
--  return (poly16x8_t) __builtin_aarch64_reinterpretv8hiv8hi (__a);
-+  return (poly16x8_t) __a;
- }
- 
- __extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
- vreinterpretq_p16_s32 (int32x4_t __a)
- {
--  return (poly16x8_t) __builtin_aarch64_reinterpretv8hiv4si (__a);
-+  return (poly16x8_t) __a;
- }
- 
- __extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
- vreinterpretq_p16_s64 (int64x2_t __a)
- {
--  return (poly16x8_t) __builtin_aarch64_reinterpretv8hiv2di (__a);
-+  return (poly16x8_t) __a;
- }
- 
- __extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
- vreinterpretq_p16_f32 (float32x4_t __a)
- {
--  return (poly16x8_t) __builtin_aarch64_reinterpretv8hiv4sf (__a);
-+  return (poly16x8_t) __a;
- }
- 
- __extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
- vreinterpretq_p16_u8 (uint8x16_t __a)
- {
--  return (poly16x8_t) __builtin_aarch64_reinterpretv8hiv16qi ((int8x16_t)
--							      __a);
-+  return (poly16x8_t) __a;
- }
- 
- __extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
- vreinterpretq_p16_u16 (uint16x8_t __a)
- {
--  return (poly16x8_t) __builtin_aarch64_reinterpretv8hiv8hi ((int16x8_t) __a);
-+  return (poly16x8_t) __a;
- }
- 
- __extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
- vreinterpretq_p16_u32 (uint32x4_t __a)
- {
--  return (poly16x8_t) __builtin_aarch64_reinterpretv8hiv4si ((int32x4_t) __a);
-+  return (poly16x8_t) __a;
- }
- 
- __extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
- vreinterpretq_p16_u64 (uint64x2_t __a)
- {
--  return (poly16x8_t) __builtin_aarch64_reinterpretv8hiv2di ((int64x2_t) __a);
-+  return (poly16x8_t) __a;
- }
- 
- __extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
- vreinterpretq_p16_p8 (poly8x16_t __a)
- {
--  return (poly16x8_t) __builtin_aarch64_reinterpretv8hiv16qi ((int8x16_t)
--							      __a);
-+  return (poly16x8_t) __a;
- }
- 
- __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
-+vreinterpret_f32_f64 (float64x1_t __a)
-+{
-+  return __builtin_aarch64_reinterpretv2sfdf (__a);
-+}
-+
-+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
- vreinterpret_f32_s8 (int8x8_t __a)
- {
--  return (float32x2_t) __builtin_aarch64_reinterpretv2sfv8qi (__a);
-+  return (float32x2_t) __a;
- }
- 
- __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
- vreinterpret_f32_s16 (int16x4_t __a)
- {
--  return (float32x2_t) __builtin_aarch64_reinterpretv2sfv4hi (__a);
-+  return (float32x2_t) __a;
- }
- 
- __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
- vreinterpret_f32_s32 (int32x2_t __a)
- {
--  return (float32x2_t) __builtin_aarch64_reinterpretv2sfv2si (__a);
-+  return (float32x2_t) __a;
- }
- 
- __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
- vreinterpret_f32_s64 (int64x1_t __a)
- {
--  return (float32x2_t) __builtin_aarch64_reinterpretv2sfdi (__a);
-+  return (float32x2_t) __a;
- }
- 
- __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
- vreinterpret_f32_u8 (uint8x8_t __a)
- {
--  return (float32x2_t) __builtin_aarch64_reinterpretv2sfv8qi ((int8x8_t) __a);
-+  return (float32x2_t) __a;
- }
- 
- __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
- vreinterpret_f32_u16 (uint16x4_t __a)
- {
--  return (float32x2_t) __builtin_aarch64_reinterpretv2sfv4hi ((int16x4_t)
--							      __a);
-+  return (float32x2_t) __a;
- }
- 
- __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
- vreinterpret_f32_u32 (uint32x2_t __a)
- {
--  return (float32x2_t) __builtin_aarch64_reinterpretv2sfv2si ((int32x2_t)
--							      __a);
-+  return (float32x2_t) __a;
- }
- 
- __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
- vreinterpret_f32_u64 (uint64x1_t __a)
- {
--  return (float32x2_t) __builtin_aarch64_reinterpretv2sfdi ((int64x1_t) __a);
-+  return (float32x2_t) __a;
- }
- 
- __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
- vreinterpret_f32_p8 (poly8x8_t __a)
- {
--  return (float32x2_t) __builtin_aarch64_reinterpretv2sfv8qi ((int8x8_t) __a);
-+  return (float32x2_t) __a;
- }
- 
- __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
- vreinterpret_f32_p16 (poly16x4_t __a)
- {
--  return (float32x2_t) __builtin_aarch64_reinterpretv2sfv4hi ((int16x4_t)
--							      __a);
-+  return (float32x2_t) __a;
- }
- 
- __extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
-+vreinterpretq_f32_f64 (float64x2_t __a)
-+{
-+  return (float32x4_t) __a;
-+}
-+
-+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
- vreinterpretq_f32_s8 (int8x16_t __a)
- {
--  return (float32x4_t) __builtin_aarch64_reinterpretv4sfv16qi (__a);
-+  return (float32x4_t) __a;
- }
- 
- __extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
- vreinterpretq_f32_s16 (int16x8_t __a)
- {
--  return (float32x4_t) __builtin_aarch64_reinterpretv4sfv8hi (__a);
-+  return (float32x4_t) __a;
- }
- 
- __extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
- vreinterpretq_f32_s32 (int32x4_t __a)
- {
--  return (float32x4_t) __builtin_aarch64_reinterpretv4sfv4si (__a);
-+  return (float32x4_t) __a;
- }
- 
- __extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
- vreinterpretq_f32_s64 (int64x2_t __a)
- {
--  return (float32x4_t) __builtin_aarch64_reinterpretv4sfv2di (__a);
-+  return (float32x4_t) __a;
- }
- 
- __extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
- vreinterpretq_f32_u8 (uint8x16_t __a)
- {
--  return (float32x4_t) __builtin_aarch64_reinterpretv4sfv16qi ((int8x16_t)
--							       __a);
-+  return (float32x4_t) __a;
- }
- 
- __extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
- vreinterpretq_f32_u16 (uint16x8_t __a)
- {
--  return (float32x4_t) __builtin_aarch64_reinterpretv4sfv8hi ((int16x8_t)
--							      __a);
-+  return (float32x4_t) __a;
- }
- 
- __extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
- vreinterpretq_f32_u32 (uint32x4_t __a)
- {
--  return (float32x4_t) __builtin_aarch64_reinterpretv4sfv4si ((int32x4_t)
--							      __a);
-+  return (float32x4_t) __a;
- }
- 
- __extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
- vreinterpretq_f32_u64 (uint64x2_t __a)
- {
--  return (float32x4_t) __builtin_aarch64_reinterpretv4sfv2di ((int64x2_t)
--							      __a);
-+  return (float32x4_t) __a;
- }
- 
- __extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
- vreinterpretq_f32_p8 (poly8x16_t __a)
- {
--  return (float32x4_t) __builtin_aarch64_reinterpretv4sfv16qi ((int8x16_t)
--							       __a);
-+  return (float32x4_t) __a;
- }
- 
- __extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
- vreinterpretq_f32_p16 (poly16x8_t __a)
- {
--  return (float32x4_t) __builtin_aarch64_reinterpretv4sfv8hi ((int16x8_t)
--							      __a);
-+  return (float32x4_t) __a;
- }
- 
-+__extension__ static __inline float64x1_t __attribute__((__always_inline__))
-+vreinterpret_f64_f32 (float32x2_t __a)
-+{
-+  return __builtin_aarch64_reinterpretdfv2sf (__a);
-+}
-+
-+__extension__ static __inline float64x1_t __attribute__((__always_inline__))
-+vreinterpret_f64_p8 (poly8x8_t __a)
-+{
-+  return __builtin_aarch64_reinterpretdfv8qi_sp (__a);
-+}
-+
-+__extension__ static __inline float64x1_t __attribute__((__always_inline__))
-+vreinterpret_f64_p16 (poly16x4_t __a)
-+{
-+  return __builtin_aarch64_reinterpretdfv4hi_sp (__a);
-+}
-+
-+__extension__ static __inline float64x1_t __attribute__((__always_inline__))
-+vreinterpret_f64_s8 (int8x8_t __a)
-+{
-+  return __builtin_aarch64_reinterpretdfv8qi (__a);
-+}
-+
-+__extension__ static __inline float64x1_t __attribute__((__always_inline__))
-+vreinterpret_f64_s16 (int16x4_t __a)
-+{
-+  return __builtin_aarch64_reinterpretdfv4hi (__a);
-+}
-+
-+__extension__ static __inline float64x1_t __attribute__((__always_inline__))
-+vreinterpret_f64_s32 (int32x2_t __a)
-+{
-+  return __builtin_aarch64_reinterpretdfv2si (__a);
-+}
-+
-+__extension__ static __inline float64x1_t __attribute__((__always_inline__))
-+vreinterpret_f64_s64 (int64x1_t __a)
-+{
-+  return __builtin_aarch64_createdf ((uint64_t) vget_lane_s64 (__a, 0));
-+}
-+
-+__extension__ static __inline float64x1_t __attribute__((__always_inline__))
-+vreinterpret_f64_u8 (uint8x8_t __a)
-+{
-+  return __builtin_aarch64_reinterpretdfv8qi_su (__a);
-+}
-+
-+__extension__ static __inline float64x1_t __attribute__((__always_inline__))
-+vreinterpret_f64_u16 (uint16x4_t __a)
-+{
-+  return __builtin_aarch64_reinterpretdfv4hi_su (__a);
-+}
-+
-+__extension__ static __inline float64x1_t __attribute__((__always_inline__))
-+vreinterpret_f64_u32 (uint32x2_t __a)
-+{
-+  return __builtin_aarch64_reinterpretdfv2si_su (__a);
-+}
-+
-+__extension__ static __inline float64x1_t __attribute__((__always_inline__))
-+vreinterpret_f64_u64 (uint64x1_t __a)
-+{
-+  return __builtin_aarch64_createdf (vget_lane_u64 (__a, 0));
-+}
-+
-+__extension__ static __inline float64x2_t __attribute__((__always_inline__))
-+vreinterpretq_f64_f32 (float32x4_t __a)
-+{
-+  return (float64x2_t) __a;
-+}
-+
-+__extension__ static __inline float64x2_t __attribute__((__always_inline__))
-+vreinterpretq_f64_p8 (poly8x16_t __a)
-+{
-+  return (float64x2_t) __a;
-+}
-+
-+__extension__ static __inline float64x2_t __attribute__((__always_inline__))
-+vreinterpretq_f64_p16 (poly16x8_t __a)
-+{
-+  return (float64x2_t) __a;
-+}
-+
-+__extension__ static __inline float64x2_t __attribute__((__always_inline__))
-+vreinterpretq_f64_s8 (int8x16_t __a)
-+{
-+  return (float64x2_t) __a;
-+}
-+
-+__extension__ static __inline float64x2_t __attribute__((__always_inline__))
-+vreinterpretq_f64_s16 (int16x8_t __a)
-+{
-+  return (float64x2_t) __a;
-+}
-+
-+__extension__ static __inline float64x2_t __attribute__((__always_inline__))
-+vreinterpretq_f64_s32 (int32x4_t __a)
-+{
-+  return (float64x2_t) __a;
-+}
-+
-+__extension__ static __inline float64x2_t __attribute__((__always_inline__))
-+vreinterpretq_f64_s64 (int64x2_t __a)
-+{
-+  return (float64x2_t) __a;
-+}
-+
-+__extension__ static __inline float64x2_t __attribute__((__always_inline__))
-+vreinterpretq_f64_u8 (uint8x16_t __a)
-+{
-+  return (float64x2_t) __a;
-+}
-+
-+__extension__ static __inline float64x2_t __attribute__((__always_inline__))
-+vreinterpretq_f64_u16 (uint16x8_t __a)
-+{
-+  return (float64x2_t) __a;
-+}
-+
-+__extension__ static __inline float64x2_t __attribute__((__always_inline__))
-+vreinterpretq_f64_u32 (uint32x4_t __a)
-+{
-+  return (float64x2_t) __a;
-+}
-+
-+__extension__ static __inline float64x2_t __attribute__((__always_inline__))
-+vreinterpretq_f64_u64 (uint64x2_t __a)
-+{
-+  return (float64x2_t) __a;
-+}
-+
- __extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
-+vreinterpret_s64_f64 (float64x1_t __a)
-+{
-+  return __builtin_aarch64_reinterpretdidf (__a);
-+}
-+
-+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
- vreinterpret_s64_s8 (int8x8_t __a)
- {
--  return (int64x1_t) __builtin_aarch64_reinterpretdiv8qi (__a);
-+  return (int64x1_t) __a;
- }
- 
- __extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
- vreinterpret_s64_s16 (int16x4_t __a)
- {
--  return (int64x1_t) __builtin_aarch64_reinterpretdiv4hi (__a);
-+  return (int64x1_t) __a;
- }
- 
- __extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
- vreinterpret_s64_s32 (int32x2_t __a)
- {
--  return (int64x1_t) __builtin_aarch64_reinterpretdiv2si (__a);
-+  return (int64x1_t) __a;
- }
- 
- __extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
- vreinterpret_s64_f32 (float32x2_t __a)
- {
--  return (int64x1_t) __builtin_aarch64_reinterpretdiv2sf (__a);
-+  return (int64x1_t) __a;
- }
- 
- __extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
- vreinterpret_s64_u8 (uint8x8_t __a)
- {
--  return (int64x1_t) __builtin_aarch64_reinterpretdiv8qi ((int8x8_t) __a);
-+  return (int64x1_t) __a;
- }
- 
- __extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
- vreinterpret_s64_u16 (uint16x4_t __a)
- {
--  return (int64x1_t) __builtin_aarch64_reinterpretdiv4hi ((int16x4_t) __a);
-+  return (int64x1_t) __a;
- }
- 
- __extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
- vreinterpret_s64_u32 (uint32x2_t __a)
- {
--  return (int64x1_t) __builtin_aarch64_reinterpretdiv2si ((int32x2_t) __a);
-+  return (int64x1_t) __a;
- }
- 
- __extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
- vreinterpret_s64_u64 (uint64x1_t __a)
- {
--  return (int64x1_t) __builtin_aarch64_reinterpretdidi ((int64x1_t) __a);
-+  return (int64x1_t) __a;
- }
- 
- __extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
- vreinterpret_s64_p8 (poly8x8_t __a)
- {
--  return (int64x1_t) __builtin_aarch64_reinterpretdiv8qi ((int8x8_t) __a);
-+  return (int64x1_t) __a;
- }
- 
- __extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
- vreinterpret_s64_p16 (poly16x4_t __a)
- {
--  return (int64x1_t) __builtin_aarch64_reinterpretdiv4hi ((int16x4_t) __a);
-+  return (int64x1_t) __a;
- }
- 
- __extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
-+vreinterpretq_s64_f64 (float64x2_t __a)
-+{
-+  return (int64x2_t) __a;
-+}
-+
-+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
- vreinterpretq_s64_s8 (int8x16_t __a)
- {
--  return (int64x2_t) __builtin_aarch64_reinterpretv2div16qi (__a);
-+  return (int64x2_t) __a;
- }
- 
- __extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
- vreinterpretq_s64_s16 (int16x8_t __a)
- {
--  return (int64x2_t) __builtin_aarch64_reinterpretv2div8hi (__a);
-+  return (int64x2_t) __a;
- }
- 
- __extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
- vreinterpretq_s64_s32 (int32x4_t __a)
- {
--  return (int64x2_t) __builtin_aarch64_reinterpretv2div4si (__a);
-+  return (int64x2_t) __a;
- }
- 
- __extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
- vreinterpretq_s64_f32 (float32x4_t __a)
- {
--  return (int64x2_t) __builtin_aarch64_reinterpretv2div4sf (__a);
-+  return (int64x2_t) __a;
- }
- 
- __extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
- vreinterpretq_s64_u8 (uint8x16_t __a)
- {
--  return (int64x2_t) __builtin_aarch64_reinterpretv2div16qi ((int8x16_t) __a);
-+  return (int64x2_t) __a;
- }
- 
- __extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
- vreinterpretq_s64_u16 (uint16x8_t __a)
- {
--  return (int64x2_t) __builtin_aarch64_reinterpretv2div8hi ((int16x8_t) __a);
-+  return (int64x2_t) __a;
- }
- 
- __extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
- vreinterpretq_s64_u32 (uint32x4_t __a)
- {
--  return (int64x2_t) __builtin_aarch64_reinterpretv2div4si ((int32x4_t) __a);
-+  return (int64x2_t) __a;
- }
- 
- __extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
- vreinterpretq_s64_u64 (uint64x2_t __a)
- {
--  return (int64x2_t) __builtin_aarch64_reinterpretv2div2di ((int64x2_t) __a);
-+  return (int64x2_t) __a;
- }
- 
- __extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
- vreinterpretq_s64_p8 (poly8x16_t __a)
- {
--  return (int64x2_t) __builtin_aarch64_reinterpretv2div16qi ((int8x16_t) __a);
-+  return (int64x2_t) __a;
- }
- 
- __extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
- vreinterpretq_s64_p16 (poly16x8_t __a)
- {
--  return (int64x2_t) __builtin_aarch64_reinterpretv2div8hi ((int16x8_t) __a);
-+  return (int64x2_t) __a;
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
-+vreinterpret_u64_f64 (float64x1_t __a)
-+{
-+  return __builtin_aarch64_reinterpretdidf_us (__a);
-+}
-+
-+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vreinterpret_u64_s8 (int8x8_t __a)
- {
--  return (uint64x1_t) __builtin_aarch64_reinterpretdiv8qi (__a);
-+  return (uint64x1_t) __a;
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vreinterpret_u64_s16 (int16x4_t __a)
- {
--  return (uint64x1_t) __builtin_aarch64_reinterpretdiv4hi (__a);
-+  return (uint64x1_t) __a;
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vreinterpret_u64_s32 (int32x2_t __a)
- {
--  return (uint64x1_t) __builtin_aarch64_reinterpretdiv2si (__a);
-+  return (uint64x1_t) __a;
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vreinterpret_u64_s64 (int64x1_t __a)
- {
--  return (uint64x1_t) __builtin_aarch64_reinterpretdidi (__a);
-+  return (uint64x1_t) __a;
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vreinterpret_u64_f32 (float32x2_t __a)
- {
--  return (uint64x1_t) __builtin_aarch64_reinterpretdiv2sf (__a);
-+  return (uint64x1_t) __a;
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vreinterpret_u64_u8 (uint8x8_t __a)
- {
--  return (uint64x1_t) __builtin_aarch64_reinterpretdiv8qi ((int8x8_t) __a);
-+  return (uint64x1_t) __a;
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vreinterpret_u64_u16 (uint16x4_t __a)
- {
--  return (uint64x1_t) __builtin_aarch64_reinterpretdiv4hi ((int16x4_t) __a);
-+  return (uint64x1_t) __a;
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vreinterpret_u64_u32 (uint32x2_t __a)
- {
--  return (uint64x1_t) __builtin_aarch64_reinterpretdiv2si ((int32x2_t) __a);
-+  return (uint64x1_t) __a;
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vreinterpret_u64_p8 (poly8x8_t __a)
- {
--  return (uint64x1_t) __builtin_aarch64_reinterpretdiv8qi ((int8x8_t) __a);
-+  return (uint64x1_t) __a;
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vreinterpret_u64_p16 (poly16x4_t __a)
- {
--  return (uint64x1_t) __builtin_aarch64_reinterpretdiv4hi ((int16x4_t) __a);
-+  return (uint64x1_t) __a;
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
-+vreinterpretq_u64_f64 (float64x2_t __a)
-+{
-+  return (uint64x2_t) __a;
-+}
-+
-+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vreinterpretq_u64_s8 (int8x16_t __a)
- {
--  return (uint64x2_t) __builtin_aarch64_reinterpretv2div16qi (__a);
-+  return (uint64x2_t) __a;
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vreinterpretq_u64_s16 (int16x8_t __a)
- {
--  return (uint64x2_t) __builtin_aarch64_reinterpretv2div8hi (__a);
-+  return (uint64x2_t) __a;
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vreinterpretq_u64_s32 (int32x4_t __a)
- {
--  return (uint64x2_t) __builtin_aarch64_reinterpretv2div4si (__a);
-+  return (uint64x2_t) __a;
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vreinterpretq_u64_s64 (int64x2_t __a)
- {
--  return (uint64x2_t) __builtin_aarch64_reinterpretv2div2di (__a);
-+  return (uint64x2_t) __a;
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vreinterpretq_u64_f32 (float32x4_t __a)
- {
--  return (uint64x2_t) __builtin_aarch64_reinterpretv2div4sf (__a);
-+  return (uint64x2_t) __a;
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vreinterpretq_u64_u8 (uint8x16_t __a)
- {
--  return (uint64x2_t) __builtin_aarch64_reinterpretv2div16qi ((int8x16_t)
--							      __a);
-+  return (uint64x2_t) __a;
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vreinterpretq_u64_u16 (uint16x8_t __a)
- {
--  return (uint64x2_t) __builtin_aarch64_reinterpretv2div8hi ((int16x8_t) __a);
-+  return (uint64x2_t) __a;
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vreinterpretq_u64_u32 (uint32x4_t __a)
- {
--  return (uint64x2_t) __builtin_aarch64_reinterpretv2div4si ((int32x4_t) __a);
-+  return (uint64x2_t) __a;
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vreinterpretq_u64_p8 (poly8x16_t __a)
- {
--  return (uint64x2_t) __builtin_aarch64_reinterpretv2div16qi ((int8x16_t)
--							      __a);
-+  return (uint64x2_t) __a;
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vreinterpretq_u64_p16 (poly16x8_t __a)
- {
--  return (uint64x2_t) __builtin_aarch64_reinterpretv2div8hi ((int16x8_t) __a);
-+  return (uint64x2_t) __a;
- }
- 
- __extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
-+vreinterpret_s8_f64 (float64x1_t __a)
-+{
-+  return __builtin_aarch64_reinterpretv8qidf (__a);
-+}
-+
-+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
- vreinterpret_s8_s16 (int16x4_t __a)
- {
--  return (int8x8_t) __builtin_aarch64_reinterpretv8qiv4hi (__a);
-+  return (int8x8_t) __a;
- }
- 
- __extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
- vreinterpret_s8_s32 (int32x2_t __a)
- {
--  return (int8x8_t) __builtin_aarch64_reinterpretv8qiv2si (__a);
-+  return (int8x8_t) __a;
- }
- 
- __extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
- vreinterpret_s8_s64 (int64x1_t __a)
- {
--  return (int8x8_t) __builtin_aarch64_reinterpretv8qidi (__a);
-+  return (int8x8_t) __a;
- }
- 
- __extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
- vreinterpret_s8_f32 (float32x2_t __a)
- {
--  return (int8x8_t) __builtin_aarch64_reinterpretv8qiv2sf (__a);
-+  return (int8x8_t) __a;
- }
- 
- __extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
- vreinterpret_s8_u8 (uint8x8_t __a)
- {
--  return (int8x8_t) __builtin_aarch64_reinterpretv8qiv8qi ((int8x8_t) __a);
-+  return (int8x8_t) __a;
- }
- 
- __extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
- vreinterpret_s8_u16 (uint16x4_t __a)
- {
--  return (int8x8_t) __builtin_aarch64_reinterpretv8qiv4hi ((int16x4_t) __a);
-+  return (int8x8_t) __a;
- }
- 
- __extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
- vreinterpret_s8_u32 (uint32x2_t __a)
- {
--  return (int8x8_t) __builtin_aarch64_reinterpretv8qiv2si ((int32x2_t) __a);
-+  return (int8x8_t) __a;
- }
- 
- __extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
- vreinterpret_s8_u64 (uint64x1_t __a)
- {
--  return (int8x8_t) __builtin_aarch64_reinterpretv8qidi ((int64x1_t) __a);
-+  return (int8x8_t) __a;
- }
- 
- __extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
- vreinterpret_s8_p8 (poly8x8_t __a)
- {
--  return (int8x8_t) __builtin_aarch64_reinterpretv8qiv8qi ((int8x8_t) __a);
-+  return (int8x8_t) __a;
- }
- 
- __extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
- vreinterpret_s8_p16 (poly16x4_t __a)
- {
--  return (int8x8_t) __builtin_aarch64_reinterpretv8qiv4hi ((int16x4_t) __a);
-+  return (int8x8_t) __a;
- }
- 
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
-+vreinterpretq_s8_f64 (float64x2_t __a)
-+{
-+  return (int8x16_t) __a;
-+}
-+
-+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
- vreinterpretq_s8_s16 (int16x8_t __a)
- {
--  return (int8x16_t) __builtin_aarch64_reinterpretv16qiv8hi (__a);
-+  return (int8x16_t) __a;
- }
- 
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
- vreinterpretq_s8_s32 (int32x4_t __a)
- {
--  return (int8x16_t) __builtin_aarch64_reinterpretv16qiv4si (__a);
-+  return (int8x16_t) __a;
- }
- 
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
- vreinterpretq_s8_s64 (int64x2_t __a)
- {
--  return (int8x16_t) __builtin_aarch64_reinterpretv16qiv2di (__a);
-+  return (int8x16_t) __a;
- }
- 
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
- vreinterpretq_s8_f32 (float32x4_t __a)
- {
--  return (int8x16_t) __builtin_aarch64_reinterpretv16qiv4sf (__a);
-+  return (int8x16_t) __a;
- }
- 
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
- vreinterpretq_s8_u8 (uint8x16_t __a)
- {
--  return (int8x16_t) __builtin_aarch64_reinterpretv16qiv16qi ((int8x16_t)
--							      __a);
-+  return (int8x16_t) __a;
- }
- 
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
- vreinterpretq_s8_u16 (uint16x8_t __a)
- {
--  return (int8x16_t) __builtin_aarch64_reinterpretv16qiv8hi ((int16x8_t) __a);
-+  return (int8x16_t) __a;
- }
- 
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
- vreinterpretq_s8_u32 (uint32x4_t __a)
- {
--  return (int8x16_t) __builtin_aarch64_reinterpretv16qiv4si ((int32x4_t) __a);
-+  return (int8x16_t) __a;
- }
- 
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
- vreinterpretq_s8_u64 (uint64x2_t __a)
- {
--  return (int8x16_t) __builtin_aarch64_reinterpretv16qiv2di ((int64x2_t) __a);
-+  return (int8x16_t) __a;
- }
- 
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
- vreinterpretq_s8_p8 (poly8x16_t __a)
- {
--  return (int8x16_t) __builtin_aarch64_reinterpretv16qiv16qi ((int8x16_t)
--							      __a);
-+  return (int8x16_t) __a;
- }
- 
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
- vreinterpretq_s8_p16 (poly16x8_t __a)
- {
--  return (int8x16_t) __builtin_aarch64_reinterpretv16qiv8hi ((int16x8_t) __a);
-+  return (int8x16_t) __a;
- }
- 
- __extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
-+vreinterpret_s16_f64 (float64x1_t __a)
-+{
-+  return __builtin_aarch64_reinterpretv4hidf (__a);
-+}
-+
-+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
- vreinterpret_s16_s8 (int8x8_t __a)
- {
--  return (int16x4_t) __builtin_aarch64_reinterpretv4hiv8qi (__a);
-+  return (int16x4_t) __a;
- }
- 
- __extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
- vreinterpret_s16_s32 (int32x2_t __a)
- {
--  return (int16x4_t) __builtin_aarch64_reinterpretv4hiv2si (__a);
-+  return (int16x4_t) __a;
- }
- 
- __extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
- vreinterpret_s16_s64 (int64x1_t __a)
- {
--  return (int16x4_t) __builtin_aarch64_reinterpretv4hidi (__a);
-+  return (int16x4_t) __a;
- }
- 
- __extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
- vreinterpret_s16_f32 (float32x2_t __a)
- {
--  return (int16x4_t) __builtin_aarch64_reinterpretv4hiv2sf (__a);
-+  return (int16x4_t) __a;
- }
- 
- __extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
- vreinterpret_s16_u8 (uint8x8_t __a)
- {
--  return (int16x4_t) __builtin_aarch64_reinterpretv4hiv8qi ((int8x8_t) __a);
-+  return (int16x4_t) __a;
- }
- 
- __extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
- vreinterpret_s16_u16 (uint16x4_t __a)
- {
--  return (int16x4_t) __builtin_aarch64_reinterpretv4hiv4hi ((int16x4_t) __a);
-+  return (int16x4_t) __a;
- }
- 
- __extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
- vreinterpret_s16_u32 (uint32x2_t __a)
- {
--  return (int16x4_t) __builtin_aarch64_reinterpretv4hiv2si ((int32x2_t) __a);
-+  return (int16x4_t) __a;
- }
- 
- __extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
- vreinterpret_s16_u64 (uint64x1_t __a)
- {
--  return (int16x4_t) __builtin_aarch64_reinterpretv4hidi ((int64x1_t) __a);
-+  return (int16x4_t) __a;
- }
- 
- __extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
- vreinterpret_s16_p8 (poly8x8_t __a)
- {
--  return (int16x4_t) __builtin_aarch64_reinterpretv4hiv8qi ((int8x8_t) __a);
-+  return (int16x4_t) __a;
- }
- 
- __extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
- vreinterpret_s16_p16 (poly16x4_t __a)
- {
--  return (int16x4_t) __builtin_aarch64_reinterpretv4hiv4hi ((int16x4_t) __a);
-+  return (int16x4_t) __a;
- }
- 
- __extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
-+vreinterpretq_s16_f64 (float64x2_t __a)
-+{
-+  return (int16x8_t) __a;
-+}
-+
-+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
- vreinterpretq_s16_s8 (int8x16_t __a)
- {
--  return (int16x8_t) __builtin_aarch64_reinterpretv8hiv16qi (__a);
-+  return (int16x8_t) __a;
- }
- 
- __extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
- vreinterpretq_s16_s32 (int32x4_t __a)
- {
--  return (int16x8_t) __builtin_aarch64_reinterpretv8hiv4si (__a);
-+  return (int16x8_t) __a;
- }
- 
- __extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
- vreinterpretq_s16_s64 (int64x2_t __a)
- {
--  return (int16x8_t) __builtin_aarch64_reinterpretv8hiv2di (__a);
-+  return (int16x8_t) __a;
- }
- 
- __extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
- vreinterpretq_s16_f32 (float32x4_t __a)
- {
--  return (int16x8_t) __builtin_aarch64_reinterpretv8hiv4sf (__a);
-+  return (int16x8_t) __a;
- }
- 
- __extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
- vreinterpretq_s16_u8 (uint8x16_t __a)
- {
--  return (int16x8_t) __builtin_aarch64_reinterpretv8hiv16qi ((int8x16_t) __a);
-+  return (int16x8_t) __a;
- }
- 
- __extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
- vreinterpretq_s16_u16 (uint16x8_t __a)
- {
--  return (int16x8_t) __builtin_aarch64_reinterpretv8hiv8hi ((int16x8_t) __a);
-+  return (int16x8_t) __a;
- }
- 
- __extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
- vreinterpretq_s16_u32 (uint32x4_t __a)
- {
--  return (int16x8_t) __builtin_aarch64_reinterpretv8hiv4si ((int32x4_t) __a);
-+  return (int16x8_t) __a;
- }
- 
- __extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
- vreinterpretq_s16_u64 (uint64x2_t __a)
- {
--  return (int16x8_t) __builtin_aarch64_reinterpretv8hiv2di ((int64x2_t) __a);
-+  return (int16x8_t) __a;
- }
- 
- __extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
- vreinterpretq_s16_p8 (poly8x16_t __a)
- {
--  return (int16x8_t) __builtin_aarch64_reinterpretv8hiv16qi ((int8x16_t) __a);
-+  return (int16x8_t) __a;
- }
- 
- __extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
- vreinterpretq_s16_p16 (poly16x8_t __a)
- {
--  return (int16x8_t) __builtin_aarch64_reinterpretv8hiv8hi ((int16x8_t) __a);
-+  return (int16x8_t) __a;
- }
- 
- __extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
-+vreinterpret_s32_f64 (float64x1_t __a)
-+{
-+  return __builtin_aarch64_reinterpretv2sidf (__a);
-+}
-+
-+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
- vreinterpret_s32_s8 (int8x8_t __a)
- {
--  return (int32x2_t) __builtin_aarch64_reinterpretv2siv8qi (__a);
-+  return (int32x2_t) __a;
- }
- 
- __extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
- vreinterpret_s32_s16 (int16x4_t __a)
- {
--  return (int32x2_t) __builtin_aarch64_reinterpretv2siv4hi (__a);
-+  return (int32x2_t) __a;
- }
- 
- __extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
- vreinterpret_s32_s64 (int64x1_t __a)
- {
--  return (int32x2_t) __builtin_aarch64_reinterpretv2sidi (__a);
-+  return (int32x2_t) __a;
- }
- 
- __extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
- vreinterpret_s32_f32 (float32x2_t __a)
- {
--  return (int32x2_t) __builtin_aarch64_reinterpretv2siv2sf (__a);
-+  return (int32x2_t) __a;
- }
- 
- __extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
- vreinterpret_s32_u8 (uint8x8_t __a)
- {
--  return (int32x2_t) __builtin_aarch64_reinterpretv2siv8qi ((int8x8_t) __a);
-+  return (int32x2_t) __a;
- }
- 
- __extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
- vreinterpret_s32_u16 (uint16x4_t __a)
- {
--  return (int32x2_t) __builtin_aarch64_reinterpretv2siv4hi ((int16x4_t) __a);
-+  return (int32x2_t) __a;
- }
- 
- __extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
- vreinterpret_s32_u32 (uint32x2_t __a)
- {
--  return (int32x2_t) __builtin_aarch64_reinterpretv2siv2si ((int32x2_t) __a);
-+  return (int32x2_t) __a;
- }
- 
- __extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
- vreinterpret_s32_u64 (uint64x1_t __a)
- {
--  return (int32x2_t) __builtin_aarch64_reinterpretv2sidi ((int64x1_t) __a);
-+  return (int32x2_t) __a;
- }
- 
- __extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
- vreinterpret_s32_p8 (poly8x8_t __a)
- {
--  return (int32x2_t) __builtin_aarch64_reinterpretv2siv8qi ((int8x8_t) __a);
-+  return (int32x2_t) __a;
- }
- 
- __extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
- vreinterpret_s32_p16 (poly16x4_t __a)
- {
--  return (int32x2_t) __builtin_aarch64_reinterpretv2siv4hi ((int16x4_t) __a);
-+  return (int32x2_t) __a;
- }
- 
- __extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
-+vreinterpretq_s32_f64 (float64x2_t __a)
-+{
-+  return (int32x4_t) __a;
-+}
-+
-+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
- vreinterpretq_s32_s8 (int8x16_t __a)
- {
--  return (int32x4_t) __builtin_aarch64_reinterpretv4siv16qi (__a);
-+  return (int32x4_t) __a;
- }
- 
- __extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
- vreinterpretq_s32_s16 (int16x8_t __a)
- {
--  return (int32x4_t) __builtin_aarch64_reinterpretv4siv8hi (__a);
-+  return (int32x4_t) __a;
- }
- 
- __extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
- vreinterpretq_s32_s64 (int64x2_t __a)
- {
--  return (int32x4_t) __builtin_aarch64_reinterpretv4siv2di (__a);
-+  return (int32x4_t) __a;
- }
- 
- __extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
- vreinterpretq_s32_f32 (float32x4_t __a)
- {
--  return (int32x4_t) __builtin_aarch64_reinterpretv4siv4sf (__a);
-+  return (int32x4_t) __a;
- }
- 
- __extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
- vreinterpretq_s32_u8 (uint8x16_t __a)
- {
--  return (int32x4_t) __builtin_aarch64_reinterpretv4siv16qi ((int8x16_t) __a);
-+  return (int32x4_t) __a;
- }
- 
- __extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
- vreinterpretq_s32_u16 (uint16x8_t __a)
- {
--  return (int32x4_t) __builtin_aarch64_reinterpretv4siv8hi ((int16x8_t) __a);
-+  return (int32x4_t) __a;
- }
- 
- __extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
- vreinterpretq_s32_u32 (uint32x4_t __a)
- {
--  return (int32x4_t) __builtin_aarch64_reinterpretv4siv4si ((int32x4_t) __a);
-+  return (int32x4_t) __a;
- }
- 
- __extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
- vreinterpretq_s32_u64 (uint64x2_t __a)
- {
--  return (int32x4_t) __builtin_aarch64_reinterpretv4siv2di ((int64x2_t) __a);
-+  return (int32x4_t) __a;
- }
- 
- __extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
- vreinterpretq_s32_p8 (poly8x16_t __a)
- {
--  return (int32x4_t) __builtin_aarch64_reinterpretv4siv16qi ((int8x16_t) __a);
-+  return (int32x4_t) __a;
- }
- 
- __extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
- vreinterpretq_s32_p16 (poly16x8_t __a)
- {
--  return (int32x4_t) __builtin_aarch64_reinterpretv4siv8hi ((int16x8_t) __a);
-+  return (int32x4_t) __a;
- }
- 
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
-+vreinterpret_u8_f64 (float64x1_t __a)
-+{
-+  return __builtin_aarch64_reinterpretv8qidf_us (__a);
-+}
-+
-+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vreinterpret_u8_s8 (int8x8_t __a)
- {
--  return (uint8x8_t) __builtin_aarch64_reinterpretv8qiv8qi (__a);
-+  return (uint8x8_t) __a;
- }
- 
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vreinterpret_u8_s16 (int16x4_t __a)
- {
--  return (uint8x8_t) __builtin_aarch64_reinterpretv8qiv4hi (__a);
-+  return (uint8x8_t) __a;
- }
- 
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vreinterpret_u8_s32 (int32x2_t __a)
- {
--  return (uint8x8_t) __builtin_aarch64_reinterpretv8qiv2si (__a);
-+  return (uint8x8_t) __a;
- }
- 
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vreinterpret_u8_s64 (int64x1_t __a)
- {
--  return (uint8x8_t) __builtin_aarch64_reinterpretv8qidi (__a);
-+  return (uint8x8_t) __a;
- }
- 
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vreinterpret_u8_f32 (float32x2_t __a)
- {
--  return (uint8x8_t) __builtin_aarch64_reinterpretv8qiv2sf (__a);
-+  return (uint8x8_t) __a;
- }
- 
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vreinterpret_u8_u16 (uint16x4_t __a)
- {
--  return (uint8x8_t) __builtin_aarch64_reinterpretv8qiv4hi ((int16x4_t) __a);
-+  return (uint8x8_t) __a;
- }
- 
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vreinterpret_u8_u32 (uint32x2_t __a)
- {
--  return (uint8x8_t) __builtin_aarch64_reinterpretv8qiv2si ((int32x2_t) __a);
-+  return (uint8x8_t) __a;
- }
- 
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vreinterpret_u8_u64 (uint64x1_t __a)
- {
--  return (uint8x8_t) __builtin_aarch64_reinterpretv8qidi ((int64x1_t) __a);
-+  return (uint8x8_t) __a;
- }
- 
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vreinterpret_u8_p8 (poly8x8_t __a)
- {
--  return (uint8x8_t) __builtin_aarch64_reinterpretv8qiv8qi ((int8x8_t) __a);
-+  return (uint8x8_t) __a;
- }
- 
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vreinterpret_u8_p16 (poly16x4_t __a)
- {
--  return (uint8x8_t) __builtin_aarch64_reinterpretv8qiv4hi ((int16x4_t) __a);
-+  return (uint8x8_t) __a;
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
-+vreinterpretq_u8_f64 (float64x2_t __a)
-+{
-+  return (uint8x16_t) __a;
-+}
-+
-+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vreinterpretq_u8_s8 (int8x16_t __a)
- {
--  return (uint8x16_t) __builtin_aarch64_reinterpretv16qiv16qi (__a);
-+  return (uint8x16_t) __a;
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vreinterpretq_u8_s16 (int16x8_t __a)
- {
--  return (uint8x16_t) __builtin_aarch64_reinterpretv16qiv8hi (__a);
-+  return (uint8x16_t) __a;
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vreinterpretq_u8_s32 (int32x4_t __a)
- {
--  return (uint8x16_t) __builtin_aarch64_reinterpretv16qiv4si (__a);
-+  return (uint8x16_t) __a;
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vreinterpretq_u8_s64 (int64x2_t __a)
- {
--  return (uint8x16_t) __builtin_aarch64_reinterpretv16qiv2di (__a);
-+  return (uint8x16_t) __a;
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vreinterpretq_u8_f32 (float32x4_t __a)
- {
--  return (uint8x16_t) __builtin_aarch64_reinterpretv16qiv4sf (__a);
-+  return (uint8x16_t) __a;
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vreinterpretq_u8_u16 (uint16x8_t __a)
- {
--  return (uint8x16_t) __builtin_aarch64_reinterpretv16qiv8hi ((int16x8_t)
--							      __a);
-+  return (uint8x16_t) __a;
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vreinterpretq_u8_u32 (uint32x4_t __a)
- {
--  return (uint8x16_t) __builtin_aarch64_reinterpretv16qiv4si ((int32x4_t)
--							      __a);
-+  return (uint8x16_t) __a;
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vreinterpretq_u8_u64 (uint64x2_t __a)
- {
--  return (uint8x16_t) __builtin_aarch64_reinterpretv16qiv2di ((int64x2_t)
--							      __a);
-+  return (uint8x16_t) __a;
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vreinterpretq_u8_p8 (poly8x16_t __a)
- {
--  return (uint8x16_t) __builtin_aarch64_reinterpretv16qiv16qi ((int8x16_t)
--							       __a);
-+  return (uint8x16_t) __a;
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vreinterpretq_u8_p16 (poly16x8_t __a)
- {
--  return (uint8x16_t) __builtin_aarch64_reinterpretv16qiv8hi ((int16x8_t)
--							      __a);
-+  return (uint8x16_t) __a;
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
-+vreinterpret_u16_f64 (float64x1_t __a)
-+{
-+  return __builtin_aarch64_reinterpretv4hidf_us (__a);
-+}
-+
-+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vreinterpret_u16_s8 (int8x8_t __a)
- {
--  return (uint16x4_t) __builtin_aarch64_reinterpretv4hiv8qi (__a);
-+  return (uint16x4_t) __a;
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vreinterpret_u16_s16 (int16x4_t __a)
- {
--  return (uint16x4_t) __builtin_aarch64_reinterpretv4hiv4hi (__a);
-+  return (uint16x4_t) __a;
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vreinterpret_u16_s32 (int32x2_t __a)
- {
--  return (uint16x4_t) __builtin_aarch64_reinterpretv4hiv2si (__a);
-+  return (uint16x4_t) __a;
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vreinterpret_u16_s64 (int64x1_t __a)
- {
--  return (uint16x4_t) __builtin_aarch64_reinterpretv4hidi (__a);
-+  return (uint16x4_t) __a;
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vreinterpret_u16_f32 (float32x2_t __a)
- {
--  return (uint16x4_t) __builtin_aarch64_reinterpretv4hiv2sf (__a);
-+  return (uint16x4_t) __a;
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vreinterpret_u16_u8 (uint8x8_t __a)
- {
--  return (uint16x4_t) __builtin_aarch64_reinterpretv4hiv8qi ((int8x8_t) __a);
-+  return (uint16x4_t) __a;
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vreinterpret_u16_u32 (uint32x2_t __a)
- {
--  return (uint16x4_t) __builtin_aarch64_reinterpretv4hiv2si ((int32x2_t) __a);
-+  return (uint16x4_t) __a;
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vreinterpret_u16_u64 (uint64x1_t __a)
- {
--  return (uint16x4_t) __builtin_aarch64_reinterpretv4hidi ((int64x1_t) __a);
-+  return (uint16x4_t) __a;
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vreinterpret_u16_p8 (poly8x8_t __a)
- {
--  return (uint16x4_t) __builtin_aarch64_reinterpretv4hiv8qi ((int8x8_t) __a);
-+  return (uint16x4_t) __a;
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vreinterpret_u16_p16 (poly16x4_t __a)
- {
--  return (uint16x4_t) __builtin_aarch64_reinterpretv4hiv4hi ((int16x4_t) __a);
-+  return (uint16x4_t) __a;
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
-+vreinterpretq_u16_f64 (float64x2_t __a)
-+{
-+  return (uint16x8_t) __a;
-+}
-+
-+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vreinterpretq_u16_s8 (int8x16_t __a)
- {
--  return (uint16x8_t) __builtin_aarch64_reinterpretv8hiv16qi (__a);
-+  return (uint16x8_t) __a;
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vreinterpretq_u16_s16 (int16x8_t __a)
- {
--  return (uint16x8_t) __builtin_aarch64_reinterpretv8hiv8hi (__a);
-+  return (uint16x8_t) __a;
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vreinterpretq_u16_s32 (int32x4_t __a)
- {
--  return (uint16x8_t) __builtin_aarch64_reinterpretv8hiv4si (__a);
-+  return (uint16x8_t) __a;
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vreinterpretq_u16_s64 (int64x2_t __a)
- {
--  return (uint16x8_t) __builtin_aarch64_reinterpretv8hiv2di (__a);
-+  return (uint16x8_t) __a;
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vreinterpretq_u16_f32 (float32x4_t __a)
- {
--  return (uint16x8_t) __builtin_aarch64_reinterpretv8hiv4sf (__a);
-+  return (uint16x8_t) __a;
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vreinterpretq_u16_u8 (uint8x16_t __a)
- {
--  return (uint16x8_t) __builtin_aarch64_reinterpretv8hiv16qi ((int8x16_t)
--							      __a);
-+  return (uint16x8_t) __a;
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vreinterpretq_u16_u32 (uint32x4_t __a)
- {
--  return (uint16x8_t) __builtin_aarch64_reinterpretv8hiv4si ((int32x4_t) __a);
-+  return (uint16x8_t) __a;
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vreinterpretq_u16_u64 (uint64x2_t __a)
- {
--  return (uint16x8_t) __builtin_aarch64_reinterpretv8hiv2di ((int64x2_t) __a);
-+  return (uint16x8_t) __a;
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vreinterpretq_u16_p8 (poly8x16_t __a)
- {
--  return (uint16x8_t) __builtin_aarch64_reinterpretv8hiv16qi ((int8x16_t)
--							      __a);
-+  return (uint16x8_t) __a;
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vreinterpretq_u16_p16 (poly16x8_t __a)
- {
--  return (uint16x8_t) __builtin_aarch64_reinterpretv8hiv8hi ((int16x8_t) __a);
-+  return (uint16x8_t) __a;
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
-+vreinterpret_u32_f64 (float64x1_t __a)
-+{
-+  return __builtin_aarch64_reinterpretv2sidf_us (__a);
-+}
-+
-+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vreinterpret_u32_s8 (int8x8_t __a)
- {
--  return (uint32x2_t) __builtin_aarch64_reinterpretv2siv8qi (__a);
-+  return (uint32x2_t) __a;
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vreinterpret_u32_s16 (int16x4_t __a)
- {
--  return (uint32x2_t) __builtin_aarch64_reinterpretv2siv4hi (__a);
-+  return (uint32x2_t) __a;
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vreinterpret_u32_s32 (int32x2_t __a)
- {
--  return (uint32x2_t) __builtin_aarch64_reinterpretv2siv2si (__a);
-+  return (uint32x2_t) __a;
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vreinterpret_u32_s64 (int64x1_t __a)
- {
--  return (uint32x2_t) __builtin_aarch64_reinterpretv2sidi (__a);
-+  return (uint32x2_t) __a;
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vreinterpret_u32_f32 (float32x2_t __a)
- {
--  return (uint32x2_t) __builtin_aarch64_reinterpretv2siv2sf (__a);
-+  return (uint32x2_t) __a;
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vreinterpret_u32_u8 (uint8x8_t __a)
- {
--  return (uint32x2_t) __builtin_aarch64_reinterpretv2siv8qi ((int8x8_t) __a);
-+  return (uint32x2_t) __a;
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vreinterpret_u32_u16 (uint16x4_t __a)
- {
--  return (uint32x2_t) __builtin_aarch64_reinterpretv2siv4hi ((int16x4_t) __a);
-+  return (uint32x2_t) __a;
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vreinterpret_u32_u64 (uint64x1_t __a)
- {
--  return (uint32x2_t) __builtin_aarch64_reinterpretv2sidi ((int64x1_t) __a);
-+  return (uint32x2_t) __a;
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vreinterpret_u32_p8 (poly8x8_t __a)
- {
--  return (uint32x2_t) __builtin_aarch64_reinterpretv2siv8qi ((int8x8_t) __a);
-+  return (uint32x2_t) __a;
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vreinterpret_u32_p16 (poly16x4_t __a)
- {
--  return (uint32x2_t) __builtin_aarch64_reinterpretv2siv4hi ((int16x4_t) __a);
-+  return (uint32x2_t) __a;
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
-+vreinterpretq_u32_f64 (float64x2_t __a)
-+{
-+  return (uint32x4_t) __a;
-+}
-+
-+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vreinterpretq_u32_s8 (int8x16_t __a)
- {
--  return (uint32x4_t) __builtin_aarch64_reinterpretv4siv16qi (__a);
-+  return (uint32x4_t) __a;
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vreinterpretq_u32_s16 (int16x8_t __a)
- {
--  return (uint32x4_t) __builtin_aarch64_reinterpretv4siv8hi (__a);
-+  return (uint32x4_t) __a;
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vreinterpretq_u32_s32 (int32x4_t __a)
- {
--  return (uint32x4_t) __builtin_aarch64_reinterpretv4siv4si (__a);
-+  return (uint32x4_t) __a;
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vreinterpretq_u32_s64 (int64x2_t __a)
- {
--  return (uint32x4_t) __builtin_aarch64_reinterpretv4siv2di (__a);
-+  return (uint32x4_t) __a;
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vreinterpretq_u32_f32 (float32x4_t __a)
- {
--  return (uint32x4_t) __builtin_aarch64_reinterpretv4siv4sf (__a);
-+  return (uint32x4_t) __a;
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vreinterpretq_u32_u8 (uint8x16_t __a)
- {
--  return (uint32x4_t) __builtin_aarch64_reinterpretv4siv16qi ((int8x16_t)
--							      __a);
-+  return (uint32x4_t) __a;
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vreinterpretq_u32_u16 (uint16x8_t __a)
- {
--  return (uint32x4_t) __builtin_aarch64_reinterpretv4siv8hi ((int16x8_t) __a);
-+  return (uint32x4_t) __a;
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vreinterpretq_u32_u64 (uint64x2_t __a)
- {
--  return (uint32x4_t) __builtin_aarch64_reinterpretv4siv2di ((int64x2_t) __a);
-+  return (uint32x4_t) __a;
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vreinterpretq_u32_p8 (poly8x16_t __a)
- {
--  return (uint32x4_t) __builtin_aarch64_reinterpretv4siv16qi ((int8x16_t)
--							      __a);
-+  return (uint32x4_t) __a;
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vreinterpretq_u32_p16 (poly16x8_t __a)
- {
--  return (uint32x4_t) __builtin_aarch64_reinterpretv4siv8hi ((int16x8_t) __a);
-+  return (uint32x4_t) __a;
- }
- 
- #define __GET_LOW(__TYPE) \
-@@ -4064,6 +4297,85 @@
- 
- #undef __GET_LOW
- 
-+#define __GET_HIGH(__TYPE)					\
-+  uint64x2_t tmp = vreinterpretq_u64_##__TYPE (__a);		\
-+  uint64x1_t hi = vcreate_u64 (vgetq_lane_u64 (tmp, 1));	\
-+  return vreinterpret_##__TYPE##_u64 (hi);
-+
-+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
-+vget_high_f32 (float32x4_t __a)
-+{
-+  __GET_HIGH (f32);
-+}
-+
-+__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
-+vget_high_f64 (float64x2_t __a)
-+{
-+  __GET_HIGH (f64);
-+}
-+
-+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
-+vget_high_p8 (poly8x16_t __a)
-+{
-+  __GET_HIGH (p8);
-+}
-+
-+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
-+vget_high_p16 (poly16x8_t __a)
-+{
-+  __GET_HIGH (p16);
-+}
-+
-+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
-+vget_high_s8 (int8x16_t __a)
-+{
-+  __GET_HIGH (s8);
-+}
-+
-+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
-+vget_high_s16 (int16x8_t __a)
-+{
-+  __GET_HIGH (s16);
-+}
-+
-+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
-+vget_high_s32 (int32x4_t __a)
-+{
-+  __GET_HIGH (s32);
-+}
-+
-+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
-+vget_high_s64 (int64x2_t __a)
-+{
-+  __GET_HIGH (s64);
-+}
-+
-+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
-+vget_high_u8 (uint8x16_t __a)
-+{
-+  __GET_HIGH (u8);
-+}
-+
-+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
-+vget_high_u16 (uint16x8_t __a)
-+{
-+  __GET_HIGH (u16);
-+}
-+
-+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
-+vget_high_u32 (uint32x4_t __a)
-+{
-+  __GET_HIGH (u32);
-+}
-+
-+#undef __GET_HIGH
-+
-+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
-+vget_high_u64 (uint64x2_t __a)
-+{
-+  return vcreate_u64 (vgetq_lane_u64 (__a, 1));
-+}
-+
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
- vcombine_s8 (int8x8_t __a, int8x8_t __b)
- {
-@@ -5408,318 +5720,6 @@
-   return result;
- }
- 
--#define vext_f32(a, b, c)                                               \
--  __extension__                                                         \
--    ({                                                                  \
--       float32x2_t b_ = (b);                                            \
--       float32x2_t a_ = (a);                                            \
--       float32x2_t result;                                              \
--       __asm__ ("ext %0.8b, %1.8b, %2.8b, #%3*4"                        \
--                : "=w"(result)                                          \
--                : "w"(a_), "w"(b_), "i"(c)                              \
--                : /* No clobbers */);                                   \
--       result;                                                          \
--     })
--
--#define vext_f64(a, b, c)                                               \
--  __extension__                                                         \
--    ({                                                                  \
--       float64x1_t b_ = (b);                                            \
--       float64x1_t a_ = (a);                                            \
--       float64x1_t result;                                              \
--       __asm__ ("ext %0.8b, %1.8b, %2.8b, #%3*8"                        \
--                : "=w"(result)                                          \
--                : "w"(a_), "w"(b_), "i"(c)                              \
--                : /* No clobbers */);                                   \
--       result;                                                          \
--     })
--
--#define vext_p8(a, b, c)                                                \
--  __extension__                                                         \
--    ({                                                                  \
--       poly8x8_t b_ = (b);                                              \
--       poly8x8_t a_ = (a);                                              \
--       poly8x8_t result;                                                \
--       __asm__ ("ext %0.8b,%1.8b,%2.8b,%3"                              \
--                : "=w"(result)                                          \
--                : "w"(a_), "w"(b_), "i"(c)                              \
--                : /* No clobbers */);                                   \
--       result;                                                          \
--     })
--
--#define vext_p16(a, b, c)                                               \
--  __extension__                                                         \
--    ({                                                                  \
--       poly16x4_t b_ = (b);                                             \
--       poly16x4_t a_ = (a);                                             \
--       poly16x4_t result;                                               \
--       __asm__ ("ext %0.8b, %1.8b, %2.8b, #%3*2"                        \
--                : "=w"(result)                                          \
--                : "w"(a_), "w"(b_), "i"(c)                              \
--                : /* No clobbers */);                                   \
--       result;                                                          \
--     })
--
--#define vext_s8(a, b, c)                                                \
--  __extension__                                                         \
--    ({                                                                  \
--       int8x8_t b_ = (b);                                               \
--       int8x8_t a_ = (a);                                               \
--       int8x8_t result;                                                 \
--       __asm__ ("ext %0.8b,%1.8b,%2.8b,%3"                              \
--                : "=w"(result)                                          \
--                : "w"(a_), "w"(b_), "i"(c)                              \
--                : /* No clobbers */);                                   \
--       result;                                                          \
--     })
--
--#define vext_s16(a, b, c)                                               \
--  __extension__                                                         \
--    ({                                                                  \
--       int16x4_t b_ = (b);                                              \
--       int16x4_t a_ = (a);                                              \
--       int16x4_t result;                                                \
--       __asm__ ("ext %0.8b, %1.8b, %2.8b, #%3*2"                        \
--                : "=w"(result)                                          \
--                : "w"(a_), "w"(b_), "i"(c)                              \
--                : /* No clobbers */);                                   \
--       result;                                                          \
--     })
--
--#define vext_s32(a, b, c)                                               \
--  __extension__                                                         \
--    ({                                                                  \
--       int32x2_t b_ = (b);                                              \
--       int32x2_t a_ = (a);                                              \
--       int32x2_t result;                                                \
--       __asm__ ("ext %0.8b, %1.8b, %2.8b, #%3*4"                        \
--                : "=w"(result)                                          \
--                : "w"(a_), "w"(b_), "i"(c)                              \
--                : /* No clobbers */);                                   \
--       result;                                                          \
--     })
--
--#define vext_s64(a, b, c)                                               \
--  __extension__                                                         \
--    ({                                                                  \
--       int64x1_t b_ = (b);                                              \
--       int64x1_t a_ = (a);                                              \
--       int64x1_t result;                                                \
--       __asm__ ("ext %0.8b, %1.8b, %2.8b, #%3*8"                        \
--                : "=w"(result)                                          \
--                : "w"(a_), "w"(b_), "i"(c)                              \
--                : /* No clobbers */);                                   \
--       result;                                                          \
--     })
--
--#define vext_u8(a, b, c)                                                \
--  __extension__                                                         \
--    ({                                                                  \
--       uint8x8_t b_ = (b);                                              \
--       uint8x8_t a_ = (a);                                              \
--       uint8x8_t result;                                                \
--       __asm__ ("ext %0.8b,%1.8b,%2.8b,%3"                              \
--                : "=w"(result)                                          \
--                : "w"(a_), "w"(b_), "i"(c)                              \
--                : /* No clobbers */);                                   \
--       result;                                                          \
--     })
--
--#define vext_u16(a, b, c)                                               \
--  __extension__                                                         \
--    ({                                                                  \
--       uint16x4_t b_ = (b);                                             \
--       uint16x4_t a_ = (a);                                             \
--       uint16x4_t result;                                               \
--       __asm__ ("ext %0.8b, %1.8b, %2.8b, #%3*2"                        \
--                : "=w"(result)                                          \
--                : "w"(a_), "w"(b_), "i"(c)                              \
--                : /* No clobbers */);                                   \
--       result;                                                          \
--     })
--
--#define vext_u32(a, b, c)                                               \
--  __extension__                                                         \
--    ({                                                                  \
--       uint32x2_t b_ = (b);                                             \
--       uint32x2_t a_ = (a);                                             \
--       uint32x2_t result;                                               \
--       __asm__ ("ext %0.8b, %1.8b, %2.8b, #%3*4"                        \
--                : "=w"(result)                                          \
--                : "w"(a_), "w"(b_), "i"(c)                              \
--                : /* No clobbers */);                                   \
--       result;                                                          \
--     })
--
--#define vext_u64(a, b, c)                                               \
--  __extension__                                                         \
--    ({                                                                  \
--       uint64x1_t b_ = (b);                                             \
--       uint64x1_t a_ = (a);                                             \
--       uint64x1_t result;                                               \
--       __asm__ ("ext %0.8b, %1.8b, %2.8b, #%3*8"                        \
--                : "=w"(result)                                          \
--                : "w"(a_), "w"(b_), "i"(c)                              \
--                : /* No clobbers */);                                   \
--       result;                                                          \
--     })
--
--#define vextq_f32(a, b, c)                                              \
--  __extension__                                                         \
--    ({                                                                  \
--       float32x4_t b_ = (b);                                            \
--       float32x4_t a_ = (a);                                            \
--       float32x4_t result;                                              \
--       __asm__ ("ext %0.16b, %1.16b, %2.16b, #%3*4"                     \
--                : "=w"(result)                                          \
--                : "w"(a_), "w"(b_), "i"(c)                              \
--                : /* No clobbers */);                                   \
--       result;                                                          \
--     })
--
--#define vextq_f64(a, b, c)                                              \
--  __extension__                                                         \
--    ({                                                                  \
--       float64x2_t b_ = (b);                                            \
--       float64x2_t a_ = (a);                                            \
--       float64x2_t result;                                              \
--       __asm__ ("ext %0.16b, %1.16b, %2.16b, #%3*8"                     \
--                : "=w"(result)                                          \
--                : "w"(a_), "w"(b_), "i"(c)                              \
--                : /* No clobbers */);                                   \
--       result;                                                          \
--     })
--
--#define vextq_p8(a, b, c)                                               \
--  __extension__                                                         \
--    ({                                                                  \
--       poly8x16_t b_ = (b);                                             \
--       poly8x16_t a_ = (a);                                             \
--       poly8x16_t result;                                               \
--       __asm__ ("ext %0.16b, %1.16b, %2.16b, #%3"                       \
--                : "=w"(result)                                          \
--                : "w"(a_), "w"(b_), "i"(c)                              \
--                : /* No clobbers */);                                   \
--       result;                                                          \
--     })
--
--#define vextq_p16(a, b, c)                                              \
--  __extension__                                                         \
--    ({                                                                  \
--       poly16x8_t b_ = (b);                                             \
--       poly16x8_t a_ = (a);                                             \
--       poly16x8_t result;                                               \
--       __asm__ ("ext %0.16b, %1.16b, %2.16b, #%3*2"                     \
--                : "=w"(result)                                          \
--                : "w"(a_), "w"(b_), "i"(c)                              \
--                : /* No clobbers */);                                   \
--       result;                                                          \
--     })
--
--#define vextq_s8(a, b, c)                                               \
--  __extension__                                                         \
--    ({                                                                  \
--       int8x16_t b_ = (b);                                              \
--       int8x16_t a_ = (a);                                              \
--       int8x16_t result;                                                \
--       __asm__ ("ext %0.16b, %1.16b, %2.16b, #%3"                       \
--                : "=w"(result)                                          \
--                : "w"(a_), "w"(b_), "i"(c)                              \
--                : /* No clobbers */);                                   \
--       result;                                                          \
--     })
--
--#define vextq_s16(a, b, c)                                              \
--  __extension__                                                         \
--    ({                                                                  \
--       int16x8_t b_ = (b);                                              \
--       int16x8_t a_ = (a);                                              \
--       int16x8_t result;                                                \
--       __asm__ ("ext %0.16b, %1.16b, %2.16b, #%3*2"                     \
--                : "=w"(result)                                          \
--                : "w"(a_), "w"(b_), "i"(c)                              \
--                : /* No clobbers */);                                   \
--       result;                                                          \
--     })
--
--#define vextq_s32(a, b, c)                                              \
--  __extension__                                                         \
--    ({                                                                  \
--       int32x4_t b_ = (b);                                              \
--       int32x4_t a_ = (a);                                              \
--       int32x4_t result;                                                \
--       __asm__ ("ext %0.16b, %1.16b, %2.16b, #%3*4"                     \
--                : "=w"(result)                                          \
--                : "w"(a_), "w"(b_), "i"(c)                              \
--                : /* No clobbers */);                                   \
--       result;                                                          \
--     })
--
--#define vextq_s64(a, b, c)                                              \
--  __extension__                                                         \
--    ({                                                                  \
--       int64x2_t b_ = (b);                                              \
--       int64x2_t a_ = (a);                                              \
--       int64x2_t result;                                                \
--       __asm__ ("ext %0.16b, %1.16b, %2.16b, #%3*8"                     \
--                : "=w"(result)                                          \
--                : "w"(a_), "w"(b_), "i"(c)                              \
--                : /* No clobbers */);                                   \
--       result;                                                          \
--     })
--
--#define vextq_u8(a, b, c)                                               \
--  __extension__                                                         \
--    ({                                                                  \
--       uint8x16_t b_ = (b);                                             \
--       uint8x16_t a_ = (a);                                             \
--       uint8x16_t result;                                               \
--       __asm__ ("ext %0.16b, %1.16b, %2.16b, #%3"                       \
--                : "=w"(result)                                          \
--                : "w"(a_), "w"(b_), "i"(c)                              \
--                : /* No clobbers */);                                   \
--       result;                                                          \
--     })
--
--#define vextq_u16(a, b, c)                                              \
--  __extension__                                                         \
--    ({                                                                  \
--       uint16x8_t b_ = (b);                                             \
--       uint16x8_t a_ = (a);                                             \
--       uint16x8_t result;                                               \
--       __asm__ ("ext %0.16b, %1.16b, %2.16b, #%3*2"                     \
--                : "=w"(result)                                          \
--                : "w"(a_), "w"(b_), "i"(c)                              \
--                : /* No clobbers */);                                   \
--       result;                                                          \
--     })
--
--#define vextq_u32(a, b, c)                                              \
--  __extension__                                                         \
--    ({                                                                  \
--       uint32x4_t b_ = (b);                                             \
--       uint32x4_t a_ = (a);                                             \
--       uint32x4_t result;                                               \
--       __asm__ ("ext %0.16b, %1.16b, %2.16b, #%3*4"                     \
--                : "=w"(result)                                          \
--                : "w"(a_), "w"(b_), "i"(c)                              \
--                : /* No clobbers */);                                   \
--       result;                                                          \
--     })
--
--#define vextq_u64(a, b, c)                                              \
--  __extension__                                                         \
--    ({                                                                  \
--       uint64x2_t b_ = (b);                                             \
--       uint64x2_t a_ = (a);                                             \
--       uint64x2_t result;                                               \
--       __asm__ ("ext %0.16b, %1.16b, %2.16b, #%3*8"                     \
--                : "=w"(result)                                          \
--                : "w"(a_), "w"(b_), "i"(c)                              \
--                : /* No clobbers */);                                   \
--       result;                                                          \
--     })
--
- __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
- vfma_f32 (float32x2_t a, float32x2_t b, float32x2_t c)
- {
-@@ -5819,139 +5819,7 @@
-   return result;
- }
- 
--__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
--vget_high_f32 (float32x4_t a)
--{
--  float32x2_t result;
--  __asm__ ("ins %0.d[0], %1.d[1]"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
--vget_high_f64 (float64x2_t a)
--{
--  float64x1_t result;
--  __asm__ ("ins %0.d[0], %1.d[1]"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
--vget_high_p8 (poly8x16_t a)
--{
--  poly8x8_t result;
--  __asm__ ("ins %0.d[0], %1.d[1]"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
--vget_high_p16 (poly16x8_t a)
--{
--  poly16x4_t result;
--  __asm__ ("ins %0.d[0], %1.d[1]"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
- __extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
--vget_high_s8 (int8x16_t a)
--{
--  int8x8_t result;
--  __asm__ ("ins %0.d[0], %1.d[1]"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
--vget_high_s16 (int16x8_t a)
--{
--  int16x4_t result;
--  __asm__ ("ins %0.d[0], %1.d[1]"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
--vget_high_s32 (int32x4_t a)
--{
--  int32x2_t result;
--  __asm__ ("ins %0.d[0], %1.d[1]"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
--vget_high_s64 (int64x2_t a)
--{
--  int64x1_t result;
--  __asm__ ("ins %0.d[0], %1.d[1]"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
--vget_high_u8 (uint8x16_t a)
--{
--  uint8x8_t result;
--  __asm__ ("ins %0.d[0], %1.d[1]"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
--vget_high_u16 (uint16x8_t a)
--{
--  uint16x4_t result;
--  __asm__ ("ins %0.d[0], %1.d[1]"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
--vget_high_u32 (uint32x4_t a)
--{
--  uint32x2_t result;
--  __asm__ ("ins %0.d[0], %1.d[1]"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
--vget_high_u64 (uint64x2_t a)
--{
--  uint64x1_t result;
--  __asm__ ("ins %0.d[0], %1.d[1]"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
- vhsub_s8 (int8x8_t a, int8x8_t b)
- {
-   int8x8_t result;
-@@ -6784,7 +6652,7 @@
- #define vmlal_high_lane_s16(a, b, c, d)                                 \
-   __extension__                                                         \
-     ({                                                                  \
--       int16x8_t c_ = (c);                                              \
-+       int16x4_t c_ = (c);                                              \
-        int16x8_t b_ = (b);                                              \
-        int32x4_t a_ = (a);                                              \
-        int32x4_t result;                                                \
-@@ -6798,7 +6666,7 @@
- #define vmlal_high_lane_s32(a, b, c, d)                                 \
-   __extension__                                                         \
-     ({                                                                  \
--       int32x4_t c_ = (c);                                              \
-+       int32x2_t c_ = (c);                                              \
-        int32x4_t b_ = (b);                                              \
-        int64x2_t a_ = (a);                                              \
-        int64x2_t result;                                                \
-@@ -6812,7 +6680,7 @@
- #define vmlal_high_lane_u16(a, b, c, d)                                 \
-   __extension__                                                         \
-     ({                                                                  \
--       uint16x8_t c_ = (c);                                             \
-+       uint16x4_t c_ = (c);                                             \
-        uint16x8_t b_ = (b);                                             \
-        uint32x4_t a_ = (a);                                             \
-        uint32x4_t result;                                               \
-@@ -6826,7 +6694,7 @@
- #define vmlal_high_lane_u32(a, b, c, d)                                 \
-   __extension__                                                         \
-     ({                                                                  \
--       uint32x4_t c_ = (c);                                             \
-+       uint32x2_t c_ = (c);                                             \
-        uint32x4_t b_ = (b);                                             \
-        uint64x2_t a_ = (a);                                             \
-        uint64x2_t result;                                               \
-@@ -7237,18 +7105,6 @@
-   return result;
- }
- 
--__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
--vmlaq_n_f64 (float64x2_t a, float64x2_t b, float64_t c)
--{
--  float64x2_t result;
--  float64x2_t t1;
--  __asm__ ("fmul %1.2d, %3.2d, %4.d[0]; fadd %0.2d, %0.2d, %1.2d"
--           : "=w"(result), "=w"(t1)
--           : "0"(a), "w"(b), "w"(c)
--           : /* No clobbers */);
--  return result;
--}
--
- __extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
- vmlaq_n_s16 (int16x8_t a, int16x8_t b, int16_t c)
- {
-@@ -7484,7 +7340,7 @@
- #define vmlsl_high_lane_s16(a, b, c, d)                                 \
-   __extension__                                                         \
-     ({                                                                  \
--       int16x8_t c_ = (c);                                              \
-+       int16x4_t c_ = (c);                                              \
-        int16x8_t b_ = (b);                                              \
-        int32x4_t a_ = (a);                                              \
-        int32x4_t result;                                                \
-@@ -7498,7 +7354,7 @@
- #define vmlsl_high_lane_s32(a, b, c, d)                                 \
-   __extension__                                                         \
-     ({                                                                  \
--       int32x4_t c_ = (c);                                              \
-+       int32x2_t c_ = (c);                                              \
-        int32x4_t b_ = (b);                                              \
-        int64x2_t a_ = (a);                                              \
-        int64x2_t result;                                                \
-@@ -7512,7 +7368,7 @@
- #define vmlsl_high_lane_u16(a, b, c, d)                                 \
-   __extension__                                                         \
-     ({                                                                  \
--       uint16x8_t c_ = (c);                                             \
-+       uint16x4_t c_ = (c);                                             \
-        uint16x8_t b_ = (b);                                             \
-        uint32x4_t a_ = (a);                                             \
-        uint32x4_t result;                                               \
-@@ -7526,7 +7382,7 @@
- #define vmlsl_high_lane_u32(a, b, c, d)                                 \
-   __extension__                                                         \
-     ({                                                                  \
--       uint32x4_t c_ = (c);                                             \
-+       uint32x2_t c_ = (c);                                             \
-        uint32x4_t b_ = (b);                                             \
-        uint64x2_t a_ = (a);                                             \
-        uint64x2_t result;                                               \
-@@ -7937,18 +7793,6 @@
-   return result;
- }
- 
--__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
--vmlsq_n_f64 (float64x2_t a, float64x2_t b, float64_t c)
--{
--  float64x2_t result;
--  float64x2_t t1;
--  __asm__ ("fmul %1.2d, %3.2d, %4.d[0]; fsub %0.2d, %0.2d, %1.2d"
--           : "=w"(result), "=w"(t1)
--           : "0"(a), "w"(b), "x"(c)
--           : /* No clobbers */);
--  return result;
--}
--
- __extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
- vmlsq_n_s16 (int16x8_t a, int16x8_t b, int16_t c)
- {
-@@ -9312,57 +9156,7 @@
-   return result;
- }
- 
--__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
--vpadd_s8 (int8x8_t __a, int8x8_t __b)
--{
--  return __builtin_aarch64_addpv8qi (__a, __b);
--}
--
- __extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
--vpadd_s16 (int16x4_t __a, int16x4_t __b)
--{
--  return __builtin_aarch64_addpv4hi (__a, __b);
--}
--
--__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
--vpadd_s32 (int32x2_t __a, int32x2_t __b)
--{
--  return __builtin_aarch64_addpv2si (__a, __b);
--}
--
--__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
--vpadd_u8 (uint8x8_t __a, uint8x8_t __b)
--{
--  return (uint8x8_t) __builtin_aarch64_addpv8qi ((int8x8_t) __a,
--						 (int8x8_t) __b);
--}
--
--__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
--vpadd_u16 (uint16x4_t __a, uint16x4_t __b)
--{
--  return (uint16x4_t) __builtin_aarch64_addpv4hi ((int16x4_t) __a,
--						  (int16x4_t) __b);
--}
--
--__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
--vpadd_u32 (uint32x2_t __a, uint32x2_t __b)
--{
--  return (uint32x2_t) __builtin_aarch64_addpv2si ((int32x2_t) __a,
--						  (int32x2_t) __b);
--}
--
--__extension__ static __inline float64_t __attribute__ ((__always_inline__))
--vpaddd_f64 (float64x2_t a)
--{
--  float64_t result;
--  __asm__ ("faddp %d0,%1.2d"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
- vpaddl_s8 (int8x8_t a)
- {
-   int16x4_t result;
-@@ -10556,50 +10350,6 @@
-        result;                                                          \
-      })
- 
--__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
--vrbit_s8 (int8x8_t a)
--{
--  int8x8_t result;
--  __asm__ ("rbit %0.8b,%1.8b"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
--vrbit_u8 (uint8x8_t a)
--{
--  uint8x8_t result;
--  __asm__ ("rbit %0.8b,%1.8b"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
--vrbitq_s8 (int8x16_t a)
--{
--  int8x16_t result;
--  __asm__ ("rbit %0.16b,%1.16b"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
--vrbitq_u8 (uint8x16_t a)
--{
--  uint8x16_t result;
--  __asm__ ("rbit %0.16b,%1.16b"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vrecpe_u32 (uint32x2_t a)
- {
-@@ -10622,402 +10372,6 @@
-   return result;
- }
- 
--__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
--vrev16_p8 (poly8x8_t a)
--{
--  poly8x8_t result;
--  __asm__ ("rev16 %0.8b,%1.8b"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
--vrev16_s8 (int8x8_t a)
--{
--  int8x8_t result;
--  __asm__ ("rev16 %0.8b,%1.8b"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
--vrev16_u8 (uint8x8_t a)
--{
--  uint8x8_t result;
--  __asm__ ("rev16 %0.8b,%1.8b"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
--vrev16q_p8 (poly8x16_t a)
--{
--  poly8x16_t result;
--  __asm__ ("rev16 %0.16b,%1.16b"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
--vrev16q_s8 (int8x16_t a)
--{
--  int8x16_t result;
--  __asm__ ("rev16 %0.16b,%1.16b"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
--vrev16q_u8 (uint8x16_t a)
--{
--  uint8x16_t result;
--  __asm__ ("rev16 %0.16b,%1.16b"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
--vrev32_p8 (poly8x8_t a)
--{
--  poly8x8_t result;
--  __asm__ ("rev32 %0.8b,%1.8b"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
--vrev32_p16 (poly16x4_t a)
--{
--  poly16x4_t result;
--  __asm__ ("rev32 %0.4h,%1.4h"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
--vrev32_s8 (int8x8_t a)
--{
--  int8x8_t result;
--  __asm__ ("rev32 %0.8b,%1.8b"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
--vrev32_s16 (int16x4_t a)
--{
--  int16x4_t result;
--  __asm__ ("rev32 %0.4h,%1.4h"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
--vrev32_u8 (uint8x8_t a)
--{
--  uint8x8_t result;
--  __asm__ ("rev32 %0.8b,%1.8b"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
--vrev32_u16 (uint16x4_t a)
--{
--  uint16x4_t result;
--  __asm__ ("rev32 %0.4h,%1.4h"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
--vrev32q_p8 (poly8x16_t a)
--{
--  poly8x16_t result;
--  __asm__ ("rev32 %0.16b,%1.16b"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
--vrev32q_p16 (poly16x8_t a)
--{
--  poly16x8_t result;
--  __asm__ ("rev32 %0.8h,%1.8h"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
--vrev32q_s8 (int8x16_t a)
--{
--  int8x16_t result;
--  __asm__ ("rev32 %0.16b,%1.16b"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
--vrev32q_s16 (int16x8_t a)
--{
--  int16x8_t result;
--  __asm__ ("rev32 %0.8h,%1.8h"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
--vrev32q_u8 (uint8x16_t a)
--{
--  uint8x16_t result;
--  __asm__ ("rev32 %0.16b,%1.16b"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
--vrev32q_u16 (uint16x8_t a)
--{
--  uint16x8_t result;
--  __asm__ ("rev32 %0.8h,%1.8h"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
--vrev64_f32 (float32x2_t a)
--{
--  float32x2_t result;
--  __asm__ ("rev64 %0.2s,%1.2s"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
--vrev64_p8 (poly8x8_t a)
--{
--  poly8x8_t result;
--  __asm__ ("rev64 %0.8b,%1.8b"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
--vrev64_p16 (poly16x4_t a)
--{
--  poly16x4_t result;
--  __asm__ ("rev64 %0.4h,%1.4h"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
--vrev64_s8 (int8x8_t a)
--{
--  int8x8_t result;
--  __asm__ ("rev64 %0.8b,%1.8b"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
--vrev64_s16 (int16x4_t a)
--{
--  int16x4_t result;
--  __asm__ ("rev64 %0.4h,%1.4h"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
--vrev64_s32 (int32x2_t a)
--{
--  int32x2_t result;
--  __asm__ ("rev64 %0.2s,%1.2s"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
--vrev64_u8 (uint8x8_t a)
--{
--  uint8x8_t result;
--  __asm__ ("rev64 %0.8b,%1.8b"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
--vrev64_u16 (uint16x4_t a)
--{
--  uint16x4_t result;
--  __asm__ ("rev64 %0.4h,%1.4h"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
--vrev64_u32 (uint32x2_t a)
--{
--  uint32x2_t result;
--  __asm__ ("rev64 %0.2s,%1.2s"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
--vrev64q_f32 (float32x4_t a)
--{
--  float32x4_t result;
--  __asm__ ("rev64 %0.4s,%1.4s"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
--vrev64q_p8 (poly8x16_t a)
--{
--  poly8x16_t result;
--  __asm__ ("rev64 %0.16b,%1.16b"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
--vrev64q_p16 (poly16x8_t a)
--{
--  poly16x8_t result;
--  __asm__ ("rev64 %0.8h,%1.8h"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
--vrev64q_s8 (int8x16_t a)
--{
--  int8x16_t result;
--  __asm__ ("rev64 %0.16b,%1.16b"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
--vrev64q_s16 (int16x8_t a)
--{
--  int16x8_t result;
--  __asm__ ("rev64 %0.8h,%1.8h"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
--vrev64q_s32 (int32x4_t a)
--{
--  int32x4_t result;
--  __asm__ ("rev64 %0.4s,%1.4s"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
--vrev64q_u8 (uint8x16_t a)
--{
--  uint8x16_t result;
--  __asm__ ("rev64 %0.16b,%1.16b"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
--vrev64q_u16 (uint16x8_t a)
--{
--  uint16x8_t result;
--  __asm__ ("rev64 %0.8h,%1.8h"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
--vrev64q_u32 (uint32x4_t a)
--{
--  uint32x4_t result;
--  __asm__ ("rev64 %0.4s,%1.4s"
--           : "=w"(result)
--           : "w"(a)
--           : /* No clobbers */);
--  return result;
--}
--
- #define vrshrn_high_n_s16(a, b, c)                                      \
-   __extension__                                                         \
-     ({                                                                  \
-@@ -11323,17 +10677,6 @@
-   return result;
- }
- 
--__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
--vrsrtsq_f64 (float64x2_t a, float64x2_t b)
--{
--  float64x2_t result;
--  __asm__ ("frsqrts %0.2d,%1.2d,%2.2d"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
- vrsubhn_high_s16 (int8x8_t a, int16x8_t b, int16x8_t c)
- {
-@@ -12441,469 +11784,7 @@
-   return result;
- }
- 
--__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
--vtrn1_f32 (float32x2_t a, float32x2_t b)
--{
--  float32x2_t result;
--  __asm__ ("trn1 %0.2s,%1.2s,%2.2s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
--vtrn1_p8 (poly8x8_t a, poly8x8_t b)
--{
--  poly8x8_t result;
--  __asm__ ("trn1 %0.8b,%1.8b,%2.8b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
--vtrn1_p16 (poly16x4_t a, poly16x4_t b)
--{
--  poly16x4_t result;
--  __asm__ ("trn1 %0.4h,%1.4h,%2.4h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
--vtrn1_s8 (int8x8_t a, int8x8_t b)
--{
--  int8x8_t result;
--  __asm__ ("trn1 %0.8b,%1.8b,%2.8b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
--vtrn1_s16 (int16x4_t a, int16x4_t b)
--{
--  int16x4_t result;
--  __asm__ ("trn1 %0.4h,%1.4h,%2.4h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
--vtrn1_s32 (int32x2_t a, int32x2_t b)
--{
--  int32x2_t result;
--  __asm__ ("trn1 %0.2s,%1.2s,%2.2s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
--vtrn1_u8 (uint8x8_t a, uint8x8_t b)
--{
--  uint8x8_t result;
--  __asm__ ("trn1 %0.8b,%1.8b,%2.8b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
--vtrn1_u16 (uint16x4_t a, uint16x4_t b)
--{
--  uint16x4_t result;
--  __asm__ ("trn1 %0.4h,%1.4h,%2.4h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
--vtrn1_u32 (uint32x2_t a, uint32x2_t b)
--{
--  uint32x2_t result;
--  __asm__ ("trn1 %0.2s,%1.2s,%2.2s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
--vtrn1q_f32 (float32x4_t a, float32x4_t b)
--{
--  float32x4_t result;
--  __asm__ ("trn1 %0.4s,%1.4s,%2.4s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
--vtrn1q_f64 (float64x2_t a, float64x2_t b)
--{
--  float64x2_t result;
--  __asm__ ("trn1 %0.2d,%1.2d,%2.2d"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
--vtrn1q_p8 (poly8x16_t a, poly8x16_t b)
--{
--  poly8x16_t result;
--  __asm__ ("trn1 %0.16b,%1.16b,%2.16b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
--vtrn1q_p16 (poly16x8_t a, poly16x8_t b)
--{
--  poly16x8_t result;
--  __asm__ ("trn1 %0.8h,%1.8h,%2.8h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
--vtrn1q_s8 (int8x16_t a, int8x16_t b)
--{
--  int8x16_t result;
--  __asm__ ("trn1 %0.16b,%1.16b,%2.16b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
--vtrn1q_s16 (int16x8_t a, int16x8_t b)
--{
--  int16x8_t result;
--  __asm__ ("trn1 %0.8h,%1.8h,%2.8h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
--vtrn1q_s32 (int32x4_t a, int32x4_t b)
--{
--  int32x4_t result;
--  __asm__ ("trn1 %0.4s,%1.4s,%2.4s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
--vtrn1q_s64 (int64x2_t a, int64x2_t b)
--{
--  int64x2_t result;
--  __asm__ ("trn1 %0.2d,%1.2d,%2.2d"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
--vtrn1q_u8 (uint8x16_t a, uint8x16_t b)
--{
--  uint8x16_t result;
--  __asm__ ("trn1 %0.16b,%1.16b,%2.16b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
--vtrn1q_u16 (uint16x8_t a, uint16x8_t b)
--{
--  uint16x8_t result;
--  __asm__ ("trn1 %0.8h,%1.8h,%2.8h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
--vtrn1q_u32 (uint32x4_t a, uint32x4_t b)
--{
--  uint32x4_t result;
--  __asm__ ("trn1 %0.4s,%1.4s,%2.4s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
--vtrn1q_u64 (uint64x2_t a, uint64x2_t b)
--{
--  uint64x2_t result;
--  __asm__ ("trn1 %0.2d,%1.2d,%2.2d"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
--vtrn2_f32 (float32x2_t a, float32x2_t b)
--{
--  float32x2_t result;
--  __asm__ ("trn2 %0.2s,%1.2s,%2.2s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
--vtrn2_p8 (poly8x8_t a, poly8x8_t b)
--{
--  poly8x8_t result;
--  __asm__ ("trn2 %0.8b,%1.8b,%2.8b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
--vtrn2_p16 (poly16x4_t a, poly16x4_t b)
--{
--  poly16x4_t result;
--  __asm__ ("trn2 %0.4h,%1.4h,%2.4h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
--vtrn2_s8 (int8x8_t a, int8x8_t b)
--{
--  int8x8_t result;
--  __asm__ ("trn2 %0.8b,%1.8b,%2.8b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
--vtrn2_s16 (int16x4_t a, int16x4_t b)
--{
--  int16x4_t result;
--  __asm__ ("trn2 %0.4h,%1.4h,%2.4h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
--vtrn2_s32 (int32x2_t a, int32x2_t b)
--{
--  int32x2_t result;
--  __asm__ ("trn2 %0.2s,%1.2s,%2.2s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
--vtrn2_u8 (uint8x8_t a, uint8x8_t b)
--{
--  uint8x8_t result;
--  __asm__ ("trn2 %0.8b,%1.8b,%2.8b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
--vtrn2_u16 (uint16x4_t a, uint16x4_t b)
--{
--  uint16x4_t result;
--  __asm__ ("trn2 %0.4h,%1.4h,%2.4h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
--vtrn2_u32 (uint32x2_t a, uint32x2_t b)
--{
--  uint32x2_t result;
--  __asm__ ("trn2 %0.2s,%1.2s,%2.2s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
--vtrn2q_f32 (float32x4_t a, float32x4_t b)
--{
--  float32x4_t result;
--  __asm__ ("trn2 %0.4s,%1.4s,%2.4s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
--vtrn2q_f64 (float64x2_t a, float64x2_t b)
--{
--  float64x2_t result;
--  __asm__ ("trn2 %0.2d,%1.2d,%2.2d"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
--vtrn2q_p8 (poly8x16_t a, poly8x16_t b)
--{
--  poly8x16_t result;
--  __asm__ ("trn2 %0.16b,%1.16b,%2.16b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
--vtrn2q_p16 (poly16x8_t a, poly16x8_t b)
--{
--  poly16x8_t result;
--  __asm__ ("trn2 %0.8h,%1.8h,%2.8h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
--vtrn2q_s8 (int8x16_t a, int8x16_t b)
--{
--  int8x16_t result;
--  __asm__ ("trn2 %0.16b,%1.16b,%2.16b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
--vtrn2q_s16 (int16x8_t a, int16x8_t b)
--{
--  int16x8_t result;
--  __asm__ ("trn2 %0.8h,%1.8h,%2.8h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
--vtrn2q_s32 (int32x4_t a, int32x4_t b)
--{
--  int32x4_t result;
--  __asm__ ("trn2 %0.4s,%1.4s,%2.4s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
--vtrn2q_s64 (int64x2_t a, int64x2_t b)
--{
--  int64x2_t result;
--  __asm__ ("trn2 %0.2d,%1.2d,%2.2d"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
--vtrn2q_u8 (uint8x16_t a, uint8x16_t b)
--{
--  uint8x16_t result;
--  __asm__ ("trn2 %0.16b,%1.16b,%2.16b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
--vtrn2q_u16 (uint16x8_t a, uint16x8_t b)
--{
--  uint16x8_t result;
--  __asm__ ("trn2 %0.8h,%1.8h,%2.8h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
--vtrn2q_u32 (uint32x4_t a, uint32x4_t b)
--{
--  uint32x4_t result;
--  __asm__ ("trn2 %0.4s,%1.4s,%2.4s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
--vtrn2q_u64 (uint64x2_t a, uint64x2_t b)
--{
--  uint64x2_t result;
--  __asm__ ("trn2 %0.2d,%1.2d,%2.2d"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vtst_p8 (poly8x8_t a, poly8x8_t b)
- {
-   uint8x8_t result;
-@@ -12946,930 +11827,7 @@
-            : /* No clobbers */);
-   return result;
- }
--__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
--vuzp1_f32 (float32x2_t a, float32x2_t b)
--{
--  float32x2_t result;
--  __asm__ ("uzp1 %0.2s,%1.2s,%2.2s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
- 
--__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
--vuzp1_p8 (poly8x8_t a, poly8x8_t b)
--{
--  poly8x8_t result;
--  __asm__ ("uzp1 %0.8b,%1.8b,%2.8b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
--vuzp1_p16 (poly16x4_t a, poly16x4_t b)
--{
--  poly16x4_t result;
--  __asm__ ("uzp1 %0.4h,%1.4h,%2.4h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
--vuzp1_s8 (int8x8_t a, int8x8_t b)
--{
--  int8x8_t result;
--  __asm__ ("uzp1 %0.8b,%1.8b,%2.8b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
--vuzp1_s16 (int16x4_t a, int16x4_t b)
--{
--  int16x4_t result;
--  __asm__ ("uzp1 %0.4h,%1.4h,%2.4h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
--vuzp1_s32 (int32x2_t a, int32x2_t b)
--{
--  int32x2_t result;
--  __asm__ ("uzp1 %0.2s,%1.2s,%2.2s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
--vuzp1_u8 (uint8x8_t a, uint8x8_t b)
--{
--  uint8x8_t result;
--  __asm__ ("uzp1 %0.8b,%1.8b,%2.8b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
--vuzp1_u16 (uint16x4_t a, uint16x4_t b)
--{
--  uint16x4_t result;
--  __asm__ ("uzp1 %0.4h,%1.4h,%2.4h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
--vuzp1_u32 (uint32x2_t a, uint32x2_t b)
--{
--  uint32x2_t result;
--  __asm__ ("uzp1 %0.2s,%1.2s,%2.2s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
--vuzp1q_f32 (float32x4_t a, float32x4_t b)
--{
--  float32x4_t result;
--  __asm__ ("uzp1 %0.4s,%1.4s,%2.4s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
--vuzp1q_f64 (float64x2_t a, float64x2_t b)
--{
--  float64x2_t result;
--  __asm__ ("uzp1 %0.2d,%1.2d,%2.2d"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
--vuzp1q_p8 (poly8x16_t a, poly8x16_t b)
--{
--  poly8x16_t result;
--  __asm__ ("uzp1 %0.16b,%1.16b,%2.16b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
--vuzp1q_p16 (poly16x8_t a, poly16x8_t b)
--{
--  poly16x8_t result;
--  __asm__ ("uzp1 %0.8h,%1.8h,%2.8h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
--vuzp1q_s8 (int8x16_t a, int8x16_t b)
--{
--  int8x16_t result;
--  __asm__ ("uzp1 %0.16b,%1.16b,%2.16b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
--vuzp1q_s16 (int16x8_t a, int16x8_t b)
--{
--  int16x8_t result;
--  __asm__ ("uzp1 %0.8h,%1.8h,%2.8h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
--vuzp1q_s32 (int32x4_t a, int32x4_t b)
--{
--  int32x4_t result;
--  __asm__ ("uzp1 %0.4s,%1.4s,%2.4s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
--vuzp1q_s64 (int64x2_t a, int64x2_t b)
--{
--  int64x2_t result;
--  __asm__ ("uzp1 %0.2d,%1.2d,%2.2d"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
--vuzp1q_u8 (uint8x16_t a, uint8x16_t b)
--{
--  uint8x16_t result;
--  __asm__ ("uzp1 %0.16b,%1.16b,%2.16b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
--vuzp1q_u16 (uint16x8_t a, uint16x8_t b)
--{
--  uint16x8_t result;
--  __asm__ ("uzp1 %0.8h,%1.8h,%2.8h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
--vuzp1q_u32 (uint32x4_t a, uint32x4_t b)
--{
--  uint32x4_t result;
--  __asm__ ("uzp1 %0.4s,%1.4s,%2.4s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
--vuzp1q_u64 (uint64x2_t a, uint64x2_t b)
--{
--  uint64x2_t result;
--  __asm__ ("uzp1 %0.2d,%1.2d,%2.2d"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
--vuzp2_f32 (float32x2_t a, float32x2_t b)
--{
--  float32x2_t result;
--  __asm__ ("uzp2 %0.2s,%1.2s,%2.2s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
--vuzp2_p8 (poly8x8_t a, poly8x8_t b)
--{
--  poly8x8_t result;
--  __asm__ ("uzp2 %0.8b,%1.8b,%2.8b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
--vuzp2_p16 (poly16x4_t a, poly16x4_t b)
--{
--  poly16x4_t result;
--  __asm__ ("uzp2 %0.4h,%1.4h,%2.4h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
--vuzp2_s8 (int8x8_t a, int8x8_t b)
--{
--  int8x8_t result;
--  __asm__ ("uzp2 %0.8b,%1.8b,%2.8b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
--vuzp2_s16 (int16x4_t a, int16x4_t b)
--{
--  int16x4_t result;
--  __asm__ ("uzp2 %0.4h,%1.4h,%2.4h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
--vuzp2_s32 (int32x2_t a, int32x2_t b)
--{
--  int32x2_t result;
--  __asm__ ("uzp2 %0.2s,%1.2s,%2.2s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
--vuzp2_u8 (uint8x8_t a, uint8x8_t b)
--{
--  uint8x8_t result;
--  __asm__ ("uzp2 %0.8b,%1.8b,%2.8b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
--vuzp2_u16 (uint16x4_t a, uint16x4_t b)
--{
--  uint16x4_t result;
--  __asm__ ("uzp2 %0.4h,%1.4h,%2.4h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
--vuzp2_u32 (uint32x2_t a, uint32x2_t b)
--{
--  uint32x2_t result;
--  __asm__ ("uzp2 %0.2s,%1.2s,%2.2s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
--vuzp2q_f32 (float32x4_t a, float32x4_t b)
--{
--  float32x4_t result;
--  __asm__ ("uzp2 %0.4s,%1.4s,%2.4s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
--vuzp2q_f64 (float64x2_t a, float64x2_t b)
--{
--  float64x2_t result;
--  __asm__ ("uzp2 %0.2d,%1.2d,%2.2d"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
--vuzp2q_p8 (poly8x16_t a, poly8x16_t b)
--{
--  poly8x16_t result;
--  __asm__ ("uzp2 %0.16b,%1.16b,%2.16b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
--vuzp2q_p16 (poly16x8_t a, poly16x8_t b)
--{
--  poly16x8_t result;
--  __asm__ ("uzp2 %0.8h,%1.8h,%2.8h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
--vuzp2q_s8 (int8x16_t a, int8x16_t b)
--{
--  int8x16_t result;
--  __asm__ ("uzp2 %0.16b,%1.16b,%2.16b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
--vuzp2q_s16 (int16x8_t a, int16x8_t b)
--{
--  int16x8_t result;
--  __asm__ ("uzp2 %0.8h,%1.8h,%2.8h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
--vuzp2q_s32 (int32x4_t a, int32x4_t b)
--{
--  int32x4_t result;
--  __asm__ ("uzp2 %0.4s,%1.4s,%2.4s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
--vuzp2q_s64 (int64x2_t a, int64x2_t b)
--{
--  int64x2_t result;
--  __asm__ ("uzp2 %0.2d,%1.2d,%2.2d"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
--vuzp2q_u8 (uint8x16_t a, uint8x16_t b)
--{
--  uint8x16_t result;
--  __asm__ ("uzp2 %0.16b,%1.16b,%2.16b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
--vuzp2q_u16 (uint16x8_t a, uint16x8_t b)
--{
--  uint16x8_t result;
--  __asm__ ("uzp2 %0.8h,%1.8h,%2.8h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
--vuzp2q_u32 (uint32x4_t a, uint32x4_t b)
--{
--  uint32x4_t result;
--  __asm__ ("uzp2 %0.4s,%1.4s,%2.4s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
--vuzp2q_u64 (uint64x2_t a, uint64x2_t b)
--{
--  uint64x2_t result;
--  __asm__ ("uzp2 %0.2d,%1.2d,%2.2d"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
--vzip1_f32 (float32x2_t a, float32x2_t b)
--{
--  float32x2_t result;
--  __asm__ ("zip1 %0.2s,%1.2s,%2.2s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
--vzip1_p8 (poly8x8_t a, poly8x8_t b)
--{
--  poly8x8_t result;
--  __asm__ ("zip1 %0.8b,%1.8b,%2.8b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
--vzip1_p16 (poly16x4_t a, poly16x4_t b)
--{
--  poly16x4_t result;
--  __asm__ ("zip1 %0.4h,%1.4h,%2.4h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
--vzip1_s8 (int8x8_t a, int8x8_t b)
--{
--  int8x8_t result;
--  __asm__ ("zip1 %0.8b,%1.8b,%2.8b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
--vzip1_s16 (int16x4_t a, int16x4_t b)
--{
--  int16x4_t result;
--  __asm__ ("zip1 %0.4h,%1.4h,%2.4h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
--vzip1_s32 (int32x2_t a, int32x2_t b)
--{
--  int32x2_t result;
--  __asm__ ("zip1 %0.2s,%1.2s,%2.2s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
--vzip1_u8 (uint8x8_t a, uint8x8_t b)
--{
--  uint8x8_t result;
--  __asm__ ("zip1 %0.8b,%1.8b,%2.8b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
--vzip1_u16 (uint16x4_t a, uint16x4_t b)
--{
--  uint16x4_t result;
--  __asm__ ("zip1 %0.4h,%1.4h,%2.4h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
--vzip1_u32 (uint32x2_t a, uint32x2_t b)
--{
--  uint32x2_t result;
--  __asm__ ("zip1 %0.2s,%1.2s,%2.2s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
--vzip1q_f32 (float32x4_t a, float32x4_t b)
--{
--  float32x4_t result;
--  __asm__ ("zip1 %0.4s,%1.4s,%2.4s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
--vzip1q_f64 (float64x2_t a, float64x2_t b)
--{
--  float64x2_t result;
--  __asm__ ("zip1 %0.2d,%1.2d,%2.2d"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
--vzip1q_p8 (poly8x16_t a, poly8x16_t b)
--{
--  poly8x16_t result;
--  __asm__ ("zip1 %0.16b,%1.16b,%2.16b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
--vzip1q_p16 (poly16x8_t a, poly16x8_t b)
--{
--  poly16x8_t result;
--  __asm__ ("zip1 %0.8h,%1.8h,%2.8h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
--vzip1q_s8 (int8x16_t a, int8x16_t b)
--{
--  int8x16_t result;
--  __asm__ ("zip1 %0.16b,%1.16b,%2.16b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
--vzip1q_s16 (int16x8_t a, int16x8_t b)
--{
--  int16x8_t result;
--  __asm__ ("zip1 %0.8h,%1.8h,%2.8h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
--vzip1q_s32 (int32x4_t a, int32x4_t b)
--{
--  int32x4_t result;
--  __asm__ ("zip1 %0.4s,%1.4s,%2.4s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
--vzip1q_s64 (int64x2_t a, int64x2_t b)
--{
--  int64x2_t result;
--  __asm__ ("zip1 %0.2d,%1.2d,%2.2d"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
--vzip1q_u8 (uint8x16_t a, uint8x16_t b)
--{
--  uint8x16_t result;
--  __asm__ ("zip1 %0.16b,%1.16b,%2.16b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
--vzip1q_u16 (uint16x8_t a, uint16x8_t b)
--{
--  uint16x8_t result;
--  __asm__ ("zip1 %0.8h,%1.8h,%2.8h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
--vzip1q_u32 (uint32x4_t a, uint32x4_t b)
--{
--  uint32x4_t result;
--  __asm__ ("zip1 %0.4s,%1.4s,%2.4s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
--vzip1q_u64 (uint64x2_t a, uint64x2_t b)
--{
--  uint64x2_t result;
--  __asm__ ("zip1 %0.2d,%1.2d,%2.2d"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
--vzip2_f32 (float32x2_t a, float32x2_t b)
--{
--  float32x2_t result;
--  __asm__ ("zip2 %0.2s,%1.2s,%2.2s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
--vzip2_p8 (poly8x8_t a, poly8x8_t b)
--{
--  poly8x8_t result;
--  __asm__ ("zip2 %0.8b,%1.8b,%2.8b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
--vzip2_p16 (poly16x4_t a, poly16x4_t b)
--{
--  poly16x4_t result;
--  __asm__ ("zip2 %0.4h,%1.4h,%2.4h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
--vzip2_s8 (int8x8_t a, int8x8_t b)
--{
--  int8x8_t result;
--  __asm__ ("zip2 %0.8b,%1.8b,%2.8b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
--vzip2_s16 (int16x4_t a, int16x4_t b)
--{
--  int16x4_t result;
--  __asm__ ("zip2 %0.4h,%1.4h,%2.4h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
--vzip2_s32 (int32x2_t a, int32x2_t b)
--{
--  int32x2_t result;
--  __asm__ ("zip2 %0.2s,%1.2s,%2.2s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
--vzip2_u8 (uint8x8_t a, uint8x8_t b)
--{
--  uint8x8_t result;
--  __asm__ ("zip2 %0.8b,%1.8b,%2.8b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
--vzip2_u16 (uint16x4_t a, uint16x4_t b)
--{
--  uint16x4_t result;
--  __asm__ ("zip2 %0.4h,%1.4h,%2.4h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
--vzip2_u32 (uint32x2_t a, uint32x2_t b)
--{
--  uint32x2_t result;
--  __asm__ ("zip2 %0.2s,%1.2s,%2.2s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
--vzip2q_f32 (float32x4_t a, float32x4_t b)
--{
--  float32x4_t result;
--  __asm__ ("zip2 %0.4s,%1.4s,%2.4s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
--vzip2q_f64 (float64x2_t a, float64x2_t b)
--{
--  float64x2_t result;
--  __asm__ ("zip2 %0.2d,%1.2d,%2.2d"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
--vzip2q_p8 (poly8x16_t a, poly8x16_t b)
--{
--  poly8x16_t result;
--  __asm__ ("zip2 %0.16b,%1.16b,%2.16b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
--vzip2q_p16 (poly16x8_t a, poly16x8_t b)
--{
--  poly16x8_t result;
--  __asm__ ("zip2 %0.8h,%1.8h,%2.8h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
--vzip2q_s8 (int8x16_t a, int8x16_t b)
--{
--  int8x16_t result;
--  __asm__ ("zip2 %0.16b,%1.16b,%2.16b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
--vzip2q_s16 (int16x8_t a, int16x8_t b)
--{
--  int16x8_t result;
--  __asm__ ("zip2 %0.8h,%1.8h,%2.8h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
--vzip2q_s32 (int32x4_t a, int32x4_t b)
--{
--  int32x4_t result;
--  __asm__ ("zip2 %0.4s,%1.4s,%2.4s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
--vzip2q_s64 (int64x2_t a, int64x2_t b)
--{
--  int64x2_t result;
--  __asm__ ("zip2 %0.2d,%1.2d,%2.2d"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
--vzip2q_u8 (uint8x16_t a, uint8x16_t b)
--{
--  uint8x16_t result;
--  __asm__ ("zip2 %0.16b,%1.16b,%2.16b"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
--vzip2q_u16 (uint16x8_t a, uint16x8_t b)
--{
--  uint16x8_t result;
--  __asm__ ("zip2 %0.8h,%1.8h,%2.8h"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
--vzip2q_u32 (uint32x4_t a, uint32x4_t b)
--{
--  uint32x4_t result;
--  __asm__ ("zip2 %0.4s,%1.4s,%2.4s"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
--__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
--vzip2q_u64 (uint64x2_t a, uint64x2_t b)
--{
--  uint64x2_t result;
--  __asm__ ("zip2 %0.2d,%1.2d,%2.2d"
--           : "=w"(result)
--           : "w"(a), "w"(b)
--           : /* No clobbers */);
--  return result;
--}
--
- /* End of temporary inline asm implementations.  */
- 
- /* Start of temporary inline asm for vldn, vstn and friends.  */
-@@ -13953,46 +11911,6 @@
- __STRUCTN (float, 64, 4)
- #undef __STRUCTN
- 
--#define __LD2R_FUNC(rettype, structtype, ptrtype,			\
--		    regsuffix, funcsuffix, Q)				\
--  __extension__ static __inline rettype					\
--  __attribute__ ((__always_inline__)) 					\
--  vld2 ## Q ## _dup_ ## funcsuffix (const ptrtype *ptr)			\
--  {									\
--    rettype result;							\
--    __asm__ ("ld2r {v16." #regsuffix ", v17." #regsuffix "}, %1\n\t"	\
--	     "st1 {v16." #regsuffix ", v17." #regsuffix "}, %0\n\t"	\
--	     : "=Q"(result)						\
--	     : "Q"(*(const structtype *)ptr)				\
--	     : "memory", "v16", "v17");					\
--    return result;							\
--  }
--
--__LD2R_FUNC (float32x2x2_t, float32x2_t, float32_t, 2s, f32,)
--__LD2R_FUNC (float64x1x2_t, float64x2_t, float64_t, 1d, f64,)
--__LD2R_FUNC (poly8x8x2_t, poly8x2_t, poly8_t, 8b, p8,)
--__LD2R_FUNC (poly16x4x2_t, poly16x2_t, poly16_t, 4h, p16,)
--__LD2R_FUNC (int8x8x2_t, int8x2_t, int8_t, 8b, s8,)
--__LD2R_FUNC (int16x4x2_t, int16x2_t, int16_t, 4h, s16,)
--__LD2R_FUNC (int32x2x2_t, int32x2_t, int32_t, 2s, s32,)
--__LD2R_FUNC (int64x1x2_t, int64x2_t, int64_t, 1d, s64,)
--__LD2R_FUNC (uint8x8x2_t, uint8x2_t, uint8_t, 8b, u8,)
--__LD2R_FUNC (uint16x4x2_t, uint16x2_t, uint16_t, 4h, u16,)
--__LD2R_FUNC (uint32x2x2_t, uint32x2_t, uint32_t, 2s, u32,)
--__LD2R_FUNC (uint64x1x2_t, uint64x2_t, uint64_t, 1d, u64,)
--__LD2R_FUNC (float32x4x2_t, float32x2_t, float32_t, 4s, f32, q)
--__LD2R_FUNC (float64x2x2_t, float64x2_t, float64_t, 2d, f64, q)
--__LD2R_FUNC (poly8x16x2_t, poly8x2_t, poly8_t, 16b, p8, q)
--__LD2R_FUNC (poly16x8x2_t, poly16x2_t, poly16_t, 8h, p16, q)
--__LD2R_FUNC (int8x16x2_t, int8x2_t, int8_t, 16b, s8, q)
--__LD2R_FUNC (int16x8x2_t, int16x2_t, int16_t, 8h, s16, q)
--__LD2R_FUNC (int32x4x2_t, int32x2_t, int32_t, 4s, s32, q)
--__LD2R_FUNC (int64x2x2_t, int64x2_t, int64_t, 2d, s64, q)
--__LD2R_FUNC (uint8x16x2_t, uint8x2_t, uint8_t, 16b, u8, q)
--__LD2R_FUNC (uint16x8x2_t, uint16x2_t, uint16_t, 8h, u16, q)
--__LD2R_FUNC (uint32x4x2_t, uint32x2_t, uint32_t, 4s, u32, q)
--__LD2R_FUNC (uint64x2x2_t, uint64x2_t, uint64_t, 2d, u64, q)
--
- #define __LD2_LANE_FUNC(rettype, ptrtype, regsuffix,			\
- 			lnsuffix, funcsuffix, Q)			\
-   __extension__ static __inline rettype					\
-@@ -14035,46 +11953,6 @@
- __LD2_LANE_FUNC (uint32x4x2_t, uint32_t, 4s, s, u32, q)
- __LD2_LANE_FUNC (uint64x2x2_t, uint64_t, 2d, d, u64, q)
- 
--#define __LD3R_FUNC(rettype, structtype, ptrtype,			\
--		    regsuffix, funcsuffix, Q)				\
--  __extension__ static __inline rettype					\
--  __attribute__ ((__always_inline__))					\
--  vld3 ## Q ## _dup_ ## funcsuffix (const ptrtype *ptr)			\
--  {									\
--    rettype result;							\
--    __asm__ ("ld3r {v16." #regsuffix " - v18." #regsuffix "}, %1\n\t"	\
--	     "st1 {v16." #regsuffix " - v18." #regsuffix "}, %0\n\t"	\
--	     : "=Q"(result)						\
--	     : "Q"(*(const structtype *)ptr)				\
--	     : "memory", "v16", "v17", "v18");				\
--    return result;							\
--  }
--
--__LD3R_FUNC (float32x2x3_t, float32x3_t, float32_t, 2s, f32,)
--__LD3R_FUNC (float64x1x3_t, float64x3_t, float64_t, 1d, f64,)
--__LD3R_FUNC (poly8x8x3_t, poly8x3_t, poly8_t, 8b, p8,)
--__LD3R_FUNC (poly16x4x3_t, poly16x3_t, poly16_t, 4h, p16,)
--__LD3R_FUNC (int8x8x3_t, int8x3_t, int8_t, 8b, s8,)
--__LD3R_FUNC (int16x4x3_t, int16x3_t, int16_t, 4h, s16,)
--__LD3R_FUNC (int32x2x3_t, int32x3_t, int32_t, 2s, s32,)
--__LD3R_FUNC (int64x1x3_t, int64x3_t, int64_t, 1d, s64,)
--__LD3R_FUNC (uint8x8x3_t, uint8x3_t, uint8_t, 8b, u8,)
--__LD3R_FUNC (uint16x4x3_t, uint16x3_t, uint16_t, 4h, u16,)
--__LD3R_FUNC (uint32x2x3_t, uint32x3_t, uint32_t, 2s, u32,)
--__LD3R_FUNC (uint64x1x3_t, uint64x3_t, uint64_t, 1d, u64,)
--__LD3R_FUNC (float32x4x3_t, float32x3_t, float32_t, 4s, f32, q)
--__LD3R_FUNC (float64x2x3_t, float64x3_t, float64_t, 2d, f64, q)
--__LD3R_FUNC (poly8x16x3_t, poly8x3_t, poly8_t, 16b, p8, q)
--__LD3R_FUNC (poly16x8x3_t, poly16x3_t, poly16_t, 8h, p16, q)
--__LD3R_FUNC (int8x16x3_t, int8x3_t, int8_t, 16b, s8, q)
--__LD3R_FUNC (int16x8x3_t, int16x3_t, int16_t, 8h, s16, q)
--__LD3R_FUNC (int32x4x3_t, int32x3_t, int32_t, 4s, s32, q)
--__LD3R_FUNC (int64x2x3_t, int64x3_t, int64_t, 2d, s64, q)
--__LD3R_FUNC (uint8x16x3_t, uint8x3_t, uint8_t, 16b, u8, q)
--__LD3R_FUNC (uint16x8x3_t, uint16x3_t, uint16_t, 8h, u16, q)
--__LD3R_FUNC (uint32x4x3_t, uint32x3_t, uint32_t, 4s, u32, q)
--__LD3R_FUNC (uint64x2x3_t, uint64x3_t, uint64_t, 2d, u64, q)
--
- #define __LD3_LANE_FUNC(rettype, ptrtype, regsuffix,			\
- 			lnsuffix, funcsuffix, Q)			\
-   __extension__ static __inline rettype					\
-@@ -14117,46 +11995,6 @@
- __LD3_LANE_FUNC (uint32x4x3_t, uint32_t, 4s, s, u32, q)
- __LD3_LANE_FUNC (uint64x2x3_t, uint64_t, 2d, d, u64, q)
- 
--#define __LD4R_FUNC(rettype, structtype, ptrtype,			\
--		    regsuffix, funcsuffix, Q)				\
--  __extension__ static __inline rettype					\
--  __attribute__ ((__always_inline__))					\
--  vld4 ## Q ## _dup_ ## funcsuffix (const ptrtype *ptr)			\
--  {									\
--    rettype result;							\
--    __asm__ ("ld4r {v16." #regsuffix " - v19." #regsuffix "}, %1\n\t"	\
--	     "st1 {v16." #regsuffix " - v19." #regsuffix "}, %0\n\t"	\
--	     : "=Q"(result)						\
--	     : "Q"(*(const structtype *)ptr)				\
--	     : "memory", "v16", "v17", "v18", "v19");			\
--    return result;							\
--  }
--
--__LD4R_FUNC (float32x2x4_t, float32x4_t, float32_t, 2s, f32,)
--__LD4R_FUNC (float64x1x4_t, float64x4_t, float64_t, 1d, f64,)
--__LD4R_FUNC (poly8x8x4_t, poly8x4_t, poly8_t, 8b, p8,)
--__LD4R_FUNC (poly16x4x4_t, poly16x4_t, poly16_t, 4h, p16,)
--__LD4R_FUNC (int8x8x4_t, int8x4_t, int8_t, 8b, s8,)
--__LD4R_FUNC (int16x4x4_t, int16x4_t, int16_t, 4h, s16,)
--__LD4R_FUNC (int32x2x4_t, int32x4_t, int32_t, 2s, s32,)
--__LD4R_FUNC (int64x1x4_t, int64x4_t, int64_t, 1d, s64,)
--__LD4R_FUNC (uint8x8x4_t, uint8x4_t, uint8_t, 8b, u8,)
--__LD4R_FUNC (uint16x4x4_t, uint16x4_t, uint16_t, 4h, u16,)
--__LD4R_FUNC (uint32x2x4_t, uint32x4_t, uint32_t, 2s, u32,)
--__LD4R_FUNC (uint64x1x4_t, uint64x4_t, uint64_t, 1d, u64,)
--__LD4R_FUNC (float32x4x4_t, float32x4_t, float32_t, 4s, f32, q)
--__LD4R_FUNC (float64x2x4_t, float64x4_t, float64_t, 2d, f64, q)
--__LD4R_FUNC (poly8x16x4_t, poly8x4_t, poly8_t, 16b, p8, q)
--__LD4R_FUNC (poly16x8x4_t, poly16x4_t, poly16_t, 8h, p16, q)
--__LD4R_FUNC (int8x16x4_t, int8x4_t, int8_t, 16b, s8, q)
--__LD4R_FUNC (int16x8x4_t, int16x4_t, int16_t, 8h, s16, q)
--__LD4R_FUNC (int32x4x4_t, int32x4_t, int32_t, 4s, s32, q)
--__LD4R_FUNC (int64x2x4_t, int64x4_t, int64_t, 2d, s64, q)
--__LD4R_FUNC (uint8x16x4_t, uint8x4_t, uint8_t, 16b, u8, q)
--__LD4R_FUNC (uint16x8x4_t, uint16x4_t, uint16_t, 8h, u16, q)
--__LD4R_FUNC (uint32x4x4_t, uint32x4_t, uint32_t, 4s, u32, q)
--__LD4R_FUNC (uint64x2x4_t, uint64x4_t, uint64_t, 2d, u64, q)
--
- #define __LD4_LANE_FUNC(rettype, ptrtype, regsuffix,			\
- 			lnsuffix, funcsuffix, Q)			\
-   __extension__ static __inline rettype					\
-@@ -14199,132 +12037,225 @@
- __LD4_LANE_FUNC (uint32x4x4_t, uint32_t, 4s, s, u32, q)
- __LD4_LANE_FUNC (uint64x2x4_t, uint64_t, 2d, d, u64, q)
- 
--#define __ST2_LANE_FUNC(intype, ptrtype, regsuffix,			\
--			lnsuffix, funcsuffix, Q)			\
--  typedef struct { ptrtype __x[2]; } __ST2_LANE_STRUCTURE_##intype;	\
--  __extension__ static __inline void					\
--  __attribute__ ((__always_inline__))					\
--  vst2 ## Q ## _lane_ ## funcsuffix (ptrtype *ptr,			\
--				     intype b, const int c)		\
--  {									\
--    __ST2_LANE_STRUCTURE_##intype *__p =				\
--				(__ST2_LANE_STRUCTURE_##intype *)ptr;	\
--    __asm__ ("ld1 {v16." #regsuffix ", v17." #regsuffix "}, %1\n\t"	\
--	     "st2 {v16." #lnsuffix ", v17." #lnsuffix "}[%2], %0\n\t"	\
--	     : "=Q"(*__p)						\
--	     : "Q"(b), "i"(c)						\
--	     : "v16", "v17");						\
--  }
-+#define __ST2_LANE_FUNC(intype, largetype, ptrtype,			     \
-+			mode, ptr_mode, funcsuffix, signedtype)		     \
-+__extension__ static __inline void					     \
-+__attribute__ ((__always_inline__))					     \
-+vst2_lane_ ## funcsuffix (ptrtype *__ptr,				     \
-+			  intype __b, const int __c)			     \
-+{									     \
-+  __builtin_aarch64_simd_oi __o;					     \
-+  largetype __temp;							     \
-+  __temp.val[0]								     \
-+    = vcombine_##funcsuffix (__b.val[0],				     \
-+			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
-+  __temp.val[1]								     \
-+    = vcombine_##funcsuffix (__b.val[1],				     \
-+			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
-+  __o = __builtin_aarch64_set_qregoi##mode (__o,			     \
-+					    (signedtype) __temp.val[0], 0);  \
-+  __o = __builtin_aarch64_set_qregoi##mode (__o,			     \
-+					    (signedtype) __temp.val[1], 1);  \
-+  __builtin_aarch64_st2_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *)  \
-+				     __ptr, __o, __c);			     \
-+}
- 
--__ST2_LANE_FUNC (int8x8x2_t, int8_t, 8b, b, s8,)
--__ST2_LANE_FUNC (float32x2x2_t, float32_t, 2s, s, f32,)
--__ST2_LANE_FUNC (float64x1x2_t, float64_t, 1d, d, f64,)
--__ST2_LANE_FUNC (poly8x8x2_t, poly8_t, 8b, b, p8,)
--__ST2_LANE_FUNC (poly16x4x2_t, poly16_t, 4h, h, p16,)
--__ST2_LANE_FUNC (int16x4x2_t, int16_t, 4h, h, s16,)
--__ST2_LANE_FUNC (int32x2x2_t, int32_t, 2s, s, s32,)
--__ST2_LANE_FUNC (int64x1x2_t, int64_t, 1d, d, s64,)
--__ST2_LANE_FUNC (uint8x8x2_t, uint8_t, 8b, b, u8,)
--__ST2_LANE_FUNC (uint16x4x2_t, uint16_t, 4h, h, u16,)
--__ST2_LANE_FUNC (uint32x2x2_t, uint32_t, 2s, s, u32,)
--__ST2_LANE_FUNC (uint64x1x2_t, uint64_t, 1d, d, u64,)
--__ST2_LANE_FUNC (float32x4x2_t, float32_t, 4s, s, f32, q)
--__ST2_LANE_FUNC (float64x2x2_t, float64_t, 2d, d, f64, q)
--__ST2_LANE_FUNC (poly8x16x2_t, poly8_t, 16b, b, p8, q)
--__ST2_LANE_FUNC (poly16x8x2_t, poly16_t, 8h, h, p16, q)
--__ST2_LANE_FUNC (int8x16x2_t, int8_t, 16b, b, s8, q)
--__ST2_LANE_FUNC (int16x8x2_t, int16_t, 8h, h, s16, q)
--__ST2_LANE_FUNC (int32x4x2_t, int32_t, 4s, s, s32, q)
--__ST2_LANE_FUNC (int64x2x2_t, int64_t, 2d, d, s64, q)
--__ST2_LANE_FUNC (uint8x16x2_t, uint8_t, 16b, b, u8, q)
--__ST2_LANE_FUNC (uint16x8x2_t, uint16_t, 8h, h, u16, q)
--__ST2_LANE_FUNC (uint32x4x2_t, uint32_t, 4s, s, u32, q)
--__ST2_LANE_FUNC (uint64x2x2_t, uint64_t, 2d, d, u64, q)
-+__ST2_LANE_FUNC (float32x2x2_t, float32x4x2_t, float32_t, v4sf, sf, f32,
-+		 float32x4_t)
-+__ST2_LANE_FUNC (float64x1x2_t, float64x2x2_t, float64_t, v2df, df, f64,
-+		 float64x2_t)
-+__ST2_LANE_FUNC (poly8x8x2_t, poly8x16x2_t, poly8_t, v16qi, qi, p8, int8x16_t)
-+__ST2_LANE_FUNC (poly16x4x2_t, poly16x8x2_t, poly16_t, v8hi, hi, p16,
-+		 int16x8_t)
-+__ST2_LANE_FUNC (int8x8x2_t, int8x16x2_t, int8_t, v16qi, qi, s8, int8x16_t)
-+__ST2_LANE_FUNC (int16x4x2_t, int16x8x2_t, int16_t, v8hi, hi, s16, int16x8_t)
-+__ST2_LANE_FUNC (int32x2x2_t, int32x4x2_t, int32_t, v4si, si, s32, int32x4_t)
-+__ST2_LANE_FUNC (int64x1x2_t, int64x2x2_t, int64_t, v2di, di, s64, int64x2_t)
-+__ST2_LANE_FUNC (uint8x8x2_t, uint8x16x2_t, uint8_t, v16qi, qi, u8, int8x16_t)
-+__ST2_LANE_FUNC (uint16x4x2_t, uint16x8x2_t, uint16_t, v8hi, hi, u16,
-+		 int16x8_t)
-+__ST2_LANE_FUNC (uint32x2x2_t, uint32x4x2_t, uint32_t, v4si, si, u32,
-+		 int32x4_t)
-+__ST2_LANE_FUNC (uint64x1x2_t, uint64x2x2_t, uint64_t, v2di, di, u64,
-+		 int64x2_t)
- 
--#define __ST3_LANE_FUNC(intype, ptrtype, regsuffix,			\
--			lnsuffix, funcsuffix, Q)			\
--  typedef struct { ptrtype __x[3]; } __ST3_LANE_STRUCTURE_##intype;	\
--  __extension__ static __inline void					\
--  __attribute__ ((__always_inline__))					\
--  vst3 ## Q ## _lane_ ## funcsuffix (ptrtype *ptr,			\
--				     intype b, const int c)		\
--  {									\
--    __ST3_LANE_STRUCTURE_##intype *__p =				\
--				(__ST3_LANE_STRUCTURE_##intype *)ptr;	\
--    __asm__ ("ld1 {v16." #regsuffix " - v18." #regsuffix "}, %1\n\t"	\
--	     "st3 {v16." #lnsuffix " - v18." #lnsuffix "}[%2], %0\n\t"	\
--	     : "=Q"(*__p)						\
--	     : "Q"(b), "i"(c)						\
--	     : "v16", "v17", "v18");					\
--  }
-+#undef __ST2_LANE_FUNC
-+#define __ST2_LANE_FUNC(intype, ptrtype, mode, ptr_mode, funcsuffix)	    \
-+__extension__ static __inline void					    \
-+__attribute__ ((__always_inline__))					    \
-+vst2q_lane_ ## funcsuffix (ptrtype *__ptr,				    \
-+			   intype __b, const int __c)			    \
-+{									    \
-+  union { intype __i;							    \
-+	  __builtin_aarch64_simd_oi __o; } __temp = { __b };		    \
-+  __builtin_aarch64_st2_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *) \
-+				    __ptr, __temp.__o, __c);		    \
-+}
- 
--__ST3_LANE_FUNC (int8x8x3_t, int8_t, 8b, b, s8,)
--__ST3_LANE_FUNC (float32x2x3_t, float32_t, 2s, s, f32,)
--__ST3_LANE_FUNC (float64x1x3_t, float64_t, 1d, d, f64,)
--__ST3_LANE_FUNC (poly8x8x3_t, poly8_t, 8b, b, p8,)
--__ST3_LANE_FUNC (poly16x4x3_t, poly16_t, 4h, h, p16,)
--__ST3_LANE_FUNC (int16x4x3_t, int16_t, 4h, h, s16,)
--__ST3_LANE_FUNC (int32x2x3_t, int32_t, 2s, s, s32,)
--__ST3_LANE_FUNC (int64x1x3_t, int64_t, 1d, d, s64,)
--__ST3_LANE_FUNC (uint8x8x3_t, uint8_t, 8b, b, u8,)
--__ST3_LANE_FUNC (uint16x4x3_t, uint16_t, 4h, h, u16,)
--__ST3_LANE_FUNC (uint32x2x3_t, uint32_t, 2s, s, u32,)
--__ST3_LANE_FUNC (uint64x1x3_t, uint64_t, 1d, d, u64,)
--__ST3_LANE_FUNC (float32x4x3_t, float32_t, 4s, s, f32, q)
--__ST3_LANE_FUNC (float64x2x3_t, float64_t, 2d, d, f64, q)
--__ST3_LANE_FUNC (poly8x16x3_t, poly8_t, 16b, b, p8, q)
--__ST3_LANE_FUNC (poly16x8x3_t, poly16_t, 8h, h, p16, q)
--__ST3_LANE_FUNC (int8x16x3_t, int8_t, 16b, b, s8, q)
--__ST3_LANE_FUNC (int16x8x3_t, int16_t, 8h, h, s16, q)
--__ST3_LANE_FUNC (int32x4x3_t, int32_t, 4s, s, s32, q)
--__ST3_LANE_FUNC (int64x2x3_t, int64_t, 2d, d, s64, q)
--__ST3_LANE_FUNC (uint8x16x3_t, uint8_t, 16b, b, u8, q)
--__ST3_LANE_FUNC (uint16x8x3_t, uint16_t, 8h, h, u16, q)
--__ST3_LANE_FUNC (uint32x4x3_t, uint32_t, 4s, s, u32, q)
--__ST3_LANE_FUNC (uint64x2x3_t, uint64_t, 2d, d, u64, q)
-+__ST2_LANE_FUNC (float32x4x2_t, float32_t, v4sf, sf, f32)
-+__ST2_LANE_FUNC (float64x2x2_t, float64_t, v2df, df, f64)
-+__ST2_LANE_FUNC (poly8x16x2_t, poly8_t, v16qi, qi, p8)
-+__ST2_LANE_FUNC (poly16x8x2_t, poly16_t, v8hi, hi, p16)
-+__ST2_LANE_FUNC (int8x16x2_t, int8_t, v16qi, qi, s8)
-+__ST2_LANE_FUNC (int16x8x2_t, int16_t, v8hi, hi, s16)
-+__ST2_LANE_FUNC (int32x4x2_t, int32_t, v4si, si, s32)
-+__ST2_LANE_FUNC (int64x2x2_t, int64_t, v2di, di, s64)
-+__ST2_LANE_FUNC (uint8x16x2_t, uint8_t, v16qi, qi, u8)
-+__ST2_LANE_FUNC (uint16x8x2_t, uint16_t, v8hi, hi, u16)
-+__ST2_LANE_FUNC (uint32x4x2_t, uint32_t, v4si, si, u32)
-+__ST2_LANE_FUNC (uint64x2x2_t, uint64_t, v2di, di, u64)
- 
--#define __ST4_LANE_FUNC(intype, ptrtype, regsuffix,			\
--			lnsuffix, funcsuffix, Q)			\
--  typedef struct { ptrtype __x[4]; } __ST4_LANE_STRUCTURE_##intype;	\
--  __extension__ static __inline void					\
--  __attribute__ ((__always_inline__))					\
--  vst4 ## Q ## _lane_ ## funcsuffix (ptrtype *ptr,			\
--				     intype b, const int c)		\
--  {									\
--    __ST4_LANE_STRUCTURE_##intype *__p =				\
--				(__ST4_LANE_STRUCTURE_##intype *)ptr;	\
--    __asm__ ("ld1 {v16." #regsuffix " - v19." #regsuffix "}, %1\n\t"	\
--	     "st4 {v16." #lnsuffix " - v19." #lnsuffix "}[%2], %0\n\t"	\
--	     : "=Q"(*__p)						\
--	     : "Q"(b), "i"(c)						\
--	     : "v16", "v17", "v18", "v19");				\
--  }
-+#define __ST3_LANE_FUNC(intype, largetype, ptrtype,			     \
-+			mode, ptr_mode, funcsuffix, signedtype)		     \
-+__extension__ static __inline void					     \
-+__attribute__ ((__always_inline__))					     \
-+vst3_lane_ ## funcsuffix (ptrtype *__ptr,				     \
-+			  intype __b, const int __c)			     \
-+{									     \
-+  __builtin_aarch64_simd_ci __o;					     \
-+  largetype __temp;							     \
-+  __temp.val[0]								     \
-+    = vcombine_##funcsuffix (__b.val[0],				     \
-+			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
-+  __temp.val[1]								     \
-+    = vcombine_##funcsuffix (__b.val[1],				     \
-+			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
-+  __temp.val[2]								     \
-+    = vcombine_##funcsuffix (__b.val[2],				     \
-+			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
-+  __o = __builtin_aarch64_set_qregci##mode (__o,			     \
-+					    (signedtype) __temp.val[0], 0);  \
-+  __o = __builtin_aarch64_set_qregci##mode (__o,			     \
-+					    (signedtype) __temp.val[1], 1);  \
-+  __o = __builtin_aarch64_set_qregci##mode (__o,			     \
-+					    (signedtype) __temp.val[2], 2);  \
-+  __builtin_aarch64_st3_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *)  \
-+				     __ptr, __o, __c);			     \
-+}
- 
--__ST4_LANE_FUNC (int8x8x4_t, int8_t, 8b, b, s8,)
--__ST4_LANE_FUNC (float32x2x4_t, float32_t, 2s, s, f32,)
--__ST4_LANE_FUNC (float64x1x4_t, float64_t, 1d, d, f64,)
--__ST4_LANE_FUNC (poly8x8x4_t, poly8_t, 8b, b, p8,)
--__ST4_LANE_FUNC (poly16x4x4_t, poly16_t, 4h, h, p16,)
--__ST4_LANE_FUNC (int16x4x4_t, int16_t, 4h, h, s16,)
--__ST4_LANE_FUNC (int32x2x4_t, int32_t, 2s, s, s32,)
--__ST4_LANE_FUNC (int64x1x4_t, int64_t, 1d, d, s64,)
--__ST4_LANE_FUNC (uint8x8x4_t, uint8_t, 8b, b, u8,)
--__ST4_LANE_FUNC (uint16x4x4_t, uint16_t, 4h, h, u16,)
--__ST4_LANE_FUNC (uint32x2x4_t, uint32_t, 2s, s, u32,)
--__ST4_LANE_FUNC (uint64x1x4_t, uint64_t, 1d, d, u64,)
--__ST4_LANE_FUNC (float32x4x4_t, float32_t, 4s, s, f32, q)
--__ST4_LANE_FUNC (float64x2x4_t, float64_t, 2d, d, f64, q)
--__ST4_LANE_FUNC (poly8x16x4_t, poly8_t, 16b, b, p8, q)
--__ST4_LANE_FUNC (poly16x8x4_t, poly16_t, 8h, h, p16, q)
--__ST4_LANE_FUNC (int8x16x4_t, int8_t, 16b, b, s8, q)
--__ST4_LANE_FUNC (int16x8x4_t, int16_t, 8h, h, s16, q)
--__ST4_LANE_FUNC (int32x4x4_t, int32_t, 4s, s, s32, q)
--__ST4_LANE_FUNC (int64x2x4_t, int64_t, 2d, d, s64, q)
--__ST4_LANE_FUNC (uint8x16x4_t, uint8_t, 16b, b, u8, q)
--__ST4_LANE_FUNC (uint16x8x4_t, uint16_t, 8h, h, u16, q)
--__ST4_LANE_FUNC (uint32x4x4_t, uint32_t, 4s, s, u32, q)
--__ST4_LANE_FUNC (uint64x2x4_t, uint64_t, 2d, d, u64, q)
-+__ST3_LANE_FUNC (float32x2x3_t, float32x4x3_t, float32_t, v4sf, sf, f32,
-+		 float32x4_t)
-+__ST3_LANE_FUNC (float64x1x3_t, float64x2x3_t, float64_t, v2df, df, f64,
-+		 float64x2_t)
-+__ST3_LANE_FUNC (poly8x8x3_t, poly8x16x3_t, poly8_t, v16qi, qi, p8, int8x16_t)
-+__ST3_LANE_FUNC (poly16x4x3_t, poly16x8x3_t, poly16_t, v8hi, hi, p16,
-+		 int16x8_t)
-+__ST3_LANE_FUNC (int8x8x3_t, int8x16x3_t, int8_t, v16qi, qi, s8, int8x16_t)
-+__ST3_LANE_FUNC (int16x4x3_t, int16x8x3_t, int16_t, v8hi, hi, s16, int16x8_t)
-+__ST3_LANE_FUNC (int32x2x3_t, int32x4x3_t, int32_t, v4si, si, s32, int32x4_t)
-+__ST3_LANE_FUNC (int64x1x3_t, int64x2x3_t, int64_t, v2di, di, s64, int64x2_t)
-+__ST3_LANE_FUNC (uint8x8x3_t, uint8x16x3_t, uint8_t, v16qi, qi, u8, int8x16_t)
-+__ST3_LANE_FUNC (uint16x4x3_t, uint16x8x3_t, uint16_t, v8hi, hi, u16,
-+		 int16x8_t)
-+__ST3_LANE_FUNC (uint32x2x3_t, uint32x4x3_t, uint32_t, v4si, si, u32,
-+		 int32x4_t)
-+__ST3_LANE_FUNC (uint64x1x3_t, uint64x2x3_t, uint64_t, v2di, di, u64,
-+		 int64x2_t)
- 
-+#undef __ST3_LANE_FUNC
-+#define __ST3_LANE_FUNC(intype, ptrtype, mode, ptr_mode, funcsuffix)	    \
-+__extension__ static __inline void					    \
-+__attribute__ ((__always_inline__))					    \
-+vst3q_lane_ ## funcsuffix (ptrtype *__ptr,				    \
-+			   intype __b, const int __c)			    \
-+{									    \
-+  union { intype __i;							    \
-+	  __builtin_aarch64_simd_ci __o; } __temp = { __b };		    \
-+  __builtin_aarch64_st3_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *) \
-+				    __ptr, __temp.__o, __c);		    \
-+}
-+
-+__ST3_LANE_FUNC (float32x4x3_t, float32_t, v4sf, sf, f32)
-+__ST3_LANE_FUNC (float64x2x3_t, float64_t, v2df, df, f64)
-+__ST3_LANE_FUNC (poly8x16x3_t, poly8_t, v16qi, qi, p8)
-+__ST3_LANE_FUNC (poly16x8x3_t, poly16_t, v8hi, hi, p16)
-+__ST3_LANE_FUNC (int8x16x3_t, int8_t, v16qi, qi, s8)
-+__ST3_LANE_FUNC (int16x8x3_t, int16_t, v8hi, hi, s16)
-+__ST3_LANE_FUNC (int32x4x3_t, int32_t, v4si, si, s32)
-+__ST3_LANE_FUNC (int64x2x3_t, int64_t, v2di, di, s64)
-+__ST3_LANE_FUNC (uint8x16x3_t, uint8_t, v16qi, qi, u8)
-+__ST3_LANE_FUNC (uint16x8x3_t, uint16_t, v8hi, hi, u16)
-+__ST3_LANE_FUNC (uint32x4x3_t, uint32_t, v4si, si, u32)
-+__ST3_LANE_FUNC (uint64x2x3_t, uint64_t, v2di, di, u64)
-+
-+#define __ST4_LANE_FUNC(intype, largetype, ptrtype,			     \
-+			mode, ptr_mode, funcsuffix, signedtype)		     \
-+__extension__ static __inline void					     \
-+__attribute__ ((__always_inline__))					     \
-+vst4_lane_ ## funcsuffix (ptrtype *__ptr,				     \
-+			  intype __b, const int __c)			     \
-+{									     \
-+  __builtin_aarch64_simd_xi __o;					     \
-+  largetype __temp;							     \
-+  __temp.val[0]								     \
-+    = vcombine_##funcsuffix (__b.val[0],				     \
-+			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
-+  __temp.val[1]								     \
-+    = vcombine_##funcsuffix (__b.val[1],				     \
-+			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
-+  __temp.val[2]								     \
-+    = vcombine_##funcsuffix (__b.val[2],				     \
-+			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
-+  __temp.val[3]								     \
-+    = vcombine_##funcsuffix (__b.val[3],				     \
-+			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
-+  __o = __builtin_aarch64_set_qregxi##mode (__o,			     \
-+					    (signedtype) __temp.val[0], 0);  \
-+  __o = __builtin_aarch64_set_qregxi##mode (__o,			     \
-+					    (signedtype) __temp.val[1], 1);  \
-+  __o = __builtin_aarch64_set_qregxi##mode (__o,			     \
-+					    (signedtype) __temp.val[2], 2);  \
-+  __o = __builtin_aarch64_set_qregxi##mode (__o,			     \
-+					    (signedtype) __temp.val[3], 3);  \
-+  __builtin_aarch64_st4_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *)  \
-+				     __ptr, __o, __c);			     \
-+}
-+
-+__ST4_LANE_FUNC (float32x2x4_t, float32x4x4_t, float32_t, v4sf, sf, f32,
-+		 float32x4_t)
-+__ST4_LANE_FUNC (float64x1x4_t, float64x2x4_t, float64_t, v2df, df, f64,
-+		 float64x2_t)
-+__ST4_LANE_FUNC (poly8x8x4_t, poly8x16x4_t, poly8_t, v16qi, qi, p8, int8x16_t)
-+__ST4_LANE_FUNC (poly16x4x4_t, poly16x8x4_t, poly16_t, v8hi, hi, p16,
-+		 int16x8_t)
-+__ST4_LANE_FUNC (int8x8x4_t, int8x16x4_t, int8_t, v16qi, qi, s8, int8x16_t)
-+__ST4_LANE_FUNC (int16x4x4_t, int16x8x4_t, int16_t, v8hi, hi, s16, int16x8_t)
-+__ST4_LANE_FUNC (int32x2x4_t, int32x4x4_t, int32_t, v4si, si, s32, int32x4_t)
-+__ST4_LANE_FUNC (int64x1x4_t, int64x2x4_t, int64_t, v2di, di, s64, int64x2_t)
-+__ST4_LANE_FUNC (uint8x8x4_t, uint8x16x4_t, uint8_t, v16qi, qi, u8, int8x16_t)
-+__ST4_LANE_FUNC (uint16x4x4_t, uint16x8x4_t, uint16_t, v8hi, hi, u16,
-+		 int16x8_t)
-+__ST4_LANE_FUNC (uint32x2x4_t, uint32x4x4_t, uint32_t, v4si, si, u32,
-+		 int32x4_t)
-+__ST4_LANE_FUNC (uint64x1x4_t, uint64x2x4_t, uint64_t, v2di, di, u64,
-+		 int64x2_t)
-+
-+#undef __ST4_LANE_FUNC
-+#define __ST4_LANE_FUNC(intype, ptrtype, mode, ptr_mode, funcsuffix)	    \
-+__extension__ static __inline void					    \
-+__attribute__ ((__always_inline__))					    \
-+vst4q_lane_ ## funcsuffix (ptrtype *__ptr,				    \
-+			   intype __b, const int __c)			    \
-+{									    \
-+  union { intype __i;							    \
-+	  __builtin_aarch64_simd_xi __o; } __temp = { __b };		    \
-+  __builtin_aarch64_st4_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *) \
-+				    __ptr, __temp.__o, __c);		    \
-+}
-+
-+__ST4_LANE_FUNC (float32x4x4_t, float32_t, v4sf, sf, f32)
-+__ST4_LANE_FUNC (float64x2x4_t, float64_t, v2df, df, f64)
-+__ST4_LANE_FUNC (poly8x16x4_t, poly8_t, v16qi, qi, p8)
-+__ST4_LANE_FUNC (poly16x8x4_t, poly16_t, v8hi, hi, p16)
-+__ST4_LANE_FUNC (int8x16x4_t, int8_t, v16qi, qi, s8)
-+__ST4_LANE_FUNC (int16x8x4_t, int16_t, v8hi, hi, s16)
-+__ST4_LANE_FUNC (int32x4x4_t, int32_t, v4si, si, s32)
-+__ST4_LANE_FUNC (int64x2x4_t, int64_t, v2di, di, s64)
-+__ST4_LANE_FUNC (uint8x16x4_t, uint8_t, v16qi, qi, u8)
-+__ST4_LANE_FUNC (uint16x8x4_t, uint16_t, v8hi, hi, u16)
-+__ST4_LANE_FUNC (uint32x4x4_t, uint32_t, v4si, si, u32)
-+__ST4_LANE_FUNC (uint64x2x4_t, uint64_t, v2di, di, u64)
-+
- __extension__ static __inline int64_t __attribute__ ((__always_inline__))
- vaddlv_s32 (int32x2_t a)
- {
-@@ -14341,12 +12272,6 @@
-   return result;
- }
- 
--__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
--vpaddd_s64 (int64x2_t __a)
--{
--  return __builtin_aarch64_addpdi (__a);
--}
--
- __extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
- vqdmulh_laneq_s16 (int16x4_t __a, int16x8_t __b, const int __c)
- {
-@@ -15706,7 +13631,7 @@
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vceq_f32 (float32x2_t __a, float32x2_t __b)
- {
--  return (uint32x2_t) __builtin_aarch64_cmeqv2sf (__a, __b);
-+  return (uint32x2_t) (__a == __b);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
-@@ -15718,26 +13643,25 @@
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vceq_p8 (poly8x8_t __a, poly8x8_t __b)
- {
--  return (uint8x8_t) __builtin_aarch64_cmeqv8qi ((int8x8_t) __a,
--						 (int8x8_t) __b);
-+  return (uint8x8_t) (__a == __b);
- }
- 
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vceq_s8 (int8x8_t __a, int8x8_t __b)
- {
--  return (uint8x8_t) __builtin_aarch64_cmeqv8qi (__a, __b);
-+  return (uint8x8_t) (__a == __b);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vceq_s16 (int16x4_t __a, int16x4_t __b)
- {
--  return (uint16x4_t) __builtin_aarch64_cmeqv4hi (__a, __b);
-+  return (uint16x4_t) (__a == __b);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vceq_s32 (int32x2_t __a, int32x2_t __b)
- {
--  return (uint32x2_t) __builtin_aarch64_cmeqv2si (__a, __b);
-+  return (uint32x2_t) (__a == __b);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
-@@ -15749,22 +13673,19 @@
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vceq_u8 (uint8x8_t __a, uint8x8_t __b)
- {
--  return (uint8x8_t) __builtin_aarch64_cmeqv8qi ((int8x8_t) __a,
--						 (int8x8_t) __b);
-+  return (__a == __b);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vceq_u16 (uint16x4_t __a, uint16x4_t __b)
- {
--  return (uint16x4_t) __builtin_aarch64_cmeqv4hi ((int16x4_t) __a,
--						  (int16x4_t) __b);
-+  return (__a == __b);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vceq_u32 (uint32x2_t __a, uint32x2_t __b)
- {
--  return (uint32x2_t) __builtin_aarch64_cmeqv2si ((int32x2_t) __a,
--						  (int32x2_t) __b);
-+  return (__a == __b);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
-@@ -15776,72 +13697,67 @@
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vceqq_f32 (float32x4_t __a, float32x4_t __b)
- {
--  return (uint32x4_t) __builtin_aarch64_cmeqv4sf (__a, __b);
-+  return (uint32x4_t) (__a == __b);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vceqq_f64 (float64x2_t __a, float64x2_t __b)
- {
--  return (uint64x2_t) __builtin_aarch64_cmeqv2df (__a, __b);
-+  return (uint64x2_t) (__a == __b);
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vceqq_p8 (poly8x16_t __a, poly8x16_t __b)
- {
--  return (uint8x16_t) __builtin_aarch64_cmeqv16qi ((int8x16_t) __a,
--						   (int8x16_t) __b);
-+  return (uint8x16_t) (__a == __b);
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vceqq_s8 (int8x16_t __a, int8x16_t __b)
- {
--  return (uint8x16_t) __builtin_aarch64_cmeqv16qi (__a, __b);
-+  return (uint8x16_t) (__a == __b);
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vceqq_s16 (int16x8_t __a, int16x8_t __b)
- {
--  return (uint16x8_t) __builtin_aarch64_cmeqv8hi (__a, __b);
-+  return (uint16x8_t) (__a == __b);
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vceqq_s32 (int32x4_t __a, int32x4_t __b)
- {
--  return (uint32x4_t) __builtin_aarch64_cmeqv4si (__a, __b);
-+  return (uint32x4_t) (__a == __b);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vceqq_s64 (int64x2_t __a, int64x2_t __b)
- {
--  return (uint64x2_t) __builtin_aarch64_cmeqv2di (__a, __b);
-+  return (uint64x2_t) (__a == __b);
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vceqq_u8 (uint8x16_t __a, uint8x16_t __b)
- {
--  return (uint8x16_t) __builtin_aarch64_cmeqv16qi ((int8x16_t) __a,
--						   (int8x16_t) __b);
-+  return (__a == __b);
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vceqq_u16 (uint16x8_t __a, uint16x8_t __b)
- {
--  return (uint16x8_t) __builtin_aarch64_cmeqv8hi ((int16x8_t) __a,
--						  (int16x8_t) __b);
-+  return (__a == __b);
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vceqq_u32 (uint32x4_t __a, uint32x4_t __b)
- {
--  return (uint32x4_t) __builtin_aarch64_cmeqv4si ((int32x4_t) __a,
--						  (int32x4_t) __b);
-+  return (__a == __b);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vceqq_u64 (uint64x2_t __a, uint64x2_t __b)
- {
--  return (uint64x2_t) __builtin_aarch64_cmeqv2di ((int64x2_t) __a,
--						  (int64x2_t) __b);
-+  return (__a == __b);
- }
- 
- /* vceq - scalar.  */
-@@ -15875,8 +13791,7 @@
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vceqz_f32 (float32x2_t __a)
- {
--  float32x2_t __b = {0.0f, 0.0f};
--  return (uint32x2_t) __builtin_aarch64_cmeqv2sf (__a, __b);
-+  return (uint32x2_t) (__a == 0.0f);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
-@@ -15888,30 +13803,25 @@
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vceqz_p8 (poly8x8_t __a)
- {
--  poly8x8_t __b = {0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint8x8_t) __builtin_aarch64_cmeqv8qi ((int8x8_t) __a,
--						 (int8x8_t) __b);
-+  return (uint8x8_t) (__a == 0);
- }
- 
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vceqz_s8 (int8x8_t __a)
- {
--  int8x8_t __b = {0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint8x8_t) __builtin_aarch64_cmeqv8qi (__a, __b);
-+  return (uint8x8_t) (__a == 0);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vceqz_s16 (int16x4_t __a)
- {
--  int16x4_t __b = {0, 0, 0, 0};
--  return (uint16x4_t) __builtin_aarch64_cmeqv4hi (__a, __b);
-+  return (uint16x4_t) (__a == 0);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vceqz_s32 (int32x2_t __a)
- {
--  int32x2_t __b = {0, 0};
--  return (uint32x2_t) __builtin_aarch64_cmeqv2si (__a, __b);
-+  return (uint32x2_t) (__a == 0);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
-@@ -15923,25 +13833,19 @@
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vceqz_u8 (uint8x8_t __a)
- {
--  uint8x8_t __b = {0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint8x8_t) __builtin_aarch64_cmeqv8qi ((int8x8_t) __a,
--						 (int8x8_t) __b);
-+  return (__a == 0);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vceqz_u16 (uint16x4_t __a)
- {
--  uint16x4_t __b = {0, 0, 0, 0};
--  return (uint16x4_t) __builtin_aarch64_cmeqv4hi ((int16x4_t) __a,
--						  (int16x4_t) __b);
-+  return (__a == 0);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vceqz_u32 (uint32x2_t __a)
- {
--  uint32x2_t __b = {0, 0};
--  return (uint32x2_t) __builtin_aarch64_cmeqv2si ((int32x2_t) __a,
--						  (int32x2_t) __b);
-+  return (__a == 0);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
-@@ -15953,86 +13857,67 @@
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vceqzq_f32 (float32x4_t __a)
- {
--  float32x4_t __b = {0.0f, 0.0f, 0.0f, 0.0f};
--  return (uint32x4_t) __builtin_aarch64_cmeqv4sf (__a, __b);
-+  return (uint32x4_t) (__a == 0.0f);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vceqzq_f64 (float64x2_t __a)
- {
--  float64x2_t __b = {0.0, 0.0};
--  return (uint64x2_t) __builtin_aarch64_cmeqv2df (__a, __b);
-+  return (uint64x2_t) (__a == 0.0f);
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vceqzq_p8 (poly8x16_t __a)
- {
--  poly8x16_t __b = {0, 0, 0, 0, 0, 0, 0, 0,
--		    0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint8x16_t) __builtin_aarch64_cmeqv16qi ((int8x16_t) __a,
--						   (int8x16_t) __b);
-+  return (uint8x16_t) (__a == 0);
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vceqzq_s8 (int8x16_t __a)
- {
--  int8x16_t __b = {0, 0, 0, 0, 0, 0, 0, 0,
--		   0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint8x16_t) __builtin_aarch64_cmeqv16qi (__a, __b);
-+  return (uint8x16_t) (__a == 0);
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vceqzq_s16 (int16x8_t __a)
- {
--  int16x8_t __b = {0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint16x8_t) __builtin_aarch64_cmeqv8hi (__a, __b);
-+  return (uint16x8_t) (__a == 0);
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vceqzq_s32 (int32x4_t __a)
- {
--  int32x4_t __b = {0, 0, 0, 0};
--  return (uint32x4_t) __builtin_aarch64_cmeqv4si (__a, __b);
-+  return (uint32x4_t) (__a == 0);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vceqzq_s64 (int64x2_t __a)
- {
--  int64x2_t __b = {0, 0};
--  return (uint64x2_t) __builtin_aarch64_cmeqv2di (__a, __b);
-+  return (uint64x2_t) (__a == __AARCH64_INT64_C (0));
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vceqzq_u8 (uint8x16_t __a)
- {
--  uint8x16_t __b = {0, 0, 0, 0, 0, 0, 0, 0,
--		    0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint8x16_t) __builtin_aarch64_cmeqv16qi ((int8x16_t) __a,
--						   (int8x16_t) __b);
-+  return (__a == 0);
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vceqzq_u16 (uint16x8_t __a)
- {
--  uint16x8_t __b = {0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint16x8_t) __builtin_aarch64_cmeqv8hi ((int16x8_t) __a,
--						  (int16x8_t) __b);
-+  return (__a == 0);
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vceqzq_u32 (uint32x4_t __a)
- {
--  uint32x4_t __b = {0, 0, 0, 0};
--  return (uint32x4_t) __builtin_aarch64_cmeqv4si ((int32x4_t) __a,
--						  (int32x4_t) __b);
-+  return (__a == 0);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vceqzq_u64 (uint64x2_t __a)
- {
--  uint64x2_t __b = {0, 0};
--  return (uint64x2_t) __builtin_aarch64_cmeqv2di ((int64x2_t) __a,
--						  (int64x2_t) __b);
-+  return (__a == __AARCH64_UINT64_C (0));
- }
- 
- /* vceqz - scalar.  */
-@@ -16066,7 +13951,7 @@
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vcge_f32 (float32x2_t __a, float32x2_t __b)
- {
--  return (uint32x2_t) __builtin_aarch64_cmgev2sf (__a, __b);
-+  return (uint32x2_t) (__a >= __b);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
-@@ -16076,28 +13961,21 @@
- }
- 
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
--vcge_p8 (poly8x8_t __a, poly8x8_t __b)
--{
--  return (uint8x8_t) __builtin_aarch64_cmgev8qi ((int8x8_t) __a,
--						 (int8x8_t) __b);
--}
--
--__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vcge_s8 (int8x8_t __a, int8x8_t __b)
- {
--  return (uint8x8_t) __builtin_aarch64_cmgev8qi (__a, __b);
-+  return (uint8x8_t) (__a >= __b);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vcge_s16 (int16x4_t __a, int16x4_t __b)
- {
--  return (uint16x4_t) __builtin_aarch64_cmgev4hi (__a, __b);
-+  return (uint16x4_t) (__a >= __b);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vcge_s32 (int32x2_t __a, int32x2_t __b)
- {
--  return (uint32x2_t) __builtin_aarch64_cmgev2si (__a, __b);
-+  return (uint32x2_t) (__a >= __b);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
-@@ -16109,22 +13987,19 @@
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vcge_u8 (uint8x8_t __a, uint8x8_t __b)
- {
--  return (uint8x8_t) __builtin_aarch64_cmgeuv8qi ((int8x8_t) __a,
--						 (int8x8_t) __b);
-+  return (__a >= __b);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vcge_u16 (uint16x4_t __a, uint16x4_t __b)
- {
--  return (uint16x4_t) __builtin_aarch64_cmgeuv4hi ((int16x4_t) __a,
--						  (int16x4_t) __b);
-+  return (__a >= __b);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vcge_u32 (uint32x2_t __a, uint32x2_t __b)
- {
--  return (uint32x2_t) __builtin_aarch64_cmgeuv2si ((int32x2_t) __a,
--						  (int32x2_t) __b);
-+  return (__a >= __b);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
-@@ -16136,72 +14011,61 @@
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vcgeq_f32 (float32x4_t __a, float32x4_t __b)
- {
--  return (uint32x4_t) __builtin_aarch64_cmgev4sf (__a, __b);
-+  return (uint32x4_t) (__a >= __b);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vcgeq_f64 (float64x2_t __a, float64x2_t __b)
- {
--  return (uint64x2_t) __builtin_aarch64_cmgev2df (__a, __b);
-+  return (uint64x2_t) (__a >= __b);
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
--vcgeq_p8 (poly8x16_t __a, poly8x16_t __b)
--{
--  return (uint8x16_t) __builtin_aarch64_cmgev16qi ((int8x16_t) __a,
--						   (int8x16_t) __b);
--}
--
--__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vcgeq_s8 (int8x16_t __a, int8x16_t __b)
- {
--  return (uint8x16_t) __builtin_aarch64_cmgev16qi (__a, __b);
-+  return (uint8x16_t) (__a >= __b);
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vcgeq_s16 (int16x8_t __a, int16x8_t __b)
- {
--  return (uint16x8_t) __builtin_aarch64_cmgev8hi (__a, __b);
-+  return (uint16x8_t) (__a >= __b);
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vcgeq_s32 (int32x4_t __a, int32x4_t __b)
- {
--  return (uint32x4_t) __builtin_aarch64_cmgev4si (__a, __b);
-+  return (uint32x4_t) (__a >= __b);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vcgeq_s64 (int64x2_t __a, int64x2_t __b)
- {
--  return (uint64x2_t) __builtin_aarch64_cmgev2di (__a, __b);
-+  return (uint64x2_t) (__a >= __b);
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vcgeq_u8 (uint8x16_t __a, uint8x16_t __b)
- {
--  return (uint8x16_t) __builtin_aarch64_cmgeuv16qi ((int8x16_t) __a,
--						   (int8x16_t) __b);
-+  return (__a >= __b);
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vcgeq_u16 (uint16x8_t __a, uint16x8_t __b)
- {
--  return (uint16x8_t) __builtin_aarch64_cmgeuv8hi ((int16x8_t) __a,
--						  (int16x8_t) __b);
-+  return (__a >= __b);
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vcgeq_u32 (uint32x4_t __a, uint32x4_t __b)
- {
--  return (uint32x4_t) __builtin_aarch64_cmgeuv4si ((int32x4_t) __a,
--						  (int32x4_t) __b);
-+  return (__a >= __b);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vcgeq_u64 (uint64x2_t __a, uint64x2_t __b)
- {
--  return (uint64x2_t) __builtin_aarch64_cmgeuv2di ((int64x2_t) __a,
--						  (int64x2_t) __b);
-+  return (__a >= __b);
- }
- 
- /* vcge - scalar.  */
-@@ -16235,8 +14099,7 @@
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vcgez_f32 (float32x2_t __a)
- {
--  float32x2_t __b = {0.0f, 0.0f};
--  return (uint32x2_t) __builtin_aarch64_cmgev2sf (__a, __b);
-+  return (uint32x2_t) (__a >= 0.0f);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
-@@ -16246,32 +14109,21 @@
- }
- 
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
--vcgez_p8 (poly8x8_t __a)
--{
--  poly8x8_t __b = {0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint8x8_t) __builtin_aarch64_cmgev8qi ((int8x8_t) __a,
--						 (int8x8_t) __b);
--}
--
--__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vcgez_s8 (int8x8_t __a)
- {
--  int8x8_t __b = {0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint8x8_t) __builtin_aarch64_cmgev8qi (__a, __b);
-+  return (uint8x8_t) (__a >= 0);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vcgez_s16 (int16x4_t __a)
- {
--  int16x4_t __b = {0, 0, 0, 0};
--  return (uint16x4_t) __builtin_aarch64_cmgev4hi (__a, __b);
-+  return (uint16x4_t) (__a >= 0);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vcgez_s32 (int32x2_t __a)
- {
--  int32x2_t __b = {0, 0};
--  return (uint32x2_t) __builtin_aarch64_cmgev2si (__a, __b);
-+  return (uint32x2_t) (__a >= 0);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
-@@ -16280,121 +14132,42 @@
-   return __a >= 0ll ? -1ll : 0ll;
- }
- 
--__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
--vcgez_u8 (uint8x8_t __a)
--{
--  uint8x8_t __b = {0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint8x8_t) __builtin_aarch64_cmgeuv8qi ((int8x8_t) __a,
--						 (int8x8_t) __b);
--}
--
--__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
--vcgez_u16 (uint16x4_t __a)
--{
--  uint16x4_t __b = {0, 0, 0, 0};
--  return (uint16x4_t) __builtin_aarch64_cmgeuv4hi ((int16x4_t) __a,
--						  (int16x4_t) __b);
--}
--
--__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
--vcgez_u32 (uint32x2_t __a)
--{
--  uint32x2_t __b = {0, 0};
--  return (uint32x2_t) __builtin_aarch64_cmgeuv2si ((int32x2_t) __a,
--						  (int32x2_t) __b);
--}
--
--__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
--vcgez_u64 (uint64x1_t __a)
--{
--  return __a >= 0ll ? -1ll : 0ll;
--}
--
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vcgezq_f32 (float32x4_t __a)
- {
--  float32x4_t __b = {0.0f, 0.0f, 0.0f, 0.0f};
--  return (uint32x4_t) __builtin_aarch64_cmgev4sf (__a, __b);
-+  return (uint32x4_t) (__a >= 0.0f);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vcgezq_f64 (float64x2_t __a)
- {
--  float64x2_t __b = {0.0, 0.0};
--  return (uint64x2_t) __builtin_aarch64_cmgev2df (__a, __b);
-+  return (uint64x2_t) (__a >= 0.0);
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
--vcgezq_p8 (poly8x16_t __a)
--{
--  poly8x16_t __b = {0, 0, 0, 0, 0, 0, 0, 0,
--		    0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint8x16_t) __builtin_aarch64_cmgev16qi ((int8x16_t) __a,
--						   (int8x16_t) __b);
--}
--
--__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vcgezq_s8 (int8x16_t __a)
- {
--  int8x16_t __b = {0, 0, 0, 0, 0, 0, 0, 0,
--		   0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint8x16_t) __builtin_aarch64_cmgev16qi (__a, __b);
-+  return (uint8x16_t) (__a >= 0);
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vcgezq_s16 (int16x8_t __a)
- {
--  int16x8_t __b = {0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint16x8_t) __builtin_aarch64_cmgev8hi (__a, __b);
-+  return (uint16x8_t) (__a >= 0);
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vcgezq_s32 (int32x4_t __a)
- {
--  int32x4_t __b = {0, 0, 0, 0};
--  return (uint32x4_t) __builtin_aarch64_cmgev4si (__a, __b);
-+  return (uint32x4_t) (__a >= 0);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vcgezq_s64 (int64x2_t __a)
- {
--  int64x2_t __b = {0, 0};
--  return (uint64x2_t) __builtin_aarch64_cmgev2di (__a, __b);
-+  return (uint64x2_t) (__a >= __AARCH64_INT64_C (0));
- }
- 
--__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
--vcgezq_u8 (uint8x16_t __a)
--{
--  uint8x16_t __b = {0, 0, 0, 0, 0, 0, 0, 0,
--		    0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint8x16_t) __builtin_aarch64_cmgeuv16qi ((int8x16_t) __a,
--						   (int8x16_t) __b);
--}
--
--__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
--vcgezq_u16 (uint16x8_t __a)
--{
--  uint16x8_t __b = {0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint16x8_t) __builtin_aarch64_cmgeuv8hi ((int16x8_t) __a,
--						  (int16x8_t) __b);
--}
--
--__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
--vcgezq_u32 (uint32x4_t __a)
--{
--  uint32x4_t __b = {0, 0, 0, 0};
--  return (uint32x4_t) __builtin_aarch64_cmgeuv4si ((int32x4_t) __a,
--						  (int32x4_t) __b);
--}
--
--__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
--vcgezq_u64 (uint64x2_t __a)
--{
--  uint64x2_t __b = {0, 0};
--  return (uint64x2_t) __builtin_aarch64_cmgeuv2di ((int64x2_t) __a,
--						  (int64x2_t) __b);
--}
--
- /* vcgez - scalar.  */
- 
- __extension__ static __inline uint32_t __attribute__ ((__always_inline__))
-@@ -16409,12 +14182,6 @@
-   return __a >= 0 ? -1ll : 0ll;
- }
- 
--__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
--vcgezd_u64 (int64x1_t __a)
--{
--  return __a >= 0 ? -1ll : 0ll;
--}
--
- __extension__ static __inline uint64_t __attribute__ ((__always_inline__))
- vcgezd_f64 (float64_t __a)
- {
-@@ -16426,7 +14193,7 @@
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vcgt_f32 (float32x2_t __a, float32x2_t __b)
- {
--  return (uint32x2_t) __builtin_aarch64_cmgtv2sf (__a, __b);
-+  return (uint32x2_t) (__a > __b);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
-@@ -16436,28 +14203,21 @@
- }
- 
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
--vcgt_p8 (poly8x8_t __a, poly8x8_t __b)
--{
--  return (uint8x8_t) __builtin_aarch64_cmgtv8qi ((int8x8_t) __a,
--						 (int8x8_t) __b);
--}
--
--__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vcgt_s8 (int8x8_t __a, int8x8_t __b)
- {
--  return (uint8x8_t) __builtin_aarch64_cmgtv8qi (__a, __b);
-+  return (uint8x8_t) (__a > __b);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vcgt_s16 (int16x4_t __a, int16x4_t __b)
- {
--  return (uint16x4_t) __builtin_aarch64_cmgtv4hi (__a, __b);
-+  return (uint16x4_t) (__a > __b);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vcgt_s32 (int32x2_t __a, int32x2_t __b)
- {
--  return (uint32x2_t) __builtin_aarch64_cmgtv2si (__a, __b);
-+  return (uint32x2_t) (__a > __b);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
-@@ -16469,22 +14229,19 @@
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vcgt_u8 (uint8x8_t __a, uint8x8_t __b)
- {
--  return (uint8x8_t) __builtin_aarch64_cmgtuv8qi ((int8x8_t) __a,
--						 (int8x8_t) __b);
-+  return (__a > __b);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vcgt_u16 (uint16x4_t __a, uint16x4_t __b)
- {
--  return (uint16x4_t) __builtin_aarch64_cmgtuv4hi ((int16x4_t) __a,
--						  (int16x4_t) __b);
-+  return (__a > __b);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vcgt_u32 (uint32x2_t __a, uint32x2_t __b)
- {
--  return (uint32x2_t) __builtin_aarch64_cmgtuv2si ((int32x2_t) __a,
--						  (int32x2_t) __b);
-+  return (__a > __b);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
-@@ -16496,72 +14253,61 @@
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vcgtq_f32 (float32x4_t __a, float32x4_t __b)
- {
--  return (uint32x4_t) __builtin_aarch64_cmgtv4sf (__a, __b);
-+  return (uint32x4_t) (__a > __b);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vcgtq_f64 (float64x2_t __a, float64x2_t __b)
- {
--  return (uint64x2_t) __builtin_aarch64_cmgtv2df (__a, __b);
-+  return (uint64x2_t) (__a > __b);
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
--vcgtq_p8 (poly8x16_t __a, poly8x16_t __b)
--{
--  return (uint8x16_t) __builtin_aarch64_cmgtv16qi ((int8x16_t) __a,
--						   (int8x16_t) __b);
--}
--
--__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vcgtq_s8 (int8x16_t __a, int8x16_t __b)
- {
--  return (uint8x16_t) __builtin_aarch64_cmgtv16qi (__a, __b);
-+  return (uint8x16_t) (__a > __b);
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vcgtq_s16 (int16x8_t __a, int16x8_t __b)
- {
--  return (uint16x8_t) __builtin_aarch64_cmgtv8hi (__a, __b);
-+  return (uint16x8_t) (__a > __b);
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vcgtq_s32 (int32x4_t __a, int32x4_t __b)
- {
--  return (uint32x4_t) __builtin_aarch64_cmgtv4si (__a, __b);
-+  return (uint32x4_t) (__a > __b);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vcgtq_s64 (int64x2_t __a, int64x2_t __b)
- {
--  return (uint64x2_t) __builtin_aarch64_cmgtv2di (__a, __b);
-+  return (uint64x2_t) (__a > __b);
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vcgtq_u8 (uint8x16_t __a, uint8x16_t __b)
- {
--  return (uint8x16_t) __builtin_aarch64_cmgtuv16qi ((int8x16_t) __a,
--						   (int8x16_t) __b);
-+  return (__a > __b);
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vcgtq_u16 (uint16x8_t __a, uint16x8_t __b)
- {
--  return (uint16x8_t) __builtin_aarch64_cmgtuv8hi ((int16x8_t) __a,
--						  (int16x8_t) __b);
-+  return (__a > __b);
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vcgtq_u32 (uint32x4_t __a, uint32x4_t __b)
- {
--  return (uint32x4_t) __builtin_aarch64_cmgtuv4si ((int32x4_t) __a,
--						  (int32x4_t) __b);
-+  return (__a > __b);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vcgtq_u64 (uint64x2_t __a, uint64x2_t __b)
- {
--  return (uint64x2_t) __builtin_aarch64_cmgtuv2di ((int64x2_t) __a,
--						  (int64x2_t) __b);
-+  return (__a > __b);
- }
- 
- /* vcgt - scalar.  */
-@@ -16595,8 +14341,7 @@
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vcgtz_f32 (float32x2_t __a)
- {
--  float32x2_t __b = {0.0f, 0.0f};
--  return (uint32x2_t) __builtin_aarch64_cmgtv2sf (__a, __b);
-+  return (uint32x2_t) (__a > 0.0f);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
-@@ -16606,32 +14351,21 @@
- }
- 
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
--vcgtz_p8 (poly8x8_t __a)
--{
--  poly8x8_t __b = {0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint8x8_t) __builtin_aarch64_cmgtv8qi ((int8x8_t) __a,
--						 (int8x8_t) __b);
--}
--
--__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vcgtz_s8 (int8x8_t __a)
- {
--  int8x8_t __b = {0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint8x8_t) __builtin_aarch64_cmgtv8qi (__a, __b);
-+  return (uint8x8_t) (__a > 0);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vcgtz_s16 (int16x4_t __a)
- {
--  int16x4_t __b = {0, 0, 0, 0};
--  return (uint16x4_t) __builtin_aarch64_cmgtv4hi (__a, __b);
-+  return (uint16x4_t) (__a > 0);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vcgtz_s32 (int32x2_t __a)
- {
--  int32x2_t __b = {0, 0};
--  return (uint32x2_t) __builtin_aarch64_cmgtv2si (__a, __b);
-+  return (uint32x2_t) (__a > 0);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
-@@ -16640,121 +14374,42 @@
-   return __a > 0ll ? -1ll : 0ll;
- }
- 
--__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
--vcgtz_u8 (uint8x8_t __a)
--{
--  uint8x8_t __b = {0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint8x8_t) __builtin_aarch64_cmgtuv8qi ((int8x8_t) __a,
--						 (int8x8_t) __b);
--}
--
--__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
--vcgtz_u16 (uint16x4_t __a)
--{
--  uint16x4_t __b = {0, 0, 0, 0};
--  return (uint16x4_t) __builtin_aarch64_cmgtuv4hi ((int16x4_t) __a,
--						  (int16x4_t) __b);
--}
--
--__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
--vcgtz_u32 (uint32x2_t __a)
--{
--  uint32x2_t __b = {0, 0};
--  return (uint32x2_t) __builtin_aarch64_cmgtuv2si ((int32x2_t) __a,
--						  (int32x2_t) __b);
--}
--
--__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
--vcgtz_u64 (uint64x1_t __a)
--{
--  return __a > 0ll ? -1ll : 0ll;
--}
--
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vcgtzq_f32 (float32x4_t __a)
- {
--  float32x4_t __b = {0.0f, 0.0f, 0.0f, 0.0f};
--  return (uint32x4_t) __builtin_aarch64_cmgtv4sf (__a, __b);
-+  return (uint32x4_t) (__a > 0.0f);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vcgtzq_f64 (float64x2_t __a)
- {
--  float64x2_t __b = {0.0, 0.0};
--  return (uint64x2_t) __builtin_aarch64_cmgtv2df (__a, __b);
-+    return (uint64x2_t) (__a > 0.0);
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
--vcgtzq_p8 (poly8x16_t __a)
--{
--  poly8x16_t __b = {0, 0, 0, 0, 0, 0, 0, 0,
--		    0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint8x16_t) __builtin_aarch64_cmgtv16qi ((int8x16_t) __a,
--						   (int8x16_t) __b);
--}
--
--__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vcgtzq_s8 (int8x16_t __a)
- {
--  int8x16_t __b = {0, 0, 0, 0, 0, 0, 0, 0,
--		   0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint8x16_t) __builtin_aarch64_cmgtv16qi (__a, __b);
-+  return (uint8x16_t) (__a > 0);
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vcgtzq_s16 (int16x8_t __a)
- {
--  int16x8_t __b = {0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint16x8_t) __builtin_aarch64_cmgtv8hi (__a, __b);
-+  return (uint16x8_t) (__a > 0);
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vcgtzq_s32 (int32x4_t __a)
- {
--  int32x4_t __b = {0, 0, 0, 0};
--  return (uint32x4_t) __builtin_aarch64_cmgtv4si (__a, __b);
-+  return (uint32x4_t) (__a > 0);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vcgtzq_s64 (int64x2_t __a)
- {
--  int64x2_t __b = {0, 0};
--  return (uint64x2_t) __builtin_aarch64_cmgtv2di (__a, __b);
-+  return (uint64x2_t) (__a > __AARCH64_INT64_C (0));
- }
- 
--__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
--vcgtzq_u8 (uint8x16_t __a)
--{
--  uint8x16_t __b = {0, 0, 0, 0, 0, 0, 0, 0,
--		    0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint8x16_t) __builtin_aarch64_cmgtuv16qi ((int8x16_t) __a,
--						   (int8x16_t) __b);
--}
--
--__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
--vcgtzq_u16 (uint16x8_t __a)
--{
--  uint16x8_t __b = {0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint16x8_t) __builtin_aarch64_cmgtuv8hi ((int16x8_t) __a,
--						  (int16x8_t) __b);
--}
--
--__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
--vcgtzq_u32 (uint32x4_t __a)
--{
--  uint32x4_t __b = {0, 0, 0, 0};
--  return (uint32x4_t) __builtin_aarch64_cmgtuv4si ((int32x4_t) __a,
--						  (int32x4_t) __b);
--}
--
--__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
--vcgtzq_u64 (uint64x2_t __a)
--{
--  uint64x2_t __b = {0, 0};
--  return (uint64x2_t) __builtin_aarch64_cmgtuv2di ((int64x2_t) __a,
--						  (int64x2_t) __b);
--}
--
- /* vcgtz - scalar.  */
- 
- __extension__ static __inline uint32_t __attribute__ ((__always_inline__))
-@@ -16769,12 +14424,6 @@
-   return __a > 0 ? -1ll : 0ll;
- }
- 
--__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
--vcgtzd_u64 (int64x1_t __a)
--{
--  return __a > 0 ? -1ll : 0ll;
--}
--
- __extension__ static __inline uint64_t __attribute__ ((__always_inline__))
- vcgtzd_f64 (float64_t __a)
- {
-@@ -16786,7 +14435,7 @@
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vcle_f32 (float32x2_t __a, float32x2_t __b)
- {
--  return (uint32x2_t) __builtin_aarch64_cmgev2sf (__b, __a);
-+  return (uint32x2_t) (__a <= __b);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
-@@ -16796,28 +14445,21 @@
- }
- 
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
--vcle_p8 (poly8x8_t __a, poly8x8_t __b)
--{
--  return (uint8x8_t) __builtin_aarch64_cmgev8qi ((int8x8_t) __b,
--						 (int8x8_t) __a);
--}
--
--__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vcle_s8 (int8x8_t __a, int8x8_t __b)
- {
--  return (uint8x8_t) __builtin_aarch64_cmgev8qi (__b, __a);
-+  return (uint8x8_t) (__a <= __b);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vcle_s16 (int16x4_t __a, int16x4_t __b)
- {
--  return (uint16x4_t) __builtin_aarch64_cmgev4hi (__b, __a);
-+  return (uint16x4_t) (__a <= __b);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vcle_s32 (int32x2_t __a, int32x2_t __b)
- {
--  return (uint32x2_t) __builtin_aarch64_cmgev2si (__b, __a);
-+  return (uint32x2_t) (__a <= __b);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
-@@ -16829,22 +14471,19 @@
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vcle_u8 (uint8x8_t __a, uint8x8_t __b)
- {
--  return (uint8x8_t) __builtin_aarch64_cmgeuv8qi ((int8x8_t) __b,
--						 (int8x8_t) __a);
-+  return (__a <= __b);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vcle_u16 (uint16x4_t __a, uint16x4_t __b)
- {
--  return (uint16x4_t) __builtin_aarch64_cmgeuv4hi ((int16x4_t) __b,
--						  (int16x4_t) __a);
-+  return (__a <= __b);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vcle_u32 (uint32x2_t __a, uint32x2_t __b)
- {
--  return (uint32x2_t) __builtin_aarch64_cmgeuv2si ((int32x2_t) __b,
--						  (int32x2_t) __a);
-+  return (__a <= __b);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
-@@ -16856,72 +14495,61 @@
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vcleq_f32 (float32x4_t __a, float32x4_t __b)
- {
--  return (uint32x4_t) __builtin_aarch64_cmgev4sf (__b, __a);
-+  return (uint32x4_t) (__a <= __b);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vcleq_f64 (float64x2_t __a, float64x2_t __b)
- {
--  return (uint64x2_t) __builtin_aarch64_cmgev2df (__b, __a);
-+  return (uint64x2_t) (__a <= __b);
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
--vcleq_p8 (poly8x16_t __a, poly8x16_t __b)
--{
--  return (uint8x16_t) __builtin_aarch64_cmgev16qi ((int8x16_t) __b,
--						   (int8x16_t) __a);
--}
--
--__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vcleq_s8 (int8x16_t __a, int8x16_t __b)
- {
--  return (uint8x16_t) __builtin_aarch64_cmgev16qi (__b, __a);
-+  return (uint8x16_t) (__a <= __b);
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vcleq_s16 (int16x8_t __a, int16x8_t __b)
- {
--  return (uint16x8_t) __builtin_aarch64_cmgev8hi (__b, __a);
-+  return (uint16x8_t) (__a <= __b);
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vcleq_s32 (int32x4_t __a, int32x4_t __b)
- {
--  return (uint32x4_t) __builtin_aarch64_cmgev4si (__b, __a);
-+  return (uint32x4_t) (__a <= __b);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vcleq_s64 (int64x2_t __a, int64x2_t __b)
- {
--  return (uint64x2_t) __builtin_aarch64_cmgev2di (__b, __a);
-+  return (uint64x2_t) (__a <= __b);
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vcleq_u8 (uint8x16_t __a, uint8x16_t __b)
- {
--  return (uint8x16_t) __builtin_aarch64_cmgeuv16qi ((int8x16_t) __b,
--						   (int8x16_t) __a);
-+  return (__a <= __b);
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vcleq_u16 (uint16x8_t __a, uint16x8_t __b)
- {
--  return (uint16x8_t) __builtin_aarch64_cmgeuv8hi ((int16x8_t) __b,
--						  (int16x8_t) __a);
-+  return (__a <= __b);
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vcleq_u32 (uint32x4_t __a, uint32x4_t __b)
- {
--  return (uint32x4_t) __builtin_aarch64_cmgeuv4si ((int32x4_t) __b,
--						  (int32x4_t) __a);
-+  return (__a <= __b);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vcleq_u64 (uint64x2_t __a, uint64x2_t __b)
- {
--  return (uint64x2_t) __builtin_aarch64_cmgeuv2di ((int64x2_t) __b,
--						  (int64x2_t) __a);
-+  return (__a <= __b);
- }
- 
- /* vcle - scalar.  */
-@@ -16955,8 +14583,7 @@
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vclez_f32 (float32x2_t __a)
- {
--  float32x2_t __b = {0.0f, 0.0f};
--  return (uint32x2_t) __builtin_aarch64_cmlev2sf (__a, __b);
-+  return (uint32x2_t) (__a <= 0.0f);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
-@@ -16966,32 +14593,21 @@
- }
- 
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
--vclez_p8 (poly8x8_t __a)
--{
--  poly8x8_t __b = {0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint8x8_t) __builtin_aarch64_cmlev8qi ((int8x8_t) __a,
--						 (int8x8_t) __b);
--}
--
--__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vclez_s8 (int8x8_t __a)
- {
--  int8x8_t __b = {0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint8x8_t) __builtin_aarch64_cmlev8qi (__a, __b);
-+  return (uint8x8_t) (__a <= 0);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vclez_s16 (int16x4_t __a)
- {
--  int16x4_t __b = {0, 0, 0, 0};
--  return (uint16x4_t) __builtin_aarch64_cmlev4hi (__a, __b);
-+  return (uint16x4_t) (__a <= 0);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vclez_s32 (int32x2_t __a)
- {
--  int32x2_t __b = {0, 0};
--  return (uint32x2_t) __builtin_aarch64_cmlev2si (__a, __b);
-+  return (uint32x2_t) (__a <= 0);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
-@@ -17000,62 +14616,40 @@
-   return __a <= 0ll ? -1ll : 0ll;
- }
- 
--__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
--vclez_u64 (uint64x1_t __a)
--{
--  return __a <= 0ll ? -1ll : 0ll;
--}
--
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vclezq_f32 (float32x4_t __a)
- {
--  float32x4_t __b = {0.0f, 0.0f, 0.0f, 0.0f};
--  return (uint32x4_t) __builtin_aarch64_cmlev4sf (__a, __b);
-+  return (uint32x4_t) (__a <= 0.0f);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vclezq_f64 (float64x2_t __a)
- {
--  float64x2_t __b = {0.0, 0.0};
--  return (uint64x2_t) __builtin_aarch64_cmlev2df (__a, __b);
-+  return (uint64x2_t) (__a <= 0.0);
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
--vclezq_p8 (poly8x16_t __a)
--{
--  poly8x16_t __b = {0, 0, 0, 0, 0, 0, 0, 0,
--		    0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint8x16_t) __builtin_aarch64_cmlev16qi ((int8x16_t) __a,
--						   (int8x16_t) __b);
--}
--
--__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vclezq_s8 (int8x16_t __a)
- {
--  int8x16_t __b = {0, 0, 0, 0, 0, 0, 0, 0,
--		   0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint8x16_t) __builtin_aarch64_cmlev16qi (__a, __b);
-+  return (uint8x16_t) (__a <= 0);
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vclezq_s16 (int16x8_t __a)
- {
--  int16x8_t __b = {0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint16x8_t) __builtin_aarch64_cmlev8hi (__a, __b);
-+  return (uint16x8_t) (__a <= 0);
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vclezq_s32 (int32x4_t __a)
- {
--  int32x4_t __b = {0, 0, 0, 0};
--  return (uint32x4_t) __builtin_aarch64_cmlev4si (__a, __b);
-+  return (uint32x4_t) (__a <= 0);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vclezq_s64 (int64x2_t __a)
- {
--  int64x2_t __b = {0, 0};
--  return (uint64x2_t) __builtin_aarch64_cmlev2di (__a, __b);
-+  return (uint64x2_t) (__a <= __AARCH64_INT64_C (0));
- }
- 
- /* vclez - scalar.  */
-@@ -17072,12 +14666,6 @@
-   return __a <= 0 ? -1ll : 0ll;
- }
- 
--__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
--vclezd_u64 (int64x1_t __a)
--{
--  return __a <= 0 ? -1ll : 0ll;
--}
--
- __extension__ static __inline uint64_t __attribute__ ((__always_inline__))
- vclezd_f64 (float64_t __a)
- {
-@@ -17089,7 +14677,7 @@
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vclt_f32 (float32x2_t __a, float32x2_t __b)
- {
--  return (uint32x2_t) __builtin_aarch64_cmgtv2sf (__b, __a);
-+  return (uint32x2_t) (__a < __b);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
-@@ -17099,28 +14687,21 @@
- }
- 
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
--vclt_p8 (poly8x8_t __a, poly8x8_t __b)
--{
--  return (uint8x8_t) __builtin_aarch64_cmgtv8qi ((int8x8_t) __b,
--						 (int8x8_t) __a);
--}
--
--__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vclt_s8 (int8x8_t __a, int8x8_t __b)
- {
--  return (uint8x8_t) __builtin_aarch64_cmgtv8qi (__b, __a);
-+  return (uint8x8_t) (__a < __b);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vclt_s16 (int16x4_t __a, int16x4_t __b)
- {
--  return (uint16x4_t) __builtin_aarch64_cmgtv4hi (__b, __a);
-+  return (uint16x4_t) (__a < __b);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vclt_s32 (int32x2_t __a, int32x2_t __b)
- {
--  return (uint32x2_t) __builtin_aarch64_cmgtv2si (__b, __a);
-+  return (uint32x2_t) (__a < __b);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
-@@ -17132,22 +14713,19 @@
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vclt_u8 (uint8x8_t __a, uint8x8_t __b)
- {
--  return (uint8x8_t) __builtin_aarch64_cmgtuv8qi ((int8x8_t) __b,
--						 (int8x8_t) __a);
-+  return (__a < __b);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vclt_u16 (uint16x4_t __a, uint16x4_t __b)
- {
--  return (uint16x4_t) __builtin_aarch64_cmgtuv4hi ((int16x4_t) __b,
--						  (int16x4_t) __a);
-+  return (__a < __b);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vclt_u32 (uint32x2_t __a, uint32x2_t __b)
- {
--  return (uint32x2_t) __builtin_aarch64_cmgtuv2si ((int32x2_t) __b,
--						  (int32x2_t) __a);
-+  return (__a < __b);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
-@@ -17159,72 +14737,61 @@
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vcltq_f32 (float32x4_t __a, float32x4_t __b)
- {
--  return (uint32x4_t) __builtin_aarch64_cmgtv4sf (__b, __a);
-+  return (uint32x4_t) (__a < __b);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vcltq_f64 (float64x2_t __a, float64x2_t __b)
- {
--  return (uint64x2_t) __builtin_aarch64_cmgtv2df (__b, __a);
-+  return (uint64x2_t) (__a < __b);
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
--vcltq_p8 (poly8x16_t __a, poly8x16_t __b)
--{
--  return (uint8x16_t) __builtin_aarch64_cmgtv16qi ((int8x16_t) __b,
--						   (int8x16_t) __a);
--}
--
--__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vcltq_s8 (int8x16_t __a, int8x16_t __b)
- {
--  return (uint8x16_t) __builtin_aarch64_cmgtv16qi (__b, __a);
-+  return (uint8x16_t) (__a < __b);
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vcltq_s16 (int16x8_t __a, int16x8_t __b)
- {
--  return (uint16x8_t) __builtin_aarch64_cmgtv8hi (__b, __a);
-+  return (uint16x8_t) (__a < __b);
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vcltq_s32 (int32x4_t __a, int32x4_t __b)
- {
--  return (uint32x4_t) __builtin_aarch64_cmgtv4si (__b, __a);
-+  return (uint32x4_t) (__a < __b);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vcltq_s64 (int64x2_t __a, int64x2_t __b)
- {
--  return (uint64x2_t) __builtin_aarch64_cmgtv2di (__b, __a);
-+  return (uint64x2_t) (__a < __b);
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vcltq_u8 (uint8x16_t __a, uint8x16_t __b)
- {
--  return (uint8x16_t) __builtin_aarch64_cmgtuv16qi ((int8x16_t) __b,
--						   (int8x16_t) __a);
-+  return (__a < __b);
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vcltq_u16 (uint16x8_t __a, uint16x8_t __b)
- {
--  return (uint16x8_t) __builtin_aarch64_cmgtuv8hi ((int16x8_t) __b,
--						  (int16x8_t) __a);
-+  return (__a < __b);
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vcltq_u32 (uint32x4_t __a, uint32x4_t __b)
- {
--  return (uint32x4_t) __builtin_aarch64_cmgtuv4si ((int32x4_t) __b,
--						  (int32x4_t) __a);
-+  return (__a < __b);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vcltq_u64 (uint64x2_t __a, uint64x2_t __b)
- {
--  return (uint64x2_t) __builtin_aarch64_cmgtuv2di ((int64x2_t) __b,
--						  (int64x2_t) __a);
-+  return (__a < __b);
- }
- 
- /* vclt - scalar.  */
-@@ -17258,8 +14825,7 @@
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vcltz_f32 (float32x2_t __a)
- {
--  float32x2_t __b = {0.0f, 0.0f};
--  return (uint32x2_t) __builtin_aarch64_cmltv2sf (__a, __b);
-+  return (uint32x2_t) (__a < 0.0f);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
-@@ -17269,32 +14835,21 @@
- }
- 
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
--vcltz_p8 (poly8x8_t __a)
--{
--  poly8x8_t __b = {0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint8x8_t) __builtin_aarch64_cmltv8qi ((int8x8_t) __a,
--						 (int8x8_t) __b);
--}
--
--__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vcltz_s8 (int8x8_t __a)
- {
--  int8x8_t __b = {0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint8x8_t) __builtin_aarch64_cmltv8qi (__a, __b);
-+  return (uint8x8_t) (__a < 0);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vcltz_s16 (int16x4_t __a)
- {
--  int16x4_t __b = {0, 0, 0, 0};
--  return (uint16x4_t) __builtin_aarch64_cmltv4hi (__a, __b);
-+  return (uint16x4_t) (__a < 0);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vcltz_s32 (int32x2_t __a)
- {
--  int32x2_t __b = {0, 0};
--  return (uint32x2_t) __builtin_aarch64_cmltv2si (__a, __b);
-+  return (uint32x2_t) (__a < 0);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
-@@ -17306,53 +14861,37 @@
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vcltzq_f32 (float32x4_t __a)
- {
--  float32x4_t __b = {0.0f, 0.0f, 0.0f, 0.0f};
--  return (uint32x4_t) __builtin_aarch64_cmltv4sf (__a, __b);
-+  return (uint32x4_t) (__a < 0.0f);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vcltzq_f64 (float64x2_t __a)
- {
--  float64x2_t __b = {0.0, 0.0};
--  return (uint64x2_t) __builtin_aarch64_cmltv2df (__a, __b);
-+  return (uint64x2_t) (__a < 0.0);
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
--vcltzq_p8 (poly8x16_t __a)
--{
--  poly8x16_t __b = {0, 0, 0, 0, 0, 0, 0, 0,
--		    0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint8x16_t) __builtin_aarch64_cmltv16qi ((int8x16_t) __a,
--						   (int8x16_t) __b);
--}
--
--__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vcltzq_s8 (int8x16_t __a)
- {
--  int8x16_t __b = {0, 0, 0, 0, 0, 0, 0, 0,
--		   0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint8x16_t) __builtin_aarch64_cmltv16qi (__a, __b);
-+  return (uint8x16_t) (__a < 0);
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vcltzq_s16 (int16x8_t __a)
- {
--  int16x8_t __b = {0, 0, 0, 0, 0, 0, 0, 0};
--  return (uint16x8_t) __builtin_aarch64_cmltv8hi (__a, __b);
-+  return (uint16x8_t) (__a < 0);
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vcltzq_s32 (int32x4_t __a)
- {
--  int32x4_t __b = {0, 0, 0, 0};
--  return (uint32x4_t) __builtin_aarch64_cmltv4si (__a, __b);
-+  return (uint32x4_t) (__a < 0);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vcltzq_s64 (int64x2_t __a)
- {
--  int64x2_t __b = {0, 0};
--  return (uint64x2_t) __builtin_aarch64_cmltv2di (__a, __b);
-+  return (uint64x2_t) (__a < __AARCH64_INT64_C (0));
- }
- 
- /* vcltz - scalar.  */
-@@ -17369,12 +14908,6 @@
-   return __a < 0 ? -1ll : 0ll;
- }
- 
--__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
--vcltzd_u64 (int64x1_t __a)
--{
--  return __a < 0 ? -1ll : 0ll;
--}
--
- __extension__ static __inline uint64_t __attribute__ ((__always_inline__))
- vcltzd_f64 (float64_t __a)
- {
-@@ -18483,6 +16016,292 @@
-   return __aarch64_vgetq_lane_u64 (__a, __b);
- }
- 
-+/* vext  */
-+
-+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
-+vext_f32 (float32x2_t __a, float32x2_t __b, __const int __c)
-+{
-+  __builtin_aarch64_im_lane_boundsi (__c, 2);
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__b, __a, (uint32x2_t) {2-__c, 3-__c});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {__c, __c+1});
-+#endif
-+}
-+
-+__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
-+vext_f64 (float64x1_t __a, float64x1_t __b, __const int __c)
-+{
-+  /* The only possible index to the assembler instruction returns element 0.  */
-+  __builtin_aarch64_im_lane_boundsi (__c, 1);
-+  return __a;
-+}
-+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
-+vext_p8 (poly8x8_t __a, poly8x8_t __b, __const int __c)
-+{
-+  __builtin_aarch64_im_lane_boundsi (__c, 8);
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__b, __a, (uint8x8_t)
-+      {8-__c, 9-__c, 10-__c, 11-__c, 12-__c, 13-__c, 14-__c, 15-__c});
-+#else
-+  return __builtin_shuffle (__a, __b,
-+      (uint8x8_t) {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7});
-+#endif
-+}
-+
-+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
-+vext_p16 (poly16x4_t __a, poly16x4_t __b, __const int __c)
-+{
-+  __builtin_aarch64_im_lane_boundsi (__c, 4);
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__b, __a,
-+      (uint16x4_t) {4-__c, 5-__c, 6-__c, 7-__c});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {__c, __c+1, __c+2, __c+3});
-+#endif
-+}
-+
-+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
-+vext_s8 (int8x8_t __a, int8x8_t __b, __const int __c)
-+{
-+  __builtin_aarch64_im_lane_boundsi (__c, 8);
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__b, __a, (uint8x8_t)
-+      {8-__c, 9-__c, 10-__c, 11-__c, 12-__c, 13-__c, 14-__c, 15-__c});
-+#else
-+  return __builtin_shuffle (__a, __b,
-+      (uint8x8_t) {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7});
-+#endif
-+}
-+
-+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
-+vext_s16 (int16x4_t __a, int16x4_t __b, __const int __c)
-+{
-+  __builtin_aarch64_im_lane_boundsi (__c, 4);
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__b, __a,
-+      (uint16x4_t) {4-__c, 5-__c, 6-__c, 7-__c});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {__c, __c+1, __c+2, __c+3});
-+#endif
-+}
-+
-+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
-+vext_s32 (int32x2_t __a, int32x2_t __b, __const int __c)
-+{
-+  __builtin_aarch64_im_lane_boundsi (__c, 2);
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__b, __a, (uint32x2_t) {2-__c, 3-__c});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {__c, __c+1});
-+#endif
-+}
-+
-+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
-+vext_s64 (int64x1_t __a, int64x1_t __b, __const int __c)
-+{
-+  /* The only possible index to the assembler instruction returns element 0.  */
-+  __builtin_aarch64_im_lane_boundsi (__c, 1);
-+  return __a;
-+}
-+
-+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
-+vext_u8 (uint8x8_t __a, uint8x8_t __b, __const int __c)
-+{
-+  __builtin_aarch64_im_lane_boundsi (__c, 8);
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__b, __a, (uint8x8_t)
-+      {8-__c, 9-__c, 10-__c, 11-__c, 12-__c, 13-__c, 14-__c, 15-__c});
-+#else
-+  return __builtin_shuffle (__a, __b,
-+      (uint8x8_t) {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7});
-+#endif
-+}
-+
-+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
-+vext_u16 (uint16x4_t __a, uint16x4_t __b, __const int __c)
-+{
-+  __builtin_aarch64_im_lane_boundsi (__c, 4);
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__b, __a,
-+      (uint16x4_t) {4-__c, 5-__c, 6-__c, 7-__c});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {__c, __c+1, __c+2, __c+3});
-+#endif
-+}
-+
-+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
-+vext_u32 (uint32x2_t __a, uint32x2_t __b, __const int __c)
-+{
-+  __builtin_aarch64_im_lane_boundsi (__c, 2);
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__b, __a, (uint32x2_t) {2-__c, 3-__c});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {__c, __c+1});
-+#endif
-+}
-+
-+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
-+vext_u64 (uint64x1_t __a, uint64x1_t __b, __const int __c)
-+{
-+  /* The only possible index to the assembler instruction returns element 0.  */
-+  __builtin_aarch64_im_lane_boundsi (__c, 1);
-+  return __a;
-+}
-+
-+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
-+vextq_f32 (float32x4_t __a, float32x4_t __b, __const int __c)
-+{
-+  __builtin_aarch64_im_lane_boundsi (__c, 4);
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__b, __a,
-+      (uint32x4_t) {4-__c, 5-__c, 6-__c, 7-__c});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {__c, __c+1, __c+2, __c+3});
-+#endif
-+}
-+
-+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
-+vextq_f64 (float64x2_t __a, float64x2_t __b, __const int __c)
-+{
-+  __builtin_aarch64_im_lane_boundsi (__c, 2);
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__b, __a, (uint64x2_t) {2-__c, 3-__c});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {__c, __c+1});
-+#endif
-+}
-+
-+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
-+vextq_p8 (poly8x16_t __a, poly8x16_t __b, __const int __c)
-+{
-+  __builtin_aarch64_im_lane_boundsi (__c, 16);
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__b, __a, (uint8x16_t)
-+      {16-__c, 17-__c, 18-__c, 19-__c, 20-__c, 21-__c, 22-__c, 23-__c,
-+       24-__c, 25-__c, 26-__c, 27-__c, 28-__c, 29-__c, 30-__c, 31-__c});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint8x16_t)
-+      {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7,
-+       __c+8, __c+9, __c+10, __c+11, __c+12, __c+13, __c+14, __c+15});
-+#endif
-+}
-+
-+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
-+vextq_p16 (poly16x8_t __a, poly16x8_t __b, __const int __c)
-+{
-+  __builtin_aarch64_im_lane_boundsi (__c, 8);
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__b, __a, (uint16x8_t)
-+      {8-__c, 9-__c, 10-__c, 11-__c, 12-__c, 13-__c, 14-__c, 15-__c});
-+#else
-+  return __builtin_shuffle (__a, __b,
-+      (uint16x8_t) {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7});
-+#endif
-+}
-+
-+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
-+vextq_s8 (int8x16_t __a, int8x16_t __b, __const int __c)
-+{
-+  __builtin_aarch64_im_lane_boundsi (__c, 16);
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__b, __a, (uint8x16_t)
-+      {16-__c, 17-__c, 18-__c, 19-__c, 20-__c, 21-__c, 22-__c, 23-__c,
-+       24-__c, 25-__c, 26-__c, 27-__c, 28-__c, 29-__c, 30-__c, 31-__c});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint8x16_t)
-+      {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7,
-+       __c+8, __c+9, __c+10, __c+11, __c+12, __c+13, __c+14, __c+15});
-+#endif
-+}
-+
-+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
-+vextq_s16 (int16x8_t __a, int16x8_t __b, __const int __c)
-+{
-+  __builtin_aarch64_im_lane_boundsi (__c, 8);
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__b, __a, (uint16x8_t)
-+      {8-__c, 9-__c, 10-__c, 11-__c, 12-__c, 13-__c, 14-__c, 15-__c});
-+#else
-+  return __builtin_shuffle (__a, __b,
-+      (uint16x8_t) {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7});
-+#endif
-+}
-+
-+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
-+vextq_s32 (int32x4_t __a, int32x4_t __b, __const int __c)
-+{
-+  __builtin_aarch64_im_lane_boundsi (__c, 4);
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__b, __a,
-+      (uint32x4_t) {4-__c, 5-__c, 6-__c, 7-__c});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {__c, __c+1, __c+2, __c+3});
-+#endif
-+}
-+
-+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
-+vextq_s64 (int64x2_t __a, int64x2_t __b, __const int __c)
-+{
-+  __builtin_aarch64_im_lane_boundsi (__c, 2);
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__b, __a, (uint64x2_t) {2-__c, 3-__c});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {__c, __c+1});
-+#endif
-+}
-+
-+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
-+vextq_u8 (uint8x16_t __a, uint8x16_t __b, __const int __c)
-+{
-+  __builtin_aarch64_im_lane_boundsi (__c, 16);
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__b, __a, (uint8x16_t)
-+      {16-__c, 17-__c, 18-__c, 19-__c, 20-__c, 21-__c, 22-__c, 23-__c,
-+       24-__c, 25-__c, 26-__c, 27-__c, 28-__c, 29-__c, 30-__c, 31-__c});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint8x16_t)
-+      {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7,
-+       __c+8, __c+9, __c+10, __c+11, __c+12, __c+13, __c+14, __c+15});
-+#endif
-+}
-+
-+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
-+vextq_u16 (uint16x8_t __a, uint16x8_t __b, __const int __c)
-+{
-+  __builtin_aarch64_im_lane_boundsi (__c, 8);
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__b, __a, (uint16x8_t)
-+      {8-__c, 9-__c, 10-__c, 11-__c, 12-__c, 13-__c, 14-__c, 15-__c});
-+#else
-+  return __builtin_shuffle (__a, __b,
-+      (uint16x8_t) {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7});
-+#endif
-+}
-+
-+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
-+vextq_u32 (uint32x4_t __a, uint32x4_t __b, __const int __c)
-+{
-+  __builtin_aarch64_im_lane_boundsi (__c, 4);
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__b, __a,
-+      (uint32x4_t) {4-__c, 5-__c, 6-__c, 7-__c});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {__c, __c+1, __c+2, __c+3});
-+#endif
-+}
-+
-+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
-+vextq_u64 (uint64x2_t __a, uint64x2_t __b, __const int __c)
-+{
-+  __builtin_aarch64_im_lane_boundsi (__c, 2);
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__b, __a, (uint64x2_t) {2-__c, 3-__c});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {__c, __c+1});
-+#endif
-+}
-+
- /* vfma_lane  */
- 
- __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
-@@ -19712,6 +17531,872 @@
-   return ret;
- }
- 
-+/* vldn_dup */
-+
-+__extension__ static __inline int8x8x2_t __attribute__ ((__always_inline__))
-+vld2_dup_s8 (const int8_t * __a)
-+{
-+  int8x8x2_t ret;
-+  __builtin_aarch64_simd_oi __o;
-+  __o = __builtin_aarch64_ld2rv8qi ((const __builtin_aarch64_simd_qi *) __a);
-+  ret.val[0] = (int8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 0);
-+  ret.val[1] = (int8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 1);
-+  return ret;
-+}
-+
-+__extension__ static __inline int16x4x2_t __attribute__ ((__always_inline__))
-+vld2_dup_s16 (const int16_t * __a)
-+{
-+  int16x4x2_t ret;
-+  __builtin_aarch64_simd_oi __o;
-+  __o = __builtin_aarch64_ld2rv4hi ((const __builtin_aarch64_simd_hi *) __a);
-+  ret.val[0] = (int16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 0);
-+  ret.val[1] = (int16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 1);
-+  return ret;
-+}
-+
-+__extension__ static __inline int32x2x2_t __attribute__ ((__always_inline__))
-+vld2_dup_s32 (const int32_t * __a)
-+{
-+  int32x2x2_t ret;
-+  __builtin_aarch64_simd_oi __o;
-+  __o = __builtin_aarch64_ld2rv2si ((const __builtin_aarch64_simd_si *) __a);
-+  ret.val[0] = (int32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 0);
-+  ret.val[1] = (int32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 1);
-+  return ret;
-+}
-+
-+__extension__ static __inline float32x2x2_t __attribute__ ((__always_inline__))
-+vld2_dup_f32 (const float32_t * __a)
-+{
-+  float32x2x2_t ret;
-+  __builtin_aarch64_simd_oi __o;
-+  __o = __builtin_aarch64_ld2rv2sf ((const __builtin_aarch64_simd_sf *) __a);
-+  ret.val[0] = (float32x2_t) __builtin_aarch64_get_dregoiv2sf (__o, 0);
-+  ret.val[1] = (float32x2_t) __builtin_aarch64_get_dregoiv2sf (__o, 1);
-+  return ret;
-+}
-+
-+__extension__ static __inline float64x1x2_t __attribute__ ((__always_inline__))
-+vld2_dup_f64 (const float64_t * __a)
-+{
-+  float64x1x2_t ret;
-+  __builtin_aarch64_simd_oi __o;
-+  __o = __builtin_aarch64_ld2rdf ((const __builtin_aarch64_simd_df *) __a);
-+  ret.val[0] = (float64x1_t) {__builtin_aarch64_get_dregoidf (__o, 0)};
-+  ret.val[1] = (float64x1_t) {__builtin_aarch64_get_dregoidf (__o, 1)};
-+  return ret;
-+}
-+
-+__extension__ static __inline uint8x8x2_t __attribute__ ((__always_inline__))
-+vld2_dup_u8 (const uint8_t * __a)
-+{
-+  uint8x8x2_t ret;
-+  __builtin_aarch64_simd_oi __o;
-+  __o = __builtin_aarch64_ld2rv8qi ((const __builtin_aarch64_simd_qi *) __a);
-+  ret.val[0] = (uint8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 0);
-+  ret.val[1] = (uint8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 1);
-+  return ret;
-+}
-+
-+__extension__ static __inline uint16x4x2_t __attribute__ ((__always_inline__))
-+vld2_dup_u16 (const uint16_t * __a)
-+{
-+  uint16x4x2_t ret;
-+  __builtin_aarch64_simd_oi __o;
-+  __o = __builtin_aarch64_ld2rv4hi ((const __builtin_aarch64_simd_hi *) __a);
-+  ret.val[0] = (uint16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 0);
-+  ret.val[1] = (uint16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 1);
-+  return ret;
-+}
-+
-+__extension__ static __inline uint32x2x2_t __attribute__ ((__always_inline__))
-+vld2_dup_u32 (const uint32_t * __a)
-+{
-+  uint32x2x2_t ret;
-+  __builtin_aarch64_simd_oi __o;
-+  __o = __builtin_aarch64_ld2rv2si ((const __builtin_aarch64_simd_si *) __a);
-+  ret.val[0] = (uint32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 0);
-+  ret.val[1] = (uint32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 1);
-+  return ret;
-+}
-+
-+__extension__ static __inline poly8x8x2_t __attribute__ ((__always_inline__))
-+vld2_dup_p8 (const poly8_t * __a)
-+{
-+  poly8x8x2_t ret;
-+  __builtin_aarch64_simd_oi __o;
-+  __o = __builtin_aarch64_ld2rv8qi ((const __builtin_aarch64_simd_qi *) __a);
-+  ret.val[0] = (poly8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 0);
-+  ret.val[1] = (poly8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 1);
-+  return ret;
-+}
-+
-+__extension__ static __inline poly16x4x2_t __attribute__ ((__always_inline__))
-+vld2_dup_p16 (const poly16_t * __a)
-+{
-+  poly16x4x2_t ret;
-+  __builtin_aarch64_simd_oi __o;
-+  __o = __builtin_aarch64_ld2rv4hi ((const __builtin_aarch64_simd_hi *) __a);
-+  ret.val[0] = (poly16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 0);
-+  ret.val[1] = (poly16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 1);
-+  return ret;
-+}
-+
-+__extension__ static __inline int64x1x2_t __attribute__ ((__always_inline__))
-+vld2_dup_s64 (const int64_t * __a)
-+{
-+  int64x1x2_t ret;
-+  __builtin_aarch64_simd_oi __o;
-+  __o = __builtin_aarch64_ld2rdi ((const __builtin_aarch64_simd_di *) __a);
-+  ret.val[0] = (int64x1_t) __builtin_aarch64_get_dregoidi (__o, 0);
-+  ret.val[1] = (int64x1_t) __builtin_aarch64_get_dregoidi (__o, 1);
-+  return ret;
-+}
-+
-+__extension__ static __inline uint64x1x2_t __attribute__ ((__always_inline__))
-+vld2_dup_u64 (const uint64_t * __a)
-+{
-+  uint64x1x2_t ret;
-+  __builtin_aarch64_simd_oi __o;
-+  __o = __builtin_aarch64_ld2rdi ((const __builtin_aarch64_simd_di *) __a);
-+  ret.val[0] = (uint64x1_t) __builtin_aarch64_get_dregoidi (__o, 0);
-+  ret.val[1] = (uint64x1_t) __builtin_aarch64_get_dregoidi (__o, 1);
-+  return ret;
-+}
-+
-+__extension__ static __inline int8x16x2_t __attribute__ ((__always_inline__))
-+vld2q_dup_s8 (const int8_t * __a)
-+{
-+  int8x16x2_t ret;
-+  __builtin_aarch64_simd_oi __o;
-+  __o = __builtin_aarch64_ld2rv16qi ((const __builtin_aarch64_simd_qi *) __a);
-+  ret.val[0] = (int8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 0);
-+  ret.val[1] = (int8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 1);
-+  return ret;
-+}
-+
-+__extension__ static __inline poly8x16x2_t __attribute__ ((__always_inline__))
-+vld2q_dup_p8 (const poly8_t * __a)
-+{
-+  poly8x16x2_t ret;
-+  __builtin_aarch64_simd_oi __o;
-+  __o = __builtin_aarch64_ld2rv16qi ((const __builtin_aarch64_simd_qi *) __a);
-+  ret.val[0] = (poly8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 0);
-+  ret.val[1] = (poly8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 1);
-+  return ret;
-+}
-+
-+__extension__ static __inline int16x8x2_t __attribute__ ((__always_inline__))
-+vld2q_dup_s16 (const int16_t * __a)
-+{
-+  int16x8x2_t ret;
-+  __builtin_aarch64_simd_oi __o;
-+  __o = __builtin_aarch64_ld2rv8hi ((const __builtin_aarch64_simd_hi *) __a);
-+  ret.val[0] = (int16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 0);
-+  ret.val[1] = (int16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 1);
-+  return ret;
-+}
-+
-+__extension__ static __inline poly16x8x2_t __attribute__ ((__always_inline__))
-+vld2q_dup_p16 (const poly16_t * __a)
-+{
-+  poly16x8x2_t ret;
-+  __builtin_aarch64_simd_oi __o;
-+  __o = __builtin_aarch64_ld2rv8hi ((const __builtin_aarch64_simd_hi *) __a);
-+  ret.val[0] = (poly16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 0);
-+  ret.val[1] = (poly16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 1);
-+  return ret;
-+}
-+
-+__extension__ static __inline int32x4x2_t __attribute__ ((__always_inline__))
-+vld2q_dup_s32 (const int32_t * __a)
-+{
-+  int32x4x2_t ret;
-+  __builtin_aarch64_simd_oi __o;
-+  __o = __builtin_aarch64_ld2rv4si ((const __builtin_aarch64_simd_si *) __a);
-+  ret.val[0] = (int32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 0);
-+  ret.val[1] = (int32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 1);
-+  return ret;
-+}
-+
-+__extension__ static __inline int64x2x2_t __attribute__ ((__always_inline__))
-+vld2q_dup_s64 (const int64_t * __a)
-+{
-+  int64x2x2_t ret;
-+  __builtin_aarch64_simd_oi __o;
-+  __o = __builtin_aarch64_ld2rv2di ((const __builtin_aarch64_simd_di *) __a);
-+  ret.val[0] = (int64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 0);
-+  ret.val[1] = (int64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 1);
-+  return ret;
-+}
-+
-+__extension__ static __inline uint8x16x2_t __attribute__ ((__always_inline__))
-+vld2q_dup_u8 (const uint8_t * __a)
-+{
-+  uint8x16x2_t ret;
-+  __builtin_aarch64_simd_oi __o;
-+  __o = __builtin_aarch64_ld2rv16qi ((const __builtin_aarch64_simd_qi *) __a);
-+  ret.val[0] = (uint8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 0);
-+  ret.val[1] = (uint8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 1);
-+  return ret;
-+}
-+
-+__extension__ static __inline uint16x8x2_t __attribute__ ((__always_inline__))
-+vld2q_dup_u16 (const uint16_t * __a)
-+{
-+  uint16x8x2_t ret;
-+  __builtin_aarch64_simd_oi __o;
-+  __o = __builtin_aarch64_ld2rv8hi ((const __builtin_aarch64_simd_hi *) __a);
-+  ret.val[0] = (uint16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 0);
-+  ret.val[1] = (uint16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 1);
-+  return ret;
-+}
-+
-+__extension__ static __inline uint32x4x2_t __attribute__ ((__always_inline__))
-+vld2q_dup_u32 (const uint32_t * __a)
-+{
-+  uint32x4x2_t ret;
-+  __builtin_aarch64_simd_oi __o;
-+  __o = __builtin_aarch64_ld2rv4si ((const __builtin_aarch64_simd_si *) __a);
-+  ret.val[0] = (uint32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 0);
-+  ret.val[1] = (uint32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 1);
-+  return ret;
-+}
-+
-+__extension__ static __inline uint64x2x2_t __attribute__ ((__always_inline__))
-+vld2q_dup_u64 (const uint64_t * __a)
-+{
-+  uint64x2x2_t ret;
-+  __builtin_aarch64_simd_oi __o;
-+  __o = __builtin_aarch64_ld2rv2di ((const __builtin_aarch64_simd_di *) __a);
-+  ret.val[0] = (uint64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 0);
-+  ret.val[1] = (uint64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 1);
-+  return ret;
-+}
-+
-+__extension__ static __inline float32x4x2_t __attribute__ ((__always_inline__))
-+vld2q_dup_f32 (const float32_t * __a)
-+{
-+  float32x4x2_t ret;
-+  __builtin_aarch64_simd_oi __o;
-+  __o = __builtin_aarch64_ld2rv4sf ((const __builtin_aarch64_simd_sf *) __a);
-+  ret.val[0] = (float32x4_t) __builtin_aarch64_get_qregoiv4sf (__o, 0);
-+  ret.val[1] = (float32x4_t) __builtin_aarch64_get_qregoiv4sf (__o, 1);
-+  return ret;
-+}
-+
-+__extension__ static __inline float64x2x2_t __attribute__ ((__always_inline__))
-+vld2q_dup_f64 (const float64_t * __a)
-+{
-+  float64x2x2_t ret;
-+  __builtin_aarch64_simd_oi __o;
-+  __o = __builtin_aarch64_ld2rv2df ((const __builtin_aarch64_simd_df *) __a);
-+  ret.val[0] = (float64x2_t) __builtin_aarch64_get_qregoiv2df (__o, 0);
-+  ret.val[1] = (float64x2_t) __builtin_aarch64_get_qregoiv2df (__o, 1);
-+  return ret;
-+}
-+
-+__extension__ static __inline int64x1x3_t __attribute__ ((__always_inline__))
-+vld3_dup_s64 (const int64_t * __a)
-+{
-+  int64x1x3_t ret;
-+  __builtin_aarch64_simd_ci __o;
-+  __o = __builtin_aarch64_ld3rdi ((const __builtin_aarch64_simd_di *) __a);
-+  ret.val[0] = (int64x1_t) __builtin_aarch64_get_dregcidi (__o, 0);
-+  ret.val[1] = (int64x1_t) __builtin_aarch64_get_dregcidi (__o, 1);
-+  ret.val[2] = (int64x1_t) __builtin_aarch64_get_dregcidi (__o, 2);
-+  return ret;
-+}
-+
-+__extension__ static __inline uint64x1x3_t __attribute__ ((__always_inline__))
-+vld3_dup_u64 (const uint64_t * __a)
-+{
-+  uint64x1x3_t ret;
-+  __builtin_aarch64_simd_ci __o;
-+  __o = __builtin_aarch64_ld3rdi ((const __builtin_aarch64_simd_di *) __a);
-+  ret.val[0] = (uint64x1_t) __builtin_aarch64_get_dregcidi (__o, 0);
-+  ret.val[1] = (uint64x1_t) __builtin_aarch64_get_dregcidi (__o, 1);
-+  ret.val[2] = (uint64x1_t) __builtin_aarch64_get_dregcidi (__o, 2);
-+  return ret;
-+}
-+
-+__extension__ static __inline float64x1x3_t __attribute__ ((__always_inline__))
-+vld3_dup_f64 (const float64_t * __a)
-+{
-+  float64x1x3_t ret;
-+  __builtin_aarch64_simd_ci __o;
-+  __o = __builtin_aarch64_ld3rdf ((const __builtin_aarch64_simd_df *) __a);
-+  ret.val[0] = (float64x1_t) {__builtin_aarch64_get_dregcidf (__o, 0)};
-+  ret.val[1] = (float64x1_t) {__builtin_aarch64_get_dregcidf (__o, 1)};
-+  ret.val[2] = (float64x1_t) {__builtin_aarch64_get_dregcidf (__o, 2)};
-+  return ret;
-+}
-+
-+__extension__ static __inline int8x8x3_t __attribute__ ((__always_inline__))
-+vld3_dup_s8 (const int8_t * __a)
-+{
-+  int8x8x3_t ret;
-+  __builtin_aarch64_simd_ci __o;
-+  __o = __builtin_aarch64_ld3rv8qi ((const __builtin_aarch64_simd_qi *) __a);
-+  ret.val[0] = (int8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 0);
-+  ret.val[1] = (int8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 1);
-+  ret.val[2] = (int8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 2);
-+  return ret;
-+}
-+
-+__extension__ static __inline poly8x8x3_t __attribute__ ((__always_inline__))
-+vld3_dup_p8 (const poly8_t * __a)
-+{
-+  poly8x8x3_t ret;
-+  __builtin_aarch64_simd_ci __o;
-+  __o = __builtin_aarch64_ld3rv8qi ((const __builtin_aarch64_simd_qi *) __a);
-+  ret.val[0] = (poly8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 0);
-+  ret.val[1] = (poly8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 1);
-+  ret.val[2] = (poly8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 2);
-+  return ret;
-+}
-+
-+__extension__ static __inline int16x4x3_t __attribute__ ((__always_inline__))
-+vld3_dup_s16 (const int16_t * __a)
-+{
-+  int16x4x3_t ret;
-+  __builtin_aarch64_simd_ci __o;
-+  __o = __builtin_aarch64_ld3rv4hi ((const __builtin_aarch64_simd_hi *) __a);
-+  ret.val[0] = (int16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 0);
-+  ret.val[1] = (int16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 1);
-+  ret.val[2] = (int16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 2);
-+  return ret;
-+}
-+
-+__extension__ static __inline poly16x4x3_t __attribute__ ((__always_inline__))
-+vld3_dup_p16 (const poly16_t * __a)
-+{
-+  poly16x4x3_t ret;
-+  __builtin_aarch64_simd_ci __o;
-+  __o = __builtin_aarch64_ld3rv4hi ((const __builtin_aarch64_simd_hi *) __a);
-+  ret.val[0] = (poly16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 0);
-+  ret.val[1] = (poly16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 1);
-+  ret.val[2] = (poly16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 2);
-+  return ret;
-+}
-+
-+__extension__ static __inline int32x2x3_t __attribute__ ((__always_inline__))
-+vld3_dup_s32 (const int32_t * __a)
-+{
-+  int32x2x3_t ret;
-+  __builtin_aarch64_simd_ci __o;
-+  __o = __builtin_aarch64_ld3rv2si ((const __builtin_aarch64_simd_si *) __a);
-+  ret.val[0] = (int32x2_t) __builtin_aarch64_get_dregciv2si (__o, 0);
-+  ret.val[1] = (int32x2_t) __builtin_aarch64_get_dregciv2si (__o, 1);
-+  ret.val[2] = (int32x2_t) __builtin_aarch64_get_dregciv2si (__o, 2);
-+  return ret;
-+}
-+
-+__extension__ static __inline uint8x8x3_t __attribute__ ((__always_inline__))
-+vld3_dup_u8 (const uint8_t * __a)
-+{
-+  uint8x8x3_t ret;
-+  __builtin_aarch64_simd_ci __o;
-+  __o = __builtin_aarch64_ld3rv8qi ((const __builtin_aarch64_simd_qi *) __a);
-+  ret.val[0] = (uint8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 0);
-+  ret.val[1] = (uint8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 1);
-+  ret.val[2] = (uint8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 2);
-+  return ret;
-+}
-+
-+__extension__ static __inline uint16x4x3_t __attribute__ ((__always_inline__))
-+vld3_dup_u16 (const uint16_t * __a)
-+{
-+  uint16x4x3_t ret;
-+  __builtin_aarch64_simd_ci __o;
-+  __o = __builtin_aarch64_ld3rv4hi ((const __builtin_aarch64_simd_hi *) __a);
-+  ret.val[0] = (uint16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 0);
-+  ret.val[1] = (uint16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 1);
-+  ret.val[2] = (uint16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 2);
-+  return ret;
-+}
-+
-+__extension__ static __inline uint32x2x3_t __attribute__ ((__always_inline__))
-+vld3_dup_u32 (const uint32_t * __a)
-+{
-+  uint32x2x3_t ret;
-+  __builtin_aarch64_simd_ci __o;
-+  __o = __builtin_aarch64_ld3rv2si ((const __builtin_aarch64_simd_si *) __a);
-+  ret.val[0] = (uint32x2_t) __builtin_aarch64_get_dregciv2si (__o, 0);
-+  ret.val[1] = (uint32x2_t) __builtin_aarch64_get_dregciv2si (__o, 1);
-+  ret.val[2] = (uint32x2_t) __builtin_aarch64_get_dregciv2si (__o, 2);
-+  return ret;
-+}
-+
-+__extension__ static __inline float32x2x3_t __attribute__ ((__always_inline__))
-+vld3_dup_f32 (const float32_t * __a)
-+{
-+  float32x2x3_t ret;
-+  __builtin_aarch64_simd_ci __o;
-+  __o = __builtin_aarch64_ld3rv2sf ((const __builtin_aarch64_simd_sf *) __a);
-+  ret.val[0] = (float32x2_t) __builtin_aarch64_get_dregciv2sf (__o, 0);
-+  ret.val[1] = (float32x2_t) __builtin_aarch64_get_dregciv2sf (__o, 1);
-+  ret.val[2] = (float32x2_t) __builtin_aarch64_get_dregciv2sf (__o, 2);
-+  return ret;
-+}
-+
-+__extension__ static __inline int8x16x3_t __attribute__ ((__always_inline__))
-+vld3q_dup_s8 (const int8_t * __a)
-+{
-+  int8x16x3_t ret;
-+  __builtin_aarch64_simd_ci __o;
-+  __o = __builtin_aarch64_ld3rv16qi ((const __builtin_aarch64_simd_qi *) __a);
-+  ret.val[0] = (int8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 0);
-+  ret.val[1] = (int8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 1);
-+  ret.val[2] = (int8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 2);
-+  return ret;
-+}
-+
-+__extension__ static __inline poly8x16x3_t __attribute__ ((__always_inline__))
-+vld3q_dup_p8 (const poly8_t * __a)
-+{
-+  poly8x16x3_t ret;
-+  __builtin_aarch64_simd_ci __o;
-+  __o = __builtin_aarch64_ld3rv16qi ((const __builtin_aarch64_simd_qi *) __a);
-+  ret.val[0] = (poly8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 0);
-+  ret.val[1] = (poly8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 1);
-+  ret.val[2] = (poly8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 2);
-+  return ret;
-+}
-+
-+__extension__ static __inline int16x8x3_t __attribute__ ((__always_inline__))
-+vld3q_dup_s16 (const int16_t * __a)
-+{
-+  int16x8x3_t ret;
-+  __builtin_aarch64_simd_ci __o;
-+  __o = __builtin_aarch64_ld3rv8hi ((const __builtin_aarch64_simd_hi *) __a);
-+  ret.val[0] = (int16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 0);
-+  ret.val[1] = (int16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 1);
-+  ret.val[2] = (int16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 2);
-+  return ret;
-+}
-+
-+__extension__ static __inline poly16x8x3_t __attribute__ ((__always_inline__))
-+vld3q_dup_p16 (const poly16_t * __a)
-+{
-+  poly16x8x3_t ret;
-+  __builtin_aarch64_simd_ci __o;
-+  __o = __builtin_aarch64_ld3rv8hi ((const __builtin_aarch64_simd_hi *) __a);
-+  ret.val[0] = (poly16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 0);
-+  ret.val[1] = (poly16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 1);
-+  ret.val[2] = (poly16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 2);
-+  return ret;
-+}
-+
-+__extension__ static __inline int32x4x3_t __attribute__ ((__always_inline__))
-+vld3q_dup_s32 (const int32_t * __a)
-+{
-+  int32x4x3_t ret;
-+  __builtin_aarch64_simd_ci __o;
-+  __o = __builtin_aarch64_ld3rv4si ((const __builtin_aarch64_simd_si *) __a);
-+  ret.val[0] = (int32x4_t) __builtin_aarch64_get_qregciv4si (__o, 0);
-+  ret.val[1] = (int32x4_t) __builtin_aarch64_get_qregciv4si (__o, 1);
-+  ret.val[2] = (int32x4_t) __builtin_aarch64_get_qregciv4si (__o, 2);
-+  return ret;
-+}
-+
-+__extension__ static __inline int64x2x3_t __attribute__ ((__always_inline__))
-+vld3q_dup_s64 (const int64_t * __a)
-+{
-+  int64x2x3_t ret;
-+  __builtin_aarch64_simd_ci __o;
-+  __o = __builtin_aarch64_ld3rv2di ((const __builtin_aarch64_simd_di *) __a);
-+  ret.val[0] = (int64x2_t) __builtin_aarch64_get_qregciv2di (__o, 0);
-+  ret.val[1] = (int64x2_t) __builtin_aarch64_get_qregciv2di (__o, 1);
-+  ret.val[2] = (int64x2_t) __builtin_aarch64_get_qregciv2di (__o, 2);
-+  return ret;
-+}
-+
-+__extension__ static __inline uint8x16x3_t __attribute__ ((__always_inline__))
-+vld3q_dup_u8 (const uint8_t * __a)
-+{
-+  uint8x16x3_t ret;
-+  __builtin_aarch64_simd_ci __o;
-+  __o = __builtin_aarch64_ld3rv16qi ((const __builtin_aarch64_simd_qi *) __a);
-+  ret.val[0] = (uint8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 0);
-+  ret.val[1] = (uint8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 1);
-+  ret.val[2] = (uint8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 2);
-+  return ret;
-+}
-+
-+__extension__ static __inline uint16x8x3_t __attribute__ ((__always_inline__))
-+vld3q_dup_u16 (const uint16_t * __a)
-+{
-+  uint16x8x3_t ret;
-+  __builtin_aarch64_simd_ci __o;
-+  __o = __builtin_aarch64_ld3rv8hi ((const __builtin_aarch64_simd_hi *) __a);
-+  ret.val[0] = (uint16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 0);
-+  ret.val[1] = (uint16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 1);
-+  ret.val[2] = (uint16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 2);
-+  return ret;
-+}
-+
-+__extension__ static __inline uint32x4x3_t __attribute__ ((__always_inline__))
-+vld3q_dup_u32 (const uint32_t * __a)
-+{
-+  uint32x4x3_t ret;
-+  __builtin_aarch64_simd_ci __o;
-+  __o = __builtin_aarch64_ld3rv4si ((const __builtin_aarch64_simd_si *) __a);
-+  ret.val[0] = (uint32x4_t) __builtin_aarch64_get_qregciv4si (__o, 0);
-+  ret.val[1] = (uint32x4_t) __builtin_aarch64_get_qregciv4si (__o, 1);
-+  ret.val[2] = (uint32x4_t) __builtin_aarch64_get_qregciv4si (__o, 2);
-+  return ret;
-+}
-+
-+__extension__ static __inline uint64x2x3_t __attribute__ ((__always_inline__))
-+vld3q_dup_u64 (const uint64_t * __a)
-+{
-+  uint64x2x3_t ret;
-+  __builtin_aarch64_simd_ci __o;
-+  __o = __builtin_aarch64_ld3rv2di ((const __builtin_aarch64_simd_di *) __a);
-+  ret.val[0] = (uint64x2_t) __builtin_aarch64_get_qregciv2di (__o, 0);
-+  ret.val[1] = (uint64x2_t) __builtin_aarch64_get_qregciv2di (__o, 1);
-+  ret.val[2] = (uint64x2_t) __builtin_aarch64_get_qregciv2di (__o, 2);
-+  return ret;
-+}
-+
-+__extension__ static __inline float32x4x3_t __attribute__ ((__always_inline__))
-+vld3q_dup_f32 (const float32_t * __a)
-+{
-+  float32x4x3_t ret;
-+  __builtin_aarch64_simd_ci __o;
-+  __o = __builtin_aarch64_ld3rv4sf ((const __builtin_aarch64_simd_sf *) __a);
-+  ret.val[0] = (float32x4_t) __builtin_aarch64_get_qregciv4sf (__o, 0);
-+  ret.val[1] = (float32x4_t) __builtin_aarch64_get_qregciv4sf (__o, 1);
-+  ret.val[2] = (float32x4_t) __builtin_aarch64_get_qregciv4sf (__o, 2);
-+  return ret;
-+}
-+
-+__extension__ static __inline float64x2x3_t __attribute__ ((__always_inline__))
-+vld3q_dup_f64 (const float64_t * __a)
-+{
-+  float64x2x3_t ret;
-+  __builtin_aarch64_simd_ci __o;
-+  __o = __builtin_aarch64_ld3rv2df ((const __builtin_aarch64_simd_df *) __a);
-+  ret.val[0] = (float64x2_t) __builtin_aarch64_get_qregciv2df (__o, 0);
-+  ret.val[1] = (float64x2_t) __builtin_aarch64_get_qregciv2df (__o, 1);
-+  ret.val[2] = (float64x2_t) __builtin_aarch64_get_qregciv2df (__o, 2);
-+  return ret;
-+}
-+
-+__extension__ static __inline int64x1x4_t __attribute__ ((__always_inline__))
-+vld4_dup_s64 (const int64_t * __a)
-+{
-+  int64x1x4_t ret;
-+  __builtin_aarch64_simd_xi __o;
-+  __o = __builtin_aarch64_ld4rdi ((const __builtin_aarch64_simd_di *) __a);
-+  ret.val[0] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 0);
-+  ret.val[1] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 1);
-+  ret.val[2] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 2);
-+  ret.val[3] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 3);
-+  return ret;
-+}
-+
-+__extension__ static __inline uint64x1x4_t __attribute__ ((__always_inline__))
-+vld4_dup_u64 (const uint64_t * __a)
-+{
-+  uint64x1x4_t ret;
-+  __builtin_aarch64_simd_xi __o;
-+  __o = __builtin_aarch64_ld4rdi ((const __builtin_aarch64_simd_di *) __a);
-+  ret.val[0] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 0);
-+  ret.val[1] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 1);
-+  ret.val[2] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 2);
-+  ret.val[3] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 3);
-+  return ret;
-+}
-+
-+__extension__ static __inline float64x1x4_t __attribute__ ((__always_inline__))
-+vld4_dup_f64 (const float64_t * __a)
-+{
-+  float64x1x4_t ret;
-+  __builtin_aarch64_simd_xi __o;
-+  __o = __builtin_aarch64_ld4rdf ((const __builtin_aarch64_simd_df *) __a);
-+  ret.val[0] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 0)};
-+  ret.val[1] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 1)};
-+  ret.val[2] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 2)};
-+  ret.val[3] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 3)};
-+  return ret;
-+}
-+
-+__extension__ static __inline int8x8x4_t __attribute__ ((__always_inline__))
-+vld4_dup_s8 (const int8_t * __a)
-+{
-+  int8x8x4_t ret;
-+  __builtin_aarch64_simd_xi __o;
-+  __o = __builtin_aarch64_ld4rv8qi ((const __builtin_aarch64_simd_qi *) __a);
-+  ret.val[0] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 0);
-+  ret.val[1] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 1);
-+  ret.val[2] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 2);
-+  ret.val[3] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 3);
-+  return ret;
-+}
-+
-+__extension__ static __inline poly8x8x4_t __attribute__ ((__always_inline__))
-+vld4_dup_p8 (const poly8_t * __a)
-+{
-+  poly8x8x4_t ret;
-+  __builtin_aarch64_simd_xi __o;
-+  __o = __builtin_aarch64_ld4rv8qi ((const __builtin_aarch64_simd_qi *) __a);
-+  ret.val[0] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 0);
-+  ret.val[1] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 1);
-+  ret.val[2] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 2);
-+  ret.val[3] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 3);
-+  return ret;
-+}
-+
-+__extension__ static __inline int16x4x4_t __attribute__ ((__always_inline__))
-+vld4_dup_s16 (const int16_t * __a)
-+{
-+  int16x4x4_t ret;
-+  __builtin_aarch64_simd_xi __o;
-+  __o = __builtin_aarch64_ld4rv4hi ((const __builtin_aarch64_simd_hi *) __a);
-+  ret.val[0] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 0);
-+  ret.val[1] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 1);
-+  ret.val[2] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 2);
-+  ret.val[3] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 3);
-+  return ret;
-+}
-+
-+__extension__ static __inline poly16x4x4_t __attribute__ ((__always_inline__))
-+vld4_dup_p16 (const poly16_t * __a)
-+{
-+  poly16x4x4_t ret;
-+  __builtin_aarch64_simd_xi __o;
-+  __o = __builtin_aarch64_ld4rv4hi ((const __builtin_aarch64_simd_hi *) __a);
-+  ret.val[0] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 0);
-+  ret.val[1] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 1);
-+  ret.val[2] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 2);
-+  ret.val[3] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 3);
-+  return ret;
-+}
-+
-+__extension__ static __inline int32x2x4_t __attribute__ ((__always_inline__))
-+vld4_dup_s32 (const int32_t * __a)
-+{
-+  int32x2x4_t ret;
-+  __builtin_aarch64_simd_xi __o;
-+  __o = __builtin_aarch64_ld4rv2si ((const __builtin_aarch64_simd_si *) __a);
-+  ret.val[0] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 0);
-+  ret.val[1] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 1);
-+  ret.val[2] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 2);
-+  ret.val[3] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 3);
-+  return ret;
-+}
-+
-+__extension__ static __inline uint8x8x4_t __attribute__ ((__always_inline__))
-+vld4_dup_u8 (const uint8_t * __a)
-+{
-+  uint8x8x4_t ret;
-+  __builtin_aarch64_simd_xi __o;
-+  __o = __builtin_aarch64_ld4rv8qi ((const __builtin_aarch64_simd_qi *) __a);
-+  ret.val[0] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 0);
-+  ret.val[1] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 1);
-+  ret.val[2] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 2);
-+  ret.val[3] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 3);
-+  return ret;
-+}
-+
-+__extension__ static __inline uint16x4x4_t __attribute__ ((__always_inline__))
-+vld4_dup_u16 (const uint16_t * __a)
-+{
-+  uint16x4x4_t ret;
-+  __builtin_aarch64_simd_xi __o;
-+  __o = __builtin_aarch64_ld4rv4hi ((const __builtin_aarch64_simd_hi *) __a);
-+  ret.val[0] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 0);
-+  ret.val[1] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 1);
-+  ret.val[2] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 2);
-+  ret.val[3] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 3);
-+  return ret;
-+}
-+
-+__extension__ static __inline uint32x2x4_t __attribute__ ((__always_inline__))
-+vld4_dup_u32 (const uint32_t * __a)
-+{
-+  uint32x2x4_t ret;
-+  __builtin_aarch64_simd_xi __o;
-+  __o = __builtin_aarch64_ld4rv2si ((const __builtin_aarch64_simd_si *) __a);
-+  ret.val[0] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 0);
-+  ret.val[1] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 1);
-+  ret.val[2] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 2);
-+  ret.val[3] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 3);
-+  return ret;
-+}
-+
-+__extension__ static __inline float32x2x4_t __attribute__ ((__always_inline__))
-+vld4_dup_f32 (const float32_t * __a)
-+{
-+  float32x2x4_t ret;
-+  __builtin_aarch64_simd_xi __o;
-+  __o = __builtin_aarch64_ld4rv2sf ((const __builtin_aarch64_simd_sf *) __a);
-+  ret.val[0] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 0);
-+  ret.val[1] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 1);
-+  ret.val[2] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 2);
-+  ret.val[3] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 3);
-+  return ret;
-+}
-+
-+__extension__ static __inline int8x16x4_t __attribute__ ((__always_inline__))
-+vld4q_dup_s8 (const int8_t * __a)
-+{
-+  int8x16x4_t ret;
-+  __builtin_aarch64_simd_xi __o;
-+  __o = __builtin_aarch64_ld4rv16qi ((const __builtin_aarch64_simd_qi *) __a);
-+  ret.val[0] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 0);
-+  ret.val[1] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 1);
-+  ret.val[2] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 2);
-+  ret.val[3] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 3);
-+  return ret;
-+}
-+
-+__extension__ static __inline poly8x16x4_t __attribute__ ((__always_inline__))
-+vld4q_dup_p8 (const poly8_t * __a)
-+{
-+  poly8x16x4_t ret;
-+  __builtin_aarch64_simd_xi __o;
-+  __o = __builtin_aarch64_ld4rv16qi ((const __builtin_aarch64_simd_qi *) __a);
-+  ret.val[0] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 0);
-+  ret.val[1] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 1);
-+  ret.val[2] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 2);
-+  ret.val[3] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 3);
-+  return ret;
-+}
-+
-+__extension__ static __inline int16x8x4_t __attribute__ ((__always_inline__))
-+vld4q_dup_s16 (const int16_t * __a)
-+{
-+  int16x8x4_t ret;
-+  __builtin_aarch64_simd_xi __o;
-+  __o = __builtin_aarch64_ld4rv8hi ((const __builtin_aarch64_simd_hi *) __a);
-+  ret.val[0] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 0);
-+  ret.val[1] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 1);
-+  ret.val[2] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 2);
-+  ret.val[3] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 3);
-+  return ret;
-+}
-+
-+__extension__ static __inline poly16x8x4_t __attribute__ ((__always_inline__))
-+vld4q_dup_p16 (const poly16_t * __a)
-+{
-+  poly16x8x4_t ret;
-+  __builtin_aarch64_simd_xi __o;
-+  __o = __builtin_aarch64_ld4rv8hi ((const __builtin_aarch64_simd_hi *) __a);
-+  ret.val[0] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 0);
-+  ret.val[1] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 1);
-+  ret.val[2] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 2);
-+  ret.val[3] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 3);
-+  return ret;
-+}
-+
-+__extension__ static __inline int32x4x4_t __attribute__ ((__always_inline__))
-+vld4q_dup_s32 (const int32_t * __a)
-+{
-+  int32x4x4_t ret;
-+  __builtin_aarch64_simd_xi __o;
-+  __o = __builtin_aarch64_ld4rv4si ((const __builtin_aarch64_simd_si *) __a);
-+  ret.val[0] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 0);
-+  ret.val[1] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 1);
-+  ret.val[2] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 2);
-+  ret.val[3] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 3);
-+  return ret;
-+}
-+
-+__extension__ static __inline int64x2x4_t __attribute__ ((__always_inline__))
-+vld4q_dup_s64 (const int64_t * __a)
-+{
-+  int64x2x4_t ret;
-+  __builtin_aarch64_simd_xi __o;
-+  __o = __builtin_aarch64_ld4rv2di ((const __builtin_aarch64_simd_di *) __a);
-+  ret.val[0] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 0);
-+  ret.val[1] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 1);
-+  ret.val[2] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 2);
-+  ret.val[3] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 3);
-+  return ret;
-+}
-+
-+__extension__ static __inline uint8x16x4_t __attribute__ ((__always_inline__))
-+vld4q_dup_u8 (const uint8_t * __a)
-+{
-+  uint8x16x4_t ret;
-+  __builtin_aarch64_simd_xi __o;
-+  __o = __builtin_aarch64_ld4rv16qi ((const __builtin_aarch64_simd_qi *) __a);
-+  ret.val[0] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 0);
-+  ret.val[1] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 1);
-+  ret.val[2] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 2);
-+  ret.val[3] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 3);
-+  return ret;
-+}
-+
-+__extension__ static __inline uint16x8x4_t __attribute__ ((__always_inline__))
-+vld4q_dup_u16 (const uint16_t * __a)
-+{
-+  uint16x8x4_t ret;
-+  __builtin_aarch64_simd_xi __o;
-+  __o = __builtin_aarch64_ld4rv8hi ((const __builtin_aarch64_simd_hi *) __a);
-+  ret.val[0] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 0);
-+  ret.val[1] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 1);
-+  ret.val[2] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 2);
-+  ret.val[3] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 3);
-+  return ret;
-+}
-+
-+__extension__ static __inline uint32x4x4_t __attribute__ ((__always_inline__))
-+vld4q_dup_u32 (const uint32_t * __a)
-+{
-+  uint32x4x4_t ret;
-+  __builtin_aarch64_simd_xi __o;
-+  __o = __builtin_aarch64_ld4rv4si ((const __builtin_aarch64_simd_si *) __a);
-+  ret.val[0] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 0);
-+  ret.val[1] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 1);
-+  ret.val[2] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 2);
-+  ret.val[3] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 3);
-+  return ret;
-+}
-+
-+__extension__ static __inline uint64x2x4_t __attribute__ ((__always_inline__))
-+vld4q_dup_u64 (const uint64_t * __a)
-+{
-+  uint64x2x4_t ret;
-+  __builtin_aarch64_simd_xi __o;
-+  __o = __builtin_aarch64_ld4rv2di ((const __builtin_aarch64_simd_di *) __a);
-+  ret.val[0] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 0);
-+  ret.val[1] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 1);
-+  ret.val[2] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 2);
-+  ret.val[3] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 3);
-+  return ret;
-+}
-+
-+__extension__ static __inline float32x4x4_t __attribute__ ((__always_inline__))
-+vld4q_dup_f32 (const float32_t * __a)
-+{
-+  float32x4x4_t ret;
-+  __builtin_aarch64_simd_xi __o;
-+  __o = __builtin_aarch64_ld4rv4sf ((const __builtin_aarch64_simd_sf *) __a);
-+  ret.val[0] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 0);
-+  ret.val[1] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 1);
-+  ret.val[2] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 2);
-+  ret.val[3] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 3);
-+  return ret;
-+}
-+
-+__extension__ static __inline float64x2x4_t __attribute__ ((__always_inline__))
-+vld4q_dup_f64 (const float64_t * __a)
-+{
-+  float64x2x4_t ret;
-+  __builtin_aarch64_simd_xi __o;
-+  __o = __builtin_aarch64_ld4rv2df ((const __builtin_aarch64_simd_df *) __a);
-+  ret.val[0] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 0);
-+  ret.val[1] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 1);
-+  ret.val[2] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 2);
-+  ret.val[3] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 3);
-+  return ret;
-+}
-+
- /* vmax */
- 
- __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
-@@ -20911,6 +19596,65 @@
-   return -__a;
- }
- 
-+/* vpadd  */
-+
-+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
-+vpadd_s8 (int8x8_t __a, int8x8_t __b)
-+{
-+  return __builtin_aarch64_addpv8qi (__a, __b);
-+}
-+
-+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
-+vpadd_s16 (int16x4_t __a, int16x4_t __b)
-+{
-+  return __builtin_aarch64_addpv4hi (__a, __b);
-+}
-+
-+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
-+vpadd_s32 (int32x2_t __a, int32x2_t __b)
-+{
-+  return __builtin_aarch64_addpv2si (__a, __b);
-+}
-+
-+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
-+vpadd_u8 (uint8x8_t __a, uint8x8_t __b)
-+{
-+  return (uint8x8_t) __builtin_aarch64_addpv8qi ((int8x8_t) __a,
-+						 (int8x8_t) __b);
-+}
-+
-+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
-+vpadd_u16 (uint16x4_t __a, uint16x4_t __b)
-+{
-+  return (uint16x4_t) __builtin_aarch64_addpv4hi ((int16x4_t) __a,
-+						  (int16x4_t) __b);
-+}
-+
-+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
-+vpadd_u32 (uint32x2_t __a, uint32x2_t __b)
-+{
-+  return (uint32x2_t) __builtin_aarch64_addpv2si ((int32x2_t) __a,
-+						  (int32x2_t) __b);
-+}
-+
-+__extension__ static __inline float64_t __attribute__ ((__always_inline__))
-+vpaddd_f64 (float64x2_t __a)
-+{
-+  return vgetq_lane_f64 (__builtin_aarch64_reduc_splus_v2df (__a), 0);
-+}
-+
-+__extension__ static __inline int64_t __attribute__ ((__always_inline__))
-+vpaddd_s64 (int64x2_t __a)
-+{
-+  return __builtin_aarch64_addpdi (__a);
-+}
-+
-+__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
-+vpaddd_u64 (uint64x2_t __a)
-+{
-+  return __builtin_aarch64_addpdi ((int64x2_t) __a);
-+}
-+
- /* vqabs */
- 
- __extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
-@@ -20937,6 +19681,12 @@
-   return (int32_t) __builtin_aarch64_sqabssi (__a);
- }
- 
-+__extension__ static __inline int64_t __attribute__ ((__always_inline__))
-+vqabsd_s64 (int64_t __a)
-+{
-+  return __builtin_aarch64_sqabsdi (__a);
-+}
-+
- /* vqadd */
- 
- __extension__ static __inline int8_t __attribute__ ((__always_inline__))
-@@ -20966,25 +19716,26 @@
- __extension__ static __inline uint8_t __attribute__ ((__always_inline__))
- vqaddb_u8 (uint8_t __a, uint8_t __b)
- {
--  return (uint8_t) __builtin_aarch64_uqaddqi (__a, __b);
-+  return (uint8_t) __builtin_aarch64_uqaddqi_uuu (__a, __b);
- }
- 
- __extension__ static __inline uint16_t __attribute__ ((__always_inline__))
- vqaddh_u16 (uint16_t __a, uint16_t __b)
- {
--  return (uint16_t) __builtin_aarch64_uqaddhi (__a, __b);
-+  return (uint16_t) __builtin_aarch64_uqaddhi_uuu (__a, __b);
- }
- 
- __extension__ static __inline uint32_t __attribute__ ((__always_inline__))
- vqadds_u32 (uint32_t __a, uint32_t __b)
- {
--  return (uint32_t) __builtin_aarch64_uqaddsi (__a, __b);
-+  return (uint32_t) __builtin_aarch64_uqaddsi_uuu (__a, __b);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vqaddd_u64 (uint64x1_t __a, uint64x1_t __b)
- {
--  return (uint64x1_t) __builtin_aarch64_uqadddi (__a, __b);
-+  return (uint64x1_t) __builtin_aarch64_uqadddi_uuu ((uint64_t) __a,
-+						     (uint64_t) __b);
- }
- 
- /* vqdmlal */
-@@ -21549,6 +20300,12 @@
-   return (int32_t) __builtin_aarch64_sqnegsi (__a);
- }
- 
-+__extension__ static __inline int64_t __attribute__ ((__always_inline__))
-+vqnegd_s64 (int64_t __a)
-+{
-+  return __builtin_aarch64_sqnegdi (__a);
-+}
-+
- /* vqrdmulh */
- 
- __extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
-@@ -21628,25 +20385,25 @@
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vqrshl_u8 (uint8x8_t __a, int8x8_t __b)
- {
--  return (uint8x8_t) __builtin_aarch64_uqrshlv8qi ((int8x8_t) __a, __b);
-+  return __builtin_aarch64_uqrshlv8qi_uus ( __a, __b);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vqrshl_u16 (uint16x4_t __a, int16x4_t __b)
- {
--  return (uint16x4_t) __builtin_aarch64_uqrshlv4hi ((int16x4_t) __a, __b);
-+  return __builtin_aarch64_uqrshlv4hi_uus ( __a, __b);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vqrshl_u32 (uint32x2_t __a, int32x2_t __b)
- {
--  return (uint32x2_t) __builtin_aarch64_uqrshlv2si ((int32x2_t) __a, __b);
-+  return __builtin_aarch64_uqrshlv2si_uus ( __a, __b);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vqrshl_u64 (uint64x1_t __a, int64x1_t __b)
- {
--  return (uint64x1_t) __builtin_aarch64_uqrshldi ((int64x1_t) __a, __b);
-+  return __builtin_aarch64_uqrshldi_uus ( __a, __b);
- }
- 
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
-@@ -21676,25 +20433,25 @@
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vqrshlq_u8 (uint8x16_t __a, int8x16_t __b)
- {
--  return (uint8x16_t) __builtin_aarch64_uqrshlv16qi ((int8x16_t) __a, __b);
-+  return __builtin_aarch64_uqrshlv16qi_uus ( __a, __b);
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vqrshlq_u16 (uint16x8_t __a, int16x8_t __b)
- {
--  return (uint16x8_t) __builtin_aarch64_uqrshlv8hi ((int16x8_t) __a, __b);
-+  return __builtin_aarch64_uqrshlv8hi_uus ( __a, __b);
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vqrshlq_u32 (uint32x4_t __a, int32x4_t __b)
- {
--  return (uint32x4_t) __builtin_aarch64_uqrshlv4si ((int32x4_t) __a, __b);
-+  return __builtin_aarch64_uqrshlv4si_uus ( __a, __b);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vqrshlq_u64 (uint64x2_t __a, int64x2_t __b)
- {
--  return (uint64x2_t) __builtin_aarch64_uqrshlv2di ((int64x2_t) __a, __b);
-+  return __builtin_aarch64_uqrshlv2di_uus ( __a, __b);
- }
- 
- __extension__ static __inline int8_t __attribute__ ((__always_inline__))
-@@ -21724,25 +20481,25 @@
- __extension__ static __inline uint8_t __attribute__ ((__always_inline__))
- vqrshlb_u8 (uint8_t __a, uint8_t __b)
- {
--  return (uint8_t) __builtin_aarch64_uqrshlqi (__a, __b);
-+  return __builtin_aarch64_uqrshlqi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint16_t __attribute__ ((__always_inline__))
- vqrshlh_u16 (uint16_t __a, uint16_t __b)
- {
--  return (uint16_t) __builtin_aarch64_uqrshlhi (__a, __b);
-+  return __builtin_aarch64_uqrshlhi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint32_t __attribute__ ((__always_inline__))
- vqrshls_u32 (uint32_t __a, uint32_t __b)
- {
--  return (uint32_t) __builtin_aarch64_uqrshlsi (__a, __b);
-+  return __builtin_aarch64_uqrshlsi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vqrshld_u64 (uint64x1_t __a, uint64x1_t __b)
- {
--  return (uint64x1_t) __builtin_aarch64_uqrshldi (__a, __b);
-+  return __builtin_aarch64_uqrshldi_uus (__a, __b);
- }
- 
- /* vqrshrn */
-@@ -21768,19 +20525,19 @@
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vqrshrn_n_u16 (uint16x8_t __a, const int __b)
- {
--  return (uint8x8_t) __builtin_aarch64_uqrshrn_nv8hi ((int16x8_t) __a, __b);
-+  return __builtin_aarch64_uqrshrn_nv8hi_uus ( __a, __b);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vqrshrn_n_u32 (uint32x4_t __a, const int __b)
- {
--  return (uint16x4_t) __builtin_aarch64_uqrshrn_nv4si ((int32x4_t) __a, __b);
-+  return __builtin_aarch64_uqrshrn_nv4si_uus ( __a, __b);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vqrshrn_n_u64 (uint64x2_t __a, const int __b)
- {
--  return (uint32x2_t) __builtin_aarch64_uqrshrn_nv2di ((int64x2_t) __a, __b);
-+  return __builtin_aarch64_uqrshrn_nv2di_uus ( __a, __b);
- }
- 
- __extension__ static __inline int8_t __attribute__ ((__always_inline__))
-@@ -21804,19 +20561,19 @@
- __extension__ static __inline uint8_t __attribute__ ((__always_inline__))
- vqrshrnh_n_u16 (uint16_t __a, const int __b)
- {
--  return (uint8_t) __builtin_aarch64_uqrshrn_nhi (__a, __b);
-+  return __builtin_aarch64_uqrshrn_nhi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint16_t __attribute__ ((__always_inline__))
- vqrshrns_n_u32 (uint32_t __a, const int __b)
- {
--  return (uint16_t) __builtin_aarch64_uqrshrn_nsi (__a, __b);
-+  return __builtin_aarch64_uqrshrn_nsi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint32_t __attribute__ ((__always_inline__))
- vqrshrnd_n_u64 (uint64x1_t __a, const int __b)
- {
--  return (uint32_t) __builtin_aarch64_uqrshrn_ndi (__a, __b);
-+  return __builtin_aarch64_uqrshrn_ndi_uus (__a, __b);
- }
- 
- /* vqrshrun */
-@@ -21886,25 +20643,25 @@
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vqshl_u8 (uint8x8_t __a, int8x8_t __b)
- {
--  return (uint8x8_t) __builtin_aarch64_uqshlv8qi ((int8x8_t) __a, __b);
-+  return __builtin_aarch64_uqshlv8qi_uus ( __a, __b);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vqshl_u16 (uint16x4_t __a, int16x4_t __b)
- {
--  return (uint16x4_t) __builtin_aarch64_uqshlv4hi ((int16x4_t) __a, __b);
-+  return __builtin_aarch64_uqshlv4hi_uus ( __a, __b);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vqshl_u32 (uint32x2_t __a, int32x2_t __b)
- {
--  return (uint32x2_t) __builtin_aarch64_uqshlv2si ((int32x2_t) __a, __b);
-+  return __builtin_aarch64_uqshlv2si_uus ( __a, __b);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vqshl_u64 (uint64x1_t __a, int64x1_t __b)
- {
--  return (uint64x1_t) __builtin_aarch64_uqshldi ((int64x1_t) __a, __b);
-+  return __builtin_aarch64_uqshldi_uus ( __a, __b);
- }
- 
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
-@@ -21934,25 +20691,25 @@
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vqshlq_u8 (uint8x16_t __a, int8x16_t __b)
- {
--  return (uint8x16_t) __builtin_aarch64_uqshlv16qi ((int8x16_t) __a, __b);
-+  return __builtin_aarch64_uqshlv16qi_uus ( __a, __b);
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vqshlq_u16 (uint16x8_t __a, int16x8_t __b)
- {
--  return (uint16x8_t) __builtin_aarch64_uqshlv8hi ((int16x8_t) __a, __b);
-+  return __builtin_aarch64_uqshlv8hi_uus ( __a, __b);
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vqshlq_u32 (uint32x4_t __a, int32x4_t __b)
- {
--  return (uint32x4_t) __builtin_aarch64_uqshlv4si ((int32x4_t) __a, __b);
-+  return __builtin_aarch64_uqshlv4si_uus ( __a, __b);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vqshlq_u64 (uint64x2_t __a, int64x2_t __b)
- {
--  return (uint64x2_t) __builtin_aarch64_uqshlv2di ((int64x2_t) __a, __b);
-+  return __builtin_aarch64_uqshlv2di_uus ( __a, __b);
- }
- 
- __extension__ static __inline int8_t __attribute__ ((__always_inline__))
-@@ -21982,25 +20739,25 @@
- __extension__ static __inline uint8_t __attribute__ ((__always_inline__))
- vqshlb_u8 (uint8_t __a, uint8_t __b)
- {
--  return (uint8_t) __builtin_aarch64_uqshlqi (__a, __b);
-+  return __builtin_aarch64_uqshlqi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint16_t __attribute__ ((__always_inline__))
- vqshlh_u16 (uint16_t __a, uint16_t __b)
- {
--  return (uint16_t) __builtin_aarch64_uqshlhi (__a, __b);
-+  return __builtin_aarch64_uqshlhi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint32_t __attribute__ ((__always_inline__))
- vqshls_u32 (uint32_t __a, uint32_t __b)
- {
--  return (uint32_t) __builtin_aarch64_uqshlsi (__a, __b);
-+  return __builtin_aarch64_uqshlsi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vqshld_u64 (uint64x1_t __a, uint64x1_t __b)
- {
--  return (uint64x1_t) __builtin_aarch64_uqshldi (__a, __b);
-+  return __builtin_aarch64_uqshldi_uus (__a, __b);
- }
- 
- __extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
-@@ -22030,25 +20787,25 @@
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vqshl_n_u8 (uint8x8_t __a, const int __b)
- {
--  return (uint8x8_t) __builtin_aarch64_uqshl_nv8qi ((int8x8_t) __a, __b);
-+  return __builtin_aarch64_uqshl_nv8qi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vqshl_n_u16 (uint16x4_t __a, const int __b)
- {
--  return (uint16x4_t) __builtin_aarch64_uqshl_nv4hi ((int16x4_t) __a, __b);
-+  return __builtin_aarch64_uqshl_nv4hi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vqshl_n_u32 (uint32x2_t __a, const int __b)
- {
--  return (uint32x2_t) __builtin_aarch64_uqshl_nv2si ((int32x2_t) __a, __b);
-+  return __builtin_aarch64_uqshl_nv2si_uus (__a, __b);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vqshl_n_u64 (uint64x1_t __a, const int __b)
- {
--  return (uint64x1_t) __builtin_aarch64_uqshl_ndi ((int64x1_t) __a, __b);
-+  return __builtin_aarch64_uqshl_ndi_uus (__a, __b);
- }
- 
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
-@@ -22078,25 +20835,25 @@
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vqshlq_n_u8 (uint8x16_t __a, const int __b)
- {
--  return (uint8x16_t) __builtin_aarch64_uqshl_nv16qi ((int8x16_t) __a, __b);
-+  return __builtin_aarch64_uqshl_nv16qi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vqshlq_n_u16 (uint16x8_t __a, const int __b)
- {
--  return (uint16x8_t) __builtin_aarch64_uqshl_nv8hi ((int16x8_t) __a, __b);
-+  return __builtin_aarch64_uqshl_nv8hi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vqshlq_n_u32 (uint32x4_t __a, const int __b)
- {
--  return (uint32x4_t) __builtin_aarch64_uqshl_nv4si ((int32x4_t) __a, __b);
-+  return __builtin_aarch64_uqshl_nv4si_uus (__a, __b);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vqshlq_n_u64 (uint64x2_t __a, const int __b)
- {
--  return (uint64x2_t) __builtin_aarch64_uqshl_nv2di ((int64x2_t) __a, __b);
-+  return __builtin_aarch64_uqshl_nv2di_uus (__a, __b);
- }
- 
- __extension__ static __inline int8_t __attribute__ ((__always_inline__))
-@@ -22126,25 +20883,25 @@
- __extension__ static __inline uint8_t __attribute__ ((__always_inline__))
- vqshlb_n_u8 (uint8_t __a, const int __b)
- {
--  return (uint8_t) __builtin_aarch64_uqshl_nqi (__a, __b);
-+  return __builtin_aarch64_uqshl_nqi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint16_t __attribute__ ((__always_inline__))
- vqshlh_n_u16 (uint16_t __a, const int __b)
- {
--  return (uint16_t) __builtin_aarch64_uqshl_nhi (__a, __b);
-+  return __builtin_aarch64_uqshl_nhi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint32_t __attribute__ ((__always_inline__))
- vqshls_n_u32 (uint32_t __a, const int __b)
- {
--  return (uint32_t) __builtin_aarch64_uqshl_nsi (__a, __b);
-+  return __builtin_aarch64_uqshl_nsi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vqshld_n_u64 (uint64x1_t __a, const int __b)
- {
--  return (uint64x1_t) __builtin_aarch64_uqshl_ndi (__a, __b);
-+  return __builtin_aarch64_uqshl_ndi_uus (__a, __b);
- }
- 
- /* vqshlu */
-@@ -22152,73 +20909,73 @@
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vqshlu_n_s8 (int8x8_t __a, const int __b)
- {
--  return (uint8x8_t) __builtin_aarch64_sqshlu_nv8qi (__a, __b);
-+  return __builtin_aarch64_sqshlu_nv8qi_uss (__a, __b);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vqshlu_n_s16 (int16x4_t __a, const int __b)
- {
--  return (uint16x4_t) __builtin_aarch64_sqshlu_nv4hi (__a, __b);
-+  return __builtin_aarch64_sqshlu_nv4hi_uss (__a, __b);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vqshlu_n_s32 (int32x2_t __a, const int __b)
- {
--  return (uint32x2_t) __builtin_aarch64_sqshlu_nv2si (__a, __b);
-+  return __builtin_aarch64_sqshlu_nv2si_uss (__a, __b);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vqshlu_n_s64 (int64x1_t __a, const int __b)
- {
--  return (uint64x1_t) __builtin_aarch64_sqshlu_ndi (__a, __b);
-+  return __builtin_aarch64_sqshlu_ndi_uss (__a, __b);
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vqshluq_n_s8 (int8x16_t __a, const int __b)
- {
--  return (uint8x16_t) __builtin_aarch64_sqshlu_nv16qi (__a, __b);
-+  return __builtin_aarch64_sqshlu_nv16qi_uss (__a, __b);
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vqshluq_n_s16 (int16x8_t __a, const int __b)
- {
--  return (uint16x8_t) __builtin_aarch64_sqshlu_nv8hi (__a, __b);
-+  return __builtin_aarch64_sqshlu_nv8hi_uss (__a, __b);
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vqshluq_n_s32 (int32x4_t __a, const int __b)
- {
--  return (uint32x4_t) __builtin_aarch64_sqshlu_nv4si (__a, __b);
-+  return __builtin_aarch64_sqshlu_nv4si_uss (__a, __b);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vqshluq_n_s64 (int64x2_t __a, const int __b)
- {
--  return (uint64x2_t) __builtin_aarch64_sqshlu_nv2di (__a, __b);
-+  return __builtin_aarch64_sqshlu_nv2di_uss (__a, __b);
- }
- 
- __extension__ static __inline int8_t __attribute__ ((__always_inline__))
- vqshlub_n_s8 (int8_t __a, const int __b)
- {
--  return (int8_t) __builtin_aarch64_sqshlu_nqi (__a, __b);
-+  return (int8_t) __builtin_aarch64_sqshlu_nqi_uss (__a, __b);
- }
- 
- __extension__ static __inline int16_t __attribute__ ((__always_inline__))
- vqshluh_n_s16 (int16_t __a, const int __b)
- {
--  return (int16_t) __builtin_aarch64_sqshlu_nhi (__a, __b);
-+  return (int16_t) __builtin_aarch64_sqshlu_nhi_uss (__a, __b);
- }
- 
- __extension__ static __inline int32_t __attribute__ ((__always_inline__))
- vqshlus_n_s32 (int32_t __a, const int __b)
- {
--  return (int32_t) __builtin_aarch64_sqshlu_nsi (__a, __b);
-+  return (int32_t) __builtin_aarch64_sqshlu_nsi_uss (__a, __b);
- }
- 
- __extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
- vqshlud_n_s64 (int64x1_t __a, const int __b)
- {
--  return (int64x1_t) __builtin_aarch64_sqshlu_ndi (__a, __b);
-+  return (int64x1_t) __builtin_aarch64_sqshlu_ndi_uss (__a, __b);
- }
- 
- /* vqshrn */
-@@ -22244,19 +21001,19 @@
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vqshrn_n_u16 (uint16x8_t __a, const int __b)
- {
--  return (uint8x8_t) __builtin_aarch64_uqshrn_nv8hi ((int16x8_t) __a, __b);
-+  return __builtin_aarch64_uqshrn_nv8hi_uus ( __a, __b);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vqshrn_n_u32 (uint32x4_t __a, const int __b)
- {
--  return (uint16x4_t) __builtin_aarch64_uqshrn_nv4si ((int32x4_t) __a, __b);
-+  return __builtin_aarch64_uqshrn_nv4si_uus ( __a, __b);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vqshrn_n_u64 (uint64x2_t __a, const int __b)
- {
--  return (uint32x2_t) __builtin_aarch64_uqshrn_nv2di ((int64x2_t) __a, __b);
-+  return __builtin_aarch64_uqshrn_nv2di_uus ( __a, __b);
- }
- 
- __extension__ static __inline int8_t __attribute__ ((__always_inline__))
-@@ -22280,19 +21037,19 @@
- __extension__ static __inline uint8_t __attribute__ ((__always_inline__))
- vqshrnh_n_u16 (uint16_t __a, const int __b)
- {
--  return (uint8_t) __builtin_aarch64_uqshrn_nhi (__a, __b);
-+  return __builtin_aarch64_uqshrn_nhi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint16_t __attribute__ ((__always_inline__))
- vqshrns_n_u32 (uint32_t __a, const int __b)
- {
--  return (uint16_t) __builtin_aarch64_uqshrn_nsi (__a, __b);
-+  return __builtin_aarch64_uqshrn_nsi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint32_t __attribute__ ((__always_inline__))
- vqshrnd_n_u64 (uint64x1_t __a, const int __b)
- {
--  return (uint32_t) __builtin_aarch64_uqshrn_ndi (__a, __b);
-+  return __builtin_aarch64_uqshrn_ndi_uus (__a, __b);
- }
- 
- /* vqshrun */
-@@ -22362,27 +21119,66 @@
- __extension__ static __inline uint8_t __attribute__ ((__always_inline__))
- vqsubb_u8 (uint8_t __a, uint8_t __b)
- {
--  return (uint8_t) __builtin_aarch64_uqsubqi (__a, __b);
-+  return (uint8_t) __builtin_aarch64_uqsubqi_uuu (__a, __b);
- }
- 
- __extension__ static __inline uint16_t __attribute__ ((__always_inline__))
- vqsubh_u16 (uint16_t __a, uint16_t __b)
- {
--  return (uint16_t) __builtin_aarch64_uqsubhi (__a, __b);
-+  return (uint16_t) __builtin_aarch64_uqsubhi_uuu (__a, __b);
- }
- 
- __extension__ static __inline uint32_t __attribute__ ((__always_inline__))
- vqsubs_u32 (uint32_t __a, uint32_t __b)
- {
--  return (uint32_t) __builtin_aarch64_uqsubsi (__a, __b);
-+  return (uint32_t) __builtin_aarch64_uqsubsi_uuu (__a, __b);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vqsubd_u64 (uint64x1_t __a, uint64x1_t __b)
- {
--  return (uint64x1_t) __builtin_aarch64_uqsubdi (__a, __b);
-+  return (uint64x1_t) __builtin_aarch64_uqsubdi_uuu ((uint64_t) __a,
-+						     (uint64_t) __b);
- }
- 
-+/* vrbit  */
-+
-+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
-+vrbit_p8 (poly8x8_t __a)
-+{
-+  return (poly8x8_t) __builtin_aarch64_rbitv8qi ((int8x8_t) __a);
-+}
-+
-+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
-+vrbit_s8 (int8x8_t __a)
-+{
-+  return __builtin_aarch64_rbitv8qi (__a);
-+}
-+
-+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
-+vrbit_u8 (uint8x8_t __a)
-+{
-+  return (uint8x8_t) __builtin_aarch64_rbitv8qi ((int8x8_t) __a);
-+}
-+
-+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
-+vrbitq_p8 (poly8x16_t __a)
-+{
-+  return (poly8x16_t) __builtin_aarch64_rbitv16qi ((int8x16_t)__a);
-+}
-+
-+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
-+vrbitq_s8 (int8x16_t __a)
-+{
-+  return __builtin_aarch64_rbitv16qi (__a);
-+}
-+
-+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
-+vrbitq_u8 (uint8x16_t __a)
-+{
-+  return (uint8x16_t) __builtin_aarch64_rbitv16qi ((int8x16_t) __a);
-+}
-+
- /* vrecpe  */
- 
- __extension__ static __inline float32_t __attribute__ ((__always_inline__))
-@@ -22461,6 +21257,234 @@
-   return __builtin_aarch64_frecpxdf (__a);
- }
- 
-+
-+/* vrev  */
-+
-+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
-+vrev16_p8 (poly8x8_t a)
-+{
-+  return __builtin_shuffle (a, (uint8x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
-+}
-+
-+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
-+vrev16_s8 (int8x8_t a)
-+{
-+  return __builtin_shuffle (a, (uint8x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
-+}
-+
-+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
-+vrev16_u8 (uint8x8_t a)
-+{
-+  return __builtin_shuffle (a, (uint8x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
-+}
-+
-+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
-+vrev16q_p8 (poly8x16_t a)
-+{
-+  return __builtin_shuffle (a,
-+      (uint8x16_t) { 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14 });
-+}
-+
-+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
-+vrev16q_s8 (int8x16_t a)
-+{
-+  return __builtin_shuffle (a,
-+      (uint8x16_t) { 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14 });
-+}
-+
-+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
-+vrev16q_u8 (uint8x16_t a)
-+{
-+  return __builtin_shuffle (a,
-+      (uint8x16_t) { 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14 });
-+}
-+
-+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
-+vrev32_p8 (poly8x8_t a)
-+{
-+  return __builtin_shuffle (a, (uint8x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
-+}
-+
-+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
-+vrev32_p16 (poly16x4_t a)
-+{
-+  return __builtin_shuffle (a, (uint16x4_t) { 1, 0, 3, 2 });
-+}
-+
-+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
-+vrev32_s8 (int8x8_t a)
-+{
-+  return __builtin_shuffle (a, (uint8x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
-+}
-+
-+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
-+vrev32_s16 (int16x4_t a)
-+{
-+  return __builtin_shuffle (a, (uint16x4_t) { 1, 0, 3, 2 });
-+}
-+
-+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
-+vrev32_u8 (uint8x8_t a)
-+{
-+  return __builtin_shuffle (a, (uint8x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
-+}
-+
-+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
-+vrev32_u16 (uint16x4_t a)
-+{
-+  return __builtin_shuffle (a, (uint16x4_t) { 1, 0, 3, 2 });
-+}
-+
-+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
-+vrev32q_p8 (poly8x16_t a)
-+{
-+  return __builtin_shuffle (a,
-+      (uint8x16_t) { 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12 });
-+}
-+
-+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
-+vrev32q_p16 (poly16x8_t a)
-+{
-+  return __builtin_shuffle (a, (uint16x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
-+}
-+
-+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
-+vrev32q_s8 (int8x16_t a)
-+{
-+  return __builtin_shuffle (a,
-+      (uint8x16_t) { 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12 });
-+}
-+
-+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
-+vrev32q_s16 (int16x8_t a)
-+{
-+  return __builtin_shuffle (a, (uint16x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
-+}
-+
-+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
-+vrev32q_u8 (uint8x16_t a)
-+{
-+  return __builtin_shuffle (a,
-+      (uint8x16_t) { 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12 });
-+}
-+
-+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
-+vrev32q_u16 (uint16x8_t a)
-+{
-+  return __builtin_shuffle (a, (uint16x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
-+}
-+
-+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
-+vrev64_f32 (float32x2_t a)
-+{
-+  return __builtin_shuffle (a, (uint32x2_t) { 1, 0 });
-+}
-+
-+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
-+vrev64_p8 (poly8x8_t a)
-+{
-+  return __builtin_shuffle (a, (uint8x8_t) { 7, 6, 5, 4, 3, 2, 1, 0 });
-+}
-+
-+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
-+vrev64_p16 (poly16x4_t a)
-+{
-+  return __builtin_shuffle (a, (uint16x4_t) { 3, 2, 1, 0 });
-+}
-+
-+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
-+vrev64_s8 (int8x8_t a)
-+{
-+  return __builtin_shuffle (a, (uint8x8_t) { 7, 6, 5, 4, 3, 2, 1, 0 });
-+}
-+
-+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
-+vrev64_s16 (int16x4_t a)
-+{
-+  return __builtin_shuffle (a, (uint16x4_t) { 3, 2, 1, 0 });
-+}
-+
-+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
-+vrev64_s32 (int32x2_t a)
-+{
-+  return __builtin_shuffle (a, (uint32x2_t) { 1, 0 });
-+}
-+
-+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
-+vrev64_u8 (uint8x8_t a)
-+{
-+  return __builtin_shuffle (a, (uint8x8_t) { 7, 6, 5, 4, 3, 2, 1, 0 });
-+}
-+
-+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
-+vrev64_u16 (uint16x4_t a)
-+{
-+  return __builtin_shuffle (a, (uint16x4_t) { 3, 2, 1, 0 });
-+}
-+
-+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
-+vrev64_u32 (uint32x2_t a)
-+{
-+  return __builtin_shuffle (a, (uint32x2_t) { 1, 0 });
-+}
-+
-+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
-+vrev64q_f32 (float32x4_t a)
-+{
-+  return __builtin_shuffle (a, (uint32x4_t) { 1, 0, 3, 2 });
-+}
-+
-+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
-+vrev64q_p8 (poly8x16_t a)
-+{
-+  return __builtin_shuffle (a,
-+      (uint8x16_t) { 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8 });
-+}
-+
-+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
-+vrev64q_p16 (poly16x8_t a)
-+{
-+  return __builtin_shuffle (a, (uint16x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
-+}
-+
-+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
-+vrev64q_s8 (int8x16_t a)
-+{
-+  return __builtin_shuffle (a,
-+      (uint8x16_t) { 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8 });
-+}
-+
-+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
-+vrev64q_s16 (int16x8_t a)
-+{
-+  return __builtin_shuffle (a, (uint16x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
-+}
-+
-+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
-+vrev64q_s32 (int32x4_t a)
-+{
-+  return __builtin_shuffle (a, (uint32x4_t) { 1, 0, 3, 2 });
-+}
-+
-+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
-+vrev64q_u8 (uint8x16_t a)
-+{
-+  return __builtin_shuffle (a,
-+      (uint8x16_t) { 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8 });
-+}
-+
-+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
-+vrev64q_u16 (uint16x8_t a)
-+{
-+  return __builtin_shuffle (a, (uint16x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
-+}
-+
-+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
-+vrev64q_u32 (uint32x4_t a)
-+{
-+  return __builtin_shuffle (a, (uint32x4_t) { 1, 0, 3, 2 });
-+}
-+
- /* vrnd  */
- 
- __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
-@@ -22469,6 +21493,12 @@
-   return __builtin_aarch64_btruncv2sf (__a);
- }
- 
-+__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
-+vrnd_f64 (float64x1_t __a)
-+{
-+  return vset_lane_f64 (__builtin_trunc (vget_lane_f64 (__a, 0)), __a, 0);
-+}
-+
- __extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
- vrndq_f32 (float32x4_t __a)
- {
-@@ -22489,6 +21519,12 @@
-   return __builtin_aarch64_roundv2sf (__a);
- }
- 
-+__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
-+vrnda_f64 (float64x1_t __a)
-+{
-+  return vset_lane_f64 (__builtin_round (vget_lane_f64 (__a, 0)), __a, 0);
-+}
-+
- __extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
- vrndaq_f32 (float32x4_t __a)
- {
-@@ -22509,6 +21545,12 @@
-   return __builtin_aarch64_nearbyintv2sf (__a);
- }
- 
-+__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
-+vrndi_f64 (float64x1_t __a)
-+{
-+  return vset_lane_f64 (__builtin_nearbyint (vget_lane_f64 (__a, 0)), __a, 0);
-+}
-+
- __extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
- vrndiq_f32 (float32x4_t __a)
- {
-@@ -22529,6 +21571,12 @@
-   return __builtin_aarch64_floorv2sf (__a);
- }
- 
-+__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
-+vrndm_f64 (float64x1_t __a)
-+{
-+  return vset_lane_f64 (__builtin_floor (vget_lane_f64 (__a, 0)), __a, 0);
-+}
-+
- __extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
- vrndmq_f32 (float32x4_t __a)
- {
-@@ -22548,6 +21596,13 @@
- {
-   return __builtin_aarch64_frintnv2sf (__a);
- }
-+
-+__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
-+vrndn_f64 (float64x1_t __a)
-+{
-+  return __builtin_aarch64_frintndf (__a);
-+}
-+
- __extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
- vrndnq_f32 (float32x4_t __a)
- {
-@@ -22568,6 +21623,12 @@
-   return __builtin_aarch64_ceilv2sf (__a);
- }
- 
-+__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
-+vrndp_f64 (float64x1_t __a)
-+{
-+  return vset_lane_f64 (__builtin_ceil (vget_lane_f64 (__a, 0)), __a, 0);
-+}
-+
- __extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
- vrndpq_f32 (float32x4_t __a)
- {
-@@ -22588,6 +21649,12 @@
-   return __builtin_aarch64_rintv2sf (__a);
- }
- 
-+__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
-+vrndx_f64 (float64x1_t __a)
-+{
-+  return vset_lane_f64 (__builtin_rint (vget_lane_f64 (__a, 0)), __a, 0);
-+}
-+
- __extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
- vrndxq_f32 (float32x4_t __a)
- {
-@@ -22629,25 +21696,25 @@
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vrshl_u8 (uint8x8_t __a, int8x8_t __b)
- {
--  return (uint8x8_t) __builtin_aarch64_urshlv8qi ((int8x8_t) __a, __b);
-+  return __builtin_aarch64_urshlv8qi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vrshl_u16 (uint16x4_t __a, int16x4_t __b)
- {
--  return (uint16x4_t) __builtin_aarch64_urshlv4hi ((int16x4_t) __a, __b);
-+  return __builtin_aarch64_urshlv4hi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vrshl_u32 (uint32x2_t __a, int32x2_t __b)
- {
--  return (uint32x2_t) __builtin_aarch64_urshlv2si ((int32x2_t) __a, __b);
-+  return __builtin_aarch64_urshlv2si_uus (__a, __b);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vrshl_u64 (uint64x1_t __a, int64x1_t __b)
- {
--  return (uint64x1_t) __builtin_aarch64_urshldi ((int64x1_t) __a, __b);
-+  return __builtin_aarch64_urshldi_uus (__a, __b);
- }
- 
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
-@@ -22677,25 +21744,25 @@
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vrshlq_u8 (uint8x16_t __a, int8x16_t __b)
- {
--  return (uint8x16_t) __builtin_aarch64_urshlv16qi ((int8x16_t) __a, __b);
-+  return __builtin_aarch64_urshlv16qi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vrshlq_u16 (uint16x8_t __a, int16x8_t __b)
- {
--  return (uint16x8_t) __builtin_aarch64_urshlv8hi ((int16x8_t) __a, __b);
-+  return __builtin_aarch64_urshlv8hi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vrshlq_u32 (uint32x4_t __a, int32x4_t __b)
- {
--  return (uint32x4_t) __builtin_aarch64_urshlv4si ((int32x4_t) __a, __b);
-+  return __builtin_aarch64_urshlv4si_uus (__a, __b);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vrshlq_u64 (uint64x2_t __a, int64x2_t __b)
- {
--  return (uint64x2_t) __builtin_aarch64_urshlv2di ((int64x2_t) __a, __b);
-+  return __builtin_aarch64_urshlv2di_uus (__a, __b);
- }
- 
- __extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
-@@ -22707,7 +21774,7 @@
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vrshld_u64 (uint64x1_t __a, uint64x1_t __b)
- {
--  return (uint64x1_t) __builtin_aarch64_urshldi (__a, __b);
-+  return __builtin_aarch64_urshldi_uus (__a, __b);
- }
- 
- /* vrshr */
-@@ -22739,25 +21806,25 @@
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vrshr_n_u8 (uint8x8_t __a, const int __b)
- {
--  return (uint8x8_t) __builtin_aarch64_urshr_nv8qi ((int8x8_t) __a, __b);
-+  return __builtin_aarch64_urshr_nv8qi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vrshr_n_u16 (uint16x4_t __a, const int __b)
- {
--  return (uint16x4_t) __builtin_aarch64_urshr_nv4hi ((int16x4_t) __a, __b);
-+  return __builtin_aarch64_urshr_nv4hi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vrshr_n_u32 (uint32x2_t __a, const int __b)
- {
--  return (uint32x2_t) __builtin_aarch64_urshr_nv2si ((int32x2_t) __a, __b);
-+  return __builtin_aarch64_urshr_nv2si_uus (__a, __b);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vrshr_n_u64 (uint64x1_t __a, const int __b)
- {
--  return (uint64x1_t) __builtin_aarch64_urshr_ndi ((int64x1_t) __a, __b);
-+  return __builtin_aarch64_urshr_ndi_uus (__a, __b);
- }
- 
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
-@@ -22787,25 +21854,25 @@
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vrshrq_n_u8 (uint8x16_t __a, const int __b)
- {
--  return (uint8x16_t) __builtin_aarch64_urshr_nv16qi ((int8x16_t) __a, __b);
-+  return __builtin_aarch64_urshr_nv16qi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vrshrq_n_u16 (uint16x8_t __a, const int __b)
- {
--  return (uint16x8_t) __builtin_aarch64_urshr_nv8hi ((int16x8_t) __a, __b);
-+  return __builtin_aarch64_urshr_nv8hi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vrshrq_n_u32 (uint32x4_t __a, const int __b)
- {
--  return (uint32x4_t) __builtin_aarch64_urshr_nv4si ((int32x4_t) __a, __b);
-+  return __builtin_aarch64_urshr_nv4si_uus (__a, __b);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vrshrq_n_u64 (uint64x2_t __a, const int __b)
- {
--  return (uint64x2_t) __builtin_aarch64_urshr_nv2di ((int64x2_t) __a, __b);
-+  return __builtin_aarch64_urshr_nv2di_uus (__a, __b);
- }
- 
- __extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
-@@ -22817,7 +21884,7 @@
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vrshrd_n_u64 (uint64x1_t __a, const int __b)
- {
--  return (uint64x1_t) __builtin_aarch64_urshr_ndi (__a, __b);
-+  return __builtin_aarch64_urshr_ndi_uus (__a, __b);
- }
- 
- /* vrsra */
-@@ -22849,29 +21916,25 @@
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vrsra_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c)
- {
--  return (uint8x8_t) __builtin_aarch64_ursra_nv8qi ((int8x8_t) __a,
--						    (int8x8_t) __b, __c);
-+  return __builtin_aarch64_ursra_nv8qi_uuus (__a, __b, __c);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vrsra_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
- {
--  return (uint16x4_t) __builtin_aarch64_ursra_nv4hi ((int16x4_t) __a,
--						     (int16x4_t) __b, __c);
-+  return __builtin_aarch64_ursra_nv4hi_uuus (__a, __b, __c);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vrsra_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
- {
--  return (uint32x2_t) __builtin_aarch64_ursra_nv2si ((int32x2_t) __a,
--						     (int32x2_t) __b, __c);
-+  return __builtin_aarch64_ursra_nv2si_uuus (__a, __b, __c);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vrsra_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
- {
--  return (uint64x1_t) __builtin_aarch64_ursra_ndi ((int64x1_t) __a,
--						   (int64x1_t) __b, __c);
-+  return __builtin_aarch64_ursra_ndi_uuus (__a, __b, __c);
- }
- 
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
-@@ -22901,29 +21964,25 @@
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vrsraq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c)
- {
--  return (uint8x16_t) __builtin_aarch64_ursra_nv16qi ((int8x16_t) __a,
--						      (int8x16_t) __b, __c);
-+  return __builtin_aarch64_ursra_nv16qi_uuus (__a, __b, __c);
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vrsraq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c)
- {
--  return (uint16x8_t) __builtin_aarch64_ursra_nv8hi ((int16x8_t) __a,
--						     (int16x8_t) __b, __c);
-+  return __builtin_aarch64_ursra_nv8hi_uuus (__a, __b, __c);
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vrsraq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c)
- {
--  return (uint32x4_t) __builtin_aarch64_ursra_nv4si ((int32x4_t) __a,
--						     (int32x4_t) __b, __c);
-+  return __builtin_aarch64_ursra_nv4si_uuus (__a, __b, __c);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vrsraq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c)
- {
--  return (uint64x2_t) __builtin_aarch64_ursra_nv2di ((int64x2_t) __a,
--						     (int64x2_t) __b, __c);
-+  return __builtin_aarch64_ursra_nv2di_uuus (__a, __b, __c);
- }
- 
- __extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
-@@ -22935,7 +21994,7 @@
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vrsrad_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
- {
--  return (uint64x1_t) __builtin_aarch64_ursra_ndi (__a, __b, __c);
-+  return __builtin_aarch64_ursra_ndi_uuus (__a, __b, __c);
- }
- 
- #ifdef __ARM_FEATURE_CRYPTO
-@@ -23128,109 +22187,109 @@
- __extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
- vshl_s8 (int8x8_t __a, int8x8_t __b)
- {
--  return (int8x8_t) __builtin_aarch64_sshlv8qi (__a, __b);
-+  return __builtin_aarch64_sshlv8qi (__a, __b);
- }
- 
- __extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
- vshl_s16 (int16x4_t __a, int16x4_t __b)
- {
--  return (int16x4_t) __builtin_aarch64_sshlv4hi (__a, __b);
-+  return __builtin_aarch64_sshlv4hi (__a, __b);
- }
- 
- __extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
- vshl_s32 (int32x2_t __a, int32x2_t __b)
- {
--  return (int32x2_t) __builtin_aarch64_sshlv2si (__a, __b);
-+  return __builtin_aarch64_sshlv2si (__a, __b);
- }
- 
- __extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
- vshl_s64 (int64x1_t __a, int64x1_t __b)
- {
--  return (int64x1_t) __builtin_aarch64_sshldi (__a, __b);
-+  return __builtin_aarch64_sshldi (__a, __b);
- }
- 
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vshl_u8 (uint8x8_t __a, int8x8_t __b)
- {
--  return (uint8x8_t) __builtin_aarch64_ushlv8qi ((int8x8_t) __a, __b);
-+  return __builtin_aarch64_ushlv8qi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vshl_u16 (uint16x4_t __a, int16x4_t __b)
- {
--  return (uint16x4_t) __builtin_aarch64_ushlv4hi ((int16x4_t) __a, __b);
-+  return __builtin_aarch64_ushlv4hi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vshl_u32 (uint32x2_t __a, int32x2_t __b)
- {
--  return (uint32x2_t) __builtin_aarch64_ushlv2si ((int32x2_t) __a, __b);
-+  return __builtin_aarch64_ushlv2si_uus (__a, __b);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vshl_u64 (uint64x1_t __a, int64x1_t __b)
- {
--  return (uint64x1_t) __builtin_aarch64_ushldi ((int64x1_t) __a, __b);
-+  return __builtin_aarch64_ushldi_uus (__a, __b);
- }
- 
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
- vshlq_s8 (int8x16_t __a, int8x16_t __b)
- {
--  return (int8x16_t) __builtin_aarch64_sshlv16qi (__a, __b);
-+  return __builtin_aarch64_sshlv16qi (__a, __b);
- }
- 
- __extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
- vshlq_s16 (int16x8_t __a, int16x8_t __b)
- {
--  return (int16x8_t) __builtin_aarch64_sshlv8hi (__a, __b);
-+  return __builtin_aarch64_sshlv8hi (__a, __b);
- }
- 
- __extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
- vshlq_s32 (int32x4_t __a, int32x4_t __b)
- {
--  return (int32x4_t) __builtin_aarch64_sshlv4si (__a, __b);
-+  return __builtin_aarch64_sshlv4si (__a, __b);
- }
- 
- __extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
- vshlq_s64 (int64x2_t __a, int64x2_t __b)
- {
--  return (int64x2_t) __builtin_aarch64_sshlv2di (__a, __b);
-+  return __builtin_aarch64_sshlv2di (__a, __b);
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vshlq_u8 (uint8x16_t __a, int8x16_t __b)
- {
--  return (uint8x16_t) __builtin_aarch64_ushlv16qi ((int8x16_t) __a, __b);
-+  return __builtin_aarch64_ushlv16qi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vshlq_u16 (uint16x8_t __a, int16x8_t __b)
- {
--  return (uint16x8_t) __builtin_aarch64_ushlv8hi ((int16x8_t) __a, __b);
-+  return __builtin_aarch64_ushlv8hi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vshlq_u32 (uint32x4_t __a, int32x4_t __b)
- {
--  return (uint32x4_t) __builtin_aarch64_ushlv4si ((int32x4_t) __a, __b);
-+  return __builtin_aarch64_ushlv4si_uus (__a, __b);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vshlq_u64 (uint64x2_t __a, int64x2_t __b)
- {
--  return (uint64x2_t) __builtin_aarch64_ushlv2di ((int64x2_t) __a, __b);
-+  return __builtin_aarch64_ushlv2di_uus (__a, __b);
- }
- 
- __extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
- vshld_s64 (int64x1_t __a, int64x1_t __b)
- {
--  return (int64x1_t) __builtin_aarch64_sshldi (__a, __b);
-+  return __builtin_aarch64_sshldi (__a, __b);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vshld_u64 (uint64x1_t __a, uint64x1_t __b)
- {
--  return (uint64x1_t) __builtin_aarch64_ushldi (__a, __b);
-+  return __builtin_aarch64_ushldi_uus (__a, __b);
- }
- 
- __extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
-@@ -23290,19 +22349,19 @@
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vshll_n_u8 (uint8x8_t __a, const int __b)
- {
--  return (uint16x8_t) __builtin_aarch64_ushll_nv8qi ((int8x8_t) __a, __b);
-+  return __builtin_aarch64_ushll_nv8qi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vshll_n_u16 (uint16x4_t __a, const int __b)
- {
--  return (uint32x4_t) __builtin_aarch64_ushll_nv4hi ((int16x4_t) __a, __b);
-+  return __builtin_aarch64_ushll_nv4hi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vshll_n_u32 (uint32x2_t __a, const int __b)
- {
--  return (uint64x2_t) __builtin_aarch64_ushll_nv2si ((int32x2_t) __a, __b);
-+  return __builtin_aarch64_ushll_nv2si_uus (__a, __b);
- }
- 
- /* vshr */
-@@ -23444,29 +22503,25 @@
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vsli_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c)
- {
--  return (uint8x8_t) __builtin_aarch64_usli_nv8qi ((int8x8_t) __a,
--						   (int8x8_t) __b, __c);
-+  return __builtin_aarch64_usli_nv8qi_uuus (__a, __b, __c);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vsli_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
- {
--  return (uint16x4_t) __builtin_aarch64_usli_nv4hi ((int16x4_t) __a,
--						    (int16x4_t) __b, __c);
-+  return __builtin_aarch64_usli_nv4hi_uuus (__a, __b, __c);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vsli_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
- {
--  return (uint32x2_t) __builtin_aarch64_usli_nv2si ((int32x2_t) __a,
--						    (int32x2_t) __b, __c);
-+  return __builtin_aarch64_usli_nv2si_uuus (__a, __b, __c);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vsli_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
- {
--  return (uint64x1_t) __builtin_aarch64_usli_ndi ((int64x1_t) __a,
--						  (int64x1_t) __b, __c);
-+  return __builtin_aarch64_usli_ndi_uuus (__a, __b, __c);
- }
- 
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
-@@ -23496,29 +22551,25 @@
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vsliq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c)
- {
--  return (uint8x16_t) __builtin_aarch64_usli_nv16qi ((int8x16_t) __a,
--						     (int8x16_t) __b, __c);
-+  return __builtin_aarch64_usli_nv16qi_uuus (__a, __b, __c);
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vsliq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c)
- {
--  return (uint16x8_t) __builtin_aarch64_usli_nv8hi ((int16x8_t) __a,
--						    (int16x8_t) __b, __c);
-+  return __builtin_aarch64_usli_nv8hi_uuus (__a, __b, __c);
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vsliq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c)
- {
--  return (uint32x4_t) __builtin_aarch64_usli_nv4si ((int32x4_t) __a,
--						    (int32x4_t) __b, __c);
-+  return __builtin_aarch64_usli_nv4si_uuus (__a, __b, __c);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vsliq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c)
- {
--  return (uint64x2_t) __builtin_aarch64_usli_nv2di ((int64x2_t) __a,
--						    (int64x2_t) __b, __c);
-+  return __builtin_aarch64_usli_nv2di_uuus (__a, __b, __c);
- }
- 
- __extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
-@@ -23530,7 +22581,7 @@
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vslid_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
- {
--  return (uint64x1_t) __builtin_aarch64_usli_ndi (__a, __b, __c);
-+  return __builtin_aarch64_usli_ndi_uuus (__a, __b, __c);
- }
- 
- /* vsqadd */
-@@ -23538,80 +22589,73 @@
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vsqadd_u8 (uint8x8_t __a, int8x8_t __b)
- {
--  return (uint8x8_t) __builtin_aarch64_usqaddv8qi ((int8x8_t) __a,
--						   (int8x8_t) __b);
-+  return __builtin_aarch64_usqaddv8qi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vsqadd_u16 (uint16x4_t __a, int16x4_t __b)
- {
--  return (uint16x4_t) __builtin_aarch64_usqaddv4hi ((int16x4_t) __a,
--						    (int16x4_t) __b);
-+  return __builtin_aarch64_usqaddv4hi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vsqadd_u32 (uint32x2_t __a, int32x2_t __b)
- {
--  return (uint32x2_t) __builtin_aarch64_usqaddv2si ((int32x2_t) __a,
--						    (int32x2_t) __b);
-+  return __builtin_aarch64_usqaddv2si_uus (__a, __b);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vsqadd_u64 (uint64x1_t __a, int64x1_t __b)
- {
--  return (uint64x1_t) __builtin_aarch64_usqadddi ((int64x1_t) __a, __b);
-+  return __builtin_aarch64_usqadddi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vsqaddq_u8 (uint8x16_t __a, int8x16_t __b)
- {
--  return (uint8x16_t) __builtin_aarch64_usqaddv16qi ((int8x16_t) __a,
--						     (int8x16_t) __b);
-+  return __builtin_aarch64_usqaddv16qi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vsqaddq_u16 (uint16x8_t __a, int16x8_t __b)
- {
--  return (uint16x8_t) __builtin_aarch64_usqaddv8hi ((int16x8_t) __a,
--						    (int16x8_t) __b);
-+  return __builtin_aarch64_usqaddv8hi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vsqaddq_u32 (uint32x4_t __a, int32x4_t __b)
- {
--  return (uint32x4_t) __builtin_aarch64_usqaddv4si ((int32x4_t) __a,
--						    (int32x4_t) __b);
-+  return __builtin_aarch64_usqaddv4si_uus (__a, __b);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vsqaddq_u64 (uint64x2_t __a, int64x2_t __b)
- {
--  return (uint64x2_t) __builtin_aarch64_usqaddv2di ((int64x2_t) __a,
--						    (int64x2_t) __b);
-+  return __builtin_aarch64_usqaddv2di_uus (__a, __b);
- }
- 
- __extension__ static __inline uint8_t __attribute__ ((__always_inline__))
- vsqaddb_u8 (uint8_t __a, int8_t __b)
- {
--  return (uint8_t) __builtin_aarch64_usqaddqi ((int8_t) __a, __b);
-+  return __builtin_aarch64_usqaddqi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint16_t __attribute__ ((__always_inline__))
- vsqaddh_u16 (uint16_t __a, int16_t __b)
- {
--  return (uint16_t) __builtin_aarch64_usqaddhi ((int16_t) __a, __b);
-+  return __builtin_aarch64_usqaddhi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint32_t __attribute__ ((__always_inline__))
- vsqadds_u32 (uint32_t __a, int32_t __b)
- {
--  return (uint32_t) __builtin_aarch64_usqaddsi ((int32_t) __a, __b);
-+  return __builtin_aarch64_usqaddsi_uus (__a, __b);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vsqaddd_u64 (uint64x1_t __a, int64x1_t __b)
- {
--  return (uint64x1_t) __builtin_aarch64_usqadddi ((int64x1_t) __a, __b);
-+  return __builtin_aarch64_usqadddi_uus (__a, __b);
- }
- 
- /* vsqrt */
-@@ -23662,29 +22706,25 @@
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vsra_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c)
- {
--  return (uint8x8_t) __builtin_aarch64_usra_nv8qi ((int8x8_t) __a,
--						   (int8x8_t) __b, __c);
-+  return __builtin_aarch64_usra_nv8qi_uuus (__a, __b, __c);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vsra_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
- {
--  return (uint16x4_t) __builtin_aarch64_usra_nv4hi ((int16x4_t) __a,
--						    (int16x4_t) __b, __c);
-+  return __builtin_aarch64_usra_nv4hi_uuus (__a, __b, __c);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vsra_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
- {
--  return (uint32x2_t) __builtin_aarch64_usra_nv2si ((int32x2_t) __a,
--						    (int32x2_t) __b, __c);
-+  return __builtin_aarch64_usra_nv2si_uuus (__a, __b, __c);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vsra_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
- {
--  return (uint64x1_t) __builtin_aarch64_usra_ndi ((int64x1_t) __a,
--						  (int64x1_t) __b, __c);
-+  return __builtin_aarch64_usra_ndi_uuus (__a, __b, __c);
- }
- 
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
-@@ -23714,29 +22754,25 @@
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vsraq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c)
- {
--  return (uint8x16_t) __builtin_aarch64_usra_nv16qi ((int8x16_t) __a,
--						     (int8x16_t) __b, __c);
-+  return __builtin_aarch64_usra_nv16qi_uuus (__a, __b, __c);
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vsraq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c)
- {
--  return (uint16x8_t) __builtin_aarch64_usra_nv8hi ((int16x8_t) __a,
--						    (int16x8_t) __b, __c);
-+  return __builtin_aarch64_usra_nv8hi_uuus (__a, __b, __c);
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vsraq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c)
- {
--  return (uint32x4_t) __builtin_aarch64_usra_nv4si ((int32x4_t) __a,
--						    (int32x4_t) __b, __c);
-+  return __builtin_aarch64_usra_nv4si_uuus (__a, __b, __c);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vsraq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c)
- {
--  return (uint64x2_t) __builtin_aarch64_usra_nv2di ((int64x2_t) __a,
--						    (int64x2_t) __b, __c);
-+  return __builtin_aarch64_usra_nv2di_uuus (__a, __b, __c);
- }
- 
- __extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
-@@ -23748,7 +22784,7 @@
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vsrad_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
- {
--  return (uint64x1_t) __builtin_aarch64_usra_ndi (__a, __b, __c);
-+  return __builtin_aarch64_usra_ndi_uuus (__a, __b, __c);
- }
- 
- /* vsri */
-@@ -23780,29 +22816,25 @@
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vsri_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c)
- {
--  return (uint8x8_t) __builtin_aarch64_usri_nv8qi ((int8x8_t) __a,
--						   (int8x8_t) __b, __c);
-+  return __builtin_aarch64_usri_nv8qi_uuus (__a, __b, __c);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vsri_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
- {
--  return (uint16x4_t) __builtin_aarch64_usri_nv4hi ((int16x4_t) __a,
--						    (int16x4_t) __b, __c);
-+  return __builtin_aarch64_usri_nv4hi_uuus (__a, __b, __c);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vsri_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
- {
--  return (uint32x2_t) __builtin_aarch64_usri_nv2si ((int32x2_t) __a,
--						    (int32x2_t) __b, __c);
-+  return __builtin_aarch64_usri_nv2si_uuus (__a, __b, __c);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vsri_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
- {
--  return (uint64x1_t) __builtin_aarch64_usri_ndi ((int64x1_t) __a,
--						  (int64x1_t) __b, __c);
-+  return __builtin_aarch64_usri_ndi_uuus (__a, __b, __c);
- }
- 
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
-@@ -23832,29 +22864,25 @@
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vsriq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c)
- {
--  return (uint8x16_t) __builtin_aarch64_usri_nv16qi ((int8x16_t) __a,
--						     (int8x16_t) __b, __c);
-+  return __builtin_aarch64_usri_nv16qi_uuus (__a, __b, __c);
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vsriq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c)
- {
--  return (uint16x8_t) __builtin_aarch64_usri_nv8hi ((int16x8_t) __a,
--						    (int16x8_t) __b, __c);
-+  return __builtin_aarch64_usri_nv8hi_uuus (__a, __b, __c);
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vsriq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c)
- {
--  return (uint32x4_t) __builtin_aarch64_usri_nv4si ((int32x4_t) __a,
--						    (int32x4_t) __b, __c);
-+  return __builtin_aarch64_usri_nv4si_uuus (__a, __b, __c);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vsriq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c)
- {
--  return (uint64x2_t) __builtin_aarch64_usri_nv2di ((int64x2_t) __a,
--						    (int64x2_t) __b, __c);
-+  return __builtin_aarch64_usri_nv2di_uuus (__a, __b, __c);
- }
- 
- __extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
-@@ -23866,7 +22894,7 @@
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vsrid_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
- {
--  return (uint64x1_t) __builtin_aarch64_usri_ndi (__a, __b, __c);
-+  return __builtin_aarch64_usri_ndi_uuus (__a, __b, __c);
- }
- 
- /* vst1 */
-@@ -24970,6 +23998,438 @@
- 
- /* vtrn */
- 
-+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
-+vtrn1_f32 (float32x2_t __a, float32x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
-+#endif
-+}
-+
-+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
-+vtrn1_p8 (poly8x8_t __a, poly8x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {9, 1, 11, 3, 13, 5, 15, 7});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 8, 2, 10, 4, 12, 6, 14});
-+#endif
-+}
-+
-+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
-+vtrn1_p16 (poly16x4_t __a, poly16x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 1, 7, 3});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 2, 6});
-+#endif
-+}
-+
-+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
-+vtrn1_s8 (int8x8_t __a, int8x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {9, 1, 11, 3, 13, 5, 15, 7});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 8, 2, 10, 4, 12, 6, 14});
-+#endif
-+}
-+
-+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
-+vtrn1_s16 (int16x4_t __a, int16x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 1, 7, 3});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 2, 6});
-+#endif
-+}
-+
-+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
-+vtrn1_s32 (int32x2_t __a, int32x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
-+#endif
-+}
-+
-+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
-+vtrn1_u8 (uint8x8_t __a, uint8x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {9, 1, 11, 3, 13, 5, 15, 7});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 8, 2, 10, 4, 12, 6, 14});
-+#endif
-+}
-+
-+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
-+vtrn1_u16 (uint16x4_t __a, uint16x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 1, 7, 3});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 2, 6});
-+#endif
-+}
-+
-+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
-+vtrn1_u32 (uint32x2_t __a, uint32x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
-+#endif
-+}
-+
-+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
-+vtrn1q_f32 (float32x4_t __a, float32x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {5, 1, 7, 3});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 4, 2, 6});
-+#endif
-+}
-+
-+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
-+vtrn1q_f64 (float64x2_t __a, float64x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
-+#endif
-+}
-+
-+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
-+vtrn1q_p8 (poly8x16_t __a, poly8x16_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b,
-+      (uint8x16_t) {17, 1, 19, 3, 21, 5, 23, 7, 25, 9, 27, 11, 29, 13, 31, 15});
-+#else
-+  return __builtin_shuffle (__a, __b,
-+      (uint8x16_t) {0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30});
-+#endif
-+}
-+
-+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
-+vtrn1q_p16 (poly16x8_t __a, poly16x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 1, 11, 3, 13, 5, 15, 7});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 8, 2, 10, 4, 12, 6, 14});
-+#endif
-+}
-+
-+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
-+vtrn1q_s8 (int8x16_t __a, int8x16_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b,
-+      (uint8x16_t) {17, 1, 19, 3, 21, 5, 23, 7, 25, 9, 27, 11, 29, 13, 31, 15});
-+#else
-+  return __builtin_shuffle (__a, __b,
-+      (uint8x16_t) {0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30});
-+#endif
-+}
-+
-+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
-+vtrn1q_s16 (int16x8_t __a, int16x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 1, 11, 3, 13, 5, 15, 7});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 8, 2, 10, 4, 12, 6, 14});
-+#endif
-+}
-+
-+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
-+vtrn1q_s32 (int32x4_t __a, int32x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {5, 1, 7, 3});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 4, 2, 6});
-+#endif
-+}
-+
-+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
-+vtrn1q_s64 (int64x2_t __a, int64x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
-+#endif
-+}
-+
-+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
-+vtrn1q_u8 (uint8x16_t __a, uint8x16_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b,
-+      (uint8x16_t) {17, 1, 19, 3, 21, 5, 23, 7, 25, 9, 27, 11, 29, 13, 31, 15});
-+#else
-+  return __builtin_shuffle (__a, __b,
-+      (uint8x16_t) {0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30});
-+#endif
-+}
-+
-+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
-+vtrn1q_u16 (uint16x8_t __a, uint16x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 1, 11, 3, 13, 5, 15, 7});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 8, 2, 10, 4, 12, 6, 14});
-+#endif
-+}
-+
-+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
-+vtrn1q_u32 (uint32x4_t __a, uint32x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {5, 1, 7, 3});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 4, 2, 6});
-+#endif
-+}
-+
-+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
-+vtrn1q_u64 (uint64x2_t __a, uint64x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
-+#endif
-+}
-+
-+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
-+vtrn2_f32 (float32x2_t __a, float32x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
-+#endif
-+}
-+
-+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
-+vtrn2_p8 (poly8x8_t __a, poly8x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 0, 10, 2, 12, 4, 14, 6});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {1, 9, 3, 11, 5, 13, 7, 15});
-+#endif
-+}
-+
-+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
-+vtrn2_p16 (poly16x4_t __a, poly16x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 6, 2});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 5, 3, 7});
-+#endif
-+}
-+
-+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
-+vtrn2_s8 (int8x8_t __a, int8x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 0, 10, 2, 12, 4, 14, 6});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {1, 9, 3, 11, 5, 13, 7, 15});
-+#endif
-+}
-+
-+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
-+vtrn2_s16 (int16x4_t __a, int16x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 6, 2});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 5, 3, 7});
-+#endif
-+}
-+
-+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
-+vtrn2_s32 (int32x2_t __a, int32x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
-+#endif
-+}
-+
-+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
-+vtrn2_u8 (uint8x8_t __a, uint8x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 0, 10, 2, 12, 4, 14, 6});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {1, 9, 3, 11, 5, 13, 7, 15});
-+#endif
-+}
-+
-+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
-+vtrn2_u16 (uint16x4_t __a, uint16x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 6, 2});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 5, 3, 7});
-+#endif
-+}
-+
-+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
-+vtrn2_u32 (uint32x2_t __a, uint32x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
-+#endif
-+}
-+
-+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
-+vtrn2q_f32 (float32x4_t __a, float32x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 0, 6, 2});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {1, 5, 3, 7});
-+#endif
-+}
-+
-+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
-+vtrn2q_f64 (float64x2_t __a, float64x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
-+#endif
-+}
-+
-+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
-+vtrn2q_p8 (poly8x16_t __a, poly8x16_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b,
-+      (uint8x16_t) {16, 0, 18, 2, 20, 4, 22, 6, 24, 8, 26, 10, 28, 12, 30, 14});
-+#else
-+  return __builtin_shuffle (__a, __b,
-+      (uint8x16_t) {1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31});
-+#endif
-+}
-+
-+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
-+vtrn2q_p16 (poly16x8_t __a, poly16x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 0, 10, 2, 12, 4, 14, 6});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 9, 3, 11, 5, 13, 7, 15});
-+#endif
-+}
-+
-+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
-+vtrn2q_s8 (int8x16_t __a, int8x16_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b,
-+      (uint8x16_t) {16, 0, 18, 2, 20, 4, 22, 6, 24, 8, 26, 10, 28, 12, 30, 14});
-+#else
-+  return __builtin_shuffle (__a, __b,
-+      (uint8x16_t) {1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31});
-+#endif
-+}
-+
-+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
-+vtrn2q_s16 (int16x8_t __a, int16x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 0, 10, 2, 12, 4, 14, 6});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 9, 3, 11, 5, 13, 7, 15});
-+#endif
-+}
-+
-+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
-+vtrn2q_s32 (int32x4_t __a, int32x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 0, 6, 2});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {1, 5, 3, 7});
-+#endif
-+}
-+
-+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
-+vtrn2q_s64 (int64x2_t __a, int64x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
-+#endif
-+}
-+
-+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
-+vtrn2q_u8 (uint8x16_t __a, uint8x16_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b,
-+      (uint8x16_t) {16, 0, 18, 2, 20, 4, 22, 6, 24, 8, 26, 10, 28, 12, 30, 14});
-+#else
-+  return __builtin_shuffle (__a, __b,
-+      (uint8x16_t) {1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31});
-+#endif
-+}
-+
-+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
-+vtrn2q_u16 (uint16x8_t __a, uint16x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 0, 10, 2, 12, 4, 14, 6});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 9, 3, 11, 5, 13, 7, 15});
-+#endif
-+}
-+
-+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
-+vtrn2q_u32 (uint32x4_t __a, uint32x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 0, 6, 2});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {1, 5, 3, 7});
-+#endif
-+}
-+
-+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
-+vtrn2q_u64 (uint64x2_t __a, uint64x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
-+#endif
-+}
-+
- __extension__ static __inline float32x2x2_t __attribute__ ((__always_inline__))
- vtrn_f32 (float32x2_t a, float32x2_t b)
- {
-@@ -25083,19 +24543,19 @@
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vtst_s8 (int8x8_t __a, int8x8_t __b)
- {
--  return (uint8x8_t) __builtin_aarch64_cmtstv8qi (__a, __b);
-+  return (uint8x8_t) ((__a & __b) != 0);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vtst_s16 (int16x4_t __a, int16x4_t __b)
- {
--  return (uint16x4_t) __builtin_aarch64_cmtstv4hi (__a, __b);
-+  return (uint16x4_t) ((__a & __b) != 0);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vtst_s32 (int32x2_t __a, int32x2_t __b)
- {
--  return (uint32x2_t) __builtin_aarch64_cmtstv2si (__a, __b);
-+  return (uint32x2_t) ((__a & __b) != 0);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
-@@ -25107,22 +24567,19 @@
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vtst_u8 (uint8x8_t __a, uint8x8_t __b)
- {
--  return (uint8x8_t) __builtin_aarch64_cmtstv8qi ((int8x8_t) __a,
--						 (int8x8_t) __b);
-+  return ((__a & __b) != 0);
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vtst_u16 (uint16x4_t __a, uint16x4_t __b)
- {
--  return (uint16x4_t) __builtin_aarch64_cmtstv4hi ((int16x4_t) __a,
--						  (int16x4_t) __b);
-+  return ((__a & __b) != 0);
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vtst_u32 (uint32x2_t __a, uint32x2_t __b)
- {
--  return (uint32x2_t) __builtin_aarch64_cmtstv2si ((int32x2_t) __a,
--						  (int32x2_t) __b);
-+  return ((__a & __b) != 0);
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
-@@ -25134,53 +24591,49 @@
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vtstq_s8 (int8x16_t __a, int8x16_t __b)
- {
--  return (uint8x16_t) __builtin_aarch64_cmtstv16qi (__a, __b);
-+  return (uint8x16_t) ((__a & __b) != 0);
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vtstq_s16 (int16x8_t __a, int16x8_t __b)
- {
--  return (uint16x8_t) __builtin_aarch64_cmtstv8hi (__a, __b);
-+  return (uint16x8_t) ((__a & __b) != 0);
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vtstq_s32 (int32x4_t __a, int32x4_t __b)
- {
--  return (uint32x4_t) __builtin_aarch64_cmtstv4si (__a, __b);
-+  return (uint32x4_t) ((__a & __b) != 0);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vtstq_s64 (int64x2_t __a, int64x2_t __b)
- {
--  return (uint64x2_t) __builtin_aarch64_cmtstv2di (__a, __b);
-+  return (uint64x2_t) ((__a & __b) != __AARCH64_INT64_C (0));
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vtstq_u8 (uint8x16_t __a, uint8x16_t __b)
- {
--  return (uint8x16_t) __builtin_aarch64_cmtstv16qi ((int8x16_t) __a,
--						   (int8x16_t) __b);
-+  return ((__a & __b) != 0);
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vtstq_u16 (uint16x8_t __a, uint16x8_t __b)
- {
--  return (uint16x8_t) __builtin_aarch64_cmtstv8hi ((int16x8_t) __a,
--						  (int16x8_t) __b);
-+  return ((__a & __b) != 0);
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vtstq_u32 (uint32x4_t __a, uint32x4_t __b)
- {
--  return (uint32x4_t) __builtin_aarch64_cmtstv4si ((int32x4_t) __a,
--						  (int32x4_t) __b);
-+  return ((__a & __b) != 0);
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vtstq_u64 (uint64x2_t __a, uint64x2_t __b)
- {
--  return (uint64x2_t) __builtin_aarch64_cmtstv2di ((int64x2_t) __a,
--						  (int64x2_t) __b);
-+  return ((__a & __b) != __AARCH64_UINT64_C (0));
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
-@@ -25200,73 +24653,73 @@
- __extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
- vuqadd_s8 (int8x8_t __a, uint8x8_t __b)
- {
--  return (int8x8_t) __builtin_aarch64_suqaddv8qi (__a, (int8x8_t) __b);
-+  return __builtin_aarch64_suqaddv8qi_ssu (__a,  __b);
- }
- 
- __extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
- vuqadd_s16 (int16x4_t __a, uint16x4_t __b)
- {
--  return (int16x4_t) __builtin_aarch64_suqaddv4hi (__a, (int16x4_t) __b);
-+  return __builtin_aarch64_suqaddv4hi_ssu (__a,  __b);
- }
- 
- __extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
- vuqadd_s32 (int32x2_t __a, uint32x2_t __b)
- {
--  return (int32x2_t) __builtin_aarch64_suqaddv2si (__a, (int32x2_t) __b);
-+  return __builtin_aarch64_suqaddv2si_ssu (__a,  __b);
- }
- 
- __extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
- vuqadd_s64 (int64x1_t __a, uint64x1_t __b)
- {
--  return (int64x1_t) __builtin_aarch64_suqadddi (__a, (int64x1_t) __b);
-+  return __builtin_aarch64_suqadddi_ssu (__a,  __b);
- }
- 
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
- vuqaddq_s8 (int8x16_t __a, uint8x16_t __b)
- {
--  return (int8x16_t) __builtin_aarch64_suqaddv16qi (__a, (int8x16_t) __b);
-+  return __builtin_aarch64_suqaddv16qi_ssu (__a,  __b);
- }
- 
- __extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
- vuqaddq_s16 (int16x8_t __a, uint16x8_t __b)
- {
--  return (int16x8_t) __builtin_aarch64_suqaddv8hi (__a, (int16x8_t) __b);
-+  return __builtin_aarch64_suqaddv8hi_ssu (__a,  __b);
- }
- 
- __extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
- vuqaddq_s32 (int32x4_t __a, uint32x4_t __b)
- {
--  return (int32x4_t) __builtin_aarch64_suqaddv4si (__a, (int32x4_t) __b);
-+  return __builtin_aarch64_suqaddv4si_ssu (__a,  __b);
- }
- 
- __extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
- vuqaddq_s64 (int64x2_t __a, uint64x2_t __b)
- {
--  return (int64x2_t) __builtin_aarch64_suqaddv2di (__a, (int64x2_t) __b);
-+  return __builtin_aarch64_suqaddv2di_ssu (__a,  __b);
- }
- 
- __extension__ static __inline int8_t __attribute__ ((__always_inline__))
- vuqaddb_s8 (int8_t __a, uint8_t __b)
- {
--  return (int8_t) __builtin_aarch64_suqaddqi (__a, (int8_t) __b);
-+  return __builtin_aarch64_suqaddqi_ssu (__a,  __b);
- }
- 
- __extension__ static __inline int16_t __attribute__ ((__always_inline__))
- vuqaddh_s16 (int16_t __a, uint16_t __b)
- {
--  return (int16_t) __builtin_aarch64_suqaddhi (__a, (int16_t) __b);
-+  return __builtin_aarch64_suqaddhi_ssu (__a,  __b);
- }
- 
- __extension__ static __inline int32_t __attribute__ ((__always_inline__))
- vuqadds_s32 (int32_t __a, uint32_t __b)
- {
--  return (int32_t) __builtin_aarch64_suqaddsi (__a, (int32_t) __b);
-+  return __builtin_aarch64_suqaddsi_ssu (__a,  __b);
- }
- 
- __extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
- vuqaddd_s64 (int64x1_t __a, uint64x1_t __b)
- {
--  return (int64x1_t) __builtin_aarch64_suqadddi (__a, (int64x1_t) __b);
-+  return __builtin_aarch64_suqadddi_ssu (__a,  __b);
- }
- 
- #define __DEFINTERLEAVE(op, rettype, intype, funcsuffix, Q) 		\
-@@ -25300,10 +24753,880 @@
- 
- /* vuzp */
- 
-+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
-+vuzp1_f32 (float32x2_t __a, float32x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
-+#endif
-+}
-+
-+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
-+vuzp1_p8 (poly8x8_t __a, poly8x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {9, 11, 13, 15, 1, 3, 5, 7});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 2, 4, 6, 8, 10, 12, 14});
-+#endif
-+}
-+
-+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
-+vuzp1_p16 (poly16x4_t __a, poly16x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 7, 1, 3});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 2, 4, 6});
-+#endif
-+}
-+
-+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
-+vuzp1_s8 (int8x8_t __a, int8x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {9, 11, 13, 15, 1, 3, 5, 7});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 2, 4, 6, 8, 10, 12, 14});
-+#endif
-+}
-+
-+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
-+vuzp1_s16 (int16x4_t __a, int16x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 7, 1, 3});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 2, 4, 6});
-+#endif
-+}
-+
-+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
-+vuzp1_s32 (int32x2_t __a, int32x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
-+#endif
-+}
-+
-+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
-+vuzp1_u8 (uint8x8_t __a, uint8x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {9, 11, 13, 15, 1, 3, 5, 7});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 2, 4, 6, 8, 10, 12, 14});
-+#endif
-+}
-+
-+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
-+vuzp1_u16 (uint16x4_t __a, uint16x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 7, 1, 3});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 2, 4, 6});
-+#endif
-+}
-+
-+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
-+vuzp1_u32 (uint32x2_t __a, uint32x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
-+#endif
-+}
-+
-+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
-+vuzp1q_f32 (float32x4_t __a, float32x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {5, 7, 1, 3});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 2, 4, 6});
-+#endif
-+}
-+
-+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
-+vuzp1q_f64 (float64x2_t __a, float64x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
-+#endif
-+}
-+
-+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
-+vuzp1q_p8 (poly8x16_t __a, poly8x16_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint8x16_t)
-+      {17, 19, 21, 23, 25, 27, 29, 31, 1, 3, 5, 7, 9, 11, 13, 15});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint8x16_t)
-+      {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30});
-+#endif
-+}
-+
-+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
-+vuzp1q_p16 (poly16x8_t __a, poly16x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 11, 13, 15, 1, 3, 5, 7});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 2, 4, 6, 8, 10, 12, 14});
-+#endif
-+}
-+
-+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
-+vuzp1q_s8 (int8x16_t __a, int8x16_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b,
-+      (uint8x16_t) {17, 19, 21, 23, 25, 27, 29, 31, 1, 3, 5, 7, 9, 11, 13, 15});
-+#else
-+  return __builtin_shuffle (__a, __b,
-+      (uint8x16_t) {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30});
-+#endif
-+}
-+
-+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
-+vuzp1q_s16 (int16x8_t __a, int16x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 11, 13, 15, 1, 3, 5, 7});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 2, 4, 6, 8, 10, 12, 14});
-+#endif
-+}
-+
-+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
-+vuzp1q_s32 (int32x4_t __a, int32x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {5, 7, 1, 3});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 2, 4, 6});
-+#endif
-+}
-+
-+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
-+vuzp1q_s64 (int64x2_t __a, int64x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
-+#endif
-+}
-+
-+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
-+vuzp1q_u8 (uint8x16_t __a, uint8x16_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b,
-+      (uint8x16_t) {17, 19, 21, 23, 25, 27, 29, 31, 1, 3, 5, 7, 9, 11, 13, 15});
-+#else
-+  return __builtin_shuffle (__a, __b,
-+      (uint8x16_t) {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30});
-+#endif
-+}
-+
-+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
-+vuzp1q_u16 (uint16x8_t __a, uint16x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 11, 13, 15, 1, 3, 5, 7});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 2, 4, 6, 8, 10, 12, 14});
-+#endif
-+}
-+
-+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
-+vuzp1q_u32 (uint32x4_t __a, uint32x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {5, 7, 1, 3});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 2, 4, 6});
-+#endif
-+}
-+
-+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
-+vuzp1q_u64 (uint64x2_t __a, uint64x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
-+#endif
-+}
-+
-+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
-+vuzp2_f32 (float32x2_t __a, float32x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
-+#endif
-+}
-+
-+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
-+vuzp2_p8 (poly8x8_t __a, poly8x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 10, 12, 14, 0, 2, 4, 6});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {1, 3, 5, 7, 9, 11, 13, 15});
-+#endif
-+}
-+
-+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
-+vuzp2_p16 (poly16x4_t __a, poly16x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 6, 0, 2});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 3, 5, 7});
-+#endif
-+}
-+
-+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
-+vuzp2_s8 (int8x8_t __a, int8x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 10, 12, 14, 0, 2, 4, 6});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {1, 3, 5, 7, 9, 11, 13, 15});
-+#endif
-+}
-+
-+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
-+vuzp2_s16 (int16x4_t __a, int16x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 6, 0, 2});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 3, 5, 7});
-+#endif
-+}
-+
-+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
-+vuzp2_s32 (int32x2_t __a, int32x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
-+#endif
-+}
-+
-+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
-+vuzp2_u8 (uint8x8_t __a, uint8x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 10, 12, 14, 0, 2, 4, 6});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {1, 3, 5, 7, 9, 11, 13, 15});
-+#endif
-+}
-+
-+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
-+vuzp2_u16 (uint16x4_t __a, uint16x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 6, 0, 2});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 3, 5, 7});
-+#endif
-+}
-+
-+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
-+vuzp2_u32 (uint32x2_t __a, uint32x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
-+#endif
-+}
-+
-+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
-+vuzp2q_f32 (float32x4_t __a, float32x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 6, 0, 2});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {1, 3, 5, 7});
-+#endif
-+}
-+
-+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
-+vuzp2q_f64 (float64x2_t __a, float64x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
-+#endif
-+}
-+
-+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
-+vuzp2q_p8 (poly8x16_t __a, poly8x16_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b,
-+      (uint8x16_t) {16, 18, 20, 22, 24, 26, 28, 30, 0, 2, 4, 6, 8, 10, 12, 14});
-+#else
-+  return __builtin_shuffle (__a, __b,
-+      (uint8x16_t) {1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31});
-+#endif
-+}
-+
-+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
-+vuzp2q_p16 (poly16x8_t __a, poly16x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 10, 12, 14, 0, 2, 4, 6});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 3, 5, 7, 9, 11, 13, 15});
-+#endif
-+}
-+
-+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
-+vuzp2q_s8 (int8x16_t __a, int8x16_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b,
-+      (uint8x16_t) {16, 18, 20, 22, 24, 26, 28, 30, 0, 2, 4, 6, 8, 10, 12, 14});
-+#else
-+  return __builtin_shuffle (__a, __b,
-+      (uint8x16_t) {1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31});
-+#endif
-+}
-+
-+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
-+vuzp2q_s16 (int16x8_t __a, int16x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 10, 12, 14, 0, 2, 4, 6});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 3, 5, 7, 9, 11, 13, 15});
-+#endif
-+}
-+
-+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
-+vuzp2q_s32 (int32x4_t __a, int32x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 6, 0, 2});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {1, 3, 5, 7});
-+#endif
-+}
-+
-+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
-+vuzp2q_s64 (int64x2_t __a, int64x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
-+#endif
-+}
-+
-+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
-+vuzp2q_u8 (uint8x16_t __a, uint8x16_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint8x16_t)
-+      {16, 18, 20, 22, 24, 26, 28, 30, 0, 2, 4, 6, 8, 10, 12, 14});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint8x16_t)
-+      {1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31});
-+#endif
-+}
-+
-+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
-+vuzp2q_u16 (uint16x8_t __a, uint16x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 10, 12, 14, 0, 2, 4, 6});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 3, 5, 7, 9, 11, 13, 15});
-+#endif
-+}
-+
-+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
-+vuzp2q_u32 (uint32x4_t __a, uint32x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 6, 0, 2});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {1, 3, 5, 7});
-+#endif
-+}
-+
-+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
-+vuzp2q_u64 (uint64x2_t __a, uint64x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
-+#endif
-+}
-+
- __INTERLEAVE_LIST (uzp)
- 
- /* vzip */
- 
-+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
-+vzip1_f32 (float32x2_t __a, float32x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
-+#endif
-+}
-+
-+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
-+vzip1_p8 (poly8x8_t __a, poly8x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {12, 4, 13, 5, 14, 6, 15, 7});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 8, 1, 9, 2, 10, 3, 11});
-+#endif
-+}
-+
-+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
-+vzip1_p16 (poly16x4_t __a, poly16x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {6, 2, 7, 3});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 1, 5});
-+#endif
-+}
-+
-+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
-+vzip1_s8 (int8x8_t __a, int8x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {12, 4, 13, 5, 14, 6, 15, 7});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 8, 1, 9, 2, 10, 3, 11});
-+#endif
-+}
-+
-+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
-+vzip1_s16 (int16x4_t __a, int16x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {6, 2, 7, 3});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 1, 5});
-+#endif
-+}
-+
-+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
-+vzip1_s32 (int32x2_t __a, int32x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
-+#endif
-+}
-+
-+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
-+vzip1_u8 (uint8x8_t __a, uint8x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {12, 4, 13, 5, 14, 6, 15, 7});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 8, 1, 9, 2, 10, 3, 11});
-+#endif
-+}
-+
-+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
-+vzip1_u16 (uint16x4_t __a, uint16x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {6, 2, 7, 3});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 1, 5});
-+#endif
-+}
-+
-+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
-+vzip1_u32 (uint32x2_t __a, uint32x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
-+#endif
-+}
-+
-+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
-+vzip1q_f32 (float32x4_t __a, float32x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {6, 2, 7, 3});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 4, 1, 5});
-+#endif
-+}
-+
-+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
-+vzip1q_f64 (float64x2_t __a, float64x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
-+#endif
-+}
-+
-+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
-+vzip1q_p8 (poly8x16_t __a, poly8x16_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint8x16_t)
-+      {24, 8, 25, 9, 26, 10, 27, 11, 28, 12, 29, 13, 30, 14, 31, 15});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint8x16_t)
-+      {0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23});
-+#endif
-+}
-+
-+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
-+vzip1q_p16 (poly16x8_t __a, poly16x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x8_t)
-+      {12, 4, 13, 5, 14, 6, 15, 7});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 8, 1, 9, 2, 10, 3, 11});
-+#endif
-+}
-+
-+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
-+vzip1q_s8 (int8x16_t __a, int8x16_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint8x16_t)
-+      {24, 8, 25, 9, 26, 10, 27, 11, 28, 12, 29, 13, 30, 14, 31, 15});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint8x16_t)
-+      {0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23});
-+#endif
-+}
-+
-+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
-+vzip1q_s16 (int16x8_t __a, int16x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x8_t)
-+      {12, 4, 13, 5, 14, 6, 15, 7});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 8, 1, 9, 2, 10, 3, 11});
-+#endif
-+}
-+
-+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
-+vzip1q_s32 (int32x4_t __a, int32x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {6, 2, 7, 3});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 4, 1, 5});
-+#endif
-+}
-+
-+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
-+vzip1q_s64 (int64x2_t __a, int64x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
-+#endif
-+}
-+
-+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
-+vzip1q_u8 (uint8x16_t __a, uint8x16_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint8x16_t)
-+      {24, 8, 25, 9, 26, 10, 27, 11, 28, 12, 29, 13, 30, 14, 31, 15});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint8x16_t)
-+      {0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23});
-+#endif
-+}
-+
-+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
-+vzip1q_u16 (uint16x8_t __a, uint16x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x8_t)
-+      {12, 4, 13, 5, 14, 6, 15, 7});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 8, 1, 9, 2, 10, 3, 11});
-+#endif
-+}
-+
-+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
-+vzip1q_u32 (uint32x4_t __a, uint32x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {6, 2, 7, 3});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 4, 1, 5});
-+#endif
-+}
-+
-+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
-+vzip1q_u64 (uint64x2_t __a, uint64x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
-+#endif
-+}
-+
-+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
-+vzip2_f32 (float32x2_t __a, float32x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
-+#endif
-+}
-+
-+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
-+vzip2_p8 (poly8x8_t __a, poly8x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 0, 9, 1, 10, 2, 11, 3});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {4, 12, 5, 13, 6, 14, 7, 15});
-+#endif
-+}
-+
-+__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
-+vzip2_p16 (poly16x4_t __a, poly16x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 5, 1});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {2, 6, 3, 7});
-+#endif
-+}
-+
-+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
-+vzip2_s8 (int8x8_t __a, int8x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 0, 9, 1, 10, 2, 11, 3});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {4, 12, 5, 13, 6, 14, 7, 15});
-+#endif
-+}
-+
-+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
-+vzip2_s16 (int16x4_t __a, int16x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 5, 1});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {2, 6, 3, 7});
-+#endif
-+}
-+
-+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
-+vzip2_s32 (int32x2_t __a, int32x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
-+#endif
-+}
-+
-+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
-+vzip2_u8 (uint8x8_t __a, uint8x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 0, 9, 1, 10, 2, 11, 3});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint8x8_t) {4, 12, 5, 13, 6, 14, 7, 15});
-+#endif
-+}
-+
-+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
-+vzip2_u16 (uint16x4_t __a, uint16x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 5, 1});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x4_t) {2, 6, 3, 7});
-+#endif
-+}
-+
-+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
-+vzip2_u32 (uint32x2_t __a, uint32x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
-+#endif
-+}
-+
-+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
-+vzip2q_f32 (float32x4_t __a, float32x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 0, 5, 1});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {2, 6, 3, 7});
-+#endif
-+}
-+
-+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
-+vzip2q_f64 (float64x2_t __a, float64x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
-+#endif
-+}
-+
-+__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
-+vzip2q_p8 (poly8x16_t __a, poly8x16_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint8x16_t)
-+      {16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint8x16_t)
-+      {8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31});
-+#endif
-+}
-+
-+__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
-+vzip2q_p16 (poly16x8_t __a, poly16x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 0, 9, 1, 10, 2, 11, 3});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x8_t)
-+      {4, 12, 5, 13, 6, 14, 7, 15});
-+#endif
-+}
-+
-+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
-+vzip2q_s8 (int8x16_t __a, int8x16_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint8x16_t)
-+      {16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint8x16_t)
-+      {8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31});
-+#endif
-+}
-+
-+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
-+vzip2q_s16 (int16x8_t __a, int16x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 0, 9, 1, 10, 2, 11, 3});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x8_t)
-+      {4, 12, 5, 13, 6, 14, 7, 15});
-+#endif
-+}
-+
-+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
-+vzip2q_s32 (int32x4_t __a, int32x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 0, 5, 1});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {2, 6, 3, 7});
-+#endif
-+}
-+
-+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
-+vzip2q_s64 (int64x2_t __a, int64x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
-+#endif
-+}
-+
-+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
-+vzip2q_u8 (uint8x16_t __a, uint8x16_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint8x16_t)
-+      {16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint8x16_t)
-+      {8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31});
-+#endif
-+}
-+
-+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
-+vzip2q_u16 (uint16x8_t __a, uint16x8_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 0, 9, 1, 10, 2, 11, 3});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint16x8_t)
-+      {4, 12, 5, 13, 6, 14, 7, 15});
-+#endif
-+}
-+
-+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
-+vzip2q_u32 (uint32x4_t __a, uint32x4_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 0, 5, 1});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint32x4_t) {2, 6, 3, 7});
-+#endif
-+}
-+
-+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
-+vzip2q_u64 (uint64x2_t __a, uint64x2_t __b)
-+{
-+#ifdef __AARCH64EB__
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
-+#else
-+  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
-+#endif
-+}
-+
- __INTERLEAVE_LIST (zip)
- 
- #undef __INTERLEAVE_LIST
---- a/src/gcc/config/aarch64/t-aarch64-linux
-+++ b/src/gcc/config/aarch64/t-aarch64-linux
-@@ -22,10 +22,7 @@
- LIB1ASMFUNCS = _aarch64_sync_cache_range
- 
- AARCH_BE = $(if $(findstring TARGET_BIG_ENDIAN_DEFAULT=1, $(tm_defines)),_be)
--MULTILIB_OSDIRNAMES = .=../lib64$(call if_multiarch,:aarch64$(AARCH_BE)-linux-gnu)
-+MULTILIB_OSDIRNAMES = mabi.lp64=../lib64$(call if_multiarch,:aarch64$(AARCH_BE)-linux-gnu)
- MULTIARCH_DIRNAME = $(call if_multiarch,aarch64$(AARCH_BE)-linux-gnu)
- 
--# Disable the multilib for linux-gnu targets for the time being; focus
--# on the baremetal targets.
--MULTILIB_OPTIONS    =
--MULTILIB_DIRNAMES   =
-+MULTILIB_OSDIRNAMES += mabi.ilp32=../libilp32
---- a/src/gcc/config/aarch64/aarch64.md
-+++ b/src/gcc/config/aarch64/aarch64.md
-@@ -67,7 +67,14 @@
- 
- (define_c_enum "unspec" [
-     UNSPEC_CASESI
--    UNSPEC_CLS
-+    UNSPEC_CRC32B
-+    UNSPEC_CRC32CB
-+    UNSPEC_CRC32CH
-+    UNSPEC_CRC32CW
-+    UNSPEC_CRC32CX
-+    UNSPEC_CRC32H
-+    UNSPEC_CRC32W
-+    UNSPEC_CRC32X
-     UNSPEC_FRECPE
-     UNSPEC_FRECPS
-     UNSPEC_FRECPX
-@@ -83,8 +90,11 @@
-     UNSPEC_GOTTINYPIC
-     UNSPEC_LD1
-     UNSPEC_LD2
-+    UNSPEC_LD2_DUP
-     UNSPEC_LD3
-+    UNSPEC_LD3_DUP
-     UNSPEC_LD4
-+    UNSPEC_LD4_DUP
-     UNSPEC_MB
-     UNSPEC_NOP
-     UNSPEC_PRLG_STK
-@@ -98,15 +108,24 @@
-     UNSPEC_ST2
-     UNSPEC_ST3
-     UNSPEC_ST4
-+    UNSPEC_ST2_LANE
-+    UNSPEC_ST3_LANE
-+    UNSPEC_ST4_LANE
-     UNSPEC_TLS
-     UNSPEC_TLSDESC
-     UNSPEC_USHL_2S
-     UNSPEC_USHR64
-     UNSPEC_VSTRUCTDUMMY
-+    UNSPEC_SP_SET
-+    UNSPEC_SP_TEST
- ])
- 
- (define_c_enum "unspecv" [
-     UNSPECV_EH_RETURN		; Represent EH_RETURN
-+    UNSPECV_GET_FPCR		; Represent fetch of FPCR content.
-+    UNSPECV_SET_FPCR		; Represent assign of FPCR content.
-+    UNSPECV_GET_FPSR		; Represent fetch of FPSR content.
-+    UNSPECV_SET_FPSR		; Represent assign of FPSR content.
-   ]
- )
- 
-@@ -159,7 +178,7 @@
- 
- (define_attr "generic_sched" "yes,no"
-   (const (if_then_else
--          (eq_attr "tune" "cortexa53,cortexa15")
-+          (eq_attr "tune" "cortexa53,cortexa15,thunderx")
-           (const_string "no")
-           (const_string "yes"))))
- 
-@@ -166,6 +185,7 @@
- ;; Scheduling
- (include "../arm/cortex-a53.md")
- (include "../arm/cortex-a15.md")
-+(include "thunderx.md")
- 
- ;; -------------------------------------------------------------------
- ;; Jumps and other miscellaneous insns
-@@ -514,6 +534,10 @@
- 	      (use (match_operand 2 "" ""))])]
-   ""
-   {
-+    if (!REG_P (XEXP (operands[0], 0))
-+       && (GET_CODE (XEXP (operands[0], 0)) != SYMBOL_REF))
-+     XEXP (operands[0], 0) = force_reg (Pmode, XEXP (operands[0], 0));
-+
-     if (operands[2] == NULL_RTX)
-       operands[2] = const0_rtx;
-   }
-@@ -527,6 +551,10 @@
- 	      (use (match_operand 3 "" ""))])]
-   ""
-   {
-+    if (!REG_P (XEXP (operands[1], 0))
-+       && (GET_CODE (XEXP (operands[1], 0)) != SYMBOL_REF))
-+     XEXP (operands[1], 0) = force_reg (Pmode, XEXP (operands[1], 0));
-+
-     if (operands[3] == NULL_RTX)
-       operands[3] = const0_rtx;
-   }
-@@ -533,25 +561,29 @@
- )
- 
- (define_insn "*sibcall_insn"
--  [(call (mem:DI (match_operand:DI 0 "" "X"))
-+  [(call (mem:DI (match_operand:DI 0 "aarch64_call_insn_operand" "Ucs, Usf"))
- 	 (match_operand 1 "" ""))
-    (return)
-    (use (match_operand 2 "" ""))]
--  "GET_CODE (operands[0]) == SYMBOL_REF"
--  "b\\t%a0"
--  [(set_attr "type" "branch")]
--
-+  "SIBLING_CALL_P (insn)"
-+  "@
-+   br\\t%0
-+   b\\t%a0"
-+  [(set_attr "type" "branch, branch")]
- )
- 
- (define_insn "*sibcall_value_insn"
-   [(set (match_operand 0 "" "")
--	(call (mem:DI (match_operand 1 "" "X"))
-+	(call (mem:DI
-+		(match_operand:DI 1 "aarch64_call_insn_operand" "Ucs, Usf"))
- 	      (match_operand 2 "" "")))
-    (return)
-    (use (match_operand 3 "" ""))]
--  "GET_CODE (operands[1]) == SYMBOL_REF"
--  "b\\t%a1"
--  [(set_attr "type" "branch")]
-+  "SIBLING_CALL_P (insn)"
-+  "@
-+   br\\t%1
-+   b\\t%a1"
-+  [(set_attr "type" "branch, branch")]
- )
- 
- ;; Call subroutine returning any type.
-@@ -641,17 +673,20 @@
-     if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx)
-       operands[1] = force_reg (<MODE>mode, operands[1]);
- 
--    if (CONSTANT_P (operands[1]))
--      {
--	aarch64_expand_mov_immediate (operands[0], operands[1]);
--	DONE;
--      }
-+    /* FIXME: RR we still need to fix up what we are doing with
-+       symbol_refs and other types of constants.  */
-+    if (CONSTANT_P (operands[1])
-+        && !CONST_INT_P (operands[1]))
-+     {
-+       aarch64_expand_mov_immediate (operands[0], operands[1]);
-+       DONE;
-+     }
-   "
- )
- 
--(define_insn "*movsi_aarch64"
--  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,k,r,r,r,*w,m,  m,r,r  ,*w, r,*w")
--	(match_operand:SI 1 "aarch64_mov_operand"  " r,r,k,M,m, m,rZ,*w,S,Ush,rZ,*w,*w"))]
-+(define_insn_and_split "*movsi_aarch64"
-+  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,k,r,r,r,r,*w,m,  m,r,r  ,*w, r,*w")
-+	(match_operand:SI 1 "aarch64_mov_operand"  " r,r,k,M,n,m, m,rZ,*w,S,Ush,rZ,*w,*w"))]
-   "(register_operand (operands[0], SImode)
-     || aarch64_reg_or_zero (operands[1], SImode))"
-   "@
-@@ -659,6 +694,7 @@
-    mov\\t%w0, %w1
-    mov\\t%w0, %w1
-    mov\\t%w0, %1
-+   #
-    ldr\\t%w0, %1
-    ldr\\t%s0, %1
-    str\\t%w1, %0
-@@ -668,14 +704,20 @@
-    fmov\\t%s0, %w1
-    fmov\\t%w0, %s1
-    fmov\\t%s0, %s1"
--  [(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,load1,load1,store1,store1,\
--                     adr,adr,fmov,fmov,fmov")
--   (set_attr "fp" "*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes")]
-+   "CONST_INT_P (operands[1]) && !aarch64_move_imm (INTVAL (operands[1]), SImode)"
-+   [(const_int 0)]
-+   "{
-+       aarch64_expand_mov_immediate (operands[0], operands[1]);
-+       DONE;
-+    }"
-+  [(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,mov_imm,load1,load1,store1,store1,\
-+                     adr,adr,f_mcr,f_mrc,fmov")
-+   (set_attr "fp" "*,*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes")]
- )
- 
--(define_insn "*movdi_aarch64"
--  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,k,r,r,r,*w,m,  m,r,r,  *w, r,*w,w")
--	(match_operand:DI 1 "aarch64_mov_operand"  " r,r,k,N,m, m,rZ,*w,S,Ush,rZ,*w,*w,Dd"))]
-+(define_insn_and_split "*movdi_aarch64"
-+  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,k,r,r,r,r,*w,m,  m,r,r,  *w, r,*w,w")
-+	(match_operand:DI 1 "aarch64_mov_operand"  " r,r,k,N,n,m, m,rZ,*w,S,Ush,rZ,*w,*w,Dd"))]
-   "(register_operand (operands[0], DImode)
-     || aarch64_reg_or_zero (operands[1], DImode))"
-   "@
-@@ -683,6 +725,7 @@
-    mov\\t%0, %x1
-    mov\\t%x0, %1
-    mov\\t%x0, %1
-+   #
-    ldr\\t%x0, %1
-    ldr\\t%d0, %1
-    str\\t%x1, %0
-@@ -693,10 +736,16 @@
-    fmov\\t%x0, %d1
-    fmov\\t%d0, %d1
-    movi\\t%d0, %1"
--  [(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,load1,load1,store1,store1,\
--                     adr,adr,fmov,fmov,fmov,fmov")
--   (set_attr "fp" "*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*")
--   (set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,yes")]
-+   "(CONST_INT_P (operands[1]) && !aarch64_move_imm (INTVAL (operands[1]), DImode))"
-+   [(const_int 0)]
-+   "{
-+       aarch64_expand_mov_immediate (operands[0], operands[1]);
-+       DONE;
-+    }"
-+  [(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,mov_imm,load1,load1,store1,store1,\
-+                     adr,adr,f_mcr,f_mrc,fmov,fmov")
-+   (set_attr "fp" "*,*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*")
-+   (set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes")]
- )
- 
- (define_insn "insv_imm<mode>"
-@@ -789,7 +838,7 @@
-    str\\t%w1, %0
-    mov\\t%w0, %w1"
-   [(set_attr "type" "f_mcr,f_mrc,fmov,fconsts,\
--                     f_loads,f_stores,f_loads,f_stores,fmov")]
-+                     f_loads,f_stores,f_loads,f_stores,mov_reg")]
- )
- 
- (define_insn "*movdf_aarch64"
-@@ -863,6 +912,24 @@
-   }
- )
- 
-+;; 0 is dst
-+;; 1 is src
-+;; 2 is size of move in bytes
-+;; 3 is alignment
-+
-+(define_expand "movmemdi"
-+  [(match_operand:BLK 0 "memory_operand")
-+   (match_operand:BLK 1 "memory_operand")
-+   (match_operand:DI 2 "immediate_operand")
-+   (match_operand:DI 3 "immediate_operand")]
-+   "!STRICT_ALIGNMENT"
-+{
-+  if (aarch64_expand_movmem (operands))
-+    DONE;
-+  FAIL;
-+}
-+)
-+
- ;; Operands 1 and 3 are tied together by the final condition; so we allow
- ;; fairly lax checking on the second memory operation.
- (define_insn "load_pair<mode>"
-@@ -923,31 +990,45 @@
-   [(set_attr "type" "neon_store1_2reg<q>")]
- )
- 
--;; Load pair with writeback.  This is primarily used in function epilogues
--;; when restoring [fp,lr]
-+;; Load pair with post-index writeback.  This is primarily used in function
-+;; epilogues.
- (define_insn "loadwb_pair<GPI:mode>_<P:mode>"
-   [(parallel
-     [(set (match_operand:P 0 "register_operand" "=k")
-           (plus:P (match_operand:P 1 "register_operand" "0")
--                  (match_operand:P 4 "const_int_operand" "n")))
-+                  (match_operand:P 4 "aarch64_mem_pair_offset" "n")))
-      (set (match_operand:GPI 2 "register_operand" "=r")
--          (mem:GPI (plus:P (match_dup 1)
--                   (match_dup 4))))
-+          (mem:GPI (match_dup 1)))
-      (set (match_operand:GPI 3 "register_operand" "=r")
-           (mem:GPI (plus:P (match_dup 1)
-                    (match_operand:P 5 "const_int_operand" "n"))))])]
--  "INTVAL (operands[5]) == INTVAL (operands[4]) + GET_MODE_SIZE (<GPI:MODE>mode)"
-+  "INTVAL (operands[5]) == GET_MODE_SIZE (<GPI:MODE>mode)"
-   "ldp\\t%<w>2, %<w>3, [%1], %4"
-   [(set_attr "type" "load2")]
- )
- 
--;; Store pair with writeback.  This is primarily used in function prologues
--;; when saving [fp,lr]
-+(define_insn "loadwb_pair<GPF:mode>_<P:mode>"
-+  [(parallel
-+    [(set (match_operand:P 0 "register_operand" "=k")
-+          (plus:P (match_operand:P 1 "register_operand" "0")
-+                  (match_operand:P 4 "aarch64_mem_pair_offset" "n")))
-+     (set (match_operand:GPF 2 "register_operand" "=w")
-+          (mem:GPF (match_dup 1)))
-+     (set (match_operand:GPF 3 "register_operand" "=w")
-+          (mem:GPF (plus:P (match_dup 1)
-+                   (match_operand:P 5 "const_int_operand" "n"))))])]
-+  "INTVAL (operands[5]) == GET_MODE_SIZE (<GPF:MODE>mode)"
-+  "ldp\\t%<w>2, %<w>3, [%1], %4"
-+  [(set_attr "type" "neon_load1_2reg")]
-+)
-+
-+;; Store pair with pre-index writeback.  This is primarily used in function
-+;; prologues.
- (define_insn "storewb_pair<GPI:mode>_<P:mode>"
-   [(parallel
-     [(set (match_operand:P 0 "register_operand" "=&k")
-           (plus:P (match_operand:P 1 "register_operand" "0")
--                  (match_operand:P 4 "const_int_operand" "n")))
-+                  (match_operand:P 4 "aarch64_mem_pair_offset" "n")))
-      (set (mem:GPI (plus:P (match_dup 0)
-                    (match_dup 4)))
-           (match_operand:GPI 2 "register_operand" "r"))
-@@ -959,6 +1040,22 @@
-   [(set_attr "type" "store2")]
- )
- 
-+(define_insn "storewb_pair<GPF:mode>_<P:mode>"
-+  [(parallel
-+    [(set (match_operand:P 0 "register_operand" "=&k")
-+          (plus:P (match_operand:P 1 "register_operand" "0")
-+                  (match_operand:P 4 "aarch64_mem_pair_offset" "n")))
-+     (set (mem:GPF (plus:P (match_dup 0)
-+                   (match_dup 4)))
-+          (match_operand:GPF 2 "register_operand" "w"))
-+     (set (mem:GPF (plus:P (match_dup 0)
-+                   (match_operand:P 5 "const_int_operand" "n")))
-+          (match_operand:GPF 3 "register_operand" "w"))])]
-+  "INTVAL (operands[5]) == INTVAL (operands[4]) + GET_MODE_SIZE (<GPF:MODE>mode)"
-+  "stp\\t%<w>2, %<w>3, [%0, %4]!"
-+  [(set_attr "type" "neon_store1_2reg<q>")]
-+)
-+
- ;; -------------------------------------------------------------------
- ;; Sign/Zero extension
- ;; -------------------------------------------------------------------
-@@ -1063,16 +1160,18 @@
- 
- (define_insn "*addsi3_aarch64"
-   [(set
--    (match_operand:SI 0 "register_operand" "=rk,rk,rk")
-+    (match_operand:SI 0 "register_operand" "=rk,rk,w,rk")
-     (plus:SI
--     (match_operand:SI 1 "register_operand" "%rk,rk,rk")
--     (match_operand:SI 2 "aarch64_plus_operand" "I,r,J")))]
-+     (match_operand:SI 1 "register_operand" "%rk,rk,w,rk")
-+     (match_operand:SI 2 "aarch64_plus_operand" "I,r,w,J")))]
-   ""
-   "@
-   add\\t%w0, %w1, %2
-   add\\t%w0, %w1, %w2
-+  add\\t%0.2s, %1.2s, %2.2s
-   sub\\t%w0, %w1, #%n2"
--  [(set_attr "type" "alu_imm,alu_reg,alu_imm")]
-+  [(set_attr "type" "alu_imm,alu_reg,neon_add,alu_imm")
-+   (set_attr "simd" "*,*,yes,*")]
- )
- 
- ;; zero_extend version of above
-@@ -1106,7 +1205,26 @@
-    (set_attr "simd" "*,*,*,yes")]
- )
- 
--(define_insn "*add<mode>3_compare0"
-+(define_expand "addti3"
-+  [(set (match_operand:TI 0 "register_operand" "")
-+	(plus:TI (match_operand:TI 1 "register_operand" "")
-+		 (match_operand:TI 2 "register_operand" "")))]
-+  ""
-+{
-+  rtx low = gen_reg_rtx (DImode);
-+  emit_insn (gen_adddi3_compare0 (low, gen_lowpart (DImode, operands[1]),
-+				  gen_lowpart (DImode, operands[2])));
-+
-+  rtx high = gen_reg_rtx (DImode);
-+  emit_insn (gen_adddi3_carryin (high, gen_highpart (DImode, operands[1]),
-+				 gen_highpart (DImode, operands[2])));
-+
-+  emit_move_insn (gen_lowpart (DImode, operands[0]), low);
-+  emit_move_insn (gen_highpart (DImode, operands[0]), high);
-+  DONE;
-+})
-+
-+(define_insn "add<mode>3_compare0"
-   [(set (reg:CC_NZ CC_REGNUM)
- 	(compare:CC_NZ
- 	 (plus:GPI (match_operand:GPI 1 "register_operand" "%r,r,r")
-@@ -1390,7 +1508,7 @@
-   [(set_attr "type" "alu_ext")]
- )
- 
--(define_insn "*add<mode>3_carryin"
-+(define_insn "add<mode>3_carryin"
-   [(set
-     (match_operand:GPI 0 "register_operand" "=r")
-     (plus:GPI (geu:GPI (reg:CC CC_REGNUM) (const_int 0))
-@@ -1558,8 +1676,26 @@
-    (set_attr "simd" "*,yes")]
- )
- 
-+(define_expand "subti3"
-+  [(set (match_operand:TI 0 "register_operand" "")
-+	(minus:TI (match_operand:TI 1 "register_operand" "")
-+		  (match_operand:TI 2 "register_operand" "")))]
-+  ""
-+{
-+  rtx low = gen_reg_rtx (DImode);
-+  emit_insn (gen_subdi3_compare0 (low, gen_lowpart (DImode, operands[1]),
-+				  gen_lowpart (DImode, operands[2])));
- 
--(define_insn "*sub<mode>3_compare0"
-+  rtx high = gen_reg_rtx (DImode);
-+  emit_insn (gen_subdi3_carryin (high, gen_highpart (DImode, operands[1]),
-+				 gen_highpart (DImode, operands[2])));
-+
-+  emit_move_insn (gen_lowpart (DImode, operands[0]), low);
-+  emit_move_insn (gen_highpart (DImode, operands[0]), high);
-+  DONE;
-+})
-+
-+(define_insn "sub<mode>3_compare0"
-   [(set (reg:CC_NZ CC_REGNUM)
- 	(compare:CC_NZ (minus:GPI (match_operand:GPI 1 "register_operand" "r")
- 				  (match_operand:GPI 2 "register_operand" "r"))
-@@ -1706,7 +1842,7 @@
-   [(set_attr "type" "alu_ext")]
- )
- 
--(define_insn "*sub<mode>3_carryin"
-+(define_insn "sub<mode>3_carryin"
-   [(set
-     (match_operand:GPI 0 "register_operand" "=r")
-     (minus:GPI (minus:GPI
-@@ -1935,7 +2071,7 @@
-   [(set_attr "type" "mul")]
- )
- 
--(define_insn "*madd<mode>"
-+(define_insn "madd<mode>"
-   [(set (match_operand:GPI 0 "register_operand" "=r")
- 	(plus:GPI (mult:GPI (match_operand:GPI 1 "register_operand" "r")
- 			    (match_operand:GPI 2 "register_operand" "r"))
-@@ -2045,6 +2181,48 @@
-   [(set_attr "type" "<su>mull")]
- )
- 
-+(define_expand "<su_optab>mulditi3"
-+  [(set (match_operand:TI 0 "register_operand")
-+	(mult:TI (ANY_EXTEND:TI (match_operand:DI 1 "register_operand"))
-+		 (ANY_EXTEND:TI (match_operand:DI 2 "register_operand"))))]
-+  ""
-+{
-+  rtx low = gen_reg_rtx (DImode);
-+  emit_insn (gen_muldi3 (low, operands[1], operands[2]));
-+
-+  rtx high = gen_reg_rtx (DImode);
-+  emit_insn (gen_<su>muldi3_highpart (high, operands[1], operands[2]));
-+
-+  emit_move_insn (gen_lowpart (DImode, operands[0]), low);
-+  emit_move_insn (gen_highpart (DImode, operands[0]), high);
-+  DONE;
-+})
-+
-+;; The default expansion of multi3 using umuldi3_highpart will perform
-+;; the additions in an order that fails to combine into two madd insns.
-+(define_expand "multi3"
-+  [(set (match_operand:TI 0 "register_operand")
-+	(mult:TI (match_operand:TI 1 "register_operand")
-+		 (match_operand:TI 2 "register_operand")))]
-+  ""
-+{
-+  rtx l0 = gen_reg_rtx (DImode);
-+  rtx l1 = gen_lowpart (DImode, operands[1]);
-+  rtx l2 = gen_lowpart (DImode, operands[2]);
-+  rtx h0 = gen_reg_rtx (DImode);
-+  rtx h1 = gen_highpart (DImode, operands[1]);
-+  rtx h2 = gen_highpart (DImode, operands[2]);
-+
-+  emit_insn (gen_muldi3 (l0, l1, l2));
-+  emit_insn (gen_umuldi3_highpart (h0, l1, l2));
-+  emit_insn (gen_madddi (h0, h1, l2, h0));
-+  emit_insn (gen_madddi (h0, l1, h2, h0));
-+
-+  emit_move_insn (gen_lowpart (DImode, operands[0]), l0);
-+  emit_move_insn (gen_highpart (DImode, operands[0]), h0);
-+  DONE;
-+})
-+
- (define_insn "<su>muldi3_highpart"
-   [(set (match_operand:DI 0 "register_operand" "=r")
- 	(truncate:DI
-@@ -2345,11 +2523,46 @@
-   }
- )
- 
-+(define_expand "mov<mode>cc"
-+  [(set (match_operand:GPF 0 "register_operand" "")
-+	(if_then_else:GPF (match_operand 1 "aarch64_comparison_operator" "")
-+			  (match_operand:GPF 2 "register_operand" "")
-+			  (match_operand:GPF 3 "register_operand" "")))]
-+  ""
-+  {
-+    rtx ccreg;
-+    enum rtx_code code = GET_CODE (operands[1]);
-+
-+    if (code == UNEQ || code == LTGT)
-+      FAIL;
-+
-+    ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
-+				  XEXP (operands[1], 1));
-+    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
-+  }
-+)
-+
-+
-+;; CRC32 instructions.
-+(define_insn "aarch64_<crc_variant>"
-+  [(set (match_operand:SI 0 "register_operand" "=r")
-+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
-+                    (match_operand:<crc_mode> 2 "register_operand" "r")]
-+         CRC))]
-+  "TARGET_CRC32"
-+  {
-+    if (GET_MODE_BITSIZE (GET_MODE (operands[2])) >= 64)
-+      return "<crc_variant>\\t%w0, %w1, %x2";
-+    else
-+      return "<crc_variant>\\t%w0, %w1, %w2";
-+  }
-+  [(set_attr "type" "crc")]
-+)
-+
- (define_insn "*csinc2<mode>_insn"
-   [(set (match_operand:GPI 0 "register_operand" "=r")
--        (plus:GPI (match_operator:GPI 2 "aarch64_comparison_operator"
--		  [(match_operand:CC 3 "cc_register" "") (const_int 0)])
--		 (match_operand:GPI 1 "register_operand" "r")))]
-+        (plus:GPI (match_operand 2 "aarch64_comparison_operation" "")
-+                  (match_operand:GPI 1 "register_operand" "r")))]
-   ""
-   "csinc\\t%<w>0, %<w>1, %<w>1, %M2"
-   [(set_attr "type" "csel")]
-@@ -2358,13 +2571,12 @@
- (define_insn "csinc3<mode>_insn"
-   [(set (match_operand:GPI 0 "register_operand" "=r")
-         (if_then_else:GPI
--	  (match_operator:GPI 1 "aarch64_comparison_operator"
--	   [(match_operand:CC 2 "cc_register" "") (const_int 0)])
--	  (plus:GPI (match_operand:GPI 3 "register_operand" "r")
-+	  (match_operand 1 "aarch64_comparison_operation" "")
-+	  (plus:GPI (match_operand:GPI 2 "register_operand" "r")
- 		    (const_int 1))
--	  (match_operand:GPI 4 "aarch64_reg_or_zero" "rZ")))]
-+	  (match_operand:GPI 3 "aarch64_reg_or_zero" "rZ")))]
-   ""
--  "csinc\\t%<w>0, %<w>4, %<w>3, %M1"
-+  "csinc\\t%<w>0, %<w>3, %<w>2, %M1"
-   [(set_attr "type" "csel")]
- )
- 
-@@ -2371,12 +2583,11 @@
- (define_insn "*csinv3<mode>_insn"
-   [(set (match_operand:GPI 0 "register_operand" "=r")
-         (if_then_else:GPI
--	  (match_operator:GPI 1 "aarch64_comparison_operator"
--	   [(match_operand:CC 2 "cc_register" "") (const_int 0)])
--	  (not:GPI (match_operand:GPI 3 "register_operand" "r"))
--	  (match_operand:GPI 4 "aarch64_reg_or_zero" "rZ")))]
-+	  (match_operand 1 "aarch64_comparison_operation" "")
-+	  (not:GPI (match_operand:GPI 2 "register_operand" "r"))
-+	  (match_operand:GPI 3 "aarch64_reg_or_zero" "rZ")))]
-   ""
--  "csinv\\t%<w>0, %<w>4, %<w>3, %M1"
-+  "csinv\\t%<w>0, %<w>3, %<w>2, %M1"
-   [(set_attr "type" "csel")]
- )
- 
-@@ -2383,12 +2594,11 @@
- (define_insn "*csneg3<mode>_insn"
-   [(set (match_operand:GPI 0 "register_operand" "=r")
-         (if_then_else:GPI
--	  (match_operator:GPI 1 "aarch64_comparison_operator"
--	   [(match_operand:CC 2 "cc_register" "") (const_int 0)])
--	  (neg:GPI (match_operand:GPI 3 "register_operand" "r"))
--	  (match_operand:GPI 4 "aarch64_reg_or_zero" "rZ")))]
-+	  (match_operand 1 "aarch64_comparison_operation" "")
-+	  (neg:GPI (match_operand:GPI 2 "register_operand" "r"))
-+	  (match_operand:GPI 3 "aarch64_reg_or_zero" "rZ")))]
-   ""
--  "csneg\\t%<w>0, %<w>4, %<w>3, %M1"
-+  "csneg\\t%<w>0, %<w>3, %<w>2, %M1"
-   [(set_attr "type" "csel")]
- )
- 
-@@ -2486,7 +2696,18 @@
-   [(set_attr "type" "logic_shift_imm")]
- )
- 
--;; zero_extend version of above
-+(define_insn "*<optab>_rol<mode>3"
-+  [(set (match_operand:GPI 0 "register_operand" "=r")
-+	(LOGICAL:GPI (rotate:GPI
-+		      (match_operand:GPI 1 "register_operand" "r")
-+		      (match_operand:QI 2 "aarch64_shift_imm_<mode>" "n"))
-+		     (match_operand:GPI 3 "register_operand" "r")))]
-+  ""
-+  "<logical>\\t%<w>0, %<w>3, %<w>1, ror (<sizen> - %2)"
-+  [(set_attr "type" "logic_shift_imm")]
-+)
-+
-+;; zero_extend versions of above
- (define_insn "*<LOGICAL:optab>_<SHIFT:optab>si3_uxtw"
-   [(set (match_operand:DI 0 "register_operand" "=r")
- 	(zero_extend:DI
-@@ -2499,6 +2720,18 @@
-   [(set_attr "type" "logic_shift_imm")]
- )
- 
-+(define_insn "*<optab>_rolsi3_uxtw"
-+  [(set (match_operand:DI 0 "register_operand" "=r")
-+	(zero_extend:DI
-+	 (LOGICAL:SI (rotate:SI
-+		      (match_operand:SI 1 "register_operand" "r")
-+		      (match_operand:QI 2 "aarch64_shift_imm_si" "n"))
-+		     (match_operand:SI 3 "register_operand" "r"))))]
-+  ""
-+  "<logical>\\t%w0, %w3, %w1, ror (32 - %2)"
-+  [(set_attr "type" "logic_shift_imm")]
-+)
-+
- (define_insn "one_cmpl<mode>2"
-   [(set (match_operand:GPI 0 "register_operand" "=r")
- 	(not:GPI (match_operand:GPI 1 "register_operand" "r")))]
-@@ -2622,7 +2855,7 @@
- 
-     emit_insn (gen_rbit<mode>2 (operands[0], operands[1]));
-     emit_insn (gen_clz<mode>2 (operands[0], operands[0]));
--    emit_insn (gen_csinc3<mode>_insn (operands[0], x, ccreg, operands[0], const0_rtx));
-+    emit_insn (gen_csinc3<mode>_insn (operands[0], x, operands[0], const0_rtx));
-     DONE;
-   }
- )
-@@ -2629,7 +2862,7 @@
- 
- (define_insn "clrsb<mode>2"
-   [(set (match_operand:GPI 0 "register_operand" "=r")
--	(unspec:GPI [(match_operand:GPI 1 "register_operand" "r")] UNSPEC_CLS))]
-+        (clrsb:GPI (match_operand:GPI 1 "register_operand" "r")))]
-   ""
-   "cls\\t%<w>0, %<w>1"
-   [(set_attr "type" "clz")]
-@@ -3125,7 +3358,7 @@
-   [(set (zero_extract:GPI (match_operand:GPI 0 "register_operand" "+r")
- 			  (match_operand 1 "const_int_operand" "n")
- 			  (const_int 0))
--	(zero_extract:GPI (match_operand:GPI 2 "register_operand" "+r")
-+	(zero_extract:GPI (match_operand:GPI 2 "register_operand" "r")
- 			  (match_dup 1)
- 			  (match_operand 3 "const_int_operand" "n")))]
-   "!(UINTVAL (operands[1]) == 0
-@@ -3180,6 +3413,38 @@
-   [(set_attr "type" "rev")]
- )
- 
-+;; There are no canonicalisation rules for the position of the lshiftrt, ashift
-+;; operations within an IOR/AND RTX, therefore we have two patterns matching
-+;; each valid permutation.
-+
-+(define_insn "rev16<mode>2"
-+  [(set (match_operand:GPI 0 "register_operand" "=r")
-+        (ior:GPI (and:GPI (ashift:GPI (match_operand:GPI 1 "register_operand" "r")
-+                                      (const_int 8))
-+                          (match_operand:GPI 3 "const_int_operand" "n"))
-+                 (and:GPI (lshiftrt:GPI (match_dup 1)
-+                                        (const_int 8))
-+                          (match_operand:GPI 2 "const_int_operand" "n"))))]
-+  "aarch_rev16_shleft_mask_imm_p (operands[3], <MODE>mode)
-+   && aarch_rev16_shright_mask_imm_p (operands[2], <MODE>mode)"
-+  "rev16\\t%<w>0, %<w>1"
-+  [(set_attr "type" "rev")]
-+)
-+
-+(define_insn "rev16<mode>2_alt"
-+  [(set (match_operand:GPI 0 "register_operand" "=r")
-+        (ior:GPI (and:GPI (lshiftrt:GPI (match_operand:GPI 1 "register_operand" "r")
-+                                        (const_int 8))
-+                          (match_operand:GPI 2 "const_int_operand" "n"))
-+                 (and:GPI (ashift:GPI (match_dup 1)
-+                                      (const_int 8))
-+                          (match_operand:GPI 3 "const_int_operand" "n"))))]
-+  "aarch_rev16_shleft_mask_imm_p (operands[3], <MODE>mode)
-+   && aarch_rev16_shright_mask_imm_p (operands[2], <MODE>mode)"
-+  "rev16\\t%<w>0, %<w>1"
-+  [(set_attr "type" "rev")]
-+)
-+
- ;; zero_extend version of above
- (define_insn "*bswapsi2_uxtw"
-   [(set (match_operand:DI 0 "register_operand" "=r")
-@@ -3194,7 +3459,7 @@
- ;; -------------------------------------------------------------------
- 
- ;; frint floating-point round to integral standard patterns.
--;; Expands to btrunc, ceil, floor, nearbyint, rint, round.
-+;; Expands to btrunc, ceil, floor, nearbyint, rint, round, frintn.
- 
- (define_insn "<frint_pattern><mode>2"
-   [(set (match_operand:GPF 0 "register_operand" "=w")
-@@ -3305,20 +3570,24 @@
-   [(set_attr "type" "f_cvtf2i")]
- )
- 
--(define_insn "float<GPI:mode><GPF:mode>2"
--  [(set (match_operand:GPF 0 "register_operand" "=w")
--        (float:GPF (match_operand:GPI 1 "register_operand" "r")))]
--  "TARGET_FLOAT"
--  "scvtf\\t%<GPF:s>0, %<GPI:w>1"
--  [(set_attr "type" "f_cvti2f")]
-+(define_insn "<optab><fcvt_target><GPF:mode>2"
-+  [(set (match_operand:GPF 0 "register_operand" "=w,w")
-+        (FLOATUORS:GPF (match_operand:<FCVT_TARGET> 1 "register_operand" "w,r")))]
-+  ""
-+  "@
-+   <su_optab>cvtf\t%<GPF:s>0, %<s>1
-+   <su_optab>cvtf\t%<GPF:s>0, %<w1>1"
-+  [(set_attr "simd" "yes,no")
-+   (set_attr "fp" "no,yes")
-+   (set_attr "type" "neon_int_to_fp_<Vetype>,f_cvti2f")]
- )
- 
--(define_insn "floatuns<GPI:mode><GPF:mode>2"
-+(define_insn "<optab><fcvt_iesize><GPF:mode>2"
-   [(set (match_operand:GPF 0 "register_operand" "=w")
--        (unsigned_float:GPF (match_operand:GPI 1 "register_operand" "r")))]
-+        (FLOATUORS:GPF (match_operand:<FCVT_IESIZE> 1 "register_operand" "r")))]
-   "TARGET_FLOAT"
--  "ucvtf\\t%<GPF:s>0, %<GPI:w>1"
--  [(set_attr "type" "f_cvt")]
-+  "<su_optab>cvtf\t%<GPF:s>0, %<w2>1"
-+  [(set_attr "type" "f_cvti2f")]
- )
- 
- ;; -------------------------------------------------------------------
-@@ -3490,7 +3759,7 @@
- 	  (truncate:DI (match_operand:TI 1 "register_operand" "w"))))]
-   "reload_completed || reload_in_progress"
-   "fmov\\t%d0, %d1"
--  [(set_attr "type" "f_mcr")
-+  [(set_attr "type" "fmov")
-    (set_attr "length" "4")
-   ])
- 
-@@ -3588,36 +3857,63 @@
-   [(set_attr "type" "call")
-    (set_attr "length" "16")])
- 
--(define_insn "tlsie_small"
--  [(set (match_operand:DI 0 "register_operand" "=r")
--        (unspec:DI [(match_operand:DI 1 "aarch64_tls_ie_symref" "S")]
-+(define_insn "tlsie_small_<mode>"
-+  [(set (match_operand:PTR 0 "register_operand" "=r")
-+        (unspec:PTR [(match_operand 1 "aarch64_tls_ie_symref" "S")]
- 		   UNSPEC_GOTSMALLTLS))]
-   ""
--  "adrp\\t%0, %A1\;ldr\\t%0, [%0, #%L1]"
-+  "adrp\\t%0, %A1\;ldr\\t%<w>0, [%0, #%L1]"
-   [(set_attr "type" "load1")
-    (set_attr "length" "8")]
- )
- 
--(define_insn "tlsle_small"
-+(define_insn "tlsie_small_sidi"
-   [(set (match_operand:DI 0 "register_operand" "=r")
--        (unspec:DI [(match_operand:DI 1 "register_operand" "r")
--                   (match_operand:DI 2 "aarch64_tls_le_symref" "S")]
-+	(zero_extend:DI
-+          (unspec:SI [(match_operand 1 "aarch64_tls_ie_symref" "S")]
-+		      UNSPEC_GOTSMALLTLS)))]
-+  ""
-+  "adrp\\t%0, %A1\;ldr\\t%w0, [%0, #%L1]"
-+  [(set_attr "type" "load1")
-+   (set_attr "length" "8")]
-+)
-+
-+(define_expand "tlsle_small"
-+  [(set (match_operand 0 "register_operand" "=r")
-+        (unspec [(match_operand 1 "register_operand" "r")
-+                   (match_operand 2 "aarch64_tls_le_symref" "S")]
-+                   UNSPEC_GOTSMALLTLS))]
-+  ""
-+{
-+  enum machine_mode mode = GET_MODE (operands[0]);
-+  emit_insn ((mode == DImode
-+	      ? gen_tlsle_small_di
-+	      : gen_tlsle_small_si) (operands[0],
-+				     operands[1],
-+				     operands[2]));
-+  DONE;
-+})
-+
-+(define_insn "tlsle_small_<mode>"
-+  [(set (match_operand:P 0 "register_operand" "=r")
-+        (unspec:P [(match_operand:P 1 "register_operand" "r")
-+                   (match_operand 2 "aarch64_tls_le_symref" "S")]
- 		   UNSPEC_GOTSMALLTLS))]
-   ""
--  "add\\t%0, %1, #%G2\;add\\t%0, %0, #%L2"
-+  "add\\t%<w>0, %<w>1, #%G2\;add\\t%<w>0, %<w>0, #%L2"
-   [(set_attr "type" "alu_reg")
-    (set_attr "length" "8")]
- )
- 
--(define_insn "tlsdesc_small"
--  [(set (reg:DI R0_REGNUM)
--        (unspec:DI [(match_operand:DI 0 "aarch64_valid_symref" "S")]
-+(define_insn "tlsdesc_small_<mode>"
-+  [(set (reg:PTR R0_REGNUM)
-+        (unspec:PTR [(match_operand 0 "aarch64_valid_symref" "S")]
- 		   UNSPEC_TLSDESC))
-    (clobber (reg:DI LR_REGNUM))
-    (clobber (reg:CC CC_REGNUM))
-    (clobber (match_scratch:DI 1 "=r"))]
-   "TARGET_TLS_DESC"
--  "adrp\\tx0, %A0\;ldr\\t%1, [x0, #%L0]\;add\\tx0, x0, %L0\;.tlsdesccall\\t%0\;blr\\t%1"
-+  "adrp\\tx0, %A0\;ldr\\t%<w>1, [x0, #%L0]\;add\\t<w>0, <w>0, %L0\;.tlsdesccall\\t%0\;blr\\t%1"
-   [(set_attr "type" "call")
-    (set_attr "length" "16")])
- 
-@@ -3642,6 +3938,135 @@
-   DONE;
- })
- 
-+;; Named patterns for stack smashing protection.
-+(define_expand "stack_protect_set"
-+  [(match_operand 0 "memory_operand")
-+   (match_operand 1 "memory_operand")]
-+  ""
-+{
-+  enum machine_mode mode = GET_MODE (operands[0]);
-+
-+  emit_insn ((mode == DImode
-+	      ? gen_stack_protect_set_di
-+	      : gen_stack_protect_set_si) (operands[0], operands[1]));
-+  DONE;
-+})
-+
-+(define_insn "stack_protect_set_<mode>"
-+  [(set (match_operand:PTR 0 "memory_operand" "=m")
-+	(unspec:PTR [(match_operand:PTR 1 "memory_operand" "m")]
-+	 UNSPEC_SP_SET))
-+   (set (match_scratch:PTR 2 "=&r") (const_int 0))]
-+  ""
-+  "ldr\\t%<w>2, %1\;str\\t%<w>2, %0\;mov\t%<w>2,0"
-+  [(set_attr "length" "12")
-+   (set_attr "type" "multiple")])
-+
-+(define_expand "stack_protect_test"
-+  [(match_operand 0 "memory_operand")
-+   (match_operand 1 "memory_operand")
-+   (match_operand 2)]
-+  ""
-+{
-+  rtx result;
-+  enum machine_mode mode = GET_MODE (operands[0]);
-+
-+  result = gen_reg_rtx(mode);
-+
-+  emit_insn ((mode == DImode
-+	      ? gen_stack_protect_test_di
-+	      : gen_stack_protect_test_si) (result,
-+					    operands[0],
-+					    operands[1]));
-+
-+  if (mode == DImode)
-+    emit_jump_insn (gen_cbranchdi4 (gen_rtx_EQ (VOIDmode, result, const0_rtx),
-+				    result, const0_rtx, operands[2]));
-+  else
-+    emit_jump_insn (gen_cbranchsi4 (gen_rtx_EQ (VOIDmode, result, const0_rtx),
-+				    result, const0_rtx, operands[2]));
-+  DONE;
-+})
-+
-+(define_insn "stack_protect_test_<mode>"
-+  [(set (match_operand:PTR 0 "register_operand" "=r")
-+	(unspec:PTR [(match_operand:PTR 1 "memory_operand" "m")
-+		     (match_operand:PTR 2 "memory_operand" "m")]
-+	 UNSPEC_SP_TEST))
-+   (clobber (match_scratch:PTR 3 "=&r"))]
-+  ""
-+  "ldr\t%<w>3, %x1\;ldr\t%<w>0, %x2\;eor\t%<w>0, %<w>3, %<w>0"
-+  [(set_attr "length" "12")
-+   (set_attr "type" "multiple")])
-+
-+;; Write Floating-point Control Register.
-+(define_insn "set_fpcr"
-+  [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] UNSPECV_SET_FPCR)]
-+  ""
-+  "msr\\tfpcr, %0"
-+  [(set_attr "type" "mrs")])
-+
-+;; Read Floating-point Control Register.
-+(define_insn "get_fpcr"
-+  [(set (match_operand:SI 0 "register_operand" "=r")
-+        (unspec_volatile:SI [(const_int 0)] UNSPECV_GET_FPCR))]
-+  ""
-+  "mrs\\t%0, fpcr"
-+  [(set_attr "type" "mrs")])
-+
-+;; Write Floating-point Status Register.
-+(define_insn "set_fpsr"
-+  [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] UNSPECV_SET_FPSR)]
-+  ""
-+  "msr\\tfpsr, %0"
-+  [(set_attr "type" "mrs")])
-+
-+;; Read Floating-point Status Register.
-+(define_insn "get_fpsr"
-+  [(set (match_operand:SI 0 "register_operand" "=r")
-+        (unspec_volatile:SI [(const_int 0)] UNSPECV_GET_FPSR))]
-+  ""
-+  "mrs\\t%0, fpsr"
-+  [(set_attr "type" "mrs")])
-+
-+
-+;; Define the subtract-one-and-jump insns so loop.c
-+;; knows what to generate.
-+(define_expand "doloop_end"
-+  [(use (match_operand 0 "" ""))      ; loop pseudo
-+   (use (match_operand 1 "" ""))]     ; label
-+  "optimize > 0 && flag_modulo_sched"
-+{
-+  rtx s0;
-+  rtx bcomp;
-+  rtx loc_ref;
-+  rtx cc_reg;
-+  rtx insn;
-+  rtx cmp;
-+
-+  /* Currently SMS relies on the do-loop pattern to recognize loops
-+     where (1) the control part consists of all insns defining and/or
-+     using a certain 'count' register and (2) the loop count can be
-+     adjusted by modifying this register prior to the loop.
-+     ??? The possible introduction of a new block to initialize the
-+     new IV can potentially affect branch optimizations.  */
-+
-+  if (GET_MODE (operands[0]) != DImode)
-+    FAIL;
-+
-+  s0 = operands [0];
-+  insn = emit_insn (gen_adddi3_compare0 (s0, s0, GEN_INT (-1)));
-+
-+  cmp = XVECEXP (PATTERN (insn), 0, 0);
-+  cc_reg = SET_DEST (cmp);
-+  bcomp = gen_rtx_NE (VOIDmode, cc_reg, const0_rtx);
-+  loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands [1]);
-+  emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
-+			       gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp,
-+						     loc_ref, pc_rtx)));
-+  DONE;
-+})
-+
- ;; AdvSIMD Stuff
- (include "aarch64-simd.md")
- 
---- a/src/gcc/config/aarch64/t-aarch64
-+++ b/src/gcc/config/aarch64/t-aarch64
-@@ -31,10 +31,17 @@
-   $(SYSTEM_H) coretypes.h $(TM_H) \
-   $(RTL_H) $(TREE_H) expr.h $(TM_P_H) $(RECOG_H) langhooks.h \
-   $(DIAGNOSTIC_CORE_H) $(OPTABS_H) \
--  $(srcdir)/config/aarch64/aarch64-simd-builtins.def
-+  $(srcdir)/config/aarch64/aarch64-simd-builtins.def \
-+  aarch64-builtin-iterators.h
- 	$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
- 		$(srcdir)/config/aarch64/aarch64-builtins.c
- 
-+aarch64-builtin-iterators.h: $(srcdir)/config/aarch64/geniterators.sh \
-+	$(srcdir)/config/aarch64/iterators.md
-+	$(SHELL) $(srcdir)/config/aarch64/geniterators.sh \
-+		$(srcdir)/config/aarch64/iterators.md > \
-+		aarch64-builtin-iterators.h
-+
- aarch-common.o: $(srcdir)/config/arm/aarch-common.c $(CONFIG_H) $(SYSTEM_H) \
-     coretypes.h $(TM_H) $(TM_P_H) $(RTL_H) $(TREE_H) output.h $(C_COMMON_H)
- 	$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
---- a/src/gcc/config/aarch64/arm_acle.h
-+++ b/src/gcc/config/aarch64/arm_acle.h
-@@ -0,0 +1,90 @@
-+/* AArch64 Non-NEON ACLE intrinsics include file.
-+
-+   Copyright (C) 2014 Free Software Foundation, Inc.
-+   Contributed by ARM Ltd.
-+
-+   This file is part of GCC.
-+
-+   GCC is free software; you can redistribute it and/or modify it
-+   under the terms of the GNU General Public License as published
-+   by the Free Software Foundation; either version 3, or (at your
-+   option) any later version.
-+
-+   GCC is distributed in the hope that it will be useful, but WITHOUT
-+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
-+   License for more details.
-+
-+   Under Section 7 of GPL version 3, you are granted additional
-+   permissions described in the GCC Runtime Library Exception, version
-+   3.1, as published by the Free Software Foundation.
-+
-+   You should have received a copy of the GNU General Public License and
-+   a copy of the GCC Runtime Library Exception along with this program;
-+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
-+   <http://www.gnu.org/licenses/>.  */
-+
-+#ifndef _GCC_ARM_ACLE_H
-+#define _GCC_ARM_ACLE_H
-+
-+#include <stdint.h>
-+#ifdef __cplusplus
-+extern "C" {
-+#endif
-+
-+#ifdef __ARM_FEATURE_CRC32
-+__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
-+__crc32b (uint32_t __a, uint8_t __b)
-+{
-+  return __builtin_aarch64_crc32b (__a, __b);
-+}
-+
-+__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
-+__crc32cb (uint32_t __a, uint8_t __b)
-+{
-+  return __builtin_aarch64_crc32cb (__a, __b);
-+}
-+
-+__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
-+__crc32ch (uint32_t __a, uint16_t __b)
-+{
-+  return __builtin_aarch64_crc32ch (__a, __b);
-+}
-+
-+__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
-+__crc32cw (uint32_t __a, uint32_t __b)
-+{
-+  return __builtin_aarch64_crc32cw (__a, __b);
-+}
-+
-+__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
-+__crc32cd (uint32_t __a, uint64_t __b)
-+{
-+  return __builtin_aarch64_crc32cx (__a, __b);
-+}
-+
-+__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
-+__crc32h (uint32_t __a, uint16_t __b)
-+{
-+  return __builtin_aarch64_crc32h (__a, __b);
-+}
-+
-+__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
-+__crc32w (uint32_t __a, uint32_t __b)
-+{
-+  return __builtin_aarch64_crc32w (__a, __b);
-+}
-+
-+__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
-+__crc32d (uint32_t __a, uint64_t __b)
-+{
-+  return __builtin_aarch64_crc32x (__a, __b);
-+}
-+
-+#endif
-+
-+#ifdef __cplusplus
-+}
-+#endif
-+
-+#endif
---- a/src/gcc/config/aarch64/aarch64-cost-tables.h
-+++ b/src/gcc/config/aarch64/aarch64-cost-tables.h
-@@ -0,0 +1,131 @@
-+/* RTX cost tables for AArch64.
-+
-+   Copyright (C) 2014 Free Software Foundation, Inc.
-+
-+   This file is part of GCC.
-+
-+   GCC is free software; you can redistribute it and/or modify it
-+   under the terms of the GNU General Public License as published
-+   by the Free Software Foundation; either version 3, or (at your
-+   option) any later version.
-+
-+   GCC is distributed in the hope that it will be useful, but WITHOUT
-+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
-+   License for more details.
-+
-+   You should have received a copy of the GNU General Public License
-+   along with GCC; see the file COPYING3.  If not see
-+   <http://www.gnu.org/licenses/>.  */
-+
-+#ifndef GCC_AARCH64_COST_TABLES_H
-+#define GCC_AARCH64_COST_TABLES_H
-+
-+#include "config/arm/aarch-cost-tables.h"
-+
-+/* ThunderX does not have implement AArch32.  */
-+const struct cpu_cost_table thunderx_extra_costs =
-+{
-+  /* ALU */
-+  {
-+    0,			/* Arith.  */
-+    0,			/* Logical.  */
-+    0,			/* Shift.  */
-+    0,			/* Shift_reg.  */
-+    COSTS_N_INSNS (1),	/* Arith_shift.  */
-+    COSTS_N_INSNS (1),	/* Arith_shift_reg.  */
-+    COSTS_N_INSNS (1),	/* UNUSED: Log_shift.  */
-+    COSTS_N_INSNS (1),	/* UNUSED: Log_shift_reg.  */
-+    0,			/* Extend.  */
-+    COSTS_N_INSNS (1),	/* Extend_arith.  */
-+    0,			/* Bfi.  */
-+    0,			/* Bfx.  */
-+    COSTS_N_INSNS (5),	/* Clz.  */
-+    0,			/* rev.  */
-+    0,			/* UNUSED: non_exec.  */
-+    false		/* UNUSED: non_exec_costs_exec.  */
-+  },
-+  {
-+    /* MULT SImode */
-+    {
-+      COSTS_N_INSNS (3),	/* Simple.  */
-+      0,			/* Flag_setting.  */
-+      0,			/* Extend.  */
-+      0,			/* Add.  */
-+      COSTS_N_INSNS (1),	/* Extend_add.  */
-+      COSTS_N_INSNS (21)	/* Idiv.  */
-+    },
-+    /* MULT DImode */
-+    {
-+      COSTS_N_INSNS (3),	/* Simple.  */
-+      0,			/* Flag_setting.  */
-+      0,			/* Extend.  */
-+      0,			/* Add.  */
-+      COSTS_N_INSNS (1),	/* Extend_add.  */
-+      COSTS_N_INSNS (37)	/* Idiv.  */
-+    },
-+  },
-+  /* LD/ST */
-+  {
-+    COSTS_N_INSNS (2),	/* Load.  */
-+    COSTS_N_INSNS (2),	/* Load_sign_extend.  */
-+    COSTS_N_INSNS (2),	/* Ldrd.  */
-+    0,			/* N/A: Ldm_1st.  */
-+    0,			/* N/A: Ldm_regs_per_insn_1st.  */
-+    0,			/* N/A: Ldm_regs_per_insn_subsequent.  */
-+    COSTS_N_INSNS (3),	/* Loadf.  */
-+    COSTS_N_INSNS (3),	/* Loadd.  */
-+    0,  		/* N/A: Load_unaligned.  */
-+    0,			/* Store.  */
-+    0,			/* Strd.  */
-+    0,			/* N/A: Stm_1st.  */
-+    0,			/* N/A: Stm_regs_per_insn_1st.  */
-+    0,			/* N/A: Stm_regs_per_insn_subsequent.  */
-+    0,			/* Storef.  */
-+    0,			/* Stored.  */
-+    COSTS_N_INSNS (1)  /* Store_unaligned.  */
-+  },
-+  {
-+    /* FP SFmode */
-+    {
-+      COSTS_N_INSNS (11),	/* Div.  */
-+      COSTS_N_INSNS (5),	/* Mult.  */
-+      COSTS_N_INSNS (5),	/* Mult_addsub.  */
-+      COSTS_N_INSNS (5),	/* Fma.  */
-+      COSTS_N_INSNS (3),	/* Addsub.  */
-+      0,			/* Fpconst.  */
-+      COSTS_N_INSNS (1),	/* Neg.  */
-+      0,			/* Compare.  */
-+      COSTS_N_INSNS (5),	/* Widen.  */
-+      COSTS_N_INSNS (5),	/* Narrow.  */
-+      COSTS_N_INSNS (5),	/* Toint.  */
-+      COSTS_N_INSNS (5),	/* Fromint.  */
-+      COSTS_N_INSNS (1)		/* Roundint.  */
-+    },
-+    /* FP DFmode */
-+    {
-+      COSTS_N_INSNS (21),	/* Div.  */
-+      COSTS_N_INSNS (5),	/* Mult.  */
-+      COSTS_N_INSNS (5),	/* Mult_addsub.  */
-+      COSTS_N_INSNS (5),	/* Fma.  */
-+      COSTS_N_INSNS (3),	/* Addsub.  */
-+      0,			/* Fpconst.  */
-+      COSTS_N_INSNS (1),	/* Neg.  */
-+      0,			/* Compare.  */
-+      COSTS_N_INSNS (5),	/* Widen.  */
-+      COSTS_N_INSNS (5),	/* Narrow.  */
-+      COSTS_N_INSNS (5),	/* Toint.  */
-+      COSTS_N_INSNS (5),	/* Fromint.  */
-+      COSTS_N_INSNS (1)		/* Roundint.  */
-+    }
-+  },
-+  /* Vector */
-+  {
-+    COSTS_N_INSNS (1)	/* Alu.  */
-+  }
-+};
-+
-+
-+
-+#endif
-+
---- a/src/gcc/config/aarch64/aarch64-cores.def
-+++ b/src/gcc/config/aarch64/aarch64-cores.def
-@@ -34,9 +34,10 @@
- 
- /* V8 Architecture Processors.  */
- 
--AARCH64_CORE("cortex-a53",  cortexa53, cortexa53, 8,  AARCH64_FL_FPSIMD | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, cortexa53)
--AARCH64_CORE("cortex-a57",  cortexa15, cortexa15, 8,  AARCH64_FL_FPSIMD | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, cortexa57)
-+AARCH64_CORE("cortex-a53",  cortexa53, cortexa53, 8,  AARCH64_FL_FPSIMD | AARCH64_FL_CRC, cortexa53)
-+AARCH64_CORE("cortex-a57",  cortexa15, cortexa15, 8,  AARCH64_FL_FPSIMD | AARCH64_FL_CRC, cortexa57)
-+AARCH64_CORE("thunderx",    thunderx,  thunderx, 8,  AARCH64_FL_FPSIMD | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx)
- 
- /* V8 big.LITTLE implementations.  */
- 
--AARCH64_CORE("cortex-a57.cortex-a53",  cortexa57cortexa53, cortexa53, 8,  AARCH64_FL_FPSIMD | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, cortexa57)
-+AARCH64_CORE("cortex-a57.cortex-a53",  cortexa57cortexa53, cortexa53, 8,  AARCH64_FL_FPSIMD | AARCH64_FL_CRC, cortexa57)
---- a/src/gcc/config/aarch64/atomics.md
-+++ b/src/gcc/config/aarch64/atomics.md
-@@ -119,7 +119,7 @@
-   [(set (match_operand:ALLI 0 "aarch64_sync_memory_operand" "+Q")
-     (unspec_volatile:ALLI
-       [(atomic_op:ALLI (match_dup 0)
--	(match_operand:ALLI 1 "<atomic_op_operand>" "rn"))
-+	(match_operand:ALLI 1 "<atomic_op_operand>" "r<lconst_atomic>"))
-        (match_operand:SI 2 "const_int_operand")]		;; model
-       UNSPECV_ATOMIC_OP))
-        (clobber (reg:CC CC_REGNUM))
-@@ -141,7 +141,7 @@
-     (unspec_volatile:ALLI
-       [(not:ALLI
- 	(and:ALLI (match_dup 0)
--	  (match_operand:ALLI 1 "aarch64_logical_operand" "rn")))
-+	  (match_operand:ALLI 1 "aarch64_logical_operand" "r<lconst_atomic>")))
-        (match_operand:SI 2 "const_int_operand")]		;; model
-       UNSPECV_ATOMIC_OP))
-    (clobber (reg:CC CC_REGNUM))
-@@ -164,7 +164,7 @@
-    (set (match_dup 1)
-     (unspec_volatile:ALLI
-       [(atomic_op:ALLI (match_dup 1)
--	(match_operand:ALLI 2 "<atomic_op_operand>" "rn"))
-+	(match_operand:ALLI 2 "<atomic_op_operand>" "r<lconst_atomic>"))
-        (match_operand:SI 3 "const_int_operand")]		;; model
-       UNSPECV_ATOMIC_OP))
-    (clobber (reg:CC CC_REGNUM))
-@@ -188,7 +188,7 @@
-     (unspec_volatile:ALLI
-       [(not:ALLI
- 	 (and:ALLI (match_dup 1)
--	   (match_operand:ALLI 2 "aarch64_logical_operand" "rn")))
-+	   (match_operand:ALLI 2 "aarch64_logical_operand" "r<lconst_atomic>")))
-        (match_operand:SI 3 "const_int_operand")]		;; model
-       UNSPECV_ATOMIC_OP))
-    (clobber (reg:CC CC_REGNUM))
-@@ -209,7 +209,7 @@
-   [(set (match_operand:ALLI 0 "register_operand" "=&r")
-     (atomic_op:ALLI
-       (match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q")
--      (match_operand:ALLI 2 "<atomic_op_operand>" "rn")))
-+      (match_operand:ALLI 2 "<atomic_op_operand>" "r<lconst_atomic>")))
-    (set (match_dup 1)
-     (unspec_volatile:ALLI
-       [(match_dup 1) (match_dup 2)
-@@ -233,7 +233,7 @@
-     (not:ALLI
-       (and:ALLI
- 	(match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q")
--	(match_operand:ALLI 2 "aarch64_logical_operand" "rn"))))
-+	(match_operand:ALLI 2 "aarch64_logical_operand" "r<lconst_atomic>"))))
-    (set (match_dup 1)
-     (unspec_volatile:ALLI
-       [(match_dup 1) (match_dup 2)
---- a/src/gcc/config/aarch64/aarch64-tune.md
-+++ b/src/gcc/config/aarch64/aarch64-tune.md
-@@ -1,5 +1,5 @@
- ;; -*- buffer-read-only: t -*-
- ;; Generated automatically by gentune.sh from aarch64-cores.def
- (define_attr "tune"
--	"cortexa53,cortexa15,cortexa57cortexa53"
-+	"cortexa53,cortexa15,thunderx,cortexa57cortexa53"
- 	(const (symbol_ref "((enum attr_tune) aarch64_tune)")))
---- a/src/gcc/config/aarch64/aarch64-builtins.c
-+++ b/src/gcc/config/aarch64/aarch64-builtins.c
-@@ -47,52 +47,27 @@
- #include "gimple.h"
- #include "gimple-iterator.h"
- 
--enum aarch64_simd_builtin_type_mode
--{
--  T_V8QI,
--  T_V4HI,
--  T_V2SI,
--  T_V2SF,
--  T_DI,
--  T_DF,
--  T_V16QI,
--  T_V8HI,
--  T_V4SI,
--  T_V4SF,
--  T_V2DI,
--  T_V2DF,
--  T_TI,
--  T_EI,
--  T_OI,
--  T_XI,
--  T_SI,
--  T_SF,
--  T_HI,
--  T_QI,
--  T_MAX
--};
--
--#define v8qi_UP  T_V8QI
--#define v4hi_UP  T_V4HI
--#define v2si_UP  T_V2SI
--#define v2sf_UP  T_V2SF
--#define di_UP    T_DI
--#define df_UP    T_DF
--#define v16qi_UP T_V16QI
--#define v8hi_UP  T_V8HI
--#define v4si_UP  T_V4SI
--#define v4sf_UP  T_V4SF
--#define v2di_UP  T_V2DI
--#define v2df_UP  T_V2DF
--#define ti_UP	 T_TI
--#define ei_UP	 T_EI
--#define oi_UP	 T_OI
--#define xi_UP	 T_XI
--#define si_UP    T_SI
--#define sf_UP    T_SF
--#define hi_UP    T_HI
--#define qi_UP    T_QI
--
-+#define v8qi_UP  V8QImode
-+#define v4hi_UP  V4HImode
-+#define v2si_UP  V2SImode
-+#define v2sf_UP  V2SFmode
-+#define di_UP    DImode
-+#define df_UP    DFmode
-+#define v16qi_UP V16QImode
-+#define v8hi_UP  V8HImode
-+#define v4si_UP  V4SImode
-+#define v4sf_UP  V4SFmode
-+#define v2di_UP  V2DImode
-+#define v2df_UP  V2DFmode
-+#define ti_UP	 TImode
-+#define ei_UP	 EImode
-+#define oi_UP	 OImode
-+#define ci_UP	 CImode
-+#define xi_UP	 XImode
-+#define si_UP    SImode
-+#define sf_UP    SFmode
-+#define hi_UP    HImode
-+#define qi_UP    QImode
- #define UP(X) X##_UP
- 
- #define SIMD_MAX_BUILTIN_ARGS 5
-@@ -107,8 +82,6 @@
-   qualifier_const = 0x2, /* 1 << 1  */
-   /* T *foo.  */
-   qualifier_pointer = 0x4, /* 1 << 2  */
--  /* const T *foo.  */
--  qualifier_const_pointer = 0x6, /* qualifier_const | qualifier_pointer  */
-   /* Used when expanding arguments if an operand could
-      be an immediate.  */
-   qualifier_immediate = 0x8, /* 1 << 3  */
-@@ -123,7 +96,7 @@
-   qualifier_map_mode = 0x80, /* 1 << 7  */
-   /* qualifier_pointer | qualifier_map_mode  */
-   qualifier_pointer_map_mode = 0x84,
--  /* qualifier_const_pointer | qualifier_map_mode  */
-+  /* qualifier_const | qualifier_pointer | qualifier_map_mode  */
-   qualifier_const_pointer_map_mode = 0x86,
-   /* Polynomial types.  */
-   qualifier_poly = 0x100
-@@ -132,7 +105,7 @@
- typedef struct
- {
-   const char *name;
--  enum aarch64_simd_builtin_type_mode mode;
-+  enum machine_mode mode;
-   const enum insn_code code;
-   unsigned int fcode;
-   enum aarch64_type_qualifiers *qualifiers;
-@@ -147,16 +120,49 @@
-   = { qualifier_unsigned, qualifier_unsigned };
- #define TYPES_UNOPU (aarch64_types_unopu_qualifiers)
- #define TYPES_CREATE (aarch64_types_unop_qualifiers)
--#define TYPES_REINTERP (aarch64_types_unop_qualifiers)
-+#define TYPES_REINTERP_SS (aarch64_types_unop_qualifiers)
- static enum aarch64_type_qualifiers
-+aarch64_types_unop_su_qualifiers[SIMD_MAX_BUILTIN_ARGS]
-+  = { qualifier_none, qualifier_unsigned };
-+#define TYPES_REINTERP_SU (aarch64_types_unop_su_qualifiers)
-+static enum aarch64_type_qualifiers
-+aarch64_types_unop_sp_qualifiers[SIMD_MAX_BUILTIN_ARGS]
-+  = { qualifier_none, qualifier_poly };
-+#define TYPES_REINTERP_SP (aarch64_types_unop_sp_qualifiers)
-+static enum aarch64_type_qualifiers
-+aarch64_types_unop_us_qualifiers[SIMD_MAX_BUILTIN_ARGS]
-+  = { qualifier_unsigned, qualifier_none };
-+#define TYPES_REINTERP_US (aarch64_types_unop_us_qualifiers)
-+static enum aarch64_type_qualifiers
-+aarch64_types_unop_ps_qualifiers[SIMD_MAX_BUILTIN_ARGS]
-+  = { qualifier_poly, qualifier_none };
-+#define TYPES_REINTERP_PS (aarch64_types_unop_ps_qualifiers)
-+static enum aarch64_type_qualifiers
- aarch64_types_binop_qualifiers[SIMD_MAX_BUILTIN_ARGS]
-   = { qualifier_none, qualifier_none, qualifier_maybe_immediate };
- #define TYPES_BINOP (aarch64_types_binop_qualifiers)
- static enum aarch64_type_qualifiers
-+aarch64_types_cmtst_qualifiers[SIMD_MAX_BUILTIN_ARGS]
-+  = { qualifier_none, qualifier_none, qualifier_none,
-+      qualifier_internal, qualifier_internal };
-+#define TYPES_TST (aarch64_types_cmtst_qualifiers)
-+static enum aarch64_type_qualifiers
-+aarch64_types_binopv_qualifiers[SIMD_MAX_BUILTIN_ARGS]
-+  = { qualifier_void, qualifier_none, qualifier_none };
-+#define TYPES_BINOPV (aarch64_types_binopv_qualifiers)
-+static enum aarch64_type_qualifiers
- aarch64_types_binopu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
-   = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned };
- #define TYPES_BINOPU (aarch64_types_binopu_qualifiers)
- static enum aarch64_type_qualifiers
-+aarch64_types_binop_uus_qualifiers[SIMD_MAX_BUILTIN_ARGS]
-+  = { qualifier_unsigned, qualifier_unsigned, qualifier_none };
-+#define TYPES_BINOP_UUS (aarch64_types_binop_uus_qualifiers)
-+static enum aarch64_type_qualifiers
-+aarch64_types_binop_ssu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
-+  = { qualifier_none, qualifier_none, qualifier_unsigned };
-+#define TYPES_BINOP_SSU (aarch64_types_binop_ssu_qualifiers)
-+static enum aarch64_type_qualifiers
- aarch64_types_binopp_qualifiers[SIMD_MAX_BUILTIN_ARGS]
-   = { qualifier_poly, qualifier_poly, qualifier_poly };
- #define TYPES_BINOPP (aarch64_types_binopp_qualifiers)
-@@ -172,10 +178,10 @@
- #define TYPES_TERNOPU (aarch64_types_ternopu_qualifiers)
- 
- static enum aarch64_type_qualifiers
--aarch64_types_quadop_qualifiers[SIMD_MAX_BUILTIN_ARGS]
-+aarch64_types_ternop_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
-   = { qualifier_none, qualifier_none, qualifier_none,
--      qualifier_none, qualifier_none };
--#define TYPES_QUADOP (aarch64_types_quadop_qualifiers)
-+      qualifier_none, qualifier_immediate };
-+#define TYPES_TERNOP_LANE (aarch64_types_ternop_lane_qualifiers)
- 
- static enum aarch64_type_qualifiers
- aarch64_types_getlane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
-@@ -183,9 +189,14 @@
- #define TYPES_GETLANE (aarch64_types_getlane_qualifiers)
- #define TYPES_SHIFTIMM (aarch64_types_getlane_qualifiers)
- static enum aarch64_type_qualifiers
-+aarch64_types_shift_to_unsigned_qualifiers[SIMD_MAX_BUILTIN_ARGS]
-+  = { qualifier_unsigned, qualifier_none, qualifier_immediate };
-+#define TYPES_SHIFTIMM_USS (aarch64_types_shift_to_unsigned_qualifiers)
-+static enum aarch64_type_qualifiers
- aarch64_types_unsigned_shift_qualifiers[SIMD_MAX_BUILTIN_ARGS]
-   = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate };
- #define TYPES_USHIFTIMM (aarch64_types_unsigned_shift_qualifiers)
-+
- static enum aarch64_type_qualifiers
- aarch64_types_setlane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
-   = { qualifier_none, qualifier_none, qualifier_none, qualifier_immediate };
-@@ -194,6 +205,13 @@
- #define TYPES_SHIFTACC (aarch64_types_setlane_qualifiers)
- 
- static enum aarch64_type_qualifiers
-+aarch64_types_unsigned_shiftacc_qualifiers[SIMD_MAX_BUILTIN_ARGS]
-+  = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned,
-+      qualifier_immediate };
-+#define TYPES_USHIFTACC (aarch64_types_unsigned_shiftacc_qualifiers)
-+
-+
-+static enum aarch64_type_qualifiers
- aarch64_types_combine_qualifiers[SIMD_MAX_BUILTIN_ARGS]
-   = { qualifier_none, qualifier_none, qualifier_none };
- #define TYPES_COMBINE (aarch64_types_combine_qualifiers)
-@@ -230,6 +248,11 @@
-   = { qualifier_void, qualifier_pointer_map_mode, qualifier_none };
- #define TYPES_STORE1 (aarch64_types_store1_qualifiers)
- #define TYPES_STORESTRUCT (aarch64_types_store1_qualifiers)
-+static enum aarch64_type_qualifiers
-+aarch64_types_storestruct_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
-+  = { qualifier_void, qualifier_pointer_map_mode,
-+      qualifier_none, qualifier_none };
-+#define TYPES_STORESTRUCT_LANE (aarch64_types_storestruct_lane_qualifiers)
- 
- #define CF0(N, X) CODE_FOR_aarch64_##N##X
- #define CF1(N, X) CODE_FOR_##N##X##1
-@@ -239,7 +262,7 @@
- #define CF10(N, X) CODE_FOR_##N##X
- 
- #define VAR1(T, N, MAP, A) \
--  {#N, UP (A), CF##MAP (N, A), 0, TYPES_##T},
-+  {#N #A, UP (A), CF##MAP (N, A), 0, TYPES_##T},
- #define VAR2(T, N, MAP, A, B) \
-   VAR1 (T, N, MAP, A) \
-   VAR1 (T, N, MAP, B)
-@@ -274,96 +297,34 @@
-   VAR11 (T, N, MAP, A, B, C, D, E, F, G, H, I, J, K) \
-   VAR1 (T, N, MAP, L)
- 
--/* BUILTIN_<ITERATOR> macros should expand to cover the same range of
--   modes as is given for each define_mode_iterator in
--   config/aarch64/iterators.md.  */
-+#include "aarch64-builtin-iterators.h"
- 
--#define BUILTIN_DX(T, N, MAP) \
--  VAR2 (T, N, MAP, di, df)
--#define BUILTIN_GPF(T, N, MAP) \
--  VAR2 (T, N, MAP, sf, df)
--#define BUILTIN_SDQ_I(T, N, MAP) \
--  VAR4 (T, N, MAP, qi, hi, si, di)
--#define BUILTIN_SD_HSI(T, N, MAP) \
--  VAR2 (T, N, MAP, hi, si)
--#define BUILTIN_V2F(T, N, MAP) \
--  VAR2 (T, N, MAP, v2sf, v2df)
--#define BUILTIN_VALL(T, N, MAP) \
--  VAR10 (T, N, MAP, v8qi, v16qi, v4hi, v8hi, v2si, \
--	 v4si, v2di, v2sf, v4sf, v2df)
--#define BUILTIN_VALLDI(T, N, MAP) \
--  VAR11 (T, N, MAP, v8qi, v16qi, v4hi, v8hi, v2si, \
--	 v4si, v2di, v2sf, v4sf, v2df, di)
--#define BUILTIN_VALLDIF(T, N, MAP) \
--  VAR12 (T, N, MAP, v8qi, v16qi, v4hi, v8hi, v2si, \
--	 v4si, v2di, v2sf, v4sf, v2df, di, df)
--#define BUILTIN_VB(T, N, MAP) \
--  VAR2 (T, N, MAP, v8qi, v16qi)
--#define BUILTIN_VD(T, N, MAP) \
--  VAR4 (T, N, MAP, v8qi, v4hi, v2si, v2sf)
--#define BUILTIN_VDC(T, N, MAP) \
--  VAR6 (T, N, MAP, v8qi, v4hi, v2si, v2sf, di, df)
--#define BUILTIN_VDIC(T, N, MAP) \
--  VAR3 (T, N, MAP, v8qi, v4hi, v2si)
--#define BUILTIN_VDN(T, N, MAP) \
--  VAR3 (T, N, MAP, v4hi, v2si, di)
--#define BUILTIN_VDQ(T, N, MAP) \
--  VAR7 (T, N, MAP, v8qi, v16qi, v4hi, v8hi, v2si, v4si, v2di)
--#define BUILTIN_VDQF(T, N, MAP) \
--  VAR3 (T, N, MAP, v2sf, v4sf, v2df)
--#define BUILTIN_VDQH(T, N, MAP) \
--  VAR2 (T, N, MAP, v4hi, v8hi)
--#define BUILTIN_VDQHS(T, N, MAP) \
--  VAR4 (T, N, MAP, v4hi, v8hi, v2si, v4si)
--#define BUILTIN_VDQIF(T, N, MAP) \
--  VAR9 (T, N, MAP, v8qi, v16qi, v4hi, v8hi, v2si, v4si, v2sf, v4sf, v2df)
--#define BUILTIN_VDQM(T, N, MAP) \
--  VAR6 (T, N, MAP, v8qi, v16qi, v4hi, v8hi, v2si, v4si)
--#define BUILTIN_VDQV(T, N, MAP) \
--  VAR5 (T, N, MAP, v8qi, v16qi, v4hi, v8hi, v4si)
--#define BUILTIN_VDQQH(T, N, MAP) \
--  VAR4 (T, N, MAP, v8qi, v16qi, v4hi, v8hi)
--#define BUILTIN_VDQ_BHSI(T, N, MAP) \
--  VAR6 (T, N, MAP, v8qi, v16qi, v4hi, v8hi, v2si, v4si)
--#define BUILTIN_VDQ_I(T, N, MAP) \
--  VAR7 (T, N, MAP, v8qi, v16qi, v4hi, v8hi, v2si, v4si, v2di)
--#define BUILTIN_VDW(T, N, MAP) \
--  VAR3 (T, N, MAP, v8qi, v4hi, v2si)
--#define BUILTIN_VD_BHSI(T, N, MAP) \
--  VAR3 (T, N, MAP, v8qi, v4hi, v2si)
--#define BUILTIN_VD_HSI(T, N, MAP) \
--  VAR2 (T, N, MAP, v4hi, v2si)
--#define BUILTIN_VD_RE(T, N, MAP) \
--  VAR6 (T, N, MAP, v8qi, v4hi, v2si, v2sf, di, df)
--#define BUILTIN_VQ(T, N, MAP) \
--  VAR6 (T, N, MAP, v16qi, v8hi, v4si, v2di, v4sf, v2df)
--#define BUILTIN_VQN(T, N, MAP) \
--  VAR3 (T, N, MAP, v8hi, v4si, v2di)
--#define BUILTIN_VQW(T, N, MAP) \
--  VAR3 (T, N, MAP, v16qi, v8hi, v4si)
--#define BUILTIN_VQ_HSI(T, N, MAP) \
--  VAR2 (T, N, MAP, v8hi, v4si)
--#define BUILTIN_VQ_S(T, N, MAP) \
--  VAR6 (T, N, MAP, v8qi, v16qi, v4hi, v8hi, v2si, v4si)
--#define BUILTIN_VSDQ_HSI(T, N, MAP) \
--  VAR6 (T, N, MAP, v4hi, v8hi, v2si, v4si, hi, si)
--#define BUILTIN_VSDQ_I(T, N, MAP) \
--  VAR11 (T, N, MAP, v8qi, v16qi, v4hi, v8hi, v2si, v4si, v2di, qi, hi, si, di)
--#define BUILTIN_VSDQ_I_BHSI(T, N, MAP) \
--  VAR10 (T, N, MAP, v8qi, v16qi, v4hi, v8hi, v2si, v4si, v2di, qi, hi, si)
--#define BUILTIN_VSDQ_I_DI(T, N, MAP) \
--  VAR8 (T, N, MAP, v8qi, v16qi, v4hi, v8hi, v2si, v4si, v2di, di)
--#define BUILTIN_VSD_HSI(T, N, MAP) \
--  VAR4 (T, N, MAP, v4hi, v2si, hi, si)
--#define BUILTIN_VSQN_HSDI(T, N, MAP) \
--  VAR6 (T, N, MAP, v8hi, v4si, v2di, hi, si, di)
--#define BUILTIN_VSTRUCT(T, N, MAP) \
--  VAR3 (T, N, MAP, oi, ci, xi)
--
- static aarch64_simd_builtin_datum aarch64_simd_builtin_data[] = {
- #include "aarch64-simd-builtins.def"
- };
- 
-+/* There's only 8 CRC32 builtins.  Probably not worth their own .def file.  */
-+#define AARCH64_CRC32_BUILTINS \
-+  CRC32_BUILTIN (crc32b, QI) \
-+  CRC32_BUILTIN (crc32h, HI) \
-+  CRC32_BUILTIN (crc32w, SI) \
-+  CRC32_BUILTIN (crc32x, DI) \
-+  CRC32_BUILTIN (crc32cb, QI) \
-+  CRC32_BUILTIN (crc32ch, HI) \
-+  CRC32_BUILTIN (crc32cw, SI) \
-+  CRC32_BUILTIN (crc32cx, DI)
-+
-+typedef struct
-+{
-+  const char *name;
-+  enum machine_mode mode;
-+  const enum insn_code icode;
-+  unsigned int fcode;
-+} aarch64_crc_builtin_datum;
-+
-+#define CRC32_BUILTIN(N, M) \
-+  AARCH64_BUILTIN_##N,
-+
- #undef VAR1
- #define VAR1(T, N, MAP, A) \
-   AARCH64_SIMD_BUILTIN_##T##_##N##A,
-@@ -371,13 +332,32 @@
- enum aarch64_builtins
- {
-   AARCH64_BUILTIN_MIN,
-+
-+  AARCH64_BUILTIN_GET_FPCR,
-+  AARCH64_BUILTIN_SET_FPCR,
-+  AARCH64_BUILTIN_GET_FPSR,
-+  AARCH64_BUILTIN_SET_FPSR,
-+
-   AARCH64_SIMD_BUILTIN_BASE,
- #include "aarch64-simd-builtins.def"
-   AARCH64_SIMD_BUILTIN_MAX = AARCH64_SIMD_BUILTIN_BASE
- 			      + ARRAY_SIZE (aarch64_simd_builtin_data),
-+  AARCH64_CRC32_BUILTIN_BASE,
-+  AARCH64_CRC32_BUILTINS
-+  AARCH64_CRC32_BUILTIN_MAX,
-   AARCH64_BUILTIN_MAX
- };
- 
-+#undef CRC32_BUILTIN
-+#define CRC32_BUILTIN(N, M) \
-+  {"__builtin_aarch64_"#N, M##mode, CODE_FOR_aarch64_##N, AARCH64_BUILTIN_##N},
-+
-+static aarch64_crc_builtin_datum aarch64_crc_builtin_data[] = {
-+  AARCH64_CRC32_BUILTINS
-+};
-+
-+#undef CRC32_BUILTIN
-+
- static GTY(()) tree aarch64_builtin_decls[AARCH64_BUILTIN_MAX];
- 
- #define NUM_DREG_TYPES 6
-@@ -639,25 +619,10 @@
-       bool print_type_signature_p = false;
-       char type_signature[SIMD_MAX_BUILTIN_ARGS] = { 0 };
-       aarch64_simd_builtin_datum *d = &aarch64_simd_builtin_data[i];
--      const char *const modenames[] =
--	{
--	  "v8qi", "v4hi", "v2si", "v2sf", "di", "df",
--	  "v16qi", "v8hi", "v4si", "v4sf", "v2di", "v2df",
--	  "ti", "ei", "oi", "xi", "si", "sf", "hi", "qi"
--	};
--      const enum machine_mode modes[] =
--	{
--	  V8QImode, V4HImode, V2SImode, V2SFmode, DImode, DFmode,
--	  V16QImode, V8HImode, V4SImode, V4SFmode, V2DImode,
--	  V2DFmode, TImode, EImode, OImode, XImode, SImode,
--	  SFmode, HImode, QImode
--	};
-       char namebuf[60];
-       tree ftype = NULL;
-       tree fndecl = NULL;
- 
--      gcc_assert (ARRAY_SIZE (modenames) == T_MAX);
--
-       d->fcode = fcode;
- 
-       /* We must track two variables here.  op_num is
-@@ -705,7 +670,7 @@
- 	  /* Some builtins have different user-facing types
- 	     for certain arguments, encoded in d->mode.  */
- 	  if (qualifiers & qualifier_map_mode)
--	      op_mode = modes[d->mode];
-+	      op_mode = d->mode;
- 
- 	  /* For pointers, we want a pointer to the basic type
- 	     of the vector.  */
-@@ -737,11 +702,11 @@
-       gcc_assert (ftype != NULL);
- 
-       if (print_type_signature_p)
--	snprintf (namebuf, sizeof (namebuf), "__builtin_aarch64_%s%s_%s",
--		  d->name, modenames[d->mode], type_signature);
-+	snprintf (namebuf, sizeof (namebuf), "__builtin_aarch64_%s_%s",
-+		  d->name, type_signature);
-       else
--	snprintf (namebuf, sizeof (namebuf), "__builtin_aarch64_%s%s",
--		  d->name, modenames[d->mode]);
-+	snprintf (namebuf, sizeof (namebuf), "__builtin_aarch64_%s",
-+		  d->name);
- 
-       fndecl = add_builtin_function (namebuf, ftype, fcode, BUILT_IN_MD,
- 				     NULL, NULL_TREE);
-@@ -749,11 +714,49 @@
-     }
- }
- 
-+static void
-+aarch64_init_crc32_builtins ()
-+{
-+  tree usi_type = aarch64_build_unsigned_type (SImode);
-+  unsigned int i = 0;
-+
-+  for (i = 0; i < ARRAY_SIZE (aarch64_crc_builtin_data); ++i)
-+    {
-+      aarch64_crc_builtin_datum* d = &aarch64_crc_builtin_data[i];
-+      tree argtype = aarch64_build_unsigned_type (d->mode);
-+      tree ftype = build_function_type_list (usi_type, usi_type, argtype, NULL_TREE);
-+      tree fndecl = add_builtin_function (d->name, ftype, d->fcode,
-+                                          BUILT_IN_MD, NULL, NULL_TREE);
-+
-+      aarch64_builtin_decls[d->fcode] = fndecl;
-+    }
-+}
-+
- void
- aarch64_init_builtins (void)
- {
-+  tree ftype_set_fpr
-+    = build_function_type_list (void_type_node, unsigned_type_node, NULL);
-+  tree ftype_get_fpr
-+    = build_function_type_list (unsigned_type_node, NULL);
-+
-+  aarch64_builtin_decls[AARCH64_BUILTIN_GET_FPCR]
-+    = add_builtin_function ("__builtin_aarch64_get_fpcr", ftype_get_fpr,
-+			    AARCH64_BUILTIN_GET_FPCR, BUILT_IN_MD, NULL, NULL_TREE);
-+  aarch64_builtin_decls[AARCH64_BUILTIN_SET_FPCR]
-+    = add_builtin_function ("__builtin_aarch64_set_fpcr", ftype_set_fpr,
-+			    AARCH64_BUILTIN_SET_FPCR, BUILT_IN_MD, NULL, NULL_TREE);
-+  aarch64_builtin_decls[AARCH64_BUILTIN_GET_FPSR]
-+    = add_builtin_function ("__builtin_aarch64_get_fpsr", ftype_get_fpr,
-+			    AARCH64_BUILTIN_GET_FPSR, BUILT_IN_MD, NULL, NULL_TREE);
-+  aarch64_builtin_decls[AARCH64_BUILTIN_SET_FPSR]
-+    = add_builtin_function ("__builtin_aarch64_set_fpsr", ftype_set_fpr,
-+			    AARCH64_BUILTIN_SET_FPSR, BUILT_IN_MD, NULL, NULL_TREE);
-+
-   if (TARGET_SIMD)
-     aarch64_init_simd_builtins ();
-+  if (TARGET_CRC32)
-+    aarch64_init_crc32_builtins ();
- }
- 
- tree
-@@ -774,9 +777,8 @@
- 
- static rtx
- aarch64_simd_expand_args (rtx target, int icode, int have_retval,
--			  tree exp, ...)
-+			  tree exp, builtin_simd_arg *args)
- {
--  va_list ap;
-   rtx pat;
-   tree arg[SIMD_MAX_BUILTIN_ARGS];
-   rtx op[SIMD_MAX_BUILTIN_ARGS];
-@@ -790,11 +792,9 @@
- 	  || !(*insn_data[icode].operand[0].predicate) (target, tmode)))
-     target = gen_reg_rtx (tmode);
- 
--  va_start (ap, exp);
--
-   for (;;)
-     {
--      builtin_simd_arg thisarg = (builtin_simd_arg) va_arg (ap, int);
-+      builtin_simd_arg thisarg = args[argc];
- 
-       if (thisarg == SIMD_ARG_STOP)
- 	break;
-@@ -818,8 +818,11 @@
- 	    case SIMD_ARG_CONSTANT:
- 	      if (!(*insn_data[icode].operand[argc + have_retval].predicate)
- 		  (op[argc], mode[argc]))
-+	      {
- 		error_at (EXPR_LOCATION (exp), "incompatible type for argument %d, "
- 		       "expected %<const int%>", argc + 1);
-+		return const0_rtx;
-+	      }
- 	      break;
- 
- 	    case SIMD_ARG_STOP:
-@@ -830,8 +833,6 @@
- 	}
-     }
- 
--  va_end (ap);
--
-   if (have_retval)
-     switch (argc)
-       {
-@@ -886,7 +887,7 @@
-       }
- 
-   if (!pat)
--    return 0;
-+    return NULL_RTX;
- 
-   emit_insn (pat);
- 
-@@ -945,14 +946,45 @@
-   /* The interface to aarch64_simd_expand_args expects a 0 if
-      the function is void, and a 1 if it is not.  */
-   return aarch64_simd_expand_args
--	  (target, icode, !is_void, exp,
--	   args[1],
--	   args[2],
--	   args[3],
--	   args[4],
--	   SIMD_ARG_STOP);
-+	  (target, icode, !is_void, exp, &args[1]);
- }
- 
-+rtx
-+aarch64_crc32_expand_builtin (int fcode, tree exp, rtx target)
-+{
-+  rtx pat;
-+  aarch64_crc_builtin_datum *d
-+    = &aarch64_crc_builtin_data[fcode - (AARCH64_CRC32_BUILTIN_BASE + 1)];
-+  enum insn_code icode = d->icode;
-+  tree arg0 = CALL_EXPR_ARG (exp, 0);
-+  tree arg1 = CALL_EXPR_ARG (exp, 1);
-+  rtx op0 = expand_normal (arg0);
-+  rtx op1 = expand_normal (arg1);
-+  enum machine_mode tmode = insn_data[icode].operand[0].mode;
-+  enum machine_mode mode0 = insn_data[icode].operand[1].mode;
-+  enum machine_mode mode1 = insn_data[icode].operand[2].mode;
-+
-+  if (! target
-+      || GET_MODE (target) != tmode
-+      || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
-+    target = gen_reg_rtx (tmode);
-+
-+  gcc_assert ((GET_MODE (op0) == mode0 || GET_MODE (op0) == VOIDmode)
-+	      && (GET_MODE (op1) == mode1 || GET_MODE (op1) == VOIDmode));
-+
-+  if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
-+    op0 = copy_to_mode_reg (mode0, op0);
-+  if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
-+    op1 = copy_to_mode_reg (mode1, op1);
-+
-+  pat = GEN_FCN (icode) (target, op0, op1);
-+  if (!pat)
-+    return NULL_RTX;
-+
-+  emit_insn (pat);
-+  return target;
-+}
-+
- /* Expand an expression EXP that calls a built-in function,
-    with result going to TARGET if that's convenient.  */
- rtx
-@@ -964,11 +996,43 @@
- {
-   tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
-   int fcode = DECL_FUNCTION_CODE (fndecl);
-+  int icode;
-+  rtx pat, op0;
-+  tree arg0;
- 
--  if (fcode >= AARCH64_SIMD_BUILTIN_BASE)
-+  switch (fcode)
-+    {
-+    case AARCH64_BUILTIN_GET_FPCR:
-+    case AARCH64_BUILTIN_SET_FPCR:
-+    case AARCH64_BUILTIN_GET_FPSR:
-+    case AARCH64_BUILTIN_SET_FPSR:
-+      if ((fcode == AARCH64_BUILTIN_GET_FPCR)
-+	  || (fcode == AARCH64_BUILTIN_GET_FPSR))
-+	{
-+	  icode = (fcode == AARCH64_BUILTIN_GET_FPSR) ?
-+	    CODE_FOR_get_fpsr : CODE_FOR_get_fpcr;
-+	  target = gen_reg_rtx (SImode);
-+	  pat = GEN_FCN (icode) (target);
-+	}
-+      else
-+	{
-+	  target = NULL_RTX;
-+	  icode = (fcode == AARCH64_BUILTIN_SET_FPSR) ?
-+	    CODE_FOR_set_fpsr : CODE_FOR_set_fpcr;
-+	  arg0 = CALL_EXPR_ARG (exp, 0);
-+	  op0 = expand_normal (arg0);
-+	  pat = GEN_FCN (icode) (op0);
-+	}
-+      emit_insn (pat);
-+      return target;
-+    }
-+
-+  if (fcode >= AARCH64_SIMD_BUILTIN_BASE && fcode <= AARCH64_SIMD_BUILTIN_MAX)
-     return aarch64_simd_expand_builtin (fcode, exp, target);
-+  else if (fcode >= AARCH64_CRC32_BUILTIN_BASE && fcode <= AARCH64_CRC32_BUILTIN_MAX)
-+    return aarch64_crc32_expand_builtin (fcode, exp, target);
- 
--  return NULL_RTX;
-+  gcc_unreachable ();
- }
- 
- tree
-@@ -1086,7 +1150,29 @@
- 
- 	    return aarch64_builtin_decls[builtin];
- 	  }
--
-+	case BUILT_IN_BSWAP16:
-+#undef AARCH64_CHECK_BUILTIN_MODE
-+#define AARCH64_CHECK_BUILTIN_MODE(C, N) \
-+  (out_mode == N##Imode && out_n == C \
-+   && in_mode == N##Imode && in_n == C)
-+	  if (AARCH64_CHECK_BUILTIN_MODE (4, H))
-+	    return aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_UNOPU_bswapv4hi];
-+	  else if (AARCH64_CHECK_BUILTIN_MODE (8, H))
-+	    return aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_UNOPU_bswapv8hi];
-+	  else
-+	    return NULL_TREE;
-+	case BUILT_IN_BSWAP32:
-+	  if (AARCH64_CHECK_BUILTIN_MODE (2, S))
-+	    return aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_UNOPU_bswapv2si];
-+	  else if (AARCH64_CHECK_BUILTIN_MODE (4, S))
-+	    return aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_UNOPU_bswapv4si];
-+	  else
-+	    return NULL_TREE;
-+	case BUILT_IN_BSWAP64:
-+	  if (AARCH64_CHECK_BUILTIN_MODE (2, D))
-+	    return aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_UNOPU_bswapv2di];
-+	  else
-+	    return NULL_TREE;
- 	default:
- 	  return NULL_TREE;
-       }
-@@ -1111,22 +1197,25 @@
-       BUILTIN_VALLDI (UNOP, abs, 2)
- 	return fold_build1 (ABS_EXPR, type, args[0]);
- 	break;
--      BUILTIN_VALLDI (BINOP, cmge, 0)
--	return fold_build2 (GE_EXPR, type, args[0], args[1]);
--	break;
--      BUILTIN_VALLDI (BINOP, cmgt, 0)
--	return fold_build2 (GT_EXPR, type, args[0], args[1]);
--	break;
--      BUILTIN_VALLDI (BINOP, cmeq, 0)
--	return fold_build2 (EQ_EXPR, type, args[0], args[1]);
--	break;
--      BUILTIN_VSDQ_I_DI (BINOP, cmtst, 0)
--	{
--	  tree and_node = fold_build2 (BIT_AND_EXPR, type, args[0], args[1]);
--	  tree vec_zero_node = build_zero_cst (type);
--	  return fold_build2 (NE_EXPR, type, and_node, vec_zero_node);
--	  break;
--	}
-+      VAR1 (REINTERP_SS, reinterpretdi, 0, df)
-+      VAR1 (REINTERP_SS, reinterpretv8qi, 0, df)
-+      VAR1 (REINTERP_SS, reinterpretv4hi, 0, df)
-+      VAR1 (REINTERP_SS, reinterpretv2si, 0, df)
-+      VAR1 (REINTERP_SS, reinterpretv2sf, 0, df)
-+      BUILTIN_VD (REINTERP_SS, reinterpretdf, 0)
-+      BUILTIN_VD (REINTERP_SU, reinterpretdf, 0)
-+      VAR1 (REINTERP_US, reinterpretdi, 0, df)
-+      VAR1 (REINTERP_US, reinterpretv8qi, 0, df)
-+      VAR1 (REINTERP_US, reinterpretv4hi, 0, df)
-+      VAR1 (REINTERP_US, reinterpretv2si, 0, df)
-+      VAR1 (REINTERP_US, reinterpretv2sf, 0, df)
-+      BUILTIN_VD (REINTERP_SP, reinterpretdf, 0)
-+      VAR1 (REINTERP_PS, reinterpretdi, 0, df)
-+      VAR1 (REINTERP_PS, reinterpretv8qi, 0, df)
-+      VAR1 (REINTERP_PS, reinterpretv4hi, 0, df)
-+      VAR1 (REINTERP_PS, reinterpretv2si, 0, df)
-+      VAR1 (REINTERP_PS, reinterpretv2sf, 0, df)
-+	return fold_build1 (VIEW_CONVERT_EXPR, type, args[0]);
-       VAR1 (UNOP, floatv2si, 2, v2sf)
-       VAR1 (UNOP, floatv4si, 2, v4sf)
-       VAR1 (UNOP, floatv2di, 2, v2df)
-@@ -1146,6 +1235,20 @@
-   tree call = gimple_call_fn (stmt);
-   tree fndecl;
-   gimple new_stmt = NULL;
-+
-+  /* The operations folded below are reduction operations.  These are
-+     defined to leave their result in the 0'th element (from the perspective
-+     of GCC).  The architectural instruction we are folding will leave the
-+     result in the 0'th element (from the perspective of the architecture).
-+     For big-endian systems, these perspectives are not aligned.
-+
-+     It is therefore wrong to perform this fold on big-endian.  There
-+     are some tricks we could play with shuffling, but the mid-end is
-+     inconsistent in the way it treats reduction operations, so we will
-+     end up in difficulty.  Until we fix the ambiguity - just bail out.  */
-+  if (BYTES_BIG_ENDIAN)
-+    return false;
-+
-   if (call)
-     {
-       fndecl = gimple_call_fndecl (stmt);
-@@ -1196,43 +1299,108 @@
-   return changed;
- }
- 
-+void
-+aarch64_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
-+{
-+  const unsigned AARCH64_FE_INVALID = 1;
-+  const unsigned AARCH64_FE_DIVBYZERO = 2;
-+  const unsigned AARCH64_FE_OVERFLOW = 4;
-+  const unsigned AARCH64_FE_UNDERFLOW = 8;
-+  const unsigned AARCH64_FE_INEXACT = 16;
-+  const unsigned HOST_WIDE_INT AARCH64_FE_ALL_EXCEPT = (AARCH64_FE_INVALID
-+							| AARCH64_FE_DIVBYZERO
-+							| AARCH64_FE_OVERFLOW
-+							| AARCH64_FE_UNDERFLOW
-+							| AARCH64_FE_INEXACT);
-+  const unsigned HOST_WIDE_INT AARCH64_FE_EXCEPT_SHIFT = 8;
-+  tree fenv_cr, fenv_sr, get_fpcr, set_fpcr, mask_cr, mask_sr;
-+  tree ld_fenv_cr, ld_fenv_sr, masked_fenv_cr, masked_fenv_sr, hold_fnclex_cr;
-+  tree hold_fnclex_sr, new_fenv_var, reload_fenv, restore_fnenv, get_fpsr, set_fpsr;
-+  tree update_call, atomic_feraiseexcept, hold_fnclex, masked_fenv, ld_fenv;
-+
-+  /* Generate the equivalence of :
-+       unsigned int fenv_cr;
-+       fenv_cr = __builtin_aarch64_get_fpcr ();
-+
-+       unsigned int fenv_sr;
-+       fenv_sr = __builtin_aarch64_get_fpsr ();
-+
-+       Now set all exceptions to non-stop
-+       unsigned int mask_cr
-+		= ~(AARCH64_FE_ALL_EXCEPT << AARCH64_FE_EXCEPT_SHIFT);
-+       unsigned int masked_cr;
-+       masked_cr = fenv_cr & mask_cr;
-+
-+       And clear all exception flags
-+       unsigned int maske_sr = ~AARCH64_FE_ALL_EXCEPT;
-+       unsigned int masked_cr;
-+       masked_sr = fenv_sr & mask_sr;
-+
-+       __builtin_aarch64_set_cr (masked_cr);
-+       __builtin_aarch64_set_sr (masked_sr);  */
-+
-+  fenv_cr = create_tmp_var (unsigned_type_node, NULL);
-+  fenv_sr = create_tmp_var (unsigned_type_node, NULL);
-+
-+  get_fpcr = aarch64_builtin_decls[AARCH64_BUILTIN_GET_FPCR];
-+  set_fpcr = aarch64_builtin_decls[AARCH64_BUILTIN_SET_FPCR];
-+  get_fpsr = aarch64_builtin_decls[AARCH64_BUILTIN_GET_FPSR];
-+  set_fpsr = aarch64_builtin_decls[AARCH64_BUILTIN_SET_FPSR];
-+
-+  mask_cr = build_int_cst (unsigned_type_node,
-+			   ~(AARCH64_FE_ALL_EXCEPT << AARCH64_FE_EXCEPT_SHIFT));
-+  mask_sr = build_int_cst (unsigned_type_node,
-+			   ~(AARCH64_FE_ALL_EXCEPT));
-+
-+  ld_fenv_cr = build2 (MODIFY_EXPR, unsigned_type_node,
-+		    fenv_cr, build_call_expr (get_fpcr, 0));
-+  ld_fenv_sr = build2 (MODIFY_EXPR, unsigned_type_node,
-+		    fenv_sr, build_call_expr (get_fpsr, 0));
-+
-+  masked_fenv_cr = build2 (BIT_AND_EXPR, unsigned_type_node, fenv_cr, mask_cr);
-+  masked_fenv_sr = build2 (BIT_AND_EXPR, unsigned_type_node, fenv_sr, mask_sr);
-+
-+  hold_fnclex_cr = build_call_expr (set_fpcr, 1, masked_fenv_cr);
-+  hold_fnclex_sr = build_call_expr (set_fpsr, 1, masked_fenv_sr);
-+
-+  hold_fnclex = build2 (COMPOUND_EXPR, void_type_node, hold_fnclex_cr,
-+			hold_fnclex_sr);
-+  masked_fenv = build2 (COMPOUND_EXPR, void_type_node, masked_fenv_cr,
-+			masked_fenv_sr);
-+  ld_fenv = build2 (COMPOUND_EXPR, void_type_node, ld_fenv_cr, ld_fenv_sr);
-+
-+  *hold = build2 (COMPOUND_EXPR, void_type_node,
-+		  build2 (COMPOUND_EXPR, void_type_node, masked_fenv, ld_fenv),
-+		  hold_fnclex);
-+
-+  /* Store the value of masked_fenv to clear the exceptions:
-+     __builtin_aarch64_set_fpsr (masked_fenv_sr);  */
-+
-+  *clear = build_call_expr (set_fpsr, 1, masked_fenv_sr);
-+
-+  /* Generate the equivalent of :
-+       unsigned int new_fenv_var;
-+       new_fenv_var = __builtin_aarch64_get_fpsr ();
-+
-+       __builtin_aarch64_set_fpsr (fenv_sr);
-+
-+       __atomic_feraiseexcept (new_fenv_var);  */
-+
-+  new_fenv_var = create_tmp_var (unsigned_type_node, NULL);
-+  reload_fenv = build2 (MODIFY_EXPR, unsigned_type_node,
-+			new_fenv_var, build_call_expr (get_fpsr, 0));
-+  restore_fnenv = build_call_expr (set_fpsr, 1, fenv_sr);
-+  atomic_feraiseexcept = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT);
-+  update_call = build_call_expr (atomic_feraiseexcept, 1,
-+				 fold_convert (integer_type_node, new_fenv_var));
-+  *update = build2 (COMPOUND_EXPR, void_type_node,
-+		    build2 (COMPOUND_EXPR, void_type_node,
-+			    reload_fenv, restore_fnenv), update_call);
-+}
-+
-+
- #undef AARCH64_CHECK_BUILTIN_MODE
- #undef AARCH64_FIND_FRINT_VARIANT
--#undef BUILTIN_DX
--#undef BUILTIN_SDQ_I
--#undef BUILTIN_SD_HSI
--#undef BUILTIN_V2F
--#undef BUILTIN_VALL
--#undef BUILTIN_VB
--#undef BUILTIN_VD
--#undef BUILTIN_VDC
--#undef BUILTIN_VDIC
--#undef BUILTIN_VDN
--#undef BUILTIN_VDQ
--#undef BUILTIN_VDQF
--#undef BUILTIN_VDQH
--#undef BUILTIN_VDQHS
--#undef BUILTIN_VDQIF
--#undef BUILTIN_VDQM
--#undef BUILTIN_VDQV
--#undef BUILTIN_VDQ_BHSI
--#undef BUILTIN_VDQ_I
--#undef BUILTIN_VDW
--#undef BUILTIN_VD_BHSI
--#undef BUILTIN_VD_HSI
--#undef BUILTIN_VD_RE
--#undef BUILTIN_VQ
--#undef BUILTIN_VQN
--#undef BUILTIN_VQW
--#undef BUILTIN_VQ_HSI
--#undef BUILTIN_VQ_S
--#undef BUILTIN_VSDQ_HSI
--#undef BUILTIN_VSDQ_I
--#undef BUILTIN_VSDQ_I_BHSI
--#undef BUILTIN_VSDQ_I_DI
--#undef BUILTIN_VSD_HSI
--#undef BUILTIN_VSQN_HSDI
--#undef BUILTIN_VSTRUCT
- #undef CF0
- #undef CF1
- #undef CF2
-@@ -1251,3 +1419,4 @@
- #undef VAR10
- #undef VAR11
- 
-+#include "gt-aarch64-builtins.h"
---- a/src/gcc/config/aarch64/thunderx.md
-+++ b/src/gcc/config/aarch64/thunderx.md
-@@ -0,0 +1,260 @@
-+;; Cavium ThunderX pipeline description
-+;; Copyright (C) 2014 Free Software Foundation, Inc.
-+;;
-+;; Written by Andrew Pinski  <apinski@cavium.com>
-+
-+;; This file is part of GCC.
-+
-+;; GCC is free software; you can redistribute it and/or modify
-+;; it under the terms of the GNU General Public License as published by
-+;; the Free Software Foundation; either version 3, or (at your option)
-+;; any later version.
-+
-+;; GCC is distributed in the hope that it will be useful,
-+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+;; GNU General Public License for more details.
-+
-+;; You should have received a copy of the GNU General Public License
-+;; along with GCC; see the file COPYING3.  If not see
-+;; <http://www.gnu.org/licenses/>.
-+;;   Copyright (C) 2004, 2005, 2006 Cavium Networks.
-+
-+
-+;; Thunder is a dual-issue processor that can issue all instructions on
-+;; pipe0 and a subset on pipe1.
-+
-+
-+(define_automaton "thunderx_main, thunderx_mult, thunderx_divide, thunderx_simd")
-+
-+(define_cpu_unit "thunderx_pipe0" "thunderx_main")
-+(define_cpu_unit "thunderx_pipe1" "thunderx_main")
-+(define_cpu_unit "thunderx_mult" "thunderx_mult")
-+(define_cpu_unit "thunderx_divide" "thunderx_divide")
-+(define_cpu_unit "thunderx_simd" "thunderx_simd")
-+
-+(define_insn_reservation "thunderx_add" 1
-+  (and (eq_attr "tune" "thunderx")
-+       (eq_attr "type" "adc_imm,adc_reg,adr,alu_imm,alu_reg,alus_imm,alus_reg,extend,logic_imm,logic_reg,logics_imm,logics_reg,mov_imm,mov_reg"))
-+  "thunderx_pipe0 | thunderx_pipe1")
-+
-+(define_insn_reservation "thunderx_shift" 1
-+  (and (eq_attr "tune" "thunderx")
-+       (eq_attr "type" "bfm,extend,shift_imm,shift_reg"))
-+  "thunderx_pipe0 | thunderx_pipe1")
-+
-+
-+;; Arthimentic instructions with an extra shift or extend is two cycles.
-+;; FIXME: This needs more attributes on aarch64 than what is currently there;
-+;;    this is conserative for now.
-+;; Except this is not correct as this is only for !(LSL && shift by 0/1/2/3)
-+;; Except this is not correct as this is only for !(zero extend)
-+
-+(define_insn_reservation "thunderx_arith_shift" 2
-+  (and (eq_attr "tune" "thunderx")
-+       (eq_attr "type" "alu_ext,alu_shift_imm,alu_shift_reg,alus_ext,logic_shift_imm,logic_shift_reg,logics_shift_imm,logics_shift_reg,alus_shift_imm"))
-+  "thunderx_pipe0 | thunderx_pipe1")
-+
-+(define_insn_reservation "thunderx_csel" 2
-+  (and (eq_attr "tune" "thunderx")
-+       (eq_attr "type" "csel"))
-+  "thunderx_pipe0 | thunderx_pipe1")
-+
-+;; Multiply and mulitply accumulate and count leading zeros can only happen on pipe 1
-+
-+(define_insn_reservation "thunderx_mul" 4
-+  (and (eq_attr "tune" "thunderx")
-+       (eq_attr "type" "mul,muls,mla,mlas,clz,smull,umull,smlal,umlal"))
-+  "thunderx_pipe1 + thunderx_mult")
-+
-+;; Multiply high instructions take an extra cycle and cause the muliply unit to
-+;; be busy for an extra cycle.
-+
-+;(define_insn_reservation "thunderx_mul_high" 5
-+;  (and (eq_attr "tune" "thunderx")
-+;       (eq_attr "type" "smull,umull"))
-+;  "thunderx_pipe1 + thunderx_mult")
-+
-+(define_insn_reservation "thunderx_div32" 22
-+  (and (eq_attr "tune" "thunderx")
-+       (eq_attr "type" "udiv,sdiv"))
-+  "thunderx_pipe1 + thunderx_divide, thunderx_divide * 21")
-+
-+;(define_insn_reservation "thunderx_div64" 38
-+;  (and (eq_attr "tune" "thunderx")
-+;       (eq_attr "type" "udiv,sdiv")
-+;       (eq_attr "mode" "DI"))
-+;  "thunderx_pipe1 + thunderx_divide, thunderx_divide * 34")
-+
-+;; Stores take one cycle in pipe 0
-+(define_insn_reservation "thunderx_store" 1
-+  (and (eq_attr "tune" "thunderx")
-+       (eq_attr "type" "store1"))
-+  "thunderx_pipe0")
-+
-+;; Store pair are single issued
-+(define_insn_reservation "thunderx_storepair" 1
-+  (and (eq_attr "tune" "thunderx")
-+       (eq_attr "type" "store2"))
-+  "thunderx_pipe0 + thunderx_pipe1")
-+
-+
-+;; loads (and load pairs) from L1 take 3 cycles in pipe 0
-+(define_insn_reservation "thunderx_load" 3
-+  (and (eq_attr "tune" "thunderx")
-+       (eq_attr "type" "load1, load2"))
-+  "thunderx_pipe0")
-+
-+(define_insn_reservation "thunderx_brj" 1
-+  (and (eq_attr "tune" "thunderx")
-+       (eq_attr "type" "branch,trap,call"))
-+  "thunderx_pipe1")
-+
-+;; FPU
-+
-+(define_insn_reservation "thunderx_fadd" 4
-+  (and (eq_attr "tune" "thunderx")
-+       (eq_attr "type" "faddd,fadds"))
-+  "thunderx_pipe1")
-+
-+(define_insn_reservation "thunderx_fconst" 1
-+  (and (eq_attr "tune" "thunderx")
-+       (eq_attr "type" "fconsts,fconstd"))
-+  "thunderx_pipe1")
-+
-+;; Moves between fp are 2 cycles including min/max/select/abs/neg
-+(define_insn_reservation "thunderx_fmov" 2
-+  (and (eq_attr "tune" "thunderx")
-+       (eq_attr "type" "fmov,f_minmaxs,f_minmaxd,fcsel,ffarithd,ffariths"))
-+  "thunderx_pipe1")
-+
-+(define_insn_reservation "thunderx_fmovgpr" 2
-+  (and (eq_attr "tune" "thunderx")
-+       (eq_attr "type" "f_mrc, f_mcr"))
-+  "thunderx_pipe1")
-+
-+(define_insn_reservation "thunderx_fmul" 6
-+  (and (eq_attr "tune" "thunderx")
-+       (eq_attr "type" "fmacs,fmacd,fmuls,fmuld"))
-+  "thunderx_pipe1")
-+
-+(define_insn_reservation "thunderx_fdivs" 12
-+  (and (eq_attr "tune" "thunderx")
-+       (eq_attr "type" "fdivs"))
-+  "thunderx_pipe1 + thunderx_divide, thunderx_divide*8")
-+
-+(define_insn_reservation "thunderx_fdivd" 22
-+  (and (eq_attr "tune" "thunderx")
-+       (eq_attr "type" "fdivd"))
-+  "thunderx_pipe1 + thunderx_divide, thunderx_divide*18")
-+
-+(define_insn_reservation "thunderx_fsqrts" 17
-+  (and (eq_attr "tune" "thunderx")
-+       (eq_attr "type" "fsqrts"))
-+  "thunderx_pipe1 + thunderx_divide, thunderx_divide*13")
-+
-+(define_insn_reservation "thunderx_fsqrtd" 28
-+  (and (eq_attr "tune" "thunderx")
-+       (eq_attr "type" "fsqrtd"))
-+  "thunderx_pipe1 + thunderx_divide, thunderx_divide*31")
-+
-+;; The rounding conversion inside fp is 4 cycles
-+(define_insn_reservation "thunderx_frint" 4
-+  (and (eq_attr "tune" "thunderx")
-+       (eq_attr "type" "f_rints,f_rintd"))
-+  "thunderx_pipe1")
-+
-+;; Float to integer with a move from int to/from float is 6 cycles
-+(define_insn_reservation "thunderx_f_cvt" 6
-+  (and (eq_attr "tune" "thunderx")
-+       (eq_attr "type" "f_cvt,f_cvtf2i,f_cvti2f"))
-+  "thunderx_pipe1")
-+
-+;; FP/SIMD load/stores happen in pipe 0
-+;; 64bit Loads register/pairs are 4 cycles from L1
-+(define_insn_reservation "thunderx_64simd_fp_load" 4
-+  (and (eq_attr "tune" "thunderx")
-+       (eq_attr "type" "f_loadd,f_loads,neon_load1_1reg,\
-+			neon_load1_1reg_q,neon_load1_2reg"))
-+  "thunderx_pipe0")
-+
-+;; 128bit load pair is singled issue and 4 cycles from L1
-+(define_insn_reservation "thunderx_128simd_pair_load" 4
-+  (and (eq_attr "tune" "thunderx")
-+       (eq_attr "type" "neon_load1_2reg_q"))
-+  "thunderx_pipe0+thunderx_pipe1")
-+
-+;; FP/SIMD Stores takes one cycle in pipe 0
-+(define_insn_reservation "thunderx_simd_fp_store" 1
-+  (and (eq_attr "tune" "thunderx")
-+       (eq_attr "type" "f_stored,f_stores,neon_store1_1reg,neon_store1_1reg_q"))
-+  "thunderx_pipe0")
-+
-+;; 64bit neon store pairs are single issue for one cycle
-+(define_insn_reservation "thunderx_64neon_storepair" 1
-+  (and (eq_attr "tune" "thunderx")
-+       (eq_attr "type" "neon_store1_2reg"))
-+  "thunderx_pipe0 + thunderx_pipe1")
-+
-+;; 128bit neon store pair are single issued for two cycles
-+(define_insn_reservation "thunderx_128neon_storepair" 2
-+  (and (eq_attr "tune" "thunderx")
-+       (eq_attr "type" "neon_store1_2reg_q"))
-+  "(thunderx_pipe0 + thunderx_pipe1)*2")
-+
-+
-+;; SIMD/NEON (q forms take an extra cycle)
-+
-+;; Thunder simd move instruction types - 2/3 cycles
-+(define_insn_reservation "thunderx_neon_move" 2
-+  (and (eq_attr "tune" "thunderx")
-+       (eq_attr "type" "neon_logic, neon_bsl, neon_fp_compare_s, \
-+			neon_fp_compare_d, neon_move"))
-+  "thunderx_pipe1 + thunderx_simd")
-+
-+(define_insn_reservation "thunderx_neon_move_q" 3
-+  (and (eq_attr "tune" "thunderx")
-+       (eq_attr "type" "neon_logic_q, neon_bsl_q, neon_fp_compare_s_q, \
-+			neon_fp_compare_d_q, neon_move_q"))
-+  "thunderx_pipe1 + thunderx_simd, thunderx_simd")
-+
-+
-+;; Thunder simd simple/add instruction types - 4/5 cycles
-+
-+(define_insn_reservation "thunderx_neon_add" 4
-+  (and (eq_attr "tune" "thunderx")
-+       (eq_attr "type" "neon_reduc_add, neon_reduc_minmax, neon_fp_reduc_add_s, \
-+			neon_fp_reduc_add_d, neon_fp_to_int_s, neon_fp_to_int_d, \
-+			neon_add_halve, neon_sub_halve, neon_qadd, neon_compare, \
-+			neon_compare_zero, neon_minmax, neon_abd, neon_add, neon_sub, \
-+			neon_fp_minmax_s, neon_fp_minmax_d, neon_reduc_add, neon_cls, \
-+			neon_qabs, neon_qneg, neon_fp_addsub_s, neon_fp_addsub_d"))
-+  "thunderx_pipe1 + thunderx_simd")
-+
-+;; BIG NOTE: neon_add_long/neon_sub_long don't have a q form which is incorrect
-+
-+(define_insn_reservation "thunderx_neon_add_q" 5
-+  (and (eq_attr "tune" "thunderx")
-+       (eq_attr "type" "neon_reduc_add_q, neon_reduc_minmax_q, neon_fp_reduc_add_s_q, \
-+			neon_fp_reduc_add_d_q, neon_fp_to_int_s_q, neon_fp_to_int_d_q, \
-+			neon_add_halve_q, neon_sub_halve_q, neon_qadd_q, neon_compare_q, \
-+			neon_compare_zero_q, neon_minmax_q, neon_abd_q, neon_add_q, neon_sub_q, \
-+			neon_fp_minmax_s_q, neon_fp_minmax_d_q, neon_reduc_add_q, neon_cls_q, \
-+			neon_qabs_q, neon_qneg_q, neon_fp_addsub_s_q, neon_fp_addsub_d_q, \
-+			neon_add_long, neon_sub_long"))
-+  "thunderx_pipe1 + thunderx_simd, thunderx_simd")
-+
-+
-+;; Thunder 128bit SIMD reads the upper halve in cycle 2 and writes in the last cycle
-+(define_bypass 2 "thunderx_neon_move_q" "thunderx_neon_move_q, thunderx_neon_add_q")
-+(define_bypass 4 "thunderx_neon_add_q" "thunderx_neon_move_q, thunderx_neon_add_q")
-+
-+;; Assume both pipes are needed for unknown and multiple-instruction
-+;; patterns.
-+
-+(define_insn_reservation "thunderx_unknown" 1
-+  (and (eq_attr "tune" "thunderx")
-+       (eq_attr "type" "untyped,multiple"))
-+  "thunderx_pipe0 + thunderx_pipe1")
-+
-+
---- a/src/gcc/config/aarch64/aarch64-protos.h
-+++ b/src/gcc/config/aarch64/aarch64-protos.h
-@@ -108,9 +108,22 @@
-    cost models and vectors for address cost calculations, register
-    move costs and memory move costs.  */
- 
-+/* Scaled addressing modes can vary cost depending on the mode of the
-+   value to be loaded/stored.  QImode values cannot use scaled
-+   addressing modes.  */
-+
-+struct scale_addr_mode_cost
-+{
-+  const int hi;
-+  const int si;
-+  const int di;
-+  const int ti;
-+};
-+
- /* Additional cost for addresses.  */
- struct cpu_addrcost_table
- {
-+  const struct scale_addr_mode_cost addr_scale_costs;
-   const int pre_modify;
-   const int post_modify;
-   const int register_offset;
-@@ -160,6 +173,7 @@
- };
- 
- HOST_WIDE_INT aarch64_initial_elimination_offset (unsigned, unsigned);
-+int aarch64_get_condition_code (rtx);
- bool aarch64_bitmask_imm (HOST_WIDE_INT val, enum machine_mode);
- bool aarch64_cannot_change_mode_class (enum machine_mode,
- 				       enum machine_mode,
-@@ -166,7 +180,9 @@
- 				       enum reg_class);
- enum aarch64_symbol_type
- aarch64_classify_symbolic_expression (rtx, enum aarch64_symbol_context);
-+bool aarch64_const_vec_all_same_int_p (rtx, HOST_WIDE_INT);
- bool aarch64_constant_address_p (rtx);
-+bool aarch64_expand_movmem (rtx *);
- bool aarch64_float_const_zero_rtx_p (rtx);
- bool aarch64_function_arg_regno_p (unsigned);
- bool aarch64_gen_movmemqi (rtx *);
-@@ -175,9 +191,12 @@
- bool aarch64_is_long_call_p (rtx);
- bool aarch64_label_mentioned_p (rtx);
- bool aarch64_legitimate_pic_operand_p (rtx);
-+bool aarch64_modes_tieable_p (enum machine_mode mode1,
-+			      enum machine_mode mode2);
- bool aarch64_move_imm (HOST_WIDE_INT, enum machine_mode);
- bool aarch64_mov_operand_p (rtx, enum aarch64_symbol_context,
- 			    enum machine_mode);
-+bool aarch64_offset_7bit_signed_scaled_p (enum machine_mode, HOST_WIDE_INT);
- char *aarch64_output_scalar_simd_mov_immediate (rtx, enum machine_mode);
- char *aarch64_output_simd_mov_immediate (rtx, enum machine_mode, unsigned);
- bool aarch64_pad_arg_upward (enum machine_mode, const_tree);
-@@ -184,6 +203,8 @@
- bool aarch64_pad_reg_upward (enum machine_mode, const_tree, bool);
- bool aarch64_regno_ok_for_base_p (int, bool);
- bool aarch64_regno_ok_for_index_p (int, bool);
-+bool aarch64_simd_check_vect_par_cnst_half (rtx op, enum machine_mode mode,
-+					    bool high);
- bool aarch64_simd_imm_scalar_p (rtx x, enum machine_mode mode);
- bool aarch64_simd_imm_zero_p (rtx, enum machine_mode);
- bool aarch64_simd_scalar_immediate_valid_for_move (rtx, enum machine_mode);
-@@ -200,6 +221,8 @@
- enum aarch64_symbol_type aarch64_classify_tls_symbol (rtx);
- enum reg_class aarch64_regno_regclass (unsigned);
- int aarch64_asm_preferred_eh_data_format (int, int);
-+enum machine_mode aarch64_hard_regno_caller_save_mode (unsigned, unsigned,
-+						       enum machine_mode);
- int aarch64_hard_regno_mode_ok (unsigned, enum machine_mode);
- int aarch64_hard_regno_nregs (unsigned, enum machine_mode);
- int aarch64_simd_attr_length_move (rtx);
-@@ -291,4 +314,5 @@
- extern void aarch64_final_prescan_insn (rtx);
- extern bool
- aarch64_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel);
-+void aarch64_atomic_assign_expand_fenv (tree *, tree *, tree *);
- #endif /* GCC_AARCH64_PROTOS_H */
---- a/src/gcc/config/aarch64/aarch64-simd-builtins.def
-+++ b/src/gcc/config/aarch64/aarch64-simd-builtins.def
-@@ -47,36 +47,44 @@
-   VAR1 (UNOP, addp, 0, di)
-   BUILTIN_VDQ_BHSI (UNOP, clz, 2)
- 
--  BUILTIN_VALL (GETLANE, get_lane, 0)
--  VAR1 (GETLANE, get_lane, 0, di)
-   BUILTIN_VALL (GETLANE, be_checked_get_lane, 0)
- 
--  BUILTIN_VD_RE (REINTERP, reinterpretdi, 0)
--  BUILTIN_VDC (REINTERP, reinterpretv8qi, 0)
--  BUILTIN_VDC (REINTERP, reinterpretv4hi, 0)
--  BUILTIN_VDC (REINTERP, reinterpretv2si, 0)
--  BUILTIN_VDC (REINTERP, reinterpretv2sf, 0)
--  BUILTIN_VQ (REINTERP, reinterpretv16qi, 0)
--  BUILTIN_VQ (REINTERP, reinterpretv8hi, 0)
--  BUILTIN_VQ (REINTERP, reinterpretv4si, 0)
--  BUILTIN_VQ (REINTERP, reinterpretv4sf, 0)
--  BUILTIN_VQ (REINTERP, reinterpretv2di, 0)
--  BUILTIN_VQ (REINTERP, reinterpretv2df, 0)
-+  VAR1 (REINTERP_SS, reinterpretdi, 0, df)
-+  VAR1 (REINTERP_SS, reinterpretv8qi, 0, df)
-+  VAR1 (REINTERP_SS, reinterpretv4hi, 0, df)
-+  VAR1 (REINTERP_SS, reinterpretv2si, 0, df)
-+  VAR1 (REINTERP_SS, reinterpretv2sf, 0, df)
-+  BUILTIN_VD (REINTERP_SS, reinterpretdf, 0)
- 
--  BUILTIN_VDQ_I (BINOP, dup_lane, 0)
-+  BUILTIN_VD (REINTERP_SU, reinterpretdf, 0)
-+
-+  VAR1 (REINTERP_US, reinterpretdi, 0, df)
-+  VAR1 (REINTERP_US, reinterpretv8qi, 0, df)
-+  VAR1 (REINTERP_US, reinterpretv4hi, 0, df)
-+  VAR1 (REINTERP_US, reinterpretv2si, 0, df)
-+  VAR1 (REINTERP_US, reinterpretv2sf, 0, df)
-+
-+  BUILTIN_VD (REINTERP_SP, reinterpretdf, 0)
-+
-+  VAR1 (REINTERP_PS, reinterpretdi, 0, df)
-+  VAR1 (REINTERP_PS, reinterpretv8qi, 0, df)
-+  VAR1 (REINTERP_PS, reinterpretv4hi, 0, df)
-+  VAR1 (REINTERP_PS, reinterpretv2si, 0, df)
-+  VAR1 (REINTERP_PS, reinterpretv2sf, 0, df)
-+
-   /* Implemented by aarch64_<sur>q<r>shl<mode>.  */
-   BUILTIN_VSDQ_I (BINOP, sqshl, 0)
--  BUILTIN_VSDQ_I (BINOP, uqshl, 0)
-+  BUILTIN_VSDQ_I (BINOP_UUS, uqshl, 0)
-   BUILTIN_VSDQ_I (BINOP, sqrshl, 0)
--  BUILTIN_VSDQ_I (BINOP, uqrshl, 0)
-+  BUILTIN_VSDQ_I (BINOP_UUS, uqrshl, 0)
-   /* Implemented by aarch64_<su_optab><optab><mode>.  */
-   BUILTIN_VSDQ_I (BINOP, sqadd, 0)
--  BUILTIN_VSDQ_I (BINOP, uqadd, 0)
-+  BUILTIN_VSDQ_I (BINOPU, uqadd, 0)
-   BUILTIN_VSDQ_I (BINOP, sqsub, 0)
--  BUILTIN_VSDQ_I (BINOP, uqsub, 0)
-+  BUILTIN_VSDQ_I (BINOPU, uqsub, 0)
-   /* Implemented by aarch64_<sur>qadd<mode>.  */
--  BUILTIN_VSDQ_I (BINOP, suqadd, 0)
--  BUILTIN_VSDQ_I (BINOP, usqadd, 0)
-+  BUILTIN_VSDQ_I (BINOP_SSU, suqadd, 0)
-+  BUILTIN_VSDQ_I (BINOP_UUS, usqadd, 0)
- 
-   /* Implemented by aarch64_get_dreg<VSTRUCT:mode><VDC:mode>.  */
-   BUILTIN_VDC (GETLANE, get_dregoi, 0)
-@@ -98,6 +106,10 @@
-   BUILTIN_VQ (LOADSTRUCT, ld2, 0)
-   BUILTIN_VQ (LOADSTRUCT, ld3, 0)
-   BUILTIN_VQ (LOADSTRUCT, ld4, 0)
-+  /* Implemented by aarch64_ld<VSTRUCT:nregs>r<VALLDIF:mode>.  */
-+  BUILTIN_VALLDIF (LOADSTRUCT, ld2r, 0)
-+  BUILTIN_VALLDIF (LOADSTRUCT, ld3r, 0)
-+  BUILTIN_VALLDIF (LOADSTRUCT, ld4r, 0)
-   /* Implemented by aarch64_st<VSTRUCT:nregs><VDC:mode>.  */
-   BUILTIN_VDC (STORESTRUCT, st2, 0)
-   BUILTIN_VDC (STORESTRUCT, st3, 0)
-@@ -107,6 +119,10 @@
-   BUILTIN_VQ (STORESTRUCT, st3, 0)
-   BUILTIN_VQ (STORESTRUCT, st4, 0)
- 
-+  BUILTIN_VQ (STORESTRUCT_LANE, st2_lane, 0)
-+  BUILTIN_VQ (STORESTRUCT_LANE, st3_lane, 0)
-+  BUILTIN_VQ (STORESTRUCT_LANE, st4_lane, 0)
-+
-   BUILTIN_VQW (BINOP, saddl2, 0)
-   BUILTIN_VQW (BINOP, uaddl2, 0)
-   BUILTIN_VQW (BINOP, ssubl2, 0)
-@@ -142,19 +158,19 @@
-   BUILTIN_VSQN_HSDI (UNOP, sqmovn, 0)
-   BUILTIN_VSQN_HSDI (UNOP, uqmovn, 0)
-   /* Implemented by aarch64_s<optab><mode>.  */
--  BUILTIN_VSDQ_I_BHSI (UNOP, sqabs, 0)
--  BUILTIN_VSDQ_I_BHSI (UNOP, sqneg, 0)
-+  BUILTIN_VSDQ_I (UNOP, sqabs, 0)
-+  BUILTIN_VSDQ_I (UNOP, sqneg, 0)
- 
--  BUILTIN_VSD_HSI (QUADOP, sqdmlal_lane, 0)
--  BUILTIN_VSD_HSI (QUADOP, sqdmlsl_lane, 0)
--  BUILTIN_VSD_HSI (QUADOP, sqdmlal_laneq, 0)
--  BUILTIN_VSD_HSI (QUADOP, sqdmlsl_laneq, 0)
-+  BUILTIN_VSD_HSI (TERNOP_LANE, sqdmlal_lane, 0)
-+  BUILTIN_VSD_HSI (TERNOP_LANE, sqdmlsl_lane, 0)
-+  BUILTIN_VSD_HSI (TERNOP_LANE, sqdmlal_laneq, 0)
-+  BUILTIN_VSD_HSI (TERNOP_LANE, sqdmlsl_laneq, 0)
-   BUILTIN_VQ_HSI (TERNOP, sqdmlal2, 0)
-   BUILTIN_VQ_HSI (TERNOP, sqdmlsl2, 0)
--  BUILTIN_VQ_HSI (QUADOP, sqdmlal2_lane, 0)
--  BUILTIN_VQ_HSI (QUADOP, sqdmlsl2_lane, 0)
--  BUILTIN_VQ_HSI (QUADOP, sqdmlal2_laneq, 0)
--  BUILTIN_VQ_HSI (QUADOP, sqdmlsl2_laneq, 0)
-+  BUILTIN_VQ_HSI (TERNOP_LANE, sqdmlal2_lane, 0)
-+  BUILTIN_VQ_HSI (TERNOP_LANE, sqdmlsl2_lane, 0)
-+  BUILTIN_VQ_HSI (TERNOP_LANE, sqdmlal2_laneq, 0)
-+  BUILTIN_VQ_HSI (TERNOP_LANE, sqdmlsl2_laneq, 0)
-   BUILTIN_VQ_HSI (TERNOP, sqdmlal2_n, 0)
-   BUILTIN_VQ_HSI (TERNOP, sqdmlsl2_n, 0)
-   /* Implemented by aarch64_sqdml<SBINQOPS:as>l<mode>.  */
-@@ -186,9 +202,9 @@
-   BUILTIN_VSDQ_I_DI (BINOP, ashl, 3)
-   /* Implemented by aarch64_<sur>shl<mode>.  */
-   BUILTIN_VSDQ_I_DI (BINOP, sshl, 0)
--  BUILTIN_VSDQ_I_DI (BINOP, ushl, 0)
-+  BUILTIN_VSDQ_I_DI (BINOP_UUS, ushl, 0)
-   BUILTIN_VSDQ_I_DI (BINOP, srshl, 0)
--  BUILTIN_VSDQ_I_DI (BINOP, urshl, 0)
-+  BUILTIN_VSDQ_I_DI (BINOP_UUS, urshl, 0)
- 
-   BUILTIN_VDQ_I (SHIFTIMM, ashr, 3)
-   VAR1 (SHIFTIMM, ashr_simd, 0, di)
-@@ -196,15 +212,15 @@
-   VAR1 (USHIFTIMM, lshr_simd, 0, di)
-   /* Implemented by aarch64_<sur>shr_n<mode>.  */
-   BUILTIN_VSDQ_I_DI (SHIFTIMM, srshr_n, 0)
--  BUILTIN_VSDQ_I_DI (SHIFTIMM, urshr_n, 0)
-+  BUILTIN_VSDQ_I_DI (USHIFTIMM, urshr_n, 0)
-   /* Implemented by aarch64_<sur>sra_n<mode>.  */
-   BUILTIN_VSDQ_I_DI (SHIFTACC, ssra_n, 0)
--  BUILTIN_VSDQ_I_DI (SHIFTACC, usra_n, 0)
-+  BUILTIN_VSDQ_I_DI (USHIFTACC, usra_n, 0)
-   BUILTIN_VSDQ_I_DI (SHIFTACC, srsra_n, 0)
--  BUILTIN_VSDQ_I_DI (SHIFTACC, ursra_n, 0)
-+  BUILTIN_VSDQ_I_DI (USHIFTACC, ursra_n, 0)
-   /* Implemented by aarch64_<sur>shll_n<mode>.  */
-   BUILTIN_VDW (SHIFTIMM, sshll_n, 0)
--  BUILTIN_VDW (SHIFTIMM, ushll_n, 0)
-+  BUILTIN_VDW (USHIFTIMM, ushll_n, 0)
-   /* Implemented by aarch64_<sur>shll2_n<mode>.  */
-   BUILTIN_VQW (SHIFTIMM, sshll2_n, 0)
-   BUILTIN_VQW (SHIFTIMM, ushll2_n, 0)
-@@ -212,30 +228,19 @@
-   BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrun_n, 0)
-   BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrun_n, 0)
-   BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrn_n, 0)
--  BUILTIN_VSQN_HSDI (SHIFTIMM, uqshrn_n, 0)
-+  BUILTIN_VSQN_HSDI (USHIFTIMM, uqshrn_n, 0)
-   BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrn_n, 0)
--  BUILTIN_VSQN_HSDI (SHIFTIMM, uqrshrn_n, 0)
-+  BUILTIN_VSQN_HSDI (USHIFTIMM, uqrshrn_n, 0)
-   /* Implemented by aarch64_<sur>s<lr>i_n<mode>.  */
-   BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssri_n, 0)
--  BUILTIN_VSDQ_I_DI (SHIFTINSERT, usri_n, 0)
-+  BUILTIN_VSDQ_I_DI (USHIFTACC, usri_n, 0)
-   BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssli_n, 0)
--  BUILTIN_VSDQ_I_DI (SHIFTINSERT, usli_n, 0)
-+  BUILTIN_VSDQ_I_DI (USHIFTACC, usli_n, 0)
-   /* Implemented by aarch64_<sur>qshl<u>_n<mode>.  */
--  BUILTIN_VSDQ_I (SHIFTIMM, sqshlu_n, 0)
-+  BUILTIN_VSDQ_I (SHIFTIMM_USS, sqshlu_n, 0)
-   BUILTIN_VSDQ_I (SHIFTIMM, sqshl_n, 0)
--  BUILTIN_VSDQ_I (SHIFTIMM, uqshl_n, 0)
-+  BUILTIN_VSDQ_I (USHIFTIMM, uqshl_n, 0)
- 
--  /* Implemented by aarch64_cm<cmp><mode>.  */
--  BUILTIN_VALLDI (BINOP, cmeq, 0)
--  BUILTIN_VALLDI (BINOP, cmge, 0)
--  BUILTIN_VALLDI (BINOP, cmgt, 0)
--  BUILTIN_VALLDI (BINOP, cmle, 0)
--  BUILTIN_VALLDI (BINOP, cmlt, 0)
--  /* Implemented by aarch64_cm<cmp><mode>.  */
--  BUILTIN_VSDQ_I_DI (BINOP, cmgeu, 0)
--  BUILTIN_VSDQ_I_DI (BINOP, cmgtu, 0)
--  BUILTIN_VSDQ_I_DI (BINOP, cmtst, 0)
--
-   /* Implemented by reduc_<sur>plus_<mode>.  */
-   BUILTIN_VALL (UNOP, reduc_splus_, 10)
-   BUILTIN_VDQ (UNOP, reduc_uplus_, 10)
-@@ -265,7 +270,7 @@
-   BUILTIN_VDQF (UNOP, nearbyint, 2)
-   BUILTIN_VDQF (UNOP, rint, 2)
-   BUILTIN_VDQF (UNOP, round, 2)
--  BUILTIN_VDQF (UNOP, frintn, 2)
-+  BUILTIN_VDQF_DF (UNOP, frintn, 2)
- 
-   /* Implemented by l<fcvt_pattern><su_optab><VQDF:mode><vcvt_target>2.  */
-   VAR1 (UNOP, lbtruncv2sf, 2, v2si)
-@@ -330,6 +335,10 @@
-   VAR1 (UNOP, floatunsv4si, 2, v4sf)
-   VAR1 (UNOP, floatunsv2di, 2, v2df)
- 
-+  VAR5 (UNOPU, bswap, 10, v4hi, v8hi, v2si, v4si, v2di)
-+
-+  BUILTIN_VB (UNOP, rbit, 0)
-+
-   /* Implemented by
-      aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>.  */
-   BUILTIN_VALL (BINOP, zip1, 0)
-@@ -393,3 +402,6 @@
-   /* Implemented by aarch64_crypto_pmull<mode>.  */
-   VAR1 (BINOPP, crypto_pmull, 0, di)
-   VAR1 (BINOPP, crypto_pmull, 0, v2di)
-+
-+  /* Meta-op to check lane bounds of immediate in aarch64_expand_builtin.  */
-+  VAR1 (BINOPV, im_lane_bound, 0, si)
---- a/src/gcc/config/aarch64/constraints.md
-+++ b/src/gcc/config/aarch64/constraints.md
-@@ -21,6 +21,9 @@
- (define_register_constraint "k" "STACK_REG"
-   "@internal The stack register.")
- 
-+(define_register_constraint "Ucs" "CALLER_SAVE_REGS"
-+  "@internal The caller save registers.")
-+
- (define_register_constraint "w" "FP_REGS"
-   "Floating point and SIMD vector registers.")
- 
-@@ -92,6 +95,10 @@
-   (and (match_code "const_int")
-        (match_test "(unsigned HOST_WIDE_INT) ival < 64")))
- 
-+(define_constraint "Usf"
-+  "@internal Usf is a symbol reference."
-+  (match_code "symbol_ref"))
-+
- (define_constraint "UsM"
-   "@internal
-   A constraint that matches the immediate constant -1."
---- a/src/gcc/config/aarch64/aarch64.c
-+++ b/src/gcc/config/aarch64/aarch64.c
-@@ -62,7 +62,8 @@
- #include "dwarf2.h"
- #include "cfgloop.h"
- #include "tree-vectorizer.h"
--#include "config/arm/aarch-cost-tables.h"
-+#include "aarch64-cost-tables.h"
-+#include "dumpfile.h"
- 
- /* Defined for convenience.  */
- #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
-@@ -136,12 +137,13 @@
- static void aarch64_override_options_after_change (void);
- static bool aarch64_vector_mode_supported_p (enum machine_mode);
- static unsigned bit_count (unsigned HOST_WIDE_INT);
--static bool aarch64_const_vec_all_same_int_p (rtx,
--					      HOST_WIDE_INT, HOST_WIDE_INT);
--
- static bool aarch64_vectorize_vec_perm_const_ok (enum machine_mode vmode,
- 						 const unsigned char *sel);
-+static int aarch64_address_cost (rtx, enum machine_mode, addr_space_t, bool);
- 
-+/* Major revision number of the ARM Architecture implemented by the target.  */
-+unsigned aarch64_architecture_version;
-+
- /* The processor for which instructions should be scheduled.  */
- enum aarch64_processor aarch64_tune = cortexa53;
- 
-@@ -171,6 +173,15 @@
- #endif
- static const struct cpu_addrcost_table generic_addrcost_table =
- {
-+#if HAVE_DESIGNATED_INITIALIZERS
-+  .addr_scale_costs =
-+#endif
-+    {
-+      NAMED_PARAM (hi, 0),
-+      NAMED_PARAM (si, 0),
-+      NAMED_PARAM (di, 0),
-+      NAMED_PARAM (ti, 0),
-+    },
-   NAMED_PARAM (pre_modify, 0),
-   NAMED_PARAM (post_modify, 0),
-   NAMED_PARAM (register_offset, 0),
-@@ -181,14 +192,60 @@
- #if HAVE_DESIGNATED_INITIALIZERS && GCC_VERSION >= 2007
- __extension__
- #endif
-+static const struct cpu_addrcost_table cortexa57_addrcost_table =
-+{
-+#if HAVE_DESIGNATED_INITIALIZERS
-+  .addr_scale_costs =
-+#endif
-+    {
-+      NAMED_PARAM (hi, 1),
-+      NAMED_PARAM (si, 0),
-+      NAMED_PARAM (di, 0),
-+      NAMED_PARAM (ti, 1),
-+    },
-+  NAMED_PARAM (pre_modify, 0),
-+  NAMED_PARAM (post_modify, 0),
-+  NAMED_PARAM (register_offset, 0),
-+  NAMED_PARAM (register_extend, 0),
-+  NAMED_PARAM (imm_offset, 0),
-+};
-+
-+#if HAVE_DESIGNATED_INITIALIZERS && GCC_VERSION >= 2007
-+__extension__
-+#endif
- static const struct cpu_regmove_cost generic_regmove_cost =
- {
-   NAMED_PARAM (GP2GP, 1),
-   NAMED_PARAM (GP2FP, 2),
-   NAMED_PARAM (FP2GP, 2),
--  /* We currently do not provide direct support for TFmode Q->Q move.
--     Therefore we need to raise the cost above 2 in order to have
--     reload handle the situation.  */
-+  NAMED_PARAM (FP2FP, 2)
-+};
-+
-+static const struct cpu_regmove_cost cortexa57_regmove_cost =
-+{
-+  NAMED_PARAM (GP2GP, 1),
-+  /* Avoid the use of slow int<->fp moves for spilling by setting
-+     their cost higher than memmov_cost.  */
-+  NAMED_PARAM (GP2FP, 5),
-+  NAMED_PARAM (FP2GP, 5),
-+  NAMED_PARAM (FP2FP, 2)
-+};
-+
-+static const struct cpu_regmove_cost cortexa53_regmove_cost =
-+{
-+  NAMED_PARAM (GP2GP, 1),
-+  /* Avoid the use of slow int<->fp moves for spilling by setting
-+     their cost higher than memmov_cost.  */
-+  NAMED_PARAM (GP2FP, 5),
-+  NAMED_PARAM (FP2GP, 5),
-+  NAMED_PARAM (FP2FP, 2)
-+};
-+
-+static const struct cpu_regmove_cost thunderx_regmove_cost =
-+{
-+  NAMED_PARAM (GP2GP, 2),
-+  NAMED_PARAM (GP2FP, 2),
-+  NAMED_PARAM (FP2GP, 6),
-   NAMED_PARAM (FP2FP, 4)
- };
- 
-@@ -212,9 +269,29 @@
-   NAMED_PARAM (cond_not_taken_branch_cost, 1)
- };
- 
-+/* Generic costs for vector insn classes.  */
- #if HAVE_DESIGNATED_INITIALIZERS && GCC_VERSION >= 2007
- __extension__
- #endif
-+static const struct cpu_vector_cost cortexa57_vector_cost =
-+{
-+  NAMED_PARAM (scalar_stmt_cost, 1),
-+  NAMED_PARAM (scalar_load_cost, 4),
-+  NAMED_PARAM (scalar_store_cost, 1),
-+  NAMED_PARAM (vec_stmt_cost, 3),
-+  NAMED_PARAM (vec_to_scalar_cost, 8),
-+  NAMED_PARAM (scalar_to_vec_cost, 8),
-+  NAMED_PARAM (vec_align_load_cost, 5),
-+  NAMED_PARAM (vec_unalign_load_cost, 5),
-+  NAMED_PARAM (vec_unalign_store_cost, 1),
-+  NAMED_PARAM (vec_store_cost, 1),
-+  NAMED_PARAM (cond_taken_branch_cost, 1),
-+  NAMED_PARAM (cond_not_taken_branch_cost, 1)
-+};
-+
-+#if HAVE_DESIGNATED_INITIALIZERS && GCC_VERSION >= 2007
-+__extension__
-+#endif
- static const struct tune_params generic_tunings =
- {
-   &cortexa57_extra_costs,
-@@ -229,7 +306,7 @@
- {
-   &cortexa53_extra_costs,
-   &generic_addrcost_table,
--  &generic_regmove_cost,
-+  &cortexa53_regmove_cost,
-   &generic_vector_cost,
-   NAMED_PARAM (memmov_cost, 4),
-   NAMED_PARAM (issue_rate, 2)
-@@ -238,13 +315,23 @@
- static const struct tune_params cortexa57_tunings =
- {
-   &cortexa57_extra_costs,
--  &generic_addrcost_table,
--  &generic_regmove_cost,
--  &generic_vector_cost,
-+  &cortexa57_addrcost_table,
-+  &cortexa57_regmove_cost,
-+  &cortexa57_vector_cost,
-   NAMED_PARAM (memmov_cost, 4),
-   NAMED_PARAM (issue_rate, 3)
- };
- 
-+static const struct tune_params thunderx_tunings =
-+{
-+  &thunderx_extra_costs,
-+  &generic_addrcost_table,
-+  &thunderx_regmove_cost,
-+  &generic_vector_cost,
-+  NAMED_PARAM (memmov_cost, 6),
-+  NAMED_PARAM (issue_rate, 2)
-+};
-+
- /* A processor implementing AArch64.  */
- struct processor
- {
-@@ -251,6 +338,7 @@
-   const char *const name;
-   enum aarch64_processor core;
-   const char *arch;
-+  unsigned architecture_version;
-   const unsigned long flags;
-   const struct tune_params *const tune;
- };
-@@ -259,11 +347,13 @@
- static const struct processor all_cores[] =
- {
- #define AARCH64_CORE(NAME, X, IDENT, ARCH, FLAGS, COSTS) \
--  {NAME, IDENT, #ARCH, FLAGS | AARCH64_FL_FOR_ARCH##ARCH, &COSTS##_tunings},
-+  {NAME, IDENT, #ARCH, ARCH,\
-+    FLAGS | AARCH64_FL_FOR_ARCH##ARCH, &COSTS##_tunings},
- #include "aarch64-cores.def"
- #undef AARCH64_CORE
--  {"generic", cortexa53, "8", AARCH64_FL_FPSIMD | AARCH64_FL_FOR_ARCH8, &generic_tunings},
--  {NULL, aarch64_none, NULL, 0, NULL}
-+  {"generic", cortexa53, "8", 8,\
-+    AARCH64_FL_FPSIMD | AARCH64_FL_FOR_ARCH8, &generic_tunings},
-+  {NULL, aarch64_none, NULL, 0, 0, NULL}
- };
- 
- /* Architectures implementing AArch64.  */
-@@ -270,10 +360,10 @@
- static const struct processor all_architectures[] =
- {
- #define AARCH64_ARCH(NAME, CORE, ARCH, FLAGS) \
--  {NAME, CORE, #ARCH, FLAGS, NULL},
-+  {NAME, CORE, #ARCH, ARCH, FLAGS, NULL},
- #include "aarch64-arches.def"
- #undef AARCH64_ARCH
--  {NULL, aarch64_none, NULL, 0, NULL}
-+  {NULL, aarch64_none, NULL, 0, 0, NULL}
- };
- 
- /* Target specification.  These are populated as commandline arguments
-@@ -424,6 +514,24 @@
-   return 0;
- }
- 
-+/* Implement HARD_REGNO_CALLER_SAVE_MODE.  */
-+enum machine_mode
-+aarch64_hard_regno_caller_save_mode (unsigned regno, unsigned nregs,
-+				     enum machine_mode mode)
-+{
-+  /* Handle modes that fit within single registers.  */
-+  if (nregs == 1 && GET_MODE_SIZE (mode) <= 16)
-+    {
-+      if (GET_MODE_SIZE (mode) >= 4)
-+        return mode;
-+      else
-+        return SImode;
-+    }
-+  /* Fall back to generic for multi-reg and very large modes.  */
-+  else
-+    return choose_hard_reg_mode (regno, nregs, false);
-+}
-+
- /* Return true if calls to DECL should be treated as
-    long-calls (ie called via a register).  */
- static bool
-@@ -444,7 +552,7 @@
-    represent an expression that matches an extend operation.  The
-    operands represent the paramters from
- 
--   (extract (mult (reg) (mult_imm)) (extract_imm) (const_int 0)).  */
-+   (extract:MODE (mult (reg) (MULT_IMM)) (EXTRACT_IMM) (const_int 0)).  */
- bool
- aarch64_is_extend_from_extract (enum machine_mode mode, rtx mult_imm,
- 				rtx extract_imm)
-@@ -636,12 +744,24 @@
- 
-     case SYMBOL_SMALL_TLSDESC:
-       {
--	rtx x0 = gen_rtx_REG (Pmode, R0_REGNUM);
-+	enum machine_mode mode = GET_MODE (dest);
-+	rtx x0 = gen_rtx_REG (mode, R0_REGNUM);
- 	rtx tp;
- 
--	emit_insn (gen_tlsdesc_small (imm));
-+	gcc_assert (mode == Pmode || mode == ptr_mode);
-+
-+	/* In ILP32, the got entry is always of SImode size.  Unlike
-+	   small GOT, the dest is fixed at reg 0.  */
-+	if (TARGET_ILP32)
-+	  emit_insn (gen_tlsdesc_small_si (imm));
-+	else
-+	  emit_insn (gen_tlsdesc_small_di (imm));
- 	tp = aarch64_load_tp (NULL);
--	emit_insn (gen_rtx_SET (Pmode, dest, gen_rtx_PLUS (Pmode, tp, x0)));
-+
-+	if (mode != Pmode)
-+	  tp = gen_lowpart (mode, tp);
-+
-+	emit_insn (gen_rtx_SET (mode, dest, gen_rtx_PLUS (mode, tp, x0)));
- 	set_unique_reg_note (get_last_insn (), REG_EQUIV, imm);
- 	return;
-       }
-@@ -648,10 +768,34 @@
- 
-     case SYMBOL_SMALL_GOTTPREL:
-       {
--	rtx tmp_reg = gen_reg_rtx (Pmode);
-+	/* In ILP32, the mode of dest can be either SImode or DImode,
-+	   while the got entry is always of SImode size.  The mode of
-+	   dest depends on how dest is used: if dest is assigned to a
-+	   pointer (e.g. in the memory), it has SImode; it may have
-+	   DImode if dest is dereferenced to access the memeory.
-+	   This is why we have to handle three different tlsie_small
-+	   patterns here (two patterns for ILP32).  */
-+	enum machine_mode mode = GET_MODE (dest);
-+	rtx tmp_reg = gen_reg_rtx (mode);
- 	rtx tp = aarch64_load_tp (NULL);
--	emit_insn (gen_tlsie_small (tmp_reg, imm));
--	emit_insn (gen_rtx_SET (Pmode, dest, gen_rtx_PLUS (Pmode, tp, tmp_reg)));
-+
-+	if (mode == ptr_mode)
-+	  {
-+	    if (mode == DImode)
-+	      emit_insn (gen_tlsie_small_di (tmp_reg, imm));
-+	    else
-+	      {
-+		emit_insn (gen_tlsie_small_si (tmp_reg, imm));
-+		tp = gen_lowpart (mode, tp);
-+	      }
-+	  }
-+	else
-+	  {
-+	    gcc_assert (mode == Pmode);
-+	    emit_insn (gen_tlsie_small_sidi (tmp_reg, imm));
-+	  }
-+
-+	emit_insn (gen_rtx_SET (mode, dest, gen_rtx_PLUS (mode, tp, tmp_reg)));
- 	set_unique_reg_note (get_last_insn (), REG_EQUIV, imm);
- 	return;
-       }
-@@ -889,10 +1033,10 @@
-   return plus_constant (mode, reg, offset);
- }
- 
--void
--aarch64_expand_mov_immediate (rtx dest, rtx imm)
-+static int
-+aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,
-+				machine_mode mode)
- {
--  enum machine_mode mode = GET_MODE (dest);
-   unsigned HOST_WIDE_INT mask;
-   int i;
-   bool first;
-@@ -899,86 +1043,15 @@
-   unsigned HOST_WIDE_INT val;
-   bool subtargets;
-   rtx subtarget;
--  int one_match, zero_match;
-+  int one_match, zero_match, first_not_ffff_match;
-+  int num_insns = 0;
- 
--  gcc_assert (mode == SImode || mode == DImode);
--
--  /* Check on what type of symbol it is.  */
--  if (GET_CODE (imm) == SYMBOL_REF
--      || GET_CODE (imm) == LABEL_REF
--      || GET_CODE (imm) == CONST)
--    {
--      rtx mem, base, offset;
--      enum aarch64_symbol_type sty;
--
--      /* If we have (const (plus symbol offset)), separate out the offset
--	 before we start classifying the symbol.  */
--      split_const (imm, &base, &offset);
--
--      sty = aarch64_classify_symbol (base, SYMBOL_CONTEXT_ADR);
--      switch (sty)
--	{
--	case SYMBOL_FORCE_TO_MEM:
--	  if (offset != const0_rtx
--	      && targetm.cannot_force_const_mem (mode, imm))
--	    {
--	      gcc_assert (can_create_pseudo_p ());
--	      base = aarch64_force_temporary (mode, dest, base);
--	      base = aarch64_add_offset (mode, NULL, base, INTVAL (offset));
--	      aarch64_emit_move (dest, base);
--	      return;
--	    }
--	  mem = force_const_mem (ptr_mode, imm);
--	  gcc_assert (mem);
--	  if (mode != ptr_mode)
--	    mem = gen_rtx_ZERO_EXTEND (mode, mem);
--	  emit_insn (gen_rtx_SET (VOIDmode, dest, mem));
--	  return;
--
--        case SYMBOL_SMALL_TLSGD:
--        case SYMBOL_SMALL_TLSDESC:
--        case SYMBOL_SMALL_GOTTPREL:
--	case SYMBOL_SMALL_GOT:
--	case SYMBOL_TINY_GOT:
--	  if (offset != const0_rtx)
--	    {
--	      gcc_assert(can_create_pseudo_p ());
--	      base = aarch64_force_temporary (mode, dest, base);
--	      base = aarch64_add_offset (mode, NULL, base, INTVAL (offset));
--	      aarch64_emit_move (dest, base);
--	      return;
--	    }
--	  /* FALLTHRU */
--
--        case SYMBOL_SMALL_TPREL:
--	case SYMBOL_SMALL_ABSOLUTE:
--	case SYMBOL_TINY_ABSOLUTE:
--	  aarch64_load_symref_appropriately (dest, imm, sty);
--	  return;
--
--	default:
--	  gcc_unreachable ();
--	}
--    }
--
-   if (CONST_INT_P (imm) && aarch64_move_imm (INTVAL (imm), mode))
-     {
--      emit_insn (gen_rtx_SET (VOIDmode, dest, imm));
--      return;
--    }
--
--  if (!CONST_INT_P (imm))
--    {
--      if (GET_CODE (imm) == HIGH)
-+      if (generate)
- 	emit_insn (gen_rtx_SET (VOIDmode, dest, imm));
--      else
--        {
--	  rtx mem = force_const_mem (mode, imm);
--	  gcc_assert (mem);
--	  emit_insn (gen_rtx_SET (VOIDmode, dest, mem));
--	}
--
--      return;
-+      num_insns++;
-+      return num_insns;
-     }
- 
-   if (mode == SImode)
-@@ -986,10 +1059,15 @@
-       /* We know we can't do this in 1 insn, and we must be able to do it
- 	 in two; so don't mess around looking for sequences that don't buy
- 	 us anything.  */
--      emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_INT (INTVAL (imm) & 0xffff)));
--      emit_insn (gen_insv_immsi (dest, GEN_INT (16),
--				 GEN_INT ((INTVAL (imm) >> 16) & 0xffff)));
--      return;
-+      if (generate)
-+	{
-+	  emit_insn (gen_rtx_SET (VOIDmode, dest,
-+				  GEN_INT (INTVAL (imm) & 0xffff)));
-+	  emit_insn (gen_insv_immsi (dest, GEN_INT (16),
-+				     GEN_INT ((INTVAL (imm) >> 16) & 0xffff)));
-+	}
-+      num_insns += 2;
-+      return num_insns;
-     }
- 
-   /* Remaining cases are all for DImode.  */
-@@ -1000,29 +1078,34 @@
-   one_match = 0;
-   zero_match = 0;
-   mask = 0xffff;
-+  first_not_ffff_match = -1;
- 
-   for (i = 0; i < 64; i += 16, mask <<= 16)
-     {
--      if ((val & mask) == 0)
--	zero_match++;
--      else if ((val & mask) == mask)
-+      if ((val & mask) == mask)
- 	one_match++;
-+      else
-+	{
-+	  if (first_not_ffff_match < 0)
-+	    first_not_ffff_match = i;
-+	  if ((val & mask) == 0)
-+	    zero_match++;
-+	}
-     }
- 
-   if (one_match == 2)
-     {
--      mask = 0xffff;
--      for (i = 0; i < 64; i += 16, mask <<= 16)
-+      /* Set one of the quarters and then insert back into result.  */
-+      mask = 0xffffll << first_not_ffff_match;
-+      if (generate)
- 	{
--	  if ((val & mask) != mask)
--	    {
--	      emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_INT (val | mask)));
--	      emit_insn (gen_insv_immdi (dest, GEN_INT (i),
--					 GEN_INT ((val >> i) & 0xffff)));
--	      return;
--	    }
-+	  emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_INT (val | mask)));
-+	  emit_insn (gen_insv_immdi (dest, GEN_INT (first_not_ffff_match),
-+				     GEN_INT ((val >> first_not_ffff_match)
-+					      & 0xffff)));
- 	}
--      gcc_unreachable ();
-+      num_insns += 2;
-+      return num_insns;
-     }
- 
-   if (zero_match == 2)
-@@ -1035,42 +1118,55 @@
- 
-       if (aarch64_uimm12_shift (val - (val & mask)))
- 	{
--	  subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
--
--	  emit_insn (gen_rtx_SET (VOIDmode, subtarget, GEN_INT (val & mask)));
--	  emit_insn (gen_adddi3 (dest, subtarget,
--				 GEN_INT (val - (val & mask))));
--	  return;
-+	  if (generate)
-+	    {
-+	      subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
-+	      emit_insn (gen_rtx_SET (VOIDmode, subtarget,
-+				      GEN_INT (val & mask)));
-+	      emit_insn (gen_adddi3 (dest, subtarget,
-+				     GEN_INT (val - (val & mask))));
-+	    }
-+	  num_insns += 2;
-+	  return num_insns;
- 	}
-       else if (aarch64_uimm12_shift (-(val - ((val + comp) & mask))))
- 	{
--	  subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
--
--	  emit_insn (gen_rtx_SET (VOIDmode, subtarget,
--				  GEN_INT ((val + comp) & mask)));
--	  emit_insn (gen_adddi3 (dest, subtarget,
--				 GEN_INT (val - ((val + comp) & mask))));
--	  return;
-+	  if (generate)
-+	    {
-+	      subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
-+	      emit_insn (gen_rtx_SET (VOIDmode, subtarget,
-+				      GEN_INT ((val + comp) & mask)));
-+	      emit_insn (gen_adddi3 (dest, subtarget,
-+				     GEN_INT (val - ((val + comp) & mask))));
-+	    }
-+	  num_insns += 2;
-+	  return num_insns;
- 	}
-       else if (aarch64_uimm12_shift (val - ((val - comp) | ~mask)))
- 	{
--	  subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
--
--	  emit_insn (gen_rtx_SET (VOIDmode, subtarget,
--				  GEN_INT ((val - comp) | ~mask)));
--	  emit_insn (gen_adddi3 (dest, subtarget,
--				 GEN_INT (val - ((val - comp) | ~mask))));
--	  return;
-+	  if (generate)
-+	    {
-+	      subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
-+	      emit_insn (gen_rtx_SET (VOIDmode, subtarget,
-+				      GEN_INT ((val - comp) | ~mask)));
-+	      emit_insn (gen_adddi3 (dest, subtarget,
-+				     GEN_INT (val - ((val - comp) | ~mask))));
-+	    }
-+	  num_insns += 2;
-+	  return num_insns;
- 	}
-       else if (aarch64_uimm12_shift (-(val - (val | ~mask))))
- 	{
--	  subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
--
--	  emit_insn (gen_rtx_SET (VOIDmode, subtarget,
--				  GEN_INT (val | ~mask)));
--	  emit_insn (gen_adddi3 (dest, subtarget,
--				 GEN_INT (val - (val | ~mask))));
--	  return;
-+	  if (generate)
-+	    {
-+	      subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
-+	      emit_insn (gen_rtx_SET (VOIDmode, subtarget,
-+				      GEN_INT (val | ~mask)));
-+	      emit_insn (gen_adddi3 (dest, subtarget,
-+				     GEN_INT (val - (val | ~mask))));
-+	    }
-+	  num_insns += 2;
-+	  return num_insns;
- 	}
-     }
- 
-@@ -1084,12 +1180,16 @@
-       if (aarch64_uimm12_shift (val - aarch64_bitmasks[i])
- 	  || aarch64_uimm12_shift (-val + aarch64_bitmasks[i]))
- 	{
--	  subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
--	  emit_insn (gen_rtx_SET (VOIDmode, subtarget,
--				  GEN_INT (aarch64_bitmasks[i])));
--	  emit_insn (gen_adddi3 (dest, subtarget,
--				 GEN_INT (val - aarch64_bitmasks[i])));
--	  return;
-+	  if (generate)
-+	    {
-+	      subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
-+	      emit_insn (gen_rtx_SET (VOIDmode, subtarget,
-+				      GEN_INT (aarch64_bitmasks[i])));
-+	      emit_insn (gen_adddi3 (dest, subtarget,
-+				     GEN_INT (val - aarch64_bitmasks[i])));
-+	    }
-+	  num_insns += 2;
-+	  return num_insns;
- 	}
- 
-       for (j = 0; j < 64; j += 16, mask <<= 16)
-@@ -1096,11 +1196,15 @@
- 	{
- 	  if ((aarch64_bitmasks[i] & ~mask) == (val & ~mask))
- 	    {
--	      emit_insn (gen_rtx_SET (VOIDmode, dest,
--				      GEN_INT (aarch64_bitmasks[i])));
--	      emit_insn (gen_insv_immdi (dest, GEN_INT (j),
--					 GEN_INT ((val >> j) & 0xffff)));
--	      return;
-+	      if (generate)
-+		{
-+		  emit_insn (gen_rtx_SET (VOIDmode, dest,
-+					  GEN_INT (aarch64_bitmasks[i])));
-+		  emit_insn (gen_insv_immdi (dest, GEN_INT (j),
-+					     GEN_INT ((val >> j) & 0xffff)));
-+		}
-+	      num_insns += 2;
-+	      return num_insns;
- 	    }
- 	}
-     }
-@@ -1115,12 +1219,16 @@
- 	  for (j = i + 1; j < AARCH64_NUM_BITMASKS; j++)
- 	    if (val == (aarch64_bitmasks[i] | aarch64_bitmasks[j]))
- 	      {
--		subtarget = subtargets ? gen_reg_rtx (mode) : dest;
--		emit_insn (gen_rtx_SET (VOIDmode, subtarget,
--					GEN_INT (aarch64_bitmasks[i])));
--		emit_insn (gen_iordi3 (dest, subtarget,
--				       GEN_INT (aarch64_bitmasks[j])));
--		return;
-+		if (generate)
-+		  {
-+		    subtarget = subtargets ? gen_reg_rtx (mode) : dest;
-+		    emit_insn (gen_rtx_SET (VOIDmode, subtarget,
-+					    GEN_INT (aarch64_bitmasks[i])));
-+		    emit_insn (gen_iordi3 (dest, subtarget,
-+					   GEN_INT (aarch64_bitmasks[j])));
-+		  }
-+		num_insns += 2;
-+		return num_insns;
- 	      }
- 	}
-       else if ((val & aarch64_bitmasks[i]) == val)
-@@ -1130,17 +1238,44 @@
- 	  for (j = i + 1; j < AARCH64_NUM_BITMASKS; j++)
- 	    if (val == (aarch64_bitmasks[j] & aarch64_bitmasks[i]))
- 	      {
--
--		subtarget = subtargets ? gen_reg_rtx (mode) : dest;
--		emit_insn (gen_rtx_SET (VOIDmode, subtarget,
--					GEN_INT (aarch64_bitmasks[j])));
--		emit_insn (gen_anddi3 (dest, subtarget,
--				       GEN_INT (aarch64_bitmasks[i])));
--		return;
-+		if (generate)
-+		  {
-+		    subtarget = subtargets ? gen_reg_rtx (mode) : dest;
-+		    emit_insn (gen_rtx_SET (VOIDmode, subtarget,
-+					    GEN_INT (aarch64_bitmasks[j])));
-+		    emit_insn (gen_anddi3 (dest, subtarget,
-+					   GEN_INT (aarch64_bitmasks[i])));
-+		  }
-+		num_insns += 2;
-+		return num_insns;
- 	      }
- 	}
-     }
- 
-+  if (one_match > zero_match)
-+    {
-+      /* Set either first three quarters or all but the third.	 */
-+      mask = 0xffffll << (16 - first_not_ffff_match);
-+      if (generate)
-+	emit_insn (gen_rtx_SET (VOIDmode, dest,
-+				GEN_INT (val | mask | 0xffffffff00000000ull)));
-+      num_insns ++;
-+
-+      /* Now insert other two quarters.	 */
-+      for (i = first_not_ffff_match + 16, mask <<= (first_not_ffff_match << 1);
-+	   i < 64; i += 16, mask <<= 16)
-+	{
-+	  if ((val & mask) != mask)
-+	    {
-+	      if (generate)
-+		emit_insn (gen_insv_immdi (dest, GEN_INT (i),
-+					   GEN_INT ((val >> i) & 0xffff)));
-+	      num_insns ++;
-+	    }
-+	}
-+      return num_insns;
-+    }
-+
-  simple_sequence:
-   first = true;
-   mask = 0xffff;
-@@ -1150,30 +1285,113 @@
- 	{
- 	  if (first)
- 	    {
--	      emit_insn (gen_rtx_SET (VOIDmode, dest,
--				      GEN_INT (val & mask)));
-+	      if (generate)
-+		emit_insn (gen_rtx_SET (VOIDmode, dest,
-+					GEN_INT (val & mask)));
-+	      num_insns ++;
- 	      first = false;
- 	    }
- 	  else
--	    emit_insn (gen_insv_immdi (dest, GEN_INT (i),
--				       GEN_INT ((val >> i) & 0xffff)));
-+	    {
-+	      if (generate)
-+		emit_insn (gen_insv_immdi (dest, GEN_INT (i),
-+					   GEN_INT ((val >> i) & 0xffff)));
-+	      num_insns ++;
-+	    }
- 	}
-     }
-+
-+  return num_insns;
- }
- 
--static bool
--aarch64_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
-+
-+void
-+aarch64_expand_mov_immediate (rtx dest, rtx imm)
- {
--  /* Indirect calls are not currently supported.  */
--  if (decl == NULL)
--    return false;
-+  machine_mode mode = GET_MODE (dest);
- 
--  /* Cannot tail-call to long-calls, since these are outside of the
--     range of a branch instruction (we could handle this if we added
--     support for indirect tail-calls.  */
--  if (aarch64_decl_is_long_call_p (decl))
--    return false;
-+  gcc_assert (mode == SImode || mode == DImode);
- 
-+  /* Check on what type of symbol it is.  */
-+  if (GET_CODE (imm) == SYMBOL_REF
-+      || GET_CODE (imm) == LABEL_REF
-+      || GET_CODE (imm) == CONST)
-+    {
-+      rtx mem, base, offset;
-+      enum aarch64_symbol_type sty;
-+
-+      /* If we have (const (plus symbol offset)), separate out the offset
-+	 before we start classifying the symbol.  */
-+      split_const (imm, &base, &offset);
-+
-+      sty = aarch64_classify_symbol (base, SYMBOL_CONTEXT_ADR);
-+      switch (sty)
-+	{
-+	case SYMBOL_FORCE_TO_MEM:
-+	  if (offset != const0_rtx
-+	      && targetm.cannot_force_const_mem (mode, imm))
-+	    {
-+	      gcc_assert (can_create_pseudo_p ());
-+	      base = aarch64_force_temporary (mode, dest, base);
-+	      base = aarch64_add_offset (mode, NULL, base, INTVAL (offset));
-+	      aarch64_emit_move (dest, base);
-+	      return;
-+	    }
-+	  mem = force_const_mem (ptr_mode, imm);
-+	  gcc_assert (mem);
-+	  if (mode != ptr_mode)
-+	    mem = gen_rtx_ZERO_EXTEND (mode, mem);
-+	  emit_insn (gen_rtx_SET (VOIDmode, dest, mem));
-+	  return;
-+
-+        case SYMBOL_SMALL_TLSGD:
-+        case SYMBOL_SMALL_TLSDESC:
-+        case SYMBOL_SMALL_GOTTPREL:
-+	case SYMBOL_SMALL_GOT:
-+	case SYMBOL_TINY_GOT:
-+	  if (offset != const0_rtx)
-+	    {
-+	      gcc_assert(can_create_pseudo_p ());
-+	      base = aarch64_force_temporary (mode, dest, base);
-+	      base = aarch64_add_offset (mode, NULL, base, INTVAL (offset));
-+	      aarch64_emit_move (dest, base);
-+	      return;
-+	    }
-+	  /* FALLTHRU */
-+
-+        case SYMBOL_SMALL_TPREL:
-+	case SYMBOL_SMALL_ABSOLUTE:
-+	case SYMBOL_TINY_ABSOLUTE:
-+	  aarch64_load_symref_appropriately (dest, imm, sty);
-+	  return;
-+
-+	default:
-+	  gcc_unreachable ();
-+	}
-+    }
-+
-+  if (!CONST_INT_P (imm))
-+    {
-+      if (GET_CODE (imm) == HIGH)
-+	emit_insn (gen_rtx_SET (VOIDmode, dest, imm));
-+      else
-+        {
-+	  rtx mem = force_const_mem (mode, imm);
-+	  gcc_assert (mem);
-+	  emit_insn (gen_rtx_SET (VOIDmode, dest, mem));
-+	}
-+
-+      return;
-+    }
-+
-+  aarch64_internal_mov_immediate (dest, imm, true, GET_MODE (dest));
-+}
-+
-+static bool
-+aarch64_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
-+				 tree exp ATTRIBUTE_UNUSED)
-+{
-+  /* Currently, always true.  */
-   return true;
- }
- 
-@@ -1688,11 +1906,6 @@
- static bool
- aarch64_frame_pointer_required (void)
- {
--  /* If the function contains dynamic stack allocations, we need to
--     use the frame pointer to access the static parts of the frame.  */
--  if (cfun->calls_alloca)
--    return true;
--
-   /* In aarch64_override_options_after_change
-      flag_omit_leaf_frame_pointer turns off the frame pointer by
-      default.  Turn it back on now if we've not got a leaf
-@@ -1716,268 +1929,312 @@
-   if (reload_completed && cfun->machine->frame.laid_out)
-     return;
- 
--  cfun->machine->frame.fp_lr_offset = 0;
-+#define SLOT_NOT_REQUIRED (-2)
-+#define SLOT_REQUIRED     (-1)
- 
-+  cfun->machine->frame.wb_candidate1 = FIRST_PSEUDO_REGISTER;
-+  cfun->machine->frame.wb_candidate2 = FIRST_PSEUDO_REGISTER;
-+
-   /* First mark all the registers that really need to be saved...  */
-   for (regno = R0_REGNUM; regno <= R30_REGNUM; regno++)
--    cfun->machine->frame.reg_offset[regno] = -1;
-+    cfun->machine->frame.reg_offset[regno] = SLOT_NOT_REQUIRED;
- 
-   for (regno = V0_REGNUM; regno <= V31_REGNUM; regno++)
--    cfun->machine->frame.reg_offset[regno] = -1;
-+    cfun->machine->frame.reg_offset[regno] = SLOT_NOT_REQUIRED;
- 
-   /* ... that includes the eh data registers (if needed)...  */
-   if (crtl->calls_eh_return)
-     for (regno = 0; EH_RETURN_DATA_REGNO (regno) != INVALID_REGNUM; regno++)
--      cfun->machine->frame.reg_offset[EH_RETURN_DATA_REGNO (regno)] = 0;
-+      cfun->machine->frame.reg_offset[EH_RETURN_DATA_REGNO (regno)]
-+	= SLOT_REQUIRED;
- 
-   /* ... and any callee saved register that dataflow says is live.  */
-   for (regno = R0_REGNUM; regno <= R30_REGNUM; regno++)
-     if (df_regs_ever_live_p (regno)
- 	&& !call_used_regs[regno])
--      cfun->machine->frame.reg_offset[regno] = 0;
-+      cfun->machine->frame.reg_offset[regno] = SLOT_REQUIRED;
- 
-   for (regno = V0_REGNUM; regno <= V31_REGNUM; regno++)
-     if (df_regs_ever_live_p (regno)
- 	&& !call_used_regs[regno])
--      cfun->machine->frame.reg_offset[regno] = 0;
-+      cfun->machine->frame.reg_offset[regno] = SLOT_REQUIRED;
- 
-   if (frame_pointer_needed)
-     {
--      cfun->machine->frame.reg_offset[R30_REGNUM] = 0;
-+      /* FP and LR are placed in the linkage record.  */
-       cfun->machine->frame.reg_offset[R29_REGNUM] = 0;
-+      cfun->machine->frame.wb_candidate1 = R29_REGNUM;
-+      cfun->machine->frame.reg_offset[R30_REGNUM] = UNITS_PER_WORD;
-+      cfun->machine->frame.wb_candidate2 = R30_REGNUM;
-       cfun->machine->frame.hardfp_offset = 2 * UNITS_PER_WORD;
-+      offset += 2 * UNITS_PER_WORD;
-     }
- 
-   /* Now assign stack slots for them.  */
--  for (regno = R0_REGNUM; regno <= R28_REGNUM; regno++)
--    if (cfun->machine->frame.reg_offset[regno] != -1)
-+  for (regno = R0_REGNUM; regno <= R30_REGNUM; regno++)
-+    if (cfun->machine->frame.reg_offset[regno] == SLOT_REQUIRED)
-       {
- 	cfun->machine->frame.reg_offset[regno] = offset;
-+	if (cfun->machine->frame.wb_candidate1 == FIRST_PSEUDO_REGISTER)
-+	  cfun->machine->frame.wb_candidate1 = regno;
-+	else if (cfun->machine->frame.wb_candidate2 == FIRST_PSEUDO_REGISTER)
-+	  cfun->machine->frame.wb_candidate2 = regno;
- 	offset += UNITS_PER_WORD;
-       }
- 
-   for (regno = V0_REGNUM; regno <= V31_REGNUM; regno++)
--    if (cfun->machine->frame.reg_offset[regno] != -1)
-+    if (cfun->machine->frame.reg_offset[regno] == SLOT_REQUIRED)
-       {
- 	cfun->machine->frame.reg_offset[regno] = offset;
-+	if (cfun->machine->frame.wb_candidate1 == FIRST_PSEUDO_REGISTER)
-+	  cfun->machine->frame.wb_candidate1 = regno;
-+	else if (cfun->machine->frame.wb_candidate2 == FIRST_PSEUDO_REGISTER
-+		 && cfun->machine->frame.wb_candidate1 >= V0_REGNUM)
-+	  cfun->machine->frame.wb_candidate2 = regno;
- 	offset += UNITS_PER_WORD;
-       }
- 
--  if (frame_pointer_needed)
--    {
--      cfun->machine->frame.reg_offset[R29_REGNUM] = offset;
--      offset += UNITS_PER_WORD;
--      cfun->machine->frame.fp_lr_offset = UNITS_PER_WORD;
--    }
--
--  if (cfun->machine->frame.reg_offset[R30_REGNUM] != -1)
--    {
--      cfun->machine->frame.reg_offset[R30_REGNUM] = offset;
--      offset += UNITS_PER_WORD;
--      cfun->machine->frame.fp_lr_offset += UNITS_PER_WORD;
--    }
--
-   cfun->machine->frame.padding0 =
-     (AARCH64_ROUND_UP (offset, STACK_BOUNDARY / BITS_PER_UNIT) - offset);
-   offset = AARCH64_ROUND_UP (offset, STACK_BOUNDARY / BITS_PER_UNIT);
- 
-   cfun->machine->frame.saved_regs_size = offset;
-+
-+  cfun->machine->frame.hard_fp_offset
-+    = AARCH64_ROUND_UP (cfun->machine->frame.saved_varargs_size
-+			+ get_frame_size ()
-+			+ cfun->machine->frame.saved_regs_size,
-+			STACK_BOUNDARY / BITS_PER_UNIT);
-+
-+  cfun->machine->frame.frame_size
-+    = AARCH64_ROUND_UP (cfun->machine->frame.hard_fp_offset
-+			+ crtl->outgoing_args_size,
-+			STACK_BOUNDARY / BITS_PER_UNIT);
-+
-   cfun->machine->frame.laid_out = true;
- }
- 
--/* Make the last instruction frame-related and note that it performs
--   the operation described by FRAME_PATTERN.  */
-+static bool
-+aarch64_register_saved_on_entry (int regno)
-+{
-+  return cfun->machine->frame.reg_offset[regno] >= 0;
-+}
- 
-+static unsigned
-+aarch64_next_callee_save (unsigned regno, unsigned limit)
-+{
-+  while (regno <= limit && !aarch64_register_saved_on_entry (regno))
-+    regno ++;
-+  return regno;
-+}
-+
- static void
--aarch64_set_frame_expr (rtx frame_pattern)
-+aarch64_pushwb_single_reg (enum machine_mode mode, unsigned regno,
-+			   HOST_WIDE_INT adjustment)
-+ {
-+  rtx base_rtx = stack_pointer_rtx;
-+  rtx insn, reg, mem;
-+
-+  reg = gen_rtx_REG (mode, regno);
-+  mem = gen_rtx_PRE_MODIFY (Pmode, base_rtx,
-+			    plus_constant (Pmode, base_rtx, -adjustment));
-+  mem = gen_rtx_MEM (mode, mem);
-+
-+  insn = emit_move_insn (mem, reg);
-+  RTX_FRAME_RELATED_P (insn) = 1;
-+}
-+
-+static rtx
-+aarch64_gen_storewb_pair (enum machine_mode mode, rtx base, rtx reg, rtx reg2,
-+			  HOST_WIDE_INT adjustment)
- {
-+  switch (mode)
-+    {
-+    case DImode:
-+      return gen_storewb_pairdi_di (base, base, reg, reg2,
-+				    GEN_INT (-adjustment),
-+				    GEN_INT (UNITS_PER_WORD - adjustment));
-+    case DFmode:
-+      return gen_storewb_pairdf_di (base, base, reg, reg2,
-+				    GEN_INT (-adjustment),
-+				    GEN_INT (UNITS_PER_WORD - adjustment));
-+    default:
-+      gcc_unreachable ();
-+    }
-+}
-+
-+static void
-+aarch64_pushwb_pair_reg (enum machine_mode mode, unsigned regno1,
-+			 unsigned regno2, HOST_WIDE_INT adjustment)
-+{
-   rtx insn;
-+  rtx reg1 = gen_rtx_REG (mode, regno1);
-+  rtx reg2 = gen_rtx_REG (mode, regno2);
- 
--  insn = get_last_insn ();
-+  insn = emit_insn (aarch64_gen_storewb_pair (mode, stack_pointer_rtx, reg1,
-+					      reg2, adjustment));
-+  RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 2)) = 1;
-+
-+  RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
-   RTX_FRAME_RELATED_P (insn) = 1;
--  RTX_FRAME_RELATED_P (frame_pattern) = 1;
--  REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
--				      frame_pattern,
--				      REG_NOTES (insn));
- }
- 
--static bool
--aarch64_register_saved_on_entry (int regno)
-+static rtx
-+aarch64_gen_loadwb_pair (enum machine_mode mode, rtx base, rtx reg, rtx reg2,
-+			 HOST_WIDE_INT adjustment)
- {
--  return cfun->machine->frame.reg_offset[regno] != -1;
-+  switch (mode)
-+    {
-+    case DImode:
-+      return gen_loadwb_pairdi_di (base, base, reg, reg2, GEN_INT (adjustment),
-+				   GEN_INT (UNITS_PER_WORD));
-+    case DFmode:
-+      return gen_loadwb_pairdf_di (base, base, reg, reg2, GEN_INT (adjustment),
-+				   GEN_INT (UNITS_PER_WORD));
-+    default:
-+      gcc_unreachable ();
-+    }
- }
- 
-+static rtx
-+aarch64_gen_store_pair (enum machine_mode mode, rtx mem1, rtx reg1, rtx mem2,
-+			rtx reg2)
-+{
-+  switch (mode)
-+    {
-+    case DImode:
-+      return gen_store_pairdi (mem1, reg1, mem2, reg2);
- 
--static void
--aarch64_save_or_restore_fprs (int start_offset, int increment,
--			      bool restore, rtx base_rtx)
-+    case DFmode:
-+      return gen_store_pairdf (mem1, reg1, mem2, reg2);
- 
-+    default:
-+      gcc_unreachable ();
-+    }
-+}
-+
-+static rtx
-+aarch64_gen_load_pair (enum machine_mode mode, rtx reg1, rtx mem1, rtx reg2,
-+		       rtx mem2)
- {
-+  switch (mode)
-+    {
-+    case DImode:
-+      return gen_load_pairdi (reg1, mem1, reg2, mem2);
-+
-+    case DFmode:
-+      return gen_load_pairdf (reg1, mem1, reg2, mem2);
-+
-+    default:
-+      gcc_unreachable ();
-+    }
-+}
-+
-+
-+static void
-+aarch64_save_callee_saves (enum machine_mode mode, HOST_WIDE_INT start_offset,
-+			   unsigned start, unsigned limit, bool skip_wb)
-+{
-+  rtx insn;
-+  rtx (*gen_mem_ref) (enum machine_mode, rtx) = (frame_pointer_needed
-+						 ? gen_frame_mem : gen_rtx_MEM);
-   unsigned regno;
-   unsigned regno2;
--  rtx insn;
--  rtx (*gen_mem_ref)(enum machine_mode, rtx)
--    = (frame_pointer_needed)? gen_frame_mem : gen_rtx_MEM;
- 
--
--  for (regno = V0_REGNUM; regno <= V31_REGNUM; regno++)
-+  for (regno = aarch64_next_callee_save (start, limit);
-+       regno <= limit;
-+       regno = aarch64_next_callee_save (regno + 1, limit))
-     {
--      if (aarch64_register_saved_on_entry (regno))
--	{
--	  rtx mem;
--	  mem = gen_mem_ref (DFmode,
--			     plus_constant (Pmode,
--					    base_rtx,
--					    start_offset));
-+      rtx reg, mem;
-+      HOST_WIDE_INT offset;
- 
--	  for (regno2 = regno + 1;
--	       regno2 <= V31_REGNUM
--		 && !aarch64_register_saved_on_entry (regno2);
--	       regno2++)
--	    {
--	      /* Empty loop.  */
--	    }
--	  if (regno2 <= V31_REGNUM &&
--	      aarch64_register_saved_on_entry (regno2))
--	    {
--	      rtx mem2;
--	      /* Next highest register to be saved.  */
--	      mem2 = gen_mem_ref (DFmode,
--				  plus_constant
--				  (Pmode,
--				   base_rtx,
--				   start_offset + increment));
--	      if (restore == false)
--		{
--		  insn = emit_insn
--		    ( gen_store_pairdf (mem, gen_rtx_REG (DFmode, regno),
--					mem2, gen_rtx_REG (DFmode, regno2)));
-+      if (skip_wb
-+	  && (regno == cfun->machine->frame.wb_candidate1
-+	      || regno == cfun->machine->frame.wb_candidate2))
-+	continue;
- 
--		}
--	      else
--		{
--		  insn = emit_insn
--		    ( gen_load_pairdf (gen_rtx_REG (DFmode, regno), mem,
--				       gen_rtx_REG (DFmode, regno2), mem2));
-+      reg = gen_rtx_REG (mode, regno);
-+      offset = start_offset + cfun->machine->frame.reg_offset[regno];
-+      mem = gen_mem_ref (mode, plus_constant (Pmode, stack_pointer_rtx,
-+					      offset));
- 
--		  add_reg_note (insn, REG_CFA_RESTORE,
--				gen_rtx_REG (DFmode, regno));
--		  add_reg_note (insn, REG_CFA_RESTORE,
--				gen_rtx_REG (DFmode, regno2));
--		}
-+      regno2 = aarch64_next_callee_save (regno + 1, limit);
- 
--		  /* The first part of a frame-related parallel insn
--		     is always assumed to be relevant to the frame
--		     calculations; subsequent parts, are only
--		     frame-related if explicitly marked.  */
--	      RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
--	      regno = regno2;
--	      start_offset += increment * 2;
--	    }
--	  else
--	    {
--	      if (restore == false)
--		insn = emit_move_insn (mem, gen_rtx_REG (DFmode, regno));
--	      else
--		{
--		  insn = emit_move_insn (gen_rtx_REG (DFmode, regno), mem);
--		  add_reg_note (insn, REG_CFA_RESTORE,
--				gen_rtx_REG (DImode, regno));
--		}
--	      start_offset += increment;
--	    }
--	  RTX_FRAME_RELATED_P (insn) = 1;
-+      if (regno2 <= limit
-+	  && ((cfun->machine->frame.reg_offset[regno] + UNITS_PER_WORD)
-+	      == cfun->machine->frame.reg_offset[regno2]))
-+
-+	{
-+	  rtx reg2 = gen_rtx_REG (mode, regno2);
-+	  rtx mem2;
-+
-+	  offset = start_offset + cfun->machine->frame.reg_offset[regno2];
-+	  mem2 = gen_mem_ref (mode, plus_constant (Pmode, stack_pointer_rtx,
-+						   offset));
-+	  insn = emit_insn (aarch64_gen_store_pair (mode, mem, reg, mem2,
-+						    reg2));
-+
-+	  /* The first part of a frame-related parallel insn is
-+	     always assumed to be relevant to the frame
-+	     calculations; subsequent parts, are only
-+	     frame-related if explicitly marked.  */
-+	  RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
-+	  regno = regno2;
- 	}
-+      else
-+	insn = emit_move_insn (mem, reg);
-+
-+      RTX_FRAME_RELATED_P (insn) = 1;
-     }
--
- }
- 
--
--/* offset from the stack pointer of where the saves and
--   restore's have to happen.  */
- static void
--aarch64_save_or_restore_callee_save_registers (HOST_WIDE_INT offset,
--					    bool restore)
-+aarch64_restore_callee_saves (enum machine_mode mode,
-+			      HOST_WIDE_INT start_offset, unsigned start,
-+			      unsigned limit, bool skip_wb, rtx *cfi_ops)
- {
--  rtx insn;
-   rtx base_rtx = stack_pointer_rtx;
--  HOST_WIDE_INT start_offset = offset;
--  HOST_WIDE_INT increment = UNITS_PER_WORD;
--  rtx (*gen_mem_ref)(enum machine_mode, rtx) = (frame_pointer_needed)? gen_frame_mem : gen_rtx_MEM;
--  unsigned limit = (frame_pointer_needed)? R28_REGNUM: R30_REGNUM;
-+  rtx (*gen_mem_ref) (enum machine_mode, rtx) = (frame_pointer_needed
-+						 ? gen_frame_mem : gen_rtx_MEM);
-   unsigned regno;
-   unsigned regno2;
-+  HOST_WIDE_INT offset;
- 
--  for (regno = R0_REGNUM; regno <= limit; regno++)
-+  for (regno = aarch64_next_callee_save (start, limit);
-+       regno <= limit;
-+       regno = aarch64_next_callee_save (regno + 1, limit))
-     {
--      if (aarch64_register_saved_on_entry (regno))
--	{
--	  rtx mem;
--	  mem = gen_mem_ref (Pmode,
--			     plus_constant (Pmode,
--					    base_rtx,
--					    start_offset));
-+      rtx reg, mem;
- 
--	  for (regno2 = regno + 1;
--	       regno2 <= limit
--		 && !aarch64_register_saved_on_entry (regno2);
--	       regno2++)
--	    {
--	      /* Empty loop.  */
--	    }
--	  if (regno2 <= limit &&
--	      aarch64_register_saved_on_entry (regno2))
--	    {
--	      rtx mem2;
--	      /* Next highest register to be saved.  */
--	      mem2 = gen_mem_ref (Pmode,
--				  plus_constant
--				  (Pmode,
--				   base_rtx,
--				   start_offset + increment));
--	      if (restore == false)
--		{
--		  insn = emit_insn
--		    ( gen_store_pairdi (mem, gen_rtx_REG (DImode, regno),
--					mem2, gen_rtx_REG (DImode, regno2)));
-+      if (skip_wb
-+	  && (regno == cfun->machine->frame.wb_candidate1
-+	      || regno == cfun->machine->frame.wb_candidate2))
-+	continue;
- 
--		}
--	      else
--		{
--		  insn = emit_insn
--		    ( gen_load_pairdi (gen_rtx_REG (DImode, regno), mem,
--				     gen_rtx_REG (DImode, regno2), mem2));
-+      reg = gen_rtx_REG (mode, regno);
-+      offset = start_offset + cfun->machine->frame.reg_offset[regno];
-+      mem = gen_mem_ref (mode, plus_constant (Pmode, base_rtx, offset));
- 
--		  add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (DImode, regno));
--		  add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (DImode, regno2));
--		}
-+      regno2 = aarch64_next_callee_save (regno + 1, limit);
- 
--		  /* The first part of a frame-related parallel insn
--		     is always assumed to be relevant to the frame
--		     calculations; subsequent parts, are only
--		     frame-related if explicitly marked.  */
--	      RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0,
--					    1)) = 1;
--	      regno = regno2;
--	      start_offset += increment * 2;
--	    }
--	  else
--	    {
--	      if (restore == false)
--		insn = emit_move_insn (mem, gen_rtx_REG (DImode, regno));
--	      else
--		{
--		  insn = emit_move_insn (gen_rtx_REG (DImode, regno), mem);
--		  add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (DImode, regno));
--		}
--	      start_offset += increment;
--	    }
--	  RTX_FRAME_RELATED_P (insn) = 1;
-+      if (regno2 <= limit
-+	  && ((cfun->machine->frame.reg_offset[regno] + UNITS_PER_WORD)
-+	      == cfun->machine->frame.reg_offset[regno2]))
-+	{
-+	  rtx reg2 = gen_rtx_REG (mode, regno2);
-+	  rtx mem2;
-+
-+	  offset = start_offset + cfun->machine->frame.reg_offset[regno2];
-+	  mem2 = gen_mem_ref (mode, plus_constant (Pmode, base_rtx, offset));
-+	  emit_insn (aarch64_gen_load_pair (mode, reg, mem, reg2, mem2));
-+
-+	  *cfi_ops = alloc_reg_note (REG_CFA_RESTORE, reg2, *cfi_ops);
-+	  regno = regno2;
- 	}
-+      else
-+	emit_move_insn (reg, mem);
-+      *cfi_ops = alloc_reg_note (REG_CFA_RESTORE, reg, *cfi_ops);
-     }
--
--  aarch64_save_or_restore_fprs (start_offset, increment, restore, base_rtx);
--
- }
- 
- /* AArch64 stack frames generated by this compiler look like:
-@@ -1986,37 +2243,35 @@
- 	|                               |
- 	|  incoming stack arguments     |
- 	|                               |
--	+-------------------------------+ <-- arg_pointer_rtx
--	|                               |
-+	+-------------------------------+
-+	|                               | <-- incoming stack pointer (aligned)
- 	|  callee-allocated save area   |
- 	|  for register varargs         |
- 	|                               |
--	+-------------------------------+ <-- frame_pointer_rtx
-+	+-------------------------------+
-+	|  local variables              | <-- frame_pointer_rtx
- 	|                               |
--	|  local variables              |
--	|                               |
- 	+-------------------------------+
- 	|  padding0                     | \
- 	+-------------------------------+  |
--	|                               |  |
--	|                               |  |
- 	|  callee-saved registers       |  | frame.saved_regs_size
--	|                               |  |
- 	+-------------------------------+  |
- 	|  LR'                          |  |
- 	+-------------------------------+  |
--	|  FP'                          | /
--      P +-------------------------------+ <-- hard_frame_pointer_rtx
-+	|  FP'                          | / <- hard_frame_pointer_rtx (aligned)
-+        +-------------------------------+
- 	|  dynamic allocation           |
- 	+-------------------------------+
--	|                               |
--	|  outgoing stack arguments     |
--	|                               |
--	+-------------------------------+ <-- stack_pointer_rtx
-+	|  padding                      |
-+	+-------------------------------+
-+	|  outgoing stack arguments     | <-- arg_pointer
-+        |                               |
-+	+-------------------------------+
-+	|                               | <-- stack_pointer_rtx (aligned)
- 
--   Dynamic stack allocations such as alloca insert data at point P.
--   They decrease stack_pointer_rtx but leave frame_pointer_rtx and
--   hard_frame_pointer_rtx unchanged.  */
-+   Dynamic stack allocations via alloca() decrease stack_pointer_rtx
-+   but leave frame_pointer_rtx and hard_frame_pointer_rtx
-+   unchanged.  */
- 
- /* Generate the prologue instructions for entry into a function.
-    Establish the stack frame by decreasing the stack pointer with a
-@@ -2034,27 +2289,20 @@
- 
-      sub sp, sp, <final_adjustment_if_any>
-   */
--  HOST_WIDE_INT original_frame_size;	/* local variables + vararg save */
-   HOST_WIDE_INT frame_size, offset;
--  HOST_WIDE_INT fp_offset;		/* FP offset from SP */
-+  HOST_WIDE_INT fp_offset;		/* Offset from hard FP to SP.  */
-+  HOST_WIDE_INT hard_fp_offset;
-   rtx insn;
- 
-   aarch64_layout_frame ();
--  original_frame_size = get_frame_size () + cfun->machine->saved_varargs_size;
--  gcc_assert ((!cfun->machine->saved_varargs_size || cfun->stdarg)
--	      && (cfun->stdarg || !cfun->machine->saved_varargs_size));
--  frame_size = (original_frame_size + cfun->machine->frame.saved_regs_size
--		+ crtl->outgoing_args_size);
--  offset = frame_size = AARCH64_ROUND_UP (frame_size,
--					  STACK_BOUNDARY / BITS_PER_UNIT);
- 
-+  offset = frame_size = cfun->machine->frame.frame_size;
-+  hard_fp_offset = cfun->machine->frame.hard_fp_offset;
-+  fp_offset = frame_size - hard_fp_offset;
-+
-   if (flag_stack_usage_info)
-     current_function_static_stack_size = frame_size;
- 
--  fp_offset = (offset
--	       - original_frame_size
--	       - cfun->machine->frame.saved_regs_size);
--
-   /* Store pairs and load pairs have a range only -512 to 504.  */
-   if (offset >= 512)
-     {
-@@ -2064,7 +2312,7 @@
- 	 register area.  This will allow the pre-index write-back
- 	 store pair instructions to be used for setting up the stack frame
- 	 efficiently.  */
--      offset = original_frame_size + cfun->machine->frame.saved_regs_size;
-+      offset = hard_fp_offset;
-       if (offset >= 512)
- 	offset = cfun->machine->frame.saved_regs_size;
- 
-@@ -2075,29 +2323,29 @@
- 	{
- 	  rtx op0 = gen_rtx_REG (Pmode, IP0_REGNUM);
- 	  emit_move_insn (op0, GEN_INT (-frame_size));
--	  emit_insn (gen_add2_insn (stack_pointer_rtx, op0));
--	  aarch64_set_frame_expr (gen_rtx_SET
--				  (Pmode, stack_pointer_rtx,
--				   plus_constant (Pmode,
--						  stack_pointer_rtx,
--						  -frame_size)));
-+	  insn = emit_insn (gen_add2_insn (stack_pointer_rtx, op0));
-+
-+	  add_reg_note (insn, REG_CFA_ADJUST_CFA,
-+			gen_rtx_SET (VOIDmode, stack_pointer_rtx,
-+				     plus_constant (Pmode, stack_pointer_rtx,
-+						    -frame_size)));
-+	  RTX_FRAME_RELATED_P (insn) = 1;
- 	}
-       else if (frame_size > 0)
- 	{
--	  if ((frame_size & 0xfff) != frame_size)
-+	  int hi_ofs = frame_size & 0xfff000;
-+	  int lo_ofs = frame_size & 0x000fff;
-+
-+	  if (hi_ofs)
- 	    {
- 	      insn = emit_insn (gen_add2_insn
--				(stack_pointer_rtx,
--				 GEN_INT (-(frame_size
--					    & ~(HOST_WIDE_INT)0xfff))));
-+				(stack_pointer_rtx, GEN_INT (-hi_ofs)));
- 	      RTX_FRAME_RELATED_P (insn) = 1;
- 	    }
--	  if ((frame_size & 0xfff) != 0)
-+	  if (lo_ofs)
- 	    {
- 	      insn = emit_insn (gen_add2_insn
--				(stack_pointer_rtx,
--				 GEN_INT (-(frame_size
--					    & (HOST_WIDE_INT)0xfff))));
-+				(stack_pointer_rtx, GEN_INT (-lo_ofs)));
- 	      RTX_FRAME_RELATED_P (insn) = 1;
- 	    }
- 	}
-@@ -2107,12 +2355,11 @@
- 
-   if (offset > 0)
-     {
--      /* Save the frame pointer and lr if the frame pointer is needed
--	 first.  Make the frame pointer point to the location of the
--	 old frame pointer on the stack.  */
-+      bool skip_wb = false;
-+
-       if (frame_pointer_needed)
- 	{
--	  rtx mem_fp, mem_lr;
-+	  skip_wb = true;
- 
- 	  if (fp_offset)
- 	    {
-@@ -2119,67 +2366,52 @@
- 	      insn = emit_insn (gen_add2_insn (stack_pointer_rtx,
- 					       GEN_INT (-offset)));
- 	      RTX_FRAME_RELATED_P (insn) = 1;
--	      aarch64_set_frame_expr (gen_rtx_SET
--				      (Pmode, stack_pointer_rtx,
--				       gen_rtx_MINUS (Pmode,
--						      stack_pointer_rtx,
--						      GEN_INT (offset))));
--	      mem_fp = gen_frame_mem (DImode,
--				      plus_constant (Pmode,
--						     stack_pointer_rtx,
--						     fp_offset));
--	      mem_lr = gen_frame_mem (DImode,
--				      plus_constant (Pmode,
--						     stack_pointer_rtx,
--						     fp_offset
--						     + UNITS_PER_WORD));
--	      insn = emit_insn (gen_store_pairdi (mem_fp,
--						  hard_frame_pointer_rtx,
--						  mem_lr,
--						  gen_rtx_REG (DImode,
--							       LR_REGNUM)));
-+
-+	      aarch64_save_callee_saves (DImode, fp_offset, R29_REGNUM,
-+					 R30_REGNUM, false);
- 	    }
- 	  else
--	    {
--	      insn = emit_insn (gen_storewb_pairdi_di
--				(stack_pointer_rtx, stack_pointer_rtx,
--				 hard_frame_pointer_rtx,
--				 gen_rtx_REG (DImode, LR_REGNUM),
--				 GEN_INT (-offset),
--				 GEN_INT (GET_MODE_SIZE (DImode) - offset)));
--	      RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 2)) = 1;
--	    }
-+	    aarch64_pushwb_pair_reg (DImode, R29_REGNUM, R30_REGNUM, offset);
- 
--	  /* The first part of a frame-related parallel insn is always
--	     assumed to be relevant to the frame calculations;
--	     subsequent parts, are only frame-related if explicitly
--	     marked.  */
--	  RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
--	  RTX_FRAME_RELATED_P (insn) = 1;
--
- 	  /* Set up frame pointer to point to the location of the
- 	     previous frame pointer on the stack.  */
- 	  insn = emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
- 					   stack_pointer_rtx,
- 					   GEN_INT (fp_offset)));
--	  aarch64_set_frame_expr (gen_rtx_SET
--				  (Pmode, hard_frame_pointer_rtx,
--				   plus_constant (Pmode,
--						  stack_pointer_rtx,
--						  fp_offset)));
- 	  RTX_FRAME_RELATED_P (insn) = 1;
--	  insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
--					   hard_frame_pointer_rtx));
-+	  emit_insn (gen_stack_tie (stack_pointer_rtx, hard_frame_pointer_rtx));
- 	}
-       else
- 	{
--	  insn = emit_insn (gen_add2_insn (stack_pointer_rtx,
--					   GEN_INT (-offset)));
--	  RTX_FRAME_RELATED_P (insn) = 1;
-+	  unsigned reg1 = cfun->machine->frame.wb_candidate1;
-+	  unsigned reg2 = cfun->machine->frame.wb_candidate2;
-+
-+	  if (fp_offset
-+	      || reg1 == FIRST_PSEUDO_REGISTER
-+	      || (reg2 == FIRST_PSEUDO_REGISTER
-+		  && offset >= 256))
-+	    {
-+	      insn = emit_insn (gen_add2_insn (stack_pointer_rtx,
-+					       GEN_INT (-offset)));
-+	      RTX_FRAME_RELATED_P (insn) = 1;
-+	    }
-+	  else
-+	    {
-+	      enum machine_mode mode1 = (reg1 <= R30_REGNUM) ? DImode : DFmode;
-+
-+	      skip_wb = true;
-+
-+	      if (reg2 == FIRST_PSEUDO_REGISTER)
-+		aarch64_pushwb_single_reg (mode1, reg1, offset);
-+	      else
-+		aarch64_pushwb_pair_reg (mode1, reg1, reg2, offset);
-+	    }
- 	}
- 
--      aarch64_save_or_restore_callee_save_registers
--	(fp_offset + cfun->machine->frame.hardfp_offset, 0);
-+      aarch64_save_callee_saves (DImode, fp_offset, R0_REGNUM, R30_REGNUM,
-+				 skip_wb);
-+      aarch64_save_callee_saves (DFmode, fp_offset, V0_REGNUM, V31_REGNUM,
-+				 skip_wb);
-     }
- 
-   /* when offset >= 512,
-@@ -2200,28 +2432,21 @@
- void
- aarch64_expand_epilogue (bool for_sibcall)
- {
--  HOST_WIDE_INT original_frame_size, frame_size, offset;
-+  HOST_WIDE_INT frame_size, offset;
-   HOST_WIDE_INT fp_offset;
-+  HOST_WIDE_INT hard_fp_offset;
-   rtx insn;
--  rtx cfa_reg;
- 
-   aarch64_layout_frame ();
--  original_frame_size = get_frame_size () + cfun->machine->saved_varargs_size;
--  frame_size = (original_frame_size + cfun->machine->frame.saved_regs_size
--		+ crtl->outgoing_args_size);
--  offset = frame_size = AARCH64_ROUND_UP (frame_size,
--					  STACK_BOUNDARY / BITS_PER_UNIT);
- 
--  fp_offset = (offset
--	       - original_frame_size
--	       - cfun->machine->frame.saved_regs_size);
-+  offset = frame_size = cfun->machine->frame.frame_size;
-+  hard_fp_offset = cfun->machine->frame.hard_fp_offset;
-+  fp_offset = frame_size - hard_fp_offset;
- 
--  cfa_reg = frame_pointer_needed ? hard_frame_pointer_rtx : stack_pointer_rtx;
--
-   /* Store pairs and load pairs have a range only -512 to 504.  */
-   if (offset >= 512)
-     {
--      offset = original_frame_size + cfun->machine->frame.saved_regs_size;
-+      offset = hard_fp_offset;
-       if (offset >= 512)
- 	offset = cfun->machine->frame.saved_regs_size;
- 
-@@ -2247,72 +2472,51 @@
-     {
-       insn = emit_insn (gen_add3_insn (stack_pointer_rtx,
- 				       hard_frame_pointer_rtx,
--				       GEN_INT (- fp_offset)));
--      RTX_FRAME_RELATED_P (insn) = 1;
--      /* As SP is set to (FP - fp_offset), according to the rules in
--	 dwarf2cfi.c:dwarf2out_frame_debug_expr, CFA should be calculated
--	 from the value of SP from now on.  */
--      cfa_reg = stack_pointer_rtx;
-+				       GEN_INT (0)));
-+      offset = offset - fp_offset;
-     }
- 
--  aarch64_save_or_restore_callee_save_registers
--    (fp_offset + cfun->machine->frame.hardfp_offset, 1);
--
--  /* Restore the frame pointer and lr if the frame pointer is needed.  */
-   if (offset > 0)
-     {
-+      unsigned reg1 = cfun->machine->frame.wb_candidate1;
-+      unsigned reg2 = cfun->machine->frame.wb_candidate2;
-+      bool skip_wb = true;
-+      rtx cfi_ops = NULL;
-+
-       if (frame_pointer_needed)
-+	fp_offset = 0;
-+      else if (fp_offset
-+	       || reg1 == FIRST_PSEUDO_REGISTER
-+	       || (reg2 == FIRST_PSEUDO_REGISTER
-+		   && offset >= 256))
-+	skip_wb = false;
-+
-+      aarch64_restore_callee_saves (DImode, fp_offset, R0_REGNUM, R30_REGNUM,
-+				    skip_wb, &cfi_ops);
-+      aarch64_restore_callee_saves (DFmode, fp_offset, V0_REGNUM, V31_REGNUM,
-+				    skip_wb, &cfi_ops);
-+
-+      if (skip_wb)
- 	{
--	  rtx mem_fp, mem_lr;
-+	  enum machine_mode mode1 = (reg1 <= R30_REGNUM) ? DImode : DFmode;
-+	  rtx rreg1 = gen_rtx_REG (mode1, reg1);
- 
--	  if (fp_offset)
-+	  cfi_ops = alloc_reg_note (REG_CFA_RESTORE, rreg1, cfi_ops);
-+	  if (reg2 == FIRST_PSEUDO_REGISTER)
- 	    {
--	      mem_fp = gen_frame_mem (DImode,
--				      plus_constant (Pmode,
--						     stack_pointer_rtx,
--						     fp_offset));
--	      mem_lr = gen_frame_mem (DImode,
--				      plus_constant (Pmode,
--						     stack_pointer_rtx,
--						     fp_offset
--						     + UNITS_PER_WORD));
--	      insn = emit_insn (gen_load_pairdi (hard_frame_pointer_rtx,
--						 mem_fp,
--						 gen_rtx_REG (DImode,
--							      LR_REGNUM),
--						 mem_lr));
-+	      rtx mem = plus_constant (Pmode, stack_pointer_rtx, offset);
-+	      mem = gen_rtx_POST_MODIFY (Pmode, stack_pointer_rtx, mem);
-+	      mem = gen_rtx_MEM (mode1, mem);
-+	      insn = emit_move_insn (rreg1, mem);
- 	    }
- 	  else
- 	    {
--	      insn = emit_insn (gen_loadwb_pairdi_di
--				(stack_pointer_rtx,
--				 stack_pointer_rtx,
--				 hard_frame_pointer_rtx,
--				 gen_rtx_REG (DImode, LR_REGNUM),
--				 GEN_INT (offset),
--				 GEN_INT (GET_MODE_SIZE (DImode) + offset)));
--	      RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 2)) = 1;
--	      add_reg_note (insn, REG_CFA_ADJUST_CFA,
--			    (gen_rtx_SET (Pmode, stack_pointer_rtx,
--					  plus_constant (Pmode, cfa_reg,
--							 offset))));
--	    }
-+	      rtx rreg2 = gen_rtx_REG (mode1, reg2);
- 
--	  /* The first part of a frame-related parallel insn
--	     is always assumed to be relevant to the frame
--	     calculations; subsequent parts, are only
--	     frame-related if explicitly marked.  */
--	  RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
--	  RTX_FRAME_RELATED_P (insn) = 1;
--	  add_reg_note (insn, REG_CFA_RESTORE, hard_frame_pointer_rtx);
--	  add_reg_note (insn, REG_CFA_RESTORE,
--			gen_rtx_REG (DImode, LR_REGNUM));
--
--	  if (fp_offset)
--	    {
--	      insn = emit_insn (gen_add2_insn (stack_pointer_rtx,
--					       GEN_INT (offset)));
--	      RTX_FRAME_RELATED_P (insn) = 1;
-+	      cfi_ops = alloc_reg_note (REG_CFA_RESTORE, rreg2, cfi_ops);
-+	      insn = emit_insn (aarch64_gen_loadwb_pair
-+				(mode1, stack_pointer_rtx, rreg1,
-+				 rreg2, offset));
- 	    }
- 	}
-       else
-@@ -2319,79 +2523,57 @@
- 	{
- 	  insn = emit_insn (gen_add2_insn (stack_pointer_rtx,
- 					   GEN_INT (offset)));
--	  RTX_FRAME_RELATED_P (insn) = 1;
- 	}
--    }
- 
--  /* Stack adjustment for exception handler.  */
--  if (crtl->calls_eh_return)
--    {
--      /* We need to unwind the stack by the offset computed by
--	 EH_RETURN_STACKADJ_RTX.  However, at this point the CFA is
--	 based on SP.  Ideally we would update the SP and define the
--	 CFA along the lines of:
--
--	 SP = SP + EH_RETURN_STACKADJ_RTX
--	 (regnote CFA = SP - EH_RETURN_STACKADJ_RTX)
--
--	 However the dwarf emitter only understands a constant
--	 register offset.
--
--	 The solution chosen here is to use the otherwise unused IP0
--	 as a temporary register to hold the current SP value.  The
--	 CFA is described using IP0 then SP is modified.  */
--
--      rtx ip0 = gen_rtx_REG (DImode, IP0_REGNUM);
--
--      insn = emit_move_insn (ip0, stack_pointer_rtx);
--      add_reg_note (insn, REG_CFA_DEF_CFA, ip0);
-+      /* Reset the CFA to be SP + FRAME_SIZE.  */
-+      rtx new_cfa = stack_pointer_rtx;
-+      if (frame_size > 0)
-+	new_cfa = plus_constant (Pmode, new_cfa, frame_size);
-+      cfi_ops = alloc_reg_note (REG_CFA_DEF_CFA, new_cfa, cfi_ops);
-+      REG_NOTES (insn) = cfi_ops;
-       RTX_FRAME_RELATED_P (insn) = 1;
--
--      emit_insn (gen_add2_insn (stack_pointer_rtx, EH_RETURN_STACKADJ_RTX));
--
--      /* Ensure the assignment to IP0 does not get optimized away.  */
--      emit_use (ip0);
-     }
- 
--  if (frame_size > -1)
-+  if (frame_size > 0)
-     {
-       if (frame_size >= 0x1000000)
- 	{
- 	  rtx op0 = gen_rtx_REG (Pmode, IP0_REGNUM);
- 	  emit_move_insn (op0, GEN_INT (frame_size));
--	  emit_insn (gen_add2_insn (stack_pointer_rtx, op0));
--	  aarch64_set_frame_expr (gen_rtx_SET
--				  (Pmode, stack_pointer_rtx,
--				   plus_constant (Pmode,
--						  stack_pointer_rtx,
--						  frame_size)));
-+	  insn = emit_insn (gen_add2_insn (stack_pointer_rtx, op0));
- 	}
--      else if (frame_size > 0)
-+      else
- 	{
--	  if ((frame_size & 0xfff) != 0)
-+          int hi_ofs = frame_size & 0xfff000;
-+          int lo_ofs = frame_size & 0x000fff;
-+
-+	  if (hi_ofs && lo_ofs)
- 	    {
- 	      insn = emit_insn (gen_add2_insn
--				(stack_pointer_rtx,
--				 GEN_INT ((frame_size
--					   & (HOST_WIDE_INT) 0xfff))));
-+				(stack_pointer_rtx, GEN_INT (hi_ofs)));
- 	      RTX_FRAME_RELATED_P (insn) = 1;
-+	      frame_size = lo_ofs;
- 	    }
--	  if ((frame_size & 0xfff) != frame_size)
--	    {
--	      insn = emit_insn (gen_add2_insn
--				(stack_pointer_rtx,
--				 GEN_INT ((frame_size
--					   & ~ (HOST_WIDE_INT) 0xfff))));
--	      RTX_FRAME_RELATED_P (insn) = 1;
--	    }
-+	  insn = emit_insn (gen_add2_insn
-+			    (stack_pointer_rtx, GEN_INT (frame_size)));
- 	}
- 
--        aarch64_set_frame_expr (gen_rtx_SET (Pmode, stack_pointer_rtx,
--					     plus_constant (Pmode,
--							    stack_pointer_rtx,
--							    offset)));
-+      /* Reset the CFA to be SP + 0.  */
-+      add_reg_note (insn, REG_CFA_DEF_CFA, stack_pointer_rtx);
-+      RTX_FRAME_RELATED_P (insn) = 1;
-     }
- 
-+  /* Stack adjustment for exception handler.  */
-+  if (crtl->calls_eh_return)
-+    {
-+      /* We need to unwind the stack by the offset computed by
-+	 EH_RETURN_STACKADJ_RTX.  We have already reset the CFA
-+	 to be SP; letting the CFA move during this adjustment
-+	 is just as correct as retaining the CFA from the body
-+	 of the function.  Therefore, do nothing special.  */
-+      emit_insn (gen_add2_insn (stack_pointer_rtx, EH_RETURN_STACKADJ_RTX));
-+    }
-+
-   emit_use (gen_rtx_REG (DImode, LR_REGNUM));
-   if (!for_sibcall)
-     emit_jump_insn (ret_rtx);
-@@ -2403,17 +2585,13 @@
- rtx
- aarch64_final_eh_return_addr (void)
- {
--  HOST_WIDE_INT original_frame_size, frame_size, offset, fp_offset;
-+  HOST_WIDE_INT fp_offset;
-+
-   aarch64_layout_frame ();
--  original_frame_size = get_frame_size () + cfun->machine->saved_varargs_size;
--  frame_size = (original_frame_size + cfun->machine->frame.saved_regs_size
--		+ crtl->outgoing_args_size);
--  offset = frame_size = AARCH64_ROUND_UP (frame_size,
--					  STACK_BOUNDARY / BITS_PER_UNIT);
--  fp_offset = offset
--    - original_frame_size
--    - cfun->machine->frame.saved_regs_size;
- 
-+  fp_offset = cfun->machine->frame.frame_size
-+	      - cfun->machine->frame.hard_fp_offset;
-+
-   if (cfun->machine->frame.reg_offset[LR_REGNUM] < 0)
-     return gen_rtx_REG (DImode, LR_REGNUM);
- 
-@@ -2449,12 +2627,22 @@
- 				       - 2 * UNITS_PER_WORD));
- }
- 
--/* Output code to build up a constant in a register.  */
--static void
--aarch64_build_constant (int regnum, HOST_WIDE_INT val)
-+/* Possibly output code to build up a constant in a register.  For
-+   the benefit of the costs infrastructure, returns the number of
-+   instructions which would be emitted.  GENERATE inhibits or
-+   enables code generation.  */
-+
-+static int
-+aarch64_build_constant (int regnum, HOST_WIDE_INT val, bool generate)
- {
-+  int insns = 0;
-+
-   if (aarch64_bitmask_imm (val, DImode))
--    emit_move_insn (gen_rtx_REG (Pmode, regnum), GEN_INT (val));
-+    {
-+      if (generate)
-+	emit_move_insn (gen_rtx_REG (Pmode, regnum), GEN_INT (val));
-+      insns = 1;
-+    }
-   else
-     {
-       int i;
-@@ -2485,15 +2673,19 @@
- 	 the same.  */
-       if (ncount < zcount)
- 	{
--	  emit_move_insn (gen_rtx_REG (Pmode, regnum),
--			  GEN_INT (val | ~(HOST_WIDE_INT) 0xffff));
-+	  if (generate)
-+	    emit_move_insn (gen_rtx_REG (Pmode, regnum),
-+			    GEN_INT (val | ~(HOST_WIDE_INT) 0xffff));
- 	  tval = 0xffff;
-+	  insns++;
- 	}
-       else
- 	{
--	  emit_move_insn (gen_rtx_REG (Pmode, regnum),
--			  GEN_INT (val & 0xffff));
-+	  if (generate)
-+	    emit_move_insn (gen_rtx_REG (Pmode, regnum),
-+			    GEN_INT (val & 0xffff));
- 	  tval = 0;
-+	  insns++;
- 	}
- 
-       val >>= 16;
-@@ -2501,11 +2693,17 @@
-       for (i = 16; i < 64; i += 16)
- 	{
- 	  if ((val & 0xffff) != tval)
--	    emit_insn (gen_insv_immdi (gen_rtx_REG (Pmode, regnum),
--				       GEN_INT (i), GEN_INT (val & 0xffff)));
-+	    {
-+	      if (generate)
-+		emit_insn (gen_insv_immdi (gen_rtx_REG (Pmode, regnum),
-+					   GEN_INT (i),
-+					   GEN_INT (val & 0xffff)));
-+	      insns++;
-+	    }
- 	  val >>= 16;
- 	}
-     }
-+  return insns;
- }
- 
- static void
-@@ -2520,7 +2718,7 @@
- 
-   if (mdelta >= 4096 * 4096)
-     {
--      aarch64_build_constant (scratchreg, delta);
-+      (void) aarch64_build_constant (scratchreg, delta, true);
-       emit_insn (gen_add3_insn (this_rtx, this_rtx, scratch_rtx));
-     }
-   else if (mdelta > 0)
-@@ -2594,7 +2792,7 @@
- 	  addr = plus_constant (Pmode, temp0, vcall_offset);
-       else
- 	{
--	  aarch64_build_constant (IP1_REGNUM, vcall_offset);
-+	  (void) aarch64_build_constant (IP1_REGNUM, vcall_offset, true);
- 	  addr = gen_rtx_PLUS (Pmode, temp0, temp1);
- 	}
- 
-@@ -3011,8 +3209,8 @@
-   return false;
- }
- 
--static inline bool
--offset_7bit_signed_scaled_p (enum machine_mode mode, HOST_WIDE_INT offset)
-+bool
-+aarch64_offset_7bit_signed_scaled_p (enum machine_mode mode, HOST_WIDE_INT offset)
- {
-   return (offset >= -64 * GET_MODE_SIZE (mode)
- 	  && offset < 64 * GET_MODE_SIZE (mode)
-@@ -3046,11 +3244,11 @@
-   enum rtx_code code = GET_CODE (x);
-   rtx op0, op1;
-   bool allow_reg_index_p =
--    outer_code != PARALLEL && GET_MODE_SIZE(mode) != 16;
--
-+    outer_code != PARALLEL && (GET_MODE_SIZE (mode) != 16
-+			       || aarch64_vector_mode_supported_p (mode));
-   /* Don't support anything other than POST_INC or REG addressing for
-      AdvSIMD.  */
--  if (aarch64_vector_mode_p (mode)
-+  if (aarch64_vect_struct_mode_p (mode)
-       && (code != POST_INC && code != REG))
-     return false;
- 
-@@ -3066,6 +3264,21 @@
-     case PLUS:
-       op0 = XEXP (x, 0);
-       op1 = XEXP (x, 1);
-+
-+      if (! strict_p
-+	  && REG_P (op0)
-+	  && (op0 == virtual_stack_vars_rtx
-+	      || op0 == frame_pointer_rtx
-+	      || op0 == arg_pointer_rtx)
-+	  && CONST_INT_P (op1))
-+	{
-+	  info->type = ADDRESS_REG_IMM;
-+	  info->base = op0;
-+	  info->offset = op1;
-+
-+	  return true;
-+	}
-+
-       if (GET_MODE_SIZE (mode) != 0
- 	  && CONST_INT_P (op1)
- 	  && aarch64_base_register_rtx_p (op0, strict_p))
-@@ -3084,12 +3297,12 @@
- 	     We conservatively require an offset representable in either mode.
- 	   */
- 	  if (mode == TImode || mode == TFmode)
--	    return (offset_7bit_signed_scaled_p (mode, offset)
-+	    return (aarch64_offset_7bit_signed_scaled_p (mode, offset)
- 		    && offset_9bit_signed_unscaled_p (mode, offset));
- 
- 	  if (outer_code == PARALLEL)
- 	    return ((GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)
--		    && offset_7bit_signed_scaled_p (mode, offset));
-+		    && aarch64_offset_7bit_signed_scaled_p (mode, offset));
- 	  else
- 	    return (offset_9bit_signed_unscaled_p (mode, offset)
- 		    || offset_12bit_unsigned_scaled_p (mode, offset));
-@@ -3144,12 +3357,12 @@
- 	     We conservatively require an offset representable in either mode.
- 	   */
- 	  if (mode == TImode || mode == TFmode)
--	    return (offset_7bit_signed_scaled_p (mode, offset)
-+	    return (aarch64_offset_7bit_signed_scaled_p (mode, offset)
- 		    && offset_9bit_signed_unscaled_p (mode, offset));
- 
- 	  if (outer_code == PARALLEL)
- 	    return ((GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)
--		    && offset_7bit_signed_scaled_p (mode, offset));
-+		    && aarch64_offset_7bit_signed_scaled_p (mode, offset));
- 	  else
- 	    return offset_9bit_signed_unscaled_p (mode, offset);
- 	}
-@@ -3333,7 +3546,7 @@
-      the comparison will have to be swapped when we emit the assembly
-      code.  */
-   if ((GET_MODE (x) == SImode || GET_MODE (x) == DImode)
--      && (GET_CODE (y) == REG || GET_CODE (y) == SUBREG)
-+      && (REG_P (y) || GET_CODE (y) == SUBREG)
-       && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
- 	  || GET_CODE (x) == LSHIFTRT
- 	  || GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND))
-@@ -3342,7 +3555,7 @@
-   /* Similarly for a negated operand, but we can only do this for
-      equalities.  */
-   if ((GET_MODE (x) == SImode || GET_MODE (x) == DImode)
--      && (GET_CODE (y) == REG || GET_CODE (y) == SUBREG)
-+      && (REG_P (y) || GET_CODE (y) == SUBREG)
-       && (code == EQ || code == NE)
-       && GET_CODE (x) == NEG)
-     return CC_Zmode;
-@@ -3359,7 +3572,7 @@
-   return CCmode;
- }
- 
--static unsigned
-+int
- aarch64_get_condition_code (rtx x)
- {
-   enum machine_mode mode = GET_MODE (XEXP (x, 0));
-@@ -3386,7 +3599,7 @@
- 	case UNLE: return AARCH64_LE;
- 	case UNGT: return AARCH64_HI;
- 	case UNGE: return AARCH64_PL;
--	default: gcc_unreachable ();
-+	default: return -1;
- 	}
-       break;
- 
-@@ -3403,7 +3616,7 @@
- 	case GTU: return AARCH64_HI;
- 	case LEU: return AARCH64_LS;
- 	case LTU: return AARCH64_CC;
--	default: gcc_unreachable ();
-+	default: return -1;
- 	}
-       break;
- 
-@@ -3422,7 +3635,7 @@
- 	case GTU: return AARCH64_CC;
- 	case LEU: return AARCH64_CS;
- 	case LTU: return AARCH64_HI;
--	default: gcc_unreachable ();
-+	default: return -1;
- 	}
-       break;
- 
-@@ -3433,7 +3646,7 @@
- 	case EQ: return AARCH64_EQ;
- 	case GE: return AARCH64_PL;
- 	case LT: return AARCH64_MI;
--	default: gcc_unreachable ();
-+	default: return -1;
- 	}
-       break;
- 
-@@ -3442,16 +3655,46 @@
- 	{
- 	case NE: return AARCH64_NE;
- 	case EQ: return AARCH64_EQ;
--	default: gcc_unreachable ();
-+	default: return -1;
- 	}
-       break;
- 
-     default:
--      gcc_unreachable ();
-+      return -1;
-       break;
-     }
- }
- 
-+bool
-+aarch64_const_vec_all_same_in_range_p (rtx x,
-+				  HOST_WIDE_INT minval,
-+				  HOST_WIDE_INT maxval)
-+{
-+  HOST_WIDE_INT firstval;
-+  int count, i;
-+
-+  if (GET_CODE (x) != CONST_VECTOR
-+      || GET_MODE_CLASS (GET_MODE (x)) != MODE_VECTOR_INT)
-+    return false;
-+
-+  firstval = INTVAL (CONST_VECTOR_ELT (x, 0));
-+  if (firstval < minval || firstval > maxval)
-+    return false;
-+
-+  count = CONST_VECTOR_NUNITS (x);
-+  for (i = 1; i < count; i++)
-+    if (INTVAL (CONST_VECTOR_ELT (x, i)) != firstval)
-+      return false;
-+
-+  return true;
-+}
-+
-+bool
-+aarch64_const_vec_all_same_int_p (rtx x, HOST_WIDE_INT val)
-+{
-+  return aarch64_const_vec_all_same_in_range_p (x, val, val);
-+}
-+
- static unsigned
- bit_count (unsigned HOST_WIDE_INT value)
- {
-@@ -3502,7 +3745,7 @@
-       {
- 	int n;
- 
--	if (GET_CODE (x) != CONST_INT
-+	if (!CONST_INT_P (x)
- 	    || (n = exact_log2 (INTVAL (x) & ~7)) <= 0)
- 	  {
- 	    output_operand_lossage ("invalid operand for '%%%c'", code);
-@@ -3532,7 +3775,7 @@
- 	int n;
- 
- 	/* Print N such that 2^N == X.  */
--	if (GET_CODE (x) != CONST_INT || (n = exact_log2 (INTVAL (x))) < 0)
-+	if (!CONST_INT_P (x) || (n = exact_log2 (INTVAL (x))) < 0)
- 	  {
- 	    output_operand_lossage ("invalid operand for '%%%c'", code);
- 	    return;
-@@ -3544,7 +3787,7 @@
- 
-     case 'P':
-       /* Print the number of non-zero bits in X (a const_int).  */
--      if (GET_CODE (x) != CONST_INT)
-+      if (!CONST_INT_P (x))
- 	{
- 	  output_operand_lossage ("invalid operand for '%%%c'", code);
- 	  return;
-@@ -3555,7 +3798,7 @@
- 
-     case 'H':
-       /* Print the higher numbered register of a pair (TImode) of regs.  */
--      if (GET_CODE (x) != REG || !GP_REGNUM_P (REGNO (x) + 1))
-+      if (!REG_P (x) || !GP_REGNUM_P (REGNO (x) + 1))
- 	{
- 	  output_operand_lossage ("invalid operand for '%%%c'", code);
- 	  return;
-@@ -3565,39 +3808,48 @@
-       break;
- 
-     case 'm':
--      /* Print a condition (eq, ne, etc).  */
-+      {
-+        int cond_code;
-+        /* Print a condition (eq, ne, etc).  */
- 
--      /* CONST_TRUE_RTX means always -- that's the default.  */
--      if (x == const_true_rtx)
--	return;
--
--      if (!COMPARISON_P (x))
--	{
--	  output_operand_lossage ("invalid operand for '%%%c'", code);
-+        /* CONST_TRUE_RTX means always -- that's the default.  */
-+        if (x == const_true_rtx)
- 	  return;
--	}
- 
--      fputs (aarch64_condition_codes[aarch64_get_condition_code (x)], f);
-+        if (!COMPARISON_P (x))
-+	  {
-+	    output_operand_lossage ("invalid operand for '%%%c'", code);
-+	    return;
-+	  }
-+
-+        cond_code = aarch64_get_condition_code (x);
-+        gcc_assert (cond_code >= 0);
-+        fputs (aarch64_condition_codes[cond_code], f);
-+      }
-       break;
- 
-     case 'M':
--      /* Print the inverse of a condition (eq <-> ne, etc).  */
-+      {
-+        int cond_code;
-+        /* Print the inverse of a condition (eq <-> ne, etc).  */
- 
--      /* CONST_TRUE_RTX means never -- that's the default.  */
--      if (x == const_true_rtx)
--	{
--	  fputs ("nv", f);
--	  return;
--	}
-+        /* CONST_TRUE_RTX means never -- that's the default.  */
-+        if (x == const_true_rtx)
-+	  {
-+	    fputs ("nv", f);
-+	    return;
-+	  }
- 
--      if (!COMPARISON_P (x))
--	{
--	  output_operand_lossage ("invalid operand for '%%%c'", code);
--	  return;
--	}
--
--      fputs (aarch64_condition_codes[AARCH64_INVERSE_CONDITION_CODE
--				  (aarch64_get_condition_code (x))], f);
-+        if (!COMPARISON_P (x))
-+	  {
-+	    output_operand_lossage ("invalid operand for '%%%c'", code);
-+	    return;
-+	  }
-+        cond_code = aarch64_get_condition_code (x);
-+        gcc_assert (cond_code >= 0);
-+        fputs (aarch64_condition_codes[AARCH64_INVERSE_CONDITION_CODE
-+                                       (cond_code)], f);
-+      }
-       break;
- 
-     case 'b':
-@@ -3629,7 +3881,7 @@
- 
-     case 'X':
-       /* Print bottom 16 bits of integer constant in hex.  */
--      if (GET_CODE (x) != CONST_INT)
-+      if (!CONST_INT_P (x))
- 	{
- 	  output_operand_lossage ("invalid operand for '%%%c'", code);
- 	  return;
-@@ -3694,9 +3946,10 @@
- 	case CONST_VECTOR:
- 	  if (GET_MODE_CLASS (GET_MODE (x)) == MODE_VECTOR_INT)
- 	    {
--	      gcc_assert (aarch64_const_vec_all_same_int_p (x,
--							    HOST_WIDE_INT_MIN,
--							    HOST_WIDE_INT_MAX));
-+	      gcc_assert (
-+		  aarch64_const_vec_all_same_in_range_p (x,
-+							 HOST_WIDE_INT_MIN,
-+							 HOST_WIDE_INT_MAX));
- 	      asm_fprintf (f, "%wd", INTVAL (CONST_VECTOR_ELT (x, 0)));
- 	    }
- 	  else if (aarch64_simd_imm_zero_p (x, GET_MODE (x)))
-@@ -3839,34 +4092,34 @@
- 	if (addr.offset == const0_rtx)
- 	  asm_fprintf (f, "[%s]", reg_names [REGNO (addr.base)]);
- 	else
--	  asm_fprintf (f, "[%s,%wd]", reg_names [REGNO (addr.base)],
-+	  asm_fprintf (f, "[%s, %wd]", reg_names [REGNO (addr.base)],
- 		       INTVAL (addr.offset));
- 	return;
- 
-       case ADDRESS_REG_REG:
- 	if (addr.shift == 0)
--	  asm_fprintf (f, "[%s,%s]", reg_names [REGNO (addr.base)],
-+	  asm_fprintf (f, "[%s, %s]", reg_names [REGNO (addr.base)],
- 		       reg_names [REGNO (addr.offset)]);
- 	else
--	  asm_fprintf (f, "[%s,%s,lsl %u]", reg_names [REGNO (addr.base)],
-+	  asm_fprintf (f, "[%s, %s, lsl %u]", reg_names [REGNO (addr.base)],
- 		       reg_names [REGNO (addr.offset)], addr.shift);
- 	return;
- 
-       case ADDRESS_REG_UXTW:
- 	if (addr.shift == 0)
--	  asm_fprintf (f, "[%s,w%d,uxtw]", reg_names [REGNO (addr.base)],
-+	  asm_fprintf (f, "[%s, w%d, uxtw]", reg_names [REGNO (addr.base)],
- 		       REGNO (addr.offset) - R0_REGNUM);
- 	else
--	  asm_fprintf (f, "[%s,w%d,uxtw %u]", reg_names [REGNO (addr.base)],
-+	  asm_fprintf (f, "[%s, w%d, uxtw %u]", reg_names [REGNO (addr.base)],
- 		       REGNO (addr.offset) - R0_REGNUM, addr.shift);
- 	return;
- 
-       case ADDRESS_REG_SXTW:
- 	if (addr.shift == 0)
--	  asm_fprintf (f, "[%s,w%d,sxtw]", reg_names [REGNO (addr.base)],
-+	  asm_fprintf (f, "[%s, w%d, sxtw]", reg_names [REGNO (addr.base)],
- 		       REGNO (addr.offset) - R0_REGNUM);
- 	else
--	  asm_fprintf (f, "[%s,w%d,sxtw %u]", reg_names [REGNO (addr.base)],
-+	  asm_fprintf (f, "[%s, w%d, sxtw %u]", reg_names [REGNO (addr.base)],
- 		       REGNO (addr.offset) - R0_REGNUM, addr.shift);
- 	return;
- 
-@@ -3874,27 +4127,27 @@
- 	switch (GET_CODE (x))
- 	  {
- 	  case PRE_INC:
--	    asm_fprintf (f, "[%s,%d]!", reg_names [REGNO (addr.base)], 
-+	    asm_fprintf (f, "[%s, %d]!", reg_names [REGNO (addr.base)],
- 			 GET_MODE_SIZE (aarch64_memory_reference_mode));
- 	    return;
- 	  case POST_INC:
--	    asm_fprintf (f, "[%s],%d", reg_names [REGNO (addr.base)],
-+	    asm_fprintf (f, "[%s], %d", reg_names [REGNO (addr.base)],
- 			 GET_MODE_SIZE (aarch64_memory_reference_mode));
- 	    return;
- 	  case PRE_DEC:
--	    asm_fprintf (f, "[%s,-%d]!", reg_names [REGNO (addr.base)],
-+	    asm_fprintf (f, "[%s, -%d]!", reg_names [REGNO (addr.base)],
- 			 GET_MODE_SIZE (aarch64_memory_reference_mode));
- 	    return;
- 	  case POST_DEC:
--	    asm_fprintf (f, "[%s],-%d", reg_names [REGNO (addr.base)],
-+	    asm_fprintf (f, "[%s], -%d", reg_names [REGNO (addr.base)],
- 			 GET_MODE_SIZE (aarch64_memory_reference_mode));
- 	    return;
- 	  case PRE_MODIFY:
--	    asm_fprintf (f, "[%s,%wd]!", reg_names [REGNO (addr.base)],
-+	    asm_fprintf (f, "[%s, %wd]!", reg_names [REGNO (addr.base)],
- 			 INTVAL (addr.offset));
- 	    return;
- 	  case POST_MODIFY:
--	    asm_fprintf (f, "[%s],%wd", reg_names [REGNO (addr.base)],
-+	    asm_fprintf (f, "[%s], %wd", reg_names [REGNO (addr.base)],
- 			 INTVAL (addr.offset));
- 	    return;
- 	  default:
-@@ -3903,7 +4156,7 @@
- 	break;
- 
-       case ADDRESS_LO_SUM:
--	asm_fprintf (f, "[%s,#:lo12:", reg_names [REGNO (addr.base)]);
-+	asm_fprintf (f, "[%s, #:lo12:", reg_names [REGNO (addr.base)]);
- 	output_addr_const (f, addr.offset);
- 	asm_fprintf (f, "]");
- 	return;
-@@ -3954,7 +4207,7 @@
- aarch64_regno_regclass (unsigned regno)
- {
-   if (GP_REGNUM_P (regno))
--    return CORE_REGS;
-+    return GENERAL_REGS;
- 
-   if (regno == SP_REGNUM)
-     return STACK_REG;
-@@ -3969,6 +4222,47 @@
-   return NO_REGS;
- }
- 
-+static rtx
-+aarch64_legitimize_address (rtx x, rtx /* orig_x  */, enum machine_mode mode)
-+{
-+  /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
-+     where mask is selected by alignment and size of the offset.
-+     We try to pick as large a range for the offset as possible to
-+     maximize the chance of a CSE.  However, for aligned addresses
-+     we limit the range to 4k so that structures with different sized
-+     elements are likely to use the same base.  */
-+
-+  if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
-+    {
-+      HOST_WIDE_INT offset = INTVAL (XEXP (x, 1));
-+      HOST_WIDE_INT base_offset;
-+
-+      /* Does it look like we'll need a load/store-pair operation?  */
-+      if (GET_MODE_SIZE (mode) > 16
-+	  || mode == TImode)
-+	base_offset = ((offset + 64 * GET_MODE_SIZE (mode))
-+		       & ~((128 * GET_MODE_SIZE (mode)) - 1));
-+      /* For offsets aren't a multiple of the access size, the limit is
-+	 -256...255.  */
-+      else if (offset & (GET_MODE_SIZE (mode) - 1))
-+	base_offset = (offset + 0x100) & ~0x1ff;
-+      else
-+	base_offset = offset & ~0xfff;
-+
-+      if (base_offset == 0)
-+	return x;
-+
-+      offset -= base_offset;
-+      rtx base_reg = gen_reg_rtx (Pmode);
-+      rtx val = force_operand (plus_constant (Pmode, XEXP (x, 0), base_offset),
-+			   NULL_RTX);
-+      emit_move_insn (base_reg, val);
-+      x = plus_constant (Pmode, base_reg, offset);
-+    }
-+
-+  return x;
-+}
-+
- /* Try a machine-dependent way of reloading an illegitimate address
-    operand.  If we find one, push the reload and return the new rtx.  */
- 
-@@ -3980,8 +4274,8 @@
- {
-   rtx x = *x_p;
- 
--  /* Do not allow mem (plus (reg, const)) if vector mode.  */
--  if (aarch64_vector_mode_p (mode)
-+  /* Do not allow mem (plus (reg, const)) if vector struct mode.  */
-+  if (aarch64_vect_struct_mode_p (mode)
-       && GET_CODE (x) == PLUS
-       && REG_P (XEXP (x, 0))
-       && CONST_INT_P (XEXP (x, 1)))
-@@ -4105,12 +4399,12 @@
-   /* A TFmode or TImode memory access should be handled via an FP_REGS
-      because AArch64 has richer addressing modes for LDR/STR instructions
-      than LDP/STP instructions.  */
--  if (!TARGET_GENERAL_REGS_ONLY && rclass == CORE_REGS
-+  if (!TARGET_GENERAL_REGS_ONLY && rclass == GENERAL_REGS
-       && GET_MODE_SIZE (mode) == 16 && MEM_P (x))
-     return FP_REGS;
- 
-   if (rclass == FP_REGS && (mode == TImode || mode == TFmode) && CONSTANT_P(x))
--      return CORE_REGS;
-+      return GENERAL_REGS;
- 
-   return NO_REGS;
- }
-@@ -4142,43 +4436,28 @@
- HOST_WIDE_INT
- aarch64_initial_elimination_offset (unsigned from, unsigned to)
- {
--  HOST_WIDE_INT frame_size;
--  HOST_WIDE_INT offset;
--
-   aarch64_layout_frame ();
--  frame_size = (get_frame_size () + cfun->machine->frame.saved_regs_size
--		+ crtl->outgoing_args_size
--		+ cfun->machine->saved_varargs_size);
- 
--   frame_size = AARCH64_ROUND_UP (frame_size, STACK_BOUNDARY / BITS_PER_UNIT);
--   offset = frame_size;
-+  if (to == HARD_FRAME_POINTER_REGNUM)
-+    {
-+      if (from == ARG_POINTER_REGNUM)
-+	return cfun->machine->frame.frame_size - crtl->outgoing_args_size;
- 
--   if (to == HARD_FRAME_POINTER_REGNUM)
--     {
--       if (from == ARG_POINTER_REGNUM)
--	 return offset - crtl->outgoing_args_size;
-+      if (from == FRAME_POINTER_REGNUM)
-+	return (cfun->machine->frame.hard_fp_offset
-+		- cfun->machine->frame.saved_varargs_size);
-+    }
- 
--       if (from == FRAME_POINTER_REGNUM)
--	 return cfun->machine->frame.saved_regs_size + get_frame_size ();
--     }
-+  if (to == STACK_POINTER_REGNUM)
-+    {
-+      if (from == FRAME_POINTER_REGNUM)
-+	  return (cfun->machine->frame.frame_size
-+		  - cfun->machine->frame.saved_varargs_size);
-+    }
- 
--   if (to == STACK_POINTER_REGNUM)
--     {
--       if (from == FRAME_POINTER_REGNUM)
--         {
--           HOST_WIDE_INT elim = crtl->outgoing_args_size
--                              + cfun->machine->frame.saved_regs_size
--                              + get_frame_size ()
--                              - cfun->machine->frame.fp_lr_offset;
--           elim = AARCH64_ROUND_UP (elim, STACK_BOUNDARY / BITS_PER_UNIT);
--           return elim;
--         }
--     }
--
--   return offset;
-+  return cfun->machine->frame.frame_size;
- }
- 
--
- /* Implement RETURN_ADDR_RTX.  We do not support moving back to a
-    previous frame.  */
- 
-@@ -4242,7 +4521,7 @@
- {
-   switch (regclass)
-     {
--    case CORE_REGS:
-+    case CALLER_SAVE_REGS:
-     case POINTER_REGS:
-     case GENERAL_REGS:
-     case ALL_REGS:
-@@ -4443,9 +4722,13 @@
- {
-   rtx op = x;
- 
-+  /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
-+     we can convert both to ROR during final output.  */
-   if ((GET_CODE (op) == ASHIFT
-        || GET_CODE (op) == ASHIFTRT
--       || GET_CODE (op) == LSHIFTRT)
-+       || GET_CODE (op) == LSHIFTRT
-+       || GET_CODE (op) == ROTATERT
-+       || GET_CODE (op) == ROTATE)
-       && CONST_INT_P (XEXP (op, 1)))
-     return XEXP (op, 0);
- 
-@@ -4457,12 +4740,12 @@
-   return x;
- }
- 
--/* Helper function for rtx cost calculation.  Strip a shift or extend
-+/* Helper function for rtx cost calculation.  Strip an extend
-    expression from X.  Returns the inner operand if successful, or the
-    original expression on failure.  We deal with a number of possible
-    canonicalization variations here.  */
- static rtx
--aarch64_strip_shift_or_extend (rtx x)
-+aarch64_strip_extend (rtx x)
- {
-   rtx op = x;
- 
-@@ -4469,6 +4752,7 @@
-   /* Zero and sign extraction of a widened value.  */
-   if ((GET_CODE (op) == ZERO_EXTRACT || GET_CODE (op) == SIGN_EXTRACT)
-       && XEXP (op, 2) == const0_rtx
-+      && GET_CODE (XEXP (op, 0)) == MULT
-       && aarch64_is_extend_from_extract (GET_MODE (op), XEXP (XEXP (op, 0), 1),
- 					 XEXP (op, 1)))
-     return XEXP (XEXP (op, 0), 0);
-@@ -4497,9 +4781,335 @@
-   if (op != x)
-     return op;
- 
--  return aarch64_strip_shift (x);
-+  return x;
- }
- 
-+/* Helper function for rtx cost calculation.  Calculate the cost of
-+   a MULT, which may be part of a multiply-accumulate rtx.  Return
-+   the calculated cost of the expression, recursing manually in to
-+   operands where needed.  */
-+
-+static int
-+aarch64_rtx_mult_cost (rtx x, int code, int outer, bool speed)
-+{
-+  rtx op0, op1;
-+  const struct cpu_cost_table *extra_cost
-+    = aarch64_tune_params->insn_extra_cost;
-+  int cost = 0;
-+  bool maybe_fma = (outer == PLUS || outer == MINUS);
-+  enum machine_mode mode = GET_MODE (x);
-+
-+  gcc_checking_assert (code == MULT);
-+
-+  op0 = XEXP (x, 0);
-+  op1 = XEXP (x, 1);
-+
-+  if (VECTOR_MODE_P (mode))
-+    mode = GET_MODE_INNER (mode);
-+
-+  /* Integer multiply/fma.  */
-+  if (GET_MODE_CLASS (mode) == MODE_INT)
-+    {
-+      /* The multiply will be canonicalized as a shift, cost it as such.  */
-+      if (CONST_INT_P (op1)
-+	  && exact_log2 (INTVAL (op1)) > 0)
-+	{
-+	  if (speed)
-+	    {
-+	      if (maybe_fma)
-+		/* ADD (shifted register).  */
-+		cost += extra_cost->alu.arith_shift;
-+	      else
-+		/* LSL (immediate).  */
-+		cost += extra_cost->alu.shift;
-+	    }
-+
-+	  cost += rtx_cost (op0, GET_CODE (op0), 0, speed);
-+
-+	  return cost;
-+	}
-+
-+      /* Integer multiplies or FMAs have zero/sign extending variants.  */
-+      if ((GET_CODE (op0) == ZERO_EXTEND
-+	   && GET_CODE (op1) == ZERO_EXTEND)
-+	  || (GET_CODE (op0) == SIGN_EXTEND
-+	      && GET_CODE (op1) == SIGN_EXTEND))
-+	{
-+	  cost += rtx_cost (XEXP (op0, 0), MULT, 0, speed)
-+		  + rtx_cost (XEXP (op1, 0), MULT, 1, speed);
-+
-+	  if (speed)
-+	    {
-+	      if (maybe_fma)
-+		/* MADD/SMADDL/UMADDL.  */
-+		cost += extra_cost->mult[0].extend_add;
-+	      else
-+		/* MUL/SMULL/UMULL.  */
-+		cost += extra_cost->mult[0].extend;
-+	    }
-+
-+	  return cost;
-+	}
-+
-+      /* This is either an integer multiply or an FMA.  In both cases
-+	 we want to recurse and cost the operands.  */
-+      cost += rtx_cost (op0, MULT, 0, speed)
-+	      + rtx_cost (op1, MULT, 1, speed);
-+
-+      if (speed)
-+	{
-+	  if (maybe_fma)
-+	    /* MADD.  */
-+	    cost += extra_cost->mult[mode == DImode].add;
-+	  else
-+	    /* MUL.  */
-+	    cost += extra_cost->mult[mode == DImode].simple;
-+	}
-+
-+      return cost;
-+    }
-+  else
-+    {
-+      if (speed)
-+	{
-+	  /* Floating-point FMA/FMUL can also support negations of the
-+	     operands.  */
-+	  if (GET_CODE (op0) == NEG)
-+	    op0 = XEXP (op0, 0);
-+	  if (GET_CODE (op1) == NEG)
-+	    op1 = XEXP (op1, 0);
-+
-+	  if (maybe_fma)
-+	    /* FMADD/FNMADD/FNMSUB/FMSUB.  */
-+	    cost += extra_cost->fp[mode == DFmode].fma;
-+	  else
-+	    /* FMUL/FNMUL.  */
-+	    cost += extra_cost->fp[mode == DFmode].mult;
-+	}
-+
-+      cost += rtx_cost (op0, MULT, 0, speed)
-+	      + rtx_cost (op1, MULT, 1, speed);
-+      return cost;
-+    }
-+}
-+
-+static int
-+aarch64_address_cost (rtx x,
-+		      enum machine_mode mode,
-+		      addr_space_t as ATTRIBUTE_UNUSED,
-+		      bool speed)
-+{
-+  enum rtx_code c = GET_CODE (x);
-+  const struct cpu_addrcost_table *addr_cost = aarch64_tune_params->addr_cost;
-+  struct aarch64_address_info info;
-+  int cost = 0;
-+  info.shift = 0;
-+
-+  if (!aarch64_classify_address (&info, x, mode, c, false))
-+    {
-+      if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF)
-+	{
-+	  /* This is a CONST or SYMBOL ref which will be split
-+	     in a different way depending on the code model in use.
-+	     Cost it through the generic infrastructure.  */
-+	  int cost_symbol_ref = rtx_cost (x, MEM, 1, speed);
-+	  /* Divide through by the cost of one instruction to
-+	     bring it to the same units as the address costs.  */
-+	  cost_symbol_ref /= COSTS_N_INSNS (1);
-+	  /* The cost is then the cost of preparing the address,
-+	     followed by an immediate (possibly 0) offset.  */
-+	  return cost_symbol_ref + addr_cost->imm_offset;
-+	}
-+      else
-+	{
-+	  /* This is most likely a jump table from a case
-+	     statement.  */
-+	  return addr_cost->register_offset;
-+	}
-+    }
-+
-+  switch (info.type)
-+    {
-+      case ADDRESS_LO_SUM:
-+      case ADDRESS_SYMBOLIC:
-+      case ADDRESS_REG_IMM:
-+	cost += addr_cost->imm_offset;
-+	break;
-+
-+      case ADDRESS_REG_WB:
-+	if (c == PRE_INC || c == PRE_DEC || c == PRE_MODIFY)
-+	  cost += addr_cost->pre_modify;
-+	else if (c == POST_INC || c == POST_DEC || c == POST_MODIFY)
-+	  cost += addr_cost->post_modify;
-+	else
-+	  gcc_unreachable ();
-+
-+	break;
-+
-+      case ADDRESS_REG_REG:
-+	cost += addr_cost->register_offset;
-+	break;
-+
-+      case ADDRESS_REG_UXTW:
-+      case ADDRESS_REG_SXTW:
-+	cost += addr_cost->register_extend;
-+	break;
-+
-+      default:
-+	gcc_unreachable ();
-+    }
-+
-+
-+  if (info.shift > 0)
-+    {
-+      /* For the sake of calculating the cost of the shifted register
-+	 component, we can treat same sized modes in the same way.  */
-+      switch (GET_MODE_BITSIZE (mode))
-+	{
-+	  case 16:
-+	    cost += addr_cost->addr_scale_costs.hi;
-+	    break;
-+
-+	  case 32:
-+	    cost += addr_cost->addr_scale_costs.si;
-+	    break;
-+
-+	  case 64:
-+	    cost += addr_cost->addr_scale_costs.di;
-+	    break;
-+
-+	  /* We can't tell, or this is a 128-bit vector.  */
-+	  default:
-+	    cost += addr_cost->addr_scale_costs.ti;
-+	    break;
-+	}
-+    }
-+
-+  return cost;
-+}
-+
-+/* Return true if the RTX X in mode MODE is a zero or sign extract
-+   usable in an ADD or SUB (extended register) instruction.  */
-+static bool
-+aarch64_rtx_arith_op_extract_p (rtx x, enum machine_mode mode)
-+{
-+  /* Catch add with a sign extract.
-+     This is add_<optab><mode>_multp2.  */
-+  if (GET_CODE (x) == SIGN_EXTRACT
-+      || GET_CODE (x) == ZERO_EXTRACT)
-+    {
-+      rtx op0 = XEXP (x, 0);
-+      rtx op1 = XEXP (x, 1);
-+      rtx op2 = XEXP (x, 2);
-+
-+      if (GET_CODE (op0) == MULT
-+	  && CONST_INT_P (op1)
-+	  && op2 == const0_rtx
-+	  && CONST_INT_P (XEXP (op0, 1))
-+	  && aarch64_is_extend_from_extract (mode,
-+					     XEXP (op0, 1),
-+					     op1))
-+	{
-+	  return true;
-+	}
-+    }
-+
-+  return false;
-+}
-+
-+static bool
-+aarch64_frint_unspec_p (unsigned int u)
-+{
-+  switch (u)
-+    {
-+      case UNSPEC_FRINTZ:
-+      case UNSPEC_FRINTP:
-+      case UNSPEC_FRINTM:
-+      case UNSPEC_FRINTA:
-+      case UNSPEC_FRINTN:
-+      case UNSPEC_FRINTX:
-+      case UNSPEC_FRINTI:
-+        return true;
-+
-+      default:
-+        return false;
-+    }
-+}
-+
-+/* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
-+   storing it in *COST.  Result is true if the total cost of the operation
-+   has now been calculated.  */
-+static bool
-+aarch64_if_then_else_costs (rtx op0, rtx op1, rtx op2, int *cost, bool speed)
-+{
-+  rtx inner;
-+  rtx comparator;
-+  enum rtx_code cmpcode;
-+
-+  if (COMPARISON_P (op0))
-+    {
-+      inner = XEXP (op0, 0);
-+      comparator = XEXP (op0, 1);
-+      cmpcode = GET_CODE (op0);
-+    }
-+  else
-+    {
-+      inner = op0;
-+      comparator = const0_rtx;
-+      cmpcode = NE;
-+    }
-+
-+  if (GET_CODE (op1) == PC || GET_CODE (op2) == PC)
-+    {
-+      /* Conditional branch.  */
-+      if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_CC)
-+	return true;
-+      else
-+	{
-+	  if (cmpcode == NE || cmpcode == EQ)
-+	    {
-+	      if (comparator == const0_rtx)
-+		{
-+		  /* TBZ/TBNZ/CBZ/CBNZ.  */
-+		  if (GET_CODE (inner) == ZERO_EXTRACT)
-+		    /* TBZ/TBNZ.  */
-+		    *cost += rtx_cost (XEXP (inner, 0), ZERO_EXTRACT,
-+			 	       0, speed);
-+		else
-+		  /* CBZ/CBNZ.  */
-+		  *cost += rtx_cost (inner, cmpcode, 0, speed);
-+
-+	        return true;
-+	      }
-+	    }
-+	  else if (cmpcode == LT || cmpcode == GE)
-+	    {
-+	      /* TBZ/TBNZ.  */
-+	      if (comparator == const0_rtx)
-+		return true;
-+	    }
-+	}
-+    }
-+  else if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_CC)
-+    {
-+      /* It's a conditional operation based on the status flags,
-+	 so it must be some flavor of CSEL.  */
-+
-+      /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL.  */
-+      if (GET_CODE (op1) == NEG
-+          || GET_CODE (op1) == NOT
-+          || (GET_CODE (op1) == PLUS && XEXP (op1, 1) == const1_rtx))
-+	op1 = XEXP (op1, 0);
-+
-+      *cost += rtx_cost (op1, IF_THEN_ELSE, 1, speed);
-+      *cost += rtx_cost (op2, IF_THEN_ELSE, 2, speed);
-+      return true;
-+    }
-+
-+  /* We don't know what this is, cost all operands.  */
-+  return false;
-+}
-+
- /* Calculate the cost of calculating X, storing it in *COST.  Result
-    is true if the total cost of the operation has now been calculated.  */
- static bool
-@@ -4506,13 +5116,31 @@
- aarch64_rtx_costs (rtx x, int code, int outer ATTRIBUTE_UNUSED,
- 		   int param ATTRIBUTE_UNUSED, int *cost, bool speed)
- {
--  rtx op0, op1;
-+  rtx op0, op1, op2;
-   const struct cpu_cost_table *extra_cost
-     = aarch64_tune_params->insn_extra_cost;
-+  enum machine_mode mode = GET_MODE (x);
- 
-+  /* By default, assume that everything has equivalent cost to the
-+     cheapest instruction.  Any additional costs are applied as a delta
-+     above this default.  */
-+  *cost = COSTS_N_INSNS (1);
-+
-+  /* TODO: The cost infrastructure currently does not handle
-+     vector operations.  Assume that all vector operations
-+     are equally expensive.  */
-+  if (VECTOR_MODE_P (mode))
-+    {
-+      if (speed)
-+	*cost += extra_cost->vect.alu;
-+      return true;
-+    }
-+
-   switch (code)
-     {
-     case SET:
-+      /* The cost depends entirely on the operands to SET.  */
-+      *cost = 0;
-       op0 = SET_DEST (x);
-       op1 = SET_SRC (x);
- 
-@@ -4520,52 +5148,194 @@
- 	{
- 	case MEM:
- 	  if (speed)
--	    *cost += extra_cost->ldst.store;
-+	    {
-+	      rtx address = XEXP (op0, 0);
-+	      if (GET_MODE_CLASS (mode) == MODE_INT)
-+		*cost += extra_cost->ldst.store;
-+	      else if (mode == SFmode)
-+		*cost += extra_cost->ldst.storef;
-+	      else if (mode == DFmode)
-+		*cost += extra_cost->ldst.stored;
- 
--	  if (op1 != const0_rtx)
--	    *cost += rtx_cost (op1, SET, 1, speed);
-+	      *cost +=
-+		COSTS_N_INSNS (aarch64_address_cost (address, mode,
-+						     0, speed));
-+	    }
-+
-+	  *cost += rtx_cost (op1, SET, 1, speed);
- 	  return true;
- 
- 	case SUBREG:
- 	  if (! REG_P (SUBREG_REG (op0)))
- 	    *cost += rtx_cost (SUBREG_REG (op0), SET, 0, speed);
-+
- 	  /* Fall through.  */
- 	case REG:
--	  /* Cost is just the cost of the RHS of the set.  */
--	  *cost += rtx_cost (op1, SET, 1, true);
-+	  /* const0_rtx is in general free, but we will use an
-+	     instruction to set a register to 0.  */
-+          if (REG_P (op1) || op1 == const0_rtx)
-+            {
-+              /* The cost is 1 per register copied.  */
-+              int n_minus_1 = (GET_MODE_SIZE (GET_MODE (op0)) - 1)
-+			      / UNITS_PER_WORD;
-+              *cost = COSTS_N_INSNS (n_minus_1 + 1);
-+            }
-+          else
-+	    /* Cost is just the cost of the RHS of the set.  */
-+	    *cost += rtx_cost (op1, SET, 1, speed);
- 	  return true;
- 
--	case ZERO_EXTRACT:  /* Bit-field insertion.  */
-+	case ZERO_EXTRACT:
- 	case SIGN_EXTRACT:
--	  /* Strip any redundant widening of the RHS to meet the width of
--	     the target.  */
-+	  /* Bit-field insertion.  Strip any redundant widening of
-+	     the RHS to meet the width of the target.  */
- 	  if (GET_CODE (op1) == SUBREG)
- 	    op1 = SUBREG_REG (op1);
- 	  if ((GET_CODE (op1) == ZERO_EXTEND
- 	       || GET_CODE (op1) == SIGN_EXTEND)
--	      && GET_CODE (XEXP (op0, 1)) == CONST_INT
-+	      && CONST_INT_P (XEXP (op0, 1))
- 	      && (GET_MODE_BITSIZE (GET_MODE (XEXP (op1, 0)))
- 		  >= INTVAL (XEXP (op0, 1))))
- 	    op1 = XEXP (op1, 0);
--	  *cost += rtx_cost (op1, SET, 1, speed);
-+
-+          if (CONST_INT_P (op1))
-+            {
-+              /* MOV immediate is assumed to always be cheap.  */
-+              *cost = COSTS_N_INSNS (1);
-+            }
-+          else
-+            {
-+              /* BFM.  */
-+	      if (speed)
-+		*cost += extra_cost->alu.bfi;
-+              *cost += rtx_cost (op1, (enum rtx_code) code, 1, speed);
-+            }
-+
- 	  return true;
- 
- 	default:
--	  break;
-+	  /* We can't make sense of this, assume default cost.  */
-+          *cost = COSTS_N_INSNS (1);
-+	  return false;
- 	}
-       return false;
- 
-+    case CONST_INT:
-+      /* If an instruction can incorporate a constant within the
-+	 instruction, the instruction's expression avoids calling
-+	 rtx_cost() on the constant.  If rtx_cost() is called on a
-+	 constant, then it is usually because the constant must be
-+	 moved into a register by one or more instructions.
-+
-+	 The exception is constant 0, which can be expressed
-+	 as XZR/WZR and is therefore free.  The exception to this is
-+	 if we have (set (reg) (const0_rtx)) in which case we must cost
-+	 the move.  However, we can catch that when we cost the SET, so
-+	 we don't need to consider that here.  */
-+      if (x == const0_rtx)
-+	*cost = 0;
-+      else
-+	{
-+	  /* To an approximation, building any other constant is
-+	     proportionally expensive to the number of instructions
-+	     required to build that constant.  This is true whether we
-+	     are compiling for SPEED or otherwise.  */
-+	  *cost = COSTS_N_INSNS (aarch64_internal_mov_immediate
-+				 (NULL_RTX, x, false, mode));
-+	}
-+      return true;
-+
-+    case CONST_DOUBLE:
-+      if (speed)
-+	{
-+	  /* mov[df,sf]_aarch64.  */
-+	  if (aarch64_float_const_representable_p (x))
-+	    /* FMOV (scalar immediate).  */
-+	    *cost += extra_cost->fp[mode == DFmode].fpconst;
-+	  else if (!aarch64_float_const_zero_rtx_p (x))
-+	    {
-+	      /* This will be a load from memory.  */
-+	      if (mode == DFmode)
-+		*cost += extra_cost->ldst.loadd;
-+	      else
-+		*cost += extra_cost->ldst.loadf;
-+	    }
-+	  else
-+	    /* Otherwise this is +0.0.  We get this using MOVI d0, #0
-+	       or MOV v0.s[0], wzr - neither of which are modeled by the
-+	       cost tables.  Just use the default cost.  */
-+	    {
-+	    }
-+	}
-+
-+      return true;
-+
-     case MEM:
-       if (speed)
--	*cost += extra_cost->ldst.load;
-+	{
-+	  /* For loads we want the base cost of a load, plus an
-+	     approximation for the additional cost of the addressing
-+	     mode.  */
-+	  rtx address = XEXP (x, 0);
-+	  if (GET_MODE_CLASS (mode) == MODE_INT)
-+	    *cost += extra_cost->ldst.load;
-+	  else if (mode == SFmode)
-+	    *cost += extra_cost->ldst.loadf;
-+	  else if (mode == DFmode)
-+	    *cost += extra_cost->ldst.loadd;
- 
-+	  *cost +=
-+		COSTS_N_INSNS (aarch64_address_cost (address, mode,
-+						     0, speed));
-+	}
-+
-       return true;
- 
-     case NEG:
--      op0 = CONST0_RTX (GET_MODE (x));
--      op1 = XEXP (x, 0);
--      goto cost_minus;
-+      op0 = XEXP (x, 0);
- 
-+      if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
-+       {
-+          if (GET_RTX_CLASS (GET_CODE (op0)) == RTX_COMPARE
-+              || GET_RTX_CLASS (GET_CODE (op0)) == RTX_COMM_COMPARE)
-+            {
-+              /* CSETM.  */
-+              *cost += rtx_cost (XEXP (op0, 0), NEG, 0, speed);
-+              return true;
-+            }
-+
-+	  /* Cost this as SUB wzr, X.  */
-+          op0 = CONST0_RTX (GET_MODE (x));
-+          op1 = XEXP (x, 0);
-+          goto cost_minus;
-+        }
-+
-+      if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
-+        {
-+          /* Support (neg(fma...)) as a single instruction only if
-+             sign of zeros is unimportant.  This matches the decision
-+             making in aarch64.md.  */
-+          if (GET_CODE (op0) == FMA && !HONOR_SIGNED_ZEROS (GET_MODE (op0)))
-+            {
-+	      /* FNMADD.  */
-+              *cost = rtx_cost (op0, NEG, 0, speed);
-+              return true;
-+            }
-+	  if (speed)
-+	    /* FNEG.  */
-+	    *cost += extra_cost->fp[mode == DFmode].neg;
-+          return false;
-+        }
-+
-+      return false;
-+
-+    case CLRSB:
-+    case CLZ:
-+      if (speed)
-+        *cost += extra_cost->alu.clz;
-+
-+      return false;
-+
-     case COMPARE:
-       op0 = XEXP (x, 0);
-       op1 = XEXP (x, 1);
-@@ -4577,96 +5347,228 @@
- 	  goto cost_logic;
- 	}
- 
--      /* Comparisons can work if the order is swapped.
--	 Canonicalization puts the more complex operation first, but
--	 we want it in op1.  */
--      if (! (REG_P (op0)
--	     || (GET_CODE (op0) == SUBREG && REG_P (SUBREG_REG (op0)))))
--	{
--	  op0 = XEXP (x, 1);
--	  op1 = XEXP (x, 0);
--	}
--      goto cost_minus;
-+      if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
-+        {
-+          /* TODO: A write to the CC flags possibly costs extra, this
-+	     needs encoding in the cost tables.  */
- 
-+          /* CC_ZESWPmode supports zero extend for free.  */
-+          if (GET_MODE (x) == CC_ZESWPmode && GET_CODE (op0) == ZERO_EXTEND)
-+            op0 = XEXP (op0, 0);
-+
-+          /* ANDS.  */
-+          if (GET_CODE (op0) == AND)
-+            {
-+              x = op0;
-+              goto cost_logic;
-+            }
-+
-+          if (GET_CODE (op0) == PLUS)
-+            {
-+	      /* ADDS (and CMN alias).  */
-+              x = op0;
-+              goto cost_plus;
-+            }
-+
-+          if (GET_CODE (op0) == MINUS)
-+            {
-+	      /* SUBS.  */
-+              x = op0;
-+              goto cost_minus;
-+            }
-+
-+          if (GET_CODE (op1) == NEG)
-+            {
-+	      /* CMN.  */
-+	      if (speed)
-+		*cost += extra_cost->alu.arith;
-+
-+              *cost += rtx_cost (op0, COMPARE, 0, speed);
-+	      *cost += rtx_cost (XEXP (op1, 0), NEG, 1, speed);
-+              return true;
-+            }
-+
-+          /* CMP.
-+
-+	     Compare can freely swap the order of operands, and
-+             canonicalization puts the more complex operation first.
-+             But the integer MINUS logic expects the shift/extend
-+             operation in op1.  */
-+          if (! (REG_P (op0)
-+                 || (GET_CODE (op0) == SUBREG && REG_P (SUBREG_REG (op0)))))
-+          {
-+            op0 = XEXP (x, 1);
-+            op1 = XEXP (x, 0);
-+          }
-+          goto cost_minus;
-+        }
-+
-+      if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_FLOAT)
-+        {
-+	  /* FCMP.  */
-+	  if (speed)
-+	    *cost += extra_cost->fp[mode == DFmode].compare;
-+
-+          if (CONST_DOUBLE_P (op1) && aarch64_float_const_zero_rtx_p (op1))
-+            {
-+              /* FCMP supports constant 0.0 for no extra cost. */
-+              return true;
-+            }
-+          return false;
-+        }
-+
-+      return false;
-+
-     case MINUS:
--      op0 = XEXP (x, 0);
--      op1 = XEXP (x, 1);
-+      {
-+	op0 = XEXP (x, 0);
-+	op1 = XEXP (x, 1);
- 
--    cost_minus:
--      if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT
--	  || (GET_MODE_CLASS (GET_MODE (x)) == MODE_CC
--	      && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT))
--	{
--	  if (op0 != const0_rtx)
-+cost_minus:
-+	/* Detect valid immediates.  */
-+	if ((GET_MODE_CLASS (mode) == MODE_INT
-+	     || (GET_MODE_CLASS (mode) == MODE_CC
-+		 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT))
-+	    && CONST_INT_P (op1)
-+	    && aarch64_uimm12_shift (INTVAL (op1)))
-+	  {
- 	    *cost += rtx_cost (op0, MINUS, 0, speed);
- 
--	  if (CONST_INT_P (op1))
--	    {
--	      if (!aarch64_uimm12_shift (INTVAL (op1)))
--		*cost += rtx_cost (op1, MINUS, 1, speed);
--	    }
--	  else
--	    {
--	      op1 = aarch64_strip_shift_or_extend (op1);
--	      *cost += rtx_cost (op1, MINUS, 1, speed);
--	    }
--	  return true;
--	}
-+	    if (speed)
-+	      /* SUB(S) (immediate).  */
-+	      *cost += extra_cost->alu.arith;
-+	    return true;
- 
--      return false;
-+	  }
- 
-+	/* Look for SUB (extended register).  */
-+        if (aarch64_rtx_arith_op_extract_p (op1, mode))
-+	  {
-+	    if (speed)
-+	      *cost += extra_cost->alu.arith_shift;
-+
-+	    *cost += rtx_cost (XEXP (XEXP (op1, 0), 0),
-+			       (enum rtx_code) GET_CODE (op1),
-+			       0, speed);
-+	    return true;
-+	  }
-+
-+	rtx new_op1 = aarch64_strip_extend (op1);
-+
-+	/* Cost this as an FMA-alike operation.  */
-+	if ((GET_CODE (new_op1) == MULT
-+	     || GET_CODE (new_op1) == ASHIFT)
-+	    && code != COMPARE)
-+	  {
-+	    *cost += aarch64_rtx_mult_cost (new_op1, MULT,
-+					    (enum rtx_code) code,
-+					    speed);
-+	    *cost += rtx_cost (op0, MINUS, 0, speed);
-+	    return true;
-+	  }
-+
-+	*cost += rtx_cost (new_op1, MINUS, 1, speed);
-+
-+	if (speed)
-+	  {
-+	    if (GET_MODE_CLASS (mode) == MODE_INT)
-+	      /* SUB(S).  */
-+	      *cost += extra_cost->alu.arith;
-+	    else if (GET_MODE_CLASS (mode) == MODE_FLOAT)
-+	      /* FSUB.  */
-+	      *cost += extra_cost->fp[mode == DFmode].addsub;
-+	  }
-+	return true;
-+      }
-+
-     case PLUS:
--      op0 = XEXP (x, 0);
--      op1 = XEXP (x, 1);
-+      {
-+	rtx new_op0;
- 
--      if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
--	{
--	  if (CONST_INT_P (op1) && aarch64_uimm12_shift (INTVAL (op1)))
--	    {
--	      *cost += rtx_cost (op0, PLUS, 0, speed);
--	    }
--	  else
--	    {
--	      rtx new_op0 = aarch64_strip_shift_or_extend (op0);
-+	op0 = XEXP (x, 0);
-+	op1 = XEXP (x, 1);
- 
--	      if (new_op0 == op0
--		  && GET_CODE (op0) == MULT)
--		{
--		  if ((GET_CODE (XEXP (op0, 0)) == ZERO_EXTEND
--		       && GET_CODE (XEXP (op0, 1)) == ZERO_EXTEND)
--		      || (GET_CODE (XEXP (op0, 0)) == SIGN_EXTEND
--			  && GET_CODE (XEXP (op0, 1)) == SIGN_EXTEND))
--		    {
--		      *cost += (rtx_cost (XEXP (XEXP (op0, 0), 0), MULT, 0,
--					  speed)
--				+ rtx_cost (XEXP (XEXP (op0, 1), 0), MULT, 1,
--					    speed)
--				+ rtx_cost (op1, PLUS, 1, speed));
--		      if (speed)
--			*cost +=
--			  extra_cost->mult[GET_MODE (x) == DImode].extend_add;
--		      return true;
--		    }
-+cost_plus:
-+	if (GET_RTX_CLASS (GET_CODE (op0)) == RTX_COMPARE
-+	    || GET_RTX_CLASS (GET_CODE (op0)) == RTX_COMM_COMPARE)
-+	  {
-+	    /* CSINC.  */
-+	    *cost += rtx_cost (XEXP (op0, 0), PLUS, 0, speed);
-+	    *cost += rtx_cost (op1, PLUS, 1, speed);
-+	    return true;
-+	  }
- 
--		  *cost += (rtx_cost (XEXP (op0, 0), MULT, 0, speed)
--			    + rtx_cost (XEXP (op0, 1), MULT, 1, speed)
--			    + rtx_cost (op1, PLUS, 1, speed));
-+	if (GET_MODE_CLASS (mode) == MODE_INT
-+	    && CONST_INT_P (op1)
-+	    && aarch64_uimm12_shift (INTVAL (op1)))
-+	  {
-+	    *cost += rtx_cost (op0, PLUS, 0, speed);
- 
--		  if (speed)
--		    *cost += extra_cost->mult[GET_MODE (x) == DImode].add;
-+	    if (speed)
-+	      /* ADD (immediate).  */
-+	      *cost += extra_cost->alu.arith;
-+	    return true;
-+	  }
- 
--		  return true;
--		}
-+	/* Look for ADD (extended register).  */
-+        if (aarch64_rtx_arith_op_extract_p (op0, mode))
-+	  {
-+	    if (speed)
-+	      *cost += extra_cost->alu.arith_shift;
- 
--	      *cost += (rtx_cost (new_op0, PLUS, 0, speed)
--			+ rtx_cost (op1, PLUS, 1, speed));
--	    }
--	  return true;
--	}
-+	    *cost += rtx_cost (XEXP (XEXP (op0, 0), 0),
-+			       (enum rtx_code) GET_CODE (op0),
-+			       0, speed);
-+	    return true;
-+	  }
- 
-+	/* Strip any extend, leave shifts behind as we will
-+	   cost them through mult_cost.  */
-+	new_op0 = aarch64_strip_extend (op0);
-+
-+	if (GET_CODE (new_op0) == MULT
-+	    || GET_CODE (new_op0) == ASHIFT)
-+	  {
-+	    *cost += aarch64_rtx_mult_cost (new_op0, MULT, PLUS,
-+					    speed);
-+	    *cost += rtx_cost (op1, PLUS, 1, speed);
-+	    return true;
-+	  }
-+
-+	*cost += (rtx_cost (new_op0, PLUS, 0, speed)
-+		  + rtx_cost (op1, PLUS, 1, speed));
-+
-+	if (speed)
-+	  {
-+	    if (GET_MODE_CLASS (mode) == MODE_INT)
-+	      /* ADD.  */
-+	      *cost += extra_cost->alu.arith;
-+	    else if (GET_MODE_CLASS (mode) == MODE_FLOAT)
-+	      /* FADD.  */
-+	      *cost += extra_cost->fp[mode == DFmode].addsub;
-+	  }
-+	return true;
-+      }
-+
-+    case BSWAP:
-+      *cost = COSTS_N_INSNS (1);
-+
-+      if (speed)
-+        *cost += extra_cost->alu.rev;
-+
-       return false;
- 
-     case IOR:
-+      if (aarch_rev16_p (x))
-+        {
-+          *cost = COSTS_N_INSNS (1);
-+
-+          if (speed)
-+            *cost += extra_cost->alu.rev;
-+
-+          return true;
-+        }
-+    /* Fall through.  */
-     case XOR:
-     case AND:
-     cost_logic:
-@@ -4673,117 +5575,252 @@
-       op0 = XEXP (x, 0);
-       op1 = XEXP (x, 1);
- 
-+      if (code == AND
-+          && GET_CODE (op0) == MULT
-+          && CONST_INT_P (XEXP (op0, 1))
-+          && CONST_INT_P (op1)
-+          && aarch64_uxt_size (exact_log2 (INTVAL (XEXP (op0, 1))),
-+                               INTVAL (op1)) != 0)
-+        {
-+          /* This is a UBFM/SBFM.  */
-+          *cost += rtx_cost (XEXP (op0, 0), ZERO_EXTRACT, 0, speed);
-+	  if (speed)
-+	    *cost += extra_cost->alu.bfx;
-+          return true;
-+        }
-+
-       if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
- 	{
-+	  /* We possibly get the immediate for free, this is not
-+	     modelled.  */
- 	  if (CONST_INT_P (op1)
- 	      && aarch64_bitmask_imm (INTVAL (op1), GET_MODE (x)))
- 	    {
--	      *cost += rtx_cost (op0, AND, 0, speed);
-+	      *cost += rtx_cost (op0, (enum rtx_code) code, 0, speed);
-+
-+	      if (speed)
-+		*cost += extra_cost->alu.logical;
-+
-+	      return true;
- 	    }
- 	  else
- 	    {
-+	      rtx new_op0 = op0;
-+
-+	      /* Handle ORN, EON, or BIC.  */
- 	      if (GET_CODE (op0) == NOT)
- 		op0 = XEXP (op0, 0);
--	      op0 = aarch64_strip_shift (op0);
--	      *cost += (rtx_cost (op0, AND, 0, speed)
--			+ rtx_cost (op1, AND, 1, speed));
-+
-+	      new_op0 = aarch64_strip_shift (op0);
-+
-+	      /* If we had a shift on op0 then this is a logical-shift-
-+		 by-register/immediate operation.  Otherwise, this is just
-+		 a logical operation.  */
-+	      if (speed)
-+		{
-+		  if (new_op0 != op0)
-+		    {
-+		      /* Shift by immediate.  */
-+		      if (CONST_INT_P (XEXP (op0, 1)))
-+			*cost += extra_cost->alu.log_shift;
-+		      else
-+			*cost += extra_cost->alu.log_shift_reg;
-+		    }
-+		  else
-+		    *cost += extra_cost->alu.logical;
-+		}
-+
-+	      /* In both cases we want to cost both operands.  */
-+	      *cost += rtx_cost (new_op0, (enum rtx_code) code, 0, speed)
-+		       + rtx_cost (op1, (enum rtx_code) code, 1, speed);
-+
-+	      return true;
- 	    }
--	  return true;
- 	}
-       return false;
- 
-+    case NOT:
-+      /* MVN.  */
-+      if (speed)
-+	*cost += extra_cost->alu.logical;
-+
-+      /* The logical instruction could have the shifted register form,
-+         but the cost is the same if the shift is processed as a separate
-+         instruction, so we don't bother with it here.  */
-+      return false;
-+
-     case ZERO_EXTEND:
--      if ((GET_MODE (x) == DImode
--	   && GET_MODE (XEXP (x, 0)) == SImode)
--	  || GET_CODE (XEXP (x, 0)) == MEM)
-+
-+      op0 = XEXP (x, 0);
-+      /* If a value is written in SI mode, then zero extended to DI
-+	 mode, the operation will in general be free as a write to
-+	 a 'w' register implicitly zeroes the upper bits of an 'x'
-+	 register.  However, if this is
-+
-+	   (set (reg) (zero_extend (reg)))
-+
-+	 we must cost the explicit register move.  */
-+      if (mode == DImode
-+	  && GET_MODE (op0) == SImode
-+	  && outer == SET)
- 	{
--	  *cost += rtx_cost (XEXP (x, 0), ZERO_EXTEND, 0, speed);
-+	  int op_cost = rtx_cost (XEXP (x, 0), ZERO_EXTEND, 0, speed);
-+
-+	  if (!op_cost && speed)
-+	    /* MOV.  */
-+	    *cost += extra_cost->alu.extend;
-+	  else
-+	    /* Free, the cost is that of the SI mode operation.  */
-+	    *cost = op_cost;
-+
- 	  return true;
- 	}
-+      else if (MEM_P (XEXP (x, 0)))
-+	{
-+	  /* All loads can zero extend to any size for free.  */
-+	  *cost = rtx_cost (XEXP (x, 0), ZERO_EXTEND, param, speed);
-+	  return true;
-+	}
-+
-+      /* UXTB/UXTH.  */
-+      if (speed)
-+	*cost += extra_cost->alu.extend;
-+
-       return false;
- 
-     case SIGN_EXTEND:
--      if (GET_CODE (XEXP (x, 0)) == MEM)
-+      if (MEM_P (XEXP (x, 0)))
- 	{
--	  *cost += rtx_cost (XEXP (x, 0), SIGN_EXTEND, 0, speed);
-+	  /* LDRSH.  */
-+	  if (speed)
-+	    {
-+	      rtx address = XEXP (XEXP (x, 0), 0);
-+	      *cost += extra_cost->ldst.load_sign_extend;
-+
-+	      *cost +=
-+		COSTS_N_INSNS (aarch64_address_cost (address, mode,
-+						     0, speed));
-+	    }
- 	  return true;
- 	}
-+
-+      if (speed)
-+	*cost += extra_cost->alu.extend;
-       return false;
- 
-+    case ASHIFT:
-+      op0 = XEXP (x, 0);
-+      op1 = XEXP (x, 1);
-+
-+      if (CONST_INT_P (op1))
-+        {
-+	  /* LSL (immediate), UBMF, UBFIZ and friends.  These are all
-+	     aliases.  */
-+	  if (speed)
-+	    *cost += extra_cost->alu.shift;
-+
-+          /* We can incorporate zero/sign extend for free.  */
-+          if (GET_CODE (op0) == ZERO_EXTEND
-+              || GET_CODE (op0) == SIGN_EXTEND)
-+            op0 = XEXP (op0, 0);
-+
-+          *cost += rtx_cost (op0, ASHIFT, 0, speed);
-+          return true;
-+        }
-+      else
-+        {
-+	  /* LSLV.  */
-+	  if (speed)
-+	    *cost += extra_cost->alu.shift_reg;
-+
-+	  return false;  /* All arguments need to be in registers.  */
-+        }
-+
-     case ROTATE:
--      if (!CONST_INT_P (XEXP (x, 1)))
--	*cost += COSTS_N_INSNS (2);
--      /* Fall through.  */
-     case ROTATERT:
-     case LSHIFTRT:
--    case ASHIFT:
-     case ASHIFTRT:
-+      op0 = XEXP (x, 0);
-+      op1 = XEXP (x, 1);
- 
--      /* Shifting by a register often takes an extra cycle.  */
--      if (speed && !CONST_INT_P (XEXP (x, 1)))
--	*cost += extra_cost->alu.arith_shift_reg;
-+      if (CONST_INT_P (op1))
-+	{
-+	  /* ASR (immediate) and friends.  */
-+	  if (speed)
-+	    *cost += extra_cost->alu.shift;
- 
--      *cost += rtx_cost (XEXP (x, 0), ASHIFT, 0, speed);
-+	  *cost += rtx_cost (op0, (enum rtx_code) code, 0, speed);
-+	  return true;
-+	}
-+      else
-+	{
-+
-+	  /* ASR (register) and friends.  */
-+	  if (speed)
-+	    *cost += extra_cost->alu.shift_reg;
-+
-+	  return false;  /* All arguments need to be in registers.  */
-+	}
-+
-+    case SYMBOL_REF:
-+
-+      if (aarch64_cmodel == AARCH64_CMODEL_LARGE)
-+	{
-+	  /* LDR.  */
-+	  if (speed)
-+	    *cost += extra_cost->ldst.load;
-+	}
-+      else if (aarch64_cmodel == AARCH64_CMODEL_SMALL
-+	       || aarch64_cmodel == AARCH64_CMODEL_SMALL_PIC)
-+	{
-+	  /* ADRP, followed by ADD.  */
-+	  *cost += COSTS_N_INSNS (1);
-+	  if (speed)
-+	    *cost += 2 * extra_cost->alu.arith;
-+	}
-+      else if (aarch64_cmodel == AARCH64_CMODEL_TINY
-+	       || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC)
-+	{
-+	  /* ADR.  */
-+	  if (speed)
-+	    *cost += extra_cost->alu.arith;
-+	}
-+
-+      if (flag_pic)
-+	{
-+	  /* One extra load instruction, after accessing the GOT.  */
-+	  *cost += COSTS_N_INSNS (1);
-+	  if (speed)
-+	    *cost += extra_cost->ldst.load;
-+	}
-       return true;
- 
-     case HIGH:
--      if (!CONSTANT_P (XEXP (x, 0)))
--	*cost += rtx_cost (XEXP (x, 0), HIGH, 0, speed);
--      return true;
--
-     case LO_SUM:
--      if (!CONSTANT_P (XEXP (x, 1)))
--	*cost += rtx_cost (XEXP (x, 1), LO_SUM, 1, speed);
--      *cost += rtx_cost (XEXP (x, 0), LO_SUM, 0, speed);
-+      /* ADRP/ADD (immediate).  */
-+      if (speed)
-+	*cost += extra_cost->alu.arith;
-       return true;
- 
-     case ZERO_EXTRACT:
-     case SIGN_EXTRACT:
--      *cost += rtx_cost (XEXP (x, 0), ZERO_EXTRACT, 0, speed);
-+      /* UBFX/SBFX.  */
-+      if (speed)
-+	*cost += extra_cost->alu.bfx;
-+
-+      /* We can trust that the immediates used will be correct (there
-+	 are no by-register forms), so we need only cost op0.  */
-+      *cost += rtx_cost (XEXP (x, 0), (enum rtx_code) code, 0, speed);
-       return true;
- 
-     case MULT:
--      op0 = XEXP (x, 0);
--      op1 = XEXP (x, 1);
-+      *cost += aarch64_rtx_mult_cost (x, MULT, 0, speed);
-+      /* aarch64_rtx_mult_cost always handles recursion to its
-+	 operands.  */
-+      return true;
- 
--      *cost = COSTS_N_INSNS (1);
--      if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
--	{
--	  if (CONST_INT_P (op1)
--	      && exact_log2 (INTVAL (op1)) > 0)
--	    {
--	      *cost += rtx_cost (op0, ASHIFT, 0, speed);
--	      return true;
--	    }
--
--	  if ((GET_CODE (op0) == ZERO_EXTEND
--	       && GET_CODE (op1) == ZERO_EXTEND)
--	      || (GET_CODE (op0) == SIGN_EXTEND
--		  && GET_CODE (op1) == SIGN_EXTEND))
--	    {
--	      *cost += (rtx_cost (XEXP (op0, 0), MULT, 0, speed)
--			+ rtx_cost (XEXP (op1, 0), MULT, 1, speed));
--	      if (speed)
--		*cost += extra_cost->mult[GET_MODE (x) == DImode].extend;
--	      return true;
--	    }
--
--	  if (speed)
--	    *cost += extra_cost->mult[GET_MODE (x) == DImode].simple;
--	}
--      else if (speed)
--	{
--	  if (GET_MODE (x) == DFmode)
--	    *cost += extra_cost->fp[1].mult;
--	  else if (GET_MODE (x) == SFmode)
--	    *cost += extra_cost->fp[0].mult;
--	}
--
--      return false;  /* All arguments need to be in registers.  */
--
-     case MOD:
-     case UMOD:
--      *cost = COSTS_N_INSNS (2);
-       if (speed)
- 	{
- 	  if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
-@@ -4800,53 +5837,222 @@
- 
-     case DIV:
-     case UDIV:
--      *cost = COSTS_N_INSNS (1);
-+    case SQRT:
-       if (speed)
- 	{
--	  if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
--	    *cost += extra_cost->mult[GET_MODE (x) == DImode].idiv;
--	  else if (GET_MODE (x) == DFmode)
--	    *cost += extra_cost->fp[1].div;
--	  else if (GET_MODE (x) == SFmode)
--	    *cost += extra_cost->fp[0].div;
-+	  if (GET_MODE_CLASS (mode) == MODE_INT)
-+	    /* There is no integer SQRT, so only DIV and UDIV can get
-+	       here.  */
-+	    *cost += extra_cost->mult[mode == DImode].idiv;
-+	  else
-+	    *cost += extra_cost->fp[mode == DFmode].div;
- 	}
-       return false;  /* All arguments need to be in registers.  */
- 
-+    case IF_THEN_ELSE:
-+      return aarch64_if_then_else_costs (XEXP (x, 0), XEXP (x, 1),
-+					 XEXP (x, 2), cost, speed);
-+
-+    case EQ:
-+    case NE:
-+    case GT:
-+    case GTU:
-+    case LT:
-+    case LTU:
-+    case GE:
-+    case GEU:
-+    case LE:
-+    case LEU:
-+
-+      return false; /* All arguments must be in registers.  */
-+
-+    case FMA:
-+      op0 = XEXP (x, 0);
-+      op1 = XEXP (x, 1);
-+      op2 = XEXP (x, 2);
-+
-+      if (speed)
-+	*cost += extra_cost->fp[mode == DFmode].fma;
-+
-+      /* FMSUB, FNMADD, and FNMSUB are free.  */
-+      if (GET_CODE (op0) == NEG)
-+        op0 = XEXP (op0, 0);
-+
-+      if (GET_CODE (op2) == NEG)
-+        op2 = XEXP (op2, 0);
-+
-+      /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
-+	 and the by-element operand as operand 0.  */
-+      if (GET_CODE (op1) == NEG)
-+        op1 = XEXP (op1, 0);
-+
-+      /* Catch vector-by-element operations.  The by-element operand can
-+	 either be (vec_duplicate (vec_select (x))) or just
-+	 (vec_select (x)), depending on whether we are multiplying by
-+	 a vector or a scalar.
-+
-+	 Canonicalization is not very good in these cases, FMA4 will put the
-+	 by-element operand as operand 0, FNMA4 will have it as operand 1.  */
-+      if (GET_CODE (op0) == VEC_DUPLICATE)
-+	op0 = XEXP (op0, 0);
-+      else if (GET_CODE (op1) == VEC_DUPLICATE)
-+	op1 = XEXP (op1, 0);
-+
-+      if (GET_CODE (op0) == VEC_SELECT)
-+	op0 = XEXP (op0, 0);
-+      else if (GET_CODE (op1) == VEC_SELECT)
-+	op1 = XEXP (op1, 0);
-+
-+      /* If the remaining parameters are not registers,
-+         get the cost to put them into registers.  */
-+      *cost += rtx_cost (op0, FMA, 0, speed);
-+      *cost += rtx_cost (op1, FMA, 1, speed);
-+      *cost += rtx_cost (op2, FMA, 2, speed);
-+      return true;
-+
-+    case FLOAT_EXTEND:
-+      if (speed)
-+	*cost += extra_cost->fp[mode == DFmode].widen;
-+      return false;
-+
-+    case FLOAT_TRUNCATE:
-+      if (speed)
-+	*cost += extra_cost->fp[mode == DFmode].narrow;
-+      return false;
-+
-+    case FIX:
-+    case UNSIGNED_FIX:
-+      x = XEXP (x, 0);
-+      /* Strip the rounding part.  They will all be implemented
-+         by the fcvt* family of instructions anyway.  */
-+      if (GET_CODE (x) == UNSPEC)
-+        {
-+          unsigned int uns_code = XINT (x, 1);
-+
-+          if (uns_code == UNSPEC_FRINTA
-+              || uns_code == UNSPEC_FRINTM
-+              || uns_code == UNSPEC_FRINTN
-+              || uns_code == UNSPEC_FRINTP
-+              || uns_code == UNSPEC_FRINTZ)
-+            x = XVECEXP (x, 0, 0);
-+        }
-+
-+      if (speed)
-+        *cost += extra_cost->fp[GET_MODE (x) == DFmode].toint;
-+
-+      *cost += rtx_cost (x, (enum rtx_code) code, 0, speed);
-+      return true;
-+
-+    case ABS:
-+      if (GET_MODE_CLASS (mode) == MODE_FLOAT)
-+	{
-+	  /* FABS and FNEG are analogous.  */
-+	  if (speed)
-+	    *cost += extra_cost->fp[mode == DFmode].neg;
-+	}
-+      else
-+	{
-+	  /* Integer ABS will either be split to
-+	     two arithmetic instructions, or will be an ABS
-+	     (scalar), which we don't model.  */
-+	  *cost = COSTS_N_INSNS (2);
-+	  if (speed)
-+	    *cost += 2 * extra_cost->alu.arith;
-+	}
-+      return false;
-+
-+    case SMAX:
-+    case SMIN:
-+      if (speed)
-+	{
-+	  /* FMAXNM/FMINNM/FMAX/FMIN.
-+	     TODO: This may not be accurate for all implementations, but
-+	     we do not model this in the cost tables.  */
-+	  *cost += extra_cost->fp[mode == DFmode].addsub;
-+	}
-+      return false;
-+
-+    case UNSPEC:
-+      /* The floating point round to integer frint* instructions.  */
-+      if (aarch64_frint_unspec_p (XINT (x, 1)))
-+        {
-+          if (speed)
-+            *cost += extra_cost->fp[mode == DFmode].roundint;
-+
-+          return false;
-+        }
-+
-+      if (XINT (x, 1) == UNSPEC_RBIT)
-+        {
-+          if (speed)
-+            *cost += extra_cost->alu.rev;
-+
-+          return false;
-+        }
-+      break;
-+
-+    case TRUNCATE:
-+
-+      /* Decompose <su>muldi3_highpart.  */
-+      if (/* (truncate:DI  */
-+	  mode == DImode
-+	  /*   (lshiftrt:TI  */
-+          && GET_MODE (XEXP (x, 0)) == TImode
-+          && GET_CODE (XEXP (x, 0)) == LSHIFTRT
-+	  /*      (mult:TI  */
-+          && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
-+	  /*        (ANY_EXTEND:TI (reg:DI))
-+	            (ANY_EXTEND:TI (reg:DI)))  */
-+          && ((GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
-+               && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == ZERO_EXTEND)
-+              || (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND
-+                  && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == SIGN_EXTEND))
-+          && GET_MODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0)) == DImode
-+          && GET_MODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 1), 0)) == DImode
-+	  /*     (const_int 64)  */
-+          && CONST_INT_P (XEXP (XEXP (x, 0), 1))
-+          && UINTVAL (XEXP (XEXP (x, 0), 1)) == 64)
-+        {
-+          /* UMULH/SMULH.  */
-+	  if (speed)
-+	    *cost += extra_cost->mult[mode == DImode].extend;
-+          *cost += rtx_cost (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
-+			     MULT, 0, speed);
-+          *cost += rtx_cost (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 1), 0),
-+			     MULT, 1, speed);
-+          return true;
-+        }
-+
-+      /* Fall through.  */
-     default:
-       break;
-     }
--  return false;
-+
-+  if (dump_file && (dump_flags & TDF_DETAILS))
-+    fprintf (dump_file,
-+      "\nFailed to cost RTX.  Assuming default cost.\n");
-+
-+  return true;
- }
- 
--static int
--aarch64_address_cost (rtx x ATTRIBUTE_UNUSED,
--		  enum machine_mode mode ATTRIBUTE_UNUSED,
--		  addr_space_t as ATTRIBUTE_UNUSED, bool speed ATTRIBUTE_UNUSED)
-+/* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
-+   calculated for X.  This cost is stored in *COST.  Returns true
-+   if the total cost of X was calculated.  */
-+static bool
-+aarch64_rtx_costs_wrapper (rtx x, int code, int outer,
-+		   int param, int *cost, bool speed)
- {
--  enum rtx_code c  = GET_CODE (x);
--  const struct cpu_addrcost_table *addr_cost = aarch64_tune_params->addr_cost;
-+  bool result = aarch64_rtx_costs (x, code, outer, param, cost, speed);
- 
--  if (c == PRE_INC || c == PRE_DEC || c == PRE_MODIFY)
--    return addr_cost->pre_modify;
--
--  if (c == POST_INC || c == POST_DEC || c == POST_MODIFY)
--    return addr_cost->post_modify;
--
--  if (c == PLUS)
-+  if (dump_file && (dump_flags & TDF_DETAILS))
-     {
--      if (GET_CODE (XEXP (x, 1)) == CONST_INT)
--	return addr_cost->imm_offset;
--      else if (GET_CODE (XEXP (x, 0)) == MULT
--	       || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
--	       || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
--	return addr_cost->register_extend;
--
--      return addr_cost->register_offset;
-+      print_rtl_single (dump_file, x);
-+      fprintf (dump_file, "\n%s cost: %d (%s)\n",
-+	       speed ? "Hot" : "Cold",
-+	       *cost, result ? "final" : "partial");
-     }
--  else if (c == MEM || c == LABEL_REF || c == SYMBOL_REF)
--    return addr_cost->imm_offset;
- 
--  return 0;
-+  return result;
- }
- 
- static int
-@@ -4858,6 +6064,13 @@
-   const struct cpu_regmove_cost *regmove_cost
-     = aarch64_tune_params->regmove_cost;
- 
-+  /* Caller save and pointer regs are equivalent to GENERAL_REGS.  */
-+  if (to == CALLER_SAVE_REGS || to == POINTER_REGS)
-+    to = GENERAL_REGS;
-+
-+  if (from == CALLER_SAVE_REGS || from == POINTER_REGS)
-+    from = GENERAL_REGS;
-+
-   /* Moving between GPR and stack cost is the same as GP2GP.  */
-   if ((from == GENERAL_REGS && to == STACK_REG)
-       || (to == GENERAL_REGS && from == STACK_REG))
-@@ -4880,7 +6093,7 @@
-      secondary reload.  A general register is used as a scratch to move
-      the upper DI value and the lower DI value is moved directly,
-      hence the cost is the sum of three moves. */
--  if (! TARGET_SIMD && GET_MODE_SIZE (mode) == 128)
-+  if (! TARGET_SIMD && GET_MODE_SIZE (mode) == 16)
-     return regmove_cost->GP2FP + regmove_cost->FP2GP + regmove_cost->FP2FP;
- 
-   return regmove_cost->FP2FP;
-@@ -5253,6 +6466,7 @@
-   aarch64_tune_flags = selected_tune->flags;
-   aarch64_tune = selected_tune->core;
-   aarch64_tune_params = selected_tune->tune;
-+  aarch64_architecture_version = selected_cpu->architecture_version;
- 
-   if (aarch64_fix_a53_err835769 == 2)
-     {
-@@ -5998,7 +7212,7 @@
- 
-   /* We don't save the size into *PRETEND_SIZE because we want to avoid
-      any complication of having crtl->args.pretend_args_size changed.  */
--  cfun->machine->saved_varargs_size
-+  cfun->machine->frame.saved_varargs_size
-     = (AARCH64_ROUND_UP (gr_saved * UNITS_PER_WORD,
- 		      STACK_BOUNDARY / BITS_PER_UNIT)
-        + vr_saved * UNITS_PER_VREG);
-@@ -6685,7 +7899,7 @@
-       unsigned HOST_WIDE_INT elpart;
-       unsigned int part, parts;
- 
--      if (GET_CODE (el) == CONST_INT)
-+      if (CONST_INT_P (el))
-         {
-           elpart = INTVAL (el);
-           parts = 1;
-@@ -6816,30 +8030,6 @@
- #undef CHECK
- }
- 
--static bool
--aarch64_const_vec_all_same_int_p (rtx x,
--				  HOST_WIDE_INT minval,
--				  HOST_WIDE_INT maxval)
--{
--  HOST_WIDE_INT firstval;
--  int count, i;
--
--  if (GET_CODE (x) != CONST_VECTOR
--      || GET_MODE_CLASS (GET_MODE (x)) != MODE_VECTOR_INT)
--    return false;
--
--  firstval = INTVAL (CONST_VECTOR_ELT (x, 0));
--  if (firstval < minval || firstval > maxval)
--    return false;
--
--  count = CONST_VECTOR_NUNITS (x);
--  for (i = 1; i < count; i++)
--    if (INTVAL (CONST_VECTOR_ELT (x, i)) != firstval)
--      return false;
--
--  return true;
--}
--
- /* Check of immediate shift constants are within range.  */
- bool
- aarch64_simd_shift_imm_p (rtx x, enum machine_mode mode, bool left)
-@@ -6846,9 +8036,9 @@
- {
-   int bit_width = GET_MODE_UNIT_SIZE (mode) * BITS_PER_UNIT;
-   if (left)
--    return aarch64_const_vec_all_same_int_p (x, 0, bit_width - 1);
-+    return aarch64_const_vec_all_same_in_range_p (x, 0, bit_width - 1);
-   else
--    return aarch64_const_vec_all_same_int_p (x, 1, bit_width);
-+    return aarch64_const_vec_all_same_in_range_p (x, 1, bit_width);
- }
- 
- /* Return true if X is a uniform vector where all elements
-@@ -6886,7 +8076,7 @@
-       && aarch64_valid_symref (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
-     return true;
- 
--  if (CONST_INT_P (x) && aarch64_move_imm (INTVAL (x), mode))
-+  if (CONST_INT_P (x))
-     return true;
- 
-   if (GET_CODE (x) == SYMBOL_REF && mode == DImode && CONSTANT_ADDRESS_P (x))
-@@ -6923,17 +8113,43 @@
-   return aarch64_simd_valid_immediate (op_v, vmode, false, NULL);
- }
- 
--/* Construct and return a PARALLEL RTX vector.  */
-+/* Construct and return a PARALLEL RTX vector with elements numbering the
-+   lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
-+   the vector - from the perspective of the architecture.  This does not
-+   line up with GCC's perspective on lane numbers, so we end up with
-+   different masks depending on our target endian-ness.  The diagram
-+   below may help.  We must draw the distinction when building masks
-+   which select one half of the vector.  An instruction selecting
-+   architectural low-lanes for a big-endian target, must be described using
-+   a mask selecting GCC high-lanes.
-+
-+                 Big-Endian             Little-Endian
-+
-+GCC             0   1   2   3           3   2   1   0
-+              | x | x | x | x |       | x | x | x | x |
-+Architecture    3   2   1   0           3   2   1   0
-+
-+Low Mask:         { 2, 3 }                { 0, 1 }
-+High Mask:        { 0, 1 }                { 2, 3 }
-+*/
-+
- rtx
- aarch64_simd_vect_par_cnst_half (enum machine_mode mode, bool high)
- {
-   int nunits = GET_MODE_NUNITS (mode);
-   rtvec v = rtvec_alloc (nunits / 2);
--  int base = high ? nunits / 2 : 0;
-+  int high_base = nunits / 2;
-+  int low_base = 0;
-+  int base;
-   rtx t1;
-   int i;
- 
--  for (i=0; i < nunits / 2; i++)
-+  if (BYTES_BIG_ENDIAN)
-+    base = high ? low_base : high_base;
-+  else
-+    base = high ? high_base : low_base;
-+
-+  for (i = 0; i < nunits / 2; i++)
-     RTVEC_ELT (v, i) = GEN_INT (base + i);
- 
-   t1 = gen_rtx_PARALLEL (mode, v);
-@@ -6940,6 +8156,38 @@
-   return t1;
- }
- 
-+/* Check OP for validity as a PARALLEL RTX vector with elements
-+   numbering the lanes of either the high (HIGH == TRUE) or low lanes,
-+   from the perspective of the architecture.  See the diagram above
-+   aarch64_simd_vect_par_cnst_half for more details.  */
-+
-+bool
-+aarch64_simd_check_vect_par_cnst_half (rtx op, enum machine_mode mode,
-+				       bool high)
-+{
-+  rtx ideal = aarch64_simd_vect_par_cnst_half (mode, high);
-+  HOST_WIDE_INT count_op = XVECLEN (op, 0);
-+  HOST_WIDE_INT count_ideal = XVECLEN (ideal, 0);
-+  int i = 0;
-+
-+  if (!VECTOR_MODE_P (mode))
-+    return false;
-+
-+  if (count_op != count_ideal)
-+    return false;
-+
-+  for (i = 0; i < count_ideal; i++)
-+    {
-+      rtx elt_op = XVECEXP (op, 0, i);
-+      rtx elt_ideal = XVECEXP (ideal, 0, i);
-+
-+      if (!CONST_INT_P (elt_op)
-+	  || INTVAL (elt_ideal) != INTVAL (elt_op))
-+	return false;
-+    }
-+  return true;
-+}
-+
- /* Bounds-check lanes.  Ensure OPERAND lies between LOW (inclusive) and
-    HIGH (exclusive).  */
- void
-@@ -6946,7 +8194,7 @@
- aarch64_simd_lane_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high)
- {
-   HOST_WIDE_INT lane;
--  gcc_assert (GET_CODE (operand) == CONST_INT);
-+  gcc_assert (CONST_INT_P (operand));
-   lane = INTVAL (operand);
- 
-   if (lane < low || lane >= high)
-@@ -6956,7 +8204,7 @@
- void
- aarch64_simd_const_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high)
- {
--  gcc_assert (GET_CODE (operand) == CONST_INT);
-+  gcc_assert (CONST_INT_P (operand));
-   HOST_WIDE_INT lane = INTVAL (operand);
- 
-   if (lane < low || lane >= high)
-@@ -6994,7 +8242,7 @@
- aarch64_simd_mem_operand_p (rtx op)
- {
-   return MEM_P (op) && (GET_CODE (XEXP (op, 0)) == POST_INC
--			|| GET_CODE (XEXP (op, 0)) == REG);
-+			|| REG_P (XEXP (op, 0)));
- }
- 
- /* Set up OPERANDS for a register copy from SRC to DEST, taking care
-@@ -7647,6 +8895,9 @@
-   if (!CONST_DOUBLE_P (x))
-     return false;
- 
-+  if (GET_MODE (x) == VOIDmode)
-+    return false;
-+
-   REAL_VALUE_FROM_CONST_DOUBLE (r, x);
- 
-   /* We cannot represent infinities, NaNs or +/-zero.  We won't
-@@ -7899,20 +9150,26 @@
- aarch64_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel)
- {
-   enum machine_mode vmode = GET_MODE (target);
--  unsigned int i, nelt = GET_MODE_NUNITS (vmode);
-+  unsigned int nelt = GET_MODE_NUNITS (vmode);
-   bool one_vector_p = rtx_equal_p (op0, op1);
--  rtx rmask[MAX_VECT_LEN], mask;
-+  rtx mask;
- 
--  gcc_checking_assert (!BYTES_BIG_ENDIAN);
--
-   /* The TBL instruction does not use a modulo index, so we must take care
-      of that ourselves.  */
--  mask = GEN_INT (one_vector_p ? nelt - 1 : 2 * nelt - 1);
--  for (i = 0; i < nelt; ++i)
--    rmask[i] = mask;
--  mask = gen_rtx_CONST_VECTOR (vmode, gen_rtvec_v (nelt, rmask));
-+  mask = aarch64_simd_gen_const_vector_dup (vmode,
-+      one_vector_p ? nelt - 1 : 2 * nelt - 1);
-   sel = expand_simple_binop (vmode, AND, sel, mask, NULL, 0, OPTAB_LIB_WIDEN);
- 
-+  /* For big-endian, we also need to reverse the index within the vector
-+     (but not which vector).  */
-+  if (BYTES_BIG_ENDIAN)
-+    {
-+      /* If one_vector_p, mask is a vector of (nelt - 1)'s already.  */
-+      if (!one_vector_p)
-+        mask = aarch64_simd_gen_const_vector_dup (vmode, nelt - 1);
-+      sel = expand_simple_binop (vmode, XOR, sel, mask,
-+				 NULL, 0, OPTAB_LIB_WIDEN);
-+    }
-   aarch64_expand_vec_perm_1 (target, op0, op1, sel);
- }
- 
-@@ -8171,7 +9428,145 @@
-   return true;
- }
- 
-+/* Recognize patterns for the EXT insn.  */
-+
- static bool
-+aarch64_evpc_ext (struct expand_vec_perm_d *d)
-+{
-+  unsigned int i, nelt = d->nelt;
-+  rtx (*gen) (rtx, rtx, rtx, rtx);
-+  rtx offset;
-+
-+  unsigned int location = d->perm[0]; /* Always < nelt.  */
-+
-+  /* Check if the extracted indices are increasing by one.  */
-+  for (i = 1; i < nelt; i++)
-+    {
-+      unsigned int required = location + i;
-+      if (d->one_vector_p)
-+        {
-+          /* We'll pass the same vector in twice, so allow indices to wrap.  */
-+	  required &= (nelt - 1);
-+	}
-+      if (d->perm[i] != required)
-+        return false;
-+    }
-+
-+  switch (d->vmode)
-+    {
-+    case V16QImode: gen = gen_aarch64_extv16qi; break;
-+    case V8QImode: gen = gen_aarch64_extv8qi; break;
-+    case V4HImode: gen = gen_aarch64_extv4hi; break;
-+    case V8HImode: gen = gen_aarch64_extv8hi; break;
-+    case V2SImode: gen = gen_aarch64_extv2si; break;
-+    case V4SImode: gen = gen_aarch64_extv4si; break;
-+    case V2SFmode: gen = gen_aarch64_extv2sf; break;
-+    case V4SFmode: gen = gen_aarch64_extv4sf; break;
-+    case V2DImode: gen = gen_aarch64_extv2di; break;
-+    case V2DFmode: gen = gen_aarch64_extv2df; break;
-+    default:
-+      return false;
-+    }
-+
-+  /* Success! */
-+  if (d->testing_p)
-+    return true;
-+
-+  /* The case where (location == 0) is a no-op for both big- and little-endian,
-+     and is removed by the mid-end at optimization levels -O1 and higher.  */
-+
-+  if (BYTES_BIG_ENDIAN && (location != 0))
-+    {
-+      /* After setup, we want the high elements of the first vector (stored
-+         at the LSB end of the register), and the low elements of the second
-+         vector (stored at the MSB end of the register). So swap.  */
-+      rtx temp = d->op0;
-+      d->op0 = d->op1;
-+      d->op1 = temp;
-+      /* location != 0 (above), so safe to assume (nelt - location) < nelt.  */
-+      location = nelt - location;
-+    }
-+
-+  offset = GEN_INT (location);
-+  emit_insn (gen (d->target, d->op0, d->op1, offset));
-+  return true;
-+}
-+
-+/* Recognize patterns for the REV insns.  */
-+
-+static bool
-+aarch64_evpc_rev (struct expand_vec_perm_d *d)
-+{
-+  unsigned int i, j, diff, nelt = d->nelt;
-+  rtx (*gen) (rtx, rtx);
-+
-+  if (!d->one_vector_p)
-+    return false;
-+
-+  diff = d->perm[0];
-+  switch (diff)
-+    {
-+    case 7:
-+      switch (d->vmode)
-+	{
-+	case V16QImode: gen = gen_aarch64_rev64v16qi; break;
-+	case V8QImode: gen = gen_aarch64_rev64v8qi;  break;
-+	default:
-+	  return false;
-+	}
-+      break;
-+    case 3:
-+      switch (d->vmode)
-+	{
-+	case V16QImode: gen = gen_aarch64_rev32v16qi; break;
-+	case V8QImode: gen = gen_aarch64_rev32v8qi;  break;
-+	case V8HImode: gen = gen_aarch64_rev64v8hi;  break;
-+	case V4HImode: gen = gen_aarch64_rev64v4hi;  break;
-+	default:
-+	  return false;
-+	}
-+      break;
-+    case 1:
-+      switch (d->vmode)
-+	{
-+	case V16QImode: gen = gen_aarch64_rev16v16qi; break;
-+	case V8QImode: gen = gen_aarch64_rev16v8qi;  break;
-+	case V8HImode: gen = gen_aarch64_rev32v8hi;  break;
-+	case V4HImode: gen = gen_aarch64_rev32v4hi;  break;
-+	case V4SImode: gen = gen_aarch64_rev64v4si;  break;
-+	case V2SImode: gen = gen_aarch64_rev64v2si;  break;
-+	case V4SFmode: gen = gen_aarch64_rev64v4sf;  break;
-+	case V2SFmode: gen = gen_aarch64_rev64v2sf;  break;
-+	default:
-+	  return false;
-+	}
-+      break;
-+    default:
-+      return false;
-+    }
-+
-+  for (i = 0; i < nelt ; i += diff + 1)
-+    for (j = 0; j <= diff; j += 1)
-+      {
-+	/* This is guaranteed to be true as the value of diff
-+	   is 7, 3, 1 and we should have enough elements in the
-+	   queue to generate this.  Getting a vector mask with a
-+	   value of diff other than these values implies that
-+	   something is wrong by the time we get here.  */
-+	gcc_assert (i + j < nelt);
-+	if (d->perm[i + j] != i + diff - j)
-+	  return false;
-+      }
-+
-+  /* Success! */
-+  if (d->testing_p)
-+    return true;
-+
-+  emit_insn (gen (d->target, d->op0));
-+  return true;
-+}
-+
-+static bool
- aarch64_evpc_dup (struct expand_vec_perm_d *d)
- {
-   rtx (*gen) (rtx, rtx, rtx);
-@@ -8181,10 +9576,6 @@
-   unsigned int i, elt, nelt = d->nelt;
-   rtx lane;
- 
--  /* TODO: This may not be big-endian safe.  */
--  if (BYTES_BIG_ENDIAN)
--    return false;
--
-   elt = d->perm[0];
-   for (i = 1; i < nelt; i++)
-     {
-@@ -8198,7 +9589,7 @@
-      use d->op0 and need not do any extra arithmetic to get the
-      correct lane number.  */
-   in0 = d->op0;
--  lane = GEN_INT (elt);
-+  lane = GEN_INT (elt); /* The pattern corrects for big-endian.  */
- 
-   switch (vmode)
-     {
-@@ -8227,11 +9618,6 @@
-   enum machine_mode vmode = d->vmode;
-   unsigned int i, nelt = d->nelt;
- 
--  /* TODO: ARM's TBL indexing is little-endian.  In order to handle GCC's
--     numbering of elements for big-endian, we must reverse the order.  */
--  if (BYTES_BIG_ENDIAN)
--    return false;
--
-   if (d->testing_p)
-     return true;
- 
-@@ -8242,7 +9628,15 @@
-     return false;
- 
-   for (i = 0; i < nelt; ++i)
--    rperm[i] = GEN_INT (d->perm[i]);
-+    {
-+      int nunits = GET_MODE_NUNITS (vmode);
-+
-+      /* If big-endian and two vectors we end up with a weird mixed-endian
-+	 mode on NEON.  Reverse the index within each word but not the word
-+	 itself.  */
-+      rperm[i] = GEN_INT (BYTES_BIG_ENDIAN ? d->perm[i] ^ (nunits - 1)
-+					   : d->perm[i]);
-+    }
-   sel = gen_rtx_CONST_VECTOR (vmode, gen_rtvec_v (nelt, rperm));
-   sel = force_reg (vmode, sel);
- 
-@@ -8271,14 +9665,18 @@
- 
-   if (TARGET_SIMD)
-     {
--      if (aarch64_evpc_zip (d))
-+      if (aarch64_evpc_rev (d))
- 	return true;
-+      else if (aarch64_evpc_ext (d))
-+	return true;
-+      else if (aarch64_evpc_dup (d))
-+	return true;
-+      else if (aarch64_evpc_zip (d))
-+	return true;
-       else if (aarch64_evpc_uzp (d))
- 	return true;
-       else if (aarch64_evpc_trn (d))
- 	return true;
--      else if (aarch64_evpc_dup (d))
--	return true;
-       return aarch64_evpc_tbl (d);
-     }
-   return false;
-@@ -8397,7 +9795,8 @@
-   /* Limited combinations of subregs are safe on FPREGs.  Particularly,
-      1. Vector Mode to Scalar mode where 1 unit of the vector is accessed.
-      2. Scalar to Scalar for integer modes or same size float modes.
--     3. Vector to Vector modes.  */
-+     3. Vector to Vector modes.
-+     4. On little-endian only, Vector-Structure to Vector modes.  */
-   if (GET_MODE_SIZE (from) > GET_MODE_SIZE (to))
-     {
-       if (aarch64_vector_mode_supported_p (from)
-@@ -8413,11 +9812,215 @@
-       if (aarch64_vector_mode_supported_p (from)
- 	  && aarch64_vector_mode_supported_p (to))
- 	return false;
-+
-+      /* Within an vector structure straddling multiple vector registers
-+	 we are in a mixed-endian representation.  As such, we can't
-+	 easily change modes for BYTES_BIG_ENDIAN.  Otherwise, we can
-+	 switch between vectors and vector structures cheaply.  */
-+      if (!BYTES_BIG_ENDIAN)
-+	if ((aarch64_vector_mode_supported_p (from)
-+	      && aarch64_vect_struct_mode_p (to))
-+	    || (aarch64_vector_mode_supported_p (to)
-+	      && aarch64_vect_struct_mode_p (from)))
-+	  return false;
-     }
- 
-   return true;
- }
- 
-+/* Implement MODES_TIEABLE_P.  */
-+
-+bool
-+aarch64_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
-+{
-+  if (GET_MODE_CLASS (mode1) == GET_MODE_CLASS (mode2))
-+    return true;
-+
-+  /* We specifically want to allow elements of "structure" modes to
-+     be tieable to the structure.  This more general condition allows
-+     other rarer situations too.  */
-+  if (TARGET_SIMD
-+      && aarch64_vector_mode_p (mode1)
-+      && aarch64_vector_mode_p (mode2))
-+    return true;
-+
-+  return false;
-+}
-+
-+/* Return a new RTX holding the result of moving POINTER forward by
-+   AMOUNT bytes.  */
-+
-+static rtx
-+aarch64_move_pointer (rtx pointer, int amount)
-+{
-+  rtx next = plus_constant (Pmode, XEXP (pointer, 0), amount);
-+
-+  return adjust_automodify_address (pointer, GET_MODE (pointer),
-+				    next, amount);
-+}
-+
-+/* Return a new RTX holding the result of moving POINTER forward by the
-+   size of the mode it points to.  */
-+
-+static rtx
-+aarch64_progress_pointer (rtx pointer)
-+{
-+  HOST_WIDE_INT amount = GET_MODE_SIZE (GET_MODE (pointer));
-+
-+  return aarch64_move_pointer (pointer, amount);
-+}
-+
-+/* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
-+   MODE bytes.  */
-+
-+static void
-+aarch64_copy_one_block_and_progress_pointers (rtx *src, rtx *dst,
-+					      enum machine_mode mode)
-+{
-+  rtx reg = gen_reg_rtx (mode);
-+
-+  /* "Cast" the pointers to the correct mode.  */
-+  *src = adjust_address (*src, mode, 0);
-+  *dst = adjust_address (*dst, mode, 0);
-+  /* Emit the memcpy.  */
-+  emit_move_insn (reg, *src);
-+  emit_move_insn (*dst, reg);
-+  /* Move the pointers forward.  */
-+  *src = aarch64_progress_pointer (*src);
-+  *dst = aarch64_progress_pointer (*dst);
-+}
-+
-+/* Expand movmem, as if from a __builtin_memcpy.  Return true if
-+   we succeed, otherwise return false.  */
-+
-+bool
-+aarch64_expand_movmem (rtx *operands)
-+{
-+  unsigned int n;
-+  rtx dst = operands[0];
-+  rtx src = operands[1];
-+  rtx base;
-+  bool speed_p = !optimize_function_for_size_p (cfun);
-+
-+  /* When optimizing for size, give a better estimate of the length of a
-+     memcpy call, but use the default otherwise.  */
-+  unsigned int max_instructions = (speed_p ? 15 : AARCH64_CALL_RATIO) / 2;
-+
-+  /* We can't do anything smart if the amount to copy is not constant.  */
-+  if (!CONST_INT_P (operands[2]))
-+    return false;
-+
-+  n = UINTVAL (operands[2]);
-+
-+  /* Try to keep the number of instructions low.  For cases below 16 bytes we
-+     need to make at most two moves.  For cases above 16 bytes it will be one
-+     move for each 16 byte chunk, then at most two additional moves.  */
-+  if (((n / 16) + (n % 16 ? 2 : 0)) > max_instructions)
-+    return false;
-+
-+  base = copy_to_mode_reg (Pmode, XEXP (dst, 0));
-+  dst = adjust_automodify_address (dst, VOIDmode, base, 0);
-+
-+  base = copy_to_mode_reg (Pmode, XEXP (src, 0));
-+  src = adjust_automodify_address (src, VOIDmode, base, 0);
-+
-+  /* Simple cases.  Copy 0-3 bytes, as (if applicable) a 2-byte, then a
-+     1-byte chunk.  */
-+  if (n < 4)
-+    {
-+      if (n >= 2)
-+	{
-+	  aarch64_copy_one_block_and_progress_pointers (&src, &dst, HImode);
-+	  n -= 2;
-+	}
-+
-+      if (n == 1)
-+	aarch64_copy_one_block_and_progress_pointers (&src, &dst, QImode);
-+
-+      return true;
-+    }
-+
-+  /* Copy 4-8 bytes.  First a 4-byte chunk, then (if applicable) a second
-+     4-byte chunk, partially overlapping with the previously copied chunk.  */
-+  if (n < 8)
-+    {
-+      aarch64_copy_one_block_and_progress_pointers (&src, &dst, SImode);
-+      n -= 4;
-+      if (n > 0)
-+	{
-+	  int move = n - 4;
-+
-+	  src = aarch64_move_pointer (src, move);
-+	  dst = aarch64_move_pointer (dst, move);
-+	  aarch64_copy_one_block_and_progress_pointers (&src, &dst, SImode);
-+	}
-+      return true;
-+    }
-+
-+  /* Copy more than 8 bytes.  Copy chunks of 16 bytes until we run out of
-+     them, then (if applicable) an 8-byte chunk.  */
-+  while (n >= 8)
-+    {
-+      if (n / 16)
-+	{
-+	  aarch64_copy_one_block_and_progress_pointers (&src, &dst, TImode);
-+	  n -= 16;
-+	}
-+      else
-+	{
-+	  aarch64_copy_one_block_and_progress_pointers (&src, &dst, DImode);
-+	  n -= 8;
-+	}
-+    }
-+
-+  /* Finish the final bytes of the copy.  We can always do this in one
-+     instruction.  We either copy the exact amount we need, or partially
-+     overlap with the previous chunk we copied and copy 8-bytes.  */
-+  if (n == 0)
-+    return true;
-+  else if (n == 1)
-+    aarch64_copy_one_block_and_progress_pointers (&src, &dst, QImode);
-+  else if (n == 2)
-+    aarch64_copy_one_block_and_progress_pointers (&src, &dst, HImode);
-+  else if (n == 4)
-+    aarch64_copy_one_block_and_progress_pointers (&src, &dst, SImode);
-+  else
-+    {
-+      if (n == 3)
-+	{
-+	  src = aarch64_move_pointer (src, -1);
-+	  dst = aarch64_move_pointer (dst, -1);
-+	  aarch64_copy_one_block_and_progress_pointers (&src, &dst, SImode);
-+	}
-+      else
-+	{
-+	  int move = n - 8;
-+
-+	  src = aarch64_move_pointer (src, move);
-+	  dst = aarch64_move_pointer (dst, move);
-+	  aarch64_copy_one_block_and_progress_pointers (&src, &dst, DImode);
-+	}
-+    }
-+
-+  return true;
-+}
-+
-+static bool
-+aarch64_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size,
-+					unsigned int align,
-+					enum by_pieces_operation op,
-+					bool speed_p)
-+{
-+  /* STORE_BY_PIECES can be used when copying a constant string, but
-+     in that case each 64-bit chunk takes 5 insns instead of 2 (LDR/STR).
-+     For now we always fail this and let the move_by_pieces code copy
-+     the string from read-only memory.  */
-+  if (op == STORE_BY_PIECES)
-+    return false;
-+
-+  return default_use_by_pieces_infrastructure_p (size, align, op, speed_p);
-+}
-+
- #undef TARGET_ADDRESS_COST
- #define TARGET_ADDRESS_COST aarch64_address_cost
- 
-@@ -8588,7 +10191,7 @@
- #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
- 
- #undef TARGET_RTX_COSTS
--#define TARGET_RTX_COSTS aarch64_rtx_costs
-+#define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
- 
- #undef TARGET_SCHED_ISSUE_RATE
- #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
-@@ -8626,6 +10229,10 @@
- #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
-   aarch64_autovectorize_vector_sizes
- 
-+#undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
-+#define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
-+  aarch64_atomic_assign_expand_fenv
-+
- /* Section anchor support.  */
- 
- #undef TARGET_MIN_ANCHOR_OFFSET
-@@ -8654,6 +10261,19 @@
- #undef TARGET_FIXED_CONDITION_CODE_REGS
- #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
- 
-+#undef TARGET_FLAGS_REGNUM
-+#define TARGET_FLAGS_REGNUM CC_REGNUM
-+
-+#undef TARGET_LEGITIMIZE_ADDRESS
-+#define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
-+
-+#undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
-+#define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
-+  aarch64_use_by_pieces_infrastructure_p
-+
-+#undef TARGET_CAN_USE_DOLOOP_P
-+#define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
-+
- struct gcc_target targetm = TARGET_INITIALIZER;
- 
- #include "gt-aarch64.h"
---- a/src/gcc/config/aarch64/aarch64-elf-raw.h
-+++ b/src/gcc/config/aarch64/aarch64-elf-raw.h
-@@ -23,7 +23,9 @@
- #define GCC_AARCH64_ELF_RAW_H
- 
- #define STARTFILE_SPEC " crti%O%s crtbegin%O%s crt0%O%s"
--#define ENDFILE_SPEC " crtend%O%s crtn%O%s"
-+#define ENDFILE_SPEC \
-+  " crtend%O%s crtn%O%s " \
-+  "%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s}"
- 
- #ifdef TARGET_FIX_ERR_A53_835769_DEFAULT
- #define CA53_ERR_835769_SPEC \
---- a/src/gcc/config/aarch64/aarch64-linux.h
-+++ b/src/gcc/config/aarch64/aarch64-linux.h
-@@ -21,7 +21,7 @@
- #ifndef GCC_AARCH64_LINUX_H
- #define GCC_AARCH64_LINUX_H
- 
--#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-aarch64%{mbig-endian:_be}.so.1"
-+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
- 
- #define CPP_SPEC "%{pthread:-D_REENTRANT}"
- 
-@@ -33,7 +33,7 @@
-    -dynamic-linker " GNU_USER_DYNAMIC_LINKER "	\
-    -X						\
-    %{mbig-endian:-EB} %{mlittle-endian:-EL}     \
--   -maarch64linux%{mbig-endian:b}"
-+   -maarch64linux%{mabi=ilp32:32}%{mbig-endian:b}"
- 
- #ifdef TARGET_FIX_ERR_A53_835769_DEFAULT
- #define CA53_ERR_835769_SPEC \
-@@ -46,6 +46,14 @@
- #define LINK_SPEC LINUX_TARGET_LINK_SPEC \
-                   CA53_ERR_835769_SPEC
- 
-+#define GNU_USER_TARGET_MATHFILE_SPEC \
-+  "%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s}"
-+
-+#undef ENDFILE_SPEC
-+#define ENDFILE_SPEC   \
-+  GNU_USER_TARGET_MATHFILE_SPEC " " \
-+  GNU_USER_TARGET_ENDFILE_SPEC
-+
- #define TARGET_OS_CPP_BUILTINS()		\
-   do						\
-     {						\
---- a/src/gcc/config/aarch64/iterators.md
-+++ b/src/gcc/config/aarch64/iterators.md
-@@ -95,6 +95,9 @@
- ;; Vector Float modes.
- (define_mode_iterator VDQF [V2SF V4SF V2DF])
- 
-+;; Vector Float modes, and DF.
-+(define_mode_iterator VDQF_DF [V2SF V4SF V2DF DF])
-+
- ;; Vector single Float modes.
- (define_mode_iterator VDQSF [V2SF V4SF])
- 
-@@ -156,6 +159,9 @@
- ;; Vector modes for H and S types.
- (define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI])
- 
-+;; Vector modes for H, S and D types.
-+(define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI])
-+
- ;; Vector modes for Q, H and S types.
- (define_mode_iterator VDQQHS [V8QI V16QI V4HI V8HI V2SI V4SI])
- 
-@@ -273,6 +279,10 @@
-     UNSPEC_UZP2		; Used in vector permute patterns.
-     UNSPEC_TRN1		; Used in vector permute patterns.
-     UNSPEC_TRN2		; Used in vector permute patterns.
-+    UNSPEC_EXT		; Used in aarch64-simd.md.
-+    UNSPEC_REV64	; Used in vector reverse patterns (permute).
-+    UNSPEC_REV32	; Used in vector reverse patterns (permute).
-+    UNSPEC_REV16	; Used in vector reverse patterns (permute).
-     UNSPEC_AESE		; Used in aarch64-simd.md.
-     UNSPEC_AESD         ; Used in aarch64-simd.md.
-     UNSPEC_AESMC        ; Used in aarch64-simd.md.
-@@ -299,6 +309,10 @@
- ;; 32-bit version and "%x0" in the 64-bit version.
- (define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")])
- 
-+;; For inequal width int to float conversion
-+(define_mode_attr w1 [(SF "w") (DF "x")])
-+(define_mode_attr w2 [(SF "x") (DF "w")])
-+
- ;; For constraints used in scalar immediate vector moves
- (define_mode_attr hq [(HI "h") (QI "q")])
- 
-@@ -348,6 +362,9 @@
- ;; Attribute to describe constants acceptable in logical operations
- (define_mode_attr lconst [(SI "K") (DI "L")])
- 
-+;; Attribute to describe constants acceptable in atomic logical operations
-+(define_mode_attr lconst_atomic [(QI "K") (HI "K") (SI "K") (DI "L")])
-+
- ;; Map a mode to a specific constraint character.
- (define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")])
- 
-@@ -358,6 +375,9 @@
-                          (V2DI "2d") (V2SF "2s")
- 			 (V4SF "4s") (V2DF "2d")])
- 
-+(define_mode_attr Vrevsuff [(V4HI "16") (V8HI "16") (V2SI "32")
-+                            (V4SI "32") (V2DI "64")])
-+
- (define_mode_attr Vmtype [(V8QI ".8b") (V16QI ".16b")
- 			 (V4HI ".4h") (V8HI  ".8h")
- 			 (V2SI ".2s") (V4SI  ".4s")
-@@ -552,13 +572,43 @@
- 
- (define_mode_attr VSTRUCT_DREG [(OI "TI") (CI "EI") (XI "OI")])
- 
-+;; Mode of pair of elements for each vector mode, to define transfer
-+;; size for structure lane/dup loads and stores.
-+(define_mode_attr V_TWO_ELEM [(V8QI "HI")   (V16QI "HI")
-+                              (V4HI "SI")   (V8HI "SI")
-+                              (V2SI "V2SI") (V4SI "V2SI")
-+                              (DI "V2DI")   (V2DI "V2DI")
-+                              (V2SF "V2SF") (V4SF "V2SF")
-+                              (DF "V2DI")   (V2DF "V2DI")])
-+
-+;; Similar, for three elements.
-+(define_mode_attr V_THREE_ELEM [(V8QI "BLK") (V16QI "BLK")
-+                                (V4HI "BLK") (V8HI "BLK")
-+                                (V2SI "BLK") (V4SI "BLK")
-+                                (DI "EI")    (V2DI "EI")
-+                                (V2SF "BLK") (V4SF "BLK")
-+                                (DF "EI")    (V2DF "EI")])
-+
-+;; Similar, for four elements.
-+(define_mode_attr V_FOUR_ELEM [(V8QI "SI")   (V16QI "SI")
-+                               (V4HI "V4HI") (V8HI "V4HI")
-+                               (V2SI "V4SI") (V4SI "V4SI")
-+                               (DI "OI")     (V2DI "OI")
-+                               (V2SF "V4SF") (V4SF "V4SF")
-+                               (DF "OI")     (V2DF "OI")])
-+
-+
- ;; Mode for atomic operation suffixes
- (define_mode_attr atomic_sfx
-   [(QI "b") (HI "h") (SI "") (DI "")])
- 
--(define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si")])
--(define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI")])
-+(define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si") (SF "si") (DF "di")])
-+(define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI") (SF "SI") (DF "DI")])
- 
-+;; for the inequal width integer to fp conversions
-+(define_mode_attr fcvt_iesize [(SF "di") (DF "si")])
-+(define_mode_attr FCVT_IESIZE [(SF "DI") (DF "SI")])
-+
- (define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI "V8QI")
- 				(V4HI "V8HI") (V8HI  "V4HI")
- 				(V2SI "V4SI") (V4SI  "V2SI")
-@@ -853,6 +903,8 @@
- 			      UNSPEC_TRN1 UNSPEC_TRN2
- 			      UNSPEC_UZP1 UNSPEC_UZP2])
- 
-+(define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16])
-+
- (define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
- 			     UNSPEC_FRINTN UNSPEC_FRINTI UNSPEC_FRINTX
- 			     UNSPEC_FRINTA])
-@@ -862,6 +914,10 @@
- 
- (define_int_iterator FRECP [UNSPEC_FRECPE UNSPEC_FRECPX])
- 
-+(define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W
-+                          UNSPEC_CRC32X UNSPEC_CRC32CB UNSPEC_CRC32CH
-+                          UNSPEC_CRC32CW UNSPEC_CRC32CX])
-+
- (define_int_iterator CRYPTO_AES [UNSPEC_AESE UNSPEC_AESD])
- (define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC])
- 
-@@ -980,6 +1036,10 @@
- 			    (UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn")
- 			    (UNSPEC_UZP1 "uzp") (UNSPEC_UZP2 "uzp")])
- 
-+; op code for REV instructions (size within which elements are reversed).
-+(define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32")
-+			 (UNSPEC_REV16 "16")])
-+
- (define_int_attr perm_hilo [(UNSPEC_ZIP1 "1") (UNSPEC_ZIP2 "2")
- 			    (UNSPEC_TRN1 "1") (UNSPEC_TRN2 "2")
- 			    (UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2")])
-@@ -986,6 +1046,16 @@
- 
- (define_int_attr frecp_suffix  [(UNSPEC_FRECPE "e") (UNSPEC_FRECPX "x")])
- 
-+(define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h")
-+                        (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32X "crc32x")
-+                        (UNSPEC_CRC32CB "crc32cb") (UNSPEC_CRC32CH "crc32ch")
-+                        (UNSPEC_CRC32CW "crc32cw") (UNSPEC_CRC32CX "crc32cx")])
-+
-+(define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI")
-+                        (UNSPEC_CRC32W "SI") (UNSPEC_CRC32X "DI")
-+                        (UNSPEC_CRC32CB "QI") (UNSPEC_CRC32CH "HI")
-+                        (UNSPEC_CRC32CW "SI") (UNSPEC_CRC32CX "DI")])
-+
- (define_int_attr aes_op [(UNSPEC_AESE "e") (UNSPEC_AESD "d")])
- (define_int_attr aesmc_op [(UNSPEC_AESMC "mc") (UNSPEC_AESIMC "imc")])
- 
---- a/src/gcc/config/aarch64/aarch64.h
-+++ b/src/gcc/config/aarch64/aarch64.h
-@@ -26,14 +26,48 @@
- #define TARGET_CPU_CPP_BUILTINS()			\
-   do							\
-     {							\
--      builtin_define ("__aarch64__");			\
-+      builtin_define ("__aarch64__");                   \
-+      builtin_define ("__ARM_64BIT_STATE");             \
-+      builtin_define_with_int_value                     \
-+        ("__ARM_ARCH", aarch64_architecture_version);   \
-+      cpp_define_formatted                                              \
-+        (parse_in, "__ARM_ARCH_%dA", aarch64_architecture_version);     \
-+      builtin_define ("__ARM_ARCH_ISA_A64");            \
-+      builtin_define_with_int_value                     \
-+        ("__ARM_ARCH_PROFILE", 'A');                    \
-+      builtin_define ("__ARM_FEATURE_CLZ");             \
-+      builtin_define ("__ARM_FEATURE_IDIV");            \
-+      builtin_define ("__ARM_FEATURE_UNALIGNED");       \
-+      if (flag_unsafe_math_optimizations)               \
-+        builtin_define ("__ARM_FP_FAST");               \
-+      builtin_define ("__ARM_PCS_AAPCS64");             \
-+      builtin_define_with_int_value                     \
-+        ("__ARM_SIZEOF_WCHAR_T", WCHAR_TYPE_SIZE / 8);  \
-+      builtin_define_with_int_value                     \
-+        ("__ARM_SIZEOF_MINIMAL_ENUM",                   \
-+         flag_short_enums? 1 : 4);                      \
-       if (TARGET_BIG_END)				\
--	builtin_define ("__AARCH64EB__");		\
-+        {                                               \
-+          builtin_define ("__AARCH64EB__");             \
-+          builtin_define ("__ARM_BIG_ENDIAN");          \
-+        }                                               \
-       else						\
- 	builtin_define ("__AARCH64EL__");		\
- 							\
--      if (TARGET_SIMD)					\
--	builtin_define ("__ARM_NEON");			\
-+      if (TARGET_FLOAT)                                         \
-+        {                                                       \
-+          builtin_define ("__ARM_FEATURE_FMA");                 \
-+          builtin_define_with_int_value ("__ARM_FP", 0x0C);     \
-+        }                                                       \
-+      if (TARGET_SIMD)                                          \
-+        {                                                       \
-+          builtin_define ("__ARM_FEATURE_NUMERIC_MAXMIN");      \
-+          builtin_define ("__ARM_NEON");			\
-+          builtin_define_with_int_value ("__ARM_NEON_FP", 0x0C);\
-+        }                                                       \
-+							        \
-+      if (TARGET_CRC32)				        \
-+	builtin_define ("__ARM_FEATURE_CRC32");		\
- 							\
-       switch (aarch64_cmodel)				\
- 	{						\
-@@ -155,6 +189,8 @@
- 
- #define PCC_BITFIELD_TYPE_MATTERS	1
- 
-+/* Major revision number of the ARM Architecture implemented by the target.  */
-+extern unsigned aarch64_architecture_version;
- 
- /* Instruction tuning/selection flags.  */
- 
-@@ -188,6 +224,9 @@
- /* Crypto is an optional extension to AdvSIMD.  */
- #define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO)
- 
-+/* CRC instructions that can be enabled through +crc arch extension.  */
-+#define TARGET_CRC32 (AARCH64_ISA_CRC)
-+
- /* Standard register usage.  */
- 
- /* 31 64-bit general purpose registers R0-R30:
-@@ -365,8 +404,7 @@
- 
- #define HARD_REGNO_MODE_OK(REGNO, MODE)	aarch64_hard_regno_mode_ok (REGNO, MODE)
- 
--#define MODES_TIEABLE_P(MODE1, MODE2)			\
--  (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
-+#define MODES_TIEABLE_P(MODE1, MODE2) aarch64_modes_tieable_p (MODE1, MODE2)
- 
- #define DWARF2_UNWIND_INFO 1
- 
-@@ -409,7 +447,7 @@
- enum reg_class
- {
-   NO_REGS,
--  CORE_REGS,
-+  CALLER_SAVE_REGS,
-   GENERAL_REGS,
-   STACK_REG,
-   POINTER_REGS,
-@@ -424,7 +462,7 @@
- #define REG_CLASS_NAMES				\
- {						\
-   "NO_REGS",					\
--  "CORE_REGS",					\
-+  "CALLER_SAVE_REGS",				\
-   "GENERAL_REGS",				\
-   "STACK_REG",					\
-   "POINTER_REGS",				\
-@@ -436,7 +474,7 @@
- #define REG_CLASS_CONTENTS						\
- {									\
-   { 0x00000000, 0x00000000, 0x00000000 },	/* NO_REGS */		\
--  { 0x7fffffff, 0x00000000, 0x00000003 },	/* CORE_REGS */		\
-+  { 0x0007ffff, 0x00000000, 0x00000000 },	/* CALLER_SAVE_REGS */	\
-   { 0x7fffffff, 0x00000000, 0x00000003 },	/* GENERAL_REGS */	\
-   { 0x80000000, 0x00000000, 0x00000000 },	/* STACK_REG */		\
-   { 0xffffffff, 0x00000000, 0x00000003 },	/* POINTER_REGS */	\
-@@ -447,7 +485,7 @@
- 
- #define REGNO_REG_CLASS(REGNO)	aarch64_regno_regclass (REGNO)
- 
--#define INDEX_REG_CLASS	CORE_REGS
-+#define INDEX_REG_CLASS	GENERAL_REGS
- #define BASE_REG_CLASS  POINTER_REGS
- 
- /* Register pairs used to eliminate unneeded registers that point into
-@@ -524,13 +562,33 @@
- struct GTY (()) aarch64_frame
- {
-   HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
-+
-+  /* The number of extra stack bytes taken up by register varargs.
-+     This area is allocated by the callee at the very top of the
-+     frame.  This value is rounded up to a multiple of
-+     STACK_BOUNDARY.  */
-+  HOST_WIDE_INT saved_varargs_size;
-+
-   HOST_WIDE_INT saved_regs_size;
-   /* Padding if needed after the all the callee save registers have
-      been saved.  */
-   HOST_WIDE_INT padding0;
-   HOST_WIDE_INT hardfp_offset;	/* HARD_FRAME_POINTER_REGNUM */
--  HOST_WIDE_INT fp_lr_offset;	/* Space needed for saving fp and/or lr */
- 
-+  /* Offset from the base of the frame (incomming SP) to the
-+     hard_frame_pointer.  This value is always a multiple of
-+     STACK_BOUNDARY.  */
-+  HOST_WIDE_INT hard_fp_offset;
-+
-+  /* The size of the frame.  This value is the offset from base of the
-+   * frame (incomming SP) to the stack_pointer.  This value is always
-+   * a multiple of STACK_BOUNDARY.  */
-+
-+  unsigned wb_candidate1;
-+  unsigned wb_candidate2;
-+
-+  HOST_WIDE_INT frame_size;
-+
-   bool laid_out;
- };
- 
-@@ -537,11 +595,6 @@
- typedef struct GTY (()) machine_function
- {
-   struct aarch64_frame frame;
--
--  /* The number of extra stack bytes taken up by register varargs.
--     This area is allocated by the callee at the very top of the frame.  */
--  HOST_WIDE_INT saved_varargs_size;
--
- } machine_function;
- #endif
- 
-@@ -565,11 +618,7 @@
- };
- 
- 
--extern enum arm_pcs arm_pcs_variant;
- 
--#ifndef ARM_DEFAULT_PCS
--#define ARM_DEFAULT_PCS ARM_PCS_AAPCS64
--#endif
- 
- /* We can't use enum machine_mode inside a generator file because it
-    hasn't been created yet; we shouldn't be using any code that
-@@ -670,12 +719,14 @@
- /* The base cost overhead of a memcpy call, for MOVE_RATIO and friends.  */
- #define AARCH64_CALL_RATIO 8
- 
--/* When optimizing for size, give a better estimate of the length of a memcpy
--   call, but use the default otherwise.  But move_by_pieces_ninsns() counts
--   memory-to-memory moves, and we'll have to generate a load & store for each,
--   so halve the value to take that into account.  */
-+/* MOVE_RATIO dictates when we will use the move_by_pieces infrastructure.
-+   move_by_pieces will continually copy the largest safe chunks.  So a
-+   7-byte copy is a 4-byte + 2-byte + byte copy.  This proves inefficient
-+   for both size and speed of copy, so we will instead use the "movmem"
-+   standard name to implement the copy.  This logic does not apply when
-+   targeting -mstrict-align, so keep a sensible default in that case.  */
- #define MOVE_RATIO(speed) \
--  (((speed) ? 15 : AARCH64_CALL_RATIO) / 2)
-+  (!STRICT_ALIGNMENT ? 2 : (((speed) ? 15 : AARCH64_CALL_RATIO) / 2))
- 
- /* For CLEAR_RATIO, when optimizing for size, give a better estimate
-    of the length of a memset call, but use the default otherwise.  */
-@@ -688,12 +739,6 @@
- #define SET_RATIO(speed) \
-   ((speed) ? 15 : AARCH64_CALL_RATIO - 2)
- 
--/* STORE_BY_PIECES_P can be used when copying a constant string, but
--   in that case each 64-bit chunk takes 5 insns instead of 2 (LDR/STR).
--   For now we always fail this and let the move_by_pieces code copy
--   the string from read-only memory.  */
--#define STORE_BY_PIECES_P(SIZE, ALIGN) 0
--
- /* Disable auto-increment in move_by_pieces et al.  Use of auto-increment is
-    rarely a good idea in straight-line code since it adds an extra address
-    dependency between each instruction.  Better to use incrementing offsets.  */
-@@ -835,6 +880,11 @@
- 
- #define SHIFT_COUNT_TRUNCATED !TARGET_SIMD
- 
-+/* Choose appropriate mode for caller saves, so we do the minimum
-+   required size of load/store.  */
-+#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
-+  aarch64_hard_regno_caller_save_mode ((REGNO), (NREGS), (MODE))
-+
- /* Callee only saves lower 64-bits of a 128-bit register.  Tell the
-    compiler the callee clobbers the top 64-bits when restoring the
-    bottom 64-bits.  */
---- a/src/gcc/config/arc/arc.c
-+++ b/src/gcc/config/arc/arc.c
-@@ -398,6 +398,11 @@
- 
- static bool arc_frame_pointer_required (void);
- 
-+static bool arc_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT,
-+						unsigned int,
-+						enum by_pieces_operation op,
-+						bool);
-+
- /* Implements target hook vector_mode_supported_p.  */
- 
- static bool
-@@ -512,6 +517,10 @@
- #undef TARGET_DELEGITIMIZE_ADDRESS
- #define TARGET_DELEGITIMIZE_ADDRESS arc_delegitimize_address
- 
-+#undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
-+#define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
-+  arc_use_by_pieces_infrastructure_p
-+
- /* Usually, we will be able to scale anchor offsets.
-    When this fails, we want LEGITIMIZE_ADDRESS to kick in.  */
- #undef TARGET_MIN_ANCHOR_OFFSET
-@@ -9355,6 +9364,21 @@
-   return false;
- }
- 
-+/* Implement TARGET_USE_BY_PIECES_INFRASTRUCTURE_P.  */
-+
-+static bool
-+arc_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size,
-+				    unsigned int align,
-+				    enum by_pieces_operation op,
-+				    bool speed_p)
-+{
-+  /* Let the movmem expander handle small block moves.  */
-+  if (op == MOVE_BY_PIECES)
-+    return false;
-+
-+  return default_use_by_pieces_infrastructure_p (size, align, op, speed_p);
-+}
-+
- struct gcc_target targetm = TARGET_INITIALIZER;
- 
- #include "gt-arc.h"
---- a/src/gcc/config/arc/arc.h
-+++ b/src/gcc/config/arc/arc.h
-@@ -1553,12 +1553,6 @@
-    in one reasonably fast instruction.  */
- #define MOVE_MAX 4
- 
--/* Let the movmem expander handle small block moves.  */
--#define MOVE_BY_PIECES_P(LEN, ALIGN)  0
--#define CAN_MOVE_BY_PIECES(SIZE, ALIGN) \
--  (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
--   < (unsigned int) MOVE_RATIO (!optimize_size))
--
- /* Undo the effects of the movmem pattern presence on STORE_BY_PIECES_P .  */
- #define MOVE_RATIO(SPEED) ((SPEED) ? 15 : 3)
- 
---- a/src/gcc/config/arm/aarch-cost-tables.h
-+++ b/src/gcc/config/arm/aarch-cost-tables.h
-@@ -39,6 +39,7 @@
-     0,			/* bfi.  */
-     0,			/* bfx.  */
-     0,			/* clz.  */
-+    0,			/* rev.  */
-     COSTS_N_INSNS (1),	/* non_exec.  */
-     false		/* non_exec_costs_exec.  */
-   },
-@@ -139,6 +140,7 @@
-     COSTS_N_INSNS (1),	/* bfi.  */
-     COSTS_N_INSNS (1),	/* bfx.  */
-     0,			/* clz.  */
-+    0,			/* rev.  */
-     0,			/* non_exec.  */
-     true		/* non_exec_costs_exec.  */
-   },
-@@ -239,6 +241,7 @@
-     COSTS_N_INSNS (1), /* bfi.  */
-     0,                 /* bfx.  */
-     0,                 /* clz.  */
-+    0,			/* rev.  */
-     0,                 /* non_exec.  */
-     true               /* non_exec_costs_exec.  */
-   },
---- a/src/gcc/config/arm/cortex-a15.md
-+++ b/src/gcc/config/arm/cortex-a15.md
-@@ -64,7 +64,7 @@
-        (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
-                         alu_reg,alus_reg,logic_reg,logics_reg,\
-                         adc_imm,adcs_imm,adc_reg,adcs_reg,\
--                        adr,bfm,rev,\
-+                        adr,bfm,clz,rbit,rev,\
-                         shift_imm,shift_reg,\
-                         mov_imm,mov_reg,\
-                         mvn_imm,mvn_reg,\
-@@ -72,11 +72,14 @@
-   "ca15_issue1,(ca15_sx1,ca15_sx1_alu)|(ca15_sx2,ca15_sx2_alu)")
- 
- ;; ALU ops with immediate shift
-+;; crc is also included here so that appropriate scheduling of CRC32 ARMv8-A
-+;; instructions can be performed when tuning for the Cortex-A57 since that
-+;; core reuses the Cortex-A15 pipeline description for the moment.
- (define_insn_reservation "cortex_a15_alu_shift" 3
-   (and (eq_attr "tune" "cortexa15")
-        (eq_attr "type" "extend,\
-                         alu_shift_imm,alus_shift_imm,\
--                        logic_shift_imm,logics_shift_imm,\
-+                        crc,logic_shift_imm,logics_shift_imm,\
-                         mov_shift,mvn_shift"))
-   "ca15_issue1,(ca15_sx1,ca15_sx1+ca15_sx1_shf,ca15_sx1_alu)\
- 	       |(ca15_sx2,ca15_sx2+ca15_sx2_shf,ca15_sx2_alu)")
---- a/src/gcc/config/arm/arm-tables.opt
-+++ b/src/gcc/config/arm/arm-tables.opt
-@@ -274,6 +274,9 @@
- Enum(processor_type) String(cortex-r7) Value(cortexr7)
- 
- EnumValue
-+Enum(processor_type) String(cortex-m7) Value(cortexm7)
-+
-+EnumValue
- Enum(processor_type) String(cortex-m4) Value(cortexm4)
- 
- EnumValue
-@@ -423,17 +426,23 @@
- Enum(arm_fpu) String(fpv4-sp-d16) Value(11)
- 
- EnumValue
--Enum(arm_fpu) String(neon-vfpv4) Value(12)
-+Enum(arm_fpu) String(fpv5-sp-d16) Value(12)
- 
- EnumValue
--Enum(arm_fpu) String(fp-armv8) Value(13)
-+Enum(arm_fpu) String(fpv5-d16) Value(13)
- 
- EnumValue
--Enum(arm_fpu) String(neon-fp-armv8) Value(14)
-+Enum(arm_fpu) String(neon-vfpv4) Value(14)
- 
- EnumValue
--Enum(arm_fpu) String(crypto-neon-fp-armv8) Value(15)
-+Enum(arm_fpu) String(fp-armv8) Value(15)
- 
- EnumValue
--Enum(arm_fpu) String(vfp3) Value(16)
-+Enum(arm_fpu) String(neon-fp-armv8) Value(16)
- 
-+EnumValue
-+Enum(arm_fpu) String(crypto-neon-fp-armv8) Value(17)
-+
-+EnumValue
-+Enum(arm_fpu) String(vfp3) Value(18)
-+
---- a/src/gcc/config/arm/thumb2.md
-+++ b/src/gcc/config/arm/thumb2.md
-@@ -329,7 +329,7 @@
-    movw%?\\t%0, %L1\\t%@ movhi
-    str%(h%)\\t%1, %0\\t%@ movhi
-    ldr%(h%)\\t%0, %1\\t%@ movhi"
--  [(set_attr "type" "mov_reg,mov_imm,mov_imm,mov_reg,store1,load1")
-+  [(set_attr "type" "mov_reg,mov_imm,mov_imm,mov_imm,store1,load1")
-    (set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "yes,no,yes,no,no,no")
-    (set_attr "length" "2,4,2,4,4,4")
-@@ -1370,6 +1370,103 @@
-    (set_attr "type" "alu_reg")]
- )
- 
-+; Constants for op 2 will never be given to these patterns.
-+(define_insn_and_split "*iordi_notdi_di"
-+  [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
-+	(ior:DI (not:DI (match_operand:DI 1 "s_register_operand" "0,r"))
-+		(match_operand:DI 2 "s_register_operand" "r,0")))]
-+  "TARGET_THUMB2"
-+  "#"
-+  "TARGET_THUMB2 && reload_completed"
-+  [(set (match_dup 0) (ior:SI (not:SI (match_dup 1)) (match_dup 2)))
-+   (set (match_dup 3) (ior:SI (not:SI (match_dup 4)) (match_dup 5)))]
-+  "
-+  {
-+    operands[3] = gen_highpart (SImode, operands[0]);
-+    operands[0] = gen_lowpart (SImode, operands[0]);
-+    operands[4] = gen_highpart (SImode, operands[1]);
-+    operands[1] = gen_lowpart (SImode, operands[1]);
-+    operands[5] = gen_highpart (SImode, operands[2]);
-+    operands[2] = gen_lowpart (SImode, operands[2]);
-+  }"
-+  [(set_attr "length" "8")
-+   (set_attr "predicable" "yes")
-+   (set_attr "predicable_short_it" "no")
-+   (set_attr "type" "multiple")]
-+)
-+
-+(define_insn_and_split "*iordi_notzesidi_di"
-+  [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
-+	(ior:DI (not:DI (zero_extend:DI
-+			 (match_operand:SI 2 "s_register_operand" "r,r")))
-+		(match_operand:DI 1 "s_register_operand" "0,?r")))]
-+  "TARGET_THUMB2"
-+  "#"
-+  ; (not (zero_extend...)) means operand0 will always be 0xffffffff
-+  "TARGET_THUMB2 && reload_completed"
-+  [(set (match_dup 0) (ior:SI (not:SI (match_dup 2)) (match_dup 1)))
-+   (set (match_dup 3) (const_int -1))]
-+  "
-+  {
-+    operands[3] = gen_highpart (SImode, operands[0]);
-+    operands[0] = gen_lowpart (SImode, operands[0]);
-+    operands[1] = gen_lowpart (SImode, operands[1]);
-+  }"
-+  [(set_attr "length" "4,8")
-+   (set_attr "predicable" "yes")
-+   (set_attr "predicable_short_it" "no")
-+   (set_attr "type" "multiple")]
-+)
-+
-+(define_insn_and_split "*iordi_notdi_zesidi"
-+  [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
-+	(ior:DI (not:DI (match_operand:DI 2 "s_register_operand" "0,?r"))
-+		(zero_extend:DI
-+		 (match_operand:SI 1 "s_register_operand" "r,r"))))]
-+  "TARGET_THUMB2"
-+  "#"
-+  "TARGET_THUMB2 && reload_completed"
-+  [(set (match_dup 0) (ior:SI (not:SI (match_dup 2)) (match_dup 1)))
-+   (set (match_dup 3) (not:SI (match_dup 4)))]
-+  "
-+  {
-+    operands[3] = gen_highpart (SImode, operands[0]);
-+    operands[0] = gen_lowpart (SImode, operands[0]);
-+    operands[1] = gen_lowpart (SImode, operands[1]);
-+    operands[4] = gen_highpart (SImode, operands[2]);
-+    operands[2] = gen_lowpart (SImode, operands[2]);
-+  }"
-+  [(set_attr "length" "8")
-+   (set_attr "predicable" "yes")
-+   (set_attr "predicable_short_it" "no")
-+   (set_attr "type" "multiple")]
-+)
-+
-+(define_insn_and_split "*iordi_notsesidi_di"
-+  [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
-+	(ior:DI (not:DI (sign_extend:DI
-+			 (match_operand:SI 2 "s_register_operand" "r,r")))
-+		(match_operand:DI 1 "s_register_operand" "0,r")))]
-+  "TARGET_THUMB2"
-+  "#"
-+  "TARGET_THUMB2 && reload_completed"
-+  [(set (match_dup 0) (ior:SI (not:SI (match_dup 2)) (match_dup 1)))
-+   (set (match_dup 3) (ior:SI (not:SI
-+				(ashiftrt:SI (match_dup 2) (const_int 31)))
-+			       (match_dup 4)))]
-+  "
-+  {
-+    operands[3] = gen_highpart (SImode, operands[0]);
-+    operands[0] = gen_lowpart (SImode, operands[0]);
-+    operands[4] = gen_highpart (SImode, operands[1]);
-+    operands[1] = gen_lowpart (SImode, operands[1]);
-+  }"
-+  [(set_attr "length" "8")
-+   (set_attr "predicable" "yes")
-+   (set_attr "predicable_short_it" "no")
-+   (set_attr "type" "multiple")]
-+)
-+
- (define_insn "*orsi_notsi_si"
-   [(set (match_operand:SI 0 "s_register_operand" "=r")
- 	(ior:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
---- a/src/gcc/config/arm/arm.c
-+++ b/src/gcc/config/arm/arm.c
-@@ -50,6 +50,7 @@
- #include "except.h"
- #include "tm_p.h"
- #include "target.h"
-+#include "sched-int.h"
- #include "target-def.h"
- #include "debug.h"
- #include "langhooks.h"
-@@ -59,6 +60,7 @@
- #include "params.h"
- #include "opts.h"
- #include "dumpfile.h"
-+#include "gimple-expr.h"
- 
- /* Forward definitions of types.  */
- typedef struct minipool_node    Mnode;
-@@ -93,6 +95,7 @@
- static bool thumb_force_lr_save (void);
- static unsigned arm_size_return_regs (void);
- static bool arm_assemble_integer (rtx, unsigned int, int);
-+static void arm_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update);
- static void arm_print_operand (FILE *, rtx, int);
- static void arm_print_operand_address (FILE *, rtx);
- static bool arm_print_operand_punct_valid_p (unsigned char code);
-@@ -584,6 +587,9 @@
- #undef TARGET_MANGLE_TYPE
- #define TARGET_MANGLE_TYPE arm_mangle_type
- 
-+#undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
-+#define TARGET_ATOMIC_ASSIGN_EXPAND_FENV arm_atomic_assign_expand_fenv
-+
- #undef TARGET_BUILD_BUILTIN_VA_LIST
- #define TARGET_BUILD_BUILTIN_VA_LIST arm_build_builtin_va_list
- #undef TARGET_EXPAND_BUILTIN_VA_START
-@@ -985,6 +991,7 @@
-     COSTS_N_INSNS (1),	/* bfi.  */
-     COSTS_N_INSNS (1),	/* bfx.  */
-     0,			/* clz.  */
-+    0,			/* rev.  */
-     0,			/* non_exec.  */
-     true		/* non_exec_costs_exec.  */
-   },
-@@ -1068,7 +1075,210 @@
-   }
- };
- 
-+const struct cpu_cost_table cortexa8_extra_costs =
-+{
-+  /* ALU */
-+  {
-+    0,			/* arith.  */
-+    0,			/* logical.  */
-+    COSTS_N_INSNS (1),	/* shift.  */
-+    0,			/* shift_reg.  */
-+    COSTS_N_INSNS (1),	/* arith_shift.  */
-+    0,			/* arith_shift_reg.  */
-+    COSTS_N_INSNS (1),	/* log_shift.  */
-+    0,			/* log_shift_reg.  */
-+    0,			/* extend.  */
-+    0,			/* extend_arith.  */
-+    0,			/* bfi.  */
-+    0,			/* bfx.  */
-+    0,			/* clz.  */
-+    0,			/* rev.  */
-+    0,			/* non_exec.  */
-+    true		/* non_exec_costs_exec.  */
-+  },
-+  {
-+    /* MULT SImode */
-+    {
-+      COSTS_N_INSNS (1),	/* simple.  */
-+      COSTS_N_INSNS (1),	/* flag_setting.  */
-+      COSTS_N_INSNS (1),	/* extend.  */
-+      COSTS_N_INSNS (1),	/* add.  */
-+      COSTS_N_INSNS (1),	/* extend_add.  */
-+      COSTS_N_INSNS (30)	/* idiv.  No HW div on Cortex A8.  */
-+    },
-+    /* MULT DImode */
-+    {
-+      0,			/* simple (N/A).  */
-+      0,			/* flag_setting (N/A).  */
-+      COSTS_N_INSNS (2),	/* extend.  */
-+      0,			/* add (N/A).  */
-+      COSTS_N_INSNS (2),	/* extend_add.  */
-+      0				/* idiv (N/A).  */
-+    }
-+  },
-+  /* LD/ST */
-+  {
-+    COSTS_N_INSNS (1),	/* load.  */
-+    COSTS_N_INSNS (1),	/* load_sign_extend.  */
-+    COSTS_N_INSNS (1),	/* ldrd.  */
-+    COSTS_N_INSNS (1),	/* ldm_1st.  */
-+    1,			/* ldm_regs_per_insn_1st.  */
-+    2,			/* ldm_regs_per_insn_subsequent.  */
-+    COSTS_N_INSNS (1),	/* loadf.  */
-+    COSTS_N_INSNS (1),	/* loadd.  */
-+    COSTS_N_INSNS (1),  /* load_unaligned.  */
-+    COSTS_N_INSNS (1),	/* store.  */
-+    COSTS_N_INSNS (1),	/* strd.  */
-+    COSTS_N_INSNS (1),	/* stm_1st.  */
-+    1,			/* stm_regs_per_insn_1st.  */
-+    2,			/* stm_regs_per_insn_subsequent.  */
-+    COSTS_N_INSNS (1),	/* storef.  */
-+    COSTS_N_INSNS (1),	/* stored.  */
-+    COSTS_N_INSNS (1)	/* store_unaligned.  */
-+  },
-+  {
-+    /* FP SFmode */
-+    {
-+      COSTS_N_INSNS (36),	/* div.  */
-+      COSTS_N_INSNS (11),	/* mult.  */
-+      COSTS_N_INSNS (20),	/* mult_addsub. */
-+      COSTS_N_INSNS (30),	/* fma.  */
-+      COSTS_N_INSNS (9),	/* addsub.  */
-+      COSTS_N_INSNS (3),	/* fpconst.  */
-+      COSTS_N_INSNS (3),	/* neg.  */
-+      COSTS_N_INSNS (6),	/* compare.  */
-+      COSTS_N_INSNS (4),	/* widen.  */
-+      COSTS_N_INSNS (4),	/* narrow.  */
-+      COSTS_N_INSNS (8),	/* toint.  */
-+      COSTS_N_INSNS (8),	/* fromint.  */
-+      COSTS_N_INSNS (8)		/* roundint.  */
-+    },
-+    /* FP DFmode */
-+    {
-+      COSTS_N_INSNS (64),	/* div.  */
-+      COSTS_N_INSNS (16),	/* mult.  */
-+      COSTS_N_INSNS (25),	/* mult_addsub.  */
-+      COSTS_N_INSNS (30),	/* fma.  */
-+      COSTS_N_INSNS (9),	/* addsub.  */
-+      COSTS_N_INSNS (3),	/* fpconst.  */
-+      COSTS_N_INSNS (3),	/* neg.  */
-+      COSTS_N_INSNS (6),	/* compare.  */
-+      COSTS_N_INSNS (6),	/* widen.  */
-+      COSTS_N_INSNS (6),	/* narrow.  */
-+      COSTS_N_INSNS (8),	/* toint.  */
-+      COSTS_N_INSNS (8),	/* fromint.  */
-+      COSTS_N_INSNS (8)		/* roundint.  */
-+    }
-+  },
-+  /* Vector */
-+  {
-+    COSTS_N_INSNS (1)	/* alu.  */
-+  }
-+};
- 
-+const struct cpu_cost_table cortexa5_extra_costs =
-+{
-+  /* ALU */
-+  {
-+    0,			/* arith.  */
-+    0,			/* logical.  */
-+    COSTS_N_INSNS (1),	/* shift.  */
-+    COSTS_N_INSNS (1),	/* shift_reg.  */
-+    COSTS_N_INSNS (1),	/* arith_shift.  */
-+    COSTS_N_INSNS (1),	/* arith_shift_reg.  */
-+    COSTS_N_INSNS (1),	/* log_shift.  */
-+    COSTS_N_INSNS (1),	/* log_shift_reg.  */
-+    COSTS_N_INSNS (1),	/* extend.  */
-+    COSTS_N_INSNS (1),	/* extend_arith.  */
-+    COSTS_N_INSNS (1),	/* bfi.  */
-+    COSTS_N_INSNS (1),	/* bfx.  */
-+    COSTS_N_INSNS (1),	/* clz.  */
-+    COSTS_N_INSNS (1),	/* rev.  */
-+    0,			/* non_exec.  */
-+    true		/* non_exec_costs_exec.  */
-+  },
-+
-+  {
-+    /* MULT SImode */
-+    {
-+      0,			/* simple.  */
-+      COSTS_N_INSNS (1),	/* flag_setting.  */
-+      COSTS_N_INSNS (1),	/* extend.  */
-+      COSTS_N_INSNS (1),	/* add.  */
-+      COSTS_N_INSNS (1),	/* extend_add.  */
-+      COSTS_N_INSNS (7)		/* idiv.  */
-+    },
-+    /* MULT DImode */
-+    {
-+      0,			/* simple (N/A).  */
-+      0,			/* flag_setting (N/A).  */
-+      COSTS_N_INSNS (1),	/* extend.  */
-+      0,			/* add.  */
-+      COSTS_N_INSNS (2),	/* extend_add.  */
-+      0				/* idiv (N/A).  */
-+    }
-+  },
-+  /* LD/ST */
-+  {
-+    COSTS_N_INSNS (1),	/* load.  */
-+    COSTS_N_INSNS (1),	/* load_sign_extend.  */
-+    COSTS_N_INSNS (6),	/* ldrd.  */
-+    COSTS_N_INSNS (1),	/* ldm_1st.  */
-+    1,			/* ldm_regs_per_insn_1st.  */
-+    2,			/* ldm_regs_per_insn_subsequent.  */
-+    COSTS_N_INSNS (2),	/* loadf.  */
-+    COSTS_N_INSNS (4),	/* loadd.  */
-+    COSTS_N_INSNS (1),	/* load_unaligned.  */
-+    COSTS_N_INSNS (1),	/* store.  */
-+    COSTS_N_INSNS (3),	/* strd.  */
-+    COSTS_N_INSNS (1),	/* stm_1st.  */
-+    1,			/* stm_regs_per_insn_1st.  */
-+    2,			/* stm_regs_per_insn_subsequent.  */
-+    COSTS_N_INSNS (2),	/* storef.  */
-+    COSTS_N_INSNS (2),	/* stored.  */
-+    COSTS_N_INSNS (1)	/* store_unaligned.  */
-+  },
-+  {
-+    /* FP SFmode */
-+    {
-+      COSTS_N_INSNS (15),	/* div.  */
-+      COSTS_N_INSNS (3),	/* mult.  */
-+      COSTS_N_INSNS (7),	/* mult_addsub. */
-+      COSTS_N_INSNS (7),	/* fma.  */
-+      COSTS_N_INSNS (3),	/* addsub.  */
-+      COSTS_N_INSNS (3),	/* fpconst.  */
-+      COSTS_N_INSNS (3),	/* neg.  */
-+      COSTS_N_INSNS (3),	/* compare.  */
-+      COSTS_N_INSNS (3),	/* widen.  */
-+      COSTS_N_INSNS (3),	/* narrow.  */
-+      COSTS_N_INSNS (3),	/* toint.  */
-+      COSTS_N_INSNS (3),	/* fromint.  */
-+      COSTS_N_INSNS (3)		/* roundint.  */
-+    },
-+    /* FP DFmode */
-+    {
-+      COSTS_N_INSNS (30),	/* div.  */
-+      COSTS_N_INSNS (6),	/* mult.  */
-+      COSTS_N_INSNS (10),	/* mult_addsub.  */
-+      COSTS_N_INSNS (7),	/* fma.  */
-+      COSTS_N_INSNS (3),	/* addsub.  */
-+      COSTS_N_INSNS (3),	/* fpconst.  */
-+      COSTS_N_INSNS (3),	/* neg.  */
-+      COSTS_N_INSNS (3),	/* compare.  */
-+      COSTS_N_INSNS (3),	/* widen.  */
-+      COSTS_N_INSNS (3),	/* narrow.  */
-+      COSTS_N_INSNS (3),	/* toint.  */
-+      COSTS_N_INSNS (3),	/* fromint.  */
-+      COSTS_N_INSNS (3)		/* roundint.  */
-+    }
-+  },
-+  /* Vector */
-+  {
-+    COSTS_N_INSNS (1)	/* alu.  */
-+  }
-+};
-+
-+
- const struct cpu_cost_table cortexa7_extra_costs =
- {
-   /* ALU */
-@@ -1086,6 +1296,7 @@
-     COSTS_N_INSNS (1),	/* bfi.  */
-     COSTS_N_INSNS (1),	/* bfx.  */
-     COSTS_N_INSNS (1),	/* clz.  */
-+    COSTS_N_INSNS (1),	/* rev.  */
-     0,			/* non_exec.  */
-     true		/* non_exec_costs_exec.  */
-   },
-@@ -1187,6 +1398,7 @@
-     0,			/* bfi.  */
-     COSTS_N_INSNS (1),	/* bfx.  */
-     COSTS_N_INSNS (1),	/* clz.  */
-+    COSTS_N_INSNS (1),	/* rev.  */
-     0,			/* non_exec.  */
-     true		/* non_exec_costs_exec.  */
-   },
-@@ -1287,6 +1499,7 @@
-     COSTS_N_INSNS (1),	/* bfi.  */
-     0,			/* bfx.  */
-     0,			/* clz.  */
-+    0,			/* rev.  */
-     0,			/* non_exec.  */
-     true		/* non_exec_costs_exec.  */
-   },
-@@ -1387,6 +1600,7 @@
-     0,			/* bfi.  */
-     0,			/* bfx.  */
-     0,			/* clz.  */
-+    0,			/* rev.  */
-     COSTS_N_INSNS (1),	/* non_exec.  */
-     false		/* non_exec_costs_exec.  */
-   },
-@@ -1483,7 +1697,8 @@
-   false,					/* Prefer LDRD/STRD.  */
-   {true, true},					/* Prefer non short circuit.  */
-   &arm_default_vec_cost,                        /* Vectorizer costs.  */
--  false                                         /* Prefer Neon for 64-bits bitops.  */
-+  false,                                        /* Prefer Neon for 64-bits bitops.  */
-+  false, false                                  /* Prefer 32-bit encodings.  */
- };
- 
- const struct tune_params arm_fastmul_tune =
-@@ -1499,7 +1714,8 @@
-   false,					/* Prefer LDRD/STRD.  */
-   {true, true},					/* Prefer non short circuit.  */
-   &arm_default_vec_cost,                        /* Vectorizer costs.  */
--  false                                         /* Prefer Neon for 64-bits bitops.  */
-+  false,                                        /* Prefer Neon for 64-bits bitops.  */
-+  false, false                                  /* Prefer 32-bit encodings.  */
- };
- 
- /* StrongARM has early execution of branches, so a sequence that is worth
-@@ -1518,7 +1734,8 @@
-   false,					/* Prefer LDRD/STRD.  */
-   {true, true},					/* Prefer non short circuit.  */
-   &arm_default_vec_cost,                        /* Vectorizer costs.  */
--  false                                         /* Prefer Neon for 64-bits bitops.  */
-+  false,                                        /* Prefer Neon for 64-bits bitops.  */
-+  false, false                                  /* Prefer 32-bit encodings.  */
- };
- 
- const struct tune_params arm_xscale_tune =
-@@ -1534,7 +1751,8 @@
-   false,					/* Prefer LDRD/STRD.  */
-   {true, true},					/* Prefer non short circuit.  */
-   &arm_default_vec_cost,                        /* Vectorizer costs.  */
--  false                                         /* Prefer Neon for 64-bits bitops.  */
-+  false,                                        /* Prefer Neon for 64-bits bitops.  */
-+  false, false                                  /* Prefer 32-bit encodings.  */
- };
- 
- const struct tune_params arm_9e_tune =
-@@ -1550,7 +1768,8 @@
-   false,					/* Prefer LDRD/STRD.  */
-   {true, true},					/* Prefer non short circuit.  */
-   &arm_default_vec_cost,                        /* Vectorizer costs.  */
--  false                                         /* Prefer Neon for 64-bits bitops.  */
-+  false,                                        /* Prefer Neon for 64-bits bitops.  */
-+  false, false                                  /* Prefer 32-bit encodings.  */
- };
- 
- const struct tune_params arm_v6t2_tune =
-@@ -1566,7 +1785,8 @@
-   false,					/* Prefer LDRD/STRD.  */
-   {true, true},					/* Prefer non short circuit.  */
-   &arm_default_vec_cost,                        /* Vectorizer costs.  */
--  false                                         /* Prefer Neon for 64-bits bitops.  */
-+  false,                                        /* Prefer Neon for 64-bits bitops.  */
-+  false, false                                  /* Prefer 32-bit encodings.  */
- };
- 
- /* Generic Cortex tuning.  Use more specific tunings if appropriate.  */
-@@ -1583,9 +1803,27 @@
-   false,					/* Prefer LDRD/STRD.  */
-   {true, true},					/* Prefer non short circuit.  */
-   &arm_default_vec_cost,                        /* Vectorizer costs.  */
--  false                                         /* Prefer Neon for 64-bits bitops.  */
-+  false,                                        /* Prefer Neon for 64-bits bitops.  */
-+  false, false                                  /* Prefer 32-bit encodings.  */
- };
- 
-+const struct tune_params arm_cortex_a8_tune =
-+{
-+  arm_9e_rtx_costs,
-+  &cortexa8_extra_costs,
-+  NULL,						/* Sched adj cost.  */
-+  1,						/* Constant limit.  */
-+  5,						/* Max cond insns.  */
-+  ARM_PREFETCH_NOT_BENEFICIAL,
-+  false,					/* Prefer constant pool.  */
-+  arm_default_branch_cost,
-+  false,					/* Prefer LDRD/STRD.  */
-+  {true, true},					/* Prefer non short circuit.  */
-+  &arm_default_vec_cost,                        /* Vectorizer costs.  */
-+  false,                                        /* Prefer Neon for 64-bits bitops.  */
-+  false, false                                  /* Prefer 32-bit encodings.  */
-+};
-+
- const struct tune_params arm_cortex_a7_tune =
- {
-   arm_9e_rtx_costs,
-@@ -1599,7 +1837,8 @@
-   false,					/* Prefer LDRD/STRD.  */
-   {true, true},					/* Prefer non short circuit.  */
-   &arm_default_vec_cost,			/* Vectorizer costs.  */
--  false						/* Prefer Neon for 64-bits bitops.  */
-+  false,					/* Prefer Neon for 64-bits bitops.  */
-+  false, false                                  /* Prefer 32-bit encodings.  */
- };
- 
- const struct tune_params arm_cortex_a15_tune =
-@@ -1615,7 +1854,8 @@
-   true,						/* Prefer LDRD/STRD.  */
-   {true, true},					/* Prefer non short circuit.  */
-   &arm_default_vec_cost,                        /* Vectorizer costs.  */
--  false                                         /* Prefer Neon for 64-bits bitops.  */
-+  false,                                        /* Prefer Neon for 64-bits bitops.  */
-+  true, true                                    /* Prefer 32-bit encodings.  */
- };
- 
- const struct tune_params arm_cortex_a53_tune =
-@@ -1631,7 +1871,8 @@
-   false,					/* Prefer LDRD/STRD.  */
-   {true, true},					/* Prefer non short circuit.  */
-   &arm_default_vec_cost,			/* Vectorizer costs.  */
--  false						/* Prefer Neon for 64-bits bitops.  */
-+  false,					/* Prefer Neon for 64-bits bitops.  */
-+  false, false                                  /* Prefer 32-bit encodings.  */
- };
- 
- const struct tune_params arm_cortex_a57_tune =
-@@ -1647,7 +1888,8 @@
-   true,                                       /* Prefer LDRD/STRD.  */
-   {true, true},                                /* Prefer non short circuit.  */
-   &arm_default_vec_cost,                       /* Vectorizer costs.  */
--  false                                        /* Prefer Neon for 64-bits bitops.  */
-+  false,                                       /* Prefer Neon for 64-bits bitops.  */
-+  true, true                                   /* Prefer 32-bit encodings.  */
- };
- 
- /* Branches can be dual-issued on Cortex-A5, so conditional execution is
-@@ -1656,7 +1898,7 @@
- const struct tune_params arm_cortex_a5_tune =
- {
-   arm_9e_rtx_costs,
--  NULL,
-+  &cortexa5_extra_costs,
-   NULL,						/* Sched adj cost.  */
-   1,						/* Constant limit.  */
-   1,						/* Max cond insns.  */
-@@ -1666,7 +1908,8 @@
-   false,					/* Prefer LDRD/STRD.  */
-   {false, false},				/* Prefer non short circuit.  */
-   &arm_default_vec_cost,                        /* Vectorizer costs.  */
--  false                                         /* Prefer Neon for 64-bits bitops.  */
-+  false,                                        /* Prefer Neon for 64-bits bitops.  */
-+  false, false                                  /* Prefer 32-bit encodings.  */
- };
- 
- const struct tune_params arm_cortex_a9_tune =
-@@ -1682,7 +1925,8 @@
-   false,					/* Prefer LDRD/STRD.  */
-   {true, true},					/* Prefer non short circuit.  */
-   &arm_default_vec_cost,                        /* Vectorizer costs.  */
--  false                                         /* Prefer Neon for 64-bits bitops.  */
-+  false,                                        /* Prefer Neon for 64-bits bitops.  */
-+  false, false                                  /* Prefer 32-bit encodings.  */
- };
- 
- const struct tune_params arm_cortex_a12_tune =
-@@ -1698,7 +1942,8 @@
-   true,						/* Prefer LDRD/STRD.  */
-   {true, true},					/* Prefer non short circuit.  */
-   &arm_default_vec_cost,                        /* Vectorizer costs.  */
--  false                                         /* Prefer Neon for 64-bits bitops.  */
-+  false,                                        /* Prefer Neon for 64-bits bitops.  */
-+  false, false                                  /* Prefer 32-bit encodings.  */
- };
- 
- /* armv7m tuning.  On Cortex-M4 cores for example, MOVW/MOVT take a single
-@@ -1721,7 +1966,8 @@
-   false,					/* Prefer LDRD/STRD.  */
-   {false, false},				/* Prefer non short circuit.  */
-   &arm_default_vec_cost,                        /* Vectorizer costs.  */
--  false                                         /* Prefer Neon for 64-bits bitops.  */
-+  false,                                        /* Prefer Neon for 64-bits bitops.  */
-+  false, false                                  /* Prefer 32-bit encodings.  */
- };
- 
- /* The arm_v6m_tune is duplicated from arm_cortex_tune, rather than
-@@ -1739,7 +1985,8 @@
-   false,					/* Prefer LDRD/STRD.  */
-   {false, false},				/* Prefer non short circuit.  */
-   &arm_default_vec_cost,                        /* Vectorizer costs.  */
--  false                                         /* Prefer Neon for 64-bits bitops.  */
-+  false,                                        /* Prefer Neon for 64-bits bitops.  */
-+  false, false                                  /* Prefer 32-bit encodings.  */
- };
- 
- const struct tune_params arm_fa726te_tune =
-@@ -1755,7 +2002,8 @@
-   false,					/* Prefer LDRD/STRD.  */
-   {true, true},					/* Prefer non short circuit.  */
-   &arm_default_vec_cost,                        /* Vectorizer costs.  */
--  false                                         /* Prefer Neon for 64-bits bitops.  */
-+  false,                                        /* Prefer Neon for 64-bits bitops.  */
-+  false, false                                  /* Prefer 32-bit encodings.  */
- };
- 
- 
-@@ -2806,7 +3054,7 @@
-      prefer_neon_for_64bits = true;
- 
-   /* Use the alternative scheduling-pressure algorithm by default.  */
--  maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM, 2,
-+  maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM, SCHED_PRESSURE_MODEL,
-                          global_options.x_param_values,
-                          global_options_set.x_param_values);
- 
-@@ -6079,11 +6327,6 @@
-   if (TARGET_VXWORKS_RTP && flag_pic && !targetm.binds_local_p (decl))
-     return false;
- 
--  /* Cannot tail-call to long calls, since these are out of range of
--     a branch instruction.  */
--  if (decl && arm_is_long_call_p (decl))
--    return false;
--
-   /* If we are interworking and the function is not declared static
-      then we can't tail-call it unless we know that it exists in this
-      compilation unit (since it might be a Thumb routine).  */
-@@ -9337,6 +9580,47 @@
-       *cost = LIBCALL_COST (2);
-       return false;
- 
-+    case BSWAP:
-+      if (arm_arch6)
-+        {
-+          if (mode == SImode)
-+            {
-+              *cost = COSTS_N_INSNS (1);
-+              if (speed_p)
-+                *cost += extra_cost->alu.rev;
-+
-+              return false;
-+            }
-+        }
-+      else
-+        {
-+        /* No rev instruction available.  Look at arm_legacy_rev
-+           and thumb_legacy_rev for the form of RTL used then.  */
-+          if (TARGET_THUMB)
-+            {
-+              *cost = COSTS_N_INSNS (10);
-+
-+              if (speed_p)
-+                {
-+                  *cost += 6 * extra_cost->alu.shift;
-+                  *cost += 3 * extra_cost->alu.logical;
-+                }
-+            }
-+          else
-+            {
-+              *cost = COSTS_N_INSNS (5);
-+
-+              if (speed_p)
-+                {
-+                  *cost += 2 * extra_cost->alu.shift;
-+                  *cost += extra_cost->alu.arith_shift;
-+                  *cost += 2 * extra_cost->alu.logical;
-+                }
-+            }
-+          return true;
-+        }
-+      return false;
-+
-     case MINUS:
-       if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
- 	  && (mode == SFmode || !TARGET_VFP_SINGLE))
-@@ -9719,8 +10003,17 @@
-       /* Vector mode?  */
-       *cost = LIBCALL_COST (2);
-       return false;
-+    case IOR:
-+      if (mode == SImode && arm_arch6 && aarch_rev16_p (x))
-+        {
-+          *cost = COSTS_N_INSNS (1);
-+          if (speed_p)
-+            *cost += extra_cost->alu.rev;
- 
--    case AND: case XOR: case IOR:
-+          return true;
-+        }
-+    /* Fall through.  */
-+    case AND: case XOR:
-       if (mode == SImode)
- 	{
- 	  enum rtx_code subcode = GET_CODE (XEXP (x, 0));
-@@ -10619,6 +10912,36 @@
-       *cost = LIBCALL_COST (1);
-       return false;
- 
-+    case FMA:
-+      if (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA)
-+        {
-+          rtx op0 = XEXP (x, 0);
-+          rtx op1 = XEXP (x, 1);
-+          rtx op2 = XEXP (x, 2);
-+
-+          *cost = COSTS_N_INSNS (1);
-+
-+          /* vfms or vfnma.  */
-+          if (GET_CODE (op0) == NEG)
-+            op0 = XEXP (op0, 0);
-+
-+          /* vfnms or vfnma.  */
-+          if (GET_CODE (op2) == NEG)
-+            op2 = XEXP (op2, 0);
-+
-+          *cost += rtx_cost (op0, FMA, 0, speed_p);
-+          *cost += rtx_cost (op1, FMA, 1, speed_p);
-+          *cost += rtx_cost (op2, FMA, 2, speed_p);
-+
-+          if (speed_p)
-+            *cost += extra_cost->fp[mode ==DFmode].fma;
-+
-+          return true;
-+        }
-+
-+      *cost = LIBCALL_COST (3);
-+      return false;
-+
-     case FIX:
-     case UNSIGNED_FIX:
-       if (TARGET_HARD_FLOAT)
-@@ -10669,10 +10992,16 @@
-       return true;
- 
-     case ASM_OPERANDS:
--      /* Just a guess.  Cost one insn per input.  */
--      *cost = COSTS_N_INSNS (ASM_OPERANDS_INPUT_LENGTH (x));
--      return true;
-+      {
-+      /* Just a guess.  Guess number of instructions in the asm
-+         plus one insn per input.  Always a minimum of COSTS_N_INSNS (1)
-+         though (see PR60663).  */
-+        int asm_length = MAX (1, asm_str_count (ASM_OPERANDS_TEMPLATE (x)));
-+        int num_operands = ASM_OPERANDS_INPUT_LENGTH (x);
- 
-+        *cost = COSTS_N_INSNS (asm_length + num_operands);
-+        return true;
-+      }
-     default:
-       if (mode != VOIDmode)
- 	*cost = COSTS_N_INSNS (ARM_NUM_REGS (mode));
-@@ -12566,7 +12895,11 @@
-       || (type == 0 && GET_CODE (ind) == PRE_DEC))
-     return arm_address_register_rtx_p (XEXP (ind, 0), 0);
- 
--  /* FIXME: vld1 allows register post-modify.  */
-+  /* Allow post-increment by register for VLDn */
-+  if (type == 2 && GET_CODE (ind) == POST_MODIFY
-+      && GET_CODE (XEXP (ind, 1)) == PLUS
-+      && REG_P (XEXP (XEXP (ind, 1), 1)))
-+     return true;
- 
-   /* Match:
-      (plus (reg)
-@@ -16787,9 +17120,20 @@
-   compute_bb_for_insn ();
-   df_analyze ();
- 
-+  enum Convert_Action {SKIP, CONV, SWAP_CONV};
-+
-   FOR_EACH_BB_FN (bb, cfun)
-     {
-+      if (current_tune->disparage_flag_setting_t16_encodings
-+	  && optimize_bb_for_speed_p (bb))
-+	continue;
-+
-       rtx insn;
-+      Convert_Action action = SKIP;
-+      Convert_Action action_for_partial_flag_setting
-+	= (current_tune->disparage_partial_flag_setting_t16_encodings
-+	   && optimize_bb_for_speed_p (bb))
-+	  ? SKIP : CONV;
- 
-       COPY_REG_SET (&live, DF_LR_OUT (bb));
-       df_simulate_initialize_backwards (bb, &live);
-@@ -16799,7 +17143,7 @@
- 	      && !REGNO_REG_SET_P (&live, CC_REGNUM)
- 	      && GET_CODE (PATTERN (insn)) == SET)
- 	    {
--	      enum {SKIP, CONV, SWAP_CONV} action = SKIP;
-+	      action = SKIP;
- 	      rtx pat = PATTERN (insn);
- 	      rtx dst = XEXP (pat, 0);
- 	      rtx src = XEXP (pat, 1);
-@@ -16880,10 +17224,11 @@
- 		      /* ANDS <Rdn>,<Rm>  */
- 		      if (rtx_equal_p (dst, op0)
- 			  && low_register_operand (op1, SImode))
--			action = CONV;
-+			action = action_for_partial_flag_setting;
- 		      else if (rtx_equal_p (dst, op1)
- 			       && low_register_operand (op0, SImode))
--			action = SWAP_CONV;
-+			action = action_for_partial_flag_setting == SKIP
-+				 ? SKIP : SWAP_CONV;
- 		      break;
- 
- 		    case ASHIFTRT:
-@@ -16894,7 +17239,7 @@
- 		      /* LSLS <Rdn>,<Rm> */
- 		      if (rtx_equal_p (dst, op0)
- 			  && low_register_operand (op1, SImode))
--			action = CONV;
-+			action = action_for_partial_flag_setting;
- 		      /* ASRS <Rd>,<Rm>,#<imm5> */
- 		      /* LSRS <Rd>,<Rm>,#<imm5> */
- 		      /* LSLS <Rd>,<Rm>,#<imm5> */
-@@ -16901,7 +17246,7 @@
- 		      else if (low_register_operand (op0, SImode)
- 			       && CONST_INT_P (op1)
- 			       && IN_RANGE (INTVAL (op1), 0, 31))
--			action = CONV;
-+			action = action_for_partial_flag_setting;
- 		      break;
- 
- 		    case ROTATERT:
-@@ -16908,12 +17253,16 @@
- 		      /* RORS <Rdn>,<Rm>  */
- 		      if (rtx_equal_p (dst, op0)
- 			  && low_register_operand (op1, SImode))
--			action = CONV;
-+			action = action_for_partial_flag_setting;
- 		      break;
- 
- 		    case NOT:
-+		      /* MVNS <Rd>,<Rm>  */
-+		      if (low_register_operand (op0, SImode))
-+			action = action_for_partial_flag_setting;
-+		      break;
-+
- 		    case NEG:
--		      /* MVNS <Rd>,<Rm>  */
- 		      /* NEGS <Rd>,<Rm>  (a.k.a RSBS)  */
- 		      if (low_register_operand (op0, SImode))
- 			action = CONV;
-@@ -16923,7 +17272,7 @@
- 		      /* MOVS <Rd>,#<imm8>  */
- 		      if (CONST_INT_P (src)
- 			  && IN_RANGE (INTVAL (src), 0, 255))
--			action = CONV;
-+			action = action_for_partial_flag_setting;
- 		      break;
- 
- 		    case REG:
-@@ -17144,24 +17493,7 @@
- 
- /* Routines to output assembly language.  */
- 
--/* If the rtx is the correct value then return the string of the number.
--   In this way we can ensure that valid double constants are generated even
--   when cross compiling.  */
--const char *
--fp_immediate_constant (rtx x)
--{
--  REAL_VALUE_TYPE r;
--
--  if (!fp_consts_inited)
--    init_fp_table ();
--
--  REAL_VALUE_FROM_CONST_DOUBLE (r, x);
--
--  gcc_assert (REAL_VALUES_EQUAL (r, value_fp0));
--  return "0";
--}
--
--/* As for fp_immediate_constant, but value is passed directly, not in rtx.  */
-+/* Return string representation of passed in real value.  */
- static const char *
- fp_const_from_val (REAL_VALUE_TYPE *r)
- {
-@@ -17252,14 +17584,22 @@
- /* Output the assembly for a store multiple.  */
- 
- const char *
--vfp_output_fstmd (rtx * operands)
-+vfp_output_vstmd (rtx * operands)
- {
-   char pattern[100];
-   int p;
-   int base;
-   int i;
-+  rtx addr_reg = REG_P (XEXP (operands[0], 0))
-+		   ? XEXP (operands[0], 0)
-+		   : XEXP (XEXP (operands[0], 0), 0);
-+  bool push_p =  REGNO (addr_reg) == SP_REGNUM;
- 
--  strcpy (pattern, "fstmfdd%?\t%m0!, {%P1");
-+  if (push_p)
-+    strcpy (pattern, "vpush%?.64\t{%P1");
-+  else
-+    strcpy (pattern, "vstmdb%?.64\t%m0!, {%P1");
-+
-   p = strlen (pattern);
- 
-   gcc_assert (REG_P (operands[1]));
-@@ -17387,6 +17727,15 @@
-       require_pic_register ();
-       use_reg (&CALL_INSN_FUNCTION_USAGE (insn), cfun->machine->pic_reg);
-     }
-+
-+  if (TARGET_AAPCS_BASED)
-+    {
-+      /* For AAPCS, IP and CC can be clobbered by veneers inserted by the
-+         linker.  */
-+      rtx *fusage = &CALL_INSN_FUNCTION_USAGE (insn);
-+      clobber_reg (fusage, gen_rtx_REG (word_mode, IP_REGNUM));
-+      clobber_reg (fusage, gen_rtx_REG (word_mode, CC_REGNUM));
-+    }
- }
- 
- /* Output a 'call' insn.  */
-@@ -18066,19 +18415,19 @@
-   switch (GET_CODE (addr))
-     {
-     case PRE_DEC:
--      templ = "f%smdb%c%%?\t%%0!, {%%%s1}%s";
-+      templ = "v%smdb%%?.%s\t%%0!, {%%%s1}%s";
-       ops[0] = XEXP (addr, 0);
-       ops[1] = reg;
-       break;
- 
-     case POST_INC:
--      templ = "f%smia%c%%?\t%%0!, {%%%s1}%s";
-+      templ = "v%smia%%?.%s\t%%0!, {%%%s1}%s";
-       ops[0] = XEXP (addr, 0);
-       ops[1] = reg;
-       break;
- 
-     default:
--      templ = "f%s%c%%?\t%%%s0, %%1%s";
-+      templ = "v%sr%%?.%s\t%%%s0, %%1%s";
-       ops[0] = reg;
-       ops[1] = mem;
-       break;
-@@ -18086,7 +18435,7 @@
- 
-   sprintf (buff, templ,
- 	   load ? "ld" : "st",
--	   dp ? 'd' : 's',
-+	   dp ? "64" : "32",
- 	   dp ? "P" : "",
- 	   integer_p ? "\t%@ int" : "");
-   output_asm_insn (buff, ops);
-@@ -20426,6 +20775,18 @@
- 	{
- 	  int reg = -1;
- 
-+	  /* Register r3 is caller-saved.  Normally it does not need to be
-+	     saved on entry by the prologue.  However if we choose to save
-+	     it for padding then we may confuse the compiler into thinking
-+	     a prologue sequence is required when in fact it is not.  This
-+	     will occur when shrink-wrapping if r3 is used as a scratch
-+	     register and there are no other callee-saved writes.
-+
-+	     This situation can be avoided when other callee-saved registers
-+	     are available and r3 is not mandatory if we choose a callee-saved
-+	     register for padding.  */
-+	  bool prefer_callee_reg_p = false;
-+
- 	  /* If it is safe to use r3, then do so.  This sometimes
- 	     generates better code on Thumb-2 by avoiding the need to
- 	     use 32-bit push/pop instructions.  */
-@@ -20432,24 +20793,29 @@
-           if (! any_sibcall_could_use_r3 ()
- 	      && arm_size_return_regs () <= 12
- 	      && (offsets->saved_regs_mask & (1 << 3)) == 0
--              && (TARGET_THUMB2
-+	      && (TARGET_THUMB2
- 		  || !(TARGET_LDRD && current_tune->prefer_ldrd_strd)))
- 	    {
- 	      reg = 3;
-+	      if (!TARGET_THUMB2)
-+		prefer_callee_reg_p = true;
- 	    }
--	  else
--	    for (i = 4; i <= (TARGET_THUMB1 ? LAST_LO_REGNUM : 11); i++)
--	      {
--		/* Avoid fixed registers; they may be changed at
--		   arbitrary times so it's unsafe to restore them
--		   during the epilogue.  */
--		if (!fixed_regs[i]
--		    && (offsets->saved_regs_mask & (1 << i)) == 0)
--		  {
--		    reg = i;
--		    break;
--		  }
--	      }
-+	  if (reg == -1
-+	      || prefer_callee_reg_p)
-+	    {
-+	      for (i = 4; i <= (TARGET_THUMB1 ? LAST_LO_REGNUM : 11); i++)
-+		{
-+		  /* Avoid fixed registers; they may be changed at
-+		     arbitrary times so it's unsafe to restore them
-+		     during the epilogue.  */
-+		  if (!fixed_regs[i]
-+		      && (offsets->saved_regs_mask & (1 << i)) == 0)
-+		    {
-+		      reg = i;
-+		      break;
-+		    }
-+		}
-+	    }
- 
- 	  if (reg != -1)
- 	    {
-@@ -21039,7 +21405,15 @@
- }
- 
- 
--/* If CODE is 'd', then the X is a condition operand and the instruction
-+/* Globally reserved letters: acln
-+   Puncutation letters currently used: @_|?().!#
-+   Lower case letters currently used: bcdefhimpqtvwxyz
-+   Upper case letters currently used: ABCDFGHJKLMNOPQRSTU
-+   Letters previously used, but now deprecated/obsolete: sVWXYZ.
-+
-+   Note that the global reservation for 'c' is only for CONSTANT_ADDRESS_P.
-+
-+   If CODE is 'd', then the X is a condition operand and the instruction
-    should only be executed if the condition is true.
-    if CODE is 'D', then the X is a condition operand and the instruction
-    should only be executed if the condition is false: however, if the mode
-@@ -21179,6 +21553,19 @@
- 	}
-       return;
- 
-+    case 'b':
-+      /* Print the log2 of a CONST_INT.  */
-+      {
-+	HOST_WIDE_INT val;
-+
-+	if (!CONST_INT_P (x)
-+	    || (val = exact_log2 (INTVAL (x) & 0xffffffff)) < 0)
-+	  output_operand_lossage ("Unsupported operand for code '%c'", code);
-+	else
-+	  fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val);
-+      }
-+      return;
-+
-     case 'L':
-       /* The low 16 bits of an immediate constant.  */
-       fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL(x) & 0xffff);
-@@ -21421,7 +21808,7 @@
-        register.  */
-     case 'p':
-       {
--        int mode = GET_MODE (x);
-+        enum machine_mode mode = GET_MODE (x);
-         int regno;
- 
-         if (GET_MODE_SIZE (mode) != 8 || !REG_P (x))
-@@ -21445,7 +21832,7 @@
-     case 'P':
-     case 'q':
-       {
--	int mode = GET_MODE (x);
-+	enum machine_mode mode = GET_MODE (x);
- 	int is_quad = (code == 'q');
- 	int regno;
- 
-@@ -21481,7 +21868,7 @@
-     case 'e':
-     case 'f':
-       {
--        int mode = GET_MODE (x);
-+        enum machine_mode mode = GET_MODE (x);
-         int regno;
- 
-         if ((GET_MODE_SIZE (mode) != 16
-@@ -21563,6 +21950,7 @@
-       {
- 	rtx addr;
- 	bool postinc = FALSE;
-+	rtx postinc_reg = NULL;
- 	unsigned align, memsize, align_bits;
- 
- 	gcc_assert (MEM_P (x));
-@@ -21572,6 +21960,11 @@
- 	    postinc = 1;
- 	    addr = XEXP (addr, 0);
- 	  }
-+	if (GET_CODE (addr) == POST_MODIFY)
-+	  {
-+	    postinc_reg = XEXP( XEXP (addr, 1), 1);
-+	    addr = XEXP (addr, 0);
-+	  }
- 	asm_fprintf (stream, "[%r", REGNO (addr));
- 
- 	/* We know the alignment of this access, so we can emit a hint in the
-@@ -21597,6 +21990,8 @@
- 
- 	if (postinc)
- 	  fputs("!", stream);
-+	if (postinc_reg)
-+	  asm_fprintf (stream, ", %r", REGNO (postinc_reg));
-       }
-       return;
- 
-@@ -21614,7 +22009,7 @@
-     /* Translate an S register number into a D register number and element index.  */
-     case 'y':
-       {
--        int mode = GET_MODE (x);
-+        enum machine_mode mode = GET_MODE (x);
-         int regno;
- 
-         if (GET_MODE_SIZE (mode) != 4 || !REG_P (x))
-@@ -21648,7 +22043,7 @@
-        number into a D register number and element index.  */
-     case 'z':
-       {
--        int mode = GET_MODE (x);
-+        enum machine_mode mode = GET_MODE (x);
-         int regno;
- 
-         if (GET_MODE_SIZE (mode) != 2 || !REG_P (x))
-@@ -21688,15 +22083,12 @@
- 	  break;
- 
- 	case CONST_DOUBLE:
--          if (TARGET_NEON)
--            {
--              char fpstr[20];
--              real_to_decimal (fpstr, CONST_DOUBLE_REAL_VALUE (x),
--			       sizeof (fpstr), 0, 1);
--              fprintf (stream, "#%s", fpstr);
--            }
--          else
--	    fprintf (stream, "#%s", fp_immediate_constant (x));
-+	  {
-+            char fpstr[20];
-+            real_to_decimal (fpstr, CONST_DOUBLE_REAL_VALUE (x),
-+			      sizeof (fpstr), 0, 1);
-+            fprintf (stream, "#%s", fpstr);
-+	  }
- 	  break;
- 
- 	default:
-@@ -22564,6 +22956,9 @@
- 	    || (TARGET_HARD_FLOAT && TARGET_VFP
- 		&& regno == VFPCC_REGNUM));
- 
-+  if (regno == CC_REGNUM && GET_MODE_CLASS (mode) != MODE_CC)
-+    return false;
-+
-   if (TARGET_THUMB1)
-     /* For the Thumb we only allow values bigger than SImode in
-        registers 0 - 6, so that there is always a second low
-@@ -22609,13 +23004,20 @@
-     }
- 
-   /* We allow almost any value to be stored in the general registers.
--     Restrict doubleword quantities to even register pairs so that we can
--     use ldrd.  Do not allow very large Neon structure opaque modes in
--     general registers; they would use too many.  */
-+     Restrict doubleword quantities to even register pairs in ARM state
-+     so that we can use ldrd.  Do not allow very large Neon structure
-+     opaque modes in general registers; they would use too many.  */
-   if (regno <= LAST_ARM_REGNUM)
--    return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0)
--      && ARM_NUM_REGS (mode) <= 4;
-+    {
-+      if (ARM_NUM_REGS (mode) > 4)
-+	  return FALSE;
- 
-+      if (TARGET_THUMB2)
-+	return TRUE;
-+
-+      return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0);
-+    }
-+
-   if (regno == FRAME_POINTER_REGNUM
-       || regno == ARG_POINTER_REGNUM)
-     /* We only allow integers in the fake hard registers.  */
-@@ -22653,6 +23055,9 @@
- enum reg_class
- arm_regno_class (int regno)
- {
-+  if (regno == PC_REGNUM)
-+    return NO_REGS;
-+
-   if (TARGET_THUMB1)
-     {
-       if (regno == STACK_POINTER_REGNUM)
-@@ -22826,10 +23231,12 @@
-   NEON_BINOP,
-   NEON_TERNOP,
-   NEON_UNOP,
-+  NEON_BSWAP,
-   NEON_GETLANE,
-   NEON_SETLANE,
-   NEON_CREATE,
-   NEON_RINT,
-+  NEON_COPYSIGNF,
-   NEON_DUP,
-   NEON_DUPLANE,
-   NEON_COMBINE,
-@@ -22847,7 +23254,6 @@
-   NEON_FLOAT_NARROW,
-   NEON_FIXCONV,
-   NEON_SELECT,
--  NEON_RESULTPAIR,
-   NEON_REINTERP,
-   NEON_VTBL,
-   NEON_VTBX,
-@@ -23216,6 +23622,9 @@
-   ARM_BUILTIN_CRC32CH,
-   ARM_BUILTIN_CRC32CW,
- 
-+  ARM_BUILTIN_GET_FPSCR,
-+  ARM_BUILTIN_SET_FPSCR,
-+
- #undef CRYPTO1
- #undef CRYPTO2
- #undef CRYPTO3
-@@ -23293,14 +23702,19 @@
- 
-   tree V8QI_type_node;
-   tree V4HI_type_node;
-+  tree V4UHI_type_node;
-   tree V4HF_type_node;
-   tree V2SI_type_node;
-+  tree V2USI_type_node;
-   tree V2SF_type_node;
-   tree V16QI_type_node;
-   tree V8HI_type_node;
-+  tree V8UHI_type_node;
-   tree V4SI_type_node;
-+  tree V4USI_type_node;
-   tree V4SF_type_node;
-   tree V2DI_type_node;
-+  tree V2UDI_type_node;
- 
-   tree intUQI_type_node;
-   tree intUHI_type_node;
-@@ -23312,27 +23726,6 @@
-   tree intCI_type_node;
-   tree intXI_type_node;
- 
--  tree V8QI_pointer_node;
--  tree V4HI_pointer_node;
--  tree V2SI_pointer_node;
--  tree V2SF_pointer_node;
--  tree V16QI_pointer_node;
--  tree V8HI_pointer_node;
--  tree V4SI_pointer_node;
--  tree V4SF_pointer_node;
--  tree V2DI_pointer_node;
--
--  tree void_ftype_pv8qi_v8qi_v8qi;
--  tree void_ftype_pv4hi_v4hi_v4hi;
--  tree void_ftype_pv2si_v2si_v2si;
--  tree void_ftype_pv2sf_v2sf_v2sf;
--  tree void_ftype_pdi_di_di;
--  tree void_ftype_pv16qi_v16qi_v16qi;
--  tree void_ftype_pv8hi_v8hi_v8hi;
--  tree void_ftype_pv4si_v4si_v4si;
--  tree void_ftype_pv4sf_v4sf_v4sf;
--  tree void_ftype_pv2di_v2di_v2di;
--
-   tree reinterp_ftype_dreg[NUM_DREG_TYPES][NUM_DREG_TYPES];
-   tree reinterp_ftype_qreg[NUM_QREG_TYPES][NUM_QREG_TYPES];
-   tree dreg_types[NUM_DREG_TYPES], qreg_types[NUM_QREG_TYPES];
-@@ -23396,6 +23789,12 @@
-   const_intDI_pointer_node = build_pointer_type (const_intDI_node);
-   const_float_pointer_node = build_pointer_type (const_float_node);
- 
-+  /* Unsigned integer types for various mode sizes.  */
-+  intUQI_type_node = make_unsigned_type (GET_MODE_PRECISION (QImode));
-+  intUHI_type_node = make_unsigned_type (GET_MODE_PRECISION (HImode));
-+  intUSI_type_node = make_unsigned_type (GET_MODE_PRECISION (SImode));
-+  intUDI_type_node = make_unsigned_type (GET_MODE_PRECISION (DImode));
-+  neon_intUTI_type_node = make_unsigned_type (GET_MODE_PRECISION (TImode));
-   /* Now create vector types based on our NEON element types.  */
-   /* 64-bit vectors.  */
-   V8QI_type_node =
-@@ -23402,10 +23801,14 @@
-     build_vector_type_for_mode (neon_intQI_type_node, V8QImode);
-   V4HI_type_node =
-     build_vector_type_for_mode (neon_intHI_type_node, V4HImode);
-+  V4UHI_type_node =
-+    build_vector_type_for_mode (intUHI_type_node, V4HImode);
-   V4HF_type_node =
-     build_vector_type_for_mode (neon_floatHF_type_node, V4HFmode);
-   V2SI_type_node =
-     build_vector_type_for_mode (neon_intSI_type_node, V2SImode);
-+  V2USI_type_node =
-+    build_vector_type_for_mode (intUSI_type_node, V2SImode);
-   V2SF_type_node =
-     build_vector_type_for_mode (neon_float_type_node, V2SFmode);
-   /* 128-bit vectors.  */
-@@ -23413,21 +23816,20 @@
-     build_vector_type_for_mode (neon_intQI_type_node, V16QImode);
-   V8HI_type_node =
-     build_vector_type_for_mode (neon_intHI_type_node, V8HImode);
-+  V8UHI_type_node =
-+    build_vector_type_for_mode (intUHI_type_node, V8HImode);
-   V4SI_type_node =
-     build_vector_type_for_mode (neon_intSI_type_node, V4SImode);
-+  V4USI_type_node =
-+    build_vector_type_for_mode (intUSI_type_node, V4SImode);
-   V4SF_type_node =
-     build_vector_type_for_mode (neon_float_type_node, V4SFmode);
-   V2DI_type_node =
-     build_vector_type_for_mode (neon_intDI_type_node, V2DImode);
-+  V2UDI_type_node =
-+    build_vector_type_for_mode (intUDI_type_node, V2DImode);
- 
--  /* Unsigned integer types for various mode sizes.  */
--  intUQI_type_node = make_unsigned_type (GET_MODE_PRECISION (QImode));
--  intUHI_type_node = make_unsigned_type (GET_MODE_PRECISION (HImode));
--  intUSI_type_node = make_unsigned_type (GET_MODE_PRECISION (SImode));
--  intUDI_type_node = make_unsigned_type (GET_MODE_PRECISION (DImode));
--  neon_intUTI_type_node = make_unsigned_type (GET_MODE_PRECISION (TImode));
- 
--
-   (*lang_hooks.types.register_builtin_type) (intUQI_type_node,
- 					     "__builtin_neon_uqi");
-   (*lang_hooks.types.register_builtin_type) (intUHI_type_node,
-@@ -23458,53 +23860,8 @@
-   (*lang_hooks.types.register_builtin_type) (intXI_type_node,
- 					     "__builtin_neon_xi");
- 
--  /* Pointers to vector types.  */
--  V8QI_pointer_node = build_pointer_type (V8QI_type_node);
--  V4HI_pointer_node = build_pointer_type (V4HI_type_node);
--  V2SI_pointer_node = build_pointer_type (V2SI_type_node);
--  V2SF_pointer_node = build_pointer_type (V2SF_type_node);
--  V16QI_pointer_node = build_pointer_type (V16QI_type_node);
--  V8HI_pointer_node = build_pointer_type (V8HI_type_node);
--  V4SI_pointer_node = build_pointer_type (V4SI_type_node);
--  V4SF_pointer_node = build_pointer_type (V4SF_type_node);
--  V2DI_pointer_node = build_pointer_type (V2DI_type_node);
--
--  /* Operations which return results as pairs.  */
--  void_ftype_pv8qi_v8qi_v8qi =
--    build_function_type_list (void_type_node, V8QI_pointer_node, V8QI_type_node,
--  			      V8QI_type_node, NULL);
--  void_ftype_pv4hi_v4hi_v4hi =
--    build_function_type_list (void_type_node, V4HI_pointer_node, V4HI_type_node,
--  			      V4HI_type_node, NULL);
--  void_ftype_pv2si_v2si_v2si =
--    build_function_type_list (void_type_node, V2SI_pointer_node, V2SI_type_node,
--  			      V2SI_type_node, NULL);
--  void_ftype_pv2sf_v2sf_v2sf =
--    build_function_type_list (void_type_node, V2SF_pointer_node, V2SF_type_node,
--  			      V2SF_type_node, NULL);
--  void_ftype_pdi_di_di =
--    build_function_type_list (void_type_node, intDI_pointer_node,
--			      neon_intDI_type_node, neon_intDI_type_node, NULL);
--  void_ftype_pv16qi_v16qi_v16qi =
--    build_function_type_list (void_type_node, V16QI_pointer_node,
--			      V16QI_type_node, V16QI_type_node, NULL);
--  void_ftype_pv8hi_v8hi_v8hi =
--    build_function_type_list (void_type_node, V8HI_pointer_node, V8HI_type_node,
--  			      V8HI_type_node, NULL);
--  void_ftype_pv4si_v4si_v4si =
--    build_function_type_list (void_type_node, V4SI_pointer_node, V4SI_type_node,
--  			      V4SI_type_node, NULL);
--  void_ftype_pv4sf_v4sf_v4sf =
--    build_function_type_list (void_type_node, V4SF_pointer_node, V4SF_type_node,
--  			      V4SF_type_node, NULL);
--  void_ftype_pv2di_v2di_v2di =
--    build_function_type_list (void_type_node, V2DI_pointer_node, V2DI_type_node,
--			      V2DI_type_node, NULL);
--
-   if (TARGET_CRYPTO && TARGET_HARD_FLOAT)
-   {
--    tree V4USI_type_node =
--      build_vector_type_for_mode (intUSI_type_node, V4SImode);
- 
-     tree V16UQI_type_node =
-       build_vector_type_for_mode (intUQI_type_node, V16QImode);
-@@ -23790,25 +24147,6 @@
- 	  }
- 	  break;
- 
--	case NEON_RESULTPAIR:
--	  {
--	    switch (insn_data[d->code].operand[1].mode)
--	      {
--	      case V8QImode: ftype = void_ftype_pv8qi_v8qi_v8qi; break;
--	      case V4HImode: ftype = void_ftype_pv4hi_v4hi_v4hi; break;
--	      case V2SImode: ftype = void_ftype_pv2si_v2si_v2si; break;
--	      case V2SFmode: ftype = void_ftype_pv2sf_v2sf_v2sf; break;
--	      case DImode: ftype = void_ftype_pdi_di_di; break;
--	      case V16QImode: ftype = void_ftype_pv16qi_v16qi_v16qi; break;
--	      case V8HImode: ftype = void_ftype_pv8hi_v8hi_v8hi; break;
--	      case V4SImode: ftype = void_ftype_pv4si_v4si_v4si; break;
--	      case V4SFmode: ftype = void_ftype_pv4sf_v4sf_v4sf; break;
--	      case V2DImode: ftype = void_ftype_pv2di_v2di_v2di; break;
--	      default: gcc_unreachable ();
--	      }
--	  }
--	  break;
--
- 	case NEON_REINTERP:
- 	  {
- 	    /* We iterate over NUM_DREG_TYPES doubleword types,
-@@ -23868,6 +24206,47 @@
- 	    ftype = build_function_type_list (return_type, eltype, NULL);
- 	    break;
- 	  }
-+	case NEON_BSWAP:
-+	{
-+	    tree eltype = NULL_TREE;
-+	    switch (insn_data[d->code].operand[1].mode)
-+	    {
-+	      case V4HImode:
-+	        eltype = V4UHI_type_node;
-+	        break;
-+	      case V8HImode:
-+	        eltype = V8UHI_type_node;
-+	        break;
-+	      case V2SImode:
-+	        eltype = V2USI_type_node;
-+	        break;
-+	      case V4SImode:
-+	        eltype = V4USI_type_node;
-+	        break;
-+	      case V2DImode:
-+	        eltype = V2UDI_type_node;
-+	        break;
-+	      default: gcc_unreachable ();
-+	    }
-+	    ftype = build_function_type_list (eltype, eltype, NULL);
-+	    break;
-+	}
-+	case NEON_COPYSIGNF:
-+	  {
-+	    tree eltype = NULL_TREE;
-+	    switch (insn_data[d->code].operand[1].mode)
-+	      {
-+	      case V2SFmode:
-+		eltype = V2SF_type_node;
-+		break;
-+	      case V4SFmode:
-+		eltype = V4SF_type_node;
-+		break;
-+	      default: gcc_unreachable ();
-+	      }
-+	    ftype = build_function_type_list (eltype, eltype, NULL);
-+	    break;
-+	  }
- 	default:
- 	  gcc_unreachable ();
- 	}
-@@ -24014,6 +24393,15 @@
-   IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
-   IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
- 
-+
-+#define FP_BUILTIN(L, U) \
-+  {0, CODE_FOR_##L, "__builtin_arm_"#L, ARM_BUILTIN_##U, \
-+   UNKNOWN, 0},
-+
-+  FP_BUILTIN (get_fpscr, GET_FPSCR)
-+  FP_BUILTIN (set_fpscr, SET_FPSCR)
-+#undef FP_BUILTIN
-+
- #define CRC32_BUILTIN(L, U) \
-   {0, CODE_FOR_##L, "__builtin_arm_"#L, ARM_BUILTIN_##U, \
-    UNKNOWN, 0},
-@@ -24528,6 +24916,21 @@
- 
-   if (TARGET_CRC32)
-     arm_init_crc32_builtins ();
-+
-+  if (TARGET_VFP && TARGET_HARD_FLOAT)
-+    {
-+      tree ftype_set_fpscr
-+	= build_function_type_list (void_type_node, unsigned_type_node, NULL);
-+      tree ftype_get_fpscr
-+	= build_function_type_list (unsigned_type_node, NULL);
-+
-+      arm_builtin_decls[ARM_BUILTIN_GET_FPSCR]
-+	= add_builtin_function ("__builtin_arm_ldfscr", ftype_get_fpscr,
-+				ARM_BUILTIN_GET_FPSCR, BUILT_IN_MD, NULL, NULL_TREE);
-+      arm_builtin_decls[ARM_BUILTIN_SET_FPSCR]
-+	= add_builtin_function ("__builtin_arm_stfscr", ftype_set_fpscr,
-+				ARM_BUILTIN_SET_FPSCR, BUILT_IN_MD, NULL, NULL_TREE);
-+    }
- }
- 
- /* Return the ARM builtin for CODE.  */
-@@ -25042,20 +25445,17 @@
-     case NEON_SPLIT:
-     case NEON_FLOAT_WIDEN:
-     case NEON_FLOAT_NARROW:
-+    case NEON_BSWAP:
-     case NEON_REINTERP:
-       return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
-         NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
- 
-+    case NEON_COPYSIGNF:
-     case NEON_COMBINE:
-     case NEON_VTBL:
-       return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
-         NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
- 
--    case NEON_RESULTPAIR:
--      return arm_expand_neon_args (target, icode, 0, type_mode, exp, fcode,
--        NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
--        NEON_ARG_STOP);
--
-     case NEON_LANEMUL:
-     case NEON_LANEMULL:
-     case NEON_LANEMULH:
-@@ -25117,24 +25517,6 @@
-   emit_move_insn (dest, gen_lowpart (GET_MODE (dest), src));
- }
- 
--/* Emit code to place a Neon pair result in memory locations (with equal
--   registers).  */
--void
--neon_emit_pair_result_insn (enum machine_mode mode,
--			    rtx (*intfn) (rtx, rtx, rtx, rtx), rtx destaddr,
--                            rtx op1, rtx op2)
--{
--  rtx mem = gen_rtx_MEM (mode, destaddr);
--  rtx tmp1 = gen_reg_rtx (mode);
--  rtx tmp2 = gen_reg_rtx (mode);
--
--  emit_insn (intfn (tmp1, op1, op2, tmp2));
--
--  emit_move_insn (mem, tmp1);
--  mem = adjust_address (mem, mode, GET_MODE_SIZE (mode));
--  emit_move_insn (mem, tmp2);
--}
--
- /* Set up OPERANDS for a register copy from SRC to DEST, taking care
-    not to early-clobber SRC registers in the process.
- 
-@@ -25255,6 +25637,25 @@
- 
-   switch (fcode)
-     {
-+    case ARM_BUILTIN_GET_FPSCR:
-+    case ARM_BUILTIN_SET_FPSCR:
-+      if (fcode == ARM_BUILTIN_GET_FPSCR)
-+	{
-+	  icode = CODE_FOR_get_fpscr;
-+	  target = gen_reg_rtx (SImode);
-+	  pat = GEN_FCN (icode) (target);
-+	}
-+      else
-+	{
-+	  target = NULL_RTX;
-+	  icode = CODE_FOR_set_fpscr;
-+	  arg0 = CALL_EXPR_ARG (exp, 0);
-+	  op0 = expand_normal (arg0);
-+	  pat = GEN_FCN (icode) (op0);
-+	}
-+      emit_insn (pat);
-+      return target;
-+
-     case ARM_BUILTIN_TEXTRMSB:
-     case ARM_BUILTIN_TEXTRMUB:
-     case ARM_BUILTIN_TEXTRMSH:
-@@ -25888,7 +26289,7 @@
-   int pops_needed;
-   unsigned available;
-   unsigned required;
--  int mode;
-+  enum machine_mode mode;
-   int size;
-   int restore_a4 = FALSE;
- 
-@@ -29555,10 +29956,10 @@
- {
-   enum machine_mode in_mode, out_mode;
-   int in_n, out_n;
-+  bool out_unsigned_p = TYPE_UNSIGNED (type_out);
- 
-   if (TREE_CODE (type_out) != VECTOR_TYPE
--      || TREE_CODE (type_in) != VECTOR_TYPE
--      || !(TARGET_NEON && TARGET_FPU_ARMV8 && flag_unsafe_math_optimizations))
-+      || TREE_CODE (type_in) != VECTOR_TYPE)
-     return NULL_TREE;
- 
-   out_mode = TYPE_MODE (TREE_TYPE (type_out));
-@@ -29570,7 +29971,13 @@
-    decl of the vectorized builtin for the appropriate vector mode.
-    NULL_TREE is returned if no such builtin is available.  */
- #undef ARM_CHECK_BUILTIN_MODE
--#define ARM_CHECK_BUILTIN_MODE(C) \
-+#define ARM_CHECK_BUILTIN_MODE(C)    \
-+  (TARGET_NEON && TARGET_FPU_ARMV8   \
-+   && flag_unsafe_math_optimizations \
-+   && ARM_CHECK_BUILTIN_MODE_1 (C))
-+
-+#undef ARM_CHECK_BUILTIN_MODE_1
-+#define ARM_CHECK_BUILTIN_MODE_1(C) \
-   (out_mode == SFmode && out_n == C \
-    && in_mode == SFmode && in_n == C)
- 
-@@ -29595,6 +30002,67 @@
-             return ARM_FIND_VRINT_VARIANT (vrintz);
-           case BUILT_IN_ROUNDF:
-             return ARM_FIND_VRINT_VARIANT (vrinta);
-+#undef ARM_CHECK_BUILTIN_MODE_1
-+#define ARM_CHECK_BUILTIN_MODE_1(C) \
-+  (out_mode == SImode && out_n == C \
-+   && in_mode == SFmode && in_n == C)
-+
-+#define ARM_FIND_VCVT_VARIANT(N) \
-+  (ARM_CHECK_BUILTIN_MODE (2) \
-+   ? arm_builtin_decl(ARM_BUILTIN_NEON_##N##v2sfv2si, false) \
-+   : (ARM_CHECK_BUILTIN_MODE (4) \
-+     ? arm_builtin_decl(ARM_BUILTIN_NEON_##N##v4sfv4si, false) \
-+     : NULL_TREE))
-+
-+#define ARM_FIND_VCVTU_VARIANT(N) \
-+  (ARM_CHECK_BUILTIN_MODE (2) \
-+   ? arm_builtin_decl(ARM_BUILTIN_NEON_##N##uv2sfv2si, false) \
-+   : (ARM_CHECK_BUILTIN_MODE (4) \
-+     ? arm_builtin_decl(ARM_BUILTIN_NEON_##N##uv4sfv4si, false) \
-+     : NULL_TREE))
-+          case BUILT_IN_LROUNDF:
-+            return out_unsigned_p
-+                     ? ARM_FIND_VCVTU_VARIANT (vcvta)
-+                     : ARM_FIND_VCVT_VARIANT (vcvta);
-+          case BUILT_IN_LCEILF:
-+            return out_unsigned_p
-+                     ? ARM_FIND_VCVTU_VARIANT (vcvtp)
-+                     : ARM_FIND_VCVT_VARIANT (vcvtp);
-+          case BUILT_IN_LFLOORF:
-+            return out_unsigned_p
-+                     ? ARM_FIND_VCVTU_VARIANT (vcvtm)
-+                     : ARM_FIND_VCVT_VARIANT (vcvtm);
-+#undef ARM_CHECK_BUILTIN_MODE
-+#define ARM_CHECK_BUILTIN_MODE(C, N) \
-+  (out_mode == N##mode && out_n == C \
-+   && in_mode == N##mode && in_n == C)
-+          case BUILT_IN_BSWAP16:
-+            if (ARM_CHECK_BUILTIN_MODE (4, HI))
-+              return arm_builtin_decl (ARM_BUILTIN_NEON_bswapv4hi, false);
-+            else if (ARM_CHECK_BUILTIN_MODE (8, HI))
-+              return arm_builtin_decl (ARM_BUILTIN_NEON_bswapv8hi, false);
-+            else
-+              return NULL_TREE;
-+          case BUILT_IN_BSWAP32:
-+            if (ARM_CHECK_BUILTIN_MODE (2, SI))
-+              return arm_builtin_decl (ARM_BUILTIN_NEON_bswapv2si, false);
-+            else if (ARM_CHECK_BUILTIN_MODE (4, SI))
-+              return arm_builtin_decl (ARM_BUILTIN_NEON_bswapv4si, false);
-+            else
-+              return NULL_TREE;
-+          case BUILT_IN_BSWAP64:
-+            if (ARM_CHECK_BUILTIN_MODE (2, DI))
-+              return arm_builtin_decl (ARM_BUILTIN_NEON_bswapv2di, false);
-+            else
-+              return NULL_TREE;
-+	  case BUILT_IN_COPYSIGNF:
-+	    if (ARM_CHECK_BUILTIN_MODE (2, SF))
-+              return arm_builtin_decl (ARM_BUILTIN_NEON_copysignfv2sf, false);
-+	    else if (ARM_CHECK_BUILTIN_MODE (4, SF))
-+              return arm_builtin_decl (ARM_BUILTIN_NEON_copysignfv4sf, false);
-+	    else
-+	      return NULL_TREE;
-+
-           default:
-             return NULL_TREE;
-         }
-@@ -29601,9 +30069,12 @@
-     }
-   return NULL_TREE;
- }
-+#undef ARM_FIND_VCVT_VARIANT
-+#undef ARM_FIND_VCVTU_VARIANT
- #undef ARM_CHECK_BUILTIN_MODE
- #undef ARM_FIND_VRINT_VARIANT
- 
-+
- /* The AAPCS sets the maximum alignment of a vector to 64 bits.  */
- static HOST_WIDE_INT
- arm_vector_alignment (const_tree type)
-@@ -31174,6 +31645,75 @@
-   return false;
- }
- 
-+static void
-+arm_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
-+{
-+  const unsigned ARM_FE_INVALID = 1;
-+  const unsigned ARM_FE_DIVBYZERO = 2;
-+  const unsigned ARM_FE_OVERFLOW = 4;
-+  const unsigned ARM_FE_UNDERFLOW = 8;
-+  const unsigned ARM_FE_INEXACT = 16;
-+  const unsigned HOST_WIDE_INT ARM_FE_ALL_EXCEPT = (ARM_FE_INVALID
-+						    | ARM_FE_DIVBYZERO
-+						    | ARM_FE_OVERFLOW
-+						    | ARM_FE_UNDERFLOW
-+						    | ARM_FE_INEXACT);
-+  const unsigned HOST_WIDE_INT ARM_FE_EXCEPT_SHIFT = 8;
-+  tree fenv_var, get_fpscr, set_fpscr, mask, ld_fenv, masked_fenv;
-+  tree new_fenv_var, reload_fenv, restore_fnenv;
-+  tree update_call, atomic_feraiseexcept, hold_fnclex;
-+
-+  if (!TARGET_VFP || !TARGET_HARD_FLOAT)
-+    return;
-+
-+  /* Generate the equivalent of :
-+       unsigned int fenv_var;
-+       fenv_var = __builtin_arm_get_fpscr ();
-+
-+       unsigned int masked_fenv;
-+       masked_fenv = fenv_var & mask;
-+
-+       __builtin_arm_set_fpscr (masked_fenv);  */
-+
-+  fenv_var = create_tmp_var (unsigned_type_node, NULL);
-+  get_fpscr = arm_builtin_decls[ARM_BUILTIN_GET_FPSCR];
-+  set_fpscr = arm_builtin_decls[ARM_BUILTIN_SET_FPSCR];
-+  mask = build_int_cst (unsigned_type_node,
-+			~((ARM_FE_ALL_EXCEPT << ARM_FE_EXCEPT_SHIFT)
-+			  | ARM_FE_ALL_EXCEPT));
-+  ld_fenv = build2 (MODIFY_EXPR, unsigned_type_node,
-+		    fenv_var, build_call_expr (get_fpscr, 0));
-+  masked_fenv = build2 (BIT_AND_EXPR, unsigned_type_node, fenv_var, mask);
-+  hold_fnclex = build_call_expr (set_fpscr, 1, masked_fenv);
-+  *hold = build2 (COMPOUND_EXPR, void_type_node,
-+		  build2 (COMPOUND_EXPR, void_type_node, masked_fenv, ld_fenv),
-+		  hold_fnclex);
-+
-+  /* Store the value of masked_fenv to clear the exceptions:
-+     __builtin_arm_set_fpscr (masked_fenv);  */
-+
-+  *clear = build_call_expr (set_fpscr, 1, masked_fenv);
-+
-+  /* Generate the equivalent of :
-+       unsigned int new_fenv_var;
-+       new_fenv_var = __builtin_arm_get_fpscr ();
-+
-+       __builtin_arm_set_fpscr (fenv_var);
-+
-+       __atomic_feraiseexcept (new_fenv_var);  */
-+
-+  new_fenv_var = create_tmp_var (unsigned_type_node, NULL);
-+  reload_fenv = build2 (MODIFY_EXPR, unsigned_type_node, new_fenv_var,
-+			build_call_expr (get_fpscr, 0));
-+  restore_fnenv = build_call_expr (set_fpscr, 1, fenv_var);
-+  atomic_feraiseexcept = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT);
-+  update_call = build_call_expr (atomic_feraiseexcept, 1,
-+				 fold_convert (integer_type_node, new_fenv_var));
-+  *update = build2 (COMPOUND_EXPR, void_type_node,
-+		    build2 (COMPOUND_EXPR, void_type_node,
-+			    reload_fenv, restore_fnenv), update_call);
-+}
-+
- /* return TRUE if x is a reference to a value in a constant pool */
- extern bool
- arm_is_constant_pool_ref (rtx x)
---- a/src/gcc/config/arm/arm.h
-+++ b/src/gcc/config/arm/arm.h
-@@ -166,7 +166,10 @@
- 	    builtin_define ("__ARM_EABI__");		\
- 	  }						\
- 	if (TARGET_IDIV)				\
--	  builtin_define ("__ARM_ARCH_EXT_IDIV__");	\
-+         {						\
-+            builtin_define ("__ARM_ARCH_EXT_IDIV__");	\
-+            builtin_define ("__ARM_FEATURE_IDIV");	\
-+         }						\
-     } while (0)
- 
- #include "config/arm/arm-opts.h"
-@@ -298,6 +301,9 @@
- /* FPU supports VFPv3 instructions.  */
- #define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3)
- 
-+/* FPU supports FPv5 instructions.  */
-+#define TARGET_VFP5 (TARGET_VFP && arm_fpu_desc->rev >= 5)
-+
- /* FPU only supports VFP single-precision instructions.  */
- #define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE)
- 
-@@ -442,9 +448,6 @@
- #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
- #endif
- 
--#define LARGEST_EXPONENT_IS_NORMAL(bits) \
--    ((bits) == 16 && arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
--
- #ifndef ARM_DEFAULT_ABI
- #define ARM_DEFAULT_ABI ARM_ABI_APCS
- #endif
---- a/src/gcc/config/arm/unspecs.md
-+++ b/src/gcc/config/arm/unspecs.md
-@@ -143,6 +143,8 @@
-   VUNSPEC_SLX		; Represent a store-register-release-exclusive.
-   VUNSPEC_LDA		; Represent a store-register-acquire.
-   VUNSPEC_STL		; Represent a store-register-release.
-+  VUNSPEC_GET_FPSCR	; Represent fetch of FPSCR content.
-+  VUNSPEC_SET_FPSCR	; Represent assign of FPSCR content.
- ])
- 
- ;; Enumerators for NEON unspecs.
---- a/src/gcc/config/arm/cortex-m4.md
-+++ b/src/gcc/config/arm/cortex-m4.md
-@@ -34,7 +34,7 @@
-        (ior (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
-                              alu_reg,alus_reg,logic_reg,logics_reg,\
-                              adc_imm,adcs_imm,adc_reg,adcs_reg,\
--                             adr,bfm,rev,\
-+                             adr,bfm,clz,rbit,rev,\
-                              shift_imm,shift_reg,extend,\
-                              alu_shift_imm,alus_shift_imm,\
-                              logic_shift_imm,logics_shift_imm,\
---- a/src/gcc/config/arm/arm-modes.def
-+++ b/src/gcc/config/arm/arm-modes.def
-@@ -21,9 +21,6 @@
-    along with GCC; see the file COPYING3.  If not see
-    <http://www.gnu.org/licenses/>.  */
- 
--/* Extended precision floating point.
--   FIXME What format is this?  */
--FLOAT_MODE (XF, 12, 0);
- 
- /* Half-precision floating point */
- FLOAT_MODE (HF, 2, 0);
---- a/src/gcc/config/arm/arm-cores.def
-+++ b/src/gcc/config/arm/arm-cores.def
-@@ -141,7 +141,7 @@
- ARM_CORE("generic-armv7-a",	genericv7a, genericv7a,		7A,  FL_LDSCHED, cortex)
- ARM_CORE("cortex-a5",		cortexa5, cortexa5,		7A,  FL_LDSCHED, cortex_a5)
- ARM_CORE("cortex-a7",		cortexa7, cortexa7,		7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a7)
--ARM_CORE("cortex-a8",		cortexa8, cortexa8,		7A,  FL_LDSCHED, cortex)
-+ARM_CORE("cortex-a8",		cortexa8, cortexa8,		7A,  FL_LDSCHED, cortex_a8)
- ARM_CORE("cortex-a9",		cortexa9, cortexa9,		7A,  FL_LDSCHED, cortex_a9)
- ARM_CORE("cortex-a12",	  	cortexa12, cortexa15,		7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a12)
- ARM_CORE("cortex-a15",		cortexa15, cortexa15,		7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15)
-@@ -149,6 +149,7 @@
- ARM_CORE("cortex-r4f",		cortexr4f, cortexr4f,		7R,  FL_LDSCHED, cortex)
- ARM_CORE("cortex-r5",		cortexr5, cortexr5,		7R,  FL_LDSCHED | FL_ARM_DIV, cortex)
- ARM_CORE("cortex-r7",		cortexr7, cortexr7,		7R,  FL_LDSCHED | FL_ARM_DIV, cortex)
-+ARM_CORE("cortex-m7",		cortexm7, cortexm7,		7EM, FL_LDSCHED, v7m)
- ARM_CORE("cortex-m4",		cortexm4, cortexm4,		7EM, FL_LDSCHED, v7m)
- ARM_CORE("cortex-m3",		cortexm3, cortexm3,		7M,  FL_LDSCHED, v7m)
- ARM_CORE("marvell-pj4",		marvell_pj4, marvell_pj4,	7A,  FL_LDSCHED, 9e)
---- a/src/gcc/config/arm/cortex-r4.md
-+++ b/src/gcc/config/arm/cortex-r4.md
-@@ -81,7 +81,7 @@
-        (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
-                         alu_reg,alus_reg,logic_reg,logics_reg,\
-                         adc_imm,adcs_imm,adc_reg,adcs_reg,\
--                        adr,bfm,rev,\
-+                        adr,bfm,clz,rbit,rev,\
-                         shift_imm,shift_reg,mvn_imm,mvn_reg"))
-   "cortex_r4_alu")
- 
---- a/src/gcc/config/arm/arm-tune.md
-+++ b/src/gcc/config/arm/arm-tune.md
-@@ -28,7 +28,8 @@
- 	genericv7a,cortexa5,cortexa7,
- 	cortexa8,cortexa9,cortexa12,
- 	cortexa15,cortexr4,cortexr4f,
--	cortexr5,cortexr7,cortexm4,
--	cortexm3,marvell_pj4,cortexa15cortexa7,
--	cortexa53,cortexa57,cortexa57cortexa53"
-+	cortexr5,cortexr7,cortexm7,
-+	cortexm4,cortexm3,marvell_pj4,
-+	cortexa15cortexa7,cortexa53,cortexa57,
-+	cortexa57cortexa53"
- 	(const (symbol_ref "((enum attr_tune) arm_tune)")))
---- a/src/gcc/config/arm/arm-protos.h
-+++ b/src/gcc/config/arm/arm-protos.h
-@@ -126,7 +126,6 @@
- extern int arm_const_double_inline_cost (rtx);
- extern bool arm_const_double_by_parts (rtx);
- extern bool arm_const_double_by_immediates (rtx);
--extern const char *fp_immediate_constant (rtx);
- extern void arm_emit_call_insn (rtx, rtx);
- extern const char *output_call (rtx *);
- extern const char *output_call_mem (rtx *);
-@@ -150,7 +149,7 @@
- extern int    arm_emit_vector_const (FILE *, rtx);
- extern void arm_emit_fp16_const (rtx c);
- extern const char * arm_output_load_gr (rtx *);
--extern const char *vfp_output_fstmd (rtx *);
-+extern const char *vfp_output_vstmd (rtx *);
- extern void arm_output_multireg_pop (rtx *, bool, rtx, bool, bool);
- extern void arm_set_return_address (rtx, rtx);
- extern int arm_eliminable_register (rtx);
-@@ -273,6 +272,11 @@
-   const struct cpu_vec_costs* vec_costs;
-   /* Prefer Neon for 64-bit bitops.  */
-   bool prefer_neon_for_64bits;
-+  /* Prefer 32-bit encoding instead of flag-setting 16-bit encoding.  */
-+  bool disparage_flag_setting_t16_encodings;
-+  /* Prefer 32-bit encoding instead of 16-bit encoding where subset of flags
-+     would be set.  */
-+  bool disparage_partial_flag_setting_t16_encodings;
- };
- 
- extern const struct tune_params *current_tune;
---- a/src/gcc/config/arm/vfp.md
-+++ b/src/gcc/config/arm/vfp.md
-@@ -41,11 +41,11 @@
-     case 5:
-       return \"str%?\\t%1, %0\";
-     case 6:
--      return \"fmsr%?\\t%0, %1\\t%@ int\";
-+      return \"vmov%?\\t%0, %1\\t%@ int\";
-     case 7:
--      return \"fmrs%?\\t%0, %1\\t%@ int\";
-+      return \"vmov%?\\t%0, %1\\t%@ int\";
-     case 8:
--      return \"fcpys%?\\t%0, %1\\t%@ int\";
-+      return \"vmov%?.f32\\t%0, %1\\t%@ int\";
-     case 9: case 10:
-       return output_move_vfp (operands);
-     default:
-@@ -87,11 +87,11 @@
-     case 8:
-       return \"str%?\\t%1, %0\";
-     case 9:
--      return \"fmsr%?\\t%0, %1\\t%@ int\";
-+      return \"vmov%?\\t%0, %1\\t%@ int\";
-     case 10:
--      return \"fmrs%?\\t%0, %1\\t%@ int\";
-+      return \"vmov%?\\t%0, %1\\t%@ int\";
-     case 11:
--      return \"fcpys%?\\t%0, %1\\t%@ int\";
-+      return \"vmov%?.f32\\t%0, %1\\t%@ int\";
-     case 12: case 13:
-       return output_move_vfp (operands);
-     default:
-@@ -100,7 +100,7 @@
-   "
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no,no,no,no,no,no")
--   (set_attr "type" "mov_reg,mov_reg,mov_reg,mvn_reg,mov_reg,load1,load1,store1,store1,f_mcr,f_mrc,fmov,f_loads,f_stores")
-+   (set_attr "type" "mov_reg,mov_reg,mov_reg,mvn_reg,mov_imm,load1,load1,store1,store1,f_mcr,f_mrc,fmov,f_loads,f_stores")
-    (set_attr "length" "2,4,2,4,4,4,4,4,4,4,4,4,4,4")
-    (set_attr "pool_range"     "*,*,*,*,*,1018,4094,*,*,*,*,*,1018,*")
-    (set_attr "neg_pool_range" "*,*,*,*,*,   0,   0,*,*,*,*,*,1008,*")]
-@@ -130,14 +130,14 @@
-     case 6:
-       return output_move_double (operands, true, NULL);
-     case 7:
--      return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
-+      return \"vmov%?\\t%P0, %Q1, %R1\\t%@ int\";
-     case 8:
--      return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
-+      return \"vmov%?\\t%Q0, %R0, %P1\\t%@ int\";
-     case 9:
-       if (TARGET_VFP_SINGLE)
--	return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\";
-+	return \"vmov%?.f32\\t%0, %1\\t%@ int\;vmov%?.f32\\t%p0, %p1\\t%@ int\";
-       else
--	return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
-+	return \"vmov%?.f64\\t%P0, %P1\\t%@ int\";
-     case 10: case 11:
-       return output_move_vfp (operands);
-     default:
-@@ -181,11 +181,11 @@
-     case 6:
-       return output_move_double (operands, true, NULL);
-     case 7:
--      return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
-+      return \"vmov%?\\t%P0, %Q1, %R1\\t%@ int\";
-     case 8:
--      return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
-+      return \"vmov%?\\t%Q0, %R0, %P1\\t%@ int\";
-     case 9:
--      return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
-+      return \"vmov%?.f64\\t%P0, %P1\\t%@ int\";
-     case 10: case 11:
-       return output_move_vfp (operands);
-     default:
-@@ -229,13 +229,13 @@
-     case 3:     /* memory from ARM register */
-       return \"strh\\t%1, %0\\t%@ __fp16\";
-     case 4:	/* S register from S register */
--      return \"fcpys\\t%0, %1\";
-+      return \"vmov.f32\\t%0, %1\";
-     case 5:	/* ARM register from ARM register */
-       return \"mov\\t%0, %1\\t%@ __fp16\";
-     case 6:	/* S register from ARM register */
--      return \"fmsr\\t%0, %1\";
-+      return \"vmov\\t%0, %1\";
-     case 7:	/* ARM register from S register */
--      return \"fmrs\\t%0, %1\";
-+      return \"vmov\\t%0, %1\";
-     case 8:	/* ARM register from constant */
-       {
-         REAL_VALUE_TYPE r;
-@@ -280,13 +280,13 @@
-     case 1:     /* memory from ARM register */
-       return \"strh\\t%1, %0\\t%@ __fp16\";
-     case 2:	/* S register from S register */
--      return \"fcpys\\t%0, %1\";
-+      return \"vmov.f32\\t%0, %1\";
-     case 3:	/* ARM register from ARM register */
-       return \"mov\\t%0, %1\\t%@ __fp16\";
-     case 4:	/* S register from ARM register */
--      return \"fmsr\\t%0, %1\";
-+      return \"vmov\\t%0, %1\";
-     case 5:	/* ARM register from S register */
--      return \"fmrs\\t%0, %1\";
-+      return \"vmov\\t%0, %1\";
-     case 6:	/* ARM register from constant */
-       {
-         REAL_VALUE_TYPE r;
-@@ -322,7 +322,7 @@
- 
- (define_insn "*movsf_vfp"
-   [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t ,t  ,Uv,r ,m,t,r")
--	(match_operand:SF 1 "general_operand"	   " ?r,t,Dv,UvE,t, mE,r,t,r"))]
-+        (match_operand:SF 1 "general_operand"	   " ?r,t,Dv,UvE,t, mE,r,t,r"))]
-   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
-    && (   s_register_operand (operands[0], SFmode)
-        || s_register_operand (operands[1], SFmode))"
-@@ -330,11 +330,11 @@
-   switch (which_alternative)
-     {
-     case 0:
--      return \"fmsr%?\\t%0, %1\";
-+      return \"vmov%?\\t%0, %1\";
-     case 1:
--      return \"fmrs%?\\t%0, %1\";
-+      return \"vmov%?\\t%0, %1\";
-     case 2:
--      return \"fconsts%?\\t%0, #%G1\";
-+      return \"vmov%?.f32\\t%0, %1\";
-     case 3: case 4:
-       return output_move_vfp (operands);
-     case 5:
-@@ -342,7 +342,7 @@
-     case 6:
-       return \"str%?\\t%1, %0\\t%@ float\";
-     case 7:
--      return \"fcpys%?\\t%0, %1\";
-+      return \"vmov%?.f32\\t%0, %1\";
-     case 8:
-       return \"mov%?\\t%0, %1\\t%@ float\";
-     default:
-@@ -366,11 +366,11 @@
-   switch (which_alternative)
-     {
-     case 0:
--      return \"fmsr%?\\t%0, %1\";
-+      return \"vmov%?\\t%0, %1\";
-     case 1:
--      return \"fmrs%?\\t%0, %1\";
-+      return \"vmov%?\\t%0, %1\";
-     case 2:
--      return \"fconsts%?\\t%0, #%G1\";
-+      return \"vmov%?.f32\\t%0, %1\";
-     case 3: case 4:
-       return output_move_vfp (operands);
-     case 5:
-@@ -378,7 +378,7 @@
-     case 6:
-       return \"str%?\\t%1, %0\\t%@ float\";
-     case 7:
--      return \"fcpys%?\\t%0, %1\";
-+      return \"vmov%?.f32\\t%0, %1\";
-     case 8:
-       return \"mov%?\\t%0, %1\\t%@ float\";
-     default:
-@@ -406,12 +406,12 @@
-     switch (which_alternative)
-       {
-       case 0:
--	return \"fmdrr%?\\t%P0, %Q1, %R1\";
-+	return \"vmov%?\\t%P0, %Q1, %R1\";
-       case 1:
--	return \"fmrrd%?\\t%Q0, %R0, %P1\";
-+	return \"vmov%?\\t%Q0, %R0, %P1\";
-       case 2:
- 	gcc_assert (TARGET_VFP_DOUBLE);
--        return \"fconstd%?\\t%P0, #%G1\";
-+        return \"vmov%?.f64\\t%P0, %1\";
-       case 3: case 4:
- 	return output_move_vfp (operands);
-       case 5: case 6:
-@@ -418,9 +418,9 @@
- 	return output_move_double (operands, true, NULL);
-       case 7:
- 	if (TARGET_VFP_SINGLE)
--	  return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
-+	  return \"vmov%?.f32\\t%0, %1\;vmov%?.f32\\t%p0, %p1\";
- 	else
--	  return \"fcpyd%?\\t%P0, %P1\";
-+	  return \"vmov%?.f64\\t%P0, %P1\";
-       case 8:
-         return \"#\";
-       default:
-@@ -453,12 +453,12 @@
-     switch (which_alternative)
-       {
-       case 0:
--	return \"fmdrr%?\\t%P0, %Q1, %R1\";
-+	return \"vmov%?\\t%P0, %Q1, %R1\";
-       case 1:
--	return \"fmrrd%?\\t%Q0, %R0, %P1\";
-+	return \"vmov%?\\t%Q0, %R0, %P1\";
-       case 2:
- 	gcc_assert (TARGET_VFP_DOUBLE);
--	return \"fconstd%?\\t%P0, #%G1\";
-+	return \"vmov%?.f64\\t%P0, %1\";
-       case 3: case 4:
- 	return output_move_vfp (operands);
-       case 5: case 6: case 8:
-@@ -465,9 +465,9 @@
- 	return output_move_double (operands, true, NULL);
-       case 7:
- 	if (TARGET_VFP_SINGLE)
--	  return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
-+	  return \"vmov%?.f32\\t%0, %1\;vmov%?.f32\\t%p0, %p1\";
- 	else
--	  return \"fcpyd%?\\t%P0, %P1\";
-+	  return \"vmov%?.f64\\t%P0, %P1\";
-       default:
- 	abort ();
-       }
-@@ -498,15 +498,15 @@
- 	  (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
-   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
-   "@
--   fcpys%D3\\t%0, %2
--   fcpys%d3\\t%0, %1
--   fcpys%D3\\t%0, %2\;fcpys%d3\\t%0, %1
--   fmsr%D3\\t%0, %2
--   fmsr%d3\\t%0, %1
--   fmsr%D3\\t%0, %2\;fmsr%d3\\t%0, %1
--   fmrs%D3\\t%0, %2
--   fmrs%d3\\t%0, %1
--   fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
-+   vmov%D3.f32\\t%0, %2
-+   vmov%d3.f32\\t%0, %1
-+   vmov%D3.f32\\t%0, %2\;vmov%d3.f32\\t%0, %1
-+   vmov%D3\\t%0, %2
-+   vmov%d3\\t%0, %1
-+   vmov%D3\\t%0, %2\;vmov%d3\\t%0, %1
-+   vmov%D3\\t%0, %2
-+   vmov%d3\\t%0, %1
-+   vmov%D3\\t%0, %2\;vmov%d3\\t%0, %1"
-    [(set_attr "conds" "use")
-     (set_attr "length" "4,4,8,4,4,8,4,4,8")
-     (set_attr "type" "fmov,fmov,fmov,f_mcr,f_mcr,f_mcr,f_mrc,f_mrc,f_mrc")]
-@@ -521,15 +521,15 @@
- 	  (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
-   "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP && !arm_restrict_it"
-   "@
--   it\\t%D3\;fcpys%D3\\t%0, %2
--   it\\t%d3\;fcpys%d3\\t%0, %1
--   ite\\t%D3\;fcpys%D3\\t%0, %2\;fcpys%d3\\t%0, %1
--   it\\t%D3\;fmsr%D3\\t%0, %2
--   it\\t%d3\;fmsr%d3\\t%0, %1
--   ite\\t%D3\;fmsr%D3\\t%0, %2\;fmsr%d3\\t%0, %1
--   it\\t%D3\;fmrs%D3\\t%0, %2
--   it\\t%d3\;fmrs%d3\\t%0, %1
--   ite\\t%D3\;fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
-+   it\\t%D3\;vmov%D3.f32\\t%0, %2
-+   it\\t%d3\;vmov%d3.f32\\t%0, %1
-+   ite\\t%D3\;vmov%D3.f32\\t%0, %2\;vmov%d3.f32\\t%0, %1
-+   it\\t%D3\;vmov%D3\\t%0, %2
-+   it\\t%d3\;vmov%d3\\t%0, %1
-+   ite\\t%D3\;vmov%D3\\t%0, %2\;vmov%d3\\t%0, %1
-+   it\\t%D3\;vmov%D3\\t%0, %2
-+   it\\t%d3\;vmov%d3\\t%0, %1
-+   ite\\t%D3\;vmov%D3\\t%0, %2\;vmov%d3\\t%0, %1"
-    [(set_attr "conds" "use")
-     (set_attr "length" "6,6,10,6,6,10,6,6,10")
-     (set_attr "type" "fmov,fmov,fmov,f_mcr,f_mcr,f_mcr,f_mrc,f_mrc,f_mrc")]
-@@ -544,15 +544,15 @@
- 	  (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
-   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
-   "@
--   fcpyd%D3\\t%P0, %P2
--   fcpyd%d3\\t%P0, %P1
--   fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1
--   fmdrr%D3\\t%P0, %Q2, %R2
--   fmdrr%d3\\t%P0, %Q1, %R1
--   fmdrr%D3\\t%P0, %Q2, %R2\;fmdrr%d3\\t%P0, %Q1, %R1
--   fmrrd%D3\\t%Q0, %R0, %P2
--   fmrrd%d3\\t%Q0, %R0, %P1
--   fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
-+   vmov%D3.f64\\t%P0, %P2
-+   vmov%d3.f64\\t%P0, %P1
-+   vmov%D3.f64\\t%P0, %P2\;vmov%d3.f64\\t%P0, %P1
-+   vmov%D3\\t%P0, %Q2, %R2
-+   vmov%d3\\t%P0, %Q1, %R1
-+   vmov%D3\\t%P0, %Q2, %R2\;vmov%d3\\t%P0, %Q1, %R1
-+   vmov%D3\\t%Q0, %R0, %P2
-+   vmov%d3\\t%Q0, %R0, %P1
-+   vmov%D3\\t%Q0, %R0, %P2\;vmov%d3\\t%Q0, %R0, %P1"
-    [(set_attr "conds" "use")
-     (set_attr "length" "4,4,8,4,4,8,4,4,8")
-     (set_attr "type" "ffarithd,ffarithd,ffarithd,f_mcr,f_mcr,f_mcr,f_mrrc,f_mrrc,f_mrrc")]
-@@ -567,15 +567,15 @@
- 	  (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
-   "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE && !arm_restrict_it"
-   "@
--   it\\t%D3\;fcpyd%D3\\t%P0, %P2
--   it\\t%d3\;fcpyd%d3\\t%P0, %P1
--   ite\\t%D3\;fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1
--   it\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2
--   it\t%d3\;fmdrr%d3\\t%P0, %Q1, %R1
--   ite\\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2\;fmdrr%d3\\t%P0, %Q1, %R1
--   it\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2
--   it\t%d3\;fmrrd%d3\\t%Q0, %R0, %P1
--   ite\\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
-+   it\\t%D3\;vmov%D3.f64\\t%P0, %P2
-+   it\\t%d3\;vmov%d3.f64\\t%P0, %P1
-+   ite\\t%D3\;vmov%D3.f64\\t%P0, %P2\;vmov%d3.f64\\t%P0, %P1
-+   it\t%D3\;vmov%D3\\t%P0, %Q2, %R2
-+   it\t%d3\;vmov%d3\\t%P0, %Q1, %R1
-+   ite\\t%D3\;vmov%D3\\t%P0, %Q2, %R2\;vmov%d3\\t%P0, %Q1, %R1
-+   it\t%D3\;vmov%D3\\t%Q0, %R0, %P2
-+   it\t%d3\;vmov%d3\\t%Q0, %R0, %P1
-+   ite\\t%D3\;vmov%D3\\t%Q0, %R0, %P2\;vmov%d3\\t%Q0, %R0, %P1"
-    [(set_attr "conds" "use")
-     (set_attr "length" "6,6,10,6,6,10,6,6,10")
-     (set_attr "type" "ffarithd,ffarithd,ffarithd,f_mcr,f_mcr,f_mcrr,f_mrrc,f_mrrc,f_mrrc")]
-@@ -588,7 +588,7 @@
-   [(set (match_operand:SF	  0 "s_register_operand" "=t")
- 	(abs:SF (match_operand:SF 1 "s_register_operand" "t")))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
--  "fabss%?\\t%0, %1"
-+  "vabs%?.f32\\t%0, %1"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "ffariths")]
-@@ -598,7 +598,7 @@
-   [(set (match_operand:DF	  0 "s_register_operand" "=w")
- 	(abs:DF (match_operand:DF 1 "s_register_operand" "w")))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
--  "fabsd%?\\t%P0, %P1"
-+  "vabs%?.f64\\t%P0, %P1"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "ffarithd")]
-@@ -609,7 +609,7 @@
- 	(neg:SF (match_operand:SF 1 "s_register_operand" "t,r")))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
-   "@
--   fnegs%?\\t%0, %1
-+   vneg%?.f32\\t%0, %1
-    eor%?\\t%0, %1, #-2147483648"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-@@ -621,7 +621,7 @@
- 	(neg:DF (match_operand:DF 1 "s_register_operand" "w,0,r")))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
-   "@
--   fnegd%?\\t%P0, %P1
-+   vneg%?.f64\\t%P0, %P1
-    #
-    #"
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE && reload_completed
-@@ -671,7 +671,7 @@
- 	(plus:SF (match_operand:SF 1 "s_register_operand" "t")
- 		 (match_operand:SF 2 "s_register_operand" "t")))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
--  "fadds%?\\t%0, %1, %2"
-+  "vadd%?.f32\\t%0, %1, %2"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "fadds")]
-@@ -682,7 +682,7 @@
- 	(plus:DF (match_operand:DF 1 "s_register_operand" "w")
- 		 (match_operand:DF 2 "s_register_operand" "w")))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
--  "faddd%?\\t%P0, %P1, %P2"
-+  "vadd%?.f64\\t%P0, %P1, %P2"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "faddd")]
-@@ -694,7 +694,7 @@
- 	(minus:SF (match_operand:SF 1 "s_register_operand" "t")
- 		  (match_operand:SF 2 "s_register_operand" "t")))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
--  "fsubs%?\\t%0, %1, %2"
-+  "vsub%?.f32\\t%0, %1, %2"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "fadds")]
-@@ -705,7 +705,7 @@
- 	(minus:DF (match_operand:DF 1 "s_register_operand" "w")
- 		  (match_operand:DF 2 "s_register_operand" "w")))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
--  "fsubd%?\\t%P0, %P1, %P2"
-+  "vsub%?.f64\\t%P0, %P1, %P2"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "faddd")]
-@@ -719,7 +719,7 @@
- 	(div:SF (match_operand:SF 1 "s_register_operand" "t")
- 		(match_operand:SF 2 "s_register_operand" "t")))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
--  "fdivs%?\\t%0, %1, %2"
-+  "vdiv%?.f32\\t%0, %1, %2"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "fdivs")]
-@@ -730,7 +730,7 @@
- 	(div:DF (match_operand:DF 1 "s_register_operand" "w")
- 		(match_operand:DF 2 "s_register_operand" "w")))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
--  "fdivd%?\\t%P0, %P1, %P2"
-+  "vdiv%?.f64\\t%P0, %P1, %P2"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "fdivd")]
-@@ -744,7 +744,7 @@
- 	(mult:SF (match_operand:SF 1 "s_register_operand" "t")
- 		 (match_operand:SF 2 "s_register_operand" "t")))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
--  "fmuls%?\\t%0, %1, %2"
-+  "vmul%?.f32\\t%0, %1, %2"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "fmuls")]
-@@ -755,7 +755,7 @@
- 	(mult:DF (match_operand:DF 1 "s_register_operand" "w")
- 		 (match_operand:DF 2 "s_register_operand" "w")))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
--  "fmuld%?\\t%P0, %P1, %P2"
-+  "vmul%?.f64\\t%P0, %P1, %P2"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "fmuld")]
-@@ -766,7 +766,7 @@
- 	(mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "t"))
- 		 (match_operand:SF	   2 "s_register_operand" "t")))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
--  "fnmuls%?\\t%0, %1, %2"
-+  "vnmul%?.f32\\t%0, %1, %2"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "fmuls")]
-@@ -777,7 +777,7 @@
- 	(mult:DF (neg:DF (match_operand:DF 1 "s_register_operand" "w"))
- 		 (match_operand:DF	   2 "s_register_operand" "w")))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
--  "fnmuld%?\\t%P0, %P1, %P2"
-+  "vnmul%?.f64\\t%P0, %P1, %P2"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "fmuld")]
-@@ -793,7 +793,7 @@
- 			  (match_operand:SF 3 "s_register_operand" "t"))
- 		 (match_operand:SF	    1 "s_register_operand" "0")))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
--  "fmacs%?\\t%0, %2, %3"
-+  "vmla%?.f32\\t%0, %2, %3"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "fmacs")]
-@@ -805,7 +805,7 @@
- 			  (match_operand:DF 3 "s_register_operand" "w"))
- 		 (match_operand:DF	    1 "s_register_operand" "0")))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
--  "fmacd%?\\t%P0, %P2, %P3"
-+  "vmla%?.f64\\t%P0, %P2, %P3"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "fmacd")]
-@@ -818,7 +818,7 @@
- 			   (match_operand:SF 3 "s_register_operand" "t"))
- 		  (match_operand:SF	     1 "s_register_operand" "0")))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
--  "fmscs%?\\t%0, %2, %3"
-+  "vnmls%?.f32\\t%0, %2, %3"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "fmacs")]
-@@ -830,7 +830,7 @@
- 			   (match_operand:DF 3 "s_register_operand" "w"))
- 		  (match_operand:DF	     1 "s_register_operand" "0")))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
--  "fmscd%?\\t%P0, %P2, %P3"
-+  "vnmls%?.f64\\t%P0, %P2, %P3"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "fmacd")]
-@@ -843,7 +843,7 @@
- 		  (mult:SF (match_operand:SF 2 "s_register_operand" "t")
- 			   (match_operand:SF 3 "s_register_operand" "t"))))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
--  "fnmacs%?\\t%0, %2, %3"
-+  "vmls%?.f32\\t%0, %2, %3"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "fmacs")]
-@@ -855,7 +855,7 @@
- 		  (mult:DF (match_operand:DF 2 "s_register_operand" "w")
- 			   (match_operand:DF 3 "s_register_operand" "w"))))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
--  "fnmacd%?\\t%P0, %P2, %P3"
-+  "vmls%?.f64\\t%P0, %P2, %P3"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "fmacd")]
-@@ -870,7 +870,7 @@
- 		    (match_operand:SF	      3 "s_register_operand" "t"))
- 		  (match_operand:SF	      1 "s_register_operand" "0")))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
--  "fnmscs%?\\t%0, %2, %3"
-+  "vnmla%?.f32\\t%0, %2, %3"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "fmacs")]
-@@ -883,7 +883,7 @@
- 		    (match_operand:DF	      3 "s_register_operand" "w"))
- 		  (match_operand:DF	      1 "s_register_operand" "0")))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
--  "fnmscd%?\\t%P0, %P2, %P3"
-+  "vnmla%?.f64\\t%P0, %P2, %P3"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "fmacd")]
-@@ -948,7 +948,7 @@
-   [(set (match_operand:DF		   0 "s_register_operand" "=w")
- 	(float_extend:DF (match_operand:SF 1 "s_register_operand" "t")))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
--  "fcvtds%?\\t%P0, %1"
-+  "vcvt%?.f64.f32\\t%P0, %1"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "f_cvt")]
-@@ -958,7 +958,7 @@
-   [(set (match_operand:SF		   0 "s_register_operand" "=t")
- 	(float_truncate:SF (match_operand:DF 1 "s_register_operand" "w")))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
--  "fcvtsd%?\\t%0, %P1"
-+  "vcvt%?.f32.f64\\t%0, %P1"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "f_cvt")]
-@@ -988,7 +988,7 @@
-   [(set (match_operand:SI		  0 "s_register_operand" "=t")
- 	(fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
--  "ftosizs%?\\t%0, %1"
-+  "vcvt%?.s32.f32\\t%0, %1"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "f_cvtf2i")]
-@@ -998,7 +998,7 @@
-   [(set (match_operand:SI		  0 "s_register_operand" "=t")
- 	(fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "w"))))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
--  "ftosizd%?\\t%0, %P1"
-+  "vcvt%?.s32.f64\\t%0, %P1"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "f_cvtf2i")]
-@@ -1009,7 +1009,7 @@
-   [(set (match_operand:SI		  0 "s_register_operand" "=t")
- 	(unsigned_fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
--  "ftouizs%?\\t%0, %1"
-+  "vcvt%?.u32.f32\\t%0, %1"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "f_cvtf2i")]
-@@ -1019,7 +1019,7 @@
-   [(set (match_operand:SI		  0 "s_register_operand" "=t")
- 	(unsigned_fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "t"))))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
--  "ftouizd%?\\t%0, %P1"
-+  "vcvt%?.u32.f64\\t%0, %P1"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "f_cvtf2i")]
-@@ -1030,7 +1030,7 @@
-   [(set (match_operand:SF	    0 "s_register_operand" "=t")
- 	(float:SF (match_operand:SI 1 "s_register_operand" "t")))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
--  "fsitos%?\\t%0, %1"
-+  "vcvt%?.f32.s32\\t%0, %1"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "f_cvti2f")]
-@@ -1040,7 +1040,7 @@
-   [(set (match_operand:DF	    0 "s_register_operand" "=w")
- 	(float:DF (match_operand:SI 1 "s_register_operand" "t")))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
--  "fsitod%?\\t%P0, %1"
-+  "vcvt%?.f64.s32\\t%P0, %1"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "f_cvti2f")]
-@@ -1051,7 +1051,7 @@
-   [(set (match_operand:SF	    0 "s_register_operand" "=t")
- 	(unsigned_float:SF (match_operand:SI 1 "s_register_operand" "t")))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
--  "fuitos%?\\t%0, %1"
-+  "vcvt%?.f32.u32\\t%0, %1"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "f_cvti2f")]
-@@ -1061,7 +1061,7 @@
-   [(set (match_operand:DF	    0 "s_register_operand" "=w")
- 	(unsigned_float:DF (match_operand:SI 1 "s_register_operand" "t")))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
--  "fuitod%?\\t%P0, %1"
-+  "vcvt%?.f64.u32\\t%P0, %1"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "f_cvti2f")]
-@@ -1074,7 +1074,7 @@
-   [(set (match_operand:SF	   0 "s_register_operand" "=t")
- 	(sqrt:SF (match_operand:SF 1 "s_register_operand" "t")))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
--  "fsqrts%?\\t%0, %1"
-+  "vsqrt%?.f32\\t%0, %1"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "fsqrts")]
-@@ -1084,7 +1084,7 @@
-   [(set (match_operand:DF	   0 "s_register_operand" "=w")
- 	(sqrt:DF (match_operand:DF 1 "s_register_operand" "w")))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
--  "fsqrtd%?\\t%P0, %P1"
-+  "vsqrt%?.f64\\t%P0, %P1"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "fsqrtd")]
-@@ -1097,7 +1097,7 @@
-   [(set (reg CC_REGNUM)
- 	(reg VFPCC_REGNUM))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
--  "fmstat%?"
-+  "vmrs%?\\tAPSR_nzcv, FPSCR"
-   [(set_attr "conds" "set")
-    (set_attr "type" "f_flag")]
- )
-@@ -1165,6 +1165,9 @@
- 
- ;; Comparison patterns
- 
-+;; In the compare with FP zero case the ARM Architecture Reference Manual
-+;; specifies the immediate to be #0.0.  However, some buggy assemblers only
-+;; accept #0.  We don't want to autodetect broken assemblers, so output #0.
- (define_insn "*cmpsf_vfp"
-   [(set (reg:CCFP VFPCC_REGNUM)
- 	(compare:CCFP (match_operand:SF 0 "s_register_operand"  "t,t")
-@@ -1171,8 +1174,8 @@
- 		      (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
-   "@
--   fcmps%?\\t%0, %1
--   fcmpzs%?\\t%0"
-+   vcmp%?.f32\\t%0, %1
-+   vcmp%?.f32\\t%0, #0"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "fcmps")]
-@@ -1184,8 +1187,8 @@
- 		       (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
-   "@
--   fcmpes%?\\t%0, %1
--   fcmpezs%?\\t%0"
-+   vcmpe%?.f32\\t%0, %1
-+   vcmpe%?.f32\\t%0, #0"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "fcmps")]
-@@ -1197,8 +1200,8 @@
- 		      (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
-   "@
--   fcmpd%?\\t%P0, %P1
--   fcmpzd%?\\t%P0"
-+   vcmp%?.f64\\t%P0, %P1
-+   vcmp%?.f64\\t%P0, #0"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "fcmpd")]
-@@ -1210,8 +1213,8 @@
- 		       (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
-   "@
--   fcmped%?\\t%P0, %P1
--   fcmpezd%?\\t%P0"
-+   vcmpe%?.f64\\t%P0, %P1
-+   vcmpe%?.f64\\t%P0, #0"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "type" "fcmpd")]
-@@ -1272,7 +1275,7 @@
- 	  (unspec:BLK [(match_operand:DF 1 "vfp_register_operand" "")]
- 		      UNSPEC_PUSH_MULT))])]
-   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
--  "* return vfp_output_fstmd (operands);"
-+  "* return vfp_output_vstmd (operands);"
-   [(set_attr "type" "f_stored")]
- )
- 
-@@ -1285,7 +1288,7 @@
-         (unspec:SDF [(match_operand:SDF 1
- 		         "register_operand" "<F_constraint>")]
-          VRINT))]
--  "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"
-+  "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>"
-   "vrint<vrint_variant>%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1"
-   [(set_attr "predicable" "<vrint_predicable>")
-    (set_attr "predicable_short_it" "no")
-@@ -1293,6 +1296,18 @@
-    (set_attr "conds" "<vrint_conds>")]
- )
- 
-+;; Implements the lround, lfloor and lceil optabs.
-+(define_insn "l<vrint_pattern><su_optab><mode>si2"
-+  [(set (match_operand:SI 0 "register_operand" "=t")
-+        (FIXUORS:SI (unspec:SDF
-+                        [(match_operand:SDF 1
-+                           "register_operand" "<F_constraint>")] VCVT)))]
-+  "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"
-+  "vcvt<vrint_variant>%?.<su>32.<V_if_elem>\\t%0, %<V_reg>1"
-+  [(set_attr "predicable" "no")
-+   (set_attr "type" "f_cvtf2i")]
-+)
-+
- ;; MIN_EXPR and MAX_EXPR eventually map to 'smin' and 'smax' in RTL.
- ;; The 'smax' and 'smin' RTL standard pattern names do not specify which
- ;; operand will be returned when both operands are zero (i.e. they may not
-@@ -1304,7 +1319,7 @@
-   [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
-         (smax:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
- 		  (match_operand:SDF 2 "register_operand" "<F_constraint>")))]
--  "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"
-+  "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>"
-   "vmaxnm.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
-   [(set_attr "type" "f_minmax<vfp_type>")
-    (set_attr "conds" "unconditional")]
-@@ -1314,12 +1329,28 @@
-   [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
-         (smin:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
- 		  (match_operand:SDF 2 "register_operand" "<F_constraint>")))]
--  "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"
-+  "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>"
-   "vminnm.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
-   [(set_attr "type" "f_minmax<vfp_type>")
-    (set_attr "conds" "unconditional")]
- )
- 
-+;; Write Floating-point Status and Control Register.
-+(define_insn "set_fpscr"
-+  [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] VUNSPEC_SET_FPSCR)]
-+  "TARGET_VFP && TARGET_HARD_FLOAT"
-+  "mcr\\tp10, 7, %0, cr1, cr0, 0\\t @SET_FPSCR"
-+  [(set_attr "type" "mrs")])
-+
-+;; Read Floating-point Status and Control Register.
-+(define_insn "get_fpscr"
-+  [(set (match_operand:SI 0 "register_operand" "=r")
-+        (unspec_volatile:SI [(const_int 0)] VUNSPEC_GET_FPSCR))]
-+  "TARGET_VFP && TARGET_HARD_FLOAT"
-+  "mrc\\tp10, 7, %0, cr1, cr0, 0\\t @GET_FPSCR"
-+  [(set_attr "type" "mrs")])
-+
-+
- ;; Unimplemented insns:
- ;; fldm*
- ;; fstm*
---- a/src/gcc/config/arm/neon.md
-+++ b/src/gcc/config/arm/neon.md
-@@ -296,7 +296,7 @@
- 		    UNSPEC_MISALIGNED_ACCESS))]
-   "TARGET_NEON && !BYTES_BIG_ENDIAN && unaligned_access"
-   "vld1.<V_sz_elem>\t{%q0}, %A1"
--  [(set_attr "type" "neon_store1_1reg<q>")])
-+  [(set_attr "type" "neon_load1_1reg<q>")])
- 
- (define_insn "vec_set<mode>_internal"
-   [(set (match_operand:VD 0 "s_register_operand" "=w,w")
-@@ -629,6 +629,17 @@
-   [(set_attr "type" "neon_fp_round_<V_elem_ch><q>")]
- )
- 
-+(define_insn "neon_vcvt<NEON_VCVT:nvrint_variant><su_optab><VCVTF:mode><v_cmp_result>"
-+  [(set (match_operand:<V_cmp_result> 0 "register_operand" "=w")
-+	(FIXUORS:<V_cmp_result> (unspec:VCVTF
-+			       [(match_operand:VCVTF 1 "register_operand" "w")]
-+			       NEON_VCVT)))]
-+  "TARGET_NEON && TARGET_FPU_ARMV8"
-+  "vcvt<nvrint_variant>.<su>32.f32\\t%<V_reg>0, %<V_reg>1"
-+  [(set_attr "type" "neon_fp_to_int_<V_elem_ch><q>")
-+   (set_attr "predicable" "no")]
-+)
-+
- (define_insn "ior<mode>3"
-   [(set (match_operand:VDQ 0 "s_register_operand" "=w,w")
- 	(ior:VDQ (match_operand:VDQ 1 "s_register_operand" "w,0")
-@@ -1041,7 +1052,9 @@
-       }
-     else
-       {
--	if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1)
-+	if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1
-+	    && (!reg_overlap_mentioned_p (operands[0], operands[1])
-+		|| REGNO (operands[0]) == REGNO (operands[1])))
- 	  /* This clobbers CC.  */
- 	  emit_insn (gen_arm_ashldi3_1bit (operands[0], operands[1]));
- 	else
-@@ -1141,7 +1154,9 @@
-       }
-     else
-       {
--	if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1)
-+	if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1
-+	    && (!reg_overlap_mentioned_p (operands[0], operands[1])
-+		|| REGNO (operands[0]) == REGNO (operands[1])))
- 	  /* This clobbers CC.  */
- 	  emit_insn (gen_arm_<shift>di3_1bit (operands[0], operands[1]));
- 	else
-@@ -1334,33 +1349,47 @@
- 
- ;; Reduction operations
- 
--(define_expand "reduc_splus_<mode>"
--  [(match_operand:VD 0 "s_register_operand" "")
-+(define_expand "reduc_plus_scal_<mode>"
-+  [(match_operand:<V_elem> 0 "nonimmediate_operand" "")
-    (match_operand:VD 1 "s_register_operand" "")]
-   "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
- {
--  neon_pairwise_reduce (operands[0], operands[1], <MODE>mode,
-+  rtx vec = gen_reg_rtx (<MODE>mode);
-+  neon_pairwise_reduce (vec, operands[1], <MODE>mode,
- 			&gen_neon_vpadd_internal<mode>);
-+  /* The same result is actually computed into every element.  */
-+  emit_insn (gen_vec_extract<mode> (operands[0], vec, const0_rtx));
-   DONE;
- })
- 
--(define_expand "reduc_splus_<mode>"
--  [(match_operand:VQ 0 "s_register_operand" "")
-+(define_expand "reduc_plus_scal_<mode>"
-+  [(match_operand:<V_elem> 0 "nonimmediate_operand" "")
-    (match_operand:VQ 1 "s_register_operand" "")]
-   "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)
-    && !BYTES_BIG_ENDIAN"
- {
-   rtx step1 = gen_reg_rtx (<V_HALF>mode);
--  rtx res_d = gen_reg_rtx (<V_HALF>mode);
- 
-   emit_insn (gen_quad_halves_plus<mode> (step1, operands[1]));
--  emit_insn (gen_reduc_splus_<V_half> (res_d, step1));
--  emit_insn (gen_move_lo_quad_<mode> (operands[0], res_d));
-+  emit_insn (gen_reduc_plus_scal_<V_half> (operands[0], step1));
- 
-   DONE;
- })
- 
--(define_insn "reduc_splus_v2di"
-+(define_expand "reduc_plus_scal_v2di"
-+  [(match_operand:DI 0 "nonimmediate_operand" "=w")
-+   (match_operand:V2DI 1 "s_register_operand" "")]
-+  "TARGET_NEON && !BYTES_BIG_ENDIAN"
-+{
-+  rtx vec = gen_reg_rtx (V2DImode);
-+
-+  emit_insn (gen_arm_reduc_plus_internal_v2di (vec, operands[1]));
-+  emit_insn (gen_vec_extractv2di (operands[0], vec, const0_rtx));
-+
-+  DONE;
-+})
-+
-+(define_insn "arm_reduc_plus_internal_v2di"
-   [(set (match_operand:V2DI 0 "s_register_operand" "=w")
- 	(unspec:V2DI [(match_operand:V2DI 1 "s_register_operand" "w")]
- 		     UNSPEC_VPADD))]
-@@ -1369,115 +1398,109 @@
-   [(set_attr "type" "neon_add_q")]
- )
- 
--;; NEON does not distinguish between signed and unsigned addition except on
--;; widening operations.
--(define_expand "reduc_uplus_<mode>"
--  [(match_operand:VDQI 0 "s_register_operand" "")
--   (match_operand:VDQI 1 "s_register_operand" "")]
--  "TARGET_NEON && (<Is_d_reg> || !BYTES_BIG_ENDIAN)"
--{
--  emit_insn (gen_reduc_splus_<mode> (operands[0], operands[1]));
--  DONE;
--})
--
--(define_expand "reduc_smin_<mode>"
--  [(match_operand:VD 0 "s_register_operand" "")
-+(define_expand "reduc_smin_scal_<mode>"
-+  [(match_operand:<V_elem> 0 "nonimmediate_operand" "")
-    (match_operand:VD 1 "s_register_operand" "")]
-   "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
- {
--  neon_pairwise_reduce (operands[0], operands[1], <MODE>mode,
-+  rtx vec = gen_reg_rtx (<MODE>mode);
-+
-+  neon_pairwise_reduce (vec, operands[1], <MODE>mode,
- 			&gen_neon_vpsmin<mode>);
-+  /* The result is computed into every element of the vector.  */
-+  emit_insn (gen_vec_extract<mode> (operands[0], vec, const0_rtx));
-   DONE;
- })
- 
--(define_expand "reduc_smin_<mode>"
--  [(match_operand:VQ 0 "s_register_operand" "")
-+(define_expand "reduc_smin_scal_<mode>"
-+  [(match_operand:<V_elem> 0 "nonimmediate_operand" "")
-    (match_operand:VQ 1 "s_register_operand" "")]
-   "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)
-    && !BYTES_BIG_ENDIAN"
- {
-   rtx step1 = gen_reg_rtx (<V_HALF>mode);
--  rtx res_d = gen_reg_rtx (<V_HALF>mode);
- 
-   emit_insn (gen_quad_halves_smin<mode> (step1, operands[1]));
--  emit_insn (gen_reduc_smin_<V_half> (res_d, step1));
--  emit_insn (gen_move_lo_quad_<mode> (operands[0], res_d));
-+  emit_insn (gen_reduc_smin_scal_<V_half> (operands[0], step1));
- 
-   DONE;
- })
- 
--(define_expand "reduc_smax_<mode>"
--  [(match_operand:VD 0 "s_register_operand" "")
-+(define_expand "reduc_smax_scal_<mode>"
-+  [(match_operand:<V_elem> 0 "nonimmediate_operand" "")
-    (match_operand:VD 1 "s_register_operand" "")]
-   "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
- {
--  neon_pairwise_reduce (operands[0], operands[1], <MODE>mode,
-+  rtx vec = gen_reg_rtx (<MODE>mode);
-+  neon_pairwise_reduce (vec, operands[1], <MODE>mode,
- 			&gen_neon_vpsmax<mode>);
-+  /* The result is computed into every element of the vector.  */
-+  emit_insn (gen_vec_extract<mode> (operands[0], vec, const0_rtx));
-   DONE;
- })
- 
--(define_expand "reduc_smax_<mode>"
--  [(match_operand:VQ 0 "s_register_operand" "")
-+(define_expand "reduc_smax_scal_<mode>"
-+  [(match_operand:<V_elem> 0 "nonimmediate_operand" "")
-    (match_operand:VQ 1 "s_register_operand" "")]
-   "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)
-    && !BYTES_BIG_ENDIAN"
- {
-   rtx step1 = gen_reg_rtx (<V_HALF>mode);
--  rtx res_d = gen_reg_rtx (<V_HALF>mode);
- 
-   emit_insn (gen_quad_halves_smax<mode> (step1, operands[1]));
--  emit_insn (gen_reduc_smax_<V_half> (res_d, step1));
--  emit_insn (gen_move_lo_quad_<mode> (operands[0], res_d));
-+  emit_insn (gen_reduc_smax_scal_<V_half> (operands[0], step1));
- 
-   DONE;
- })
- 
--(define_expand "reduc_umin_<mode>"
--  [(match_operand:VDI 0 "s_register_operand" "")
-+(define_expand "reduc_umin_scal_<mode>"
-+  [(match_operand:<V_elem> 0 "nonimmediate_operand" "")
-    (match_operand:VDI 1 "s_register_operand" "")]
-   "TARGET_NEON"
- {
--  neon_pairwise_reduce (operands[0], operands[1], <MODE>mode,
-+  rtx vec = gen_reg_rtx (<MODE>mode);
-+  neon_pairwise_reduce (vec, operands[1], <MODE>mode,
- 			&gen_neon_vpumin<mode>);
-+  /* The result is computed into every element of the vector.  */
-+  emit_insn (gen_vec_extract<mode> (operands[0], vec, const0_rtx));
-   DONE;
- })
- 
--(define_expand "reduc_umin_<mode>"
--  [(match_operand:VQI 0 "s_register_operand" "")
-+(define_expand "reduc_umin_scal_<mode>"
-+  [(match_operand:<V_elem> 0 "nonimmediate_operand" "")
-    (match_operand:VQI 1 "s_register_operand" "")]
-   "TARGET_NEON && !BYTES_BIG_ENDIAN"
- {
-   rtx step1 = gen_reg_rtx (<V_HALF>mode);
--  rtx res_d = gen_reg_rtx (<V_HALF>mode);
- 
-   emit_insn (gen_quad_halves_umin<mode> (step1, operands[1]));
--  emit_insn (gen_reduc_umin_<V_half> (res_d, step1));
--  emit_insn (gen_move_lo_quad_<mode> (operands[0], res_d));
-+  emit_insn (gen_reduc_umin_scal_<V_half> (operands[0], step1));
- 
-   DONE;
- })
- 
--(define_expand "reduc_umax_<mode>"
--  [(match_operand:VDI 0 "s_register_operand" "")
-+(define_expand "reduc_umax_scal_<mode>"
-+  [(match_operand:<V_elem> 0 "nonimmediate_operand" "")
-    (match_operand:VDI 1 "s_register_operand" "")]
-   "TARGET_NEON"
- {
--  neon_pairwise_reduce (operands[0], operands[1], <MODE>mode,
-+  rtx vec = gen_reg_rtx (<MODE>mode);
-+  neon_pairwise_reduce (vec, operands[1], <MODE>mode,
- 			&gen_neon_vpumax<mode>);
-+  /* The result is computed into every element of the vector.  */
-+  emit_insn (gen_vec_extract<mode> (operands[0], vec, const0_rtx));
-   DONE;
- })
- 
--(define_expand "reduc_umax_<mode>"
--  [(match_operand:VQI 0 "s_register_operand" "")
-+(define_expand "reduc_umax_scal_<mode>"
-+  [(match_operand:<V_elem> 0 "nonimmediate_operand" "")
-    (match_operand:VQI 1 "s_register_operand" "")]
-   "TARGET_NEON && !BYTES_BIG_ENDIAN"
- {
-   rtx step1 = gen_reg_rtx (<V_HALF>mode);
--  rtx res_d = gen_reg_rtx (<V_HALF>mode);
- 
-   emit_insn (gen_quad_halves_umax<mode> (step1, operands[1]));
--  emit_insn (gen_reduc_umax_<V_half> (res_d, step1));
--  emit_insn (gen_move_lo_quad_<mode> (operands[0], res_d));
-+  emit_insn (gen_reduc_umax_scal_<V_half> (operands[0], step1));
- 
-   DONE;
- })
-@@ -1842,9 +1865,9 @@
- ; good for plain vadd, vaddq.
- 
- (define_expand "neon_vadd<mode>"
--  [(match_operand:VDQX 0 "s_register_operand" "=w")
--   (match_operand:VDQX 1 "s_register_operand" "w")
--   (match_operand:VDQX 2 "s_register_operand" "w")
-+  [(match_operand:VCVTF 0 "s_register_operand" "=w")
-+   (match_operand:VCVTF 1 "s_register_operand" "w")
-+   (match_operand:VCVTF 2 "s_register_operand" "w")
-    (match_operand:SI 3 "immediate_operand" "i")]
-   "TARGET_NEON"
- {
-@@ -1869,9 +1892,9 @@
- ; Used for intrinsics when flag_unsafe_math_optimizations is false.
- 
- (define_insn "neon_vadd<mode>_unspec"
--  [(set (match_operand:VDQX 0 "s_register_operand" "=w")
--        (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w")
--		      (match_operand:VDQX 2 "s_register_operand" "w")]
-+  [(set (match_operand:VCVTF 0 "s_register_operand" "=w")
-+        (unspec:VCVTF [(match_operand:VCVTF 1 "s_register_operand" "w")
-+		      (match_operand:VCVTF 2 "s_register_operand" "w")]
-                      UNSPEC_VADD))]
-   "TARGET_NEON"
-   "vadd.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
-@@ -2132,9 +2155,9 @@
- )
- 
- (define_expand "neon_vsub<mode>"
--  [(match_operand:VDQX 0 "s_register_operand" "=w")
--   (match_operand:VDQX 1 "s_register_operand" "w")
--   (match_operand:VDQX 2 "s_register_operand" "w")
-+  [(match_operand:VCVTF 0 "s_register_operand" "=w")
-+   (match_operand:VCVTF 1 "s_register_operand" "w")
-+   (match_operand:VCVTF 2 "s_register_operand" "w")
-    (match_operand:SI 3 "immediate_operand" "i")]
-   "TARGET_NEON"
- {
-@@ -2149,9 +2172,9 @@
- ; Used for intrinsics when flag_unsafe_math_optimizations is false.
- 
- (define_insn "neon_vsub<mode>_unspec"
--  [(set (match_operand:VDQX 0 "s_register_operand" "=w")
--        (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w")
--		      (match_operand:VDQX 2 "s_register_operand" "w")]
-+  [(set (match_operand:VCVTF 0 "s_register_operand" "=w")
-+        (unspec:VCVTF [(match_operand:VCVTF 1 "s_register_operand" "w")
-+		      (match_operand:VCVTF 2 "s_register_operand" "w")]
-                      UNSPEC_VSUB))]
-   "TARGET_NEON"
-   "vsub.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
-@@ -2547,6 +2570,14 @@
-   [(set_attr "type" "neon_qabs<q>")]
- )
- 
-+(define_insn "neon_bswap<mode>"
-+  [(set (match_operand:VDQHSD 0 "register_operand" "=w")
-+        (bswap:VDQHSD (match_operand:VDQHSD 1 "register_operand" "w")))]
-+  "TARGET_NEON"
-+  "vrev<V_sz_elem>.8\\t%<V_reg>0, %<V_reg>1"
-+  [(set_attr "type" "neon_rev<q>")]
-+)
-+
- (define_expand "neon_vneg<mode>"
-   [(match_operand:VDQW 0 "s_register_operand" "")
-    (match_operand:VDQW 1 "s_register_operand" "")
-@@ -2557,6 +2588,33 @@
-   DONE;
- })
- 
-+(define_expand "neon_copysignf<mode>"
-+  [(match_operand:VCVTF 0 "register_operand")
-+   (match_operand:VCVTF 1 "register_operand")
-+   (match_operand:VCVTF 2 "register_operand")]
-+  "TARGET_NEON"
-+  "{
-+     rtx v_bitmask_cast;
-+     rtx v_bitmask = gen_reg_rtx (<VCVTF:V_cmp_result>mode);
-+     int i, n_elt = GET_MODE_NUNITS (<MODE>mode);
-+     rtvec v = rtvec_alloc (n_elt);
-+
-+     /* Create bitmask for vector select.  */
-+     for (i = 0; i < n_elt; ++i)
-+       RTVEC_ELT (v, i) = GEN_INT (0x80000000);
-+
-+     emit_move_insn (v_bitmask,
-+		     gen_rtx_CONST_VECTOR (<VCVTF:V_cmp_result>mode, v));
-+     emit_move_insn (operands[0], operands[2]);
-+     v_bitmask_cast = simplify_gen_subreg (<MODE>mode, v_bitmask,
-+					   <VCVTF:V_cmp_result>mode, 0);
-+     emit_insn (gen_neon_vbsl<mode> (operands[0], v_bitmask_cast, operands[0],
-+				     operands[1]));
-+
-+     DONE;
-+  }"
-+)
-+
- (define_insn "neon_vqneg<mode>"
-   [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
- 	(unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
-@@ -4140,17 +4198,6 @@
-   [(set_attr "type" "neon_permute<q>")]
- )
- 
--(define_expand "neon_vtrn<mode>"
--  [(match_operand:SI 0 "s_register_operand" "r")
--   (match_operand:VDQW 1 "s_register_operand" "w")
--   (match_operand:VDQW 2 "s_register_operand" "w")]
--  "TARGET_NEON"
--{
--  neon_emit_pair_result_insn (<MODE>mode, gen_neon_vtrn<mode>_internal,
--			      operands[0], operands[1], operands[2]);
--  DONE;
--})
--
- (define_expand "neon_vzip<mode>_internal"
-   [(parallel
-     [(set (match_operand:VDQW 0 "s_register_operand" "")
-@@ -4177,17 +4224,6 @@
-   [(set_attr "type" "neon_zip<q>")]
- )
- 
--(define_expand "neon_vzip<mode>"
--  [(match_operand:SI 0 "s_register_operand" "r")
--   (match_operand:VDQW 1 "s_register_operand" "w")
--   (match_operand:VDQW 2 "s_register_operand" "w")]
--  "TARGET_NEON"
--{
--  neon_emit_pair_result_insn (<MODE>mode, gen_neon_vzip<mode>_internal,
--			      operands[0], operands[1], operands[2]);
--  DONE;
--})
--
- (define_expand "neon_vuzp<mode>_internal"
-   [(parallel
-     [(set (match_operand:VDQW 0 "s_register_operand" "")
-@@ -4214,17 +4250,6 @@
-   [(set_attr "type" "neon_zip<q>")]
- )
- 
--(define_expand "neon_vuzp<mode>"
--  [(match_operand:SI 0 "s_register_operand" "r")
--   (match_operand:VDQW 1 "s_register_operand" "w")
--   (match_operand:VDQW 2 "s_register_operand" "w")]
--  "TARGET_NEON"
--{
--  neon_emit_pair_result_insn (<MODE>mode, gen_neon_vuzp<mode>_internal,
--			      operands[0], operands[1], operands[2]);
--  DONE;
--})
--
- (define_expand "neon_vreinterpretv8qi<mode>"
-   [(match_operand:V8QI 0 "s_register_operand" "")
-    (match_operand:VDX 1 "s_register_operand" "")]
-@@ -5357,61 +5382,6 @@
-   [(set_attr "type" "neon_store4_4reg<q>")]
- )
- 
--(define_expand "neon_vand<mode>"
--  [(match_operand:VDQX 0 "s_register_operand" "")
--   (match_operand:VDQX 1 "s_register_operand" "")
--   (match_operand:VDQX 2 "neon_inv_logic_op2" "")
--   (match_operand:SI 3 "immediate_operand" "")]
--  "TARGET_NEON"
--{
--  emit_insn (gen_and<mode>3 (operands[0], operands[1], operands[2]));
--  DONE;
--})
--
--(define_expand "neon_vorr<mode>"
--  [(match_operand:VDQX 0 "s_register_operand" "")
--   (match_operand:VDQX 1 "s_register_operand" "")
--   (match_operand:VDQX 2 "neon_logic_op2" "")
--   (match_operand:SI 3 "immediate_operand" "")]
--  "TARGET_NEON"
--{
--  emit_insn (gen_ior<mode>3 (operands[0], operands[1], operands[2]));
--  DONE;
--})
--
--(define_expand "neon_veor<mode>"
--  [(match_operand:VDQX 0 "s_register_operand" "")
--   (match_operand:VDQX 1 "s_register_operand" "")
--   (match_operand:VDQX 2 "s_register_operand" "")
--   (match_operand:SI 3 "immediate_operand" "")]
--  "TARGET_NEON"
--{
--  emit_insn (gen_xor<mode>3 (operands[0], operands[1], operands[2]));
--  DONE;
--})
--
--(define_expand "neon_vbic<mode>"
--  [(match_operand:VDQX 0 "s_register_operand" "")
--   (match_operand:VDQX 1 "s_register_operand" "")
--   (match_operand:VDQX 2 "neon_logic_op2" "")
--   (match_operand:SI 3 "immediate_operand" "")]
--  "TARGET_NEON"
--{
--  emit_insn (gen_bic<mode>3_neon (operands[0], operands[1], operands[2]));
--  DONE;
--})
--
--(define_expand "neon_vorn<mode>"
--  [(match_operand:VDQX 0 "s_register_operand" "")
--   (match_operand:VDQX 1 "s_register_operand" "")
--   (match_operand:VDQX 2 "neon_inv_logic_op2" "")
--   (match_operand:SI 3 "immediate_operand" "")]
--  "TARGET_NEON"
--{
--  emit_insn (gen_orn<mode>3_neon (operands[0], operands[1], operands[2]));
--  DONE;
--})
--
- (define_insn "neon_vec_unpack<US>_lo_<mode>"
-   [(set (match_operand:<V_unpack> 0 "register_operand" "=w")
-         (SE:<V_unpack> (vec_select:<V_HALF>
---- a/src/gcc/config/arm/types.md
-+++ b/src/gcc/config/arm/types.md
-@@ -66,7 +66,6 @@
- ; f_mrc              transfer vfp to arm reg.
- ; f_mrrc             transfer vfp to two arm regs.
- ; f_rint[d,s]        double/single floating point rount to integral.
--; f_sel[d,s]         double/single floating byte select.
- ; f_store[d,s]       double/single store to memory.  Used for VFP unit.
- ; fadd[d,s]          double/single floating-point scalar addition.
- ; fcmp[d,s]          double/single floating-point compare.
-@@ -571,8 +570,6 @@
-   f_mrrc,\
-   f_rintd,\
-   f_rints,\
--  f_seld,\
--  f_sels,\
-   f_stored,\
-   f_stores,\
-   faddd,\
---- a/src/gcc/config/arm/arm_neon_builtins.def
-+++ b/src/gcc/config/arm/arm_neon_builtins.def
-@@ -18,8 +18,7 @@
-    along with GCC; see the file COPYING3.  If not see
-    <http://www.gnu.org/licenses/>.  */
- 
--VAR10 (BINOP, vadd,
--	v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
-+VAR2 (BINOP, vadd, v2sf, v4sf),
- VAR3 (BINOP, vaddl, v8qi, v4hi, v2si),
- VAR3 (BINOP, vaddw, v8qi, v4hi, v2si),
- VAR6 (BINOP, vhadd, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
-@@ -54,7 +53,7 @@
- VAR8 (SHIFTIMM, vqshlu_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
- VAR3 (SHIFTIMM, vshll_n, v8qi, v4hi, v2si),
- VAR8 (SHIFTACC, vsra_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
--VAR10 (BINOP, vsub, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
-+VAR2 (BINOP, vsub, v2sf, v4sf),
- VAR3 (BINOP, vsubl, v8qi, v4hi, v2si),
- VAR3 (BINOP, vsubw, v8qi, v4hi, v2si),
- VAR8 (BINOP, vqsub, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
-@@ -89,6 +88,7 @@
- VAR6 (UNOP, vqneg, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
- VAR6 (UNOP, vcls, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
- VAR6 (UNOP, vclz, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
-+VAR5 (BSWAP, bswap, v4hi, v8hi, v2si, v4si, v2di),
- VAR2 (UNOP, vcnt, v8qi, v16qi),
- VAR4 (UNOP, vrecpe, v2si, v2sf, v4si, v4sf),
- VAR4 (UNOP, vrsqrte, v2si, v2sf, v4si, v4sf),
-@@ -135,6 +135,7 @@
- VAR1 (FLOAT_NARROW, vcvtv4hf, v4sf),
- VAR10 (SELECT, vbsl,
- 	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
-+VAR2 (COPYSIGNF, copysignf, v2sf, v4sf),
- VAR2 (RINT, vrintn, v2sf, v4sf),
- VAR2 (RINT, vrinta, v2sf, v4sf),
- VAR2 (RINT, vrintp, v2sf, v4sf),
-@@ -141,6 +142,18 @@
- VAR2 (RINT, vrintm, v2sf, v4sf),
- VAR2 (RINT, vrintz, v2sf, v4sf),
- VAR2 (RINT, vrintx, v2sf, v4sf),
-+VAR1 (RINT, vcvtav2sf, v2si),
-+VAR1 (RINT, vcvtav4sf, v4si),
-+VAR1 (RINT, vcvtauv2sf, v2si),
-+VAR1 (RINT, vcvtauv4sf, v4si),
-+VAR1 (RINT, vcvtpv2sf, v2si),
-+VAR1 (RINT, vcvtpv4sf, v4si),
-+VAR1 (RINT, vcvtpuv2sf, v2si),
-+VAR1 (RINT, vcvtpuv4sf, v4si),
-+VAR1 (RINT, vcvtmv2sf, v2si),
-+VAR1 (RINT, vcvtmv4sf, v4si),
-+VAR1 (RINT, vcvtmuv2sf, v2si),
-+VAR1 (RINT, vcvtmuv4sf, v4si),
- VAR1 (VTBL, vtbl1, v8qi),
- VAR1 (VTBL, vtbl2, v8qi),
- VAR1 (VTBL, vtbl3, v8qi),
-@@ -149,9 +162,6 @@
- VAR1 (VTBX, vtbx2, v8qi),
- VAR1 (VTBX, vtbx3, v8qi),
- VAR1 (VTBX, vtbx4, v8qi),
--VAR8 (RESULTPAIR, vtrn, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
--VAR8 (RESULTPAIR, vzip, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
--VAR8 (RESULTPAIR, vuzp, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
- VAR5 (REINTERP, vreinterpretv8qi, v8qi, v4hi, v2si, v2sf, di),
- VAR5 (REINTERP, vreinterpretv4hi, v8qi, v4hi, v2si, v2sf, di),
- VAR5 (REINTERP, vreinterpretv2si, v8qi, v4hi, v2si, v2sf, di),
-@@ -199,14 +209,4 @@
- VAR9 (STORESTRUCT, vst4,
- 	v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
- VAR7 (STORESTRUCTLANE, vst4_lane,
--	v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
--VAR10 (LOGICBINOP, vand,
--	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
--VAR10 (LOGICBINOP, vorr,
--	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
--VAR10 (BINOP, veor,
--	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
--VAR10 (LOGICBINOP, vbic,
--	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
--VAR10 (LOGICBINOP, vorn,
--	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
-+	v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
---- a/src/gcc/config/arm/cortex-a7.md
-+++ b/src/gcc/config/arm/cortex-a7.md
-@@ -137,7 +137,7 @@
-   (and (eq_attr "tune" "cortexa7")
-        (eq_attr "type" "alu_reg,alus_reg,logic_reg,logics_reg,\
-                         adc_imm,adcs_imm,adc_reg,adcs_reg,\
--                        bfm,rev,\
-+                        bfm,clz,rbit,rev,\
-                         shift_imm,shift_reg,mov_reg,mvn_reg"))
-   "cortex_a7_ex1")
- 
---- a/src/gcc/config/arm/aarch-common-protos.h
-+++ b/src/gcc/config/arm/aarch-common-protos.h
-@@ -24,6 +24,9 @@
- #define GCC_AARCH_COMMON_PROTOS_H
- 
- extern int aarch_crypto_can_dual_issue (rtx, rtx);
-+extern bool aarch_rev16_p (rtx);
-+extern bool aarch_rev16_shleft_mask_imm_p (rtx, enum machine_mode);
-+extern bool aarch_rev16_shright_mask_imm_p (rtx, enum machine_mode);
- extern int arm_early_load_addr_dep (rtx, rtx);
- extern int arm_early_store_addr_dep (rtx, rtx);
- extern int arm_mac_accumulator_is_mul_result (rtx, rtx);
-@@ -54,6 +57,7 @@
-   const int bfi;		/* Bit-field insert.  */
-   const int bfx;		/* Bit-field extraction.  */
-   const int clz;		/* Count Leading Zeros.  */
-+  const int rev;		/* Reverse bits/bytes.  */
-   const int non_exec;		/* Extra cost when not executing insn.  */
-   const bool non_exec_costs_exec; /* True if non-execution must add the exec
- 				     cost.  */
---- a/src/gcc/config/arm/predicates.md
-+++ b/src/gcc/config/arm/predicates.md
-@@ -291,6 +291,15 @@
- 			      || ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
-        (match_test "mode == GET_MODE (op)")))
- 
-+(define_special_predicate "shift_nomul_operator"
-+  (and (ior (and (match_code "rotate")
-+		 (match_test "CONST_INT_P (XEXP (op, 1))
-+			      && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32"))
-+	    (and (match_code "ashift,ashiftrt,lshiftrt,rotatert")
-+		 (match_test "!CONST_INT_P (XEXP (op, 1))
-+			      || ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
-+       (match_test "mode == GET_MODE (op)")))
-+
- ;; True for shift operators which can be used with saturation instructions.
- (define_special_predicate "sat_shift_operator"
-   (and (ior (and (match_code "mult")
-@@ -681,5 +690,6 @@
-        (match_code "reg" "0")))
- 
- (define_predicate "call_insn_operand"
--  (ior (match_code "symbol_ref")
-+  (ior (and (match_code "symbol_ref")
-+	    (match_test "!arm_is_long_call_p (SYMBOL_REF_DECL (op))"))
-        (match_operand 0 "s_register_operand")))
---- a/src/gcc/config/arm/arm_neon.h
-+++ b/src/gcc/config/arm/arm_neon.h
-@@ -452,114 +452,121 @@
- } poly64x2x4_t;
- #endif
- 
--
--
-+/* vadd  */
- __extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
- vadd_s8 (int8x8_t __a, int8x8_t __b)
- {
--  return (int8x8_t)__builtin_neon_vaddv8qi (__a, __b, 1);
-+  return __a + __b;
- }
- 
- __extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
- vadd_s16 (int16x4_t __a, int16x4_t __b)
- {
--  return (int16x4_t)__builtin_neon_vaddv4hi (__a, __b, 1);
-+  return __a + __b;
- }
- 
- __extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
- vadd_s32 (int32x2_t __a, int32x2_t __b)
- {
--  return (int32x2_t)__builtin_neon_vaddv2si (__a, __b, 1);
-+  return __a + __b;
- }
- 
- __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
- vadd_f32 (float32x2_t __a, float32x2_t __b)
- {
--  return (float32x2_t)__builtin_neon_vaddv2sf (__a, __b, 3);
-+#ifdef __FAST_MATH
-+  return __a + __b;
-+#else
-+  return (float32x2_t) __builtin_neon_vaddv2sf (__a, __b, 3);
-+#endif
- }
- 
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vadd_u8 (uint8x8_t __a, uint8x8_t __b)
- {
--  return (uint8x8_t)__builtin_neon_vaddv8qi ((int8x8_t) __a, (int8x8_t) __b, 0);
-+  return __a + __b;
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vadd_u16 (uint16x4_t __a, uint16x4_t __b)
- {
--  return (uint16x4_t)__builtin_neon_vaddv4hi ((int16x4_t) __a, (int16x4_t) __b, 0);
-+  return __a + __b;
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vadd_u32 (uint32x2_t __a, uint32x2_t __b)
- {
--  return (uint32x2_t)__builtin_neon_vaddv2si ((int32x2_t) __a, (int32x2_t) __b, 0);
-+  return __a + __b;
- }
- 
- __extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
- vadd_s64 (int64x1_t __a, int64x1_t __b)
- {
--  return (int64x1_t)__builtin_neon_vadddi (__a, __b, 1);
-+  return __a + __b;
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vadd_u64 (uint64x1_t __a, uint64x1_t __b)
- {
--  return (uint64x1_t)__builtin_neon_vadddi ((int64x1_t) __a, (int64x1_t) __b, 0);
-+  return __a + __b;
- }
- 
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
- vaddq_s8 (int8x16_t __a, int8x16_t __b)
- {
--  return (int8x16_t)__builtin_neon_vaddv16qi (__a, __b, 1);
-+  return __a + __b;
- }
- 
- __extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
- vaddq_s16 (int16x8_t __a, int16x8_t __b)
- {
--  return (int16x8_t)__builtin_neon_vaddv8hi (__a, __b, 1);
-+  return __a + __b;
- }
- 
- __extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
- vaddq_s32 (int32x4_t __a, int32x4_t __b)
- {
--  return (int32x4_t)__builtin_neon_vaddv4si (__a, __b, 1);
-+  return __a + __b;
- }
- 
- __extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
- vaddq_s64 (int64x2_t __a, int64x2_t __b)
- {
--  return (int64x2_t)__builtin_neon_vaddv2di (__a, __b, 1);
-+  return __a + __b;
- }
- 
- __extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
- vaddq_f32 (float32x4_t __a, float32x4_t __b)
- {
--  return (float32x4_t)__builtin_neon_vaddv4sf (__a, __b, 3);
-+#ifdef __FAST_MATH
-+  return __a + __b;
-+#else
-+  return (float32x4_t) __builtin_neon_vaddv4sf (__a, __b, 3);
-+#endif
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vaddq_u8 (uint8x16_t __a, uint8x16_t __b)
- {
--  return (uint8x16_t)__builtin_neon_vaddv16qi ((int8x16_t) __a, (int8x16_t) __b, 0);
-+  return __a + __b;
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vaddq_u16 (uint16x8_t __a, uint16x8_t __b)
- {
--  return (uint16x8_t)__builtin_neon_vaddv8hi ((int16x8_t) __a, (int16x8_t) __b, 0);
-+  return __a + __b;
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vaddq_u32 (uint32x4_t __a, uint32x4_t __b)
- {
--  return (uint32x4_t)__builtin_neon_vaddv4si ((int32x4_t) __a, (int32x4_t) __b, 0);
-+  return __a + __b;
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vaddq_u64 (uint64x2_t __a, uint64x2_t __b)
- {
--  return (uint64x2_t)__builtin_neon_vaddv2di ((int64x2_t) __a, (int64x2_t) __b, 0);
-+  return __a + __b;
- }
- 
- __extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
-@@ -949,93 +956,102 @@
- __extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
- vmul_s8 (int8x8_t __a, int8x8_t __b)
- {
--  return (int8x8_t)__builtin_neon_vmulv8qi (__a, __b, 1);
-+  return __a * __b;
- }
- 
- __extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
- vmul_s16 (int16x4_t __a, int16x4_t __b)
- {
--  return (int16x4_t)__builtin_neon_vmulv4hi (__a, __b, 1);
-+  return __a * __b;
- }
- 
- __extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
- vmul_s32 (int32x2_t __a, int32x2_t __b)
- {
--  return (int32x2_t)__builtin_neon_vmulv2si (__a, __b, 1);
-+  return __a * __b;
- }
- 
- __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
- vmul_f32 (float32x2_t __a, float32x2_t __b)
- {
--  return (float32x2_t)__builtin_neon_vmulv2sf (__a, __b, 3);
-+#ifdef __FAST_MATH
-+  return __a * __b;
-+#else
-+  return (float32x2_t) __builtin_neon_vmulv2sf (__a, __b, 3);
-+#endif
-+
- }
- 
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vmul_u8 (uint8x8_t __a, uint8x8_t __b)
- {
--  return (uint8x8_t)__builtin_neon_vmulv8qi ((int8x8_t) __a, (int8x8_t) __b, 0);
-+  return __a * __b;
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vmul_u16 (uint16x4_t __a, uint16x4_t __b)
- {
--  return (uint16x4_t)__builtin_neon_vmulv4hi ((int16x4_t) __a, (int16x4_t) __b, 0);
-+  return __a * __b;
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vmul_u32 (uint32x2_t __a, uint32x2_t __b)
- {
--  return (uint32x2_t)__builtin_neon_vmulv2si ((int32x2_t) __a, (int32x2_t) __b, 0);
-+  return __a * __b;
- }
- 
--__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
--vmul_p8 (poly8x8_t __a, poly8x8_t __b)
--{
--  return (poly8x8_t)__builtin_neon_vmulv8qi ((int8x8_t) __a, (int8x8_t) __b, 2);
--}
--
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
- vmulq_s8 (int8x16_t __a, int8x16_t __b)
- {
--  return (int8x16_t)__builtin_neon_vmulv16qi (__a, __b, 1);
-+  return __a * __b;
- }
- 
- __extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
- vmulq_s16 (int16x8_t __a, int16x8_t __b)
- {
--  return (int16x8_t)__builtin_neon_vmulv8hi (__a, __b, 1);
-+  return __a * __b;
- }
- 
- __extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
- vmulq_s32 (int32x4_t __a, int32x4_t __b)
- {
--  return (int32x4_t)__builtin_neon_vmulv4si (__a, __b, 1);
-+  return __a * __b;
- }
- 
- __extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
- vmulq_f32 (float32x4_t __a, float32x4_t __b)
- {
--  return (float32x4_t)__builtin_neon_vmulv4sf (__a, __b, 3);
-+#ifdef __FAST_MATH
-+  return __a * __b;
-+#else
-+  return (float32x4_t) __builtin_neon_vmulv4sf (__a, __b, 3);
-+#endif
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vmulq_u8 (uint8x16_t __a, uint8x16_t __b)
- {
--  return (uint8x16_t)__builtin_neon_vmulv16qi ((int8x16_t) __a, (int8x16_t) __b, 0);
-+  return __a * __b;
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vmulq_u16 (uint16x8_t __a, uint16x8_t __b)
- {
--  return (uint16x8_t)__builtin_neon_vmulv8hi ((int16x8_t) __a, (int16x8_t) __b, 0);
-+  return __a * __b;
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vmulq_u32 (uint32x4_t __a, uint32x4_t __b)
- {
--  return (uint32x4_t)__builtin_neon_vmulv4si ((int32x4_t) __a, (int32x4_t) __b, 0);
-+  return __a * __b;
- }
- 
-+__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
-+vmul_p8 (poly8x8_t __a, poly8x8_t __b)
-+{
-+  return (poly8x8_t)__builtin_neon_vmulv8qi ((int8x8_t) __a, (int8x8_t) __b, 2);
-+}
-+
- __extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
- vmulq_p8 (poly8x16_t __a, poly8x16_t __b)
- {
-@@ -1520,112 +1536,121 @@
- }
- 
- #endif
-+
- __extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
- vsub_s8 (int8x8_t __a, int8x8_t __b)
- {
--  return (int8x8_t)__builtin_neon_vsubv8qi (__a, __b, 1);
-+  return __a - __b;
- }
- 
- __extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
- vsub_s16 (int16x4_t __a, int16x4_t __b)
- {
--  return (int16x4_t)__builtin_neon_vsubv4hi (__a, __b, 1);
-+  return __a - __b;
- }
- 
- __extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
- vsub_s32 (int32x2_t __a, int32x2_t __b)
- {
--  return (int32x2_t)__builtin_neon_vsubv2si (__a, __b, 1);
-+  return __a - __b;
- }
- 
- __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
- vsub_f32 (float32x2_t __a, float32x2_t __b)
- {
--  return (float32x2_t)__builtin_neon_vsubv2sf (__a, __b, 3);
-+#ifdef __FAST_MATH
-+  return __a - __b;
-+#else
-+  return (float32x2_t) __builtin_neon_vsubv2sf (__a, __b, 3);
-+#endif
- }
- 
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vsub_u8 (uint8x8_t __a, uint8x8_t __b)
- {
--  return (uint8x8_t)__builtin_neon_vsubv8qi ((int8x8_t) __a, (int8x8_t) __b, 0);
-+  return __a - __b;
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vsub_u16 (uint16x4_t __a, uint16x4_t __b)
- {
--  return (uint16x4_t)__builtin_neon_vsubv4hi ((int16x4_t) __a, (int16x4_t) __b, 0);
-+  return __a - __b;
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vsub_u32 (uint32x2_t __a, uint32x2_t __b)
- {
--  return (uint32x2_t)__builtin_neon_vsubv2si ((int32x2_t) __a, (int32x2_t) __b, 0);
-+  return __a - __b;
- }
- 
- __extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
- vsub_s64 (int64x1_t __a, int64x1_t __b)
- {
--  return (int64x1_t)__builtin_neon_vsubdi (__a, __b, 1);
-+  return __a - __b;
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vsub_u64 (uint64x1_t __a, uint64x1_t __b)
- {
--  return (uint64x1_t)__builtin_neon_vsubdi ((int64x1_t) __a, (int64x1_t) __b, 0);
-+  return __a - __b;
- }
- 
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
- vsubq_s8 (int8x16_t __a, int8x16_t __b)
- {
--  return (int8x16_t)__builtin_neon_vsubv16qi (__a, __b, 1);
-+  return __a - __b;
- }
- 
- __extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
- vsubq_s16 (int16x8_t __a, int16x8_t __b)
- {
--  return (int16x8_t)__builtin_neon_vsubv8hi (__a, __b, 1);
-+  return __a - __b;
- }
- 
- __extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
- vsubq_s32 (int32x4_t __a, int32x4_t __b)
- {
--  return (int32x4_t)__builtin_neon_vsubv4si (__a, __b, 1);
-+  return __a - __b;
- }
- 
- __extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
- vsubq_s64 (int64x2_t __a, int64x2_t __b)
- {
--  return (int64x2_t)__builtin_neon_vsubv2di (__a, __b, 1);
-+  return __a - __b;
- }
- 
- __extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
- vsubq_f32 (float32x4_t __a, float32x4_t __b)
- {
--  return (float32x4_t)__builtin_neon_vsubv4sf (__a, __b, 3);
-+#ifdef __FAST_MATH
-+  return __a - __b;
-+#else
-+  return (float32x4_t) __builtin_neon_vsubv4sf (__a, __b, 3);
-+#endif
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vsubq_u8 (uint8x16_t __a, uint8x16_t __b)
- {
--  return (uint8x16_t)__builtin_neon_vsubv16qi ((int8x16_t) __a, (int8x16_t) __b, 0);
-+  return __a - __b;
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vsubq_u16 (uint16x8_t __a, uint16x8_t __b)
- {
--  return (uint16x8_t)__builtin_neon_vsubv8hi ((int16x8_t) __a, (int16x8_t) __b, 0);
-+  return __a - __b;
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vsubq_u32 (uint32x4_t __a, uint32x4_t __b)
- {
--  return (uint32x4_t)__builtin_neon_vsubv4si ((int32x4_t) __a, (int32x4_t) __b, 0);
-+  return __a - __b;
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vsubq_u64 (uint64x2_t __a, uint64x2_t __b)
- {
--  return (uint64x2_t)__builtin_neon_vsubv2di ((int64x2_t) __a, (int64x2_t) __b, 0);
-+  return __a - __b;
- }
- 
- __extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
-@@ -11295,484 +11320,483 @@
- __extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
- vand_s8 (int8x8_t __a, int8x8_t __b)
- {
--  return (int8x8_t)__builtin_neon_vandv8qi (__a, __b, 1);
-+  return __a & __b;
- }
- 
- __extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
- vand_s16 (int16x4_t __a, int16x4_t __b)
- {
--  return (int16x4_t)__builtin_neon_vandv4hi (__a, __b, 1);
-+  return __a & __b;
- }
- 
- __extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
- vand_s32 (int32x2_t __a, int32x2_t __b)
- {
--  return (int32x2_t)__builtin_neon_vandv2si (__a, __b, 1);
-+  return __a & __b;
- }
- 
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vand_u8 (uint8x8_t __a, uint8x8_t __b)
- {
--  return (uint8x8_t)__builtin_neon_vandv8qi ((int8x8_t) __a, (int8x8_t) __b, 0);
-+  return __a & __b;
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vand_u16 (uint16x4_t __a, uint16x4_t __b)
- {
--  return (uint16x4_t)__builtin_neon_vandv4hi ((int16x4_t) __a, (int16x4_t) __b, 0);
-+  return __a & __b;
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vand_u32 (uint32x2_t __a, uint32x2_t __b)
- {
--  return (uint32x2_t)__builtin_neon_vandv2si ((int32x2_t) __a, (int32x2_t) __b, 0);
-+  return __a & __b;
- }
- 
- __extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
- vand_s64 (int64x1_t __a, int64x1_t __b)
- {
--  return (int64x1_t)__builtin_neon_vanddi (__a, __b, 1);
-+  return __a & __b;
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vand_u64 (uint64x1_t __a, uint64x1_t __b)
- {
--  return (uint64x1_t)__builtin_neon_vanddi ((int64x1_t) __a, (int64x1_t) __b, 0);
-+  return __a & __b;
- }
- 
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
- vandq_s8 (int8x16_t __a, int8x16_t __b)
- {
--  return (int8x16_t)__builtin_neon_vandv16qi (__a, __b, 1);
-+  return __a & __b;
- }
- 
- __extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
- vandq_s16 (int16x8_t __a, int16x8_t __b)
- {
--  return (int16x8_t)__builtin_neon_vandv8hi (__a, __b, 1);
-+  return __a & __b;
- }
- 
- __extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
- vandq_s32 (int32x4_t __a, int32x4_t __b)
- {
--  return (int32x4_t)__builtin_neon_vandv4si (__a, __b, 1);
-+  return __a & __b;
- }
- 
- __extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
- vandq_s64 (int64x2_t __a, int64x2_t __b)
- {
--  return (int64x2_t)__builtin_neon_vandv2di (__a, __b, 1);
-+  return __a & __b;
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vandq_u8 (uint8x16_t __a, uint8x16_t __b)
- {
--  return (uint8x16_t)__builtin_neon_vandv16qi ((int8x16_t) __a, (int8x16_t) __b, 0);
-+  return __a & __b;
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vandq_u16 (uint16x8_t __a, uint16x8_t __b)
- {
--  return (uint16x8_t)__builtin_neon_vandv8hi ((int16x8_t) __a, (int16x8_t) __b, 0);
-+  return __a & __b;
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vandq_u32 (uint32x4_t __a, uint32x4_t __b)
- {
--  return (uint32x4_t)__builtin_neon_vandv4si ((int32x4_t) __a, (int32x4_t) __b, 0);
-+  return __a & __b;
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vandq_u64 (uint64x2_t __a, uint64x2_t __b)
- {
--  return (uint64x2_t)__builtin_neon_vandv2di ((int64x2_t) __a, (int64x2_t) __b, 0);
-+  return __a & __b;
- }
- 
- __extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
- vorr_s8 (int8x8_t __a, int8x8_t __b)
- {
--  return (int8x8_t)__builtin_neon_vorrv8qi (__a, __b, 1);
-+  return __a | __b;
- }
- 
- __extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
- vorr_s16 (int16x4_t __a, int16x4_t __b)
- {
--  return (int16x4_t)__builtin_neon_vorrv4hi (__a, __b, 1);
-+  return __a | __b;
- }
- 
- __extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
- vorr_s32 (int32x2_t __a, int32x2_t __b)
- {
--  return (int32x2_t)__builtin_neon_vorrv2si (__a, __b, 1);
-+  return __a | __b;
- }
- 
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vorr_u8 (uint8x8_t __a, uint8x8_t __b)
- {
--  return (uint8x8_t)__builtin_neon_vorrv8qi ((int8x8_t) __a, (int8x8_t) __b, 0);
-+  return __a | __b;
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vorr_u16 (uint16x4_t __a, uint16x4_t __b)
- {
--  return (uint16x4_t)__builtin_neon_vorrv4hi ((int16x4_t) __a, (int16x4_t) __b, 0);
-+  return __a | __b;
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vorr_u32 (uint32x2_t __a, uint32x2_t __b)
- {
--  return (uint32x2_t)__builtin_neon_vorrv2si ((int32x2_t) __a, (int32x2_t) __b, 0);
-+  return __a | __b;
- }
- 
- __extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
- vorr_s64 (int64x1_t __a, int64x1_t __b)
- {
--  return (int64x1_t)__builtin_neon_vorrdi (__a, __b, 1);
-+  return __a | __b;
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vorr_u64 (uint64x1_t __a, uint64x1_t __b)
- {
--  return (uint64x1_t)__builtin_neon_vorrdi ((int64x1_t) __a, (int64x1_t) __b, 0);
-+  return __a | __b;
- }
- 
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
- vorrq_s8 (int8x16_t __a, int8x16_t __b)
- {
--  return (int8x16_t)__builtin_neon_vorrv16qi (__a, __b, 1);
-+  return __a | __b;
- }
- 
- __extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
- vorrq_s16 (int16x8_t __a, int16x8_t __b)
- {
--  return (int16x8_t)__builtin_neon_vorrv8hi (__a, __b, 1);
-+  return __a | __b;
- }
- 
- __extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
- vorrq_s32 (int32x4_t __a, int32x4_t __b)
- {
--  return (int32x4_t)__builtin_neon_vorrv4si (__a, __b, 1);
-+  return __a | __b;
- }
- 
- __extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
- vorrq_s64 (int64x2_t __a, int64x2_t __b)
- {
--  return (int64x2_t)__builtin_neon_vorrv2di (__a, __b, 1);
-+  return __a | __b;
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vorrq_u8 (uint8x16_t __a, uint8x16_t __b)
- {
--  return (uint8x16_t)__builtin_neon_vorrv16qi ((int8x16_t) __a, (int8x16_t) __b, 0);
-+  return __a | __b;
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vorrq_u16 (uint16x8_t __a, uint16x8_t __b)
- {
--  return (uint16x8_t)__builtin_neon_vorrv8hi ((int16x8_t) __a, (int16x8_t) __b, 0);
-+  return __a | __b;
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vorrq_u32 (uint32x4_t __a, uint32x4_t __b)
- {
--  return (uint32x4_t)__builtin_neon_vorrv4si ((int32x4_t) __a, (int32x4_t) __b, 0);
-+  return __a | __b;
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vorrq_u64 (uint64x2_t __a, uint64x2_t __b)
- {
--  return (uint64x2_t)__builtin_neon_vorrv2di ((int64x2_t) __a, (int64x2_t) __b, 0);
-+  return __a | __b;
- }
- 
- __extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
- veor_s8 (int8x8_t __a, int8x8_t __b)
- {
--  return (int8x8_t)__builtin_neon_veorv8qi (__a, __b, 1);
-+  return __a ^ __b;
- }
- 
- __extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
- veor_s16 (int16x4_t __a, int16x4_t __b)
- {
--  return (int16x4_t)__builtin_neon_veorv4hi (__a, __b, 1);
-+  return __a ^ __b;
- }
- 
- __extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
- veor_s32 (int32x2_t __a, int32x2_t __b)
- {
--  return (int32x2_t)__builtin_neon_veorv2si (__a, __b, 1);
-+  return __a ^ __b;
- }
- 
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- veor_u8 (uint8x8_t __a, uint8x8_t __b)
- {
--  return (uint8x8_t)__builtin_neon_veorv8qi ((int8x8_t) __a, (int8x8_t) __b, 0);
-+  return __a ^ __b;
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- veor_u16 (uint16x4_t __a, uint16x4_t __b)
- {
--  return (uint16x4_t)__builtin_neon_veorv4hi ((int16x4_t) __a, (int16x4_t) __b, 0);
-+  return __a ^ __b;
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- veor_u32 (uint32x2_t __a, uint32x2_t __b)
- {
--  return (uint32x2_t)__builtin_neon_veorv2si ((int32x2_t) __a, (int32x2_t) __b, 0);
-+  return __a ^ __b;
- }
- 
- __extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
- veor_s64 (int64x1_t __a, int64x1_t __b)
- {
--  return (int64x1_t)__builtin_neon_veordi (__a, __b, 1);
-+  return __a ^ __b;
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- veor_u64 (uint64x1_t __a, uint64x1_t __b)
- {
--  return (uint64x1_t)__builtin_neon_veordi ((int64x1_t) __a, (int64x1_t) __b, 0);
-+  return __a ^ __b;
- }
- 
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
- veorq_s8 (int8x16_t __a, int8x16_t __b)
- {
--  return (int8x16_t)__builtin_neon_veorv16qi (__a, __b, 1);
-+  return __a ^ __b;
- }
- 
- __extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
- veorq_s16 (int16x8_t __a, int16x8_t __b)
- {
--  return (int16x8_t)__builtin_neon_veorv8hi (__a, __b, 1);
-+  return __a ^ __b;
- }
- 
- __extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
- veorq_s32 (int32x4_t __a, int32x4_t __b)
- {
--  return (int32x4_t)__builtin_neon_veorv4si (__a, __b, 1);
-+  return __a ^ __b;
- }
- 
- __extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
- veorq_s64 (int64x2_t __a, int64x2_t __b)
- {
--  return (int64x2_t)__builtin_neon_veorv2di (__a, __b, 1);
-+  return __a ^ __b;
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- veorq_u8 (uint8x16_t __a, uint8x16_t __b)
- {
--  return (uint8x16_t)__builtin_neon_veorv16qi ((int8x16_t) __a, (int8x16_t) __b, 0);
-+  return __a ^ __b;
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- veorq_u16 (uint16x8_t __a, uint16x8_t __b)
- {
--  return (uint16x8_t)__builtin_neon_veorv8hi ((int16x8_t) __a, (int16x8_t) __b, 0);
-+  return __a ^ __b;
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- veorq_u32 (uint32x4_t __a, uint32x4_t __b)
- {
--  return (uint32x4_t)__builtin_neon_veorv4si ((int32x4_t) __a, (int32x4_t) __b, 0);
-+  return __a ^ __b;
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- veorq_u64 (uint64x2_t __a, uint64x2_t __b)
- {
--  return (uint64x2_t)__builtin_neon_veorv2di ((int64x2_t) __a, (int64x2_t) __b, 0);
-+  return __a ^ __b;
- }
- 
- __extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
- vbic_s8 (int8x8_t __a, int8x8_t __b)
- {
--  return (int8x8_t)__builtin_neon_vbicv8qi (__a, __b, 1);
-+  return __a & ~__b;
- }
- 
- __extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
- vbic_s16 (int16x4_t __a, int16x4_t __b)
- {
--  return (int16x4_t)__builtin_neon_vbicv4hi (__a, __b, 1);
-+  return __a & ~__b;
- }
- 
- __extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
- vbic_s32 (int32x2_t __a, int32x2_t __b)
- {
--  return (int32x2_t)__builtin_neon_vbicv2si (__a, __b, 1);
-+  return __a & ~__b;
- }
- 
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vbic_u8 (uint8x8_t __a, uint8x8_t __b)
- {
--  return (uint8x8_t)__builtin_neon_vbicv8qi ((int8x8_t) __a, (int8x8_t) __b, 0);
-+  return __a & ~__b;
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vbic_u16 (uint16x4_t __a, uint16x4_t __b)
- {
--  return (uint16x4_t)__builtin_neon_vbicv4hi ((int16x4_t) __a, (int16x4_t) __b, 0);
-+  return __a & ~__b;
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vbic_u32 (uint32x2_t __a, uint32x2_t __b)
- {
--  return (uint32x2_t)__builtin_neon_vbicv2si ((int32x2_t) __a, (int32x2_t) __b, 0);
-+  return __a & ~__b;
- }
- 
- __extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
- vbic_s64 (int64x1_t __a, int64x1_t __b)
- {
--  return (int64x1_t)__builtin_neon_vbicdi (__a, __b, 1);
-+  return __a & ~__b;
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vbic_u64 (uint64x1_t __a, uint64x1_t __b)
- {
--  return (uint64x1_t)__builtin_neon_vbicdi ((int64x1_t) __a, (int64x1_t) __b, 0);
-+  return __a & ~__b;
- }
- 
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
- vbicq_s8 (int8x16_t __a, int8x16_t __b)
- {
--  return (int8x16_t)__builtin_neon_vbicv16qi (__a, __b, 1);
-+  return __a & ~__b;
- }
- 
- __extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
- vbicq_s16 (int16x8_t __a, int16x8_t __b)
- {
--  return (int16x8_t)__builtin_neon_vbicv8hi (__a, __b, 1);
-+  return __a & ~__b;
- }
- 
- __extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
- vbicq_s32 (int32x4_t __a, int32x4_t __b)
- {
--  return (int32x4_t)__builtin_neon_vbicv4si (__a, __b, 1);
-+  return __a & ~__b;
- }
- 
- __extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
- vbicq_s64 (int64x2_t __a, int64x2_t __b)
- {
--  return (int64x2_t)__builtin_neon_vbicv2di (__a, __b, 1);
-+  return __a & ~__b;
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vbicq_u8 (uint8x16_t __a, uint8x16_t __b)
- {
--  return (uint8x16_t)__builtin_neon_vbicv16qi ((int8x16_t) __a, (int8x16_t) __b, 0);
-+  return __a & ~__b;
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vbicq_u16 (uint16x8_t __a, uint16x8_t __b)
- {
--  return (uint16x8_t)__builtin_neon_vbicv8hi ((int16x8_t) __a, (int16x8_t) __b, 0);
-+  return __a & ~__b;
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vbicq_u32 (uint32x4_t __a, uint32x4_t __b)
- {
--  return (uint32x4_t)__builtin_neon_vbicv4si ((int32x4_t) __a, (int32x4_t) __b, 0);
-+  return __a & ~__b;
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vbicq_u64 (uint64x2_t __a, uint64x2_t __b)
- {
--  return (uint64x2_t)__builtin_neon_vbicv2di ((int64x2_t) __a, (int64x2_t) __b, 0);
-+  return __a & ~__b;
- }
- 
- __extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
- vorn_s8 (int8x8_t __a, int8x8_t __b)
- {
--  return (int8x8_t)__builtin_neon_vornv8qi (__a, __b, 1);
-+  return __a | ~__b;
- }
- 
- __extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
- vorn_s16 (int16x4_t __a, int16x4_t __b)
- {
--  return (int16x4_t)__builtin_neon_vornv4hi (__a, __b, 1);
-+  return __a | ~__b;
- }
- 
- __extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
- vorn_s32 (int32x2_t __a, int32x2_t __b)
- {
--  return (int32x2_t)__builtin_neon_vornv2si (__a, __b, 1);
-+  return __a | ~__b;
- }
- 
- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
- vorn_u8 (uint8x8_t __a, uint8x8_t __b)
- {
--  return (uint8x8_t)__builtin_neon_vornv8qi ((int8x8_t) __a, (int8x8_t) __b, 0);
-+  return __a | ~__b;
- }
- 
- __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
- vorn_u16 (uint16x4_t __a, uint16x4_t __b)
- {
--  return (uint16x4_t)__builtin_neon_vornv4hi ((int16x4_t) __a, (int16x4_t) __b, 0);
-+  return __a | ~__b;
- }
- 
- __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
- vorn_u32 (uint32x2_t __a, uint32x2_t __b)
- {
--  return (uint32x2_t)__builtin_neon_vornv2si ((int32x2_t) __a, (int32x2_t) __b, 0);
-+  return __a | ~__b;
- }
- 
- __extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
- vorn_s64 (int64x1_t __a, int64x1_t __b)
- {
--  return (int64x1_t)__builtin_neon_vorndi (__a, __b, 1);
-+  return __a | ~__b;
- }
- 
- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
- vorn_u64 (uint64x1_t __a, uint64x1_t __b)
- {
--  return (uint64x1_t)__builtin_neon_vorndi ((int64x1_t) __a, (int64x1_t) __b, 0);
-+  return __a | ~__b;
- }
- 
- __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
- vornq_s8 (int8x16_t __a, int8x16_t __b)
- {
--  return (int8x16_t)__builtin_neon_vornv16qi (__a, __b, 1);
-+  return __a | ~__b;
- }
- 
- __extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
- vornq_s16 (int16x8_t __a, int16x8_t __b)
- {
--  return (int16x8_t)__builtin_neon_vornv8hi (__a, __b, 1);
-+  return __a | ~__b;
- }
- 
- __extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
- vornq_s32 (int32x4_t __a, int32x4_t __b)
- {
--  return (int32x4_t)__builtin_neon_vornv4si (__a, __b, 1);
-+  return __a | ~__b;
- }
- 
- __extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
- vornq_s64 (int64x2_t __a, int64x2_t __b)
- {
--  return (int64x2_t)__builtin_neon_vornv2di (__a, __b, 1);
-+  return __a | ~__b;
- }
- 
- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
- vornq_u8 (uint8x16_t __a, uint8x16_t __b)
- {
--  return (uint8x16_t)__builtin_neon_vornv16qi ((int8x16_t) __a, (int8x16_t) __b, 0);
-+  return __a | ~__b;
- }
- 
- __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
- vornq_u16 (uint16x8_t __a, uint16x8_t __b)
- {
--  return (uint16x8_t)__builtin_neon_vornv8hi ((int16x8_t) __a, (int16x8_t) __b, 0);
-+  return __a | ~__b;
- }
- 
- __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
- vornq_u32 (uint32x4_t __a, uint32x4_t __b)
- {
--  return (uint32x4_t)__builtin_neon_vornv4si ((int32x4_t) __a, (int32x4_t) __b, 0);
-+  return __a | ~__b;
- }
- 
- __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
- vornq_u64 (uint64x2_t __a, uint64x2_t __b)
- {
--  return (uint64x2_t)__builtin_neon_vornv2di ((int64x2_t) __a, (int64x2_t) __b, 0);
-+  return __a | ~__b;
- }
- 
--
- __extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
- vreinterpret_p8_p16 (poly16x4_t __a)
- {
---- a/src/gcc/config/arm/aarch-common.c
-+++ b/src/gcc/config/arm/aarch-common.c
-@@ -191,6 +191,83 @@
-   return 0;
- }
- 
-+bool
-+aarch_rev16_shright_mask_imm_p (rtx val, enum machine_mode mode)
-+{
-+  return CONST_INT_P (val)
-+         && INTVAL (val)
-+            == trunc_int_for_mode (HOST_WIDE_INT_C (0xff00ff00ff00ff),
-+                                   mode);
-+}
-+
-+bool
-+aarch_rev16_shleft_mask_imm_p (rtx val, enum machine_mode mode)
-+{
-+  return CONST_INT_P (val)
-+         && INTVAL (val)
-+            == trunc_int_for_mode (HOST_WIDE_INT_C (0xff00ff00ff00ff00),
-+                                   mode);
-+}
-+
-+
-+static bool
-+aarch_rev16_p_1 (rtx lhs, rtx rhs, enum machine_mode mode)
-+{
-+  if (GET_CODE (lhs) == AND
-+         && GET_CODE (XEXP (lhs, 0)) == ASHIFT
-+            && CONST_INT_P (XEXP (XEXP (lhs, 0), 1))
-+            && INTVAL (XEXP (XEXP (lhs, 0), 1)) == 8
-+            && REG_P (XEXP (XEXP (lhs, 0), 0))
-+         && CONST_INT_P (XEXP (lhs, 1))
-+      && GET_CODE (rhs) == AND
-+         && GET_CODE (XEXP (rhs, 0)) == LSHIFTRT
-+            && REG_P (XEXP (XEXP (rhs, 0), 0))
-+            && CONST_INT_P (XEXP (XEXP (rhs, 0), 1))
-+            && INTVAL (XEXP (XEXP (rhs, 0), 1)) == 8
-+         && CONST_INT_P (XEXP (rhs, 1))
-+      && REGNO (XEXP (XEXP (rhs, 0), 0)) == REGNO (XEXP (XEXP (lhs, 0), 0)))
-+
-+    {
-+      rtx lhs_mask = XEXP (lhs, 1);
-+      rtx rhs_mask = XEXP (rhs, 1);
-+
-+      return aarch_rev16_shright_mask_imm_p (rhs_mask, mode)
-+             && aarch_rev16_shleft_mask_imm_p (lhs_mask, mode);
-+    }
-+
-+  return false;
-+}
-+
-+/* Recognise a sequence of bitwise operations corresponding to a rev16 operation.
-+   These will be of the form:
-+     ((x >> 8) & 0x00ff00ff)
-+   | ((x << 8) & 0xff00ff00)
-+   for SImode and with similar but wider bitmasks for DImode.
-+   The two sub-expressions of the IOR can appear on either side so check both
-+   permutations with the help of aarch_rev16_p_1 above.  */
-+
-+bool
-+aarch_rev16_p (rtx x)
-+{
-+  rtx left_sub_rtx, right_sub_rtx;
-+  bool is_rev = false;
-+
-+  if (GET_CODE (x) != IOR)
-+    return false;
-+
-+  left_sub_rtx = XEXP (x, 0);
-+  right_sub_rtx = XEXP (x, 1);
-+
-+  /* There are no canonicalisation rules for the position of the two shifts
-+     involved in a rev, so try both permutations.  */
-+  is_rev = aarch_rev16_p_1 (left_sub_rtx, right_sub_rtx, GET_MODE (x));
-+
-+  if (!is_rev)
-+    is_rev = aarch_rev16_p_1 (right_sub_rtx, left_sub_rtx, GET_MODE (x));
-+
-+  return is_rev;
-+}
-+
- /* Return nonzero if the CONSUMER instruction (a load) does need
-    PRODUCER's value to calculate the address.  */
- int
---- a/src/gcc/config/arm/arm-fpus.def
-+++ b/src/gcc/config/arm/arm-fpus.def
-@@ -37,6 +37,8 @@
- ARM_FPU("vfpv4",	ARM_FP_MODEL_VFP, 4, VFP_REG_D32, false, true, false)
- ARM_FPU("vfpv4-d16",	ARM_FP_MODEL_VFP, 4, VFP_REG_D16, false, true, false)
- ARM_FPU("fpv4-sp-d16",	ARM_FP_MODEL_VFP, 4, VFP_REG_SINGLE, false, true, false)
-+ARM_FPU("fpv5-sp-d16",	ARM_FP_MODEL_VFP, 5, VFP_REG_SINGLE, false, true, false)
-+ARM_FPU("fpv5-d16",	ARM_FP_MODEL_VFP, 5, VFP_REG_D16, false, true, false)
- ARM_FPU("neon-vfpv4",	ARM_FP_MODEL_VFP, 4, VFP_REG_D32, true, true, false)
- ARM_FPU("fp-armv8",	ARM_FP_MODEL_VFP, 8, VFP_REG_D32, false, true, false)
- ARM_FPU("neon-fp-armv8",ARM_FP_MODEL_VFP, 8, VFP_REG_D32, true, true, false)
---- a/src/gcc/config/arm/cortex-a53.md
-+++ b/src/gcc/config/arm/cortex-a53.md
-@@ -75,7 +75,7 @@
-        (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
-                         alu_reg,alus_reg,logic_reg,logics_reg,\
-                         adc_imm,adcs_imm,adc_reg,adcs_reg,\
--                        adr,bfm,csel,rev,\
-+                        adr,bfm,csel,clz,rbit,rev,\
-                         shift_imm,shift_reg,\
-                         mov_imm,mov_reg,mvn_imm,mvn_reg,\
-                         mrs,multiple,no_insn"))
-@@ -84,8 +84,8 @@
- (define_insn_reservation "cortex_a53_alu_shift" 2
-   (and (eq_attr "tune" "cortexa53")
-        (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
--                        logic_shift_imm,logics_shift_imm,\
--                        alu_shift_reg,alus_shift_reg,\
-+                        crc,logic_shift_imm,logics_shift_imm,\
-+                        alu_ext,alus_ext,alu_shift_reg,alus_shift_reg,\
-                         logic_shift_reg,logics_shift_reg,\
-                         extend,mov_shift,mov_shift_reg,\
-                         mvn_shift,mvn_shift_reg"))
-@@ -216,7 +216,8 @@
-   (and (eq_attr "tune" "cortexa53")
-        (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fmov, fmuls,\
-                         f_cvt,f_cvtf2i,f_cvti2f,\
--			fcmps, fcmpd, fcsel"))
-+                        fcmps, fcmpd, fcsel, f_rints, f_rintd, f_minmaxs,\
-+                        f_minmaxd"))
-   "cortex_a53_slot0+cortex_a53_fpadd_pipe")
- 
- (define_insn_reservation "cortex_a53_fconst" 2
---- a/src/gcc/config/arm/bpabi.h
-+++ b/src/gcc/config/arm/bpabi.h
-@@ -73,7 +73,7 @@
-    |mcpu=generic-armv7-a                                \
-    |march=armv7ve	                                \
-    |march=armv7-m|mcpu=cortex-m3                        \
--   |march=armv7e-m|mcpu=cortex-m4                       \
-+   |march=armv7e-m|mcpu=cortex-m4|mcpu=cortex-m7        \
-    |march=armv6-m|mcpu=cortex-m0                        \
-    |march=armv8-a					\
-    :%{!r:--be8}}}"
-@@ -91,7 +91,7 @@
-    |mcpu=generic-armv7-a                                \
-    |march=armv7ve	                                \
-    |march=armv7-m|mcpu=cortex-m3                        \
--   |march=armv7e-m|mcpu=cortex-m4                       \
-+   |march=armv7e-m|mcpu=cortex-m4|mcpu=cortex-m7        \
-    |march=armv6-m|mcpu=cortex-m0                        \
-    |march=armv8-a					\
-    :%{!r:--be8}}}"
---- a/src/gcc/config/arm/iterators.md
-+++ b/src/gcc/config/arm/iterators.md
-@@ -116,6 +116,9 @@
- ;; Vector modes including 64-bit integer elements, but no floats.
- (define_mode_iterator VDQIX [V8QI V16QI V4HI V8HI V2SI V4SI DI V2DI])
- 
-+;; Vector modes for H, S and D types.
-+(define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI])
-+
- ;; Vector modes for float->int conversions.
- (define_mode_iterator VCVTF [V2SF V4SF])
- 
-@@ -191,6 +194,23 @@
- ;; Right shifts
- (define_code_iterator rshifts [ashiftrt lshiftrt])
- 
-+;; Iterator for integer conversions
-+(define_code_iterator FIXUORS [fix unsigned_fix])
-+
-+;; Binary operators whose second operand can be shifted.
-+(define_code_iterator shiftable_ops [plus minus ior xor and])
-+
-+;; plus and minus are the only shiftable_ops for which Thumb2 allows
-+;; a stack pointer opoerand.  The minus operation is a candidate for an rsub
-+;; and hence only plus is supported.
-+(define_code_attr t2_binop0
-+  [(plus "rk") (minus "r") (ior "r") (xor "r") (and "r")])
-+
-+;; The instruction to use when a shiftable_ops has a shift operation as
-+;; its first operand.
-+(define_code_attr arith_shift_insn
-+  [(plus "add") (minus "rsb") (ior "orr") (xor "eor") (and "and")])
-+
- ;;----------------------------------------------------------------------------
- ;; Int iterators
- ;;----------------------------------------------------------------------------
-@@ -198,9 +218,13 @@
- (define_int_iterator VRINT [UNSPEC_VRINTZ UNSPEC_VRINTP UNSPEC_VRINTM
-                             UNSPEC_VRINTR UNSPEC_VRINTX UNSPEC_VRINTA])
- 
-+(define_int_iterator VCVT [UNSPEC_VRINTP UNSPEC_VRINTM UNSPEC_VRINTA])
-+
- (define_int_iterator NEON_VRINT [UNSPEC_NVRINTP UNSPEC_NVRINTZ UNSPEC_NVRINTM
-                               UNSPEC_NVRINTX UNSPEC_NVRINTA UNSPEC_NVRINTN])
- 
-+(define_int_iterator NEON_VCVT [UNSPEC_NVRINTP UNSPEC_NVRINTM UNSPEC_NVRINTA])
-+
- (define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W
-                           UNSPEC_CRC32CB UNSPEC_CRC32CH UNSPEC_CRC32CW])
- 
-@@ -502,6 +526,13 @@
- ;; Assembler mnemonics for signedness of widening operations.
- (define_code_attr US [(sign_extend "s") (zero_extend "u")])
- 
-+;; Signedness suffix for float->fixed conversions.  Empty for signed
-+;; conversion.
-+(define_code_attr su_optab [(fix "") (unsigned_fix "u")])
-+
-+;; Sign prefix to use in instruction type suffixes, i.e. s32, u32.
-+(define_code_attr su [(fix "s") (unsigned_fix "u")])
-+
- ;; Right shifts
- (define_code_attr shift [(ashiftrt "ashr") (lshiftrt "lshr")])
- (define_code_attr shifttype [(ashiftrt "signed") (lshiftrt "unsigned")])
---- a/src/gcc/config/arm/arm.md
-+++ b/src/gcc/config/arm/arm.md
-@@ -205,17 +205,9 @@
- 	  (const_string "yes")]
- 	 (const_string "no")))
- 
--; Allows an insn to disable certain alternatives for reasons other than
--; arch support.
--(define_attr "insn_enabled" "no,yes"
--  (const_string "yes"))
--
- ; Enable all alternatives that are both arch_enabled and insn_enabled.
-  (define_attr "enabled" "no,yes"
--   (cond [(eq_attr "insn_enabled" "no")
--	  (const_string "no")
--
--	  (and (eq_attr "predicable_short_it" "no")
-+   (cond [(and (eq_attr "predicable_short_it" "no")
- 	       (and (eq_attr "predicated" "yes")
- 	            (match_test "arm_restrict_it")))
- 	  (const_string "no")
-@@ -2868,6 +2860,28 @@
-    (set_attr "type" "multiple")]
- )
- 
-+(define_insn_and_split "*anddi_notdi_zesidi"
-+  [(set (match_operand:DI 0 "s_register_operand" "=r")
-+        (and:DI (not:DI (match_operand:DI 2 "s_register_operand" "r"))
-+                (zero_extend:DI
-+                 (match_operand:SI 1 "s_register_operand" "r"))))]
-+  "TARGET_32BIT"
-+  "#"
-+  "TARGET_32BIT && reload_completed"
-+  [(set (match_dup 0) (and:SI (not:SI (match_dup 2)) (match_dup 1)))
-+   (set (match_dup 3) (const_int 0))]
-+  "
-+  {
-+    operands[3] = gen_highpart (SImode, operands[0]);
-+    operands[0] = gen_lowpart (SImode, operands[0]);
-+    operands[2] = gen_lowpart (SImode, operands[2]);
-+  }"
-+  [(set_attr "length" "8")
-+   (set_attr "predicable" "yes")
-+   (set_attr "predicable_short_it" "no")
-+   (set_attr "type" "multiple")]
-+)
-+
- (define_insn_and_split "*anddi_notsesidi_di"
-   [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
- 	(and:DI (not:DI (sign_extend:DI
-@@ -8906,7 +8920,7 @@
-     return \"\";
-   }"
-   [(set_attr "conds" "use")
--   (set_attr "type" "f_sel<vfp_type>")]
-+   (set_attr "type" "fcsel")]
- )
- 
- (define_insn_and_split "*movsicc_insn"
-@@ -9343,8 +9357,10 @@
-   "TARGET_32BIT"
-   "
-   {
--    if (!REG_P (XEXP (operands[0], 0))
--       && (GET_CODE (XEXP (operands[0], 0)) != SYMBOL_REF))
-+    if ((!REG_P (XEXP (operands[0], 0))
-+	 && GET_CODE (XEXP (operands[0], 0)) != SYMBOL_REF)
-+	|| (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
-+	    && arm_is_long_call_p (SYMBOL_REF_DECL (XEXP (operands[0], 0)))))
-      XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0));
- 
-     if (operands[2] == NULL_RTX)
-@@ -9361,8 +9377,10 @@
-   "TARGET_32BIT"
-   "
-   {
--    if (!REG_P (XEXP (operands[1], 0)) &&
--       (GET_CODE (XEXP (operands[1],0)) != SYMBOL_REF))
-+    if ((!REG_P (XEXP (operands[1], 0))
-+	 && GET_CODE (XEXP (operands[1], 0)) != SYMBOL_REF)
-+	|| (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
-+	    && arm_is_long_call_p (SYMBOL_REF_DECL (XEXP (operands[1], 0)))))
-      XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0));
- 
-     if (operands[3] == NULL_RTX)
-@@ -9848,39 +9866,35 @@
- 
- ;; Patterns to allow combination of arithmetic, cond code and shifts
- 
--(define_insn "*arith_shiftsi"
--  [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r")
--        (match_operator:SI 1 "shiftable_operator"
--          [(match_operator:SI 3 "shift_operator"
--             [(match_operand:SI 4 "s_register_operand" "r,r,r,r")
--              (match_operand:SI 5 "shift_amount_operand" "M,M,M,r")])
--           (match_operand:SI 2 "s_register_operand" "rk,rk,r,rk")]))]
-+(define_insn "*<arith_shift_insn>_multsi"
-+  [(set (match_operand:SI 0 "s_register_operand" "=r,r")
-+	(shiftable_ops:SI
-+	 (mult:SI (match_operand:SI 2 "s_register_operand" "r,r")
-+		  (match_operand:SI 3 "power_of_two_operand" ""))
-+	 (match_operand:SI 1 "s_register_operand" "rk,<t2_binop0>")))]
-   "TARGET_32BIT"
--  "%i1%?\\t%0, %2, %4%S3"
-+  "<arith_shift_insn>%?\\t%0, %1, %2, lsl %b3"
-   [(set_attr "predicable" "yes")
-    (set_attr "predicable_short_it" "no")
-    (set_attr "shift" "4")
--   (set_attr "arch" "a,t2,t2,a")
--   ;; Thumb2 doesn't allow the stack pointer to be used for 
--   ;; operand1 for all operations other than add and sub. In this case 
--   ;; the minus operation is a candidate for an rsub and hence needs
--   ;; to be disabled.
--   ;; We have to make sure to disable the fourth alternative if
--   ;; the shift_operator is MULT, since otherwise the insn will
--   ;; also match a multiply_accumulate pattern and validate_change
--   ;; will allow a replacement of the constant with a register
--   ;; despite the checks done in shift_operator.
--   (set_attr_alternative "insn_enabled"
--			 [(const_string "yes")
--			  (if_then_else
--			   (match_operand:SI 1 "add_operator" "")
--			   (const_string "yes") (const_string "no"))
--			  (const_string "yes")
--			  (if_then_else
--			   (match_operand:SI 3 "mult_operator" "")
--			   (const_string "no") (const_string "yes"))])
--   (set_attr "type" "alu_shift_imm,alu_shift_imm,alu_shift_imm,alu_shift_reg")])
-+   (set_attr "arch" "a,t2")
-+   (set_attr "type" "alu_shift_imm")])
- 
-+(define_insn "*<arith_shift_insn>_shiftsi"
-+  [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
-+	(shiftable_ops:SI
-+	 (match_operator:SI 2 "shift_nomul_operator"
-+	  [(match_operand:SI 3 "s_register_operand" "r,r,r")
-+	   (match_operand:SI 4 "shift_amount_operand" "M,M,r")])
-+	 (match_operand:SI 1 "s_register_operand" "rk,<t2_binop0>,rk")))]
-+  "TARGET_32BIT && GET_CODE (operands[3]) != MULT"
-+  "<arith_shift_insn>%?\\t%0, %1, %3%S2"
-+  [(set_attr "predicable" "yes")
-+   (set_attr "predicable_short_it" "no")
-+   (set_attr "shift" "4")
-+   (set_attr "arch" "a,t2,a")
-+   (set_attr "type" "alu_shift_imm,alu_shift_imm,alu_shift_reg")])
-+
- (define_split
-   [(set (match_operand:SI 0 "s_register_operand" "")
- 	(match_operator:SI 1 "shiftable_operator"
-@@ -12169,7 +12183,7 @@
-     int num_regs = XVECLEN (operands[0], 0);
-     char pattern[100];
-     rtx op_list[2];
--    strcpy (pattern, \"fldmfdd\\t\");
-+    strcpy (pattern, \"vldm\\t\");
-     strcat (pattern, reg_names[REGNO (SET_DEST (XVECEXP (operands[0], 0, 0)))]);
-     strcat (pattern, \"!, {\");
-     op_list[0] = XEXP (XVECEXP (operands[0], 0, 1), 0);
-@@ -12373,6 +12387,7 @@
-   "TARGET_32BIT && arm_arch5"
-   "clz%?\\t%0, %1"
-   [(set_attr "predicable" "yes")
-+   (set_attr "predicable_short_it" "no")
-    (set_attr "type" "clz")])
- 
- (define_insn "rbitsi2"
-@@ -12381,6 +12396,7 @@
-   "TARGET_32BIT && arm_arch_thumb2"
-   "rbit%?\\t%0, %1"
-   [(set_attr "predicable" "yes")
-+   (set_attr "predicable_short_it" "no")
-    (set_attr "type" "clz")])
- 
- (define_expand "ctzsi2"
-@@ -12556,6 +12572,8 @@
-    rev%?\t%0, %1"
-   [(set_attr "arch" "t1,t2,32")
-    (set_attr "length" "2,2,4")
-+   (set_attr "predicable" "no,yes,yes")
-+   (set_attr "predicable_short_it" "no")
-    (set_attr "type" "rev")]
- )
- 
-@@ -12673,6 +12691,44 @@
-    (set_attr "type" "rev")]
- )
- 
-+;; There are no canonicalisation rules for the position of the lshiftrt, ashift
-+;; operations within an IOR/AND RTX, therefore we have two patterns matching
-+;; each valid permutation.
-+
-+(define_insn "arm_rev16si2"
-+  [(set (match_operand:SI 0 "register_operand" "=l,l,r")
-+        (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "l,l,r")
-+                                   (const_int 8))
-+                        (match_operand:SI 3 "const_int_operand" "n,n,n"))
-+                (and:SI (lshiftrt:SI (match_dup 1)
-+                                     (const_int 8))
-+                        (match_operand:SI 2 "const_int_operand" "n,n,n"))))]
-+  "arm_arch6
-+   && aarch_rev16_shleft_mask_imm_p (operands[3], SImode)
-+   && aarch_rev16_shright_mask_imm_p (operands[2], SImode)"
-+  "rev16\\t%0, %1"
-+  [(set_attr "arch" "t1,t2,32")
-+   (set_attr "length" "2,2,4")
-+   (set_attr "type" "rev")]
-+)
-+
-+(define_insn "arm_rev16si2_alt"
-+  [(set (match_operand:SI 0 "register_operand" "=l,l,r")
-+        (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "l,l,r")
-+                                     (const_int 8))
-+                        (match_operand:SI 2 "const_int_operand" "n,n,n"))
-+                (and:SI (ashift:SI (match_dup 1)
-+                                   (const_int 8))
-+                        (match_operand:SI 3 "const_int_operand" "n,n,n"))))]
-+  "arm_arch6
-+   && aarch_rev16_shleft_mask_imm_p (operands[3], SImode)
-+   && aarch_rev16_shright_mask_imm_p (operands[2], SImode)"
-+  "rev16\\t%0, %1"
-+  [(set_attr "arch" "t1,t2,32")
-+   (set_attr "length" "2,2,4")
-+   (set_attr "type" "rev")]
-+)
-+
- (define_expand "bswaphi2"
-   [(set (match_operand:HI 0 "s_register_operand" "=r")
- 	(bswap:HI (match_operand:HI 1 "s_register_operand" "r")))]
---- a/src/gcc/config/arm/cortex-a5.md
-+++ b/src/gcc/config/arm/cortex-a5.md
-@@ -61,7 +61,7 @@
-        (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
-                         alu_reg,alus_reg,logic_reg,logics_reg,\
-                         adc_imm,adcs_imm,adc_reg,adcs_reg,\
--                        adr,bfm,rev,\
-+                        adr,bfm,clz,rbit,rev,\
-                         shift_imm,shift_reg,\
-                         mov_imm,mov_reg,mvn_imm,mvn_reg,\
-                         mrs,multiple,no_insn"))
---- a/src/gcc/config/arm/cortex-a9.md
-+++ b/src/gcc/config/arm/cortex-a9.md
-@@ -83,7 +83,7 @@
-        (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
-                         alu_reg,alus_reg,logic_reg,logics_reg,\
-                         adc_imm,adcs_imm,adc_reg,adcs_reg,\
--                        adr,bfm,rev,\
-+                        adr,bfm,clz,rbit,rev,\
-                         shift_imm,shift_reg,\
-                         mov_imm,mov_reg,mvn_imm,mvn_reg,\
-                         mov_shift_reg,mov_shift,\
---- a/src/gcc/config/mips/mips.c
-+++ b/src/gcc/config/mips/mips.c
-@@ -7197,12 +7197,17 @@
-   emit_insn (gen_slt_sf (dest, fp2, fp1));
- }
- 
--/* Implement MOVE_BY_PIECES_P.  */
-+/* Implement TARGET_USE_MOVE_BY_PIECES_INFRASTRUCTURE_P.  */
- 
- bool
--mips_move_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
-+mips_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size,
-+				     unsigned int align,
-+				     enum by_pieces_operation op,
-+				     bool speed_p)
- {
--  if (HAVE_movmemsi)
-+  if (op == STORE_BY_PIECES)
-+    return mips_store_by_pieces_p (size, align);
-+  if (op == MOVE_BY_PIECES && HAVE_movmemsi)
-     {
-       /* movmemsi is meant to generate code that is at least as good as
- 	 move_by_pieces.  However, movmemsi effectively uses a by-pieces
-@@ -7219,13 +7224,12 @@
- 	return size < UNITS_PER_WORD;
-       return size <= MIPS_MAX_MOVE_BYTES_STRAIGHT;
-     }
--  /* The default value.  If this becomes a target hook, we should
--     call the default definition instead.  */
--  return (move_by_pieces_ninsns (size, align, MOVE_MAX_PIECES + 1)
--	  < (unsigned int) MOVE_RATIO (optimize_insn_for_speed_p ()));
-+
-+  return default_use_by_pieces_infrastructure_p (size, align, op, speed_p);
- }
- 
--/* Implement STORE_BY_PIECES_P.  */
-+/* Implement a handler for STORE_BY_PIECES operations
-+   for TARGET_USE_MOVE_BY_PIECES_INFRASTRUCTURE_P.  */
- 
- bool
- mips_store_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
-@@ -19134,6 +19138,10 @@
- #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
- #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV mips_atomic_assign_expand_fenv
- 
-+#undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
-+#define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
-+  mips_use_by_pieces_infrastructure_p
-+
- struct gcc_target targetm = TARGET_INITIALIZER;
- 
- #include "gt-mips.h"
---- a/src/gcc/config/mips/mips.h
-+++ b/src/gcc/config/mips/mips.h
-@@ -2867,9 +2867,6 @@
-    ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX		\
-    : MIPS_CALL_RATIO / 2)
- 
--#define MOVE_BY_PIECES_P(SIZE, ALIGN) \
--  mips_move_by_pieces_p (SIZE, ALIGN)
--
- /* For CLEAR_RATIO, when optimizing for size, give a better estimate
-    of the length of a memset call, but use the default otherwise.  */
- 
-@@ -2882,9 +2879,6 @@
- 
- #define SET_RATIO(speed) \
-   ((speed) ? 15 : MIPS_CALL_RATIO - 2)
--
--#define STORE_BY_PIECES_P(SIZE, ALIGN) \
--  mips_store_by_pieces_p (SIZE, ALIGN)
- 
- /* Since the bits of the _init and _fini function is spread across
-    many object files, each potentially with its own GP, we must assume
---- a/src/gcc/params.def
-+++ b/src/gcc/params.def
-@@ -303,7 +303,7 @@
- DEFPARAM(PARAM_MAX_COMPLETELY_PEELED_INSNS,
- 	"max-completely-peeled-insns",
- 	"The maximum number of insns of a completely peeled loop",
--	100, 0, 0)
-+	200, 0, 0)
- /* The maximum number of peelings of a single loop that is peeled completely.  */
- DEFPARAM(PARAM_MAX_COMPLETELY_PEEL_TIMES,
- 	"max-completely-peel-times",
-@@ -1095,6 +1095,21 @@
- 	  "Maximum number of nested calls to search for control dependencies "
- 	  "during uninitialized variable analysis",
- 	  1000, 1, 0)
-+
-+DEFPARAM (PARAM_MAX_FSM_THREAD_PATH_INSNS,
-+	  "max-fsm-thread-path-insns",
-+	  "Maximum number of instructions to copy when duplicating blocks on a finite state automaton jump thread path",
-+	  100, 1, 999999)
-+
-+DEFPARAM (PARAM_MAX_FSM_THREAD_LENGTH,
-+	  "max-fsm-thread-length",
-+	  "Maximum number of basic blocks on a finite state automaton jump thread path",
-+	  10, 1, 999999)
-+
-+DEFPARAM (PARAM_MAX_FSM_THREAD_PATHS,
-+	  "max-fsm-thread-paths",
-+	  "Maximum number of new jump thread paths to create for a finite state automaton",
-+	  50, 1, 999999)
- /*
- 
- Local variables:
---- a/src/gcc/tree-ssa-threadedge.c
-+++ b/src/gcc/tree-ssa-threadedge.c
-@@ -617,6 +617,7 @@
-      rather than use a relational operator.  These are simpler to handle.  */
-   if (TREE_CODE (cond) == SSA_NAME)
-     {
-+      tree original_lhs = cond;
-       cached_lhs = cond;
- 
-       /* Get the variable's current value from the equivalence chains.
-@@ -638,6 +639,12 @@
- 	 pass specific callback to try and simplify it further.  */
-       if (cached_lhs && ! is_gimple_min_invariant (cached_lhs))
-         cached_lhs = (*simplify) (stmt, stmt);
-+
-+      /* We couldn't find an invariant.  But, callers of this
-+	 function may be able to do something useful with the
-+	 unmodified destination.  */
-+      if (!cached_lhs)
-+	cached_lhs = original_lhs;
-     }
-   else
-     cached_lhs = NULL;
-@@ -897,6 +904,248 @@
-   return false;
- }
- 
-+/* Return true if the CFG contains at least one path from START_BB to END_BB.
-+   When a path is found, record in PATH the blocks from END_BB to START_BB.
-+   VISITED_BBS is used to make sure we don't fall into an infinite loop.  Bound
-+   the recursion to basic blocks belonging to LOOP.  */
-+
-+static bool
-+fsm_find_thread_path (basic_block start_bb, basic_block end_bb,
-+		      vec<basic_block, va_gc> *&path,
-+		      pointer_set_t *visited_bbs, loop_p loop)
-+{
-+  if (loop != start_bb->loop_father)
-+    return false;
-+
-+  if (start_bb == end_bb)
-+    {
-+      vec_safe_push (path, start_bb);
-+      return true;
-+    }
-+
-+  if (!pointer_set_insert (visited_bbs, start_bb))
-+    {
-+      edge e;
-+      edge_iterator ei;
-+      FOR_EACH_EDGE (e, ei, start_bb->succs)
-+	if (fsm_find_thread_path (e->dest, end_bb, path, visited_bbs, loop))
-+	  {
-+	    vec_safe_push (path, start_bb);
-+	    return true;
-+	  }
-+    }
-+
-+  return false;
-+}
-+
-+static int max_threaded_paths;
-+
-+/* We trace the value of the variable EXPR back through any phi nodes looking
-+   for places where it gets a constant value and save the path.  Stop after
-+   having recorded MAX_PATHS jump threading paths.  */
-+
-+static void
-+fsm_find_control_statement_thread_paths (tree expr,
-+					 pointer_set_t *visited_phis,
-+					 vec<basic_block, va_gc> *&path)
-+{
-+  tree var = SSA_NAME_VAR (expr);
-+  gimple def_stmt = SSA_NAME_DEF_STMT (expr);
-+  basic_block var_bb = gimple_bb (def_stmt);
-+
-+  if (var == NULL || var_bb == NULL)
-+    return;
-+
-+  /* For the moment we assume that an SSA chain only contains phi nodes, and
-+     eventually one of the phi arguments will be an integer constant.  In the
-+     future, this could be extended to also handle simple assignments of
-+     arithmetic operations.  */
-+  if (gimple_code (def_stmt) != GIMPLE_PHI)
-+    return;
-+
-+  /* Avoid infinite recursion.  */
-+  if (pointer_set_insert (visited_phis, def_stmt))
-+    return;
-+
-+  int next_path_length = 0;
-+  basic_block last_bb_in_path = path->last ();
-+
-+  /* Following the chain of SSA_NAME definitions, we jumped from a definition in
-+     LAST_BB_IN_PATH to a definition in VAR_BB.  When these basic blocks are
-+     different, append to PATH the blocks from LAST_BB_IN_PATH to VAR_BB.  */
-+  if (var_bb != last_bb_in_path)
-+    {
-+      edge e;
-+      int e_count = 0;
-+      edge_iterator ei;
-+      vec<basic_block, va_gc> *next_path;
-+      vec_alloc (next_path, n_basic_blocks_for_fn (cfun));
-+
-+      FOR_EACH_EDGE (e, ei, last_bb_in_path->preds)
-+	{
-+	  pointer_set_t *visited_bbs = pointer_set_create ();
-+
-+	  if (fsm_find_thread_path (var_bb, e->src, next_path, visited_bbs,
-+				    e->src->loop_father))
-+	    ++e_count;
-+
-+	  pointer_set_destroy (visited_bbs);
-+
-+	  /* If there is more than one path, stop.  */
-+	  if (e_count > 1)
-+	    {
-+	      vec_free (next_path);
-+	      return;
-+	    }
-+	}
-+
-+      /* Stop if we have not found a path: this could occur when the recursion
-+	 is stopped by one of the bounds.  */
-+      if (e_count == 0)
-+	{
-+	  vec_free (next_path);
-+	  return;
-+	}
-+
-+      /* Append all the nodes from NEXT_PATH to PATH.  */
-+      vec_safe_splice (path, next_path);
-+      next_path_length = next_path->length ();
-+      vec_free (next_path);
-+    }
-+
-+  gcc_assert (path->last () == var_bb);
-+
-+  /* Iterate over the arguments of PHI.  */
-+  unsigned int i;
-+  for (i = 0; i < gimple_phi_num_args (def_stmt); i++)
-+    {
-+      tree arg = gimple_phi_arg_def (def_stmt, i);
-+      basic_block bbi = gimple_phi_arg_edge (def_stmt, i)->src;
-+
-+      /* Skip edges pointing outside the current loop.  */
-+      if (!arg || var_bb->loop_father != bbi->loop_father)
-+	continue;
-+
-+      if (TREE_CODE (arg) == SSA_NAME)
-+	{
-+	  vec_safe_push (path, bbi);
-+	  /* Recursively follow SSA_NAMEs looking for a constant definition.  */
-+	  fsm_find_control_statement_thread_paths (arg, visited_phis, path);
-+	  path->pop ();
-+	  continue;
-+	}
-+
-+      if (TREE_CODE (arg) != INTEGER_CST)
-+	continue;
-+
-+      int path_length = path->length ();
-+      /* A path with less than 2 basic blocks should not be jump-threaded.  */
-+      if (path_length < 2)
-+	continue;
-+
-+      if (path_length > PARAM_VALUE (PARAM_MAX_FSM_THREAD_LENGTH))
-+	{
-+	  if (dump_file && (dump_flags & TDF_DETAILS))
-+	    fprintf (dump_file, "FSM jump-thread path not considered: "
-+		     "the number of basic blocks on the path "
-+		     "exceeds PARAM_MAX_FSM_THREAD_LENGTH.\n");
-+	  continue;
-+	}
-+
-+      if (max_threaded_paths <= 0)
-+	{
-+	  if (dump_file && (dump_flags & TDF_DETAILS))
-+	    fprintf (dump_file, "FSM jump-thread path not considered: "
-+		     "the number of previously recorded FSM paths to thread "
-+		     "exceeds PARAM_MAX_FSM_THREAD_PATHS.\n");
-+	  continue;
-+	}
-+
-+      /* Add BBI to the path.  */
-+      vec_safe_push (path, bbi);
-+      ++path_length;
-+
-+      int n_insns = 0;
-+      gimple_stmt_iterator gsi;
-+      int j;
-+      loop_p loop = (*path)[0]->loop_father;
-+      bool path_crosses_loops = false;
-+
-+      /* Count the number of instructions on the path: as these instructions
-+	 will have to be duplicated, we will not record the path if there are
-+	 too many instructions on the path.  Also check that all the blocks in
-+	 the path belong to a single loop.  */
-+      for (j = 1; j < path_length - 1; j++)
-+	{
-+	  basic_block bb = (*path)[j];
-+
-+	  if (bb->loop_father != loop)
-+	    {
-+	      path_crosses_loops = true;
-+	      break;
-+	    }
-+
-+	  for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
-+	    {
-+	      gimple stmt = gsi_stmt (gsi);
-+	      /* Do not count empty statements and labels.  */
-+	      if (gimple_code (stmt) != GIMPLE_NOP
-+		  && gimple_code (stmt) != GIMPLE_LABEL
-+		  && !is_gimple_debug (stmt))
-+		++n_insns;
-+	    }
-+	}
-+
-+      if (path_crosses_loops)
-+	{
-+	  if (dump_file && (dump_flags & TDF_DETAILS))
-+	    fprintf (dump_file, "FSM jump-thread path not considered: "
-+		     "the path crosses loops.\n");
-+	  path->pop ();
-+	  continue;
-+	}
-+
-+      if (n_insns >= PARAM_VALUE (PARAM_MAX_FSM_THREAD_PATH_INSNS))
-+	{
-+	  if (dump_file && (dump_flags & TDF_DETAILS))
-+	    fprintf (dump_file, "FSM jump-thread path not considered: "
-+		     "the number of instructions on the path "
-+		     "exceeds PARAM_MAX_FSM_THREAD_PATH_INSNS.\n");
-+	  path->pop ();
-+	  continue;
-+	}
-+
-+      vec<jump_thread_edge *> *jump_thread_path
-+	= new vec<jump_thread_edge *> ();
-+
-+      /* Record the edges between the blocks in PATH.  */
-+      for (j = 0; j < path_length - 1; j++)
-+	{
-+	  edge e = find_edge ((*path)[path_length - j - 1],
-+			      (*path)[path_length - j - 2]);
-+	  gcc_assert (e);
-+	  jump_thread_edge *x = new jump_thread_edge (e, EDGE_FSM_THREAD);
-+	  jump_thread_path->safe_push (x);
-+	}
-+
-+      /* Add the edge taken when the control variable has value ARG.  */
-+      edge taken_edge = find_taken_edge ((*path)[0], arg);
-+      jump_thread_edge *x
-+	= new jump_thread_edge (taken_edge, EDGE_NO_COPY_SRC_BLOCK);
-+      jump_thread_path->safe_push (x);
-+
-+      register_jump_thread (jump_thread_path);
-+      --max_threaded_paths;
-+
-+      /* Remove BBI from the path.  */
-+      path->pop ();
-+    }
-+
-+  /* Remove all the nodes that we added from NEXT_PATH.  */
-+  if (next_path_length)
-+    vec_safe_truncate (path, (path->length () - next_path_length));
-+}
-+
- /* We are exiting E->src, see if E->dest ends with a conditional
-    jump which has a known value when reached via E.
- 
-@@ -982,7 +1231,10 @@
-       cond = simplify_control_stmt_condition (e, stmt, dummy_cond, simplify,
- 					      handle_dominating_asserts);
- 
--      if (cond && is_gimple_min_invariant (cond))
-+      if (!cond)
-+	return 0;
-+
-+      if (is_gimple_min_invariant (cond))
- 	{
- 	  edge taken_edge = find_taken_edge (e->dest, cond);
- 	  basic_block dest = (taken_edge ? taken_edge->dest : NULL);
-@@ -1028,6 +1280,27 @@
- 				      backedge_seen_p);
- 	  return 1;
- 	}
-+
-+      if (!flag_expensive_optimizations
-+	  || optimize_function_for_size_p (cfun)
-+	  || TREE_CODE (cond) != SSA_NAME
-+	  || e->dest->loop_father != e->src->loop_father
-+	  || loop_depth (e->dest->loop_father) == 0)
-+	return 0;
-+
-+      /* When COND cannot be simplified, try to find paths from a control
-+	 statement back through the PHI nodes which would affect that control
-+	 statement.  */
-+      vec<basic_block, va_gc> *bb_path;
-+      vec_alloc (bb_path, n_basic_blocks_for_fn (cfun));
-+      vec_safe_push (bb_path, e->dest);
-+      pointer_set_t *visited_phis = pointer_set_create ();
-+
-+      max_threaded_paths = PARAM_VALUE (PARAM_MAX_FSM_THREAD_PATHS);
-+      fsm_find_control_statement_thread_paths (cond, visited_phis, bb_path);
-+
-+      pointer_set_destroy (visited_phis);
-+      vec_free (bb_path);
-     }
-   return 0;
- }
---- a/src/gcc/convert.c
-+++ b/src/gcc/convert.c
-@@ -471,8 +471,8 @@
- 	  break;
- 
- 	CASE_FLT_FN (BUILT_IN_ROUND):
--	  /* Only convert in ISO C99 mode.  */
--	  if (!targetm.libc_has_function (function_c99_misc))
-+	  /* Only convert in ISO C99 mode and with -fno-math-errno.  */
-+	  if (!targetm.libc_has_function (function_c99_misc) || flag_errno_math)
- 	    break;
- 	  if (outprec < TYPE_PRECISION (integer_type_node)
- 	      || (outprec == TYPE_PRECISION (integer_type_node)
-@@ -492,8 +492,8 @@
- 	    break;
- 	  /* ... Fall through ...  */
- 	CASE_FLT_FN (BUILT_IN_RINT):
--	  /* Only convert in ISO C99 mode.  */
--	  if (!targetm.libc_has_function (function_c99_misc))
-+	  /* Only convert in ISO C99 mode and with -fno-math-errno.  */
-+	  if (!targetm.libc_has_function (function_c99_misc) || flag_errno_math)
- 	    break;
- 	  if (outprec < TYPE_PRECISION (integer_type_node)
- 	      || (outprec == TYPE_PRECISION (integer_type_node)
---- a/src/libobjc/ChangeLog.linaro
-+++ b/src/libobjc/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/libvtv/ChangeLog.linaro
-+++ b/src/libvtv/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/libgfortran/configure
-+++ b/src/libgfortran/configure
-@@ -25941,7 +25941,7 @@
- # test is copied from libgomp, and modified to not link in -lrt as
- # libgfortran calls clock_gettime via a weak reference if it's found
- # in librt.
--if test $ac_cv_func_clock_gettime = no; then
-+if test "$ac_cv_func_clock_gettime" = no; then
-   { $as_echo "$as_me:${as_lineno-$LINENO}: checking for clock_gettime in -lrt" >&5
- $as_echo_n "checking for clock_gettime in -lrt... " >&6; }
- if test "${ac_cv_lib_rt_clock_gettime+set}" = set; then :
---- a/src/libgfortran/configure.ac
-+++ b/src/libgfortran/configure.ac
-@@ -511,7 +511,7 @@
- # test is copied from libgomp, and modified to not link in -lrt as
- # libgfortran calls clock_gettime via a weak reference if it's found
- # in librt.
--if test $ac_cv_func_clock_gettime = no; then
-+if test "$ac_cv_func_clock_gettime" = no; then
-   AC_CHECK_LIB(rt, clock_gettime,
-     [AC_DEFINE(HAVE_CLOCK_GETTIME_LIBRT, 1,
-                [Define to 1 if you have the `clock_gettime' function in librt.])])
---- a/src/libgfortran/ChangeLog.linaro
-+++ b/src/libgfortran/ChangeLog.linaro
-@@ -0,0 +1,59 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	Backport from trunk r209747.
-+	2014-04-24  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* configure.ac: Quote usage of ac_cv_func_clock_gettime in if test.
-+	* configure: Regenerate.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/libada/ChangeLog.linaro
-+++ b/src/libada/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/libffi/ChangeLog.linaro
-+++ b/src/libffi/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/libssp/ChangeLog.linaro
-+++ b/src/libssp/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/libcilkrts/ChangeLog.linaro
-+++ b/src/libcilkrts/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/libcpp/ChangeLog.linaro
-+++ b/src/libcpp/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/libcpp/po/ChangeLog.linaro
-+++ b/src/libcpp/po/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
---- a/src/fixincludes/ChangeLog.linaro
-+++ b/src/fixincludes/ChangeLog.linaro
-@@ -0,0 +1,51 @@
-+2015-01-15  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2015.01 released.
-+
-+2014-12-11  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.12 released.
-+
-+2014-11-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.11 released.
-+
-+2014-10-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10-1 released.
-+
-+2014-10-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.10 released.
-+
-+2014-09-10  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.09 released.
-+
-+2014-08-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.08 released.
-+
-+2014-07-24  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07-1 released.
-+
-+2014-07-17  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.07 released.
-+
-+2014-06-25  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06-1 released.
-+
-+2014-06-12  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.06 released.
-+
-+2014-05-14  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.05 released.
-+
-+2014-04-22  Yvan Roux  <yvan.roux@linaro.org>
-+
-+	GCC Linaro 4.9-2014.04 released.
diff --git a/debian/patches/gcc-multiarch-trunk.diff b/debian/patches/gcc-multiarch-trunk.diff
deleted file mode 100644
index 967bcdf..0000000
--- a/debian/patches/gcc-multiarch-trunk.diff
+++ /dev/null
@@ -1,149 +0,0 @@
-# DP: - Remaining multiarch patches, not yet submitted upstream.
-# DP: - Add MULTIARCH_DIRNAME definitions for multilib configurations,
-# DP:   which are used for the non-multilib builds.
-
-2013-06-12  Matthias Klose  <doko@ubuntu.com>
-
-	* config/i386/t-linux64: Set MULTIARCH_DIRNAME.
-	* config/i386/t-kfreebsd: Set MULTIARCH_DIRNAME.
-	* config.gcc (i[34567]86-*-linux* | x86_64-*-linux*): Prepend
-	i386/t-linux to $tmake_file.
-	* config/mips/t-linux64: Set MULTIARCH_DIRNAME.
-	* config/rs6000/t-linux64: Set MULTIARCH_DIRNAME.
-	* config/s390/t-linux64: Set MULTIARCH_DIRNAME.
-	* config/sparc/t-linux64: Set MULTIARCH_DIRNAME.
-
-Index: b/src/gcc/config/sh/t-linux
-===================================================================
---- a/src/gcc/config/sh/t-linux
-+++ b/src/gcc/config/sh/t-linux
-@@ -1,2 +1,4 @@
- MULTILIB_DIRNAMES= 
- MULTILIB_MATCHES = 
-+
-+MULTILIB_OSDIRNAMES = sh4-linux-gnu:sh4-linux-gnu sh4_nofpu-linux-gnu:sh4-linux-gnu
-Index: b/src/gcc/config/sparc/t-linux64
-===================================================================
---- a/src/gcc/config/sparc/t-linux64
-+++ b/src/gcc/config/sparc/t-linux64
-@@ -27,3 +27,5 @@ MULTILIB_OPTIONS = m64/m32
- MULTILIB_DIRNAMES = 64 32
- MULTILIB_OSDIRNAMES = ../lib64$(call if_multiarch,:sparc64-linux-gnu)
- MULTILIB_OSDIRNAMES += $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:sparc-linux-gnu)
-+
-+MULTIARCH_DIRNAME = $(call if_multiarch,sparc$(if $(findstring 64,$(target)),64)-linux-gnu)
-Index: b/src/gcc/config/s390/t-linux64
-===================================================================
---- a/src/gcc/config/s390/t-linux64
-+++ b/src/gcc/config/s390/t-linux64
-@@ -9,3 +9,5 @@ MULTILIB_OPTIONS = m64/m31
- MULTILIB_DIRNAMES = 64 32
- MULTILIB_OSDIRNAMES = ../lib64$(call if_multiarch,:s390x-linux-gnu)
- MULTILIB_OSDIRNAMES += $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:s390-linux-gnu)
-+
-+MULTIARCH_DIRNAME = $(call if_multiarch,s390$(if $(findstring s390x,$(target)),x)-linux-gnu)
-Index: b/src/gcc/config/rs6000/t-linux64
-===================================================================
---- a/src/gcc/config/rs6000/t-linux64
-+++ b/src/gcc/config/rs6000/t-linux64
-@@ -31,6 +31,8 @@ MULTILIB_EXTRA_OPTS :=
- MULTILIB_OSDIRNAMES := m64=../lib64$(call if_multiarch,:powerpc64-linux-gnu)
- MULTILIB_OSDIRNAMES += m32=$(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:powerpc-linux-gnu)
- 
-+MULTIARCH_DIRNAME = $(call if_multiarch,powerpc$(if $(findstring 64,$(target)),64)-linux-gnu)
-+
- rs6000-linux.o: $(srcdir)/config/rs6000/rs6000-linux.c
- 	$(COMPILE) $<
- 	$(POSTCOMPILE)
-Index: b/src/gcc/config/i386/t-linux64
-===================================================================
---- a/src/gcc/config/i386/t-linux64
-+++ b/src/gcc/config/i386/t-linux64
-@@ -36,3 +36,13 @@ MULTILIB_DIRNAMES   = $(patsubst m%, %,
- MULTILIB_OSDIRNAMES = m64=../lib64$(call if_multiarch,:x86_64-linux-gnu)
- MULTILIB_OSDIRNAMES+= m32=$(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:i386-linux-gnu)
- MULTILIB_OSDIRNAMES+= mx32=../libx32$(call if_multiarch,:x86_64-linux-gnux32)
-+
-+ifneq (,$(findstring x86_64,$(target)))
-+  ifneq (,$(findstring biarchx32.h,$(tm_include_list)))
-+  MULTIARCH_DIRNAME = $(call if_multiarch,x86_64-linux-gnux32)
-+  else
-+  MULTIARCH_DIRNAME = $(call if_multiarch,x86_64-linux-gnu)
-+  endif
-+else
-+  MULTIARCH_DIRNAME = $(call if_multiarch,i386-linux-gnu)
-+endif
-Index: b/src/gcc/config/i386/t-kfreebsd
-===================================================================
---- a/src/gcc/config/i386/t-kfreebsd
-+++ b/src/gcc/config/i386/t-kfreebsd
-@@ -1,5 +1,9 @@
--MULTIARCH_DIRNAME = $(call if_multiarch,i386-kfreebsd-gnu)
-+ifeq (,$(MULTIARCH_DIRNAME))
-+  MULTIARCH_DIRNAME = $(call if_multiarch,i386-kfreebsd-gnu)
-+endif
- 
- # MULTILIB_OSDIRNAMES are set in t-linux64.
- KFREEBSD_OS = $(filter kfreebsd%, $(word 3, $(subst -, ,$(target))))
- MULTILIB_OSDIRNAMES := $(filter-out mx32=%,$(subst linux,$(KFREEBSD_OS),$(MULTILIB_OSDIRNAMES)))
-+
-+MULTIARCH_DIRNAME := $(subst linux,$(KFREEBSD_OS),$(MULTIARCH_DIRNAME))
-Index: b/src/gcc/config/mips/t-linux64
-===================================================================
---- a/src/gcc/config/mips/t-linux64
-+++ b/src/gcc/config/mips/t-linux64
-@@ -24,3 +24,13 @@ MULTILIB_OSDIRNAMES = \
- 	../lib32$(call if_multiarch,:mips64$(MIPS_EL)-linux-gnuabin32$(MIPS_SOFT)) \
- 	../lib$(call if_multiarch,:mips$(MIPS_EL)-linux-gnu$(MIPS_SOFT)) \
- 	../lib64$(call if_multiarch,:mips64$(MIPS_EL)-linux-gnuabi64$(MIPS_SOFT))
-+
-+ifneq (,$(findstring abin32,$(target)))
-+MULTIARCH_DIRNAME = $(call if_multiarch,mips64$(MIPS_EL)-linux-gnuabin32$(MIPS_SOFT))
-+else
-+ifneq (,$(findstring abi64,$(target)))
-+MULTIARCH_DIRNAME = $(call if_multiarch,mips64$(MIPS_EL)-linux-gnuabi64$(MIPS_SOFT))
-+else
-+MULTIARCH_DIRNAME = $(call if_multiarch,mips$(MIPS_EL)-linux-gnu$(MIPS_SOFT))
-+endif
-+endif
-Index: b/src/gcc/config.gcc
-===================================================================
---- a/src/gcc/config.gcc
-+++ b/src/gcc/config.gcc
-@@ -1942,8 +1942,11 @@ mips64*-*-linux* | mipsisa64*-*-linux*)
- 	tm_file="dbxelf.h elfos.h gnu-user.h linux.h linux-android.h glibc-stdint.h ${tm_file} mips/gnu-user.h mips/gnu-user64.h mips/linux64.h mips/linux-common.h"
- 	extra_options="${extra_options} linux-android.opt"
- 	tmake_file="${tmake_file} mips/t-linux64"
--	tm_defines="${tm_defines} MIPS_ABI_DEFAULT=ABI_N32"
-+	tm_defines="${tm_defines} MIPS_ABI_DEFAULT=ABI_64"
- 	case ${target} in
-+		*gnuabin32*)
-+			tm_defines=$(echo ${tm_defines}| sed 's/MIPS_ABI_DEFAULT=ABI_64/MIPS_ABI_DEFAULT=ABI_N32/g')
-+			;;
- 		mips64el-st-linux-gnu)
- 			tm_file="${tm_file} mips/st.h"
- 			tmake_file="${tmake_file} mips/t-st"
-@@ -4085,7 +4088,7 @@ case ${target} in
- 	i[34567]86-*-darwin* | x86_64-*-darwin*)
- 		;;
- 	i[34567]86-*-linux* | x86_64-*-linux*)
--		tmake_file="$tmake_file i386/t-linux"
-+		tmake_file="i386/t-linux $tmake_file"
- 		;;
- 	i[34567]86-*-kfreebsd*-gnu | x86_64-*-kfreebsd*-gnu)
- 		tmake_file="$tmake_file i386/t-kfreebsd"
-Index: b/src/gcc/config/aarch64/t-aarch64-linux
-===================================================================
---- a/src/gcc/config/aarch64/t-aarch64-linux
-+++ b/src/gcc/config/aarch64/t-aarch64-linux
-@@ -22,7 +22,7 @@ LIB1ASMSRC   = aarch64/lib1funcs.asm
- LIB1ASMFUNCS = _aarch64_sync_cache_range
- 
- AARCH_BE = $(if $(findstring TARGET_BIG_ENDIAN_DEFAULT=1, $(tm_defines)),_be)
--MULTILIB_OSDIRNAMES = mabi.lp64=../lib64$(call if_multiarch,:aarch64$(AARCH_BE)-linux-gnu)
--MULTIARCH_DIRNAME = $(call if_multiarch,aarch64$(AARCH_BE)-linux-gnu)
-+MULTILIB_OSDIRNAMES = mabi.lp64=../lib$(call if_multiarch,:aarch64$(AARCH_BE)-linux-gnu)
-+MULTILIB_OSDIRNAMES += mabi.ilp32=../libilp32$(call if_multiarch,:aarch64$(AARCH_BE)_ilp32-linux-gnu)
- 
--MULTILIB_OSDIRNAMES += mabi.ilp32=../libilp32
-+MULTIARCH_DIRNAME = $(call if_multiarch,aarch64$(AARCH_BE)-linux-gnu)
diff --git a/debian/patches/gcc-multiarch.diff b/debian/patches/gcc-multiarch.diff
index 045be56..5f2a4ef 100644
--- a/debian/patches/gcc-multiarch.diff
+++ b/debian/patches/gcc-multiarch.diff
@@ -110,20 +110,7 @@ Index: b/src/gcc/config.gcc
 ===================================================================
 --- a/src/gcc/config.gcc
 +++ b/src/gcc/config.gcc
-@@ -1961,8 +1961,11 @@ mips64*-*-linux* | mipsisa64*-*-linux*)
- 	tm_file="dbxelf.h elfos.h gnu-user.h linux.h linux-android.h glibc-stdint.h ${tm_file} mips/gnu-user.h mips/gnu-user64.h mips/linux64.h mips/linux-common.h"
- 	extra_options="${extra_options} linux-android.opt"
- 	tmake_file="${tmake_file} mips/t-linux64"
--	tm_defines="${tm_defines} MIPS_ABI_DEFAULT=ABI_N32"
-+	tm_defines="${tm_defines} MIPS_ABI_DEFAULT=ABI_64"
- 	case ${target} in
-+		*gnuabin32*)
-+			tm_defines=$(echo ${tm_defines}| sed 's/MIPS_ABI_DEFAULT=ABI_64/MIPS_ABI_DEFAULT=ABI_N32/g')
-+			;;
- 		mips64el-st-linux-gnu)
- 			tm_file="${tm_file} mips/st.h"
- 			tmake_file="${tmake_file} mips/t-st"
-@@ -4105,7 +4108,7 @@ case ${target} in
+@@ -4220,7 +4220,7 @@ case ${target} in
  	i[34567]86-*-darwin* | x86_64-*-darwin*)
  		;;
  	i[34567]86-*-linux* | x86_64-*-linux*)
@@ -140,8 +127,10 @@ Index: b/src/gcc/config/aarch64/t-aarch64-linux
  LIB1ASMFUNCS = _aarch64_sync_cache_range
  
  AARCH_BE = $(if $(findstring TARGET_BIG_ENDIAN_DEFAULT=1, $(tm_defines)),_be)
--MULTILIB_OSDIRNAMES = .=../lib64$(call if_multiarch,:aarch64$(AARCH_BE)-linux-gnu)
-+MULTILIB_OSDIRNAMES = .=../lib$(call if_multiarch,:aarch64$(AARCH_BE)-linux-gnu)
- MULTIARCH_DIRNAME = $(call if_multiarch,aarch64$(AARCH_BE)-linux-gnu)
+-MULTILIB_OSDIRNAMES = mabi.lp64=../lib64$(call if_multiarch,:aarch64$(AARCH_BE)-linux-gnu)
+-MULTIARCH_DIRNAME = $(call if_multiarch,aarch64$(AARCH_BE)-linux-gnu)
++MULTILIB_OSDIRNAMES = mabi.lp64=../lib$(call if_multiarch,:aarch64$(AARCH_BE)-linux-gnu)
++MULTILIB_OSDIRNAMES += mabi.ilp32=../libilp32$(call if_multiarch,:aarch64$(AARCH_BE)_ilp32-linux-gnu)
  
- # Disable the multilib for linux-gnu targets for the time being; focus
+-MULTILIB_OSDIRNAMES += mabi.ilp32=../libilp32
++MULTIARCH_DIRNAME = $(call if_multiarch,aarch64$(AARCH_BE)-linux-gnu)
diff --git a/debian/patches/gcc-setmultilib-fix.diff b/debian/patches/gcc-setmultilib-fix.diff
deleted file mode 100644
index 8ec1e79..0000000
--- a/debian/patches/gcc-setmultilib-fix.diff
+++ /dev/null
@@ -1,24 +0,0 @@
-Index: b/src/gcc/gcc.c
-===================================================================
---- a/src/gcc/gcc.c
-+++ b/src/gcc/gcc.c
-@@ -7790,10 +7790,15 @@ set_multilib_dir (void)
- 		q2++;
- 	      if (*q2 == ':')
- 		ml_end = q2;
--	      new_multilib_os_dir = XNEWVEC (char, ml_end - q);
--	      memcpy (new_multilib_os_dir, q + 1, ml_end - q - 1);
--	      new_multilib_os_dir[ml_end - q - 1] = '\0';
--	      multilib_os_dir = *new_multilib_os_dir ? new_multilib_os_dir : ".";
-+	      if (ml_end - q == 1)
-+		multilib_os_dir = xstrdup (".");
-+	      else
-+		{
-+		  new_multilib_os_dir = XNEWVEC (char, ml_end - q);
-+		  memcpy (new_multilib_os_dir, q + 1, ml_end - q - 1);
-+		  new_multilib_os_dir[ml_end - q - 1] = '\0';
-+		  multilib_os_dir = new_multilib_os_dir;
-+		}
- 
- 	      if (q2 < end && *q2 == ':')
- 		{
diff --git a/debian/patches/gcc-sysroot.diff b/debian/patches/gcc-sysroot.diff
index da42d8e..e312dd6 100644
--- a/debian/patches/gcc-sysroot.diff
+++ b/debian/patches/gcc-sysroot.diff
@@ -4,7 +4,7 @@ Index: b/src/gcc/configure.ac
 ===================================================================
 --- a/src/gcc/configure.ac
 +++ b/src/gcc/configure.ac
-@@ -117,6 +117,69 @@
+@@ -121,6 +121,69 @@ if test x$local_prefix = x; then
  	local_prefix=/usr/local
  fi
  
@@ -74,7 +74,7 @@ Index: b/src/gcc/configure.ac
  # Don't set gcc_gxx_include_dir to gxx_include_dir since that's only
  # passed in by the toplevel make and thus we'd get different behavior
  # depending on where we built the sources.
-@@ -148,7 +211,9 @@
+@@ -152,7 +215,9 @@ gcc_gxx_include_dir_add_sysroot=0
  if test "${with_sysroot+set}" = set; then
    gcc_gxx_without_sysroot=`expr "${gcc_gxx_include_dir}" : "${with_sysroot}"'\(.*\)'`
    if test "${gcc_gxx_without_sysroot}"; then
@@ -85,7 +85,7 @@ Index: b/src/gcc/configure.ac
      gcc_gxx_include_dir_add_sysroot=1
    fi
  fi
-@@ -738,69 +803,6 @@
+@@ -791,69 +856,6 @@ AC_ARG_ENABLE(shared,
  ], [enable_shared=yes])
  AC_SUBST(enable_shared)
  
diff --git a/debian/patches/gcc-target-include-asm.diff b/debian/patches/gcc-target-include-asm.diff
index 5b67c7a..495faaf 100644
--- a/debian/patches/gcc-target-include-asm.diff
+++ b/debian/patches/gcc-target-include-asm.diff
@@ -4,7 +4,7 @@ Index: b/src/configure.ac
 ===================================================================
 --- a/src/configure.ac
 +++ b/src/configure.ac
-@@ -3039,7 +3039,7 @@ fi
+@@ -3152,7 +3152,7 @@ fi
  # being built; programs in there won't even run.
  if test "${build}" = "${host}" && test -d ${srcdir}/gcc; then
    # Search for pre-installed headers if nothing else fits.
diff --git a/debian/patches/gcc-textdomain.diff b/debian/patches/gcc-textdomain.diff
index 54de5bf..e647a6e 100644
--- a/debian/patches/gcc-textdomain.diff
+++ b/debian/patches/gcc-textdomain.diff
@@ -10,8 +10,8 @@ Index: b/src/gcc/intl.c
  
 -  (void) bindtextdomain ("gcc", LOCALEDIR);
 -  (void) textdomain ("gcc");
-+  (void) bindtextdomain ("gcc-4.9", LOCALEDIR);
-+  (void) textdomain ("gcc-4.9");
++  (void) bindtextdomain ("gcc-5", LOCALEDIR);
++  (void) textdomain ("gcc-5");
  
    /* Opening quotation mark.  */
    open_quote = _("`");
@@ -19,14 +19,14 @@ Index: b/src/gcc/Makefile.in
 ===================================================================
 --- a/src/gcc/Makefile.in
 +++ b/src/gcc/Makefile.in
-@@ -3846,8 +3846,8 @@ install-po:
+@@ -3897,8 +3897,8 @@ install-po:
  	  dir=$(localedir)/$$lang/LC_MESSAGES; \
  	  echo $(mkinstalldirs) $(DESTDIR)$$dir; \
  	  $(mkinstalldirs) $(DESTDIR)$$dir || exit 1; \
 -	  echo $(INSTALL_DATA) $$cat $(DESTDIR)$$dir/gcc.mo; \
 -	  $(INSTALL_DATA) $$cat $(DESTDIR)$$dir/gcc.mo; \
-+	  echo $(INSTALL_DATA) $$cat $(DESTDIR)$$dir/gcc-4.9.mo; \
-+	  $(INSTALL_DATA) $$cat $(DESTDIR)$$dir/gcc-4.9.mo; \
++	  echo $(INSTALL_DATA) $$cat $(DESTDIR)$$dir/gcc-5.mo; \
++	  $(INSTALL_DATA) $$cat $(DESTDIR)$$dir/gcc-5.mo; \
  	done
  
  # Rule for regenerating the message template (gcc.pot).
@@ -34,7 +34,7 @@ Index: b/src/libcpp/init.c
 ===================================================================
 --- a/src/libcpp/init.c
 +++ b/src/libcpp/init.c
-@@ -152,7 +152,7 @@ init_library (void)
+@@ -153,7 +153,7 @@ init_library (void)
        init_trigraph_map ();
  
  #ifdef ENABLE_NLS
@@ -64,7 +64,7 @@ Index: b/src/libcpp/Makefile.in
  LIBICONV = @LIBICONV@
  LIBINTL = @LIBINTL@
  PACKAGE = @PACKAGE@
-+PACKAGE_SUFFIX = -4.9
++PACKAGE_SUFFIX = -5
  RANLIB = @RANLIB@
  SHELL = @SHELL@
  USED_CATALOGS = @USED_CATALOGS@
diff --git a/debian/patches/gccgo-arm64.diff b/debian/patches/gccgo-arm64.diff
index bb8de74..3fe28ed 100644
--- a/debian/patches/gccgo-arm64.diff
+++ b/debian/patches/gccgo-arm64.diff
@@ -9,13 +9,15 @@ Subject: [PATCH 3/3] Enable cgo by default on linux/arm64.
  src/libgo/go/go/build/build.go | 1 +
  1 file changed, 1 insertion(+)
 
+Index: b/src/libgo/go/go/build/build.go
+===================================================================
 --- a/src/libgo/go/go/build/build.go
 +++ b/src/libgo/go/go/build/build.go
 @@ -268,6 +268,7 @@ var cgoEnabled = map[string]bool{
- 	"linux/386":       true,
+ 	"linux/alpha":     true,
  	"linux/amd64":     true,
  	"linux/arm":       true,
 +	"linux/arm64":     true,
- 	"netbsd/386":      true,
- 	"netbsd/amd64":    true,
- 	"netbsd/arm":      true,
+ 	"linux/ppc64":     true,
+ 	"linux/ppc64le":   true,
+ 	"linux/s390":      true,
diff --git a/debian/patches/gccgo-version.diff b/debian/patches/gccgo-version.diff
index 0d92c23..6adcaaf 100644
--- a/debian/patches/gccgo-version.diff
+++ b/debian/patches/gccgo-version.diff
@@ -4,12 +4,12 @@ Index: b/src/gcc/go/Make-lang.in
 ===================================================================
 --- a/src/gcc/go/Make-lang.in
 +++ b/src/gcc/go/Make-lang.in
-@@ -223,7 +223,9 @@ go.stageprofile: stageprofile-start
+@@ -217,7 +217,9 @@ go.stageprofile: stageprofile-start
  go.stagefeedback: stagefeedback-start
  	-mv go/*$(objext) stagefeedback/go
  
 -CFLAGS-go/go-lang.o += -DDEFAULT_TARGET_VERSION=\"$(version)\" \
-+short_version := $(shell echo $(version) | sed -r 's/([0-9]+\.[0-9]+).*/\1/')
++short_version := $(shell echo $(version) | sed -r 's/([0-9]+).*/\1/')
 +
 +CFLAGS-go/go-lang.o += -DDEFAULT_TARGET_VERSION=\"$(short_version)\" \
  	-DDEFAULT_TARGET_MACHINE=\"$(target_noncanonical)\"
@@ -19,12 +19,11 @@ Index: b/src/libgo/Makefile.in
 ===================================================================
 --- a/src/libgo/Makefile.in
 +++ b/src/libgo/Makefile.in
-@@ -429,14 +429,14 @@ top_srcdir = @top_srcdir@
- SUFFIXES = .c .go .gox .o .obj .lo .a
+@@ -448,14 +448,15 @@ SUFFIXES = .c .go .gox .o .obj .lo .a
  @LIBGO_IS_RTEMS_TRUE@subdirs = testsuite
  SUBDIRS = ${subdirs}
--gcc_version := $(shell cat $(top_srcdir)/../gcc/BASE-VER)
-+short_version := $(shell sed -r 's/([0-9]+\.[0-9]+)\..*/\1/' $(top_srcdir)/../gcc/BASE-VER)
+ gcc_version := $(shell $(GOC) -dumpversion)
++short_version := $(shell echo $(gcc_version) | sed -r 's/([0-9]+)\..*/\1/')
  MAINT_CHARSET = latin1
  mkinstalldirs = $(SHELL) $(toplevel_srcdir)/mkinstalldirs
  PWD_COMMAND = $${PWDCMD-pwd}
@@ -32,7 +31,9 @@ Index: b/src/libgo/Makefile.in
  toolexecdir = $(glibgo_toolexecdir)
  toolexeclibdir = $(glibgo_toolexeclibdir)
 -toolexeclibgodir = $(nover_glibgo_toolexeclibdir)/go/$(gcc_version)/$(target_alias)
+-libexecsubdir = $(libexecdir)/gcc/$(target_alias)/$(gcc_version)
 +toolexeclibgodir = $(nover_glibgo_toolexeclibdir)/go/$(short_version)
++libexecsubdir = $(libexecdir)/gcc/$(target_alias)/$(short_version)
  WARN_CFLAGS = $(WARN_FLAGS) $(WERROR)
  
  # -I/-D flags to pass when compiling.
@@ -40,21 +41,49 @@ Index: b/src/libgo/Makefile.am
 ===================================================================
 --- a/src/libgo/Makefile.am
 +++ b/src/libgo/Makefile.am
-@@ -15,7 +15,7 @@ endif
- 
+@@ -16,6 +16,7 @@ endif
  SUBDIRS = ${subdirs}
  
--gcc_version := $(shell cat $(top_srcdir)/../gcc/BASE-VER)
-+short_version := $(shell sed -r 's/([0-9]+\.[0-9]+)\..*/\1/' $(top_srcdir)/../gcc/BASE-VER)
+ gcc_version := $(shell $(GOC) -dumpversion)
++short_version := $(shell echo $(gcc_version) | sed -r 's/([0-9]+)\..*/\1/')
  
  MAINT_CHARSET = latin1
  
-@@ -25,7 +25,7 @@ STAMP = echo timestamp >
+@@ -25,8 +26,8 @@ STAMP = echo timestamp >
  
  toolexecdir = $(glibgo_toolexecdir)
  toolexeclibdir = $(glibgo_toolexeclibdir)
 -toolexeclibgodir = $(nover_glibgo_toolexeclibdir)/go/$(gcc_version)/$(target_alias)
+-libexecsubdir = $(libexecdir)/gcc/$(target_alias)/$(gcc_version)
 +toolexeclibgodir = $(nover_glibgo_toolexeclibdir)/go/$(short_version)
++libexecsubdir = $(libexecdir)/gcc/$(target_alias)/$(short_version)
  
  LIBFFI = @LIBFFI@
  LIBFFIINCS = @LIBFFIINCS@
+# DP: 
+
+--- a/src/gotools/Makefile.am
++++ b/src/gotools/Makefile.am
+@@ -18,8 +18,9 @@
+ ACLOCAL_AMFLAGS = -I ./config -I ../config
+ 
+ gcc_version := $(shell $(GCC_FOR_TARGET) -dumpversion)
++short_version := $(shell echo $(gcc_version) | sed -r 's/([0-9]+)\..*/\1/')
+ 
+-libexecsubdir = $(libexecdir)/gcc/$(target_noncanonical)/$(gcc_version)
++libexecsubdir = $(libexecdir)/gcc/$(target_noncanonical)/$(short_version)
+ 
+ mkinstalldirs = $(SHELL) $(toplevel_srcdir)/mkinstalldirs
+ PWD_COMMAND = $${PWDCMD-pwd}
+--- a/src/gotools/Makefile.in
++++ b/src/gotools/Makefile.in
+@@ -195,7 +195,8 @@
+ top_srcdir = @top_srcdir@
+ ACLOCAL_AMFLAGS = -I ./config -I ../config
+ gcc_version := $(shell $(GCC_FOR_TARGET) -dumpversion)
+-libexecsubdir = $(libexecdir)/gcc/$(target_noncanonical)/$(gcc_version)
++short_version := $(shell echo $(gcc_version) | sed -r 's/([0-9]+)\..*/\1/')
++libexecsubdir = $(libexecdir)/gcc/$(target_noncanonical)/$(short_version)
+ mkinstalldirs = $(SHELL) $(toplevel_srcdir)/mkinstalldirs
+ PWD_COMMAND = $${PWDCMD-pwd}
+ STAMP = echo timestamp >
diff --git a/debian/patches/gdc-4.9-doc.diff b/debian/patches/gdc-5-doc.diff
index baef8d2..baef8d2 100644
--- a/debian/patches/gdc-4.9-doc.diff
+++ b/debian/patches/gdc-5-doc.diff
diff --git a/debian/patches/gdc-4.9.diff b/debian/patches/gdc-5.diff
index 5c5a6f7..5c5a6f7 100644
--- a/debian/patches/gdc-4.9.diff
+++ b/debian/patches/gdc-5.diff
diff --git a/debian/patches/go-testsuite.diff b/debian/patches/go-testsuite.diff
index 9521d5a..9856216 100644
--- a/debian/patches/go-testsuite.diff
+++ b/debian/patches/go-testsuite.diff
@@ -4,7 +4,7 @@ Index: b/src/gcc/testsuite/go.test/go-test.exp
 ===================================================================
 --- a/src/gcc/testsuite/go.test/go-test.exp
 +++ b/src/gcc/testsuite/go.test/go-test.exp
-@@ -388,6 +388,14 @@ proc go-gc-tests { } {
+@@ -398,6 +398,14 @@ proc go-gc-tests { } {
  	    }
  	}
  
diff --git a/debian/patches/go-use-gold.diff b/debian/patches/go-use-gold.diff
index 3430bea..e887221 100644
--- a/debian/patches/go-use-gold.diff
+++ b/debian/patches/go-use-gold.diff
@@ -71,7 +71,7 @@ Index: b/src/gcc/config.in
 ===================================================================
 --- a/src/gcc/config.in
 +++ b/src/gcc/config.in
-@@ -1175,6 +1175,12 @@
+@@ -1259,6 +1259,12 @@
  #endif
  
  
@@ -88,7 +88,7 @@ Index: b/src/gcc/configure.ac
 ===================================================================
 --- a/src/gcc/configure.ac
 +++ b/src/gcc/configure.ac
-@@ -2117,6 +2117,12 @@ if test x$gcc_cv_ld != x; then
+@@ -2225,6 +2225,12 @@ if test x$gcc_cv_ld != x; then
  fi
  AC_MSG_RESULT($ld_is_gold)
  
diff --git a/debian/patches/gotools-dynamic.diff b/debian/patches/gotools-dynamic.diff
new file mode 100644
index 0000000..70bc83c
--- /dev/null
+++ b/debian/patches/gotools-dynamic.diff
@@ -0,0 +1,24 @@
+# DP: Link the gotools dynamically
+
+--- a/src/gotools/Makefile.am
++++ b/src/gotools/Makefile.am
+@@ -38,7 +39,7 @@
+ GOCFLAGS = $(CFLAGS_FOR_TARGET)
+ GOCOMPILE = $(GOCOMPILER) $(GOCFLAGS)
+ 
+-AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs -static-libgo
++AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs
+ GOLINK = $(GOCOMPILER) $(AM_GOCFLAGS) $(LDFLAGS) $(AM_LDFLAGS) -o $@
+ 
+ cmdsrcdir = $(srcdir)/../libgo/go/cmd
+--- a/src/gotools/Makefile.in
++++ b/src/gotools/Makefile.in
+@@ -206,7 +207,7 @@
+ # Use the compiler we just built.
+ @NATIVE_TRUE@GOCOMPILER = $(GOC_FOR_TARGET)
+ GOCOMPILE = $(GOCOMPILER) $(GOCFLAGS)
+-AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs -static-libgo
++AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs
+ GOLINK = $(GOCOMPILER) $(AM_GOCFLAGS) $(LDFLAGS) $(AM_LDFLAGS) -o $@
+ cmdsrcdir = $(srcdir)/../libgo/go/cmd
+ go_cmd_go_files = \
diff --git a/debian/patches/isl-0.13-compat.diff b/debian/patches/isl-0.13-compat.diff
index 52a1739..5e899ee 100644
--- a/debian/patches/isl-0.13-compat.diff
+++ b/debian/patches/isl-0.13-compat.diff
@@ -1,6 +1,8 @@
-diff -Naur gcc-4.9-20140604-old/gcc/graphite-clast-to-gimple.c gcc-4.9-20140604/gcc/graphite-clast-to-gimple.c
---- gcc-4.9-20140604-old/src/gcc/graphite-clast-to-gimple.c	2014-03-03 21:39:22.000000000 +1000
-+++ gcc-4.9-20140604/src/gcc/graphite-clast-to-gimple.c	2014-06-25 15:07:57.958697105 +1000
+# DP: compatibility patches for isl-0.13
+
+diff -Naur a/gcc/graphite-clast-to-gimple.c b/gcc/graphite-clast-to-gimple.c
+--- a/src/gcc/graphite-clast-to-gimple.c	2014-03-03 21:39:22.000000000 +1000
++++ b/src/gcc/graphite-clast-to-gimple.c	2014-06-25 15:07:57.958697105 +1000
 @@ -28,6 +28,8 @@
  #include <isl/constraint.h>
  #include <isl/ilp.h>
@@ -10,9 +12,9 @@ diff -Naur gcc-4.9-20140604-old/gcc/graphite-clast-to-gimple.c gcc-4.9-20140604/
  #include <cloog/cloog.h>
  #include <cloog/isl/domain.h>
  #endif
-diff -Naur gcc-4.9-20140604-old/gcc/graphite-interchange.c gcc-4.9-20140604/gcc/graphite-interchange.c
---- gcc-4.9-20140604-old/src/gcc/graphite-interchange.c	2014-01-03 08:23:26.000000000 +1000
-+++ gcc-4.9-20140604/src/gcc/graphite-interchange.c	2014-06-25 15:10:06.882899243 +1000
+diff -Naur a/gcc/graphite-interchange.c b/gcc/graphite-interchange.c
+--- a/src/gcc/graphite-interchange.c	2014-01-03 08:23:26.000000000 +1000
++++ b/src/gcc/graphite-interchange.c	2014-06-25 15:10:06.882899243 +1000
 @@ -29,6 +29,9 @@
  #include <isl/map.h>
  #include <isl/union_map.h>
@@ -23,9 +25,9 @@ diff -Naur gcc-4.9-20140604-old/gcc/graphite-interchange.c gcc-4.9-20140604/gcc/
  #include <cloog/cloog.h>
  #include <cloog/isl/domain.h>
  #endif
-diff -Naur gcc-4.9-20140604-old/gcc/graphite-optimize-isl.c gcc-4.9-20140604/gcc/graphite-optimize-isl.c
---- gcc-4.9-20140604-old/src/gcc/graphite-optimize-isl.c	2014-01-03 08:23:26.000000000 +1000
-+++ gcc-4.9-20140604/src/gcc/graphite-optimize-isl.c	2014-06-25 15:16:57.038386166 +1000
+diff -Naur a/gcc/graphite-optimize-isl.c b/gcc/graphite-optimize-isl.c
+--- a/src/gcc/graphite-optimize-isl.c	2014-01-03 08:23:26.000000000 +1000
++++ b/src/gcc/graphite-optimize-isl.c	2014-06-25 15:16:57.038386166 +1000
 @@ -28,6 +28,8 @@
  #include <isl/band.h>
  #include <isl/aff.h>
@@ -44,9 +46,9 @@ diff -Naur gcc-4.9-20140604-old/gcc/graphite-optimize-isl.c gcc-4.9-20140604/gcc
  		{
  		  isl_map *TileMap;
  		  isl_union_map *TileUMap;
-diff -Naur gcc-4.9-20140604-old/gcc/graphite-poly.c gcc-4.9-20140604/gcc/graphite-poly.c
---- gcc-4.9-20140604-old/src/gcc/graphite-poly.c	2014-01-03 08:23:26.000000000 +1000
-+++ gcc-4.9-20140604/src/gcc/graphite-poly.c	2014-06-25 15:18:01.207157796 +1000
+diff -Naur a/gcc/graphite-poly.c b/gcc/graphite-poly.c
+--- a/src/gcc/graphite-poly.c	2014-01-03 08:23:26.000000000 +1000
++++ b/src/gcc/graphite-poly.c	2014-06-25 15:18:01.207157796 +1000
 @@ -28,6 +28,8 @@
  #include <isl/constraint.h>
  #include <isl/ilp.h>
@@ -56,9 +58,9 @@ diff -Naur gcc-4.9-20140604-old/gcc/graphite-poly.c gcc-4.9-20140604/gcc/graphit
  #include <cloog/cloog.h>
  #include <cloog/isl/domain.h>
  #endif
-diff -Naur gcc-4.9-20140604-old/gcc/graphite-sese-to-poly.c gcc-4.9-20140604/gcc/graphite-sese-to-poly.c
---- gcc-4.9-20140604-old/src/gcc/graphite-sese-to-poly.c	2014-04-08 20:59:40.000000000 +1000
-+++ gcc-4.9-20140604/src/gcc/graphite-sese-to-poly.c	2014-06-25 15:19:46.575140398 +1000
+diff -Naur a/gcc/graphite-sese-to-poly.c b/gcc/graphite-sese-to-poly.c
+--- a/src/gcc/graphite-sese-to-poly.c	2014-04-08 20:59:40.000000000 +1000
++++ b/src/gcc/graphite-sese-to-poly.c	2014-06-25 15:19:46.575140398 +1000
 @@ -26,6 +26,9 @@
  #include <isl/union_map.h>
  #include <isl/constraint.h>
diff --git a/debian/patches/kfreebsd-unwind.diff b/debian/patches/kfreebsd-unwind.diff
index 443c7ab..a4ee79c 100644
--- a/debian/patches/kfreebsd-unwind.diff
+++ b/debian/patches/kfreebsd-unwind.diff
@@ -4,7 +4,7 @@ Index: b/src/libgcc/config.host
 ===================================================================
 --- a/src/libgcc/config.host
 +++ b/src/libgcc/config.host
-@@ -567,7 +567,12 @@ i[34567]86-*-linux*)
+@@ -587,7 +587,12 @@ i[34567]86-*-linux*)
  	tmake_file="${tmake_file} i386/t-crtpc i386/t-crtfm i386/t-crtstuff t-dfprules"
  	md_unwind_header=i386/linux-unwind.h
  	;;
@@ -18,7 +18,7 @@ Index: b/src/libgcc/config.host
  	extra_parts="$extra_parts crtprec32.o crtprec64.o crtprec80.o crtfastmath.o"
  	tmake_file="${tmake_file} i386/t-crtpc i386/t-crtfm i386/t-crtstuff t-dfprules"
  	;;
-@@ -576,7 +581,12 @@ x86_64-*-linux*)
+@@ -596,7 +601,12 @@ x86_64-*-linux*)
  	tmake_file="${tmake_file} i386/t-crtpc i386/t-crtfm i386/t-crtstuff t-dfprules"
  	md_unwind_header=i386/linux-unwind.h
  	;;
diff --git a/debian/patches/libcilkrts-targets.diff b/debian/patches/libcilkrts-targets.diff
index 6bf0931..3c3e1c9 100644
--- a/debian/patches/libcilkrts-targets.diff
+++ b/debian/patches/libcilkrts-targets.diff
@@ -4,12 +4,18 @@ Index: b/src/libcilkrts/configure.tgt
 ===================================================================
 --- a/src/libcilkrts/configure.tgt
 +++ b/src/libcilkrts/configure.tgt
-@@ -46,7 +46,7 @@
- if test x$enable_libcilkrts = x ; then
-     # Enable libcilkrts by default on hosted POSIX systems.
-     case "${target}" in
--    *-*-linux* | *-*-gnu* | *-*-k*bsd*-gnu | *-*-kopensolaris*-gnu)
-+    *-*-linux* | *-*-kopensolaris*-gnu)
-         ;;
-     *-*-netbsd* | *-*-freebsd* | *-*-openbsd* | *-*-dragonfly*)
-         ;;
+@@ -44,3 +44,14 @@ esac
+ 
+ # Disable libcilkrts on non POSIX hosted systems.
+ . ${srcdir}/../config/target-posix
++
++# Disable libcilkrts on KFreeBSD and the Hurd.
++if test x$enable_libcilkrts = x ; then
++    case "${target}" in
++    *-*-linux*)
++        ;;
++    *-*-gnu* | *-*-k*bsd*-gnu)
++        UNSUPPORTED=1
++        ;;
++    esac
++fi
diff --git a/debian/patches/libffi-m68k.diff b/debian/patches/libffi-m68k.diff
deleted file mode 100644
index f4751de..0000000
--- a/debian/patches/libffi-m68k.diff
+++ /dev/null
@@ -1,141 +0,0 @@
-# DP: Apply #660525 fix to in-tree libffi
-
---- a/src/libffi/src/m68k/sysv.S
-+++ b/src/libffi/src/m68k/sysv.S
-@@ -2,9 +2,10 @@
- 	
-    sysv.S - Copyright (c) 2012 Alan Hourihane
- 	    Copyright (c) 1998, 2012 Andreas Schwab
--	    Copyright (c) 2008 Red Hat, Inc. 
--   
--   m68k Foreign Function Interface 
-+	    Copyright (c) 2008 Red Hat, Inc.
-+	    Copyright (c) 2012 Thorsten Glaser
-+
-+   m68k Foreign Function Interface
- 
-    Permission is hereby granted, free of charge, to any person obtaining
-    a copy of this software and associated documentation files (the
-@@ -168,8 +169,28 @@ retstruct1:
- 
- retstruct2:
- 	btst	#7,%d2
--	jbeq	noretval
-+	jbeq	retsint8
- 	move.w	%d0,(%a1)
-+	jbra	epilogue
-+
-+retsint8:
-+	btst	#8,%d2
-+	jbeq	retsint16
-+	| NOTE: On the mc68000, extb is not supported. 8->16, then 16->32.
-+#if !defined(__mc68020__) && !defined(__mc68030__) && !defined(__mc68040__) && !defined(__mc68060__) && !defined(__mcoldfire__)
-+	ext.w	%d0
-+	ext.l	%d0
-+#else
-+	extb.l	%d0
-+#endif
-+	move.l	%d0,(%a1)
-+	jbra	epilogue
-+
-+retsint16:
-+	btst	#9,%d2
-+	jbeq	noretval
-+	ext.l	%d0
-+	move.l	%d0,(%a1)
- 
- noretval:
- epilogue:
-@@ -201,8 +222,10 @@ CALLFUNC(ffi_closure_SYSV):
- 	lsr.l	#1,%d0
- 	jne	1f
- 	jcc	.Lcls_epilogue
-+	| CIF_FLAGS_INT
- 	move.l	-12(%fp),%d0
- .Lcls_epilogue:
-+	| no CIF_FLAGS_*
- 	unlk	%fp
- 	rts
- 1:
-@@ -210,6 +233,7 @@ CALLFUNC(ffi_closure_SYSV):
- 	lsr.l	#2,%d0
- 	jne	1f
- 	jcs	.Lcls_ret_float
-+	| CIF_FLAGS_DINT
- 	move.l	(%a0)+,%d0
- 	move.l	(%a0),%d1
- 	jra	.Lcls_epilogue
-@@ -224,6 +248,7 @@ CALLFUNC(ffi_closure_SYSV):
- 	lsr.l	#2,%d0
- 	jne	1f
- 	jcs	.Lcls_ret_ldouble
-+	| CIF_FLAGS_DOUBLE
- #if defined(__MC68881__) || defined(__HAVE_68881__)
- 	fmove.d	(%a0),%fp0
- #else
-@@ -242,17 +267,37 @@ CALLFUNC(ffi_closure_SYSV):
- 	jra	.Lcls_epilogue
- 1:
- 	lsr.l	#2,%d0
--	jne	.Lcls_ret_struct2
-+	jne	1f
- 	jcs	.Lcls_ret_struct1
-+	| CIF_FLAGS_POINTER
- 	move.l	(%a0),%a0
- 	move.l	%a0,%d0
- 	jra	.Lcls_epilogue
- .Lcls_ret_struct1:
- 	move.b	(%a0),%d0
- 	jra	.Lcls_epilogue
--.Lcls_ret_struct2:
-+1:
-+	lsr.l	#2,%d0
-+	jne	1f
-+	jcs	.Lcls_ret_sint8
-+	| CIF_FLAGS_STRUCT2
- 	move.w	(%a0),%d0
- 	jra	.Lcls_epilogue
-+.Lcls_ret_sint8:
-+	move.l	(%a0),%d0
-+	| NOTE: On the mc68000, extb is not supported. 8->16, then 16->32.
-+#if !defined(__mc68020__) && !defined(__mc68030__) && !defined(__mc68040__) && !defined(__mc68060__) && !defined(__mcoldfire__)
-+	ext.w	%d0
-+	ext.l	%d0
-+#else
-+	extb.l	%d0
-+#endif
-+	jra	.Lcls_epilogue
-+1:
-+	| CIF_FLAGS_SINT16
-+	move.l	(%a0),%d0
-+	ext.l	%d0
-+	jra	.Lcls_epilogue
- 	CFI_ENDPROC()
- 
- 	.size	CALLFUNC(ffi_closure_SYSV),.-CALLFUNC(ffi_closure_SYSV)
---- a/src/libffi/src/m68k/ffi.c
-+++ b/src/libffi/src/m68k/ffi.c
-@@ -123,6 +123,8 @@ ffi_prep_args (void *stack, extended_cif
- #define CIF_FLAGS_POINTER	32
- #define CIF_FLAGS_STRUCT1	64
- #define CIF_FLAGS_STRUCT2	128
-+#define CIF_FLAGS_SINT8		256
-+#define CIF_FLAGS_SINT16	512
- 
- /* Perform machine dependent cif processing */
- ffi_status
-@@ -200,6 +202,14 @@ ffi_prep_cif_machdep (ffi_cif *cif)
-       cif->flags = CIF_FLAGS_DINT;
-       break;
- 
-+    case FFI_TYPE_SINT16:
-+      cif->flags = CIF_FLAGS_SINT16;
-+      break;
-+
-+    case FFI_TYPE_SINT8:
-+      cif->flags = CIF_FLAGS_SINT8;
-+      break;
-+
-     default:
-       cif->flags = CIF_FLAGS_INT;
-       break;
diff --git a/debian/patches/libffi-ro-eh_frame_sect.diff b/debian/patches/libffi-ro-eh_frame_sect.diff
index 671b7d0..d208d33 100644
--- a/debian/patches/libffi-ro-eh_frame_sect.diff
+++ b/debian/patches/libffi-ro-eh_frame_sect.diff
@@ -4,12 +4,12 @@ Index: b/src/libffi/configure.ac
 ===================================================================
 --- a/src/libffi/configure.ac
 +++ b/src/libffi/configure.ac
-@@ -420,6 +420,8 @@
-   		libffi_cv_ro_eh_frame=yes
+@@ -294,6 +294,8 @@ if test "x$GCC" = "xyes"; then
+   		libffi_cv_hidden_visibility_attribute=yes
    	    fi
    	fi
 +	# FIXME: see PR libffi/47248
 +	libffi_cv_ro_eh_frame=yes
    	rm -f conftest.*
        ])
-   if test "x$libffi_cv_ro_eh_frame" = xyes; then
+   if test $libffi_cv_hidden_visibility_attribute = yes; then
diff --git a/debian/patches/libgo-revert-timeout-exp.diff b/debian/patches/libgo-revert-timeout-exp.diff
index 81032b1..fbf8a6c 100644
--- a/debian/patches/libgo-revert-timeout-exp.diff
+++ b/debian/patches/libgo-revert-timeout-exp.diff
@@ -1,8 +1,10 @@
+Index: b/src/libgo/testsuite/lib/libgo.exp
+===================================================================
 --- a/src/libgo/testsuite/lib/libgo.exp
 +++ b/src/libgo/testsuite/lib/libgo.exp
-@@ -43,7 +43,6 @@
- load_gcc_lib target-libpath.exp
- load_gcc_lib wrapper.exp
+@@ -45,7 +45,6 @@ load_gcc_lib wrapper.exp
+ load_gcc_lib target-supports.exp
+ load_gcc_lib target-utils.exp
  load_gcc_lib gcc-defs.exp
 -load_gcc_lib timeout.exp
  load_gcc_lib go.exp
diff --git a/debian/patches/libgo-setcontext-config.diff b/debian/patches/libgo-setcontext-config.diff
index 0a7aaaa..c6895b4 100644
--- a/debian/patches/libgo-setcontext-config.diff
+++ b/debian/patches/libgo-setcontext-config.diff
@@ -4,7 +4,7 @@ Index: b/src/libgo/configure.ac
 ===================================================================
 --- a/src/libgo/configure.ac
 +++ b/src/libgo/configure.ac
-@@ -763,6 +763,14 @@ main ()
+@@ -791,6 +791,14 @@ main ()
  CFLAGS="$CFLAGS_hold"
  LIBS="$LIBS_hold"
  ])
diff --git a/debian/patches/libgo-testsuite.diff b/debian/patches/libgo-testsuite.diff
index bab70e6..bf3a564 100644
--- a/debian/patches/libgo-testsuite.diff
+++ b/debian/patches/libgo-testsuite.diff
@@ -4,7 +4,7 @@ Index: b/src/libgo/Makefile.am
 ===================================================================
 --- a/src/libgo/Makefile.am
 +++ b/src/libgo/Makefile.am
-@@ -1997,6 +1997,12 @@ CHECK = \
+@@ -2055,6 +2055,12 @@ CHECK = \
  	export LD_LIBRARY_PATH; \
  	$(MKDIR_P) $(@D); \
  	rm -f $@-testsum $@-testlog; \
@@ -16,8 +16,8 @@ Index: b/src/libgo/Makefile.am
 +	if test "$$run_check" = "yes"; then \
  	if test "$(USE_DEJAGNU)" = "yes"; then \
  	  $(SHELL) $(srcdir)/testsuite/gotest --dejagnu=yes --basedir=$(srcdir) --srcdir=$(srcdir)/go/$(@D) --pkgpath="$(@D)" --pkgfiles="$(go_$(subst /,_,$(@D))_files)" --testname="$(@D)" --goarch="$(GOARCH)" $(GOTESTFLAGS) $(go_$(subst /,_,$(@D))_test_files); \
- 	else \
-@@ -2010,6 +2016,7 @@ CHECK = \
+ 	elif test "$(GOBENCH)" != ""; then \
+@@ -2070,6 +2076,7 @@ CHECK = \
  	    echo "FAIL: $(@D)" > $@-testsum; \
  	    exit 1; \
  	  fi; \
@@ -29,7 +29,7 @@ Index: b/src/libgo/Makefile.in
 ===================================================================
 --- a/src/libgo/Makefile.in
 +++ b/src/libgo/Makefile.in
-@@ -2067,6 +2067,12 @@ CHECK = \
+@@ -2122,6 +2122,12 @@ CHECK = \
  	export LD_LIBRARY_PATH; \
  	$(MKDIR_P) $(@D); \
  	rm -f $@-testsum $@-testlog; \
@@ -41,8 +41,8 @@ Index: b/src/libgo/Makefile.in
 +	if test "$$run_check" = "yes"; then \
  	if test "$(USE_DEJAGNU)" = "yes"; then \
  	  $(SHELL) $(srcdir)/testsuite/gotest --dejagnu=yes --basedir=$(srcdir) --srcdir=$(srcdir)/go/$(@D) --pkgpath="$(@D)" --pkgfiles="$(go_$(subst /,_,$(@D))_files)" --testname="$(@D)" --goarch="$(GOARCH)" $(GOTESTFLAGS) $(go_$(subst /,_,$(@D))_test_files); \
- 	else \
-@@ -2080,6 +2086,7 @@ CHECK = \
+ 	elif test "$(GOBENCH)" != ""; then \
+@@ -2137,6 +2143,7 @@ CHECK = \
  	    echo "FAIL: $(@D)" > $@-testsum; \
  	    exit 1; \
  	  fi; \
diff --git a/debian/patches/libgomp-omp_h-multilib.diff b/debian/patches/libgomp-omp_h-multilib.diff
index cebac43..05ff73d 100644
--- a/debian/patches/libgomp-omp_h-multilib.diff
+++ b/debian/patches/libgomp-omp_h-multilib.diff
@@ -4,9 +4,11 @@
 
 	* omp.h.in (omp_nest_lock_t): Fix up for Linux multilibs.
 
+Index: b/src/libgomp/omp.h.in
+===================================================================
 --- a/src/libgomp/omp.h.in
 +++ b/src/libgomp/omp.h.in
-@@ -39,8 +39,8 @@
+@@ -40,8 +40,8 @@ typedef struct
  
  typedef struct
  {
diff --git a/debian/patches/libitm-no-fortify-source.diff b/debian/patches/libitm-no-fortify-source.diff
index 30821d3..8f15964 100644
--- a/debian/patches/libitm-no-fortify-source.diff
+++ b/debian/patches/libitm-no-fortify-source.diff
@@ -4,7 +4,7 @@ Index: b/src/libitm/configure.tgt
 ===================================================================
 --- a/src/libitm/configure.tgt
 +++ b/src/libitm/configure.tgt
-@@ -118,6 +118,12 @@
+@@ -119,6 +119,12 @@ case "${target_cpu}" in
  	;;
  esac
  
diff --git a/debian/patches/libjava-jnipath.diff b/debian/patches/libjava-jnipath.diff
index d883777..b34c160 100644
--- a/debian/patches/libjava-jnipath.diff
+++ b/debian/patches/libjava-jnipath.diff
@@ -6,7 +6,7 @@ Index: b/src/libjava/configure.ac
 ===================================================================
 --- a/src/libjava/configure.ac
 +++ b/src/libjava/configure.ac
-@@ -1525,6 +1525,9 @@ AC_CHECK_SIZEOF(void *)
+@@ -1520,6 +1520,9 @@ AC_CHECK_SIZEOF(void *)
  
  AC_C_BIGENDIAN
  
diff --git a/debian/patches/libjava-multiarch.diff b/debian/patches/libjava-multiarch.diff
index 392d3bd..ffcf8fa 100644
--- a/debian/patches/libjava-multiarch.diff
+++ b/debian/patches/libjava-multiarch.diff
@@ -4,7 +4,7 @@ Index: b/src/libjava/configure.ac
 ===================================================================
 --- a/src/libjava/configure.ac
 +++ b/src/libjava/configure.ac
-@@ -1585,6 +1585,10 @@
+@@ -1580,6 +1580,10 @@ case ${version_specific_libs} in
        .) toolexeclibdir=$toolexecmainlibdir ;; # Avoid trailing /.
        *) toolexeclibdir=$toolexecmainlibdir/$multi_os_directory ;;
      esac
@@ -15,7 +15,7 @@ Index: b/src/libjava/configure.ac
      ;;
  esac
  AC_SUBST(toolexecdir)
-@@ -1602,6 +1606,10 @@
+@@ -1597,6 +1601,10 @@ AC_DEFINE_UNQUOTED(GCJVERSION, "$GCJVERS
  # libraries are found.
  gcjsubdir=gcj-$gcjversion-$libgcj_soversion
  dbexecdir='$(toolexeclibdir)/'$gcjsubdir
@@ -30,12 +30,12 @@ Index: b/src/libjava/Makefile.am
 ===================================================================
 --- a/src/libjava/Makefile.am
 +++ b/src/libjava/Makefile.am
-@@ -373,7 +373,7 @@
+@@ -373,7 +373,7 @@ AM_CXXFLAGS = \
  	-DGCJ_VERSIONED_LIBDIR="\"$(dbexecdir)\"" \
  	-DPATH_SEPARATOR="\"$(CLASSPATH_SEPARATOR)\"" \
  	-DECJ_JAR_FILE="\"$(ECJ_JAR)\"" \
 -	-DLIBGCJ_DEFAULT_DATABASE="\"$(dbexecdir)/$(db_name)\"" \
-+	-DLIBGCJ_DEFAULT_DATABASE="\"/var/lib/$(MULTIARCH_DIR)/gcj-4.9/$(db_name)\"" \
++	-DLIBGCJ_DEFAULT_DATABASE="\"/var/lib/$(MULTIARCH_DIR)/gcj-5/$(db_name)\"" \
  	-DLIBGCJ_DEFAULT_DATABASE_PATH_TAIL="\"$(db_pathtail)\""
  
  AM_GCJFLAGS = \
@@ -43,12 +43,12 @@ Index: b/src/libjava/Makefile.in
 ===================================================================
 --- a/src/libjava/Makefile.in
 +++ b/src/libjava/Makefile.in
-@@ -1032,7 +1032,7 @@
+@@ -1032,7 +1032,7 @@ AM_CXXFLAGS = \
  	-DGCJ_VERSIONED_LIBDIR="\"$(dbexecdir)\"" \
  	-DPATH_SEPARATOR="\"$(CLASSPATH_SEPARATOR)\"" \
  	-DECJ_JAR_FILE="\"$(ECJ_JAR)\"" \
 -	-DLIBGCJ_DEFAULT_DATABASE="\"$(dbexecdir)/$(db_name)\"" \
-+	-DLIBGCJ_DEFAULT_DATABASE="\"/var/lib/$(MULTIARCH_DIR)/gcj-4.9/$(db_name)\"" \
++	-DLIBGCJ_DEFAULT_DATABASE="\"/var/lib/$(MULTIARCH_DIR)/gcj-5/$(db_name)\"" \
  	-DLIBGCJ_DEFAULT_DATABASE_PATH_TAIL="\"$(db_pathtail)\""
  
  AM_GCJFLAGS = \
@@ -56,7 +56,7 @@ Index: b/src/libjava/classpath/m4/acinclude.m4
 ===================================================================
 --- a/src/libjava/classpath/m4/acinclude.m4
 +++ b/src/libjava/classpath/m4/acinclude.m4
-@@ -276,6 +276,10 @@
+@@ -276,6 +276,10 @@ AC_DEFUN([CLASSPATH_TOOLEXECLIBDIR],
        esac
        ;;
    esac
@@ -71,7 +71,7 @@ Index: b/src/libjava/classpath/configure.ac
 ===================================================================
 --- a/src/libjava/classpath/configure.ac
 +++ b/src/libjava/classpath/configure.ac
-@@ -16,6 +16,8 @@
+@@ -16,6 +16,8 @@ dnl END GCJ LOCAL
  
  AC_CANONICAL_TARGET
  
diff --git a/debian/patches/libobjc-extern-inline.diff b/debian/patches/libobjc-extern-inline.diff
new file mode 100644
index 0000000..0eb5b69
--- /dev/null
+++ b/debian/patches/libobjc-extern-inline.diff
@@ -0,0 +1,22 @@
+# DP: libobjc: still export __objc_get_forward_imp and get_imp
+
+--- a/src/libobjc/sendmsg.c
++++ b/src/libobjc/sendmsg.c
+@@ -105,7 +105,7 @@
+ id nil_method (id, SEL);
+ 
+ /* Given a selector, return the proper forwarding implementation.  */
+-inline
++extern inline
+ IMP
+ __objc_get_forward_imp (id rcv, SEL sel)
+ {
+@@ -320,7 +320,7 @@
+   return res;
+ }
+ 
+-inline
++extern inline
+ IMP
+ get_imp (Class class, SEL sel)
+ {
diff --git a/debian/patches/libstdc++-doclink.diff b/debian/patches/libstdc++-doclink.diff
index e4818c6..30a8d31 100644
--- a/debian/patches/libstdc++-doclink.diff
+++ b/debian/patches/libstdc++-doclink.diff
@@ -41,7 +41,7 @@ Index: b/src/libstdc++-v3/doc/html/api.html
 ===================================================================
 --- a/src/libstdc++-v3/doc/html/api.html
 +++ b/src/libstdc++-v3/doc/html/api.html
-@@ -18,6 +18,8 @@
+@@ -20,6 +20,8 @@
    member functions for the library classes, finding out what is in a
    particular include file, looking at inheritance diagrams, etc.
  </p><p>
@@ -54,7 +54,7 @@ Index: b/src/libstdc++-v3/doc/xml/api.xml
 ===================================================================
 --- a/src/libstdc++-v3/doc/xml/api.xml
 +++ b/src/libstdc++-v3/doc/xml/api.xml
-@@ -37,6 +37,11 @@
+@@ -40,6 +40,11 @@
  </para>
  
  <para>
diff --git a/debian/patches/libstdc++-man-3cxx.diff b/debian/patches/libstdc++-man-3cxx.diff
index da4ae35..0109e5c 100644
--- a/debian/patches/libstdc++-man-3cxx.diff
+++ b/debian/patches/libstdc++-man-3cxx.diff
@@ -4,15 +4,15 @@ Index: b/src/libstdc++-v3/doc/doxygen/user.cfg.in
 ===================================================================
 --- a/src/libstdc++-v3/doc/doxygen/user.cfg.in
 +++ b/src/libstdc++-v3/doc/doxygen/user.cfg.in
-@@ -1618,7 +1618,7 @@ MAN_OUTPUT             = man
- # The MAN_EXTENSION tag determines the extension that is added to
- # the generated man pages (default is the subroutine's section .3)
+@@ -1936,7 +1936,7 @@ MAN_OUTPUT             = man
+ # The default value is: .3.
+ # This tag requires that the tag GENERATE_MAN is set to YES.
  
 -MAN_EXTENSION          = .3
 +MAN_EXTENSION          = .3cxx
  
- # If the MAN_LINKS tag is set to YES and Doxygen generates man output,
- # then it will generate one additional man file for each entity
+ # If the MAN_LINKS tag is set to YES and doxygen generates man output, then it
+ # will generate one additional man file for each entity documented in the real
 Index: b/src/libstdc++-v3/scripts/run_doxygen
 ===================================================================
 --- a/src/libstdc++-v3/scripts/run_doxygen
diff --git a/debian/patches/libstdc++-pic.diff b/debian/patches/libstdc++-pic.diff
index 818e4c9..22a770a 100644
--- a/debian/patches/libstdc++-pic.diff
+++ b/debian/patches/libstdc++-pic.diff
@@ -4,7 +4,7 @@ Index: b/src/libstdc++-v3/src/Makefile.am
 ===================================================================
 --- a/src/libstdc++-v3/src/Makefile.am
 +++ b/src/libstdc++-v3/src/Makefile.am
-@@ -278,10 +278,12 @@
+@@ -278,10 +278,12 @@ if GLIBCXX_BUILD_DEBUG
  STAMP_DEBUG = build-debug
  STAMP_INSTALL_DEBUG = install-debug
  CLEAN_DEBUG = debug
@@ -17,7 +17,7 @@ Index: b/src/libstdc++-v3/src/Makefile.am
  endif
  
  # Build a debug variant.
-@@ -316,6 +318,7 @@
+@@ -316,6 +318,7 @@ build-debug: stamp-debug
  	  mv Makefile Makefile.tmp; \
  	  sed -e 's,all-local: all-once,all-local:,' \
  	      -e 's,install-data-local: install-data-once,install-data-local:,' \
@@ -25,7 +25,7 @@ Index: b/src/libstdc++-v3/src/Makefile.am
  	      -e '/vpath/!s,src/c,src/debug/c,' \
  	  < Makefile.tmp > Makefile ; \
  	  rm -f Makefile.tmp ; \
-@@ -326,3 +329,8 @@
+@@ -326,3 +329,8 @@ build-debug: stamp-debug
  install-debug: build-debug
  	(cd ${debugdir} && $(MAKE) CXXFLAGS='$(DEBUG_FLAGS)' \
  	toolexeclibdir=$(glibcxx_toolexeclibdir)/debug install) ;
@@ -38,7 +38,7 @@ Index: b/src/libstdc++-v3/src/Makefile.in
 ===================================================================
 --- a/src/libstdc++-v3/src/Makefile.in
 +++ b/src/libstdc++-v3/src/Makefile.in
-@@ -480,6 +480,8 @@
+@@ -481,6 +481,8 @@ CXXLINK = \
  @GLIBCXX_BUILD_DEBUG_TRUE@STAMP_INSTALL_DEBUG = install-debug
  @GLIBCXX_BUILD_DEBUG_FALSE@CLEAN_DEBUG = 
  @GLIBCXX_BUILD_DEBUG_TRUE@CLEAN_DEBUG = debug
@@ -47,7 +47,7 @@ Index: b/src/libstdc++-v3/src/Makefile.in
  
  # Build a debug variant.
  # Take care to fix all possibly-relative paths.
-@@ -769,7 +771,7 @@
+@@ -770,7 +772,7 @@ install-dvi: install-dvi-recursive
  
  install-dvi-am:
  
@@ -56,7 +56,7 @@ Index: b/src/libstdc++-v3/src/Makefile.in
  
  install-html: install-html-recursive
  
-@@ -820,11 +822,11 @@
+@@ -821,11 +823,11 @@ uninstall-am: uninstall-toolexeclibLTLIB
  	distclean-libtool distclean-tags dvi dvi-am html html-am info \
  	info-am install install-am install-data install-data-am \
  	install-data-local install-dvi install-dvi-am install-exec \
@@ -73,7 +73,7 @@ Index: b/src/libstdc++-v3/src/Makefile.in
  	maintainer-clean-generic mostlyclean mostlyclean-compile \
  	mostlyclean-generic mostlyclean-libtool pdf pdf-am ps ps-am \
  	tags tags-recursive uninstall uninstall-am \
-@@ -952,6 +954,7 @@
+@@ -953,6 +955,7 @@ build-debug: stamp-debug
  	  mv Makefile Makefile.tmp; \
  	  sed -e 's,all-local: all-once,all-local:,' \
  	      -e 's,install-data-local: install-data-once,install-data-local:,' \
@@ -81,7 +81,7 @@ Index: b/src/libstdc++-v3/src/Makefile.in
  	      -e '/vpath/!s,src/c,src/debug/c,' \
  	  < Makefile.tmp > Makefile ; \
  	  rm -f Makefile.tmp ; \
-@@ -963,6 +966,11 @@
+@@ -964,6 +967,11 @@ install-debug: build-debug
  	(cd ${debugdir} && $(MAKE) CXXFLAGS='$(DEBUG_FLAGS)' \
  	toolexeclibdir=$(glibcxx_toolexeclibdir)/debug install) ;
  
diff --git a/debian/patches/libstdc++-test-installed.diff b/debian/patches/libstdc++-test-installed.diff
index 2e07aff..09ec295 100644
--- a/debian/patches/libstdc++-test-installed.diff
+++ b/debian/patches/libstdc++-test-installed.diff
@@ -16,9 +16,9 @@ Index: b/src/libstdc++-v3/testsuite/lib/libstdc++.exp
 +}
 +
  proc load_gcc_lib { filename } {
-     global srcdir
-     load_file $srcdir/../../gcc/testsuite/lib/$filename
-@@ -93,6 +99,7 @@
+     global srcdir loaded_libs
+ 
+@@ -101,6 +107,7 @@ proc libstdc++_init { testfile } {
      global tool_timeout
      global DEFAULT_CXXFLAGS
      global STATIC_LIBCXXFLAGS
@@ -26,7 +26,7 @@ Index: b/src/libstdc++-v3/testsuite/lib/libstdc++.exp
  
      # We set LC_ALL and LANG to C so that we get the same error
      # messages as expected.
-@@ -108,6 +115,9 @@
+@@ -116,6 +123,9 @@ proc libstdc++_init { testfile } {
  
      set blddir [lookfor_file [get_multilibs] libstdc++-v3]
      set flags_file "${blddir}/scripts/testsuite_flags"
@@ -36,7 +36,7 @@ Index: b/src/libstdc++-v3/testsuite/lib/libstdc++.exp
      set shlib_ext [get_shlib_extension]
      v3track flags_file 2
  
-@@ -139,7 +149,11 @@
+@@ -147,7 +157,11 @@ proc libstdc++_init { testfile } {
  
      # Locate libgcc.a so we don't need to account for different values of
      # SHLIB_EXT on different platforms
@@ -49,7 +49,7 @@ Index: b/src/libstdc++-v3/testsuite/lib/libstdc++.exp
      if {$gccdir != ""} {
          set gccdir [file dirname $gccdir]
  	append ld_library_path_tmp ":${gccdir}"
-@@ -148,7 +162,11 @@
+@@ -156,7 +170,11 @@ proc libstdc++_init { testfile } {
  
      # Locate libgomp. This is only required for parallel mode.
      set v3-libgomp 0
@@ -62,7 +62,7 @@ Index: b/src/libstdc++-v3/testsuite/lib/libstdc++.exp
      if {$libgompdir != ""} {
  	set v3-libgomp 1
          set libgompdir [file dirname $libgompdir]
-@@ -170,7 +188,12 @@
+@@ -178,7 +196,12 @@ proc libstdc++_init { testfile } {
  
      # Locate libstdc++ shared library. (ie libstdc++.so.)
      set v3-sharedlib 0
diff --git a/debian/patches/mips-fix-loongson2f-nop-trunk.diff b/debian/patches/mips-fix-loongson2f-nop-trunk.diff
deleted file mode 100644
index 2fc8dd9..0000000
--- a/debian/patches/mips-fix-loongson2f-nop-trunk.diff
+++ /dev/null
@@ -1,15 +0,0 @@
-# DP: On mips, pass -mfix-loongson2f-nop to as, if -mno-fix-loongson2f-nop
-# DP: is not passed.
-
-Index: b/src/gcc/config/mips/mips.h
-===================================================================
---- a/src/gcc/config/mips/mips.h
-+++ b/src/gcc/config/mips/mips.h
-@@ -1189,6 +1189,7 @@ struct mips_cpu_info {
- %{mtune=*} \
- %{mhard-float} %{msoft-float} \
- %{msingle-float} %{mdouble-float} \
-+%{!mno-fix-loongson2f-nop:-mfix-loongson2f-nop} \
- %(subtarget_asm_spec)"
- 
- /* Extra switches sometimes passed to the linker.  */
diff --git a/debian/patches/mips-fix-loongson2f-nop.diff b/debian/patches/mips-fix-loongson2f-nop.diff
index a6227f1..c74ab01 100644
--- a/debian/patches/mips-fix-loongson2f-nop.diff
+++ b/debian/patches/mips-fix-loongson2f-nop.diff
@@ -5,10 +5,10 @@ Index: b/src/gcc/config/mips/mips.h
 ===================================================================
 --- a/src/gcc/config/mips/mips.h
 +++ b/src/gcc/config/mips/mips.h
-@@ -1237,6 +1237,7 @@ struct mips_cpu_info {
- %{mshared} %{mno-shared} \
+@@ -1295,6 +1295,7 @@ struct mips_cpu_info {
  %{msym32} %{mno-sym32} \
- %{mtune=*} \
+ %{mtune=*}" \
+ FP_ASM_SPEC "\
 +%{!mno-fix-loongson2f-nop:-mfix-loongson2f-nop} \
  %(subtarget_asm_spec)"
  
diff --git a/debian/patches/note-gnu-stack.diff b/debian/patches/note-gnu-stack.diff
index eaed613..e9ff769 100644
--- a/debian/patches/note-gnu-stack.diff
+++ b/debian/patches/note-gnu-stack.diff
@@ -102,7 +102,7 @@ Index: b/src/libgcc/config/ia64/crtbegin.S
 ===================================================================
 --- a/src/libgcc/config/ia64/crtbegin.S
 +++ b/src/libgcc/config/ia64/crtbegin.S
-@@ -252,3 +252,7 @@
+@@ -252,3 +252,7 @@ __do_jv_register_classes:
  .weak __cxa_finalize
  #endif
  .weak _Jv_RegisterClasses
@@ -114,7 +114,7 @@ Index: b/src/libgcc/config/ia64/crtend.S
 ===================================================================
 --- a/src/libgcc/config/ia64/crtend.S
 +++ b/src/libgcc/config/ia64/crtend.S
-@@ -119,3 +119,7 @@
+@@ -119,3 +119,7 @@ __do_global_ctors_aux:
  
  	br.ret.sptk.many rp
  	.endp __do_global_ctors_aux
@@ -126,7 +126,7 @@ Index: b/src/libgcc/config/ia64/crti.S
 ===================================================================
 --- a/src/libgcc/config/ia64/crti.S
 +++ b/src/libgcc/config/ia64/crti.S
-@@ -51,3 +51,7 @@
+@@ -51,3 +51,7 @@ _fini:
  	.body
  
  # end of crti.S
@@ -150,7 +150,7 @@ Index: b/src/libgcc/config/ia64/lib1funcs.S
 ===================================================================
 --- a/src/libgcc/config/ia64/lib1funcs.S
 +++ b/src/libgcc/config/ia64/lib1funcs.S
-@@ -793,3 +793,7 @@
+@@ -793,3 +793,7 @@ __floattitf:
  	.endp __floattitf
  #endif
  #endif
@@ -162,7 +162,7 @@ Index: b/src/gcc/config/ia64/linux.h
 ===================================================================
 --- a/src/gcc/config/ia64/linux.h
 +++ b/src/gcc/config/ia64/linux.h
-@@ -86,5 +86,8 @@
+@@ -79,5 +79,8 @@ do {						\
  #undef TARGET_INIT_LIBFUNCS
  #define TARGET_INIT_LIBFUNCS ia64_soft_fp_init_libfuncs
  
@@ -175,7 +175,7 @@ Index: b/src/gcc/config/rs6000/ppc-asm.h
 ===================================================================
 --- a/src/gcc/config/rs6000/ppc-asm.h
 +++ b/src/gcc/config/rs6000/ppc-asm.h
-@@ -375,7 +375,7 @@
+@@ -375,7 +375,7 @@ GLUE(.L,name): \
  #endif
  #endif
  
diff --git a/debian/patches/pr47818.diff b/debian/patches/pr47818.diff
index f271291..9f53bca 100644
--- a/debian/patches/pr47818.diff
+++ b/debian/patches/pr47818.diff
@@ -4,7 +4,7 @@ Index: b/src/gcc/ada/sem_prag.adb
 ===================================================================
 --- a/src/gcc/ada/sem_prag.adb
 +++ b/src/gcc/ada/sem_prag.adb
-@@ -11882,7 +11882,16 @@ package body Sem_Prag is
+@@ -11629,7 +11629,16 @@ package body Sem_Prag is
              Str   : Node_Id;
  
           begin
diff --git a/debian/patches/pr49944.diff b/debian/patches/pr49944.diff
index d07d2c8..f7e42d3 100644
--- a/debian/patches/pr49944.diff
+++ b/debian/patches/pr49944.diff
@@ -174,7 +174,7 @@ Index: b/src/gcc/ada/gcc-interface/Makefile.in
 ===================================================================
 --- a/src/gcc/ada/gcc-interface/Makefile.in
 +++ b/src/gcc/ada/gcc-interface/Makefile.in
-@@ -1275,9 +1275,7 @@ ifeq ($(strip $(filter-out %86 kfreebsd%
+@@ -1364,9 +1364,7 @@ ifeq ($(strip $(filter-out %86 kfreebsd%
    s-osinte.adb<s-osinte-posix.adb \
    s-osinte.ads<s-osinte-kfreebsd-gnu.ads \
    s-osprim.adb<s-osprim-posix.adb \
@@ -185,7 +185,7 @@ Index: b/src/gcc/ada/gcc-interface/Makefile.in
    s-taspri.ads<s-taspri-posix.ads \
    s-tpopsp.adb<s-tpopsp-posix-foreign.adb \
    $(ATOMICS_TARGET_PAIRS) \
-@@ -1308,9 +1306,7 @@ ifeq ($(strip $(filter-out x86_64 kfreeb
+@@ -1397,9 +1395,7 @@ ifeq ($(strip $(filter-out x86_64 kfreeb
    s-osinte.adb<s-osinte-posix.adb \
    s-osinte.ads<s-osinte-kfreebsd-gnu.ads \
    s-osprim.adb<s-osprim-posix.adb \
diff --git a/debian/patches/pr57653.diff b/debian/patches/pr57653.diff
deleted file mode 100644
index ea42013..0000000
--- a/debian/patches/pr57653.diff
+++ /dev/null
@@ -1,17 +0,0 @@
-# DP: Proposed patch for PR c/57653.
-
-Index: b/src/gcc/c-family/c-opts.c
-===================================================================
---- a/src/gcc/c-family/c-opts.c
-+++ b/src/gcc/c-family/c-opts.c
-@@ -1363,6 +1363,10 @@ c_finish_options (void)
- static void
- push_command_line_include (void)
- {
-+  // This can happen if disabled by -imacros for example.
-+  if (include_cursor > deferred_count)
-+    return;
-+
-   if (!done_preinclude)
-     {
-       done_preinclude = true;
diff --git a/debian/patches/pr59586.diff b/debian/patches/pr59586.diff
deleted file mode 100644
index d927240..0000000
--- a/debian/patches/pr59586.diff
+++ /dev/null
@@ -1,120 +0,0 @@
-# DP: Fix PR tree-optimization/59586, segfault with -Ofast -floop-parallelize-all
-
-gcc/
-
-2014-06-29  Roman Gareev  <gareevroman@gmail.com>
-
-	* graphite-dependences.c (subtract_commutative_associative_deps): 
-	Add NULL checking of the following variables: must_raw_no_source, 
-	may_raw_no_source, must_war_no_source, may_war_no_source, 
-	must_waw_no_source, may_waw_no_source, must_raw, may_raw, 
-	must_war, may_war, must_waw, may_waw
-
-	testsuite/gfortran.dg/graphite/pr59586.f: New testcase.
-
---- a/src/gcc/testsuite/gfortran.dg/graphite/pr59586.f
-+++ b/src/gcc/testsuite/gfortran.dg/graphite/pr59586.f
-@@ -0,0 +1,11 @@
-+! { dg-additional-options "-Ofast -floop-parallelize-all" }
-+
-+      subroutine subsm ( n, x, xp, xx)
-+      integer        n, m, x(n),xp(n), xx(n), gg(n), dd_p
-+      do 55 i=1, n
-+         dd_p  = dd_p + (x(i) - xx(i))*gg(i)
-+ 55   continue
-+      if ( dd_p .gt. 0  ) then
-+         call dcopy( n, xp, 1, x, 1 )
-+      endif
-+      end
---- a/src/gcc/graphite-dependences.c
-+++ b/src/gcc/graphite-dependences.c
-@@ -424,24 +424,71 @@
- 					  &x_may_waw_no_source);
- 	gcc_assert (res == 0);
- 
--	*must_raw = isl_union_map_subtract (*must_raw, x_must_raw);
--	*may_raw = isl_union_map_subtract (*may_raw, x_may_raw);
--	*must_raw_no_source = isl_union_map_subtract (*must_raw_no_source,
--						      x_must_raw_no_source);
--	*may_raw_no_source = isl_union_map_subtract (*may_raw_no_source,
--						     x_may_raw_no_source);
--	*must_war = isl_union_map_subtract (*must_war, x_must_war);
--	*may_war = isl_union_map_subtract (*may_war, x_may_war);
--	*must_war_no_source = isl_union_map_subtract (*must_war_no_source,
--						      x_must_war_no_source);
--	*may_war_no_source = isl_union_map_subtract (*may_war_no_source,
--						     x_may_war_no_source);
--	*must_waw = isl_union_map_subtract (*must_waw, x_must_waw);
--	*may_waw = isl_union_map_subtract (*may_waw, x_may_waw);
--	*must_waw_no_source = isl_union_map_subtract (*must_waw_no_source,
--						      x_must_waw_no_source);
--	*may_waw_no_source = isl_union_map_subtract (*may_waw_no_source,
--						     x_may_waw_no_source);
-+	if (must_raw)
-+	  *must_raw = isl_union_map_subtract (*must_raw, x_must_raw);
-+	else
-+	  isl_union_map_free (x_must_raw);
-+
-+	if (may_raw)
-+	  *may_raw = isl_union_map_subtract (*may_raw, x_may_raw);
-+	else
-+	  isl_union_map_free (x_may_raw);
-+
-+	if (must_raw_no_source)
-+	  *must_raw_no_source = isl_union_map_subtract (*must_raw_no_source,
-+						        x_must_raw_no_source);
-+	else
-+	  isl_union_map_free (x_must_raw_no_source);
-+
-+	if (may_raw_no_source)
-+	  *may_raw_no_source = isl_union_map_subtract (*may_raw_no_source,
-+						       x_may_raw_no_source);
-+	else
-+	  isl_union_map_free (x_may_raw_no_source);
-+
-+	if (must_war)
-+	  *must_war = isl_union_map_subtract (*must_war, x_must_war);
-+	else
-+	  isl_union_map_free (x_must_war);
-+
-+	if (may_war)
-+	  *may_war = isl_union_map_subtract (*may_war, x_may_war);
-+	else
-+	  isl_union_map_free (x_may_war);
-+
-+	if (must_war_no_source)
-+	  *must_war_no_source = isl_union_map_subtract (*must_war_no_source,
-+						        x_must_war_no_source);
-+	else
-+	  isl_union_map_free (x_must_war_no_source);
-+
-+	if (may_war_no_source)
-+	  *may_war_no_source = isl_union_map_subtract (*may_war_no_source,
-+						       x_may_war_no_source);
-+	else
-+	  isl_union_map_free (x_may_war_no_source);
-+
-+	if (must_waw)
-+	  *must_waw = isl_union_map_subtract (*must_waw, x_must_waw);
-+	else
-+	  isl_union_map_free (x_must_waw);
-+
-+	if (may_waw)
-+	  *may_waw = isl_union_map_subtract (*may_waw, x_may_waw);
-+	else
-+	  isl_union_map_free (x_may_waw);
-+
-+	if (must_waw_no_source)
-+	  *must_waw_no_source = isl_union_map_subtract (*must_waw_no_source,
-+						        x_must_waw_no_source);
-+	else
-+	  isl_union_map_free (x_must_waw_no_source);
-+
-+	if (may_waw_no_source)
-+	  *may_waw_no_source = isl_union_map_subtract (*may_waw_no_source,
-+						       x_may_waw_no_source);
-+	else
-+	  isl_union_map_free (x_may_waw_no_source);
-       }
- 
-   isl_union_map_free (original);
diff --git a/debian/patches/pr60655-debug-loc.diff b/debian/patches/pr60655-debug-loc.diff
deleted file mode 100644
index c308c42..0000000
--- a/debian/patches/pr60655-debug-loc.diff
+++ /dev/null
@@ -1,153 +0,0 @@
-
-On Thu, Oct 16, 2014 at 09:07:58AM +0200, Jakub Jelinek wrote:
-> So, please find the spot where we forget to simplify stuff, and put the
-> simplification there.
-
-You were correct to be suspicious that we weren't simplifying as we
-should.  After more time in the debugger than I care to admit, I found
-the underlying cause.
-
-One of the var loc expressions is
-(plus:SI (plus:SI (not:SI (debug_expr:SI D#9))
-        (value/u:SI 58:4373 @0x18d3968/0x18ef230))
-    (debug_expr:SI D#5))
-
-which after substitution (in bb7) becomes
-(plus:SI (plus:SI (not:SI (plus:SI (reg:SI 5 5 [orig:212 D.2333 ] [212])
-                (const:SI (plus:SI (symbol_ref:SI ("*.LANCHOR0") [flags 0x182])
-                        (const_int -1 [0xffffffffffffffff])))))
-        (reg:SI 10 10 [orig:223 ivtmp.33 ] [223]))
-    (plus:SI (reg:SI 5 5 [orig:212 D.2333 ] [212])
-        (const:SI (plus:SI (symbol_ref:SI ("*.LANCHOR0") [flags 0x182])
-                (const_int 323 [0x143])))))
-
-The above has 8 ops by the time you turn ~x into -x - 1, and exceeds
-the allowed number of elements in the simplify_plus_minus ops array.
-Note that the ops array has 8 elements but the code only allows 7 to
-be entered, a bug since the "spare" element isn't a sentinal or used
-in any other way.
-
-This resulted in a partial simplification of the expression to
-(plus:SI (plus:SI (reg:SI 10 10 [orig:223 ivtmp.33 ] [223])
-        (symbol_ref:SI ("*.LANCHOR0") [flags 0x182]))
-    (const:SI (minus:SI (const_int 323 [0x143])
-            (symbol_ref:SI ("*.LANCHOR0") [flags 0x182]))))
-
-I also noticed another small bug in simplify_plus_minus.  n_constants
-ought to be the number of constants in ops, not the number of times
-we look at a constant.
-
-The "Handle CONST wrapped NOT, NEG and MINUS" in the previous patch
-seems to no longer be necessary, so I took that out (didn't hit the
-code in powerpc64-linux, powerpc-linux and x86_64-linux bootstrap and
-regression tests).
-
-Bootstrapped and regression tested powerpc64-linux and x86_64-linux.
-OK to apply?
-
-	PR debug/60655
-	* simplify-rtx.c (simplify_plus_minus): Delete unused "input_ops".
-	Increase "ops" array size.  Correct array size tests.  Init
-	n_constants in loop.  Break out of innermost loop when finding
-	a trivial CONST expression.
-
---- a/src/gcc/simplify-rtx.c
-+++ b/src/gcc/simplify-rtx.c
-@@ -3965,10 +3965,10 @@
- simplify_plus_minus (enum rtx_code code, enum machine_mode mode, rtx op0,
- 		     rtx op1)
- {
--  struct simplify_plus_minus_op_data ops[8];
-+  struct simplify_plus_minus_op_data ops[16];
-   rtx result, tem;
--  int n_ops = 2, input_ops = 2;
--  int changed, n_constants = 0, canonicalized = 0;
-+  int n_ops = 2;
-+  int changed, n_constants, canonicalized = 0;
-   int i, j;
- 
-   memset (ops, 0, sizeof ops);
-@@ -3985,6 +3985,7 @@
-   do
-     {
-       changed = 0;
-+      n_constants = 0;
- 
-       for (i = 0; i < n_ops; i++)
- 	{
-@@ -3996,7 +3997,7 @@
- 	    {
- 	    case PLUS:
- 	    case MINUS:
--	      if (n_ops == 7)
-+	      if (n_ops == ARRAY_SIZE (ops))
- 		return NULL_RTX;
- 
- 	      ops[n_ops].op = XEXP (this_op, 1);
-@@ -4004,7 +4005,6 @@
- 	      n_ops++;
- 
- 	      ops[i].op = XEXP (this_op, 0);
--	      input_ops++;
- 	      changed = 1;
- 	      canonicalized |= this_neg;
- 	      break;
-@@ -4017,7 +4017,7 @@
- 	      break;
- 
- 	    case CONST:
--	      if (n_ops < 7
-+	      if (n_ops != ARRAY_SIZE (ops)
- 		  && GET_CODE (XEXP (this_op, 0)) == PLUS
- 		  && CONSTANT_P (XEXP (XEXP (this_op, 0), 0))
- 		  && CONSTANT_P (XEXP (XEXP (this_op, 0), 1)))
-@@ -4033,7 +4033,7 @@
- 
- 	    case NOT:
- 	      /* ~a -> (-a - 1) */
--	      if (n_ops != 7)
-+	      if (n_ops != ARRAY_SIZE (ops))
- 		{
- 		  ops[n_ops].op = CONSTM1_RTX (mode);
- 		  ops[n_ops++].neg = this_neg;
-@@ -4097,7 +4097,7 @@
-   /* Now simplify each pair of operands until nothing changes.  */
-   do
-     {
--      /* Insertion sort is good enough for an eight-element array.  */
-+      /* Insertion sort is good enough for a small array.  */
-       for (i = 1; i < n_ops; i++)
-         {
-           struct simplify_plus_minus_op_data save;
-@@ -4148,16 +4148,21 @@
- 		else
- 		  tem = simplify_binary_operation (ncode, mode, lhs, rhs);
- 
--		/* Reject "simplifications" that just wrap the two
--		   arguments in a CONST.  Failure to do so can result
--		   in infinite recursion with simplify_binary_operation
--		   when it calls us to simplify CONST operations.  */
--		if (tem
--		    && ! (GET_CODE (tem) == CONST
--			  && GET_CODE (XEXP (tem, 0)) == ncode
--			  && XEXP (XEXP (tem, 0), 0) == lhs
--			  && XEXP (XEXP (tem, 0), 1) == rhs))
-+		if (tem)
- 		  {
-+		    /* Reject "simplifications" that just wrap the two
-+		       arguments in a CONST.  Failure to do so can result
-+		       in infinite recursion with simplify_binary_operation
-+		       when it calls us to simplify CONST operations.
-+		       Also, if we find such a simplification, don't try
-+		       any more combinations with this rhs:  We must have
-+		       something like symbol+offset, ie. one of the
-+		       trivial CONST expressions we handle later.  */
-+		    if (GET_CODE (tem) == CONST
-+			&& GET_CODE (XEXP (tem, 0)) == ncode
-+			&& XEXP (XEXP (tem, 0), 0) == lhs
-+			&& XEXP (XEXP (tem, 0), 1) == rhs)
-+		      break;
- 		    lneg &= rneg;
- 		    if (GET_CODE (tem) == NEG)
- 		      tem = XEXP (tem, 0), lneg = !lneg;
-
diff --git a/debian/patches/pr61046.diff b/debian/patches/pr61046.diff
deleted file mode 100644
index c5e9d22..0000000
--- a/debian/patches/pr61046.diff
+++ /dev/null
@@ -1,54 +0,0 @@
-# DP: Fix PR c++/61046, taken from the trunk.
-
-gcc/cp/
-
-2014-06-02  Jason Merrill  <jason@redhat.com>
-
-	PR c++/61046
-	* decl.c (reshape_init_class): Handle un-folded
-	constant-expressions.
-
-Index: b/src/gcc/testsuite/g++.dg/ext/desig7.C
-===================================================================
---- /dev/null
-+++ b/src/gcc/testsuite/g++.dg/ext/desig7.C
-@@ -0,0 +1,8 @@
-+// PR c++/61046
-+
-+struct A
-+{
-+  int ary[4];
-+};
-+const int i = 0;
-+A bar = { [i] = 0 }; // { dg-error "designated" }
-Index: b/src/gcc/cp/decl.c
-===================================================================
---- a/src/gcc/cp/decl.c
-+++ b/src/gcc/cp/decl.c
-@@ -5253,7 +5253,12 @@ reshape_init_class (tree type, reshape_i
- 	  if (d->cur->index == error_mark_node)
- 	    return error_mark_node;
- 
--	  if (TREE_CODE (d->cur->index) == INTEGER_CST)
-+	  if (TREE_CODE (d->cur->index) == FIELD_DECL)
-+	    /* We already reshaped this.  */
-+	    gcc_assert (d->cur->index == field);
-+	  else if (TREE_CODE (d->cur->index) == IDENTIFIER_NODE)
-+	    field = lookup_field_1 (type, d->cur->index, /*want_type=*/false);
-+	  else
- 	    {
- 	      if (complain & tf_error)
- 		error ("%<[%E] =%> used in a GNU-style designated initializer"
-@@ -5261,12 +5266,6 @@ reshape_init_class (tree type, reshape_i
- 	      return error_mark_node;
- 	    }
- 
--	  if (TREE_CODE (d->cur->index) == FIELD_DECL)
--	    /* We already reshaped this.  */
--	    gcc_assert (d->cur->index == field);
--	  else
--	    field = lookup_field_1 (type, d->cur->index, /*want_type=*/false);
--
- 	  if (!field || TREE_CODE (field) != FIELD_DECL)
- 	    {
- 	      if (complain & tf_error)
diff --git a/debian/patches/pr61257.diff b/debian/patches/pr61257.diff
deleted file mode 100644
index 91fefcb..0000000
--- a/debian/patches/pr61257.diff
+++ /dev/null
@@ -1,23 +0,0 @@
-# DP: Fix PR other/61257, check for working sys/sdt.h
-
-Index: b/src/gcc/configure.ac
-===================================================================
---- a/src/gcc/configure.ac
-+++ b/src/gcc/configure.ac
-@@ -5060,9 +5060,13 @@ GCC_TARGET_TEMPLATE([HAVE_SYS_SDT_H])
- AC_MSG_CHECKING(sys/sdt.h in the target C library)
- have_sys_sdt_h=no
- if test -f $target_header_dir/sys/sdt.h; then
--  have_sys_sdt_h=yes
--  AC_DEFINE(HAVE_SYS_SDT_H, 1,
--            [Define if your target C library provides sys/sdt.h])
-+  AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[#include <sys/sdt.h>]],
-+                                     [[DTRACE_PROBE(foo,bar); return 0;]])
-+                    ],[
-+                     have_sys_sdt_h=yes
-+                     AC_DEFINE(HAVE_SYS_SDT_H, 1,
-+                       [Define if your target C library provides sys/sdt.h])
-+                    ])
- fi
- AC_MSG_RESULT($have_sys_sdt_h)
- 
diff --git a/debian/patches/pr61294-doc.diff b/debian/patches/pr61294-doc.diff
deleted file mode 100644
index b997e3f..0000000
--- a/debian/patches/pr61294-doc.diff
+++ /dev/null
@@ -1,41 +0,0 @@
-# DP: PR middle-end/61294, -Wmemset-transposed-args (documentation)
-
-gcc/
-
-2014-07-14  Jakub Jelinek  <jakub@redhat.com>
-
-	PR middle-end/61294
-	* doc/invoke.texi (-Wmemset-transposed-args): Document.
-
---- a/src/gcc/doc/invoke.texi
-+++ b/src/gcc/doc/invoke.texi
-@@ -254,8 +254,8 @@
- -Wno-int-to-pointer-cast -Wno-invalid-offsetof @gol
- -Winvalid-pch -Wlarger-than=@var{len}  -Wunsafe-loop-optimizations @gol
- -Wlogical-op -Wlong-long @gol
---Wmain -Wmaybe-uninitialized -Wmissing-braces  -Wmissing-field-initializers @gol
---Wmissing-include-dirs @gol
-+-Wmain -Wmaybe-uninitialized -Wmemset-transposed-args -Wmissing-braces @gol
-+-Wmissing-field-initializers -Wmissing-include-dirs @gol
- -Wno-multichar  -Wnonnull  -Wno-overflow -Wopenmp-simd @gol
- -Woverlength-strings  -Wpacked  -Wpacked-bitfield-compat  -Wpadded @gol
- -Wparentheses  -Wpedantic-ms-format -Wno-pedantic-ms-format @gol
-@@ -4622,6 +4622,18 @@
- @code{memcpy (&foo, ptr, sizeof (&foo));}.  This warning is enabled by
- @option{-Wall}.
- 
-+@item -Wmemset-transposed-args
-+@opindex Wmemset-transposed-args
-+@opindex Wno-memset-transposed-args
-+Warn for suspicious calls to the @code{memset} built-in function, if the
-+second argument is not zero and the third argument is zero.  This warns e.g.@
-+about @code{memset (buf, sizeof buf, 0)} where most probably
-+@code{memset (buf, 0, sizeof buf)} was meant instead.  The diagnostics
-+is only emitted if the third argument is literal zero, if it is some expression
-+that is folded to zero, or e.g. a cast of zero to some type etc., it
-+is far less likely that user has mistakenly exchanged the arguments and
-+no warning is emitted.  This warning is enabled by @option{-Wall}.
-+
- @item -Waddress
- @opindex Waddress
- @opindex Wno-address
diff --git a/debian/patches/pr61294.diff b/debian/patches/pr61294.diff
deleted file mode 100644
index 58a5ff1..0000000
--- a/debian/patches/pr61294.diff
+++ /dev/null
@@ -1,460 +0,0 @@
-# DP: PR middle-end/61294, -Wmemset-transposed-args
-
-gcc/testsuite/
-
-2014-07-14  Jakub Jelinek  <jakub@redhat.com>
-
-	PR middle-end/61294
-	* c-c++-common/Wmemset-transposed-args1.c: New test.
-	* c-c++-common/Wmemset-transposed-args2.c: New test.
-	* g++.dg/warn/Wmemset-transposed-args-1.C: New test.
-
-gcc/c-family/
-
-2014-07-14  Jakub Jelinek  <jakub@redhat.com>
-
-	PR middle-end/61294
-	* c.opt (Wmemset-transposed-args): New warning.
-
-gcc/c/
-
-2014-07-14  Jakub Jelinek  <jakub@redhat.com>
-
-	PR middle-end/61294
-	* c-parser.c (c_parser_expr_list): Add new argument literal_zero_mask.
-	If non-NULL, call c_parser_check_literal_zero.
-	(c_parser_check_literal_zero): New function.
-	(c_parser_postfix_expression_after_primary): Adjust
-	c_parser_expr_list caller, handle -Wmemset-transposed-args.
-
-gcc/cp/
-
-2014-07-14  Jakub Jelinek  <jakub@redhat.com>
-
-	PR middle-end/61294
-	* cp-tree.h (LITERAL_ZERO_P): Define.
-	* parser.c (cp_parser_parenthesized_expression_list): Add
-	want_literal_zero_p argument, if true, for literal zeros
-	insert INTEGER_CSTs with LITERAL_ZERO_P flag set.
-	(cp_parser_postfix_expression): Adjust
-	cp_parser_parenthesized_expression_list caller, handle
-	-Wmemset-transposed-args.
-	(literal_zeros): New variable.
-
---- a/src/gcc/c/c-parser.c
-+++ b/src/gcc/c/c-parser.c
-@@ -1203,7 +1203,8 @@
- static struct c_expr c_parser_expression_conv (c_parser *);
- static vec<tree, va_gc> *c_parser_expr_list (c_parser *, bool, bool,
- 					     vec<tree, va_gc> **, location_t *,
--					     tree *, vec<location_t> *);
-+					     tree *, vec<location_t> *,
-+					     unsigned int * = NULL);
- static void c_parser_omp_construct (c_parser *);
- static void c_parser_omp_threadprivate (c_parser *);
- static void c_parser_omp_barrier (c_parser *);
-@@ -7625,6 +7626,7 @@
-   tree ident, idx;
-   location_t sizeof_arg_loc[3];
-   tree sizeof_arg[3];
-+  unsigned int literal_zero_mask;
-   unsigned int i;
-   vec<tree, va_gc> *exprlist;
-   vec<tree, va_gc> *origtypes = NULL;
-@@ -7679,12 +7681,13 @@
- 	      sizeof_arg[i] = NULL_TREE;
- 	      sizeof_arg_loc[i] = UNKNOWN_LOCATION;
- 	    }
-+	  literal_zero_mask = 0;
- 	  if (c_parser_next_token_is (parser, CPP_CLOSE_PAREN))
- 	    exprlist = NULL;
- 	  else
- 	    exprlist = c_parser_expr_list (parser, true, false, &origtypes,
- 					   sizeof_arg_loc, sizeof_arg,
--					   &arg_loc);
-+					   &arg_loc, &literal_zero_mask);
- 	  c_parser_skip_until_found (parser, CPP_CLOSE_PAREN,
- 				     "expected %<)%>");
- 	  orig_expr = expr;
-@@ -7694,6 +7697,19 @@
- 					      expr.value, exprlist,
- 					      sizeof_arg,
- 					      sizeof_ptr_memacc_comptypes);
-+	  if (warn_memset_transposed_args
-+	      && TREE_CODE (expr.value) == FUNCTION_DECL
-+	      && DECL_BUILT_IN_CLASS (expr.value) == BUILT_IN_NORMAL
-+	      && DECL_FUNCTION_CODE (expr.value) == BUILT_IN_MEMSET
-+	      && vec_safe_length (exprlist) == 3
-+	      && integer_zerop ((*exprlist)[2])
-+	      && (literal_zero_mask & (1 << 2)) != 0
-+	      && (!integer_zerop ((*exprlist)[1])
-+		  || (literal_zero_mask & (1 << 1)) == 0))
-+	    warning_at (expr_loc, OPT_Wmemset_transposed_args,
-+			"%<memset%> used with constant zero length parameter; "
-+			"this could be due to transposed parameters");
-+
- 	  expr.value
- 	    = c_build_function_call_vec (expr_loc, arg_loc, expr.value,
- 					 exprlist, origtypes);
-@@ -7861,6 +7877,36 @@
-   return expr;
- }
- 
-+/* Helper function of c_parser_expr_list.  Check if IDXth (0 based)
-+   argument is a literal zero alone and if so, set it in literal_zero_mask.  */
-+
-+static inline void
-+c_parser_check_literal_zero (c_parser *parser, unsigned *literal_zero_mask,
-+			     unsigned int idx)
-+{
-+  if (idx >= HOST_BITS_PER_INT)
-+    return;
-+
-+  c_token *tok = c_parser_peek_token (parser);
-+  switch (tok->type)
-+    {
-+    case CPP_NUMBER:
-+    case CPP_CHAR:
-+    case CPP_WCHAR:
-+    case CPP_CHAR16:
-+    case CPP_CHAR32:
-+      /* If a parameter is literal zero alone, remember it
-+	 for -Wmemset-transposed-args warning.  */
-+      if (integer_zerop (tok->value)
-+	  && !TREE_OVERFLOW (tok->value)
-+	  && (c_parser_peek_2nd_token (parser)->type == CPP_COMMA
-+	      || c_parser_peek_2nd_token (parser)->type == CPP_CLOSE_PAREN))
-+	*literal_zero_mask |= 1U << idx;
-+    default:
-+      break;
-+    }
-+}
-+
- /* Parse a non-empty list of expressions.  If CONVERT_P, convert
-    functions and arrays to pointers and lvalues to rvalues.  If
-    FOLD_P, fold the expressions.  If LOCATIONS is non-NULL, save the
-@@ -7875,7 +7921,8 @@
- c_parser_expr_list (c_parser *parser, bool convert_p, bool fold_p,
- 		    vec<tree, va_gc> **p_orig_types,
- 		    location_t *sizeof_arg_loc, tree *sizeof_arg,
--		    vec<location_t> *locations)
-+		    vec<location_t> *locations,
-+		    unsigned int *literal_zero_mask)
- {
-   vec<tree, va_gc> *ret;
-   vec<tree, va_gc> *orig_types;
-@@ -7893,6 +7940,8 @@
-   if (sizeof_arg != NULL
-       && c_parser_next_token_is_keyword (parser, RID_SIZEOF))
-     cur_sizeof_arg_loc = c_parser_peek_2nd_token (parser)->location;
-+  if (literal_zero_mask)
-+    c_parser_check_literal_zero (parser, literal_zero_mask, 0);
-   expr = c_parser_expr_no_commas (parser, NULL);
-   if (convert_p)
-     expr = convert_lvalue_to_rvalue (loc, expr, true, true);
-@@ -7919,6 +7968,8 @@
- 	cur_sizeof_arg_loc = c_parser_peek_2nd_token (parser)->location;
-       else
- 	cur_sizeof_arg_loc = UNKNOWN_LOCATION;
-+      if (literal_zero_mask)
-+	c_parser_check_literal_zero (parser, literal_zero_mask, idx + 1);
-       expr = c_parser_expr_no_commas (parser, NULL);
-       if (convert_p)
- 	expr = convert_lvalue_to_rvalue (loc, expr, true, true);
---- a/src/gcc/c-family/c.opt
-+++ b/src/gcc/c-family/c.opt
-@@ -494,6 +494,10 @@
- LangEnabledBy(C ObjC C++ ObjC++,Wpedantic, 2, 0)
- ;
- 
-+Wmemset-transposed-args
-+C ObjC C++ ObjC++ Var(warn_memset_transposed_args) Warning LangEnabledBy(C ObjC C++ ObjC++,Wall)
-+Warn about suspicious calls to memset where the third argument is constant literal zero and the second is not
-+
- Wmissing-braces
- C ObjC C++ ObjC++ Var(warn_missing_braces) Warning LangEnabledBy(C ObjC,Wall)
- Warn about possibly missing braces around initializers
---- a/src/gcc/cp/cp-tree.h
-+++ b/src/gcc/cp/cp-tree.h
-@@ -4172,6 +4172,10 @@
- #define SIZEOF_EXPR_TYPE_P(NODE) \
-   TREE_LANG_FLAG_0 (SIZEOF_EXPR_CHECK (NODE))
- 
-+/* True if INTEGER_CST is a zero literal seen in function argument list.  */
-+#define LITERAL_ZERO_P(NODE) \
-+  (INTEGER_CST_CHECK (NODE)->base.nothrow_flag)
-+
- /* An enumeration of the kind of tags that C++ accepts.  */
- enum tag_types {
-   none_type = 0, /* Not a tag type.  */
---- a/src/gcc/cp/parser.c
-+++ b/src/gcc/cp/parser.c
-@@ -1921,7 +1921,7 @@
- static tree cp_parser_postfix_dot_deref_expression
-   (cp_parser *, enum cpp_ttype, tree, bool, cp_id_kind *, location_t);
- static vec<tree, va_gc> *cp_parser_parenthesized_expression_list
--  (cp_parser *, int, bool, bool, bool *);
-+  (cp_parser *, int, bool, bool, bool *, bool = false);
- /* Values for the second parameter of cp_parser_parenthesized_expression_list.  */
- enum { non_attr = 0, normal_attr = 1, id_attr = 2 };
- static void cp_parser_pseudo_destructor_name
-@@ -6037,7 +6037,8 @@
- 	    args = (cp_parser_parenthesized_expression_list
- 		    (parser, non_attr,
- 		     /*cast_p=*/false, /*allow_expansion_p=*/true,
--		     /*non_constant_p=*/NULL));
-+		     /*non_constant_p=*/NULL,
-+		     /*want_literal_zero_p=*/warn_memset_transposed_args));
- 	    if (is_builtin_constant_p)
- 	      {
- 		parser->integral_constant_expression_p
-@@ -6105,6 +6106,30 @@
- 		  }
- 	      }
- 
-+	    if (warn_memset_transposed_args)
-+	      {
-+		if (TREE_CODE (postfix_expression) == FUNCTION_DECL
-+		    && DECL_BUILT_IN_CLASS (postfix_expression) == BUILT_IN_NORMAL
-+		    && DECL_FUNCTION_CODE (postfix_expression) == BUILT_IN_MEMSET
-+		    && vec_safe_length (args) == 3
-+		    && integer_zerop ((*args)[2])
-+		    && LITERAL_ZERO_P ((*args)[2])
-+		    && !(integer_zerop ((*args)[1])
-+			 && LITERAL_ZERO_P ((*args)[1])))
-+		  warning (OPT_Wmemset_transposed_args,
-+			   "%<memset%> used with constant zero length "
-+			   "parameter; this could be due to transposed "
-+			   "parameters");
-+
-+		/* Replace LITERAL_ZERO_P INTEGER_CSTs with normal ones
-+		   to avoid leaking those into folder and middle-end.  */
-+		unsigned int i;
-+		tree arg;
-+		FOR_EACH_VEC_SAFE_ELT (args, i, arg)
-+		  if (TREE_CODE (arg) == INTEGER_CST && LITERAL_ZERO_P (arg))
-+		    (*args)[i] = build_int_cst (TREE_TYPE (arg), 0);
-+	      }
-+
- 	    if (TREE_CODE (postfix_expression) == COMPONENT_REF)
- 	      {
- 		tree instance = TREE_OPERAND (postfix_expression, 0);
-@@ -6593,6 +6618,10 @@
-   return postfix_expression;
- }
- 
-+/* Cache of LITERAL_ZERO_P constants.  */
-+
-+static GTY(()) tree literal_zeros[itk_none];
-+
- /* Parse a parenthesized expression-list.
- 
-    expression-list:
-@@ -6617,7 +6646,10 @@
-    plain identifier argument, normal_attr for an attribute that wants
-    an expression, or non_attr if we aren't parsing an attribute list.  If
-    NON_CONSTANT_P is non-NULL, *NON_CONSTANT_P indicates whether or
--   not all of the expressions in the list were constant.  */
-+   not all of the expressions in the list were constant.
-+   WANT_LITERAL_ZERO_P is true if the caller is interested in
-+   LITERAL_ZERO_P INTEGER_CSTs.  FIXME: once we don't fold everything
-+   immediately, this can be removed.  */
- 
- static vec<tree, va_gc> *
- cp_parser_parenthesized_expression_list (cp_parser* parser,
-@@ -6624,7 +6656,8 @@
- 					 int is_attribute_list,
- 					 bool cast_p,
-                                          bool allow_expansion_p,
--					 bool *non_constant_p)
-+					 bool *non_constant_p,
-+					 bool want_literal_zero_p)
- {
-   vec<tree, va_gc> *expression_list;
-   bool fold_expr_p = is_attribute_list != non_attr;
-@@ -6687,7 +6720,50 @@
- 		  *non_constant_p = true;
- 	      }
- 	    else
--	      expr = cp_parser_assignment_expression (parser, cast_p, NULL);
-+	      {
-+		expr = NULL_TREE;
-+		cp_token *tok = cp_lexer_peek_token (parser->lexer);
-+		switch (tok->type)
-+		  {
-+		  case CPP_NUMBER:
-+		  case CPP_CHAR:
-+		  case CPP_WCHAR:
-+		  case CPP_CHAR16:
-+		  case CPP_CHAR32:
-+		    /* If a parameter is literal zero alone, remember it
-+		       for -Wmemset-transposed-args warning.  */
-+		    if (integer_zerop (tok->u.value)
-+			&& !TREE_OVERFLOW (tok->u.value)
-+			&& want_literal_zero_p
-+			&& (cp_lexer_peek_nth_token (parser->lexer, 2)->type
-+			    == CPP_COMMA
-+			    || cp_lexer_peek_nth_token (parser->lexer, 2)->type
-+			       == CPP_CLOSE_PAREN))
-+		      {
-+			unsigned int i;
-+			for (i = 0; i < itk_none; ++i)
-+			  if (TREE_TYPE (tok->u.value) == integer_types[i])
-+			    break;
-+			if (i < itk_none && literal_zeros[i])
-+			  expr = literal_zeros[i];
-+			else
-+			  {
-+			    expr = copy_node (tok->u.value);
-+			    LITERAL_ZERO_P (expr) = 1;
-+			    if (i < itk_none)
-+			      literal_zeros[i] = expr;
-+			  }
-+			/* Consume the 0 token (or '\0', 0LL etc.).  */
-+			cp_lexer_consume_token (parser->lexer);
-+		      }
-+		    break;
-+		  default:
-+		    break;
-+		  }
-+		if (expr == NULL_TREE)
-+		  expr = cp_parser_assignment_expression (parser, cast_p,
-+							  NULL);
-+	      }
- 
- 	    if (fold_expr_p)
- 	      expr = fold_non_dependent_expr (expr);
---- a/src/gcc/testsuite/c-c++-common/Wmemset-transposed-args1.c
-+++ b/src/gcc/testsuite/c-c++-common/Wmemset-transposed-args1.c
-@@ -0,0 +1,31 @@
-+/* { dg-do compile } */
-+/* { dg-options "-Wall" } */
-+
-+typedef __SIZE_TYPE__ size_t;
-+extern
-+#ifdef __cplusplus
-+"C"
-+#endif
-+void *memset (void *, int, size_t);
-+char buf[1024];
-+
-+void
-+foo ()
-+{
-+  memset (buf, sizeof buf, 0);	/* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  memset (buf, sizeof buf, '\0'); /* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  memset (buf, sizeof buf, L'\0'); /* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  memset (buf, 1, 1 - 1);
-+  memset (buf, 1, 0 - 0);
-+  memset (buf, 0, 0);
-+  memset (buf, '\0', 0);
-+  memset (buf, L'\0', 0);
-+  memset (buf, 1 - 1, 0); /* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  memset (buf, 0 - 0, 0); /* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  memset (buf, sizeof buf, 0L);	/* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  memset (buf, sizeof buf, 0UL); /* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  memset (buf, sizeof buf, 0LL); /* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  memset (buf, sizeof buf, 0ULL); /* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  memset (buf, sizeof buf, (int) 0);
-+  memset (buf, sizeof buf, -0);
-+}
---- a/src/gcc/testsuite/c-c++-common/Wmemset-transposed-args2.c
-+++ b/src/gcc/testsuite/c-c++-common/Wmemset-transposed-args2.c
-@@ -0,0 +1,20 @@
-+/* { dg-do compile { target { c || c++11 } } } */
-+/* { dg-options "-Wall" } */
-+/* { dg-additional-options "-std=gnu99" { target c } } */
-+
-+typedef __SIZE_TYPE__ size_t;
-+extern
-+#ifdef __cplusplus
-+"C"
-+#endif
-+void *memset (void *, int, size_t);
-+char buf[1024];
-+
-+void
-+foo ()
-+{
-+  memset (buf, sizeof buf, u'\0'); /* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  memset (buf, sizeof buf, U'\0'); /* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  memset (buf, u'\0', 0);
-+  memset (buf, U'\0', 0);
-+}
---- a/src/gcc/testsuite/g++.dg/warn/Wmemset-transposed-args-1.C
-+++ b/src/gcc/testsuite/g++.dg/warn/Wmemset-transposed-args-1.C
-@@ -0,0 +1,74 @@
-+// { dg-do compile }
-+// { dg-options "-Wall" }
-+
-+typedef __SIZE_TYPE__ size_t;
-+extern "C" void *memset (void *, int, size_t);
-+char buf[1024];
-+namespace std
-+{
-+  extern "C" void *memset (void *, int, size_t);
-+}
-+
-+template <int N>
-+void
-+foo ()
-+{
-+  memset (buf, sizeof buf, 0);	/* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  memset (buf, sizeof buf, '\0'); /* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  memset (buf, sizeof buf, L'\0'); /* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  memset (buf, sizeof buf, N);
-+  memset (buf, 1, 1 - 1);
-+  memset (buf, 1, 0 - 0);
-+  memset (buf, 1, N - N);
-+  memset (buf, 0, 0);
-+  memset (buf, 1 - 1, 0); /* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  memset (buf, 0 - 0, 0); /* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  memset (buf, sizeof buf, 0L);	/* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  memset (buf, sizeof buf, 0UL); /* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  memset (buf, sizeof buf, 0LL); /* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  memset (buf, sizeof buf, 0ULL); /* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  memset (buf, sizeof buf, (int) 0);
-+  memset (buf, sizeof buf, -0);
-+}
-+
-+template <int N>
-+void
-+baz ()
-+{
-+  std::memset (buf, sizeof buf, 0);	/* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  std::memset (buf, sizeof buf, '\0'); /* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  std::memset (buf, sizeof buf, L'\0'); /* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  std::memset (buf, sizeof buf, N);
-+  std::memset (buf, 1, 1 - 1);
-+  std::memset (buf, 1, 0 - 0);
-+  std::memset (buf, 1, N - N);
-+  std::memset (buf, 0, 0);
-+  std::memset (buf, 1 - 1, 0); /* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  std::memset (buf, 0 - 0, 0); /* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  std::memset (buf, sizeof buf, 0L);	/* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  std::memset (buf, sizeof buf, 0UL); /* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  std::memset (buf, sizeof buf, 0LL); /* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  std::memset (buf, sizeof buf, 0ULL); /* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  std::memset (buf, sizeof buf, (int) 0);
-+  std::memset (buf, sizeof buf, -0);
-+}
-+
-+void
-+bar ()
-+{
-+  foo<0> ();
-+  std::memset (buf, sizeof buf, 0);	/* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  std::memset (buf, sizeof buf, '\0'); /* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  std::memset (buf, sizeof buf, L'\0'); /* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  std::memset (buf, 1, 1 - 1);
-+  std::memset (buf, 1, 0 - 0);
-+  std::memset (buf, 0, 0);
-+  std::memset (buf, 1 - 1, 0); /* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  std::memset (buf, 0 - 0, 0); /* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  std::memset (buf, sizeof buf, 0L);	/* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  std::memset (buf, sizeof buf, 0UL); /* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  std::memset (buf, sizeof buf, 0LL); /* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  std::memset (buf, sizeof buf, 0ULL); /* { dg-warning ".memset. used with constant zero length parameter; this could be due to transposed parameters" } */
-+  std::memset (buf, sizeof buf, (int) 0);
-+  std::memset (buf, sizeof buf, -0);
-+}
diff --git a/debian/patches/pr61336.diff b/debian/patches/pr61336.diff
deleted file mode 100644
index 7e3e7ad..0000000
--- a/debian/patches/pr61336.diff
+++ /dev/null
@@ -1,40 +0,0 @@
-# DP: Fix PR target/61336, taken from the trunk.
-
-2014-06-02  Richard Henderson  <rth@redhat.com>
-
-	PR target/61336
-	* config/alpha/alpha.c (print_operand_address): Allow symbolic
-	addresses inside asms.  Use output_operand_lossage instead of
-	gcc_unreachable.
-
---- a/src/gcc/config/alpha/alpha.c
-+++ b/src/gcc/config/alpha/alpha.c
-@@ -5450,12 +5450,13 @@
-       offset = INTVAL (addr);
-       break;
- 
--#if TARGET_ABI_OPEN_VMS
-     case SYMBOL_REF:
-+      gcc_assert(TARGET_ABI_OPEN_VMS || this_is_asm_operands);
-       fprintf (file, "%s", XSTR (addr, 0));
-       return;
- 
-     case CONST:
-+      gcc_assert(TARGET_ABI_OPEN_VMS || this_is_asm_operands);
-       gcc_assert (GET_CODE (XEXP (addr, 0)) == PLUS
- 		  && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF);
-       fprintf (file, "%s+" HOST_WIDE_INT_PRINT_DEC,
-@@ -5462,10 +5463,10 @@
- 	       XSTR (XEXP (XEXP (addr, 0), 0), 0),
- 	       INTVAL (XEXP (XEXP (addr, 0), 1)));
-       return;
--    
--#endif
-+
-     default:
--      gcc_unreachable ();
-+      output_operand_lossage ("invalid operand address");
-+      return;
-     }
- 
-   fprintf (file, HOST_WIDE_INT_PRINT_DEC "($%d)", offset, basereg);
diff --git a/debian/patches/pr61841.diff b/debian/patches/pr61841.diff
deleted file mode 100644
index 64ae1db..0000000
--- a/debian/patches/pr61841.diff
+++ /dev/null
@@ -1,14 +0,0 @@
-# DP: Proposed backport for PR libstdc++/61841
-
---- a/src/libstdc++-v3/include/std/thread
-+++ b/src/libstdc++-v3/include/std/thread
-@@ -132,6 +132,9 @@
-       explicit 
-       thread(_Callable&& __f, _Args&&... __args)
-       {
-+#ifdef GTHR_ACTIVE_PROXY
-+	__asm ("" : : "r" (&pthread_create));
-+#endif
-         _M_start_thread(_M_make_routine(std::__bind_simple(
-                 std::forward<_Callable>(__f),
-                 std::forward<_Args>(__args)...)));
diff --git a/debian/patches/pr63751.diff b/debian/patches/pr63751.diff
deleted file mode 100644
index 38271fa..0000000
--- a/debian/patches/pr63751.diff
+++ /dev/null
@@ -1,50 +0,0 @@
-# DP: Fix PR c/61553 (ice on illegal code), backported from the trunk
-
-gcc/c-family/
-
-2014-06-23  Marek Polacek  <polacek@redhat.com>
-	    Andrew MacLeod  <amacleod@redhat.com>
-
-	PR c/61553
-	* c-common.c (get_atomic_generic_size): Don't segfault if the
-	type doesn't have a size.
- 
-gcc/testsuite/
-
-2014-06-23  Marek Polacek  <polacek@redhat.com>
-
-	PR c/61553
-	* c-c++-common/pr61553.c (foo): Add dg-error.
-
-2014-06-23  Marek Polacek  <polacek@redhat.com>
-
-	PR c/61553
-	* c-c++-common/pr61553.c: New test.
-
-Index: gcc/c-family/c-common.c
-===================================================================
---- a/src/gcc/c-family/c-common.c	(revision 211904)
-+++ a/src/gcc/c-family/c-common.c	(revision 211905)
-@@ -10471,7 +10471,8 @@
- 		    function);
- 	  return 0;
- 	}
--      size = tree_to_uhwi (TYPE_SIZE_UNIT (TREE_TYPE (type)));
-+      tree type_size = TYPE_SIZE_UNIT (TREE_TYPE (type));
-+      size = type_size ? tree_to_uhwi (type_size) : 0;
-       if (size != size_0)
- 	{
- 	  error_at (loc, "size mismatch in argument %d of %qE", x + 1,
-Index: gcc/testsuite/c-c++-common/pr61553.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/pr61553.c	(revision 0)
-+++ a/src/gcc/testsuite/c-c++-common/pr61553.c	(revision 211905)
-@@ -0,0 +1,8 @@
-+/* PR c/61553 */
-+/* { dg-do compile } */
-+
-+void
-+foo (char *s)
-+{
-+  __atomic_store (s, (void *) 0, __ATOMIC_SEQ_CST); /* { dg-error "size mismatch" } */
-+}
diff --git a/debian/patches/rename-info-files.diff b/debian/patches/rename-info-files.diff
index d7b4139..18af0fa 100644
--- a/debian/patches/rename-info-files.diff
+++ b/debian/patches/rename-info-files.diff
@@ -58,7 +58,7 @@ Index: b/src/gcc/fortran/Make-lang.in
  fortran.dvi: doc/gfortran.dvi doc/gfc-internals.dvi
  
  F95_HTMLFILES = $(build_htmldir)/gfortran
-@@ -186,10 +187,10 @@ GFORTRAN_TEXI = \
+@@ -181,10 +182,10 @@ GFORTRAN_TEXI = \
    $(srcdir)/doc/include/gcc-common.texi \
    gcc-vers.texi
  
@@ -71,7 +71,7 @@ Index: b/src/gcc/fortran/Make-lang.in
  	    -o $@ $<; \
  	else true; fi
  
-@@ -252,7 +253,7 @@ fortran.install-common: install-finclude
+@@ -249,7 +250,7 @@ fortran.install-common: install-finclude
  
  fortran.install-plugin:
  
@@ -80,7 +80,7 @@ Index: b/src/gcc/fortran/Make-lang.in
  
  fortran.install-man: $(DESTDIR)$(man1dir)/$(GFORTRAN_INSTALL_NAME)$(man1ext)
  
-@@ -270,7 +271,7 @@ fortran.uninstall:
+@@ -267,7 +268,7 @@ fortran.uninstall:
  	rm -rf $(DESTDIR)$(bindir)/$(GFORTRAN_INSTALL_NAME)$(exeext); \
  	rm -rf $(DESTDIR)$(man1dir)/$(GFORTRAN_INSTALL_NAME)$(man1ext); \
  	rm -rf $(DESTDIR)$(bindir)/$(GFORTRAN_TARGET_INSTALL_NAME)$(exeext); \
@@ -93,7 +93,7 @@ Index: b/src/gcc/Makefile.in
 ===================================================================
 --- a/src/gcc/Makefile.in
 +++ b/src/gcc/Makefile.in
-@@ -2781,8 +2781,31 @@ install-no-fixedincludes:
+@@ -2873,8 +2873,32 @@ install-no-fixedincludes:
  
  doc: $(BUILD_INFO) $(GENERATED_MANPAGES)
  
@@ -117,6 +117,7 @@ Index: b/src/gcc/Makefile.in
 +MAKEINFODEFS = -D 'fncpp $(INFO_CPP_NAME)' \
 +               -D 'fngcc $(INFO_GCC_NAME)' \
 +               -D 'fngcov $(INFO_GCC_NAME)' \
++               -D 'fngcovtool $(INFO_GCC_NAME)' \
 +               -D 'fngxx $(INFO_GXX_NAME)' \
 +               -D 'fngccint $(INFO_GCCINT_NAME)' \
 +               -D 'fngccinstall $(INFO_GCCINSTALL_NAME)' \
@@ -127,7 +128,7 @@ Index: b/src/gcc/Makefile.in
  
  info: $(INFOFILES) lang.info @GENINSRC@ srcinfo lang.srcinfo
  
-@@ -2829,7 +2852,19 @@ gcc-vers.texi: $(BASEVER) $(DEVPHASE)
+@@ -2921,7 +2945,19 @@ gcc-vers.texi: $(BASEVER) $(DEVPHASE)
  	if [ -n "$(PKGVERSION)" ]; then \
  	  echo "@set VERSION_PACKAGE $(PKGVERSION)" >> $@T; \
  	fi
@@ -148,7 +149,7 @@ Index: b/src/gcc/Makefile.in
  	mv -f $@T $@
  
  
-@@ -2837,21 +2872,41 @@ gcc-vers.texi: $(BASEVER) $(DEVPHASE)
+@@ -2929,21 +2965,41 @@ gcc-vers.texi: $(BASEVER) $(DEVPHASE)
  # patterns.  To use them, put each of the specific targets with its
  # specific dependencies but no build commands.
  
@@ -197,7 +198,7 @@ Index: b/src/gcc/Makefile.in
  			-I $(gcc_docdir)/include -o $@ $<; \
  	fi
  
-@@ -3229,11 +3284,11 @@ install-driver: installdirs xgcc$(exeext
+@@ -3339,11 +3395,11 @@ install-driver: installdirs xgcc$(exeext
  # $(INSTALL_DATA) might be a relative pathname, so we can't cd into srcdir
  # to do the install.
  install-info:: doc installdirs \
@@ -214,7 +215,15 @@ Index: b/src/gcc/Makefile.in
  	lang.install-info
  
  $(DESTDIR)$(infodir)/%.info: doc/%.info installdirs
-@@ -3440,8 +3495,11 @@ uninstall: lang.uninstall
+@@ -3397,6 +3453,7 @@ install-man: lang.install-man \
+ 	$(DESTDIR)$(man1dir)/$(GCC_INSTALL_NAME)$(man1ext) \
+ 	$(DESTDIR)$(man1dir)/$(CPP_INSTALL_NAME)$(man1ext) \
+ 	$(DESTDIR)$(man1dir)/$(GCOV_INSTALL_NAME)$(man1ext) \
++	$(DESTDIR)$(man1dir)/$(GCOV_TOOL_INSTALL_NAME)$(man1ext) \
+ 	$(DESTDIR)$(man7dir)/fsf-funding$(man7ext) \
+ 	$(DESTDIR)$(man7dir)/gfdl$(man7ext) \
+ 	$(DESTDIR)$(man7dir)/gpl$(man7ext)
+@@ -3557,8 +3614,11 @@ uninstall: lang.uninstall
  	-rm -rf $(DESTDIR)$(bindir)/$(GCOV_INSTALL_NAME)$(exeext)
  	-rm -rf $(DESTDIR)$(man1dir)/$(GCC_INSTALL_NAME)$(man1ext)
  	-rm -rf $(DESTDIR)$(man1dir)/cpp$(man1ext)
@@ -325,7 +334,7 @@ Index: b/src/gcc/ada/gnat-style.texi
  @dircategory Software development
  @direntry
 -* gnat-style: (gnat-style).      GNAT Coding Style
-+* gnat-style: (gnat-style-4.9).      GNAT Coding Style
++* gnat-style: (gnat-style-5).      GNAT Coding Style
  @end direntry
  
  @macro syntax{element}
@@ -338,7 +347,7 @@ Index: b/src/gcc/ada/gnat_rm.texi
  @dircategory GNU Ada tools
  @direntry
 -* GNAT Reference Manual: (gnat_rm).  Reference Manual for GNU Ada tools.
-+* GNAT Reference Manual: (gnat_rm-4.9).  Reference Manual for GNU Ada tools.
++* GNAT Reference Manual: (gnat_rm-5).  Reference Manual for GNU Ada tools.
  @end direntry
  
  @titlepage
@@ -346,7 +355,7 @@ Index: b/src/gcc/doc/invoke.texi
 ===================================================================
 --- a/src/gcc/doc/invoke.texi
 +++ b/src/gcc/doc/invoke.texi
-@@ -10319,7 +10319,7 @@ One of the standard libraries bypassed b
+@@ -10968,7 +10968,7 @@ One of the standard libraries bypassed b
  @option{-nodefaultlibs} is @file{libgcc.a}, a library of internal subroutines
  which GCC uses to overcome shortcomings of particular machines, or special
  needs for some languages.
@@ -355,16 +364,16 @@ Index: b/src/gcc/doc/invoke.texi
  Collection (GCC) Internals},
  for more discussion of @file{libgcc.a}.)
  In most cases, you need @file{libgcc.a} even when you want to avoid
-@@ -10328,7 +10328,7 @@ or @option{-nodefaultlibs} you should us
+@@ -10977,7 +10977,7 @@ or @option{-nodefaultlibs} you should us
  This ensures that you have no unresolved references to internal GCC
  library subroutines.
- (An example of such an internal subroutine is @samp{__main}, used to ensure C++
+ (An example of such an internal subroutine is @code{__main}, used to ensure C++
 -constructors are called; @pxref{Collect2,,@code{collect2}, gccint,
 +constructors are called; @pxref{Collect2,,@code{collect2}, @value{fngccint},
  GNU Compiler Collection (GCC) Internals}.)
  
  @item -pie
-@@ -22609,7 +22609,7 @@ Note that you can also specify places to
+@@ -23683,7 +23683,7 @@ Note that you can also specify places to
  @option{-B}, @option{-I} and @option{-L} (@pxref{Directory Options}).  These
  take precedence over places specified using environment variables, which
  in turn take precedence over those specified by the configuration of GCC@.
@@ -373,7 +382,7 @@ Index: b/src/gcc/doc/invoke.texi
  GNU Compiler Collection (GCC) Internals}.
  
  @table @env
-@@ -22769,7 +22769,7 @@ the headers it contains change.
+@@ -23843,7 +23843,7 @@ the headers it contains change.
  
  A precompiled header file is searched for when @code{#include} is
  seen in the compilation.  As it searches for the included file
@@ -386,7 +395,7 @@ Index: b/src/gcc/doc/extend.texi
 ===================================================================
 --- a/src/gcc/doc/extend.texi
 +++ b/src/gcc/doc/extend.texi
-@@ -17106,7 +17106,7 @@ want to write code that checks whether t
+@@ -18256,7 +18256,7 @@ want to write code that checks whether t
  test for the GNU compiler the same way as for C programs: check for a
  predefined macro @code{__GNUC__}.  You can also use @code{__GNUG__} to
  test specifically for GNU C++ (@pxref{Common Predefined Macros,,
@@ -462,20 +471,22 @@ Index: b/src/gcc/doc/gcc.texi
 ===================================================================
 --- a/src/gcc/doc/gcc.texi
 +++ b/src/gcc/doc/gcc.texi
-@@ -63,9 +63,9 @@ Texts being (a) (see below), and with th
+@@ -63,10 +63,10 @@ Texts being (a) (see below), and with th
  @ifnottex
  @dircategory Software development
  @direntry
 -* gcc: (gcc).                  The GNU Compiler Collection.
 -* g++: (gcc).                  The GNU C++ compiler.
 -* gcov: (gcc) Gcov.            @command{gcov}---a test coverage program.
+-* gcov-tool: (gcc) Gcov-tool.  @command{gcov-tool}---an offline gcda profile processing program.
 +* @value{fngcc}: (@value{fngcc}).                  The GNU Compiler Collection.
 +* @value{fngxx}: (@value{fngcc}).                  The GNU C++ compiler.
 +* @value{fngcov}: (@value{fngcc}) Gcov.            @command{gcov}---a test coverage program.
++* @value{fngcovtool}: (@value{fngcc}) Gcov.            @command{gcov-tool}---an offline gcda profile processing program.
  @end direntry
  This file documents the use of the GNU compilers.
  @sp 1
-@@ -125,7 +125,7 @@ version @value{version-GCC}.
+@@ -126,7 +126,7 @@ version @value{version-GCC}.
  The internals of the GNU compilers, including how to port them to new
  targets and some information about how to write front ends for new
  languages, are documented in a separate manual.  @xref{Top,,
@@ -531,16 +542,16 @@ Index: b/src/libgomp/libgomp.texi
  @ifinfo
  @dircategory GNU Libraries
  @direntry
--* libgomp: (libgomp).                    GNU OpenMP runtime library
-+* @value{fnlibgomp}: (@value{fnlibgomp}).                    GNU OpenMP runtime library
+-* libgomp: (libgomp).          GNU Offloading and Multi Processing Runtime Library.
++* @value{fnlibgomp}: (@value{fnlibgomp}).          GNU Offloading and Multi Processing Runtime Library.
  @end direntry
  
- This manual documents the GNU implementation of the OpenMP API for 
+ This manual documents libgomp, the GNU Offloading and Multi Processing
 Index: b/src/libgomp/Makefile.in
 ===================================================================
 --- a/src/libgomp/Makefile.in
 +++ b/src/libgomp/Makefile.in
-@@ -345,7 +345,8 @@ info_TEXINFOS = libgomp.texi
+@@ -445,7 +445,8 @@ info_TEXINFOS = libgomp.texi
  
  # AM_CONDITIONAL on configure check ACX_CHECK_PROG_VER([MAKEINFO])
  @BUILD_INFO_TRUE@STAMP_BUILD_INFO = stamp-build-info
@@ -550,7 +561,7 @@ Index: b/src/libgomp/Makefile.in
  MAINTAINERCLEANFILES = $(srcdir)/libgomp.info
  all: config.h
  	$(MAKE) $(AM_MAKEFLAGS) all-recursive
-@@ -1093,15 +1094,16 @@ env.lo: libgomp_f.h
+@@ -1235,15 +1236,16 @@ env.lo: libgomp_f.h
  env.o: libgomp_f.h
  
  all-local: $(STAMP_GENINSRC)
@@ -576,7 +587,7 @@ Index: b/src/libgomp/Makefile.am
 ===================================================================
 --- a/src/libgomp/Makefile.am
 +++ b/src/libgomp/Makefile.am
-@@ -111,16 +111,19 @@ endif
+@@ -125,16 +125,19 @@ endif
  
  all-local: $(STAMP_GENINSRC)
  
@@ -670,7 +681,7 @@ Index: b/src/gcc/go/Make-lang.in
 ===================================================================
 --- a/src/gcc/go/Make-lang.in
 +++ b/src/gcc/go/Make-lang.in
-@@ -86,10 +86,11 @@ GO_TEXI_FILES = \
+@@ -85,10 +85,11 @@ GO_TEXI_FILES = \
  	$(gcc_docdir)/include/gcc-common.texi \
  	gcc-vers.texi
  
@@ -685,7 +696,7 @@ Index: b/src/gcc/go/Make-lang.in
  		-I $(gcc_docdir)/include -o $@ $<; \
  	else true; fi
  
-@@ -115,7 +116,7 @@ gccgo.pod: go/gccgo.texi
+@@ -114,7 +115,7 @@ gccgo.pod: go/gccgo.texi
  go.all.cross: gccgo-cross$(exeext)
  go.start.encap: gccgo$(exeext)
  go.rest.encap:
@@ -694,7 +705,7 @@ Index: b/src/gcc/go/Make-lang.in
  go.dvi: doc/gccgo.dvi
  go.pdf: doc/gccgo.pdf
  go.html: $(build_htmldir)/go/index.html
-@@ -155,7 +156,7 @@ go.install-common: installdirs
+@@ -150,7 +151,7 @@ go.install-common: installdirs
  
  go.install-plugin:
  
@@ -703,7 +714,7 @@ Index: b/src/gcc/go/Make-lang.in
  
  go.install-pdf: doc/gccgo.pdf
  	@$(NORMAL_INSTALL)
-@@ -195,7 +196,7 @@ go.uninstall:
+@@ -190,7 +191,7 @@ go.uninstall:
  	rm -rf $(DESTDIR)$(bindir)/$(GCCGO_INSTALL_NAME)$(exeext)
  	rm -rf $(DESTDIR)$(man1dir)/$(GCCGO_INSTALL_NAME)$(man1ext)
  	rm -rf $(DESTDIR)$(bindir)/$(GCCGO_TARGET_INSTALL_NAME)$(exeext)
@@ -807,7 +818,7 @@ Index: b/src/libquadmath/Makefile.in
  
  # Automake Documentation:
  # If your package has Texinfo files in many directories, you can use the
-@@ -1465,17 +1466,17 @@ uninstall-am: uninstall-dvi-am uninstall
+@@ -1466,17 +1467,17 @@ uninstall-am: uninstall-dvi-am uninstall
  
  @BUILD_LIBQUADMATH_TRUE@all-local: $(STAMP_GENINSRC)
  
diff --git a/debian/patches/sparc-force-cpu.diff b/debian/patches/sparc-force-cpu.diff
index b8916f1..ff1ec1a 100644
--- a/debian/patches/sparc-force-cpu.diff
+++ b/debian/patches/sparc-force-cpu.diff
@@ -4,7 +4,7 @@ Index: b/src/gcc/config.gcc
 ===================================================================
 --- a/src/gcc/config.gcc
 +++ b/src/gcc/config.gcc
-@@ -4200,6 +4200,20 @@
+@@ -4342,6 +4342,20 @@ do
  			;;
  		esac
  
diff --git a/debian/patches/sparc64-biarch-long-double-128.diff b/debian/patches/sparc64-biarch-long-double-128.diff
index 5173d1b..8cf8e2d 100644
--- a/debian/patches/sparc64-biarch-long-double-128.diff
+++ b/debian/patches/sparc64-biarch-long-double-128.diff
@@ -17,9 +17,11 @@ Changelog gcc/
 	* config/sparc/linux64.h (CC1_SPEC): When defaulting to 64-bit,
 	don't force -mlong-double-64 when -m32 or -mv8plus is given.
 
+Index: b/src/gcc/config/sparc/linux64.h
+===================================================================
 --- a/src/gcc/config/sparc/linux64.h
-+++ b/gcc/config/sparc/linux64.h
-@@ -162,9 +162,9 @@
++++ b/src/gcc/config/sparc/linux64.h
+@@ -154,9 +154,9 @@ extern const char *host_detect_local_cpu
  #else
  #define CC1_SPEC "%{profile:-p} \
  %{m32:%{m64:%emay not use both -m32 and -m64}} \
@@ -31,4 +33,3 @@ Changelog gcc/
    %{!mcpu*:-mcpu=v9}} \
  %{!m32:%{!mcpu*:-mcpu=ultrasparc}} \
  %{!mno-vis:%{!m32:%{!mcpu=v9:-mvis}}} \
-
diff --git a/debian/patches/svn-doc-updates.diff b/debian/patches/svn-doc-updates.diff
index f3c814d..2f92e80 100644
--- a/debian/patches/svn-doc-updates.diff
+++ b/debian/patches/svn-doc-updates.diff
@@ -1,6 +1,6 @@
-# DP: updates from the 4.9 branch upto 20140910 (documentation).
+# DP: updates from the 5 branch upto 2015xxyy (documentation).
 
-svn diff svn://gcc.gnu.org/svn/gcc/tags/gcc_4_9_2_release svn://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch \
+svn diff svn://gcc.gnu.org/svn/gcc/tags/gcc_5_1_0_release svn://gcc.gnu.org/svn/gcc/branches/gcc-5-branch \
 	| sed -r 's,^--- (\S+)\t(\S+)(.*)$,--- a/src/\1\t\2,;s,^\+\+\+ (\S+)\t(\S+)(.*)$,+++ b/src/\1\t\2,' \
 	| awk '/^Index:.*\.texi/ {skip=0; print; next} /^Index:/ {skip=1; next} skip==0'
 
diff --git a/debian/patches/svn-updates.diff b/debian/patches/svn-updates.diff
index e3e8252..d37888c 100644
--- a/debian/patches/svn-updates.diff
+++ b/debian/patches/svn-updates.diff
@@ -1,4 +1,4 @@
-# DP: updates from the 4.9 branch upto 20150120 (r219885).
+# DP: updates from the 5 branch upto 2015xxyy (r219885).
 
 last_update()
 {
@@ -8,12572 +8,7 @@ Tue Jan 20 11:43:44 UTC 2015 (revision 219885)
 EOF
 }
 
-LANG=C svn diff svn://gcc.gnu.org/svn/gcc/tags/gcc_4_9_2_release svn://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch \
+LANG=C svn diff svn://gcc.gnu.org/svn/gcc/tags/gcc_5_1_0_release svn://gcc.gnu.org/svn/gcc/branches/gcc-5-branch \
 	| sed -r 's,^--- (\S+)\t(\S+)(.*)$,--- a/src/\1\t\2,;s,^\+\+\+ (\S+)\t(\S+)(.*)$,+++ b/src/\1\t\2,' \
 	| awk '/^Index:.*\.(class|texi)/ {skip=1; next} /^Index:/ { skip=0 } skip==0'
 
-Index: libitm/configure.tgt
-===================================================================
---- a/src/libitm/configure.tgt	(.../tags/gcc_4_9_2_release)
-+++ b/src/libitm/configure.tgt	(.../branches/gcc-4_9-branch)
-@@ -102,7 +102,7 @@
-   x86_64)
- 	case " ${CC} ${CFLAGS} " in
- 	  *" -m32 "*)
--	    XCFLAGS="${XCFLAGS} -march=i486 -mtune=i686"
-+	    XCFLAGS="${XCFLAGS} -march=i486 -mtune=generic"
- 	    XCFLAGS="${XCFLAGS} -fomit-frame-pointer"
- 	    ;;
- 	esac
-Index: libitm/ChangeLog
-===================================================================
---- a/src/libitm/ChangeLog	(.../tags/gcc_4_9_2_release)
-+++ b/src/libitm/ChangeLog	(.../branches/gcc-4_9-branch)
-@@ -1,3 +1,7 @@
-+2014-12-03  Uros Bizjak  <ubizjak@gmail.com>
-+
-+	* configure.tgt (x86_64): Tune -m32 multilib to generic.
-+
- 2014-10-30  Release Manager
- 
- 	* GCC 4.9.2 released.
-Index: Makefile.in
-===================================================================
---- a/src/Makefile.in	(.../tags/gcc_4_9_2_release)
-+++ b/src/Makefile.in	(.../branches/gcc-4_9-branch)
-@@ -46988,6 +46988,38 @@
- configure-stage4-gcc: maybe-all-stage4-gmp
- configure-stageprofile-gcc: maybe-all-stageprofile-gmp
- configure-stagefeedback-gcc: maybe-all-stagefeedback-gmp
-+configure-gcc: maybe-all-mpfr
-+
-+configure-stage1-gcc: maybe-all-stage1-mpfr
-+configure-stage2-gcc: maybe-all-stage2-mpfr
-+configure-stage3-gcc: maybe-all-stage3-mpfr
-+configure-stage4-gcc: maybe-all-stage4-mpfr
-+configure-stageprofile-gcc: maybe-all-stageprofile-mpfr
-+configure-stagefeedback-gcc: maybe-all-stagefeedback-mpfr
-+configure-gcc: maybe-all-mpc
-+
-+configure-stage1-gcc: maybe-all-stage1-mpc
-+configure-stage2-gcc: maybe-all-stage2-mpc
-+configure-stage3-gcc: maybe-all-stage3-mpc
-+configure-stage4-gcc: maybe-all-stage4-mpc
-+configure-stageprofile-gcc: maybe-all-stageprofile-mpc
-+configure-stagefeedback-gcc: maybe-all-stagefeedback-mpc
-+configure-gcc: maybe-all-isl
-+
-+configure-stage1-gcc: maybe-all-stage1-isl
-+configure-stage2-gcc: maybe-all-stage2-isl
-+configure-stage3-gcc: maybe-all-stage3-isl
-+configure-stage4-gcc: maybe-all-stage4-isl
-+configure-stageprofile-gcc: maybe-all-stageprofile-isl
-+configure-stagefeedback-gcc: maybe-all-stagefeedback-isl
-+configure-gcc: maybe-all-cloog
-+
-+configure-stage1-gcc: maybe-all-stage1-cloog
-+configure-stage2-gcc: maybe-all-stage2-cloog
-+configure-stage3-gcc: maybe-all-stage3-cloog
-+configure-stage4-gcc: maybe-all-stage4-cloog
-+configure-stageprofile-gcc: maybe-all-stageprofile-cloog
-+configure-stagefeedback-gcc: maybe-all-stagefeedback-cloog
- configure-gcc: maybe-all-lto-plugin
- 
- configure-stage1-gcc: maybe-all-stage1-lto-plugin
-Index: libgomp/configure.tgt
-===================================================================
---- a/src/libgomp/configure.tgt	(.../tags/gcc_4_9_2_release)
-+++ b/src/libgomp/configure.tgt	(.../branches/gcc-4_9-branch)
-@@ -82,7 +82,7 @@
- 	config_path="linux/x86 linux posix"
- 	case " ${CC} ${CFLAGS} " in
- 	  *" -m32 "*)
--	    XCFLAGS="${XCFLAGS} -march=i486 -mtune=i686"
-+	    XCFLAGS="${XCFLAGS} -march=i486 -mtune=generic"
- 	    ;;
- 	esac
- 	;;
-Index: libgomp/ChangeLog
-===================================================================
---- a/src/libgomp/ChangeLog	(.../tags/gcc_4_9_2_release)
-+++ b/src/libgomp/ChangeLog	(.../branches/gcc-4_9-branch)
-@@ -1,3 +1,16 @@
-+2014-12-03  Uros Bizjak  <ubizjak@gmail.com>
-+
-+	* configure.tgt (x86_64-*-linux*): Tune -m32 multilib to generic.
-+
-+2014-11-28  Jakub Jelinek  <jakub@redhat.com>
-+
-+	Backported from mainline
-+	2014-11-24  Jakub Jelinek  <jakub@redhat.com>
-+
-+	PR fortran/63938
-+	* libgomp.fortran/pr63938-1.f90: New test.
-+	* libgomp.fortran/pr63938-2.f90: New test.
-+
- 2014-10-30  Release Manager
- 
- 	* GCC 4.9.2 released.
-Index: libgomp/testsuite/libgomp.fortran/pr63938-1.f90
-===================================================================
---- a/src/libgomp/testsuite/libgomp.fortran/pr63938-1.f90	(.../tags/gcc_4_9_2_release)
-+++ b/src/libgomp/testsuite/libgomp.fortran/pr63938-1.f90	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,14 @@
-+! PR fortran/63938
-+! { dg-do run }
-+
-+program pr63938_1
-+  integer :: i, x(1)
-+  x(1) = 0
-+!$omp parallel do
-+  do i = 1, 1000
-+    !$omp atomic
-+    x(1) = x(1) + 1
-+  end do
-+!$omp end parallel do
-+  if (x(1) .ne. 1000) call abort
-+end program pr63938_1
-Index: libgomp/testsuite/libgomp.fortran/pr63938-2.f90
-===================================================================
---- a/src/libgomp/testsuite/libgomp.fortran/pr63938-2.f90	(.../tags/gcc_4_9_2_release)
-+++ b/src/libgomp/testsuite/libgomp.fortran/pr63938-2.f90	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,18 @@
-+! PR fortran/63938
-+! { dg-do run }
-+
-+program pr63938_2
-+  type t
-+    integer :: x
-+  end type
-+  integer :: i
-+  type(t) :: x
-+  x%x = 0
-+!$omp parallel do
-+  do i = 1, 1000
-+    !$omp atomic
-+    x%x = x%x + 1
-+  end do
-+!$omp end parallel do
-+  if (x%x .ne. 1000) call abort
-+end program pr63938_2
-Index: libstdc++-v3/configure.host
-===================================================================
---- a/src/libstdc++-v3/configure.host	(.../tags/gcc_4_9_2_release)
-+++ b/src/libstdc++-v3/configure.host	(.../branches/gcc-4_9-branch)
-@@ -219,7 +219,6 @@
-     os_include_dir="os/aix"
-     atomicity_dir="os/aix"
-     atomic_word_dir="os/aix"
--    OPT_LDFLAGS="-Wl,-G"
-     ;;
-   aix4.*)
-     os_include_dir="os/generic"
-Index: libstdc++-v3/include/std/shared_mutex
-===================================================================
---- a/src/libstdc++-v3/include/std/shared_mutex	(.../tags/gcc_4_9_2_release)
-+++ b/src/libstdc++-v3/include/std/shared_mutex	(.../branches/gcc-4_9-branch)
-@@ -36,10 +36,8 @@
- #else
- 
- #include <bits/c++config.h>
--#if defined(_GLIBCXX_HAS_GTHREADS) && defined(_GLIBCXX_USE_C99_STDINT_TR1)
--# include <mutex>
--# include <condition_variable>
--#endif
-+#include <mutex>
-+#include <condition_variable>
- #include <bits/functexcept.h>
- 
- namespace std _GLIBCXX_VISIBILITY(default)
-@@ -51,7 +49,8 @@
-    * @{
-    */
- 
--#if defined(_GLIBCXX_HAS_GTHREADS) && defined(_GLIBCXX_USE_C99_STDINT_TR1)
-+#ifdef _GLIBCXX_USE_C99_STDINT_TR1
-+#ifdef _GLIBCXX_HAS_GTHREADS
- 
- #define __cpp_lib_shared_timed_mutex 201402
- 
-@@ -254,7 +253,7 @@
- 	}
-     }
-   };
--#endif // _GLIBCXX_HAS_GTHREADS && _GLIBCXX_USE_C99_STDINT_TR1
-+#endif // _GLIBCXX_HAS_GTHREADS
- 
-   /// shared_lock
-   template<typename _Mutex>
-@@ -393,6 +392,8 @@
-     swap(shared_lock<_Mutex>& __x, shared_lock<_Mutex>& __y) noexcept
-     { __x.swap(__y); }
- 
-+#endif // _GLIBCXX_USE_C99_STDINT_TR1
-+
-   // @} group mutexes
- _GLIBCXX_END_NAMESPACE_VERSION
- } // namespace
-Index: libstdc++-v3/include/std/tuple
-===================================================================
---- a/src/libstdc++-v3/include/std/tuple	(.../tags/gcc_4_9_2_release)
-+++ b/src/libstdc++-v3/include/std/tuple	(.../branches/gcc-4_9-branch)
-@@ -88,21 +88,22 @@
-       constexpr _Head_base(const _Head& __h)
-       : _Head(__h) { }
- 
--      template<typename _UHead, typename = typename
--	       enable_if<!is_convertible<_UHead,
--	                                 __uses_alloc_base>::value>::type>
-+      constexpr _Head_base(const _Head_base&) = default;
-+      constexpr _Head_base(_Head_base&&) = default;
-+
-+      template<typename _UHead>
-         constexpr _Head_base(_UHead&& __h)
- 	: _Head(std::forward<_UHead>(__h)) { }
- 
--      _Head_base(__uses_alloc0)
-+      _Head_base(allocator_arg_t, __uses_alloc0)
-       : _Head() { }
- 
-       template<typename _Alloc>
--	_Head_base(__uses_alloc1<_Alloc> __a)
-+	_Head_base(allocator_arg_t, __uses_alloc1<_Alloc> __a)
- 	: _Head(allocator_arg, *__a._M_a) { }
- 
-       template<typename _Alloc>
--	_Head_base(__uses_alloc2<_Alloc> __a)
-+	_Head_base(allocator_arg_t, __uses_alloc2<_Alloc> __a)
- 	: _Head(*__a._M_a) { }
- 
-       template<typename _UHead>
-@@ -133,21 +134,22 @@
-       constexpr _Head_base(const _Head& __h)
-       : _M_head_impl(__h) { }
- 
--      template<typename _UHead, typename = typename
--	       enable_if<!is_convertible<_UHead,
--	                                 __uses_alloc_base>::value>::type>
-+      constexpr _Head_base(const _Head_base&) = default;
-+      constexpr _Head_base(_Head_base&&) = default;
-+
-+      template<typename _UHead>
-         constexpr _Head_base(_UHead&& __h)
- 	: _M_head_impl(std::forward<_UHead>(__h)) { }
- 
--      _Head_base(__uses_alloc0)
-+      _Head_base(allocator_arg_t, __uses_alloc0)
-       : _M_head_impl() { }
- 
-       template<typename _Alloc>
--	_Head_base(__uses_alloc1<_Alloc> __a)
-+	_Head_base(allocator_arg_t, __uses_alloc1<_Alloc> __a)
- 	: _M_head_impl(allocator_arg, *__a._M_a) { }
- 
-       template<typename _Alloc>
--	_Head_base(__uses_alloc2<_Alloc> __a)
-+	_Head_base(allocator_arg_t, __uses_alloc2<_Alloc> __a)
- 	: _M_head_impl(*__a._M_a) { }
- 
-       template<typename _UHead>
-@@ -285,7 +287,7 @@
-       template<typename _Alloc>
- 	_Tuple_impl(allocator_arg_t __tag, const _Alloc& __a)
- 	: _Inherited(__tag, __a),
--          _Base(__use_alloc<_Head>(__a)) { }
-+          _Base(__tag, __use_alloc<_Head>(__a)) { }
- 
-       template<typename _Alloc>
- 	_Tuple_impl(allocator_arg_t __tag, const _Alloc& __a,
-Index: libstdc++-v3/include/std/future
-===================================================================
---- a/src/libstdc++-v3/include/std/future	(.../tags/gcc_4_9_2_release)
-+++ b/src/libstdc++-v3/include/std/future	(.../branches/gcc-4_9-branch)
-@@ -1450,7 +1450,8 @@
-       operator()(_ArgTypes... __args)
-       {
- 	__future_base::_State_base::_S_check(_M_state);
--	_M_state->_M_run(std::forward<_ArgTypes>(__args)...);
-+	auto __state = _M_state;
-+	__state->_M_run(std::forward<_ArgTypes>(__args)...);
-       }
- 
-       void
-Index: libstdc++-v3/include/std/functional
-===================================================================
---- a/src/libstdc++-v3/include/std/functional	(.../tags/gcc_4_9_2_release)
-+++ b/src/libstdc++-v3/include/std/functional	(.../branches/gcc-4_9-branch)
-@@ -2407,9 +2407,9 @@
-     {
-       if (static_cast<bool>(__x))
- 	{
-+	  __x._M_manager(_M_functor, __x._M_functor, __clone_functor);
- 	  _M_invoker = __x._M_invoker;
- 	  _M_manager = __x._M_manager;
--	  __x._M_manager(_M_functor, __x._M_functor, __clone_functor);
- 	}
-     }
- 
-Index: libstdc++-v3/include/parallel/numeric
-===================================================================
---- a/src/libstdc++-v3/include/parallel/numeric	(.../tags/gcc_4_9_2_release)
-+++ b/src/libstdc++-v3/include/parallel/numeric	(.../branches/gcc-4_9-branch)
-@@ -85,8 +85,7 @@
-     __accumulate_switch(__RAIter __begin, __RAIter __end, 
-                       _Tp __init, _BinaryOperation __binary_op, 
-                       random_access_iterator_tag, 
--                      __gnu_parallel::_Parallelism __parallelism_tag  
--                      = __gnu_parallel::parallel_unbalanced)
-+                      __gnu_parallel::_Parallelism __parallelism_tag)
-     {
-       if (_GLIBCXX_PARALLEL_CONDITION(
-             static_cast<__gnu_parallel::_SequenceIndex>(__end - __begin)
-@@ -193,8 +192,7 @@
- 			   _BinaryFunction2 __binary_op2,
- 			   random_access_iterator_tag,
- 			   random_access_iterator_tag,
--			   __gnu_parallel::_Parallelism __parallelism_tag
--			   = __gnu_parallel::parallel_unbalanced)
-+			   __gnu_parallel::_Parallelism __parallelism_tag)
-     {
-       if (_GLIBCXX_PARALLEL_CONDITION((__last1 - __first1)
-                                       >= __gnu_parallel::_Settings::get().
-@@ -419,8 +417,7 @@
- 				 random_access_iterator_tag,
- 				 random_access_iterator_tag,
- 				 __gnu_parallel::_Parallelism
--				 __parallelism_tag
--				 = __gnu_parallel::parallel_balanced)
-+				 __parallelism_tag)
-     {
-       if (_GLIBCXX_PARALLEL_CONDITION(
-             static_cast<__gnu_parallel::_SequenceIndex>(__end - __begin)
-Index: libstdc++-v3/include/parallel/algo.h
-===================================================================
---- a/src/libstdc++-v3/include/parallel/algo.h	(.../tags/gcc_4_9_2_release)
-+++ b/src/libstdc++-v3/include/parallel/algo.h	(.../branches/gcc-4_9-branch)
-@@ -81,9 +81,8 @@
-   template<typename _RAIter, typename _Function>
-     _Function
-     __for_each_switch(_RAIter __begin, _RAIter __end, 
--                    _Function __f, random_access_iterator_tag, 
--                    __gnu_parallel::_Parallelism __parallelism_tag
--                    = __gnu_parallel::parallel_balanced)
-+                    _Function __f, random_access_iterator_tag,
-+                    __gnu_parallel::_Parallelism __parallelism_tag)
-     {
-       if (_GLIBCXX_PARALLEL_CONDITION(
-             static_cast<__gnu_parallel::_SequenceIndex>(__end - __begin)
-@@ -896,8 +895,7 @@
-     typename iterator_traits<_RAIter>::difference_type
-     __count_switch(_RAIter __begin, _RAIter __end, 
-                  const _Tp& __value, random_access_iterator_tag, 
--                 __gnu_parallel::_Parallelism __parallelism_tag 
--                 = __gnu_parallel::parallel_unbalanced)
-+                 __gnu_parallel::_Parallelism __parallelism_tag)
-     {
-       typedef iterator_traits<_RAIter> _TraitsType;
-       typedef typename _TraitsType::value_type _ValueType;
-@@ -966,8 +964,7 @@
-     typename iterator_traits<_RAIter>::difference_type
-     __count_if_switch(_RAIter __begin, _RAIter __end, 
-                     _Predicate __pred, random_access_iterator_tag,
--                    __gnu_parallel::_Parallelism __parallelism_tag
--                    = __gnu_parallel::parallel_unbalanced)
-+                    __gnu_parallel::_Parallelism __parallelism_tag)
-     {
-       typedef iterator_traits<_RAIter> _TraitsType;
-       typedef typename _TraitsType::value_type _ValueType;
-@@ -1225,8 +1222,7 @@
-     __transform1_switch(_RAIter1 __begin, _RAIter1 __end,
-                       _RAIter2 __result, _UnaryOperation __unary_op,
-                       random_access_iterator_tag, random_access_iterator_tag,
--                      __gnu_parallel::_Parallelism __parallelism_tag
--                      = __gnu_parallel::parallel_balanced)
-+                      __gnu_parallel::_Parallelism __parallelism_tag)
-     {
-       if (_GLIBCXX_PARALLEL_CONDITION(
-             static_cast<__gnu_parallel::_SequenceIndex>(__end - __begin)
-@@ -1315,8 +1311,7 @@
-                       _RAIter3 __result, _BinaryOperation __binary_op,
-                       random_access_iterator_tag, random_access_iterator_tag,
-                       random_access_iterator_tag,
--                      __gnu_parallel::_Parallelism __parallelism_tag 
--                      = __gnu_parallel::parallel_balanced)
-+                      __gnu_parallel::_Parallelism __parallelism_tag)
-     {
-       if (_GLIBCXX_PARALLEL_CONDITION(
-             (__end1 - __begin1) >=
-@@ -1422,8 +1417,7 @@
-     __replace_switch(_RAIter __begin, _RAIter __end, 
-                    const _Tp& __old_value, const _Tp& __new_value, 
-                    random_access_iterator_tag, 
--                   __gnu_parallel::_Parallelism __parallelism_tag
--                   = __gnu_parallel::parallel_balanced)
-+                   __gnu_parallel::_Parallelism __parallelism_tag)
-     {
-       // XXX parallel version is where?
-       replace(__begin, __end, __old_value, __new_value, 
-@@ -1478,8 +1472,7 @@
-     __replace_if_switch(_RAIter __begin, _RAIter __end,
-                       _Predicate __pred, const _Tp& __new_value,
-                       random_access_iterator_tag,
--                      __gnu_parallel::_Parallelism __parallelism_tag
--                      = __gnu_parallel::parallel_balanced)
-+                      __gnu_parallel::_Parallelism __parallelism_tag)
-     {
-       if (_GLIBCXX_PARALLEL_CONDITION(
-             static_cast<__gnu_parallel::_SequenceIndex>(__end - __begin)
-@@ -1544,8 +1537,7 @@
-     void
-     __generate_switch(_RAIter __begin, _RAIter __end,
-                     _Generator __gen, random_access_iterator_tag, 
--                    __gnu_parallel::_Parallelism __parallelism_tag
--                    = __gnu_parallel::parallel_balanced)
-+                    __gnu_parallel::_Parallelism __parallelism_tag)
-     {
-       if (_GLIBCXX_PARALLEL_CONDITION(
-             static_cast<__gnu_parallel::_SequenceIndex>(__end - __begin)
-@@ -1608,8 +1600,7 @@
-     inline _RAIter
-     __generate_n_switch(_RAIter __begin, _Size __n, _Generator __gen, 
-                       random_access_iterator_tag, 
--                      __gnu_parallel::_Parallelism __parallelism_tag
--                      = __gnu_parallel::parallel_balanced)
-+                      __gnu_parallel::_Parallelism __parallelism_tag)
-     {
-       // XXX parallel version is where?
-       return generate_n(__begin, __n, __gen, __gnu_parallel::sequential_tag());
-@@ -2204,8 +2195,7 @@
-     _RAIter
-     __max_element_switch(_RAIter __begin, _RAIter __end, 
-                        _Compare __comp, random_access_iterator_tag, 
--                       __gnu_parallel::_Parallelism __parallelism_tag
--                       = __gnu_parallel::parallel_balanced)
-+			 __gnu_parallel::_Parallelism __parallelism_tag)
-     {
-       if (_GLIBCXX_PARALLEL_CONDITION(
-             static_cast<__gnu_parallel::_SequenceIndex>(__end - __begin)
-@@ -2296,8 +2286,7 @@
-     _RAIter
-     __min_element_switch(_RAIter __begin, _RAIter __end, 
-                        _Compare __comp, random_access_iterator_tag, 
--                       __gnu_parallel::_Parallelism __parallelism_tag
--                       = __gnu_parallel::parallel_balanced)
-+                       __gnu_parallel::_Parallelism __parallelism_tag)
-     {
-       if (_GLIBCXX_PARALLEL_CONDITION(
-             static_cast<__gnu_parallel::_SequenceIndex>(__end - __begin)
-Index: libstdc++-v3/include/bits/stl_uninitialized.h
-===================================================================
---- a/src/libstdc++-v3/include/bits/stl_uninitialized.h	(.../tags/gcc_4_9_2_release)
-+++ b/src/libstdc++-v3/include/bits/stl_uninitialized.h	(.../branches/gcc-4_9-branch)
-@@ -115,8 +115,9 @@
-       const bool __assignable = true;
- #else
-       // trivial types can have deleted assignment
--      typedef typename iterator_traits<_InputIterator>::reference _RefType;
--      const bool __assignable = is_assignable<_ValueType1, _RefType>::value;
-+      typedef typename iterator_traits<_InputIterator>::reference _RefType1;
-+      typedef typename iterator_traits<_ForwardIterator>::reference _RefType2;
-+      const bool __assignable = is_assignable<_RefType2, _RefType1>::value;
- #endif
- 
-       return std::__uninitialized_copy<__is_trivial(_ValueType1)
-Index: libstdc++-v3/include/bits/stl_algo.h
-===================================================================
---- a/src/libstdc++-v3/include/bits/stl_algo.h	(.../tags/gcc_4_9_2_release)
-+++ b/src/libstdc++-v3/include/bits/stl_algo.h	(.../branches/gcc-4_9-branch)
-@@ -3595,7 +3595,8 @@
- 
-       // Efficiently compare identical prefixes:  O(N) if sequences
-       // have the same elements in the same order.
--      for (; __first1 != __last1; ++__first1, ++__first2)
-+      for (; __first1 != __last1 && __first2 != __last2;
-+	  ++__first1, ++__first2)
- 	if (!__pred(__first1, __first2))
- 	  break;
- 
-Index: libstdc++-v3/include/bits/regex_executor.tcc
-===================================================================
---- a/src/libstdc++-v3/include/bits/regex_executor.tcc	(.../tags/gcc_4_9_2_release)
-+++ b/src/libstdc++-v3/include/bits/regex_executor.tcc	(.../branches/gcc-4_9-branch)
-@@ -267,9 +267,11 @@
- 	    _M_dfs<__match_mode>(__state._M_next);
- 	  break;
- 	case _S_opcode_match:
-+	  if (_M_current == _M_end)
-+	    break;
- 	  if (__dfs_mode)
- 	    {
--	      if (_M_current != _M_end && __state._M_matches(*_M_current))
-+	      if (__state._M_matches(*_M_current))
- 		{
- 		  ++_M_current;
- 		  _M_dfs<__match_mode>(__state._M_next);
-@@ -350,23 +352,24 @@
-     bool _Executor<_BiIter, _Alloc, _TraitsT, __dfs_mode>::
-     _M_word_boundary(_State<_TraitsT> __state) const
-     {
--      // By definition.
--      bool __ans = false;
--      auto __pre = _M_current;
--      --__pre;
--      if (!(_M_at_begin() && _M_at_end()))
-+      bool __left_is_word = false;
-+      if (_M_current != _M_begin
-+	  || (_M_flags & regex_constants::match_prev_avail))
- 	{
--	  if (_M_at_begin())
--	    __ans = _M_is_word(*_M_current)
--	      && !(_M_flags & regex_constants::match_not_bow);
--	  else if (_M_at_end())
--	    __ans = _M_is_word(*__pre)
--	      && !(_M_flags & regex_constants::match_not_eow);
--	  else
--	    __ans = _M_is_word(*_M_current)
--	      != _M_is_word(*__pre);
-+	  auto __prev = _M_current;
-+	  if (_M_is_word(*std::prev(__prev)))
-+	    __left_is_word = true;
- 	}
--      return __ans;
-+      bool __right_is_word =
-+	_M_current != _M_end && _M_is_word(*_M_current);
-+
-+      if (__left_is_word == __right_is_word)
-+	return false;
-+      if (__left_is_word && !(_M_flags & regex_constants::match_not_eow))
-+	return true;
-+      if (__right_is_word && !(_M_flags & regex_constants::match_not_bow))
-+	return true;
-+      return false;
-     }
- 
- _GLIBCXX_END_NAMESPACE_VERSION
-Index: libstdc++-v3/include/bits/regex.tcc
-===================================================================
---- a/src/libstdc++-v3/include/bits/regex.tcc	(.../tags/gcc_4_9_2_release)
-+++ b/src/libstdc++-v3/include/bits/regex.tcc	(.../branches/gcc-4_9-branch)
-@@ -62,6 +62,7 @@
- 	return false;
- 
-       typename match_results<_BiIter, _Alloc>::_Base_type& __res = __m;
-+      __m._M_begin = __s;
-       __res.resize(__re._M_automaton->_M_sub_count() + 2);
-       for (auto& __it : __res)
- 	__it.matched = false;
-@@ -274,53 +275,17 @@
- 	  "right-curly-bracket",
- 	  "tilde",
- 	  "DEL",
--	  ""
- 	};
- 
--      // same as boost
--      //static const char* __digraphs[] =
--      //  {
--      //    "ae",
--      //    "Ae",
--      //    "AE",
--      //    "ch",
--      //    "Ch",
--      //    "CH",
--      //    "ll",
--      //    "Ll",
--      //    "LL",
--      //    "ss",
--      //    "Ss",
--      //    "SS",
--      //    "nj",
--      //    "Nj",
--      //    "NJ",
--      //    "dz",
--      //    "Dz",
--      //    "DZ",
--      //    "lj",
--      //    "Lj",
--      //    "LJ",
--      //    ""
--      //  };
-+      string __s(__first, __last);
-+      for (const auto& __it : __collatenames)
-+	if (__s == __it)
-+	  return string_type(1, __fctyp.widen(
-+	    static_cast<char>(&__it - __collatenames)));
- 
--      std::string __s(__last - __first, '?');
--      __fctyp.narrow(__first, __last, '?', &*__s.begin());
-+      // TODO Add digraph support:
-+      // http://boost.sourceforge.net/libs/regex/doc/collating_names.html
- 
--      for (unsigned int __i = 0; *__collatenames[__i]; __i++)
--	if (__s == __collatenames[__i])
--	  return string_type(1, __fctyp.widen(static_cast<char>(__i)));
--
--      //for (unsigned int __i = 0; *__digraphs[__i]; __i++)
--      //  {
--      //    const char* __now = __digraphs[__i];
--      //    if (__s == __now)
--      //      {
--      //	string_type ret(__s.size(), __fctyp.widen('?'));
--      //	__fctyp.widen(__now, __now + 2/* ouch */, &*ret.begin());
--      //	return ret;
--      //      }
--      //  }
-       return string_type();
-     }
- 
-@@ -331,12 +296,10 @@
-     lookup_classname(_Fwd_iter __first, _Fwd_iter __last, bool __icase) const
-     {
-       typedef std::ctype<char_type> __ctype_type;
--      typedef std::ctype<char> __cctype_type;
--      typedef const pair<const char*, char_class_type> _ClassnameEntry;
-       const __ctype_type& __fctyp(use_facet<__ctype_type>(_M_locale));
--      const __cctype_type& __cctyp(use_facet<__cctype_type>(_M_locale));
- 
--      static _ClassnameEntry __classnames[] =
-+      // Mappings from class name to class mask.
-+      static const pair<const char*, char_class_type> __classnames[] =
-       {
- 	{"d", ctype_base::digit},
- 	{"w", {ctype_base::alnum, _RegexMask::_S_under}},
-@@ -355,22 +318,19 @@
- 	{"xdigit", ctype_base::xdigit},
-       };
- 
--      std::string __s(__last - __first, '?');
--      __fctyp.narrow(__first, __last, '?', &__s[0]);
--      __cctyp.tolower(&*__s.begin(), &*__s.begin() + __s.size());
--      for (_ClassnameEntry* __it = __classnames;
--	   __it < *(&__classnames + 1);
--	   ++__it)
--	{
--	  if (__s == __it->first)
--	    {
--	      if (__icase
--		  && ((__it->second
--		       & (ctype_base::lower | ctype_base::upper)) != 0))
--		return ctype_base::alpha;
--	      return __it->second;
--	    }
--	}
-+      string __s;
-+      for (auto __cur = __first; __cur != __last; ++__cur)
-+	__s += __fctyp.narrow(__fctyp.tolower(*__cur), '?');
-+
-+      for (const auto& __it : __classnames)
-+	if (__s == __it.first)
-+	  {
-+	    if (__icase
-+		&& ((__it.second
-+		     & (ctype_base::lower | ctype_base::upper)) != 0))
-+	      return ctype_base::alpha;
-+	    return __it.second;
-+	  }
-       return 0;
-     }
- 
-@@ -581,8 +541,10 @@
- 				   | regex_constants::match_continuous))
- 		    {
- 		      _GLIBCXX_DEBUG_ASSERT(_M_match[0].matched);
--		      _M_match.at(_M_match.size()).first = __prefix_first;
--		      _M_match._M_in_iterator = true;
-+		      auto& __prefix = _M_match.at(_M_match.size());
-+		      __prefix.first = __prefix_first;
-+		      __prefix.matched = __prefix.first != __prefix.second;
-+		      // [28.12.1.4.5]
- 		      _M_match._M_begin = _M_begin;
- 		      return *this;
- 		    }
-@@ -594,8 +556,10 @@
- 	  if (regex_search(__start, _M_end, _M_match, *_M_pregex, _M_flags))
- 	    {
- 	      _GLIBCXX_DEBUG_ASSERT(_M_match[0].matched);
--	      _M_match.at(_M_match.size()).first = __prefix_first;
--	      _M_match._M_in_iterator = true;
-+	      auto& __prefix = _M_match.at(_M_match.size());
-+	      __prefix.first = __prefix_first;
-+	      __prefix.matched = __prefix.first != __prefix.second;
-+	      // [28.12.1.4.5]
- 	      _M_match._M_begin = _M_begin;
- 	    }
- 	  else
-@@ -614,11 +578,9 @@
-       _M_position = __rhs._M_position;
-       _M_subs = __rhs._M_subs;
-       _M_n = __rhs._M_n;
--      _M_result = __rhs._M_result;
-       _M_suffix = __rhs._M_suffix;
-       _M_has_m1 = __rhs._M_has_m1;
--      if (__rhs._M_result == &__rhs._M_suffix)
--	_M_result = &_M_suffix;
-+      _M_normalize_result();
-       return *this;
-     }
- 
-Index: libstdc++-v3/include/bits/regex.h
-===================================================================
---- a/src/libstdc++-v3/include/bits/regex.h	(.../tags/gcc_4_9_2_release)
-+++ b/src/libstdc++-v3/include/bits/regex.h	(.../branches/gcc-4_9-branch)
-@@ -476,7 +476,10 @@
-        */
-       basic_regex(const basic_regex& __rhs)
-       : _M_flags(__rhs._M_flags), _M_original_str(__rhs._M_original_str)
--      { this->imbue(__rhs.getloc()); }
-+      {
-+	_M_traits.imbue(__rhs.getloc());
-+	this->assign(_M_original_str, _M_flags);
-+      }
- 
-       /**
-        * @brief Move-constructs a basic regular expression.
-@@ -490,7 +493,8 @@
-       : _M_flags(__rhs._M_flags),
-       _M_original_str(std::move(__rhs._M_original_str))
-       {
--	this->imbue(__rhs.getloc());
-+	_M_traits.imbue(__rhs.getloc());
-+	this->assign(_M_original_str, _M_flags);
- 	__rhs._M_automaton.reset();
-       }
- 
-@@ -604,7 +608,8 @@
-       {
- 	_M_flags = __rhs._M_flags;
- 	_M_original_str = __rhs._M_original_str;
--	this->imbue(__rhs.getloc());
-+	_M_traits.imbue(__rhs.getloc());
-+	this->assign(_M_original_str, _M_flags);
- 	return *this;
-       }
- 
-@@ -622,7 +627,9 @@
- 	_M_flags = __rhs._M_flags;
- 	_M_original_str = std::move(__rhs._M_original_str);
- 	__rhs._M_automaton.reset();
--	this->imbue(__rhs.getloc());
-+	_M_traits.imbue(__rhs.getloc());
-+	this->assign(_M_original_str, _M_flags);
-+	return *this;
-       }
- 
-       /**
-@@ -675,12 +682,10 @@
- 	assign(const basic_string<_Ch_type, _Ch_typeraits, _Alloc>& __s,
- 	       flag_type __flags = ECMAScript)
- 	{
-+	  _M_automaton = __detail::__compile_nfa(
-+	    __s.data(), __s.data() + __s.size(), _M_traits, __flags);
-+	  _M_original_str = __s;
- 	  _M_flags = __flags;
--	  _M_original_str.assign(__s.begin(), __s.end());
--	  auto __p = _M_original_str.c_str();
--	  _M_automaton = __detail::__compile_nfa(__p,
--						 __p + _M_original_str.size(),
--						 _M_traits, _M_flags);
- 	  return *this;
- 	}
- 
-@@ -725,7 +730,11 @@
-        */
-       unsigned int
-       mark_count() const
--      { return _M_automaton->_M_sub_count() - 1; }
-+      {
-+	if (_M_automaton)
-+	  return _M_automaton->_M_sub_count() - 1;
-+	return 0;
-+      }
- 
-       /**
-        * @brief Gets the flags used to construct the regular expression
-@@ -744,9 +753,8 @@
-       locale_type
-       imbue(locale_type __loc)
-       {
--	auto __ret = _M_traits.imbue(__loc);
--	this->assign(_M_original_str, _M_flags);
--	return __ret;
-+	_M_automaton = nullptr;
-+	return _M_traits.imbue(__loc);
-       }
- 
-       /**
-@@ -767,8 +775,10 @@
-       swap(basic_regex& __rhs)
-       {
- 	std::swap(_M_flags, __rhs._M_flags);
--	std::swap(_M_original_str, __rhs._M_original_str);
--	this->imbue(__rhs.imbue(this->getloc()));
-+	std::swap(_M_traits, __rhs._M_traits);
-+	auto __tmp = std::move(_M_original_str);
-+	this->assign(__rhs._M_original_str, _M_flags);
-+	__rhs.assign(__tmp, __rhs._M_flags);
-       }
- 
- #ifdef _GLIBCXX_DEBUG
-@@ -777,7 +787,7 @@
-       { _M_automaton->_M_dot(__ostr); }
- #endif
- 
--    protected:
-+    private:
-       typedef std::shared_ptr<__detail::_NFA<_Rx_traits>> _AutomatonPtr;
- 
-       template<typename _Bp, typename _Ap, typename _Cp, typename _Rp,
-@@ -1568,42 +1578,30 @@
-        */
-       explicit
-       match_results(const _Alloc& __a = _Alloc())
--      : _Base_type(__a), _M_in_iterator(false)
-+      : _Base_type(__a)
-       { }
- 
-       /**
-        * @brief Copy constructs a %match_results.
-        */
--      match_results(const match_results& __rhs)
--      : _Base_type(__rhs), _M_in_iterator(false)
--      { }
-+      match_results(const match_results& __rhs) = default;
- 
-       /**
-        * @brief Move constructs a %match_results.
-        */
--      match_results(match_results&& __rhs) noexcept
--      : _Base_type(std::move(__rhs)), _M_in_iterator(false)
--      { }
-+      match_results(match_results&& __rhs) noexcept = default;
- 
-       /**
-        * @brief Assigns rhs to *this.
-        */
-       match_results&
--      operator=(const match_results& __rhs)
--      {
--	match_results(__rhs).swap(*this);
--	return *this;
--      }
-+      operator=(const match_results& __rhs) = default;
- 
-       /**
-        * @brief Move-assigns rhs to *this.
-        */
-       match_results&
--      operator=(match_results&& __rhs)
--      {
--	match_results(std::move(__rhs)).swap(*this);
--	return *this;
--      }
-+      operator=(match_results&& __rhs) = default;
- 
-       /**
-        * @brief Destroys a %match_results object.
-@@ -1690,13 +1688,8 @@
-       difference_type
-       position(size_type __sub = 0) const
-       {
--	// [28.12.1.4.5]
--	if (_M_in_iterator)
--	  return __sub < size() ? std::distance(_M_begin,
--						(*this)[__sub].first) : -1;
--	else
--	  return __sub < size() ? std::distance(this->prefix().first,
--						(*this)[__sub].first) : -1;
-+	return __sub < size() ? std::distance(_M_begin,
-+					      (*this)[__sub].first) : -1;
-       }
- 
-       /**
-@@ -1778,7 +1771,7 @@
-        */
-       const_iterator
-       cbegin() const
--      { return _Base_type::cbegin() + 2; }
-+      { return this->begin(); }
- 
-       /**
-        * @brief Gets an iterator to one-past-the-end of the collection.
-@@ -1792,7 +1785,7 @@
-        */
-       const_iterator
-       cend() const
--      { return _Base_type::cend(); }
-+      { return this->end(); }
- 
-       //@}
- 
-@@ -1881,7 +1874,11 @@
-        */
-       void
-       swap(match_results& __that)
--      { _Base_type::swap(__that); }
-+      {
-+	using std::swap;
-+	_Base_type::swap(__that);
-+	swap(_M_begin, __that._M_begin);
-+      }
-       //@}
- 
-     private:
-@@ -2620,7 +2617,7 @@
- 			     regex_constants::match_flag_type __m
- 			     = regex_constants::match_default)
-       : _M_position(__a, __b, __re, __m),
--      _M_subs(__submatches, *(&__submatches+1)), _M_n(0)
-+      _M_subs(__submatches, __submatches + _Nm), _M_n(0)
-       { _M_init(__a, __b); }
- 
-       /**
-@@ -2629,12 +2626,8 @@
-        */
-       regex_token_iterator(const regex_token_iterator& __rhs)
-       : _M_position(__rhs._M_position), _M_subs(__rhs._M_subs),
--      _M_suffix(__rhs._M_suffix), _M_n(__rhs._M_n), _M_result(__rhs._M_result),
--      _M_has_m1(__rhs._M_has_m1)
--      {
--	if (__rhs._M_result == &__rhs._M_suffix)
--	  _M_result = &_M_suffix;
--      }
-+      _M_suffix(__rhs._M_suffix), _M_n(__rhs._M_n), _M_has_m1(__rhs._M_has_m1)
-+      { _M_normalize_result(); }
- 
-       /**
-        * @brief Assigns a %regex_token_iterator to another.
-@@ -2706,6 +2699,18 @@
-       _M_end_of_seq() const
-       { return _M_result == nullptr; }
- 
-+      // [28.12.2.2.4]
-+      void
-+      _M_normalize_result()
-+      {
-+	if (_M_position != _Position())
-+	  _M_result = &_M_current_match();
-+	else if (_M_has_m1)
-+	  _M_result = &_M_suffix;
-+	else
-+	  _M_result = nullptr;
-+      }
-+
-       _Position         _M_position;
-       std::vector<int>  _M_subs;
-       value_type        _M_suffix;
-Index: libstdc++-v3/include/bits/regex_compiler.tcc
-===================================================================
---- a/src/libstdc++-v3/include/bits/regex_compiler.tcc	(.../tags/gcc_4_9_2_release)
-+++ b/src/libstdc++-v3/include/bits/regex_compiler.tcc	(.../branches/gcc-4_9-branch)
-@@ -271,7 +271,7 @@
- 		{
- 		  auto& __tmp = _M_nfa[__stack.top()];
- 		  __stack.pop();
--		  swap(__tmp._M_next, __tmp._M_alt);
-+		  std::swap(__tmp._M_next, __tmp._M_alt);
- 		}
- 	    }
- 	  _M_stack.push(__e);
-Index: libstdc++-v3/include/tr1/functional
-===================================================================
---- a/src/libstdc++-v3/include/tr1/functional	(.../tags/gcc_4_9_2_release)
-+++ b/src/libstdc++-v3/include/tr1/functional	(.../branches/gcc-4_9-branch)
-@@ -2112,9 +2112,9 @@
-     {
-       if (static_cast<bool>(__x))
- 	{
-+	  __x._M_manager(_M_functor, __x._M_functor, __clone_functor);
- 	  _M_invoker = __x._M_invoker;
- 	  _M_manager = __x._M_manager;
--	  __x._M_manager(_M_functor, __x._M_functor, __clone_functor);
- 	}
-     }
- 
-@@ -2130,9 +2130,9 @@
- 
- 	if (_My_handler::_M_not_empty_function(__f))
- 	  {
-+	    _My_handler::_M_init_functor(_M_functor, __f);
- 	    _M_invoker = &_My_handler::_M_invoke;
- 	    _M_manager = &_My_handler::_M_manager;
--	    _My_handler::_M_init_functor(_M_functor, __f);
- 	  }
-       }
- 
-Index: libstdc++-v3/ChangeLog
-===================================================================
---- a/src/libstdc++-v3/ChangeLog	(.../tags/gcc_4_9_2_release)
-+++ b/src/libstdc++-v3/ChangeLog	(.../branches/gcc-4_9-branch)
-@@ -1,3 +1,156 @@
-+2015-01-19  Tim Shen  <timshen@google.com>
-+
-+	PR libstdc++/64649
-+	Backported from mainline
-+	2015-01-19  Tim Shen  <timshen@google.com>
-+
-+	* include/bits/regex.tcc (regex_traits<>::lookup_collatename,
-+	regex_traits<>::lookup_classname): Support forward iterators.
-+	* testsuite/28_regex/traits/char/lookup_classname.cc: New testcases.
-+	* testsuite/28_regex/traits/char/lookup_collatename.cc: New testcase.
-+
-+2015-01-19  Tim Shen  <timshen@google.com>
-+
-+	PR libstdc++/64584
-+	PR libstdc++/64585
-+	* include/bits/regex.h (basic_regex<>::basic_regex,
-+	basic_regex<>::assign, basic_regex<>::imbue,
-+	basic_regex<>::swap, basic_regex<>::mark_count): Drop NFA after
-+	imbuing basic_regex; Make assign() transactional against exception.
-+	* testsuite/28_regex/basic_regex/assign/char/string.cc: New testcase.
-+	* testsuite/28_regex/basic_regex/imbue/string.cc: New testcase.
-+
-+2015-01-18  Jonathan Wakely  <jwakely@redhat.com>
-+
-+	PR libstdc++/64646
-+	* include/bits/stl_algo.h (__is_permutation): Also test for reaching
-+	end of the second range.
-+	* testsuite/25_algorithms/is_permutation/64646.cc: New.
-+
-+2015-01-09  Jonathan Wakely  <jwakely@redhat.com>
-+
-+	PR libstdc++/64476
-+	* include/bits/stl_uninitialized.h (uninitialized_copy): Fix
-+	is_assignable arguments.
-+	* testsuite/20_util/specialized_algorithms/uninitialized_copy/64476.cc:
-+	New.
-+
-+2015-01-09  Jonathan Wakely  <jwakely@redhat.com>
-+
-+	PR libstdc++/60966
-+	* include/std/future (packaged_task::operator()): Increment the
-+	reference count on the shared state until the function returns.
-+
-+2015-01-09  Tim Shen  <timshen@google.com>
-+
-+	PR libstdc++/64239
-+	Backported form mainline
-+	2015-01-09  Tim Shen  <timshen@google.com>
-+
-+	* include/bits/regex.h (match_results<>::swap): Use std::swap
-+	instead of swap.
-+	* include/bits/regex_compiler.tcc (_Compiler<>::_M_quantifier):
-+	Likewise.
-+	* testsuite/28_regex/match_results/swap.cc: New testcase.
-+
-+2014-12-17  Tim Shen  <timshen@google.com>
-+
-+	PR libstdc++/64302
-+	PR libstdc++/64303
-+	Backported form mainline
-+	2014-12-17  Tim Shen  <timshen@google.com>
-+
-+	* include/bits/regex.h (match_results::cbegin, match_results::cend,
-+	regex_token_iterator::regex_token_iterator,
-+	regex_token_iterator::_M_normalize_result): Fix match_results cbegin
-+	and cend and regex_token_iterator::_M_result invariant.
-+	* include/bits/regex.tcc: Fix regex_token_iterator::_M_result invariant.
-+	* testsuite/28_regex/iterators/regex_token_iterator/64303.cc: Testcase.
-+
-+2014-12-13  Tim Shen  <timshen@google.com>
-+
-+	PR libstdc++/64239
-+	* include/bits/regex.h (match_results<>::match_results,
-+	match_results<>::operator=, match_results<>::position,
-+	match_results<>::swap): Fix ctor/assign/swap.
-+	* include/bits/regex.tcc: (__regex_algo_impl<>,
-+	regex_iterator<>::operator++): Set match_results::_M_begin as
-+	"start position".
-+	* testsuite/28_regex/iterators/regex_iterator/char/
-+	string_position_01.cc: Test cases.
-+
-+2014-12-09  Jonathan Wakely  <jwakely@redhat.com>
-+
-+	PR libstdc++/64203
-+	* include/std/shared_mutex: Fix preprocessor conditions.
-+	* testsuite/experimental/feat-cxx14.cc: Check conditions.
-+
-+2014-12-06  Jonathan Wakely  <jwakely@redhat.com>
-+
-+	PR libstdc++/63840
-+	* include/std/functional (function::function(const function&)): Set
-+	_M_manager after operations that might throw.
-+	* include/tr1/functional (function::function(const function&),
-+	function::function(_Functor, _Useless)): Likewise.
-+	* testsuite/20_util/function/63840.cc: New.
-+	* testsuite/tr1/3_function_objects/function/63840.cc: New.
-+
-+	PR libstdc++/61947
-+	* include/std/tuple (_Head_base): Use allocator_arg_t parameters to
-+	disambiguate unary constructors.
-+	(_Tuple_impl): Pass allocator_arg_t arguments.
-+	* testsuite/20_util/tuple/61947.cc: New.
-+	* testsuite/20_util/uses_allocator/cons_neg.cc: Adjust dg-error line.
-+
-+2014-12-06  Tim Shen  <timshen@google.com>
-+
-+	PR libstdc++/64140
-+	Backport form mainline
-+	2014-12-04  Tim Shen  <timshen@google.com>
-+
-+	* include/bits/regex.tcc (regex_iterator<>::operator++): Update
-+	prefix.matched after modifying prefix.first.
-+	* testsuite/28_regex/iterators/regex_iterator/char/64140.cc: New
-+	testcase.
-+
-+2014-12-02  Matthias Klose  <doko@ubuntu.com>
-+
-+	PR libstdc++/64103
-+	Backport from mainline
-+	2014-11-03  Paolo Carlini  <paolo.carlini@oracle.com>
-+
-+	* include/parallel/algo.h: Do not use default arguments in function
-+	template redeclarations (definitions).
-+
-+	2014-11-04  Jonathan Wakely  <jwakely@redhat.com>
-+
-+	* include/parallel/numeric.h: Do not use default arguments in function
-+	template redeclarations (definitions).
-+
-+2014-11-28  Tim Shen  <timshen@google.com>
-+
-+	PR libstdc++/63497
-+	* include/bits/regex_executor.tcc (_Executor::_M_dfs,
-+	_Executor::_M_word_boundary): Avoid dereferecing _M_current at _M_end
-+	or other invalid position.
-+
-+2014-11-13  Thomas Preud'homme  <thomas.preudhomme@arm.com>
-+
-+	Backport from mainline
-+	2014-09-10  Tony Wang  <tony.wang@arm.com>
-+
-+	PR target/56846
-+	* libsupc++/eh_personality.cc (PERSONALITY_FUNCTION):
-+	Return with CONTINUE_UNWINDING when the state pattern
-+	contains: _US_VIRTUAL_UNWIND_FRAME | _US_FORCE_UNWIND
-+
-+2014-10-30  David Edelsohn  <dje.gcc@gmail.com>
-+
-+	Backported from mainline.
-+	2014-10-30  David Edelsohn  <dje.gcc@gmail.com>
-+
-+	* configure.host (aix4.3+, 5+): Do not use -G in link command.
-+
- 2014-10-30  Release Manager
- 
- 	* GCC 4.9.2 released.
-Index: libstdc++-v3/libsupc++/eh_personality.cc
-===================================================================
---- a/src/libstdc++-v3/libsupc++/eh_personality.cc	(.../tags/gcc_4_9_2_release)
-+++ b/src/libstdc++-v3/libsupc++/eh_personality.cc	(.../branches/gcc-4_9-branch)
-@@ -378,6 +378,12 @@
-   switch (state & _US_ACTION_MASK)
-     {
-     case _US_VIRTUAL_UNWIND_FRAME:
-+      // If the unwind state pattern is
-+      // _US_VIRTUAL_UNWIND_FRAME | _US_FORCE_UNWIND
-+      // then we don't need to search for any handler as it is not a real
-+      // exception. Just unwind the stack.
-+      if (state & _US_FORCE_UNWIND)
-+	CONTINUE_UNWINDING;
-       actions = _UA_SEARCH_PHASE;
-       break;
- 
-Index: libstdc++-v3/testsuite/25_algorithms/is_permutation/64646.cc
-===================================================================
---- a/src/libstdc++-v3/testsuite/25_algorithms/is_permutation/64646.cc	(.../tags/gcc_4_9_2_release)
-+++ b/src/libstdc++-v3/testsuite/25_algorithms/is_permutation/64646.cc	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,35 @@
-+// Copyright (C) 2015 Free Software Foundation, Inc.
-+//
-+// This file is part of the GNU ISO C++ Library.  This library is free
-+// software; you can redistribute it and/or modify it under the
-+// terms of the GNU General Public License as published by the
-+// Free Software Foundation; either version 3, or (at your option)
-+// any later version.
-+
-+// This library is distributed in the hope that it will be useful,
-+// but WITHOUT ANY WARRANTY; without even the implied warranty of
-+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+// GNU General Public License for more details.
-+
-+// You should have received a copy of the GNU General Public License along
-+// with this library; see the file COPYING3.  If not see
-+// <http://www.gnu.org/licenses/>.
-+
-+// { dg-options "-std=gnu++14" }
-+
-+#include <algorithm>
-+#include <forward_list>
-+#include <testsuite_hooks.h>
-+
-+void
-+test01()
-+{
-+  std::forward_list<int> l1{0}, l2;
-+  VERIFY( !std::is_permutation(l1.begin(), l1.end(), l2.begin(), l2.end()) );
-+}
-+
-+int
-+main()
-+{
-+  test01();
-+}
-Index: libstdc++-v3/testsuite/28_regex/traits/char/lookup_collatename.cc
-===================================================================
---- a/src/libstdc++-v3/testsuite/28_regex/traits/char/lookup_collatename.cc	(.../tags/gcc_4_9_2_release)
-+++ b/src/libstdc++-v3/testsuite/28_regex/traits/char/lookup_collatename.cc	(.../branches/gcc-4_9-branch)
-@@ -26,6 +26,7 @@
- // 28.7 (8) Class template regex_traits [re.traits]
- 
- #include <regex>
-+#include <forward_list>
- #include <testsuite_hooks.h>
- 
- void
-@@ -40,8 +41,19 @@
-   VERIFY(t.lookup_collatename(name, name+sizeof(name)-1) == "~");
- }
- 
-+// Test forward iterator.
-+void
-+test02()
-+{
-+  const char strlit[] = "tilde";
-+  std::forward_list<char> s(strlit, strlit + strlen(strlit));
-+  std::regex_traits<char> traits;
-+  VERIFY(traits.lookup_collatename(s.begin(), s.end()) == "~");
-+}
-+
- int main()
- {
- 	test01();
-+	test02();
- 	return 0;
- }
-Index: libstdc++-v3/testsuite/28_regex/traits/char/lookup_classname.cc
-===================================================================
---- a/src/libstdc++-v3/testsuite/28_regex/traits/char/lookup_classname.cc	(.../tags/gcc_4_9_2_release)
-+++ b/src/libstdc++-v3/testsuite/28_regex/traits/char/lookup_classname.cc	(.../branches/gcc-4_9-branch)
-@@ -26,6 +26,7 @@
- // 28.7(9) Class template regex_traits [re.traits]
- 
- #include <regex>
-+#include <forward_list>
- #include <testsuite_hooks.h>
- 
- void
-@@ -47,8 +48,29 @@
- 	VERIFY( c2 == c3 );
- }
- 
-+// Test forward iterator
-+void
-+test02()
-+{
-+  const char strlit[] = "upper";
-+  std::forward_list<char> s(strlit, strlit + strlen(strlit));
-+  std::regex_traits<char> traits;
-+  VERIFY(traits.isctype('C', traits.lookup_classname(s.begin(), s.end(), false)));
-+}
-+
-+// icase
-+void
-+test03()
-+{
-+  std::string s("lower");
-+  std::regex_traits<char> traits;
-+  VERIFY(traits.isctype('C', traits.lookup_classname(s.begin(), s.end(), true)));
-+}
-+
- int main()
- {
- 	test01();
-+	test02();
-+	test03();
- 	return 0;
- }
-Index: libstdc++-v3/testsuite/28_regex/basic_regex/imbue/string.cc
-===================================================================
---- a/src/libstdc++-v3/testsuite/28_regex/basic_regex/imbue/string.cc	(.../tags/gcc_4_9_2_release)
-+++ b/src/libstdc++-v3/testsuite/28_regex/basic_regex/imbue/string.cc	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,44 @@
-+// { dg-options "-std=gnu++11" }
-+
-+// Copyright (C) 2015 Free Software Foundation, Inc.
-+//
-+// This file is part of the GNU ISO C++ Library.  This library is free
-+// software; you can redistribute it and/or modify it under the
-+// terms of the GNU General Public License as published by the
-+// Free Software Foundation; either version 3, or (at your option)
-+// any later version.
-+
-+// This library is distributed in the hope that it will be useful,
-+// but WITHOUT ANY WARRANTY; without even the implied warranty of
-+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+// GNU General Public License for more details.
-+
-+// You should have received a copy of the GNU General Public License along
-+// with this library; see the file COPYING3.  If not see
-+// <http://www.gnu.org/licenses/>.
-+
-+// [28.8.5] class template basic_regex locale
-+
-+#include <string>
-+#include <regex>
-+#include <testsuite_hooks.h>
-+
-+// libstdc++/64585
-+void test01()
-+{
-+  bool test __attribute__((unused)) = true;
-+
-+  static const char s[] = "a";
-+  std::regex re("a");
-+  VERIFY(std::regex_search(s, re));
-+
-+  auto loc = re.imbue(re.getloc());
-+  VERIFY(!std::regex_search(s, re));
-+}
-+
-+int
-+main()
-+{
-+  test01();
-+  return 0;
-+}
-Index: libstdc++-v3/testsuite/28_regex/basic_regex/assign/char/string.cc
-===================================================================
---- a/src/libstdc++-v3/testsuite/28_regex/basic_regex/assign/char/string.cc	(.../tags/gcc_4_9_2_release)
-+++ b/src/libstdc++-v3/testsuite/28_regex/basic_regex/assign/char/string.cc	(.../branches/gcc-4_9-branch)
-@@ -1,4 +1,3 @@
--// { dg-do compile }
- // { dg-options "-std=gnu++0x" }
- 
- // 2007-03-12  Stephen M. Webb  <stephen.webb@bregmasoft.com>
-@@ -29,6 +28,7 @@
- // Tests C++ string assignment of the basic_regex class.  
- void test01()
- {
-+  bool test __attribute__((unused)) = true;
-   typedef std::basic_regex<char> test_type;
- 
-   std::string s("a*b");
-@@ -36,9 +36,27 @@
-   re.assign(s);
- }
- 
-+// libstdc++/64584
-+void test02()
-+{
-+  bool test __attribute__((unused)) = true;
-+  std::regex re("", std::regex_constants::extended);
-+  auto flags = re.flags();
-+  try
-+    {
-+      re.assign("(", std::regex_constants::icase);
-+      VERIFY(false);
-+    }
-+  catch (const std::regex_error& e)
-+    {
-+      VERIFY(flags == re.flags());
-+    }
-+}
-+
- int
- main()
- { 
-   test01();
-+  test02();
-   return 0;
- }
-Index: libstdc++-v3/testsuite/28_regex/iterators/regex_iterator/char/64140.cc
-===================================================================
---- a/src/libstdc++-v3/testsuite/28_regex/iterators/regex_iterator/char/64140.cc	(.../tags/gcc_4_9_2_release)
-+++ b/src/libstdc++-v3/testsuite/28_regex/iterators/regex_iterator/char/64140.cc	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,53 @@
-+// { dg-options "-std=gnu++11" }
-+
-+//
-+// Copyright (C) 2014 Free Software Foundation, Inc.
-+//
-+// This file is part of the GNU ISO C++ Library.  This library is free
-+// software; you can redistribute it and/or modify it under the
-+// terms of the GNU General Public License as published by the
-+// Free Software Foundation; either version 3, or (at your option)
-+// any later version.
-+//
-+// This library is distributed in the hope that it will be useful,
-+// but WITHOUT ANY WARRANTY; without even the implied warranty of
-+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+// GNU General Public License for more details.
-+//
-+// You should have received a copy of the GNU General Public License along
-+// with this library; see the file COPYING3.  If not see
-+// <http://www.gnu.org/licenses/>.
-+
-+// libstdc++/64140
-+
-+#include <regex>
-+#include <testsuite_hooks.h>
-+
-+void
-+test01()
-+{
-+  bool test __attribute__((unused)) = true;
-+
-+  const std::regex e("z*");
-+  const std::string s("ab");
-+
-+  auto it = std::sregex_iterator(s.begin(), s.end(), e);
-+  auto end = std::sregex_iterator();
-+  VERIFY(it != end);
-+  VERIFY(!it->prefix().matched);
-+  ++it;
-+  VERIFY(it != end);
-+  VERIFY(it->prefix().matched);
-+  ++it;
-+  VERIFY(it != end);
-+  VERIFY(it->prefix().matched);
-+  ++it;
-+  VERIFY(it == end);
-+}
-+
-+int
-+main()
-+{
-+  test01();
-+  return 0;
-+}
-Index: libstdc++-v3/testsuite/28_regex/iterators/regex_iterator/char/string_position_01.cc
-===================================================================
---- a/src/libstdc++-v3/testsuite/28_regex/iterators/regex_iterator/char/string_position_01.cc	(.../tags/gcc_4_9_2_release)
-+++ b/src/libstdc++-v3/testsuite/28_regex/iterators/regex_iterator/char/string_position_01.cc	(.../branches/gcc-4_9-branch)
-@@ -24,6 +24,7 @@
- // Tests iter->position() behavior
- 
- #include <regex>
-+#include <tuple>
- #include <testsuite_hooks.h>
- 
- void
-@@ -41,9 +42,53 @@
-   }
- }
- 
-+// PR libstdc++/64239
-+void
-+test02()
-+{
-+  bool test __attribute__((unused)) = true;
-+
-+  std::regex re("\\w+");
-+  std::string s("-a-b-c-");
-+
-+  std::tuple<int, int, const char*> expected[] =
-+  {
-+    std::make_tuple(1, 1, "a"),
-+    std::make_tuple(3, 1, "b"),
-+    std::make_tuple(5, 1, "c"),
-+  };
-+
-+  int i = 0;
-+  for (auto it1 = std::sregex_iterator(s.begin(), s.end(), re),
-+       end = std::sregex_iterator(); it1 != end; ++it1, i++)
-+    {
-+      auto it2 = it1;
-+      VERIFY(it1->position() == std::get<0>(expected[i]));
-+      VERIFY(it1->length() == std::get<1>(expected[i]));
-+      VERIFY(it1->str() == std::get<2>(expected[i]));
-+      VERIFY(it2->position() == std::get<0>(expected[i]));
-+      VERIFY(it2->length() == std::get<1>(expected[i]));
-+      VERIFY(it2->str() == std::get<2>(expected[i]));
-+    }
-+}
-+
-+void
-+test03()
-+{
-+  bool test __attribute__((unused)) = true;
-+
-+  std::smatch m;
-+  std::string s = "abcde";
-+  std::regex_search(s, m, std::regex("bcd"));
-+  VERIFY(m.position() == 1);
-+  VERIFY(m.position() == m.prefix().length());
-+}
-+
- int
- main()
- {
-   test01();
-+  test02();
-+  test03();
-   return 0;
- }
-Index: libstdc++-v3/testsuite/28_regex/iterators/regex_token_iterator/64303.cc
-===================================================================
---- a/src/libstdc++-v3/testsuite/28_regex/iterators/regex_token_iterator/64303.cc	(.../tags/gcc_4_9_2_release)
-+++ b/src/libstdc++-v3/testsuite/28_regex/iterators/regex_token_iterator/64303.cc	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,49 @@
-+// { dg-do run }
-+// { dg-options "-std=gnu++11" }
-+
-+//
-+// Copyright (C) 2014 Free Software Foundation, Inc.
-+//
-+// This file is part of the GNU ISO C++ Library.  This library is free
-+// software; you can redistribute it and/or modify it under the
-+// terms of the GNU General Public License as published by the
-+// Free Software Foundation; either version 3, or (at your option)
-+// any later version.
-+//
-+// This library is distributed in the hope that it will be useful,
-+// but WITHOUT ANY WARRANTY; without even the implied warranty of
-+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+// GNU General Public License for more details.
-+//
-+// You should have received a copy of the GNU General Public License along
-+// with this library; see the file COPYING3.  If not see
-+// <http://www.gnu.org/licenses/>.
-+
-+// 28.12.2 Class template regex_token_iterator
-+
-+#include <regex>
-+#include <testsuite_hooks.h>
-+
-+void
-+test01()
-+{
-+  bool test __attribute__((unused)) = true;
-+
-+  const std::string s("  111  222  ");
-+  const std::regex re("\\w+");
-+
-+  std::sregex_token_iterator it1(s.begin(), s.end(), re), it2(it1), end;
-+
-+  for (; it1 != end; ++it1, ++it2) {
-+    VERIFY(it1 == it2);
-+    VERIFY(*it1 == *it2);
-+  }
-+  VERIFY(it2 == end);
-+}
-+
-+int
-+main()
-+{
-+  test01();
-+  return 0;
-+}
-Index: libstdc++-v3/testsuite/28_regex/match_results/swap.cc
-===================================================================
---- a/src/libstdc++-v3/testsuite/28_regex/match_results/swap.cc	(.../tags/gcc_4_9_2_release)
-+++ b/src/libstdc++-v3/testsuite/28_regex/match_results/swap.cc	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,43 @@
-+// { dg-options "-std=gnu++11" }
-+
-+//
-+// Copyright (C) 2015 Free Software Foundation, Inc.
-+//
-+// This file is part of the GNU ISO C++ Library.  This library is free
-+// software; you can redistribute it and/or modify it under the
-+// terms of the GNU General Public License as published by the
-+// Free Software Foundation; either version 3, or (at your option)
-+// any later version.
-+//
-+// This library is distributed in the hope that it will be useful,
-+// but WITHOUT ANY WARRANTY; without even the implied warranty of
-+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+// GNU General Public License for more details.
-+//
-+// You should have received a copy of the GNU General Public License along
-+// with this library; see the file COPYING3.  If not see
-+// <http://www.gnu.org/licenses/>.
-+
-+#include <regex>
-+#include <testsuite_hooks.h>
-+
-+void
-+test01()
-+{
-+  bool test __attribute__((unused)) = true;
-+
-+  std::cmatch m;
-+  std::regex_match("a", m, std::regex("a"));
-+  std::cmatch mm1 = m, mm2;
-+  mm1.swap(mm2);
-+  VERIFY(m == mm2);
-+  std::swap(mm1, mm2);
-+  VERIFY(m == mm1);
-+}
-+
-+int
-+main()
-+{
-+  test01();
-+  return 0;
-+}
-Index: libstdc++-v3/testsuite/experimental/feat-cxx14.cc
-===================================================================
---- a/src/libstdc++-v3/testsuite/experimental/feat-cxx14.cc	(.../tags/gcc_4_9_2_release)
-+++ b/src/libstdc++-v3/testsuite/experimental/feat-cxx14.cc	(.../branches/gcc-4_9-branch)
-@@ -106,10 +106,12 @@
- #  error "<shared_mutex>"
- #endif
- 
--#ifndef  __cpp_lib_shared_timed_mutex
--#  error "__cpp_lib_shared_timed_mutex"
--#elif  __cpp_lib_shared_timed_mutex != 201402
--#  error "__cpp_lib_shared_timed_mutex != 201402"
-+#if defined(_GLIBCXX_HAS_GTHREADS) && defined(_GLIBCXX_USE_C99_STDINT_TR1)
-+#  ifndef  __cpp_lib_shared_timed_mutex
-+#    error "__cpp_lib_shared_timed_mutex"
-+#  elif  __cpp_lib_shared_timed_mutex != 201402
-+#    error "__cpp_lib_shared_timed_mutex != 201402"
-+#  endif
- #endif
- 
- #ifndef  __cpp_lib_is_final
-Index: libstdc++-v3/testsuite/tr1/3_function_objects/function/63840.cc
-===================================================================
---- a/src/libstdc++-v3/testsuite/tr1/3_function_objects/function/63840.cc	(.../tags/gcc_4_9_2_release)
-+++ b/src/libstdc++-v3/testsuite/tr1/3_function_objects/function/63840.cc	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,55 @@
-+// Copyright (C) 2014 Free Software Foundation, Inc.
-+//
-+// This file is part of the GNU ISO C++ Library.  This library is free
-+// software; you can redistribute it and/or modify it under the
-+// terms of the GNU General Public License as published by the
-+// Free Software Foundation; either version 3, or (at your option)
-+// any later version.
-+
-+// This library is distributed in the hope that it will be useful,
-+// but WITHOUT ANY WARRANTY; without even the implied warranty of
-+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+// GNU General Public License for more details.
-+
-+// You should have received a copy of the GNU General Public License along
-+// with this library; see the file COPYING3.  If not see
-+// <http://www.gnu.org/licenses/>.
-+
-+#include <tr1/functional>
-+#include <stdexcept>
-+#include <testsuite_hooks.h>
-+
-+struct functor
-+{
-+  functor() : copies(0) { }
-+
-+  functor(const functor& f)
-+  : copies(f.copies + 1)
-+  {
-+    if (copies > 1)
-+      throw std::runtime_error("functor");
-+  }
-+
-+  void operator()() const { }
-+
-+  int copies;
-+};
-+
-+
-+void
-+test01()
-+{
-+  std::tr1::function<void()> f = functor();
-+  try {
-+    std::tr1::function<void()> g = f;
-+  } catch (const std::runtime_error& e) {
-+    return;
-+  }
-+  VERIFY(false);
-+}
-+
-+int
-+main()
-+{
-+  test01();
-+}
-Index: libstdc++-v3/testsuite/20_util/tuple/61947.cc
-===================================================================
---- a/src/libstdc++-v3/testsuite/20_util/tuple/61947.cc	(.../tags/gcc_4_9_2_release)
-+++ b/src/libstdc++-v3/testsuite/20_util/tuple/61947.cc	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,29 @@
-+// { dg-options "-std=gnu++11" }
-+// { dg-do compile }
-+
-+// Copyright (C) 2014 Free Software Foundation, Inc.
-+//
-+// This file is part of the GNU ISO C++ Library.  This library is free
-+// software; you can redistribute it and/or modify it under the
-+// terms of the GNU General Public License as published by the
-+// Free Software Foundation; either version 3, or (at your option)
-+// any later version.
-+
-+// This library is distributed in the hope that it will be useful,
-+// but WITHOUT ANY WARRANTY; without even the implied warranty of
-+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+// GNU General Public License for more details.
-+
-+// You should have received a copy of the GNU General Public License along
-+// with this library; see the file COPYING3.  If not see
-+// <http://www.gnu.org/licenses/>.
-+
-+#include <tuple>
-+
-+struct ConvertibleToAny {
-+  template <class T> operator T() const { return T(); }
-+};
-+
-+int main() {
-+  std::tuple<ConvertibleToAny&&> t(ConvertibleToAny{});
-+}
-Index: libstdc++-v3/testsuite/20_util/uses_allocator/cons_neg.cc
-===================================================================
---- a/src/libstdc++-v3/testsuite/20_util/uses_allocator/cons_neg.cc	(.../tags/gcc_4_9_2_release)
-+++ b/src/libstdc++-v3/testsuite/20_util/uses_allocator/cons_neg.cc	(.../branches/gcc-4_9-branch)
-@@ -44,4 +44,4 @@
- 
-   tuple<Type> t(allocator_arg, a, 1);
- }
--// { dg-error "no matching function" "" { target *-*-* } 118 }
-+// { dg-error "no matching function" "" { target *-*-* } 119 }
-Index: libstdc++-v3/testsuite/20_util/function/63840.cc
-===================================================================
---- a/src/libstdc++-v3/testsuite/20_util/function/63840.cc	(.../tags/gcc_4_9_2_release)
-+++ b/src/libstdc++-v3/testsuite/20_util/function/63840.cc	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,55 @@
-+// Copyright (C) 2014 Free Software Foundation, Inc.
-+//
-+// This file is part of the GNU ISO C++ Library.  This library is free
-+// software; you can redistribute it and/or modify it under the
-+// terms of the GNU General Public License as published by the
-+// Free Software Foundation; either version 3, or (at your option)
-+// any later version.
-+
-+// This library is distributed in the hope that it will be useful,
-+// but WITHOUT ANY WARRANTY; without even the implied warranty of
-+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+// GNU General Public License for more details.
-+
-+// You should have received a copy of the GNU General Public License along
-+// with this library; see the file COPYING3.  If not see
-+// <http://www.gnu.org/licenses/>.
-+
-+// { dg-options "-std=gnu++11" }
-+
-+#include <functional>
-+#include <stdexcept>
-+#include <testsuite_hooks.h>
-+
-+struct functor
-+{
-+  functor() = default;
-+
-+  functor(const functor&)
-+  {
-+    throw std::runtime_error("test");
-+  }
-+
-+  functor(functor&& f) = default;
-+
-+  void operator()() const { }
-+};
-+
-+
-+void
-+test01()
-+{
-+  std::function<void()> f = functor{};
-+  try {
-+    auto g = f;
-+  } catch (const std::runtime_error& e) {
-+    return;
-+  }
-+  VERIFY(false);
-+}
-+
-+int
-+main()
-+{
-+  test01();
-+}
-Index: libstdc++-v3/testsuite/20_util/specialized_algorithms/uninitialized_copy/64476.cc
-===================================================================
---- a/src/libstdc++-v3/testsuite/20_util/specialized_algorithms/uninitialized_copy/64476.cc	(.../tags/gcc_4_9_2_release)
-+++ b/src/libstdc++-v3/testsuite/20_util/specialized_algorithms/uninitialized_copy/64476.cc	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,65 @@
-+// Copyright (C) 2015 Free Software Foundation, Inc.
-+//
-+// This file is part of the GNU ISO C++ Library.  This library is free
-+// software; you can redistribute it and/or modify it under the
-+// terms of the GNU General Public License as published by the
-+// Free Software Foundation; either version 3, or (at your option)
-+// any later version.
-+
-+// This library is distributed in the hope that it will be useful,
-+// but WITHOUT ANY WARRANTY; without even the implied warranty of
-+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+// GNU General Public License for more details.
-+
-+// You should have received a copy of the GNU General Public License along
-+// with this library; see the file COPYING3.  If not see
-+// <http://www.gnu.org/licenses/>.
-+
-+// { dg-options "-std=gnu++11" }
-+
-+#include <memory>
-+#include <testsuite_hooks.h>
-+
-+struct X
-+{
-+  X() = default;
-+  X(X const &) = default;
-+  X& operator=(X const&) = delete;
-+};
-+
-+static_assert(__is_trivial(X), "X is trivial");
-+
-+int constructed = 0;
-+int assigned = 0;
-+
-+struct Y
-+{
-+  Y() = default;
-+  Y(Y const &) = default;
-+  Y& operator=(Y const&) = default;
-+
-+  Y(const X&) { ++constructed; }
-+  Y& operator=(const X&)& { ++assigned; return *this; }
-+  Y& operator=(const X&)&& = delete;
-+  Y& operator=(X&&) = delete;
-+};
-+
-+static_assert(__is_trivial(Y), "Y is trivial");
-+
-+void
-+test01()
-+{
-+  X a[100];
-+  Y b[100];
-+
-+  std::uninitialized_copy(a, a+10, b);
-+
-+  VERIFY(constructed == 0);
-+  VERIFY(assigned == 10);
-+}
-+
-+int
-+main()
-+{
-+  test01();
-+}
-Index: configure.ac
-===================================================================
---- a/src/configure.ac	(.../tags/gcc_4_9_2_release)
-+++ b/src/configure.ac	(.../branches/gcc-4_9-branch)
-@@ -1658,6 +1658,9 @@
-     ISL_CHECK_VERSION(0,11)
-     if test "${gcc_cv_isl}" = no ; then
-       ISL_CHECK_VERSION(0,12)
-+      if test "${gcc_cv_isl}" = no ; then
-+        ISL_CHECK_VERSION(0,14)
-+      fi
-     fi
-   fi
-   dnl Only execute fail-action, if ISL has been requested.
-Index: ChangeLog
-===================================================================
---- a/src/ChangeLog	(.../tags/gcc_4_9_2_release)
-+++ b/src/ChangeLog	(.../branches/gcc-4_9-branch)
-@@ -1,3 +1,10 @@
-+2014-12-04  Tobias Burnus  <burnus@net-b.de>
-+
-+	* configure.ac: Permit also ISL 0.14 with CLooG.
-+	* Makefile.def: Make more dependent on mpfr, mpc, isl, and cloog.
-+	* Makefile.in: Regenerate.
-+	* configure: Regenerate.
-+
- 2014-10-30  Release Manager
- 
- 	* GCC 4.9.2 released.
-Index: configure
-===================================================================
---- a/src/configure	(.../tags/gcc_4_9_2_release)
-+++ b/src/configure	(.../branches/gcc-4_9-branch)
-@@ -6024,6 +6024,55 @@
-   fi
- 
- 
-+      if test "${gcc_cv_isl}" = no ; then
-+
-+  if test "${ENABLE_ISL_CHECK}" = yes ; then
-+    _isl_saved_CFLAGS=$CFLAGS
-+    _isl_saved_LDFLAGS=$LDFLAGS
-+    _isl_saved_LIBS=$LIBS
-+
-+    CFLAGS="${_isl_saved_CFLAGS} ${islinc} ${gmpinc}"
-+    LDFLAGS="${_isl_saved_LDFLAGS} ${isllibs}"
-+    LIBS="${_isl_saved_LIBS} -lisl"
-+
-+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking for version 0.14 of ISL" >&5
-+$as_echo_n "checking for version 0.14 of ISL... " >&6; }
-+    if test "$cross_compiling" = yes; then :
-+  gcc_cv_isl=yes
-+else
-+  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
-+/* end confdefs.h.  */
-+#include <isl/version.h>
-+   #include <string.h>
-+int
-+main ()
-+{
-+if (strncmp (isl_version (), "isl-0.14", strlen ("isl-0.14")) != 0)
-+     return 1;
-+
-+  ;
-+  return 0;
-+}
-+_ACEOF
-+if ac_fn_c_try_run "$LINENO"; then :
-+  gcc_cv_isl=yes
-+else
-+  gcc_cv_isl=no
-+fi
-+rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \
-+  conftest.$ac_objext conftest.beam conftest.$ac_ext
-+fi
-+
-+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_isl" >&5
-+$as_echo "$gcc_cv_isl" >&6; }
-+
-+    CFLAGS=$_isl_saved_CFLAGS
-+    LDFLAGS=$_isl_saved_LDFLAGS
-+    LIBS=$_isl_saved_LIBS
-+  fi
-+
-+
-+      fi
-     fi
-   fi
- 
-Index: libgcc/ChangeLog
-===================================================================
---- a/src/libgcc/ChangeLog	(.../tags/gcc_4_9_2_release)
-+++ b/src/libgcc/ChangeLog	(.../branches/gcc-4_9-branch)
-@@ -1,3 +1,35 @@
-+2014-12-09  John David Anglin  <danglin@gcc.gnu.org>
-+
-+	Backport from mainline
-+	2014-11-24  John David Anglin  <danglin@gcc.gnu.org>
-+
-+	* config/pa/linux-atomic.c (ABORT_INSTRUCTION): Use __builtin_trap()
-+	instead.
-+
-+	2014-11-21  Guy Martin  <gmsoft@tuxicoman.be>
-+	            John David Anglin  <danglin@gcc.gnu.org>
-+
-+	* config/pa/linux-atomic.c (__kernel_cmpxchg2): New.
-+	(FETCH_AND_OP_2): New.  Use for subword and double word operations.
-+	(OP_AND_FETCH_2): Likewise.
-+	(COMPARE_AND_SWAP_2): Likewise.
-+	(SYNC_LOCK_TEST_AND_SET_2): Likewise.
-+	(SYNC_LOCK_RELEASE_2): Likewise.
-+	(SUBWORD_SYNC_OP): Remove.
-+	(SUBWORD_VAL_CAS): Likewise.
-+	(SUBWORD_BOOL_CAS): Likewise.
-+	(FETCH_AND_OP_WORD): Update.
-+	Consistently use signed types.
-+
-+2014-12-09  Oleg Endo  <olegendo@gcc.gnu.org>
-+
-+	Backport from mainline
-+	2014-11-30  Oleg Endo  <olegendo@gcc.gnu.org>
-+
-+	PR target/55351
-+	* config/sh/lib1funcs.S: Check value of __SHMEDIA__ instead of checking
-+	whether it's defined.
-+
- 2014-10-30  Release Manager
- 
- 	* GCC 4.9.2 released.
-Index: libgcc/config/sh/lib1funcs.S
-===================================================================
---- a/src/libgcc/config/sh/lib1funcs.S	(.../tags/gcc_4_9_2_release)
-+++ b/src/libgcc/config/sh/lib1funcs.S	(.../branches/gcc-4_9-branch)
-@@ -1278,7 +1278,7 @@
- #endif
- 	ENDFUNC(GLOBAL(sdivsi3_2))
- #endif
--#elif defined __SHMEDIA__
-+#elif __SHMEDIA__
- /* m5compact-nofpu */
-  // clobbered: r18,r19,r20,r21,r25,tr0,tr1,tr2
- 	.mode	SHmedia
-@@ -1683,7 +1683,7 @@
-  add.l r18,r25,r0
-  blink tr0,r63
- #endif
--#elif defined (__SHMEDIA__)
-+#elif __SHMEDIA__
- /* m5compact-nofpu - more emphasis on code size than on speed, but don't
-    ignore speed altogether - div1 needs 9 cycles, subc 7 and rotcl 4.
-    So use a short shmedia loop.  */
-@@ -1707,7 +1707,7 @@
-  bnei r25,-32,tr1
-  add.l r20,r63,r0
-  blink tr2,r63
--#else /* ! defined (__SHMEDIA__) */
-+#else /* ! __SHMEDIA__ */
- LOCAL(div8):
-  div1 r5,r4
- LOCAL(div7):
-@@ -1773,7 +1773,7 @@
- #endif /* L_udivsi3 */
- 
- #ifdef L_udivdi3
--#ifdef __SHMEDIA__
-+#if __SHMEDIA__
- 	.mode	SHmedia
- 	.section	.text..SHmedia32,"ax"
- 	.align	2
-@@ -1901,7 +1901,7 @@
- #endif /* L_udivdi3 */
- 
- #ifdef L_divdi3
--#ifdef __SHMEDIA__
-+#if __SHMEDIA__
- 	.mode	SHmedia
- 	.section	.text..SHmedia32,"ax"
- 	.align	2
-@@ -1925,7 +1925,7 @@
- #endif /* L_divdi3 */
- 
- #ifdef L_umoddi3
--#ifdef __SHMEDIA__
-+#if __SHMEDIA__
- 	.mode	SHmedia
- 	.section	.text..SHmedia32,"ax"
- 	.align	2
-@@ -2054,7 +2054,7 @@
- #endif /* L_umoddi3 */
- 
- #ifdef L_moddi3
--#ifdef __SHMEDIA__
-+#if __SHMEDIA__
- 	.mode	SHmedia
- 	.section	.text..SHmedia32,"ax"
- 	.align	2
-@@ -3142,7 +3142,7 @@
- 
- #ifdef L_div_table
- #if __SH5__
--#if defined(__pic__) && defined(__SHMEDIA__)
-+#if defined(__pic__) && __SHMEDIA__
- 	.global	GLOBAL(sdivsi3)
- 	FUNC(GLOBAL(sdivsi3))
- #if __SH5__ == 32
-@@ -3215,7 +3215,7 @@
- #else /* ! __pic__ || ! __SHMEDIA__ */
- 	.section	.rodata
- #endif /* __pic__ */
--#if defined(TEXT_DATA_BUG) && defined(__pic__) && defined(__SHMEDIA__)
-+#if defined(TEXT_DATA_BUG) && defined(__pic__) && __SHMEDIA__
- 	.balign 2
- 	.type	Local_div_table,@object
- 	.size	Local_div_table,128
-Index: libgcc/config/pa/linux-atomic.c
-===================================================================
---- a/src/libgcc/config/pa/linux-atomic.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/libgcc/config/pa/linux-atomic.c	(.../branches/gcc-4_9-branch)
-@@ -41,11 +41,8 @@
-    using the kernel helper defined below.  There is no support for
-    64-bit operations yet.  */
- 
--/* A privileged instruction to crash a userspace program with SIGILL.  */
--#define ABORT_INSTRUCTION asm ("iitlbp %r0,(%sr0, %r0)")
--
- /* Determine kernel LWS function call (0=32-bit, 1=64-bit userspace).  */
--#define LWS_CAS (sizeof(unsigned long) == 4 ? 0 : 1)
-+#define LWS_CAS (sizeof(long) == 4 ? 0 : 1)
- 
- /* Kernel helper for compare-and-exchange a 32-bit value.  */
- static inline long
-@@ -64,7 +61,7 @@
- 	: "r1", "r20", "r22", "r23", "r29", "r31", "memory"
-   );
-   if (__builtin_expect (lws_errno == -EFAULT || lws_errno == -ENOSYS, 0))
--    ABORT_INSTRUCTION;
-+    __builtin_trap ();
- 
-   /* If the kernel LWS call succeeded (lws_errno == 0), lws_ret contains
-      the old value from memory.  If this value is equal to OLDVAL, the
-@@ -75,6 +72,30 @@
-   return lws_errno;
- }
- 
-+static inline long
-+__kernel_cmpxchg2 (void * oldval, void * newval, void *mem, int val_size)
-+{
-+  register unsigned long lws_mem asm("r26") = (unsigned long) (mem);
-+  register long lws_ret   asm("r28");
-+  register long lws_errno asm("r21");
-+  register unsigned long lws_old asm("r25") = (unsigned long) oldval;
-+  register unsigned long lws_new asm("r24") = (unsigned long) newval;
-+  register int lws_size asm("r23") = val_size;
-+  asm volatile (	"ble	0xb0(%%sr2, %%r0)	\n\t"
-+			"ldi	%2, %%r20		\n\t"
-+	: "=r" (lws_ret), "=r" (lws_errno)
-+	: "i" (2), "r" (lws_mem), "r" (lws_old), "r" (lws_new), "r" (lws_size)
-+	: "r1", "r20", "r22", "r29", "r31", "fr4", "memory"
-+  );
-+  if (__builtin_expect (lws_errno == -EFAULT || lws_errno == -ENOSYS, 0))
-+    __builtin_trap ();
-+
-+  /* If the kernel LWS call fails, retrun EBUSY */
-+  if (!lws_errno && lws_ret)
-+    lws_errno = -EBUSY;
-+
-+  return lws_errno;
-+}
- #define HIDDEN __attribute__ ((visibility ("hidden")))
- 
- /* Big endian masks  */
-@@ -84,69 +105,101 @@
- #define MASK_1 0xffu
- #define MASK_2 0xffffu
- 
--#define FETCH_AND_OP_WORD(OP, PFX_OP, INF_OP)				\
--  int HIDDEN								\
--  __sync_fetch_and_##OP##_4 (int *ptr, int val)				\
-+#define FETCH_AND_OP_2(OP, PFX_OP, INF_OP, TYPE, WIDTH, INDEX)		\
-+  TYPE HIDDEN								\
-+  __sync_fetch_and_##OP##_##WIDTH (TYPE *ptr, TYPE val)			\
-   {									\
--    int failure, tmp;							\
-+    TYPE tmp, newval;							\
-+    int failure;							\
- 									\
-     do {								\
-       tmp = *ptr;							\
--      failure = __kernel_cmpxchg (tmp, PFX_OP (tmp INF_OP val), ptr);	\
-+      newval = PFX_OP (tmp INF_OP val);					\
-+      failure = __kernel_cmpxchg2 (&tmp, &newval, ptr, INDEX);		\
-     } while (failure != 0);						\
- 									\
-     return tmp;								\
-   }
- 
--FETCH_AND_OP_WORD (add,   , +)
--FETCH_AND_OP_WORD (sub,   , -)
--FETCH_AND_OP_WORD (or,    , |)
--FETCH_AND_OP_WORD (and,   , &)
--FETCH_AND_OP_WORD (xor,   , ^)
--FETCH_AND_OP_WORD (nand, ~, &)
-+FETCH_AND_OP_2 (add,   , +, long long, 8, 3)
-+FETCH_AND_OP_2 (sub,   , -, long long, 8, 3)
-+FETCH_AND_OP_2 (or,    , |, long long, 8, 3)
-+FETCH_AND_OP_2 (and,   , &, long long, 8, 3)
-+FETCH_AND_OP_2 (xor,   , ^, long long, 8, 3)
-+FETCH_AND_OP_2 (nand, ~, &, long long, 8, 3)
- 
--#define NAME_oldval(OP, WIDTH) __sync_fetch_and_##OP##_##WIDTH
--#define NAME_newval(OP, WIDTH) __sync_##OP##_and_fetch_##WIDTH
-+FETCH_AND_OP_2 (add,   , +, short, 2, 1)
-+FETCH_AND_OP_2 (sub,   , -, short, 2, 1)
-+FETCH_AND_OP_2 (or,    , |, short, 2, 1)
-+FETCH_AND_OP_2 (and,   , &, short, 2, 1)
-+FETCH_AND_OP_2 (xor,   , ^, short, 2, 1)
-+FETCH_AND_OP_2 (nand, ~, &, short, 2, 1)
- 
--/* Implement both __sync_<op>_and_fetch and __sync_fetch_and_<op> for
--   subword-sized quantities.  */
-+FETCH_AND_OP_2 (add,   , +, signed char, 1, 0)
-+FETCH_AND_OP_2 (sub,   , -, signed char, 1, 0)
-+FETCH_AND_OP_2 (or,    , |, signed char, 1, 0)
-+FETCH_AND_OP_2 (and,   , &, signed char, 1, 0)
-+FETCH_AND_OP_2 (xor,   , ^, signed char, 1, 0)
-+FETCH_AND_OP_2 (nand, ~, &, signed char, 1, 0)
- 
--#define SUBWORD_SYNC_OP(OP, PFX_OP, INF_OP, TYPE, WIDTH, RETURN)	\
-+#define OP_AND_FETCH_2(OP, PFX_OP, INF_OP, TYPE, WIDTH, INDEX)		\
-   TYPE HIDDEN								\
--  NAME##_##RETURN (OP, WIDTH) (TYPE *ptr, TYPE val)			\
-+  __sync_##OP##_and_fetch_##WIDTH (TYPE *ptr, TYPE val)			\
-   {									\
--    int *wordptr = (int *) ((unsigned long) ptr & ~3);			\
--    unsigned int mask, shift, oldval, newval;				\
-+    TYPE tmp, newval;							\
-     int failure;							\
- 									\
--    shift = (((unsigned long) ptr & 3) << 3) ^ INVERT_MASK_##WIDTH;	\
--    mask = MASK_##WIDTH << shift;					\
-+    do {								\
-+      tmp = *ptr;							\
-+      newval = PFX_OP (tmp INF_OP val);					\
-+      failure = __kernel_cmpxchg2 (&tmp, &newval, ptr, INDEX);		\
-+    } while (failure != 0);						\
- 									\
-+    return PFX_OP (tmp INF_OP val);					\
-+  }
-+
-+OP_AND_FETCH_2 (add,   , +, long long, 8, 3)
-+OP_AND_FETCH_2 (sub,   , -, long long, 8, 3)
-+OP_AND_FETCH_2 (or,    , |, long long, 8, 3)
-+OP_AND_FETCH_2 (and,   , &, long long, 8, 3)
-+OP_AND_FETCH_2 (xor,   , ^, long long, 8, 3)
-+OP_AND_FETCH_2 (nand, ~, &, long long, 8, 3)
-+
-+OP_AND_FETCH_2 (add,   , +, short, 2, 1)
-+OP_AND_FETCH_2 (sub,   , -, short, 2, 1)
-+OP_AND_FETCH_2 (or,    , |, short, 2, 1)
-+OP_AND_FETCH_2 (and,   , &, short, 2, 1)
-+OP_AND_FETCH_2 (xor,   , ^, short, 2, 1)
-+OP_AND_FETCH_2 (nand, ~, &, short, 2, 1)
-+
-+OP_AND_FETCH_2 (add,   , +, signed char, 1, 0)
-+OP_AND_FETCH_2 (sub,   , -, signed char, 1, 0)
-+OP_AND_FETCH_2 (or,    , |, signed char, 1, 0)
-+OP_AND_FETCH_2 (and,   , &, signed char, 1, 0)
-+OP_AND_FETCH_2 (xor,   , ^, signed char, 1, 0)
-+OP_AND_FETCH_2 (nand, ~, &, signed char, 1, 0)
-+
-+#define FETCH_AND_OP_WORD(OP, PFX_OP, INF_OP)				\
-+  int HIDDEN								\
-+  __sync_fetch_and_##OP##_4 (int *ptr, int val)				\
-+  {									\
-+    int failure, tmp;							\
-+									\
-     do {								\
--      oldval = *wordptr;						\
--      newval = ((PFX_OP (((oldval & mask) >> shift)			\
--                         INF_OP (unsigned int) val)) << shift) & mask;	\
--      newval |= oldval & ~mask;						\
--      failure = __kernel_cmpxchg (oldval, newval, wordptr);		\
-+      tmp = *ptr;							\
-+      failure = __kernel_cmpxchg (tmp, PFX_OP (tmp INF_OP val), ptr);	\
-     } while (failure != 0);						\
- 									\
--    return (RETURN & mask) >> shift;					\
-+    return tmp;								\
-   }
- 
--SUBWORD_SYNC_OP (add,   , +, unsigned short, 2, oldval)
--SUBWORD_SYNC_OP (sub,   , -, unsigned short, 2, oldval)
--SUBWORD_SYNC_OP (or,    , |, unsigned short, 2, oldval)
--SUBWORD_SYNC_OP (and,   , &, unsigned short, 2, oldval)
--SUBWORD_SYNC_OP (xor,   , ^, unsigned short, 2, oldval)
--SUBWORD_SYNC_OP (nand, ~, &, unsigned short, 2, oldval)
-+FETCH_AND_OP_WORD (add,   , +)
-+FETCH_AND_OP_WORD (sub,   , -)
-+FETCH_AND_OP_WORD (or,    , |)
-+FETCH_AND_OP_WORD (and,   , &)
-+FETCH_AND_OP_WORD (xor,   , ^)
-+FETCH_AND_OP_WORD (nand, ~, &)
- 
--SUBWORD_SYNC_OP (add,   , +, unsigned char, 1, oldval)
--SUBWORD_SYNC_OP (sub,   , -, unsigned char, 1, oldval)
--SUBWORD_SYNC_OP (or,    , |, unsigned char, 1, oldval)
--SUBWORD_SYNC_OP (and,   , &, unsigned char, 1, oldval)
--SUBWORD_SYNC_OP (xor,   , ^, unsigned char, 1, oldval)
--SUBWORD_SYNC_OP (nand, ~, &, unsigned char, 1, oldval)
--
- #define OP_AND_FETCH_WORD(OP, PFX_OP, INF_OP)				\
-   int HIDDEN								\
-   __sync_##OP##_and_fetch_4 (int *ptr, int val)				\
-@@ -168,20 +221,42 @@
- OP_AND_FETCH_WORD (xor,   , ^)
- OP_AND_FETCH_WORD (nand, ~, &)
- 
--SUBWORD_SYNC_OP (add,   , +, unsigned short, 2, newval)
--SUBWORD_SYNC_OP (sub,   , -, unsigned short, 2, newval)
--SUBWORD_SYNC_OP (or,    , |, unsigned short, 2, newval)
--SUBWORD_SYNC_OP (and,   , &, unsigned short, 2, newval)
--SUBWORD_SYNC_OP (xor,   , ^, unsigned short, 2, newval)
--SUBWORD_SYNC_OP (nand, ~, &, unsigned short, 2, newval)
-+typedef unsigned char bool;
- 
--SUBWORD_SYNC_OP (add,   , +, unsigned char, 1, newval)
--SUBWORD_SYNC_OP (sub,   , -, unsigned char, 1, newval)
--SUBWORD_SYNC_OP (or,    , |, unsigned char, 1, newval)
--SUBWORD_SYNC_OP (and,   , &, unsigned char, 1, newval)
--SUBWORD_SYNC_OP (xor,   , ^, unsigned char, 1, newval)
--SUBWORD_SYNC_OP (nand, ~, &, unsigned char, 1, newval)
-+#define COMPARE_AND_SWAP_2(TYPE, WIDTH, INDEX)				\
-+  TYPE HIDDEN								\
-+  __sync_val_compare_and_swap_##WIDTH (TYPE *ptr, TYPE oldval,		\
-+				       TYPE newval)			\
-+  {									\
-+    TYPE actual_oldval;							\
-+    int fail;								\
-+									\
-+    while (1)								\
-+      {									\
-+	actual_oldval = *ptr;						\
-+									\
-+	if (__builtin_expect (oldval != actual_oldval, 0))		\
-+	  return actual_oldval;						\
-+									\
-+	fail = __kernel_cmpxchg2 (&actual_oldval, &newval, ptr, INDEX);	\
-+									\
-+	if (__builtin_expect (!fail, 1))				\
-+	  return actual_oldval;						\
-+    }									\
-+  }									\
-+									\
-+  bool HIDDEN								\
-+  __sync_bool_compare_and_swap_##WIDTH (TYPE *ptr, TYPE oldval,		\
-+					TYPE newval)			\
-+  {									\
-+    int failure = __kernel_cmpxchg2 (&oldval, &newval, ptr, INDEX);	\
-+    return (failure != 0);						\
-+  }
- 
-+COMPARE_AND_SWAP_2 (long long, 8, 3)
-+COMPARE_AND_SWAP_2 (short, 2, 1)
-+COMPARE_AND_SWAP_2 (char, 1, 0)
-+
- int HIDDEN
- __sync_val_compare_and_swap_4 (int *ptr, int oldval, int newval)
- {
-@@ -201,41 +276,6 @@
-     }
- }
- 
--#define SUBWORD_VAL_CAS(TYPE, WIDTH)					\
--  TYPE HIDDEN								\
--  __sync_val_compare_and_swap_##WIDTH (TYPE *ptr, TYPE oldval,		\
--				       TYPE newval)			\
--  {									\
--    int *wordptr = (int *)((unsigned long) ptr & ~3), fail;		\
--    unsigned int mask, shift, actual_oldval, actual_newval;		\
--									\
--    shift = (((unsigned long) ptr & 3) << 3) ^ INVERT_MASK_##WIDTH;	\
--    mask = MASK_##WIDTH << shift;					\
--									\
--    while (1)								\
--      {									\
--	actual_oldval = *wordptr;					\
--									\
--	if (__builtin_expect (((actual_oldval & mask) >> shift)		\
--			      != (unsigned int) oldval, 0))		\
--	  return (actual_oldval & mask) >> shift;			\
--									\
--	actual_newval = (actual_oldval & ~mask)				\
--			| (((unsigned int) newval << shift) & mask);	\
--									\
--	fail = __kernel_cmpxchg (actual_oldval, actual_newval,		\
--				 wordptr);				\
--									\
--	if (__builtin_expect (!fail, 1))				\
--	  return (actual_oldval & mask) >> shift;			\
--      }									\
--  }
--
--SUBWORD_VAL_CAS (unsigned short, 2)
--SUBWORD_VAL_CAS (unsigned char,  1)
--
--typedef unsigned char bool;
--
- bool HIDDEN
- __sync_bool_compare_and_swap_4 (int *ptr, int oldval, int newval)
- {
-@@ -243,18 +283,24 @@
-   return (failure == 0);
- }
- 
--#define SUBWORD_BOOL_CAS(TYPE, WIDTH)					\
--  bool HIDDEN								\
--  __sync_bool_compare_and_swap_##WIDTH (TYPE *ptr, TYPE oldval,		\
--					TYPE newval)			\
-+#define SYNC_LOCK_TEST_AND_SET_2(TYPE, WIDTH, INDEX)			\
-+TYPE HIDDEN								\
-+  __sync_lock_test_and_set_##WIDTH (TYPE *ptr, TYPE val)		\
-   {									\
--    TYPE actual_oldval							\
--      = __sync_val_compare_and_swap_##WIDTH (ptr, oldval, newval);	\
--    return (oldval == actual_oldval);					\
-+    TYPE oldval;							\
-+    int failure;							\
-+									\
-+    do {								\
-+      oldval = *ptr;							\
-+      failure = __kernel_cmpxchg2 (&oldval, &val, ptr, INDEX);		\
-+    } while (failure != 0);						\
-+									\
-+    return oldval;							\
-   }
- 
--SUBWORD_BOOL_CAS (unsigned short, 2)
--SUBWORD_BOOL_CAS (unsigned char,  1)
-+SYNC_LOCK_TEST_AND_SET_2 (long long, 8, 3)
-+SYNC_LOCK_TEST_AND_SET_2 (short, 2, 1)
-+SYNC_LOCK_TEST_AND_SET_2 (signed char, 1, 0)
- 
- int HIDDEN
- __sync_lock_test_and_set_4 (int *ptr, int val)
-@@ -269,37 +315,29 @@
-   return oldval;
- }
- 
--#define SUBWORD_TEST_AND_SET(TYPE, WIDTH)				\
--  TYPE HIDDEN								\
--  __sync_lock_test_and_set_##WIDTH (TYPE *ptr, TYPE val)		\
--  {									\
--    int failure;							\
--    unsigned int oldval, newval, shift, mask;				\
--    int *wordptr = (int *) ((unsigned long) ptr & ~3);			\
--									\
--    shift = (((unsigned long) ptr & 3) << 3) ^ INVERT_MASK_##WIDTH;	\
--    mask = MASK_##WIDTH << shift;					\
--									\
--    do {								\
--      oldval = *wordptr;						\
--      newval = (oldval & ~mask)						\
--	       | (((unsigned int) val << shift) & mask);		\
--      failure = __kernel_cmpxchg (oldval, newval, wordptr);		\
--    } while (failure != 0);						\
--									\
--    return (oldval & mask) >> shift;					\
-+#define SYNC_LOCK_RELEASE_2(TYPE, WIDTH, INDEX)			\
-+  void HIDDEN							\
-+  __sync_lock_release_##WIDTH (TYPE *ptr)			\
-+  {								\
-+    TYPE failure, oldval, zero = 0;				\
-+								\
-+    do {							\
-+      oldval = *ptr;						\
-+      failure = __kernel_cmpxchg2 (&oldval, &zero, ptr, INDEX);	\
-+    } while (failure != 0);					\
-   }
- 
--SUBWORD_TEST_AND_SET (unsigned short, 2)
--SUBWORD_TEST_AND_SET (unsigned char,  1)
-+SYNC_LOCK_RELEASE_2 (long long, 8, 3)
-+SYNC_LOCK_RELEASE_2 (short, 2, 1)
-+SYNC_LOCK_RELEASE_2 (signed char, 1, 0)
- 
--#define SYNC_LOCK_RELEASE(TYPE, WIDTH)					\
--  void HIDDEN								\
--  __sync_lock_release_##WIDTH (TYPE *ptr)				\
--  {									\
--    *ptr = 0;								\
--  }
-+void HIDDEN
-+__sync_lock_release_4 (int *ptr)
-+{
-+  int failure, oldval;
- 
--SYNC_LOCK_RELEASE (int,   4)
--SYNC_LOCK_RELEASE (short, 2)
--SYNC_LOCK_RELEASE (char,  1)
-+  do {
-+    oldval = *ptr;
-+    failure = __kernel_cmpxchg (oldval, 0, ptr);
-+  } while (failure != 0);
-+}
-Index: gcc/tree-vrp.c
-===================================================================
---- a/src/gcc/tree-vrp.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/tree-vrp.c	(.../branches/gcc-4_9-branch)
-@@ -7172,7 +7172,7 @@
-       tree type = TREE_TYPE (op0);
-       value_range_t *vr0 = get_value_range (op0);
- 
--      if (vr0->type != VR_VARYING
-+      if (vr0->type == VR_RANGE
- 	  && INTEGRAL_TYPE_P (type)
- 	  && vrp_val_is_min (vr0->min)
- 	  && vrp_val_is_max (vr0->max)
-@@ -9377,8 +9377,10 @@
-     }
-   else
-     {
--      tree r1 = int_const_binop (subcode, vr0.min, vr1.min);
--      tree r2 = int_const_binop (subcode, vr0.max, vr1.max);
-+      tree r1 = int_const_binop (subcode, vr0.min,
-+				 subcode == MINUS_EXPR ? vr1.max : vr1.min);
-+      tree r2 = int_const_binop (subcode, vr0.max,
-+				 subcode == MINUS_EXPR ? vr1.min : vr1.max);
-       if (r1 == NULL_TREE || TREE_OVERFLOW (r1)
- 	  || r2 == NULL_TREE || TREE_OVERFLOW (r2))
- 	return false;
-Index: gcc/tree-ssa-tail-merge.c
-===================================================================
---- a/src/gcc/tree-ssa-tail-merge.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/tree-ssa-tail-merge.c	(.../branches/gcc-4_9-branch)
-@@ -314,7 +314,8 @@
- 
-   if (gimple_vdef (stmt) != NULL_TREE
-       || gimple_has_side_effects (stmt)
--      || gimple_could_trap_p_1 (stmt, false, false))
-+      || gimple_could_trap_p_1 (stmt, false, false)
-+      || gimple_vuse (stmt) != NULL_TREE)
-     return false;
- 
-   def_p = SINGLE_SSA_DEF_OPERAND (stmt, SSA_OP_DEF);
-@@ -1164,7 +1165,8 @@
- 						 gimple_assign_rhs1 (s2)));
-       else if (TREE_CODE (lhs1) == SSA_NAME
- 	       && TREE_CODE (lhs2) == SSA_NAME)
--	return vn_valueize (lhs1) == vn_valueize (lhs2);
-+	return operand_equal_p (gimple_assign_rhs1 (s1),
-+				gimple_assign_rhs1 (s2), 0);
-       return false;
- 
-     case GIMPLE_COND:
-Index: gcc/c-family/c-ubsan.c
-===================================================================
---- a/src/gcc/c-family/c-ubsan.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/c-family/c-ubsan.c	(.../branches/gcc-4_9-branch)
-@@ -98,19 +98,19 @@
-   tree op1_utype = unsigned_type_for (type1);
-   HOST_WIDE_INT op0_prec = TYPE_PRECISION (type0);
-   tree uprecm1 = build_int_cst (op1_utype, op0_prec - 1);
--  tree precm1 = build_int_cst (type1, op0_prec - 1);
- 
-   t = fold_convert_loc (loc, op1_utype, op1);
-   t = fold_build2 (GT_EXPR, boolean_type_node, t, uprecm1);
- 
-   /* For signed x << y, in C99/C11, the following:
--     (unsigned) x >> (precm1 - y)
-+     (unsigned) x >> (uprecm1 - y)
-      if non-zero, is undefined.  */
-   if (code == LSHIFT_EXPR
-       && !TYPE_UNSIGNED (type0)
-       && flag_isoc99)
-     {
--      tree x = fold_build2 (MINUS_EXPR, integer_type_node, precm1, op1);
-+      tree x = fold_build2 (MINUS_EXPR, unsigned_type_node, uprecm1,
-+			    fold_convert (op1_utype, op1));
-       tt = fold_convert_loc (loc, unsigned_type_for (type0), op0);
-       tt = fold_build2 (RSHIFT_EXPR, TREE_TYPE (tt), tt, x);
-       tt = fold_build2 (NE_EXPR, boolean_type_node, tt,
-@@ -118,13 +118,14 @@
-     }
- 
-   /* For signed x << y, in C++11/C++14, the following:
--     x < 0 || ((unsigned) x >> (precm1 - y))
-+     x < 0 || ((unsigned) x >> (uprecm1 - y))
-      if > 1, is undefined.  */
-   if (code == LSHIFT_EXPR
-       && !TYPE_UNSIGNED (TREE_TYPE (op0))
-       && (cxx_dialect == cxx11 || cxx_dialect == cxx1y))
-     {
--      tree x = fold_build2 (MINUS_EXPR, integer_type_node, precm1, op1);
-+      tree x = fold_build2 (MINUS_EXPR, unsigned_type_node, uprecm1,
-+			    fold_convert (op1_utype, op1));
-       tt = fold_convert_loc (loc, unsigned_type_for (type0), op0);
-       tt = fold_build2 (RSHIFT_EXPR, TREE_TYPE (tt), tt, x);
-       tt = fold_build2 (GT_EXPR, boolean_type_node, tt,
-Index: gcc/DATESTAMP
-===================================================================
---- a/src/gcc/DATESTAMP	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/DATESTAMP	(.../branches/gcc-4_9-branch)
-@@ -1 +1 @@
--20141030
-+20150120
-Index: gcc/tree-ssa-strlen.c
-===================================================================
---- a/src/gcc/tree-ssa-strlen.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/tree-ssa-strlen.c	(.../branches/gcc-4_9-branch)
-@@ -1856,7 +1856,7 @@
- 	    break;
- 	  }
-     }
--  else if (is_gimple_assign (stmt))
-+  else if (is_gimple_assign (stmt) && !gimple_clobber_p (stmt))
-     {
-       tree lhs = gimple_assign_lhs (stmt);
- 
-Index: gcc/tree.c
-===================================================================
---- a/src/gcc/tree.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/tree.c	(.../branches/gcc-4_9-branch)
-@@ -1120,7 +1120,7 @@
-   const_tree const t = (const_tree) x;
- 
-   return (TREE_INT_CST_HIGH (t) ^ TREE_INT_CST_LOW (t)
--	  ^ htab_hash_pointer (TREE_TYPE (t)));
-+	  ^ TYPE_UID (TREE_TYPE (t)));
- }
- 
- /* Return nonzero if the value represented by *X (an INTEGER_CST tree node)
-@@ -6215,8 +6215,11 @@
-       else if (TYPE_CANONICAL (type) != type)
- 	/* Build the underlying canonical type, since it is different
- 	   from TYPE. */
--	TYPE_CANONICAL (t) = build_qualified_type (TYPE_CANONICAL (type),
--						   type_quals);
-+	{
-+	  tree c = build_qualified_type (TYPE_CANONICAL (type),
-+					 type_quals);
-+	  TYPE_CANONICAL (t) = TYPE_CANONICAL (c);
-+	}
-       else
- 	/* T is its own canonical type. */
- 	TYPE_CANONICAL (t) = t;
-Index: gcc/reload.c
-===================================================================
---- a/src/gcc/reload.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/reload.c	(.../branches/gcc-4_9-branch)
-@@ -1622,6 +1622,7 @@
- 					       end_hard_regno (rel_mode,
- 							       regno),
- 					       PATTERN (this_insn), inloc)
-+	    && ! find_reg_fusage (this_insn, USE, XEXP (note, 0))
- 	    /* If this is also an output reload, IN cannot be used as
- 	       the reload register if it is set in this insn unless IN
- 	       is also OUT.  */
-Index: gcc/rtlanal.c
-===================================================================
---- a/src/gcc/rtlanal.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/rtlanal.c	(.../branches/gcc-4_9-branch)
-@@ -873,6 +873,17 @@
- int
- reg_set_p (const_rtx reg, const_rtx insn)
- {
-+  /* After delay slot handling, call and branch insns might be in a
-+     sequence.  Check all the elements there.  */
-+  if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE)
-+    {
-+      for (int i = 0; i < XVECLEN (PATTERN (insn), 0); ++i)
-+	if (reg_set_p (reg, XVECEXP (PATTERN (insn), 0, i)))
-+	  return true;
-+
-+      return false;
-+    }
-+
-   /* We can be passed an insn or part of one.  If we are passed an insn,
-      check if a side-effect of the insn clobbers REG.  */
-   if (INSN_P (insn)
-@@ -884,7 +895,7 @@
- 					       GET_MODE (reg), REGNO (reg)))
- 		  || MEM_P (reg)
- 		  || find_reg_fusage (insn, CLOBBER, reg)))))
--    return 1;
-+    return true;
- 
-   return set_of (reg, insn) != NULL_RTX;
- }
-Index: gcc/configure
-===================================================================
---- a/src/gcc/configure	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/configure	(.../branches/gcc-4_9-branch)
-@@ -27851,8 +27851,48 @@
- 
- $as_echo "#define HAVE_cloog 1" >>confdefs.h
- 
-+
-+  # Check whether isl_schedule_constraints_compute_schedule is available;
-+  # it's new in ISL-0.13.
-+  saved_CFLAGS="$CFLAGS"
-+  CFLAGS="$CFLAGS $ISLINC"
-+  saved_LIBS="$LIBS"
-+  LIBS="$LIBS $CLOOGLIBS $ISLLIBS $GMPLIBS"
-+
-+  { $as_echo "$as_me:${as_lineno-$LINENO}: checking Checking for isl_schedule_constraints_compute_schedule" >&5
-+$as_echo_n "checking Checking for isl_schedule_constraints_compute_schedule... " >&6; }
-+  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
-+/* end confdefs.h.  */
-+#include <isl/schedule.h>
-+int
-+main ()
-+{
-+isl_schedule_constraints_compute_schedule (NULL);
-+  ;
-+  return 0;
-+}
-+_ACEOF
-+if ac_fn_c_try_link "$LINENO"; then :
-+  ac_has_isl_schedule_constraints_compute_schedule=yes
-+else
-+  ac_has_isl_schedule_constraints_compute_schedule=no
- fi
-+rm -f core conftest.err conftest.$ac_objext \
-+    conftest$ac_exeext conftest.$ac_ext
-+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_has_isl_schedule_constraints_compute_schedule" >&5
-+$as_echo "$ac_has_isl_schedule_constraints_compute_schedule" >&6; }
- 
-+  LIBS="$saved_LIBS"
-+  CFLAGS="$saved_CFLAGS"
-+
-+  if test x"$ac_has_isl_schedule_constraints_compute_schedule" = x"yes"; then
-+
-+$as_echo "#define HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE 1" >>confdefs.h
-+
-+  fi
-+fi
-+
-+
- # Check for plugin support
- # Check whether --enable-plugin was given.
- if test "${enable_plugin+set}" = set; then :
-Index: gcc/fold-const.c
-===================================================================
---- a/src/gcc/fold-const.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/fold-const.c	(.../branches/gcc-4_9-branch)
-@@ -9024,7 +9024,8 @@
-       /* If the constant operation overflowed this can be
- 	 simplified as a comparison against INT_MAX/INT_MIN.  */
-       if (TREE_CODE (lhs) == INTEGER_CST
--	  && TREE_OVERFLOW (lhs))
-+	  && TREE_OVERFLOW (lhs)
-+	  && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (arg0)))
- 	{
- 	  int const1_sgn = tree_int_cst_sgn (const1);
- 	  enum tree_code code2 = code;
-@@ -13295,7 +13296,7 @@
- 	  tree itype = TREE_TYPE (arg00);
- 	  if (TREE_INT_CST_HIGH (arg01) == 0
- 	      && TREE_INT_CST_LOW (arg01)
--		 == (unsigned HOST_WIDE_INT) (TYPE_PRECISION (itype) - 1))
-+		 == (unsigned HOST_WIDE_INT) (element_precision (itype) - 1))
- 	    {
- 	      if (TYPE_UNSIGNED (itype))
- 		{
-Index: gcc/omp-low.c
-===================================================================
---- a/src/gcc/omp-low.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/omp-low.c	(.../branches/gcc-4_9-branch)
-@@ -11181,24 +11181,24 @@
-   if (orig_rettype == void_type_node)
-     return NULL_TREE;
-   TREE_TYPE (fndecl) = build_distinct_type_copy (TREE_TYPE (fndecl));
--  if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (fndecl)))
--      || POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (fndecl))))
-+  t = TREE_TYPE (TREE_TYPE (fndecl));
-+  if (INTEGRAL_TYPE_P (t) || POINTER_TYPE_P (t))
-     veclen = node->simdclone->vecsize_int;
-   else
-     veclen = node->simdclone->vecsize_float;
--  veclen /= GET_MODE_BITSIZE (TYPE_MODE (TREE_TYPE (TREE_TYPE (fndecl))));
-+  veclen /= GET_MODE_BITSIZE (TYPE_MODE (t));
-   if (veclen > node->simdclone->simdlen)
-     veclen = node->simdclone->simdlen;
-+  if (POINTER_TYPE_P (t))
-+    t = pointer_sized_int_node;
-   if (veclen == node->simdclone->simdlen)
--    TREE_TYPE (TREE_TYPE (fndecl))
--      = build_vector_type (TREE_TYPE (TREE_TYPE (fndecl)),
--			   node->simdclone->simdlen);
-+    t = build_vector_type (t, node->simdclone->simdlen);
-   else
-     {
--      t = build_vector_type (TREE_TYPE (TREE_TYPE (fndecl)), veclen);
-+      t = build_vector_type (t, veclen);
-       t = build_array_type_nelts (t, node->simdclone->simdlen / veclen);
--      TREE_TYPE (TREE_TYPE (fndecl)) = t;
-     }
-+  TREE_TYPE (TREE_TYPE (fndecl)) = t;
-   if (!node->definition)
-     return NULL_TREE;
- 
-@@ -11287,7 +11287,10 @@
- 	  if (veclen > node->simdclone->simdlen)
- 	    veclen = node->simdclone->simdlen;
- 	  adj.arg_prefix = "simd";
--	  adj.type = build_vector_type (parm_type, veclen);
-+	  if (POINTER_TYPE_P (parm_type))
-+	    adj.type = build_vector_type (pointer_sized_int_node, veclen);
-+	  else
-+	    adj.type = build_vector_type (parm_type, veclen);
- 	  node->simdclone->args[i].vector_type = adj.type;
- 	  for (j = veclen; j < node->simdclone->simdlen; j += veclen)
- 	    {
-@@ -11328,7 +11331,10 @@
-       veclen /= GET_MODE_BITSIZE (TYPE_MODE (base_type));
-       if (veclen > node->simdclone->simdlen)
- 	veclen = node->simdclone->simdlen;
--      adj.type = build_vector_type (base_type, veclen);
-+      if (POINTER_TYPE_P (base_type))
-+	adj.type = build_vector_type (pointer_sized_int_node, veclen);
-+      else
-+	adj.type = build_vector_type (base_type, veclen);
-       adjustments.safe_push (adj);
- 
-       for (j = veclen; j < node->simdclone->simdlen; j += veclen)
-Index: gcc/ChangeLog
-===================================================================
---- a/src/gcc/ChangeLog	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/ChangeLog	(.../branches/gcc-4_9-branch)
-@@ -1,3 +1,780 @@
-+2015-01-15  Martin Liska  <mliska@suse.cz>
-+
-+	Backport from mainline
-+	2014-11-27  Richard Biener  <rguenther@suse.de>
-+
-+	PR middle-end/63704
-+	* alias.c (mems_in_disjoint_alias_sets_p): Remove assert
-+	and instead return false when !fstrict-aliasing.
-+
-+2015-01-15  Eric Botcazou  <ebotcazou@adacore.com>
-+
-+	* expr.c (expand_expr_real_1) <normal_inner_ref>: Use the expression to
-+	set the memory attributes in all cases but clear MEM_EXPR if need be.
-+
-+2015-01-14  Jakub Jelinek  <jakub@redhat.com>
-+
-+	Backported from mainline
-+	2015-01-12  Jakub Jelinek  <jakub@redhat.com>
-+
-+	PR target/64513
-+	* config/i386/i386.c (ix86_expand_prologue): Add
-+	REG_FRAME_RELATED_EXPR to %rax and %r10 pushes.
-+
-+	2015-01-13  Jakub Jelinek  <jakub@redhat.com>
-+
-+	PR rtl-optimization/64286
-+	* ree.c (combine_reaching_defs): Move part of comment earlier,
-+	remove !SCALAR_INT_MODE_P check.
-+	(add_removable_extension): Don't add vector mode
-+	extensions if all uses of the source register aren't the same
-+	vector extensions.
-+
-+	2015-01-12  Jakub Jelinek  <jakub@redhat.com>
-+
-+	PR tree-optimization/64563
-+	* tree-vrp.c (vrp_evaluate_conditional): Check for VR_RANGE
-+	instead of != VR_VARYING.
-+
-+2015-01-14  Marek Polacek  <polacek@redhat.com>
-+
-+	Backport from mainline
-+	2015-01-13  Marek Polacek  <polacek@redhat.com>
-+
-+	PR middle-end/64391
-+	* trans-mem.c (get_attrs_for): Return NULL_TREE if X is NULL_TREE.
-+
-+2015-01-13  Marc Glisse  <marc.glisse@inria.fr>
-+
-+	PR c++/54442
-+	* tree.c (build_qualified_type): Use a canonical type for
-+	TYPE_CANONICAL.
-+
-+2015-01-13  Pat Haugen  <pthaugen@us.ibm.com>
-+
-+	Backport from mainline
-+	2014-12-20  Segher Boessenkool  <segher@kernel.crashing.org>
-+
-+	PR target/64358
-+	* config/rs6000/rs6000.c (rs6000_split_logical_inner): Swap the
-+	input operands if only the second is inverted.
-+	* config/rs6000/rs6000.md (*boolc<mode>3_internal1 for BOOL_128):
-+	Swap BOOL_REGS_OP1 and BOOL_REGS_OP2.  Correct arguments to
-+	rs6000_split_logical.
-+	(*boolc<mode>3_internal2 for TI2): Swap operands[1] and operands[2].
-+
-+2015-01-13  Renlin Li  <renlin.li@arm.com>
-+
-+	Backport from mainline:
-+	2014-11-19 Renlin Li <renlin.li@arm.com>
-+
-+	PR target/63424
-+	* config/aarch64/aarch64-simd.md (<su><maxmin>v2di3): New.
-+
-+2015-01-13  Oleg Endo  <olegendo@gcc.gnu.org>
-+
-+	Backport form mainline
-+	2015-01-13  Oleg Endo  <olegendo@gcc.gnu.org>
-+
-+	PR target/64479
-+	* rtlanal.c (set_reg_p): Handle SEQUENCE constructs.
-+
-+2015-01-09  Jakub Jelinek  <jakub@redhat.com>
-+
-+	PR rtl-optimization/64536
-+	* cfgrtl.c (rtl_tidy_fallthru_edge): Handle removal of degenerate
-+	tablejumps.
-+
-+2015-01-09  Michael Meissner  <meissner@linux.vnet.ibm.com>
-+
-+	Backport from mainline:
-+	2015-01-06  Michael Meissner  <meissner@linux.vnet.ibm.com>
-+
-+	PR target/64505
-+	* config/rs6000/rs6000.c (rs6000_secondary_reload): Return the
-+	correct reload handler if -m32 -mpowerpc64 is used.
-+
-+2015-01-09  Sebastian Huber  <sebastian.huber@embedded-brains.de>
-+
-+	Backport from mainline:
-+	2015-01-09  Sebastian Huber  <sebastian.huber@embedded-brains.de>
-+
-+	* config/rs6000/rtems.h (CPP_OS_RTEMS_SPEC): Define __PPC_CPU_E6500__
-+	for -mcpu=e6500.
-+	* config/rs6000/t-rtems: Add e6500 multilibs.
-+
-+2015-01-09  Sebastian Huber  <sebastian.huber@embedded-brains.de>
-+
-+	Backport from mainline:
-+	2015-01-09  Sebastian Huber  <sebastian.huber@embedded-brains.de>
-+
-+	* config/rs6000/t-rtems: Add -mno-spe to soft-float multilib for
-+	MPC8540.
-+
-+2015-01-09  Sebastian Huber  <sebastian.huber@embedded-brains.de>
-+
-+	Backport from mainline:
-+	2015-01-09  Sebastian Huber  <sebastian.huber@embedded-brains.de>
-+
-+	* config/rs6000/t-rtems: Use MULTILIB_REQUIRED instead of
-+	MULTILIB_EXCEPTIONS.
-+
-+2015-01-09  Renlin Li  <renlin.li@arm.com>
-+
-+	Backport from mainline:
-+	2014-08-12 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
-+
-+	PR target/61413
-+	* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Fix definition
-+	of __ARM_SIZEOF_WCHAR_T.
-+
-+2015-01-08  Christian Bruel  <christian.bruel@st.com>
-+
-+	PR target/64507
-+	* config/sh/sh-mem.cc (sh_expand_cmpnstr): Check 0 length.
-+
-+2015-01-03  John David Anglin  <danglin@gcc.gnu.org>
-+
-+	* config/pa/pa.md (decrement_and_branch_until_zero): Use `Q' constraint
-+	instead of `m' constraint.  Likewise for unnamed movb comparison
-+	patterns using reg_before_reload_operand predicate.
-+	* config/pa/predicates.md (reg_before_reload_operand): Tighten
-+	predicate to reject register index and LO_SUM DLT memory forms
-+	after reload.
-+
-+2014-12-27  H.J. Lu  <hongjiu.lu@intel.com>
-+
-+	Backport from mainline:
-+	2014-12-27  H.J. Lu  <hongjiu.lu@intel.com>
-+
-+	PR target/64409
-+	* config/i386/i386.c (ix86_function_type_abi): Issue an error
-+	when ms_abi attribute is used with x32.
-+
-+2014-12-27  Uros Bizjak  <ubizjak@gmail.com>
-+
-+	* config/i386/mmx.md (*vec_extractv2sf_1): Do not emit unpckhps.
-+	Emit movshdup for SSE3 and shufps otherwise.
-+	(*vec_extractv2si_1): Do not emit punpckhdq and unpckhps.
-+	Emit pshufd for SSE2 and shufps otherwise.
-+
-+2014-12-24  Nick Clifton  <nickc@redhat.com>
-+
-+	Backport from mainline:
-+	2014-06-13  Nick Clifton  <nickc@redhat.com>
-+
-+	* config/rx/rx.h (JUMP_ALIGN): Return the log value if user
-+	requested alignment is active.
-+	(LABEL_ALIGN): Likewise.
-+	(LOOP_ALIGN): Likewise.
-+
-+	2014-03-25  Nick Clifton  <nickc@redhat.com>
-+
-+	* config/rx/rx.c (rx_print_operand): Allow R operator to accept
-+	SImode values.
-+
-+2014-12-17  Ulrich Weigand  <Ulrich.Weigand@de.ibm.com>
-+
-+	Backport from mainline
-+	2014-12-03  Ulrich Weigand  <Ulrich.Weigand@de.ibm.com>
-+
-+	PR rtl-optimization/64010
-+	* reload.c (push_reload): Before reusing a register contained
-+	in an operand as input reload register, ensure that it is not
-+	used in CALL_INSN_FUNCTION_USAGE.
-+
-+2014-12-15  Jakub Jelinek  <jakub@redhat.com>
-+
-+	PR sanitizer/64265
-+	* tsan.c (instrument_func_entry): Insert __tsan_func_entry
-+	call on edge from entry block to single succ instead
-+	of after labels of single succ of entry block.
-+
-+2014-12-14  H.J. Lu  <hongjiu.lu@intel.com>
-+
-+	Backported from mainline
-+	2014-12-14  H.J. Lu  <hongjiu.lu@intel.com>
-+
-+	PR rtl-optimization/64037
-+	* combine.c (setup_incoming_promotions): Pass the argument
-+	before any promotions happen to promote_function_mode.
-+
-+2014-12-14  H.J. Lu  <hongjiu.lu@intel.com>
-+
-+	Backported from mainline
-+	2014-12-06  H.J. Lu  <hongjiu.lu@intel.com>
-+
-+	PR target/64200
-+	* config/i386/i386.c (decide_alg): Don't assert "alg != libcall"
-+	for TARGET_INLINE_STRINGOPS_DYNAMICALLY.
-+
-+2014-12-13  Jakub Jelinek  <jakub@redhat.com>
-+
-+	Backported from mainline
-+	2014-12-12  Jakub Jelinek  <jakub@redhat.com>
-+
-+	PR tree-optimization/64269
-+	* tree-ssa-forwprop.c (simplify_builtin_call): Bail out if
-+	len2 or diff are too large.
-+
-+2014-12-11  Eric Botcazou  <ebotcazou@adacore.com>
-+
-+	* doc/md.texi (Insn Lengths): Fix description of (pc).
-+
-+2014-12-11  Renlin Li  <renlin.li@arm.com>
-+
-+	Backport from mainline
-+	2014-12-11  Renlin Li  <renlin.li@arm.com>
-+
-+	* config/aarch64/aarch64.c (aarch64_parse_cpu): Don't define
-+	selected_tune.
-+	(aarch64_override_options): Use selected_cpu's tuning.
-+
-+2014-12-10  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
-+
-+	Backport from mainline
-+	2014-09-02  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
-+
-+	* config/rs6000/rs6000-builtin.def (XVCVSXDDP_SCALE):  New
-+	built-in definition.
-+	(XVCVUXDDP_SCALE): Likewise.
-+	(XVCVDPSXDS_SCALE): Likewise.
-+	(XVCVDPUXDS_SCALE): Likewise.
-+	* config/rs6000/rs6000-c.c (altivec_overloaded_builtins):  Add
-+	entries for VSX_BUILTIN_XVCVSXDDP_SCALE,
-+	VSX_BUILTIN_XVCVUXDDP_SCALE, VSX_BUILTIN_XVCVDPSXDS_SCALE, and
-+	VSX_BUILTIN_XVCVDPUXDS_SCALE.
-+	* config/rs6000/rs6000-protos.h (rs6000_scale_v2df): New
-+	prototype.
-+	* config/rs6000/rs6000.c (real.h): New include.
-+	(rs6000_scale_v2df): New function.
-+	* config/rs6000/vsx.md (UNSPEC_VSX_XVCVSXDDP): New unspec.
-+	(UNSPEC_VSX_XVCVUXDDP): Likewise.
-+	(UNSPEC_VSX_XVCVDPSXDS): Likewise.
-+	(UNSPEC_VSX_XVCVDPUXDS): Likewise.
-+	(vsx_xvcvsxddp_scale): New define_expand.
-+	(vsx_xvcvsxddp): New define_insn.
-+	(vsx_xvcvuxddp_scale): New define_expand.
-+	(vsx_xvcvuxddp): New define_insn.
-+	(vsx_xvcvdpsxds_scale): New define_expand.
-+	(vsx_xvcvdpsxds): New define_insn.
-+	(vsx_xvcvdpuxds_scale): New define_expand.
-+	(vsx_xvcvdpuxds): New define_insn.
-+	* doc/extend.texi (vec_ctf): Add new prototypes.
-+	(vec_cts): Likewise.
-+	(vec_ctu): Likewise.
-+	(vec_splat): Likewise.
-+	(vec_div): Likewise.
-+	(vec_mul): Likewise.
-+
-+	Backport from mainline
-+        2014-08-28  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
-+
-+	* config/rs6000/altivec.h (vec_xl): New #define.
-+	(vec_xst): Likewise.
-+	* config/rs6000/rs6000-builtin.def (XXSPLTD_V2DF): New built-in.
-+	(XXSPLTD_V2DI): Likewise.
-+	(DIV_V2DI): Likewise.
-+	(UDIV_V2DI): Likewise.
-+	(MUL_V2DI): Likewise.
-+	* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
-+	entries for VSX_BUILTIN_XVRDPI, VSX_BUILTIN_DIV_V2DI,
-+	VSX_BUILTIN_UDIV_V2DI, VSX_BUILTIN_MUL_V2DI,
-+	VSX_BUILTIN_XXSPLTD_V2DF, and VSX_BUILTIN_XXSPLTD_V2DI).
-+	* config/rs6000/vsx.md (UNSPEC_VSX_XXSPLTD): New unspec.
-+	(UNSPEC_VSX_DIVSD): Likewise.
-+	(UNSPEC_VSX_DIVUD): Likewise.
-+	(UNSPEC_VSX_MULSD): Likewise.
-+	(vsx_mul_v2di): New insn-and-split.
-+	(vsx_div_v2di): Likewise.
-+	(vsx_udiv_v2di): Likewise.
-+	(vsx_xxspltd_<mode>): New insn.
-+
-+	Backport from mainline
-+        2014-08-20  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
-+
-+	* config/rs6000/altivec.h (vec_cpsgn): New #define.
-+	(vec_mergee): Likewise.
-+	(vec_mergeo): Likewise.
-+	(vec_cntlz): Likewise.
-+	* config/rs600/rs6000-c.c (altivec_overloaded_builtins): Add new
-+	entries for VEC_AND, VEC_ANDC, VEC_MERGEH, VEC_MERGEL, VEC_NOR,
-+	VEC_OR, VEC_PACKSU, VEC_XOR, VEC_PERM, VEC_SEL, VEC_VCMPGT_P,
-+	VMRGEW, and VMRGOW.
-+	* doc/extend.texi: Document various forms of vec_cpsgn,
-+	vec_splats, vec_and, vec_andc, vec_mergeh, vec_mergel, vec_nor,
-+	vec_or, vec_perm, vec_sel, vec_sub, vec_xor, vec_all_eq,
-+	vec_all_ge, vec_all_gt, vec_all_le, vec_all_lt, vec_all_ne,
-+	vec_any_eq, vec_any_ge, vec_any_gt, vec_any_le, vec_any_lt,
-+	vec_any_ne, vec_mergee, vec_mergeo, vec_packsu, and vec_cntlz.
-+
-+	Backport from mainline
-+        2014-07-20  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
-+
-+	* config/rs6000/altivec.md (unspec enum):  Fix typo in UNSPEC_VSLDOI.
-+	(altivec_vsldoi_<mode>): Likewise.
-+
-+
-+2014-12-10  Jakub Jelinek  <jakub@redhat.com>
-+
-+	PR tree-optimization/62021
-+	* omp-low.c (simd_clone_adjust_return_type): Use
-+	vector of pointer_sized_int_node types instead vector of pointer
-+	types.
-+	(simd_clone_adjust_argument_types): Likewise.
-+
-+2014-12-10  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
-+
-+	Backport from mainline:
-+	2014-12-09  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
-+
-+	PR middle-end/64225
-+	* tree-ssa-reassoc.c (acceptable_pow_call): Disable transformation
-+	for BUILT_IN_POW when flag_errno_math is present.
-+
-+2014-12-10  Marek Polacek  <polacek@redhat.com>
-+
-+	Backport from mainline
-+	2014-12-10  Marek Polacek  <polacek@redhat.com>
-+
-+	PR tree-optimization/61686
-+	* tree-ssa-reassoc.c (range_entry_cmp): Use q->high instead of
-+	p->high.
-+
-+2014-12-09  David Edelsohn  <dje.gcc@gmail.com>
-+
-+	Backport from mainline
-+	2014-12-05  David Edelsohn  <dje.gcc@gmail.com>
-+
-+	* config/rs6000/xcoff.h (ASM_OUTPUT_ALIGNED_LOCAL): Append
-+	alignment to section name. Increase default alignment to
-+	word.
-+
-+2014-12-09  Uros Bizjak  <ubizjak@gmail.com>
-+
-+	PR bootstrap/64213
-+	Revert:
-+	2014-11-28  H.J. Lu  <hongjiu.lu@intel.com>
-+
-+	PR rtl-optimization/64037
-+	* combine.c (setup_incoming_promotions): Pass the argument
-+	before any promotions happen to promote_function_mode.
-+
-+2014-12-09  Richard Biener  <rguenther@suse.de>
-+
-+	PR tree-optimization/64191
-+	* tree-vect-stmts.c (vect_stmt_relevant_p): Clobbers are
-+	not relevant (nor are their uses).
-+
-+2014-12-07  Oleg Endo  <olegendo@gcc.gnu.org>
-+
-+	Backport from mainline
-+	2014-12-07  Oleg Endo  <olegendo@gcc.gnu.org>
-+
-+	PR target/50751
-+	* config/sh/sh.md (extendqihi2): Allow only for TARGET_SH1.
-+
-+2014-12-05  H.J. Lu  <hongjiu.lu@intel.com>
-+
-+	Backport from mainline
-+	2014-12-02  H.J. Lu  <hongjiu.lu@intel.com>
-+
-+	PR target/64108
-+	* config/i386/i386.c (decide_alg): Stop only if there aren't
-+	any usable algorithms.
-+
-+2014-12-05  H.J. Lu  <hongjiu.lu@intel.com>
-+
-+	Backport from mainline
-+	2014-11-28  H.J. Lu  <hongjiu.lu@intel.com>
-+
-+	PR rtl-optimization/64037
-+	* combine.c (setup_incoming_promotions): Pass the argument
-+	before any promotions happen to promote_function_mode.
-+
-+2014-12-04  Tobias Burnus  <burnus@net-b.de>
-+
-+	* configure.ac
-+	(ac_has_isl_schedule_constraints_compute_schedule):
-+	New check.
-+	* graphite-clast-to-gimple.c: For ISL 0.14, include deprecate headers.
-+	* graphite-interchange.c: Ditto.
-+	* graphite-poly.c: Ditto.
-+	* graphite-sese-to-poly.c: Ditto.
-+	* graphite-optimize-isl.c (getScheduleForBandList): Ditto.
-+	Conditionally use ISL 0.13+ functions.
-+	* config.in: Regenerate.
-+	* configure: Regenerate.
-+
-+2014-12-04  Jakub Jelinek  <jakub@redhat.com>
-+
-+	PR c++/56493
-+	* convert.c (convert_to_real, convert_to_expr, convert_to_complex):
-+	Handle COMPOUND_EXPR.
-+
-+2014-12-03  Jakub Jelinek  <jakub@redhat.com>
-+
-+	PR c/59708
-+	* expmed.c (expand_widening_mult): Return const0_rtx if
-+	coeff is 0.
-+
-+2014-12-03  Martin Jambor  <mjambor@suse.cz>
-+
-+	PR ipa/64153
-+	* ipa-inline-analysis.c (evaluate_conditions_for_known_args): Check
-+	type sizes before view_converting.
-+
-+2014-12-03  Shanyao Chen  <chenshanyao@huawei.com>
-+
-+	Backport from mainline
-+	2014-11-20  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
-+
-+	PR target/59593
-+	* config/arm/arm.md (*movhi_insn): Use right formatting
-+	for immediate.
-+
-+	2014-11-19  Felix Yang  <felix.yang@huawei.com>
-+		    Shanyao Chen  <chenshanyao@huawei.com>
-+
-+	PR target/59593
-+	* config/arm/arm.md (define_attr "arch"): Add v6t2.
-+	(define_attr "arch_enabled"): Add test for the above.
-+	(*movhi_insn_arch4): Add new alternative.
-+
-+2014-12-03  Renlin Li  <Renlin.Li@arm.com>
-+
-+	Backported from mainline
-+	2014-12-03  Renlin Li  <Renlin.Li@arm.com>
-+
-+	PR middle-end/63762
-+	PR target/63661
-+	* ira.c (ira): Update preferred class.
-+
-+2014-12-02  Uros Bizjak  <ubizjak@gmail.com>
-+
-+	PR target/64113
-+	* config/alpha/alpha.md (call_value_osf_tlsgd): Do not split insn
-+	using post-reload splitter.  Use peephole2 pass instead.
-+	(call_value_osf_tlsldm): Ditto.
-+	(TLS_CALL): New int iterator.
-+	(tls): New int attribute.
-+	(call_value_osf_<tls>): Merge insn pattern from call_value_osf_tlsgd
-+	and call_value_tlsldm using TLS_CALL int iterator.
-+
-+2014-12-02  Ulrich Weigand  <Ulrich.Weigand@de.ibm.com>
-+
-+	PR target/64115
-+	* config/rs6000/rs6000.c (rs6000_delegitimize_address): Remove
-+	invalid UNSPEC_TOCREL sanity check under ENABLE_CHECKING.
-+
-+2014-12-01  Richard Biener  <rguenther@suse.de>
-+
-+	PR middle-end/64111
-+	* tree.c (int_cst_hash_hash): Use TYPE_UID instead of
-+	htab_hash_pointer to not break PCH.
-+
-+2014-12-01  Martin Jambor  <mjambor@suse.cz>
-+
-+	PR ipa/63551
-+	* ipa-inline-analysis.c (evaluate_conditions_for_known_args): Convert
-+	value of the argument to the type of the value in the condition.
-+
-+2014-11-28  Jakub Jelinek  <jakub@redhat.com>
-+
-+	Backported from mainline
-+	2014-11-27  Jakub Jelinek  <jakub@redhat.com>
-+
-+	PR middle-end/64067
-+	* expr.c (expand_expr_addr_expr_1) <case COMPOUND_LITERAL_EXPR>:
-+	Handle it by returning address of COMPOUND_LITERAL_EXPR_DECL
-+	not only if modifier is EXPAND_INITIALIZER, but whenever
-+	COMPOUND_LITERAL_EXPR_DECL is non-NULL and TREE_STATIC.
-+
-+	2014-11-19  Jakub Jelinek  <jakub@redhat.com>
-+
-+	PR tree-optimization/63915
-+	* tree-vect-stmts.c (vectorizable_simd_clone_call): Pass
-+	true instead of false as last argument to gsi_replace.
-+
-+	PR sanitizer/63913
-+	* ubsan.c: Include tree-eh.h.
-+	(instrument_bool_enum_load): Handle loads that can throw.
-+
-+	2014-10-31  Jakub Jelinek  <jakub@redhat.com>
-+
-+	PR rtl-optimization/63659
-+	* ree.c (update_reg_equal_equiv_notes): New function.
-+	(combine_set_extension, transform_ifelse): Use it.
-+
-+2014-11-28  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
-+
-+	Backport from mainline.
-+        2014-11-28  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
-+        * config/arm/t-aprofile (MULTILIB_MATCHES): New entry for
-+        -march=armv8-a+crc.
-+
-+2014-11-26  Richard Biener  <rguenther@suse.de>
-+
-+	PR middle-end/63738
-+	* tree-data-ref.c (split_constant_offset_1): Do not follow
-+	SSA edges for SSA names with SSA_NAME_OCCURS_IN_ABNORMAL_PHI.
-+
-+2014-11-26  Richard Biener  <rguenther@suse.de>
-+
-+	Backport from mainline
-+	2014-11-26  Richard Biener  <rguenther@suse.de>
-+
-+	PR tree-optimization/62238
-+	* tree-predcom.c (ref_at_iteration): Unshare the expression
-+	before gimplifying it.
-+
-+	2014-11-25  Richard Biener  <rguenther@suse.de>
-+
-+	PR tree-optimization/61927
-+	* tree-vect-loop.c (vect_analyze_loop_2): Revert ordering
-+	of group and pattern analysis to the one in GCC 4.8.
-+
-+	2014-11-07  Richard Biener  <rguenther@suse.de>
-+
-+	PR tree-optimization/63605
-+	* fold-const.c (fold_binary_loc): Properly use element_precision
-+	for types that may not be scalar.
-+
-+	2014-10-28  Richard Biener  <rguenther@suse.de>
-+
-+	PR middle-end/63665
-+	* fold-const.c (fold_comparison): Properly guard simplifying
-+	against INT_MAX/INT_MIN with !TYPE_OVERFLOW_WRAPS.
-+
-+2014-11-25  Rohit  <rohitarulraj@freescale.com>
-+
-+	PR bootstrap/63703
-+	* config/rs6000/darwin.h (REGISTER_NAMES): Update based on 32 newly
-+	added GCC hard register numbers for SPE high registers.
-+
-+2014-11-23  Oleg Endo  <olegendo@gcc.gnu.org>
-+
-+	Backport from mainline
-+	2014-11-23  Oleg Endo  <olegendo@gcc.gnu.org>
-+
-+	PR target/53976
-+	* config/sh/sh_optimize_sett_clrt.cc
-+	(sh_optimize_sett_clrt::find_last_ccreg_values): Return bool instead
-+	of void.  Abort at complex edges.
-+	(sh_optimize_sett_clrt::execute): Do nothing if find_last_ccreg_values
-+	returned false.
-+
-+2014-11-22  Oleg Endo  <olegendo@gcc.gnu.org>
-+
-+	Backport from mainline
-+	2014-11-22  Oleg Endo  <olegendo@gcc.gnu.org>
-+
-+	PR target/63783
-+	PR target/51244
-+	* config/sh/sh_treg_combine.cc (sh_treg_combine::make_not_reg_insn):
-+	Do not emit bitwise not insn.  Emit logical not insn sequence instead.
-+	Adjust related comments throughout the file.
-+
-+2014-11-22  Oleg Endo  <olegendo@gcc.gnu.org>
-+
-+	Backport from mainline
-+	2014-11-20  Segher Boessenkool  <segher@kernel.crashing.org>
-+
-+	PR target/60111
-+	* config/sh/sh.c: Use signed char for signed field.
-+
-+2014-11-21  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
-+
-+	PR target/63673
-+	* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Allow
-+	the base pointer of vec_vsx_ld and vec_vsx_st to take a pointer to
-+	double.
-+
-+2014-11-21  Richard Biener  <rguenther@suse.de>
-+
-+	PR tree-optimization/61750
-+	* tree-ssa-forwprop.c (simplify_vce): Verify type sizes
-+	match for the resulting VIEW_CONVERT_EXPR.
-+
-+2014-11-19  Uros Bizjak  <ubizjak@gmail.com>
-+
-+	PR target/63947
-+	* config/i386/i386.c (put_condition_code) <case LTU, case GEU>:
-+	Output "b" and "nb" suffix for FP mode.
-+
-+2014-11-19  Tom de Vries  <tom@codesourcery.com>
-+
-+	Backport from mainline
-+	PR tree-optimization/62167
-+	* tree-ssa-tail-merge.c (stmt_local_def): Handle statements with vuse
-+	conservatively.
-+	(gimple_equal_p): Don't use vn_valueize to compare for lhs equality of
-+	assigns.
-+
-+2014-11-16  Eric Botcazou  <ebotcazou@adacore.com>
-+
-+	* doc/tm.texi.in (TARGET_FLAGS_REGNUM): Move around.
-+	* doc/tm.texi: Regenerate.
-+
-+2014-11-14  Felix Yang  <felix.yang@huawei.com>
-+
-+	Backport from mainline
-+	2014-11-14  Felix Yang  <felix.yang@huawei.com>
-+		    Jiji Jiang  <jiangjiji@huawei.com>
-+
-+	* config/aarch64/aarch64-simd.md (*aarch64_simd_ld1r<mode>): Use
-+	VALL mode iterator instead of VALLDI.
-+
-+2014-11-13  Teresa Johnson  <tejohnson@google.com>
-+
-+	PR tree-optimization/63841
-+	* tree-ssa-strlen.c (strlen_optimize_stmt): Ignore clobbers.
-+
-+2014-11-13  Christophe Lyon  <christophe.lyon@linaro.org>
-+
-+	Backport from mainline
-+	2014-11-02  Michael Collison  <michael.collison@linaro.org>
-+
-+	* config/arm/arm.h (CLZ_DEFINED_VALUE_AT_ZERO) : Update
-+	to support vector modes.
-+	(CTZ_DEFINED_VALUE_AT_ZERO): Ditto.
-+
-+2014-11-13  Eric Botcazou  <ebotcazou@adacore.com>
-+
-+	* doc/tm.texi.in (SELECT_CC_MODE): Update example.
-+	(REVERSIBLE_CC_MODE): Fix example.
-+	(REVERSE_CONDITION): Fix typo.
-+	* doc/tm.texi: Regenerate.
-+
-+2014-11-12  Jakub Jelinek  <jakub@redhat.com>
-+
-+	PR ipa/63838
-+	* ipa-pure-const.c (propagate_nothrow): Walk w->indirect_calls
-+	chain instead of node->indirect_calls.
-+
-+2014-11-11  Eric Botcazou  <ebotcazou@adacore.com>
-+
-+	PR target/61535
-+	* config/sparc/sparc.c (function_arg_vector_value): Deal with vectors
-+	smaller than 8 bytes.
-+	(sparc_function_arg_1): Tweak.
-+	(sparc_function_value_1): Tweak.
-+
-+2014-11-08  Eric Botcazou  <ebotcazou@adacore.com>
-+
-+	* config/arm/arm.c (arm_set_return_address): Mark the store as frame
-+	related, if any.
-+	(thumb_set_return_address): Likewise.
-+
-+2014-11-07  Daniel Hellstrom  <daniel@gaisler.com>
-+
-+	* config.gcc (sparc-*-rtems*): Clean away unused t-elf.
-+	* config/sparc/t-rtems: Add leon3v7 and muser-mode multilibs.
-+
-+2014-11-07  Marek Polacek  <polacek@redhat.com>
-+
-+	Backported from mainline
-+	2014-10-23  Marek Polacek  <polacek@redhat.com>
-+
-+	* c-ubsan.c (ubsan_instrument_shift): Perform the MINUS_EXPR
-+	in unsigned type.
-+
-+2014-11-06  John David Anglin  <danglin@gcc.gnu.org>
-+
-+	* config/pa/pa.md (trap): New insn.  Add "trap" to attribute type.
-+	Don't allow trap insn in in_branch_delay, in_nullified_branch_delay
-+	or in_call_delay.
-+
-+2014-11-06  Daniel Hellstrom  <daniel@gaisler.com>
-+
-+	* config.gcc (sparc*-*-*): Accept mcpu=leon3v7 processor.
-+	* doc/invoke.texi (SPARC options): Add mcpu=leon3v7 comment.
-+	* config/sparc/leon.md (leon3_load, leon_store, leon_fp_*): Handle
-+	leon3v7 as leon3.
-+	* config/sparc/sparc-opts.h (enum processor_type): Add LEON3V7.
-+	* config/sparc/sparc.c (sparc_option_override): Add leon3v7 support.
-+	* config/sparc/sparc.h (TARGET_CPU_leon3v7): New define.
-+	* config/sparc/sparc.md (cpu): Add leon3v7.
-+	* config/sparc/sparc.opt (enum processor_type): Add leon3v7.
-+
-+2014-11-05  Uros Bizjak  <ubizjak@gmail.com>
-+
-+	PR target/63538
-+	* config/i386/i386.c (in_large_data_p): Reject automatic variables.
-+	(ix86_encode_section_info): Do not check for non-automatic varibles
-+	when setting SYMBOL_FLAG_FAR_ADDR flag.
-+	(x86_64_elf_select_section): Do not check ix86_cmodel here.
-+	(x86_64_elf_unique_section): Ditto.
-+	(x86_elf_aligned_common): Emit tab before .largecomm.
-+
-+2014-11-05  Uros Bizjak  <ubizjak@gmail.com>
-+
-+	Backport from mainline:
-+	2014-10-20  Uros Bizjak  <ubizjak@gmail.com>
-+
-+	* varasm.c (const_alias_set): Remove.
-+	(init_varasm_once): Remove initialization of const_alias_set.
-+	(build_constant_desc): Do not set alias set to const_alias_set.
-+
-+	Backport from mainline:
-+	2014-10-14  Uros Bizjak  <ubizjak@gmail.com>
-+
-+	PR rtl-optimization/63475
-+	* alias.c (true_dependence_1): Always use get_addr to extract
-+	true address operands from x_addr and mem_addr.  Use extracted
-+	address operands to check for references with alignment ANDs.
-+	Use extracted address operands with find_base_term and
-+	base_alias_check. For noncanonicalized operands call canon_rtx with
-+	extracted address operand.
-+	(write_dependence_1): Ditto.
-+	(may_alias_p): Ditto.  Remove unused calls to canon_rtx.
-+
-+	Backport from mainline:
-+	2014-10-10  Uros Bizjak  <ubizjak@gmail.com>
-+
-+	PR rtl-optimization/63483
-+	* alias.c (true_dependence_1): Do not exit early for MEM_READONLY_P
-+	references when alignment ANDs are involved.
-+	(write_dependence_p): Ditto.
-+	(may_alias_p): Ditto.
-+
-+2014-10-31  DJ Delorie  <dj@redhat.com>
-+
-+	* expmed.c (strict_volatile_bitfield_p): Fix off-by-one error.
-+
-+2014-10-31  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
-+
-+	* config/aarch64/aarch64-elf-raw.h (CA53_ERR_835769_SPEC): Define.
-+	(LINK_SPEC): Include CA53_ERR_835769_SPEC.
-+	* config/aarch64/aarch64-linux.h (CA53_ERR_835769_SPEC): Define.
-+	(LINK_SPEC): Include CA53_ERR_835769_SPEC.
-+
-+2014-10-31  Jakub Jelinek  <jakub@redhat.com>
-+
-+	PR sanitizer/63697
-+	* tree-vrp.c (simplify_internal_call_using_ranges): For subcode ==
-+	MINUS_EXPR, check overflow on vr0.min - vr1.max and vr0.max - vr1.min
-+	instead of vr0.min - vr1.min and vr0.max - vr1.max.
-+
-+2014-10-30  Georg-Johann Lay  <avr@gjlay.de>
-+
-+	PR63633
-+	* config/avr/avr-protos.h (regmask): New inline function.
-+	(avr_fix_inputs, avr_emit3_fix_outputs): New protos.
-+	* config/avr/avr.c (avr_fix_operands, avr_move_fixed_operands)
-+	(avr_fix_inputs, avr_emit3_fix_outputs): New functions.
-+	* config/avr/avr-fixed.md (mulqq3_nomul, muluqq3_nomul)
-+	(mul<ALL2QA>3, mul<ALL4A>3, <usdiv><ALL1Q>3, <usdiv><ALL2QA>3)
-+	(<usdiv><ALL4A>3, round<ALL124QA>3): Fix input operands.
-+	* config/avr/avr-dimode.md (add<ALL8>3, sub<ALL8>3)
-+	(<ss_addsub><ALL8S>3, <us_addsub><ALL8U>3, cbranch<ALL8>4)
-+	(<di_shifts><ALL8>3, <any_extend>mulsidi3): Fix input operands.
-+	* config/avr/avr.md (mulqi3_call, mulhi3_call, mulsi3, mulpsi3)
-+	(mulu<QIHI>si3, muls<QIHI>si3, mulohisi3, <any_extend>mulhisi3)
-+	(usmulhisi3, <any_extend>mulhi3_highpart, mulsqipsi3)
-+	(fmul, fmuls, fmulsu): Fix operands.  Turn insn into expander as
-+	needed.
-+
- 2014-10-30  Release Manager
- 
- 	* GCC 4.9.2 released.
-@@ -150,8 +932,8 @@
- 	Backport from mainline
- 	2014-06-24  Max Ostapenko  <m.ostapenko@partner.samsung.com>
- 
--	* asan.c (instrument_strlen_call): Do not instrument first byte in strlen
--	if already instrumented.
-+	* asan.c (instrument_strlen_call): Do not instrument first byte in
-+	strlen if already instrumented.
- 
- 2014-10-16  Yury Gribov  <y.gribov@samsung.com>
- 
-@@ -1504,7 +2286,7 @@
- 	* omp-low.c (create_omp_child_function): Don't set DECL_NAMELESS
- 	on the FUNCTION_DECL.
- 
--	* BASE-VER: Set to 4.9.1.
-+	* BASE-VER: Set to 4.9.2.
- 	* DEV-PHASE: Set to prerelease.
- 
- 2014-07-16  Release Manager
-Index: gcc/testsuite/gcc.target/powerpc/pr64505.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/pr64505.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/pr64505.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,231 @@
-+/* { dg-do compile { target { powerpc*-*-* && ilp32 } } } */
-+/* { dg-options "-O2 -mpowerpc64" } */
-+
-+/*
-+ * (below is inlined and simplified from previously included headers)
-+ */
-+
-+struct fltcom_st {
-+    short fltbuf[950];
-+} fltcom_  __attribute__((common))  ;
-+#define CM_PLIBOR (*(((double *)&fltcom_ + 1)))
-+#define CM_QMRG (*(((double *)&fltcom_ + 2)))
-+
-+struct fltcom2_st {
-+    short fltbuf2[56];
-+} fltcom2_  __attribute__((common))  ;
-+#define CM_FLPRV ((short *)&fltcom2_ + 17)
-+#define CM_FLNXT ((short *)&fltcom2_ + 20)
-+#define CM_FLCPN (*(((double *)&fltcom2_)))
-+#define CM_FLCNT (*(((short *)&fltcom2_ + 12)))
-+
-+struct aidatcm_st {
-+    double cm_aid, cm_ext, cm_basis;
-+    short cm_aiday, cm_exday, cm_dperd, cm_aiexf, cm_aidex, cm_aiok,
-+            cm_aigdo, cm_aildo, cm_prev[3], cm_next[3], cm_aid_pad[2];
-+    double cm_rvgfact, cm_ai1st, cm_ai2nd;
-+    int cm_aieurok;
-+} aidatcm_  __attribute__((common))  ;
-+#define CM_EXDAY aidatcm_.cm_exday
-+#define CM_BASIS aidatcm_.cm_basis
-+#define CM_PREV aidatcm_.cm_prev
-+
-+struct cshfcm_st {
-+    short bufff[10862];
-+} cshfcm_  __attribute__((common))  ;
-+#define CM_FNUM (*(((short *)&cshfcm_ + 9038)))
-+#define CM_FIFLX ((double *)&cshfcm_ + 1)
-+#define CM_FEXTX ((double *)&cshfcm_ + 1201)
-+#define CM_FSHDT ((short *)&cshfcm_ + 7230)
-+
-+struct calctsdb_st {
-+    short calctsdbbuff[115];
-+} calctsdb_  __attribute__((common))  ;
-+#define CM_CTUP_GOOD_TO_GO (*(((short *)&calctsdb_ + 16)))
-+#define CM_PAYMENT_FREQUENCY (*(((short *)&calctsdb_ + 61)))
-+#define CM_DISCOUNTING_DAYTYP (*(((short *)&calctsdb_ + 59)))
-+
-+struct cf600cm_st {
-+    short bufcf[14404];
-+} cf600cm_  __attribute__((common)) ;
-+#define CM_FLT_RFIXRATES ((double *)&cf600cm_ + 600)
-+
-+typedef struct { int id; int type; const char *name; } bregdb_bitinfo_t;
-+
-+int
-+bregdb_eval_bbitcxt_bool_rv(const bregdb_bitinfo_t * const bbit,
-+                            const int bbit_default,
-+                            const void * const bregucxt);
-+
-+static const bregdb_bitinfo_t bbit_calc_dr_d33 =
-+  { 160667, 5, "bbit_calc_dr_d33" };
-+#define bbit_calc_dr_d33__value() \
-+  bregdb_eval_bbitcxt_bool_rv(&bbit_calc_dr_d33, 0, 0)
-+static const bregdb_bitinfo_t bbit_calc_sx_b24 =
-+  { 158854, 5, "bbit_calc_sx_b24" };
-+#define bbit_calc_sx_b24__value() \
-+  bregdb_eval_bbitcxt_bool_rv(&bbit_calc_sx_b24, 0, 0)
-+static const bregdb_bitinfo_t bbit_calc_dr_d36 =
-+  { 161244, 5, "bbit_calc_dr_d36" };
-+#define bbit_calc_dr_d36__value() \
-+  bregdb_eval_bbitcxt_bool_rv(&bbit_calc_dr_d36, 0, 0)
-+static const bregdb_bitinfo_t bbit_calc_dr_d37 =
-+  { 161315, 5, "bbit_calc_dr_d37" };
-+#define bbit_calc_dr_d37__value() \
-+  bregdb_eval_bbitcxt_bool_rv(&bbit_calc_dr_d37, 0, 0)
-+static const bregdb_bitinfo_t bbit_calc_dr_d47 =
-+  { 163259, 5, "bbit_calc_dr_d47" };
-+#define bbit_calc_dr_d47__value() \
-+  bregdb_eval_bbitcxt_bool_rv(&bbit_calc_dr_d47, 0, 0)
-+static const bregdb_bitinfo_t bbit_calc_dr_d46 =
-+  { 163239, 5, "bbit_calc_dr_d46" };
-+#define bbit_calc_dr_d46__value() \
-+  bregdb_eval_bbitcxt_bool_rv(&bbit_calc_dr_d46, 0, 0)
-+static const bregdb_bitinfo_t bbit_calc_dr_d62 =
-+  { 166603, 5, "bbit_calc_dr_d62" };
-+#define bbit_calc_dr_d62__value() \
-+  bregdb_eval_bbitcxt_bool_rv(&bbit_calc_dr_d62, 0, 0)
-+
-+
-+
-+int dtyp_is_actact_(short *daytyp);
-+double rnd_trunc_numb(double in, short num_digits, short rnd_or_trunc);
-+void datetrn_(const short* dt, short* dt2);
-+short difday_(short* daytyp_in, short* srtdti, short* enddti, short* ercode);
-+
-+
-+double pow(double x, double y);
-+
-+
-+/*
-+ * (above is inlined and simplified from previously included headers)
-+ */
-+
-+
-+void calc_1566(
-+  short  sCalcType,
-+  short  sDayType,
-+  short  sFreq,
-+  short  asSettleDt[3],
-+  short  asMtyDt[3],
-+  short  asIssueDt[3],
-+  short  asFCpnDt[3],
-+  double dCpn,
-+  short  *psNoPer,
-+  double *pdExt,
-+  double *pdAI,
-+  double *pdAI2,
-+  double *pdFCpn,
-+  short  *psRcode)
-+{
-+
-+    short ercode = 0;
-+    int isactact;
-+    short days_to_next_cpn = 0;
-+    const short discDaytype = CM_DISCOUNTING_DAYTYP;
-+    int j;
-+
-+    if(bbit_calc_sx_b24__value())
-+        isactact = (dtyp_is_actact_(&sDayType) != 0);
-+    else
-+        isactact = (sDayType == 1 || sDayType == 10);
-+
-+    short days_in_current_period = difday_(&sDayType,CM_FLPRV,CM_FLNXT,&ercode);
-+    const short sfreq1 = (CM_CTUP_GOOD_TO_GO == 1 && CM_PAYMENT_FREQUENCY == 1);
-+
-+    for (j = 0; j < CM_FNUM; j++) {
-+
-+        if(j == 0) {
-+            days_to_next_cpn = difday_(&sDayType,asSettleDt,CM_FLNXT,&ercode);
-+
-+            if(isactact) {
-+                CM_FIFLX[j] = CM_FLCPN / sFreq;
-+                CM_FEXTX[j] = (double)days_to_next_cpn / (double)days_in_current_period;
-+            }
-+            else {
-+                CM_FIFLX[j] = CM_FLCPN * days_in_current_period;
-+                CM_FEXTX[j] = (double)days_to_next_cpn / (double)(1/sfreq1);
-+            }
-+
-+            if(CM_FNUM == 1) {
-+                CM_FEXTX[j] = (double)days_to_next_cpn / ((double)1/sfreq1);
-+            }
-+        }
-+        else {
-+
-+            short days_from_settle, days_in_period;
-+
-+            if(bbit_calc_dr_d46__value()){
-+             days_from_settle = difday_(&sDayType,asSettleDt,
-+                                             &CM_FSHDT[j*3],&ercode);
-+             days_in_period =  difday_(&sDayType,&CM_FSHDT[(j-1)*3],
-+                                            &CM_FSHDT[j*3],&ercode);
-+            }
-+
-+            double cpn_rate = CM_PLIBOR;
-+
-+            if(bbit_calc_dr_d62__value()) {
-+              if(j < CM_FLCNT && CM_FLT_RFIXRATES[j] != 0) cpn_rate = CM_FLT_RFIXRATES[j];
-+            }
-+            else {
-+              if(j < CM_FLCNT ) cpn_rate = CM_FLT_RFIXRATES[j];
-+            }
-+
-+            if(bbit_calc_dr_d37__value()&& j >= CM_FLCNT && sCalcType == 1570) {
-+                cpn_rate = CM_PLIBOR + CM_QMRG;
-+
-+                if(bbit_calc_dr_d36__value()){
-+                double projected_rate = pow((1 + CM_PLIBOR/100.0),
-+                                            (days_in_period)) - 1;
-+
-+                projected_rate = projected_rate + CM_QMRG/100.0 * days_in_period;
-+                cpn_rate = 100 * projected_rate * (1/days_in_period);
-+                }
-+            }
-+
-+
-+            if(isactact) {
-+                CM_FIFLX[j] = cpn_rate / sFreq;
-+                CM_FEXTX[j] = CM_FEXTX[j-1] + 1;
-+
-+                if(bbit_calc_dr_d46__value() && discDaytype != 0) {
-+                    CM_FEXTX[j] = (double)days_from_settle / (double)(1/sfreq1);
-+                }
-+            }
-+            else {
-+                if(!bbit_calc_dr_d46__value()){
-+                days_from_settle = difday_(&sDayType,asSettleDt,
-+                                               &CM_FSHDT[j*3],&ercode);
-+                days_in_period =  difday_(&sDayType,&CM_FSHDT[(j-1)*3],
-+                                               &CM_FSHDT[j*3],&ercode);
-+
-+                }
-+
-+                CM_FIFLX[j] = cpn_rate * days_in_period;
-+                CM_FEXTX[j] = (double)days_from_settle / (double)(1/sfreq1);
-+            }
-+
-+        }
-+
-+        if(bbit_calc_dr_d33__value() && CM_CTUP_GOOD_TO_GO != 0) {
-+            CM_FIFLX[j] = rnd_trunc_numb (CM_FIFLX[j], 0, 0);
-+        }
-+
-+    }
-+
-+
-+    short accrued_days = difday_(&sDayType,CM_FLPRV,asSettleDt,&ercode);
-+
-+    if(!bbit_calc_dr_d47__value()) {
-+    if(isactact) {
-+        *pdAI = (CM_FLCPN / sFreq)* accrued_days / ((double)days_in_current_period);
-+    }
-+    else{
-+        *pdAI = (CM_FLCPN / sFreq)* accrued_days / ((double)1/sFreq);
-+    }
-+    }
-+
-+    CM_EXDAY = days_to_next_cpn;
-+    CM_BASIS = days_in_current_period;
-+    datetrn_(CM_FLPRV,CM_PREV);
-+}
-Index: gcc/testsuite/gcc.target/powerpc/builtins-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/builtins-1.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/builtins-1.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,166 @@
-+/* { dg-do compile { target { powerpc64le-*-* } } } */
-+/* { dg-options "-mcpu=power8 -O0" } */
-+
-+/* Test that a number of newly added builtin overloads are accepted
-+   by the compiler.  */
-+
-+#include <altivec.h>
-+
-+vector double y = { 2.0, 4.0 };
-+vector double z;
-+
-+int main ()
-+{
-+  vector float fa = {1.0, 2.0, 3.0, -4.0};
-+  vector float fb = {-2.0, -3.0, -4.0, -5.0};
-+  vector float fc = vec_cpsgn (fa, fb);
-+
-+  vector long long la = {5L, 14L};
-+  vector long long lb = {3L, 86L};
-+  vector long long lc = vec_and (la, lb);
-+  vector bool long long ld = {0, -1};
-+  vector long long le = vec_and (la, ld);
-+  vector long long lf = vec_and (ld, lb);
-+
-+  vector unsigned long long ua = {5L, 14L};
-+  vector unsigned long long ub = {3L, 86L};
-+  vector unsigned long long uc = vec_and (ua, ub);
-+  vector bool long long ud = {0, -1};
-+  vector unsigned long long ue = vec_and (ua, ud);
-+  vector unsigned long long uf = vec_and (ud, ub);
-+
-+  vector long long lg = vec_andc (la, lb);
-+  vector long long lh = vec_andc (la, ld);
-+  vector long long li = vec_andc (ld, lb);
-+
-+  vector unsigned long long ug = vec_andc (ua, ub);
-+  vector unsigned long long uh = vec_andc (ua, ud);
-+  vector unsigned long long ui = vec_andc (ud, ub);
-+
-+  vector double da = {1.0, -4.0};
-+  vector double db = {-2.0, 5.0};
-+  vector double dc = vec_cpsgn (da, db);
-+
-+  vector long long lj = vec_mergeh (la, lb);
-+  vector long long lk = vec_mergeh (la, ld);
-+  vector long long ll = vec_mergeh (ld, la);
-+
-+  vector unsigned long long uj = vec_mergeh (ua, ub);
-+  vector unsigned long long uk = vec_mergeh (ua, ud);
-+  vector unsigned long long ul = vec_mergeh (ud, ua);
-+
-+  vector long long lm = vec_mergel (la, lb);
-+  vector long long ln = vec_mergel (la, ld);
-+  vector long long lo = vec_mergel (ld, la);
-+
-+  vector unsigned long long um = vec_mergel (ua, ub);
-+  vector unsigned long long un = vec_mergel (ua, ud);
-+  vector unsigned long long uo = vec_mergel (ud, ua);
-+
-+  vector long long lp = vec_nor (la, lb);
-+  vector long long lq = vec_nor (la, ld);
-+  vector long long lr = vec_nor (ld, la);
-+
-+  vector unsigned long long up = vec_nor (ua, ub);
-+  vector unsigned long long uq = vec_nor (ua, ud);
-+  vector unsigned long long ur = vec_nor (ud, ua);
-+
-+  vector long long ls = vec_or (la, lb);
-+  vector long long lt = vec_or (la, ld);
-+  vector long long lu = vec_or (ld, la);
-+
-+  vector unsigned long long us = vec_or (ua, ub);
-+  vector unsigned long long ut = vec_or (ua, ud);
-+  vector unsigned long long uu = vec_or (ud, ua);
-+
-+  vector unsigned char ca = {0,4,8,1,5,9,2,6,10,3,7,11,15,12,14,13};
-+  vector long long lv = vec_perm (la, lb, ca);
-+  vector unsigned long long uv = vec_perm (ua, ub, ca);
-+
-+  vector long long lw = vec_sel (la, lb, lc);
-+  vector long long lx = vec_sel (la, lb, uc);
-+  vector long long ly = vec_sel (la, lb, ld);
-+
-+  vector unsigned long long uw = vec_sel (ua, ub, lc);
-+  vector unsigned long long ux = vec_sel (ua, ub, uc);
-+  vector unsigned long long uy = vec_sel (ua, ub, ld);
-+
-+  vector long long lz = vec_xor (la, lb);
-+  vector long long l0 = vec_xor (la, ld);
-+  vector long long l1 = vec_xor (ld, la);
-+
-+  vector unsigned long long uz = vec_xor (ua, ub);
-+  vector unsigned long long u0 = vec_xor (ua, ud);
-+  vector unsigned long long u1 = vec_xor (ud, ua);
-+
-+  int ia = vec_all_eq (ua, ub);
-+  int ib = vec_all_ge (ua, ub);
-+  int ic = vec_all_gt (ua, ub);
-+  int id = vec_all_le (ua, ub);
-+  int ie = vec_all_lt (ua, ub);
-+  int ig = vec_all_ne (ua, ub);
-+
-+  int ih = vec_any_eq (ua, ub);
-+  int ii = vec_any_ge (ua, ub);
-+  int ij = vec_any_gt (ua, ub);
-+  int ik = vec_any_le (ua, ub);
-+  int il = vec_any_lt (ua, ub);
-+  int im = vec_any_ne (ua, ub);
-+
-+  vector int sia = {9, 16, 25, 36};
-+  vector int sib = {-8, -27, -64, -125};
-+  vector int sic = vec_mergee (sia, sib);
-+  vector int sid = vec_mergeo (sia, sib);
-+
-+  vector unsigned int uia = {9, 16, 25, 36};
-+  vector unsigned int uib = {8, 27, 64, 125};
-+  vector unsigned int uic = vec_mergee (uia, uib);
-+  vector unsigned int uid = vec_mergeo (uia, uib);
-+
-+  vector bool int bia = {0, -1, -1, 0};
-+  vector bool int bib = {-1, -1, 0, -1};
-+  vector bool int bic = vec_mergee (bia, bib);
-+  vector bool int bid = vec_mergeo (bia, bib);
-+
-+  vector unsigned int uie = vec_packsu (ua, ub);
-+
-+  vector long long l2 = vec_cntlz (la);
-+  vector unsigned long long u2 = vec_cntlz (ua);
-+  vector int sie = vec_cntlz (sia);
-+  vector unsigned int uif = vec_cntlz (uia);
-+  vector short ssa = {20, -40, -60, 80, 100, -120, -140, 160};
-+  vector short ssb = vec_cntlz (ssa);
-+  vector unsigned short usa = {81, 72, 63, 54, 45, 36, 27, 18};
-+  vector unsigned short usb = vec_cntlz (usa);
-+  vector signed char sca = {-4, 3, -9, 15, -31, 31, 0, 0,
-+		            1, 117, -36, 99, 98, 97, 96, 95};
-+  vector signed char scb = vec_cntlz (sca);
-+  vector unsigned char cb = vec_cntlz (ca);
-+
-+  vector double dd = vec_xl (0, &y);
-+  vec_xst (dd, 0, &z);
-+
-+  vector double de = vec_round (dd);
-+
-+  vector double df = vec_splat (de, 0);
-+  vector double dg = vec_splat (de, 1);
-+  vector long long l3 = vec_splat (l2, 0);
-+  vector long long l4 = vec_splat (l2, 1);
-+  vector unsigned long long u3 = vec_splat (u2, 0);
-+  vector unsigned long long u4 = vec_splat (u2, 1);
-+  vector bool long long l5 = vec_splat (ld, 0);
-+  vector bool long long l6 = vec_splat (ld, 1);
-+
-+  vector long long l7 = vec_div (l3, l4);
-+  vector unsigned long long u5 = vec_div (u3, u4);
-+
-+  vector long long l8 = vec_mul (l3, l4);
-+  vector unsigned long long u6 = vec_mul (u3, u4);
-+
-+  vector double dh = vec_ctf (la, -2);
-+  vector double di = vec_ctf (ua, 2);
-+  vector long long l9 = vec_cts (dh, -2);
-+  vector unsigned long long u7 = vec_ctu (di, 2);
-+
-+  return 0;
-+}
-Index: gcc/testsuite/gcc.target/powerpc/builtins-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/powerpc/builtins-2.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.target/powerpc/builtins-2.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,47 @@
-+/* { dg-do run { target { powerpc64le-*-* } } } */
-+/* { dg-options "-mcpu=power8 " } */
-+
-+#include <altivec.h>
-+
-+void abort (void);
-+
-+int main ()
-+{
-+  vector long long sa = {27L, -14L};
-+  vector long long sb = {-9L, -2L};
-+
-+  vector unsigned long long ua = {27L, 14L};
-+  vector unsigned long long ub = {9L, 2L};
-+
-+  vector long long sc = vec_div (sa, sb);
-+  vector unsigned long long uc = vec_div (ua, ub);
-+
-+  if (sc[0] != -3L || sc[1] != 7L || uc[0] != 3L || uc[1] != 7L)
-+    abort ();
-+
-+  vector long long sd = vec_mul (sa, sb);
-+  vector unsigned long long ud = vec_mul (ua, ub);
-+
-+  if (sd[0] != -243L || sd[1] != 28L || ud[0] != 243L || ud[1] != 28L)
-+    abort ();
-+
-+  vector long long se = vec_splat (sa, 0);
-+  vector long long sf = vec_splat (sa, 1);
-+  vector unsigned long long ue = vec_splat (ua, 0);
-+  vector unsigned long long uf = vec_splat (ua, 1);
-+
-+  if (se[0] != 27L || se[1] != 27L || sf[0] != -14L || sf[1] != -14L
-+      || ue[0] != 27L || ue[1] != 27L || uf[0] != 14L || uf[1] != 14L)
-+    abort ();
-+
-+  vector double da = vec_ctf (sa, -2);
-+  vector double db = vec_ctf (ua, 2);
-+  vector long long sg = vec_cts (da, -2);
-+  vector unsigned long long ug = vec_ctu (db, 2);
-+
-+  if (da[0] != 108.0 || da[1] != -56.0 || db[0] != 6.75 || db[1] != 3.5
-+      || sg[0] != 27L || sg[1] != -14L || ug[0] != 27L || ug[1] != 14L)
-+    abort ();
-+
-+  return 0;
-+}
-Index: gcc/testsuite/gcc.target/aarch64/pr63424.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/aarch64/pr63424.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.target/aarch64/pr63424.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,39 @@
-+/* { dg-do compile } */
-+/* { dg-options "-O3" } */
-+
-+#include <stdint.h>
-+
-+uint32_t
-+truncate_int (const unsigned long long value)
-+{
-+  if ( value < 0 )
-+    {
-+      return 0;
-+    }
-+  else if ( value > UINT32_MAX )
-+    {
-+      return UINT32_MAX;
-+    }
-+  else
-+    return (uint32_t)value;
-+}
-+
-+uint32_t
-+mul (const unsigned long long x, const unsigned long long y)
-+{
-+  uint32_t value = truncate_int (x * y);
-+  return value;
-+}
-+
-+uint32_t *
-+test(unsigned size, uint32_t *a, uint32_t s)
-+{
-+  unsigned i;
-+
-+  for (i = 0; i < size; i++)
-+    {
-+      a[i] = mul (a[i], s);
-+    }
-+
-+  return a;
-+}
-Index: gcc/testsuite/gcc.target/avr/torture/pr63633-ice-mult.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/avr/torture/pr63633-ice-mult.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.target/avr/torture/pr63633-ice-mult.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,37 @@
-+/* { dg-do compile } */
-+
-+void ice_mult32 (int x)
-+{
-+  register long reg __asm ("22");
-+  __asm volatile (" " :: "r" (reg = 0x12345 * x));
-+}
-+
-+void ice_mult24 (int x)
-+{
-+  register __int24 reg __asm ("20");
-+  __asm volatile (" " :: "r" (reg = 0x12345 * x));
-+}
-+
-+void ice_sh24 (__int24 x)
-+{
-+  register __int24 reg __asm ("20");
-+  __asm volatile (" " :: "r" (reg = x << 3));
-+}
-+
-+void ice_sh24b (__int24 x)
-+{
-+  register __int24 reg __asm ("20");
-+  __asm volatile (" " :: "r" (reg = x << 22));
-+}
-+
-+void ice_s16s16 (int x)
-+{
-+  register long reg __asm ("20");
-+  __asm volatile (" " :: "r" (reg = (long) x*x));
-+}
-+
-+void ice_u16s16 (int x)
-+{
-+  register long reg __asm ("20");
-+  __asm volatile (" " :: "r" (reg = (long) x*0x1234u));
-+}
-Index: gcc/testsuite/gcc.target/i386/memcpy-strategy-4.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/memcpy-strategy-4.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/memcpy-strategy-4.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,21 @@
-+/* PR target/64200 */
-+/* { dg-do compile } */
-+/* { dg-options "-O2 -march=atom -mmemcpy-strategy=libcall:-1:align -minline-stringops-dynamically" } */
-+
-+#include <stdarg.h>
-+
-+extern void bar(char *x);
-+
-+void foo (int size, ...)
-+{
-+  struct
-+  {
-+    char x[size];
-+  } d;
-+
-+  va_list ap;
-+  va_start(ap, size);
-+  d = va_arg(ap, typeof (d));
-+  va_end(ap);
-+  bar(d.x);
-+}
-Index: gcc/testsuite/gcc.target/i386/pr64409.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr64409.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr64409.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,6 @@
-+/* { dg-do compile { target { ! { ia32 } } } } */
-+/* { dg-require-effective-target maybe_x32 } */
-+/* { dg-options "-O0 -mx32" } */
-+
-+int a;
-+int* __attribute__ ((ms_abi)) fn1 () { return &a; } /* { dg-error "X32 does not support ms_abi attribute" } */
-Index: gcc/testsuite/gcc.target/i386/avx256-unaligned-store-7.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-7.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-7.c	(.../branches/gcc-4_9-branch)
-@@ -29,13 +29,13 @@
-   ap = ep;
-   bp = fp;
- 
--  for (i = N; i >= 0; i--)
-+  for (i = N; i > 0; i--)
-     {
-       *ap++ = str;
-       *bp++ = str;
-     }
- 
--  for (i = N; i >= 0; i--)
-+  for (i = N; i > 0; i--)
-     {
-       if (strcmp (*--ap, "STR") != 0)
- 	abort ();
-Index: gcc/testsuite/gcc.target/i386/pr63661.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr63661.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr63661.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,80 @@
-+/* PR target/63661 */
-+/* { dg-do run } */
-+/* { dg-require-effective-target fpic } */
-+/* { dg-options "-mtune=nehalem -fPIC -O2" } */
-+
-+static void __attribute__((noinline,noclone,hot))
-+foo (double a, double q, double *ff, double *gx, int e, int ni)
-+{
-+  union
-+    {
-+      double n;
-+      unsigned long long o;
-+    } punner;
-+  double d;
-+
-+  punner.n = q;
-+   __builtin_printf("B: 0x%016llx ---- %g\n", punner.o, q);
-+
-+  d = q - 5;
-+  if(d < 0)
-+    d = -d;
-+  if (d > 0.1)
-+    __builtin_abort();
-+}
-+
-+static int __attribute__((noinline,noclone,hot))
-+bar (int order, double q, double c[])
-+{
-+  int ni, nn, i, e;
-+  double g2, x2, de, s, ratio, ff;
-+
-+  nn = 0;
-+  e = order & 1;
-+  s = 0;
-+  ratio = 0;
-+  x2 = 0;
-+  g2 = 0;
-+
-+  if(q == 0.0)
-+    return 0;
-+
-+  if (order < 5)
-+    {
-+      ratio = 1.0 / q;
-+      nn = order;
-+    }
-+
-+  ni = -nn;
-+
-+  while(1)
-+    {
-+      de = ratio - g2 - x2;
-+
-+      foo (0, q, &ff, &g2, e, ni);
-+
-+      if((int)de == 0)
-+        break;
-+    }
-+
-+  s += 2 * nn * c[nn];
-+
-+  for (i = 0; i < 1; i++)
-+    {
-+      c[0] = nn;
-+      for (; i < 10; i++)
-+        c[i] = 0.0;
-+      c[0] /= s;
-+    }
-+
-+  return 0;
-+}
-+
-+int
-+main ()
-+{
-+  double c[1000];
-+
-+  bar (1, 5.0, c);
-+  return 0;
-+}
-Index: gcc/testsuite/gcc.target/i386/pr63538.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr63538.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr63538.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,13 @@
-+/* PR target/63538 */
-+/* { dg-do compile } */
-+/* { dg-require-effective-target lp64 } */
-+/* { dg-options "-O2 -mcmodel=medium -mlarge-data-threshold=0" } */
-+
-+static char *str = "Hello World";
-+
-+char *foo ()
-+{
-+  return str;
-+}
-+
-+/* { dg-final { scan-assembler "movabs" } } */
-Index: gcc/testsuite/gcc.target/i386/pr57003.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr57003.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr57003.c	(.../branches/gcc-4_9-branch)
-@@ -1,5 +1,5 @@
- /* PR rtl-optimization/57003 */
--/* { dg-do run } */
-+/* { dg-do run { target { ! x32 } } } */
- /* { dg-options "-O2" } */
- 
- #define N 2001
-Index: gcc/testsuite/gcc.target/i386/pr60516.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr60516.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr60516.c	(.../branches/gcc-4_9-branch)
-@@ -1,5 +1,5 @@
- /* PR target/60516 */
--/* { dg-do compile } */
-+/* { dg-do compile { target { ! x32 } } } */
- /* { dg-options "-O2" } */
- 
- struct S { char c[65536]; };
-Index: gcc/testsuite/gcc.target/i386/avx256-unaligned-load-7.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-7.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-7.c	(.../branches/gcc-4_9-branch)
-@@ -33,7 +33,7 @@
-   cp = mp;
-   dp = lp;
- 
--  for (i = N; i >= 0; i--)
-+  for (i = N; i > 0; i--)
-     {
-       *cp++ = str;
-       *dp++ = str;
-@@ -44,13 +44,13 @@
-   cp = mp;
-   dp = lp;
- 
--  for (i = N; i >= 0; i--)
-+  for (i = N; i > 0; i--)
-     {
-       *ap++ = *cp++;
-       *bp++ = *dp++;
-     }
- 
--  for (i = N; i >= 0; i--)
-+  for (i = N; i > 0; i--)
-     {
-       if (strcmp (*--ap, "STR") != 0)
- 	abort ();
-Index: gcc/testsuite/gcc.target/i386/pr59927.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr59927.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr59927.c	(.../branches/gcc-4_9-branch)
-@@ -1,5 +1,5 @@
- /* PR target/59927 */
--/* { dg-do compile } */
-+/* { dg-do compile { target { ! x32 } } } */
- /* { dg-options "-O2 -g" } */
- 
- extern void baz (int) __attribute__ ((__ms_abi__));
-Index: gcc/testsuite/gcc.target/i386/pr63947.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr63947.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr63947.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,9 @@
-+/* PR target/63947 */
-+/* { dg-do assemble } */
-+/* { dg-options "-Os" } */
-+/* { dg-additional-options "-march=i686" { target ia32 } } */
-+
-+long double foo (unsigned a, unsigned b)
-+{
-+  return a + b < a;
-+}
-Index: gcc/testsuite/gcc.target/i386/pr64513.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/pr64513.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/pr64513.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,17 @@
-+/* PR target/64513 */
-+/* { dg-do compile } */
-+/* { dg-options "-O2 -mstack-arg-probe" } */
-+
-+struct A {};
-+struct B { struct A y; };
-+int foo (struct A);
-+
-+int
-+bar (int x)
-+{
-+  struct B b;
-+  int c;
-+  while (x--)
-+    c = foo (b.y);
-+  return c;
-+}
-Index: gcc/testsuite/gcc.target/i386/avx2-pr64286.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/avx2-pr64286.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/avx2-pr64286.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,37 @@
-+/* PR rtl-optimization/64286 */
-+/* { dg-do run } */
-+/* { dg-options "-O2 -mavx2" } */
-+/* { dg-require-effective-target avx2 } */
-+
-+#include <string.h>
-+#include <stdlib.h>
-+#include <x86intrin.h>
-+#include "avx2-check.h"
-+
-+__m128i v;
-+__m256i w;
-+
-+__attribute__((noinline, noclone)) void
-+foo (__m128i *p, __m128i *q)
-+{
-+  __m128i a = _mm_loadu_si128 (p);
-+  __m128i b = _mm_xor_si128 (a, v);
-+  w = _mm256_cvtepu8_epi16 (a);
-+  *q = b;
-+}
-+
-+static void
-+avx2_test (void)
-+{
-+  v = _mm_set1_epi8 (0x40);
-+  __m128i c = _mm_set_epi8 (16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1);
-+  __m128i d;
-+  foo (&c, &d);
-+  __m128i e = _mm_set_epi8 (0x50, 0x4f, 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49,
-+			    0x48, 0x47, 0x46, 0x45, 0x44, 0x43, 0x42, 0x41);
-+  __m256i f = _mm256_set_epi16 (16, 15, 14, 13, 12, 11, 10, 9,
-+				8, 7, 6, 5, 4, 3, 2, 1);
-+  if (memcmp (&w, &f, sizeof (w)) != 0
-+      || memcmp (&d, &e, sizeof (d)) != 0)
-+    abort ();
-+}
-Index: gcc/testsuite/gcc.target/i386/memset-strategy-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/i386/memset-strategy-2.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.target/i386/memset-strategy-2.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,10 @@
-+/* PR target/64108 */
-+/* { dg-do compile } */
-+/* { dg-options "-O2 -march=atom -mmemset-strategy=libcall:-1:align -minline-all-stringops" } */
-+
-+char a[2048];
-+void t (void)
-+{
-+  __builtin_memset (a, 1, 2048);
-+}
-+
-Index: gcc/testsuite/gcc.target/h8300/pragma-isr.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/h8300/pragma-isr.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.target/h8300/pragma-isr.c	(.../branches/gcc-4_9-branch)
-@@ -18,23 +18,3 @@
- {
-   foo ();
- }
--/* Check whether rte is generated for two ISRs.  */
--/* { dg-do compile { target h8300-*-* } }  */
--/* { dg-options "-O3" }  */
--/* { dg-final { scan-assembler-times "rte" 2} }  */
--
--extern void foo (void);
--
--#pragma interrupt
--void
--isr1 (void)
--{
--  foo ();
--}
--
--#pragma interrupt
--void
--isr2 (void)
--{
--  foo ();
--}
-Index: gcc/testsuite/gcc.target/h8300/pragma-isr2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/h8300/pragma-isr2.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.target/h8300/pragma-isr2.c	(.../branches/gcc-4_9-branch)
-@@ -19,24 +19,3 @@
- {
-   return 0;
- }
--/* Check whether rte is generated only for an ISR.  */
--/* { dg-do compile { target h8300-*-* } }  */
--/* { dg-options "-O" }  */
--/* { dg-final { scan-assembler-times "rte" 1 } }  */
--
--#pragma interrupt
--void
--isr (void)
--{
--}
--
--void
--delay (int a)
--{
--}
--
--int
--main (void)
--{
--  return 0;
--}
-Index: gcc/testsuite/gcc.target/h8300/h8300.exp
-===================================================================
---- a/src/gcc/testsuite/gcc.target/h8300/h8300.exp	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.target/h8300/h8300.exp	(.../branches/gcc-4_9-branch)
-@@ -39,44 +39,3 @@
- 
- # All done.
- dg-finish
--# Copyright (C) 2013-2014 Free Software Foundation, Inc.
--
--# This program is free software; you can redistribute it and/or modify
--# it under the terms of the GNU General Public License as published by
--# the Free Software Foundation; either version 3 of the License, or
--# (at your option) any later version.
--# 
--# This program is distributed in the hope that it will be useful,
--# but WITHOUT ANY WARRANTY; without even the implied warranty of
--# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--# GNU General Public License for more details.
--# 
--# You should have received a copy of the GNU General Public License
--# along with GCC; see the file COPYING3.  If not see
--# <http://www.gnu.org/licenses/>.
--
--# GCC testsuite that uses the `dg.exp' driver.
--
--# Exit immediately if this isn't a h8300 target.
--if ![istarget h8300*-*-*] then {
--  return
--}
--
--# Load support procs.
--load_lib gcc-dg.exp
--
--# If a testcase doesn't have special options, use these.
--global DEFAULT_CFLAGS
--if ![info exists DEFAULT_CFLAGS] then {
--    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
--}
--
--# Initialize `dg'.
--dg-init
--
--# Main loop.
--dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
--	"" $DEFAULT_CFLAGS
--
--# All done.
--dg-finish
-Index: gcc/testsuite/gcc.target/sh/pr64507.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/sh/pr64507.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.target/sh/pr64507.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,25 @@
-+/* Check that the __builtin_strnlen returns 0 with with 
-+   non-constant 0 length.  */
-+/* { dg-do run } */
-+/* { dg-options "-O2" } */
-+
-+extern int snprintf(char *, int, const char *, ...);
-+extern void abort (void);
-+
-+int main()
-+ {
-+   int i;
-+   int cmp = 0;
-+   char buffer[1024];
-+   const char* s = "the string";
-+
-+   snprintf(buffer, 4, "%s", s);
-+
-+   for (i = 1; i < 4; i++)
-+     cmp += __builtin_strncmp(buffer, s, i - 1);
-+
-+  if (cmp)
-+    abort();
-+
-+  return 0;
-+}
-Index: gcc/testsuite/gcc.target/sh/pr51244-20-sh2a.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/sh/pr51244-20-sh2a.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.target/sh/pr51244-20-sh2a.c	(.../branches/gcc-4_9-branch)
-@@ -3,12 +3,12 @@
- /* { dg-do compile }  */
- /* { dg-options "-O2" } */
- /* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
--/* { dg-final { scan-assembler-times "tst" 5 } } */
--/* { dg-final { scan-assembler-times "movt" 0 } } */
-+/* { dg-final { scan-assembler-times "tst" 6 } } */
-+/* { dg-final { scan-assembler-times "movt" 1 } } */
- /* { dg-final { scan-assembler-times "nott" 1 } } */
- /* { dg-final { scan-assembler-times "cmp/eq" 2 } } */
- /* { dg-final { scan-assembler-times "cmp/hi" 4 } } */
- /* { dg-final { scan-assembler-times "cmp/gt" 3 } } */
--/* { dg-final { scan-assembler-times "not\t" 1 } } */
-+/* { dg-final { scan-assembler-not "not\t" } } */
- 
- #include "pr51244-20.c"
-Index: gcc/testsuite/gcc.target/sh/pr51244-20.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/sh/pr51244-20.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.target/sh/pr51244-20.c	(.../branches/gcc-4_9-branch)
-@@ -1,15 +1,15 @@
- /* Check that the SH specific sh_treg_combine RTL optimization pass works as
-    expected.  On SH2A the expected insns are slightly different, see
--   pr51244-21.c.  */
-+   pr51244-20-sh2a.c.  */
- /* { dg-do compile }  */
- /* { dg-options "-O2" } */
- /* { dg-skip-if "" { "sh*-*-*" } { "-m5*" "-m2a*" } { "" } } */
--/* { dg-final { scan-assembler-times "tst" 6 } } */
--/* { dg-final { scan-assembler-times "movt" 1 } } */
-+/* { dg-final { scan-assembler-times "tst" 7 } } */
-+/* { dg-final { scan-assembler-times "movt" 2 } } */
- /* { dg-final { scan-assembler-times "cmp/eq" 2 } } */
- /* { dg-final { scan-assembler-times "cmp/hi" 4 } } */
- /* { dg-final { scan-assembler-times "cmp/gt" 2 } } */
--/* { dg-final { scan-assembler-times "not\t" 1 } } */
-+/* { dg-final { scan-assembler-not "not\t" } } */
- 
- 
- /* non-SH2A: 2x tst, 1x movt, 2x cmp/eq, 1x cmp/hi
-@@ -81,7 +81,7 @@
- }
- 
- 
--/* 2x tst, 1x cmp/hi, 1x not  */
-+/* 3x tst, 1x movt, 1x cmp/hi, 1x not  */
- static inline int
- blk_oversized_queue_5 (int* q)
- {
-Index: gcc/testsuite/gcc.target/sh/torture/pr63783-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/sh/torture/pr63783-1.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.target/sh/torture/pr63783-1.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,29 @@
-+/* { dg-do run }  */
-+/* { dg-additional-options "-std=c99" }  */
-+
-+#include <assert.h>
-+
-+int decision_result;
-+int val;
-+int truecount = 0;
-+
-+static void __attribute__((noinline))
-+buggy (int flag)
-+{
-+  int condition;
-+  if(flag == 0)
-+    condition = val != 0;
-+  else
-+    condition = !decision_result;
-+  if (condition)
-+     truecount++;
-+}
-+
-+int
-+main (void)
-+{
-+  decision_result = 1;
-+  buggy(1);
-+  assert (truecount == 0);
-+  return 0;
-+}
-Index: gcc/testsuite/gcc.target/sh/torture/pr63783-2.c
-===================================================================
---- a/src/gcc/testsuite/gcc.target/sh/torture/pr63783-2.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.target/sh/torture/pr63783-2.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,29 @@
-+/* { dg-do run }  */
-+/* { dg-additional-options "-std=c99" }  */
-+
-+#include <assert.h>
-+
-+long long decision_result;
-+long long val;
-+int truecount = 0;
-+
-+static void __attribute__((noinline))
-+buggy (int flag)
-+{
-+  int condition;
-+  if(flag == 0)
-+    condition = val != 0;
-+  else
-+    condition = !decision_result;
-+  if (condition)
-+     truecount++;
-+}
-+
-+int
-+main (void)
-+{
-+  decision_result = 1;
-+  buggy(1);
-+  assert (truecount == 0);
-+  return 0;
-+}
-Index: gcc/testsuite/go.test/go-test.exp
-===================================================================
---- a/src/gcc/testsuite/go.test/go-test.exp	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/go.test/go-test.exp	(.../branches/gcc-4_9-branch)
-@@ -241,7 +241,11 @@
- 	    if [check_effective_target_ilp32] {
- 		set goarch "ppc"
- 	    } else {
--		set goarch "ppc64"
-+		if [istarget "powerpc64le-*-*"] {
-+		    set goarch "ppc64le"
-+		} else {
-+		    set goarch "ppc64"
-+		}
- 	    }
- 	}
- 	"sparc*-*-*" {
-Index: gcc/testsuite/gfortran.dg/pr64528.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/pr64528.f90	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/pr64528.f90	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,20 @@
-+! PR fortran/64528
-+! { dg-do compile }
-+! { dg-options "-O -fno-tree-dce -fno-tree-ccp" }
-+
-+program pr64528
-+  interface
-+     subroutine foo(x)
-+       integer, value :: x
-+     end subroutine foo
-+  end interface
-+  integer :: x
-+  x = 10
-+  call foo(x)
-+  if(x .ne. 10) then
-+  endif
-+end program pr64528
-+subroutine foo(x)
-+  integer, value :: x
-+  x = 11
-+end subroutine foo
-Index: gcc/testsuite/gfortran.dg/typebound_operator_20.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/typebound_operator_20.f90	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/typebound_operator_20.f90	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,53 @@
-+! { dg-do run }
-+!
-+! PR 63733: [4.8/4.9/5 Regression] [OOP] wrong resolution for OPERATOR generics
-+!
-+! Original test case from Alberto F. Martín Huertas <amartin@cimne.upc.edu>
-+! Slightly modified by Salvatore Filippone <sfilippone@uniroma2.it>
-+! Further modified by Janus Weil <janus@gcc.gnu.org>
-+
-+module overwrite
-+  type parent
-+   contains
-+     procedure :: sum => sum_parent
-+     generic   :: operator(+) => sum
-+  end type
-+
-+  type, extends(parent) ::  child
-+  contains
-+    procedure :: sum => sum_child
-+  end type
-+
-+contains
-+
-+  integer function sum_parent(op1,op2)
-+    implicit none
-+    class(parent), intent(in) :: op1, op2
-+    sum_parent = 0
-+  end function
-+
-+  integer function sum_child(op1,op2)
-+    implicit none
-+    class(child) , intent(in) :: op1
-+    class(parent), intent(in) :: op2
-+    sum_child = 1
-+  end function
-+
-+end module
-+
-+program drive
-+  use overwrite
-+  implicit none
-+
-+  type(parent) :: m1, m2
-+  class(parent), pointer :: mres
-+  type(child)  :: h1, h2
-+  class(parent), pointer :: hres
-+
-+  if (m1 + m2 /= 0) call abort()
-+  if (h1 + m2 /= 1) call abort()
-+  if (h1%sum(h2) /= 1) call abort()
-+
-+end
-+
-+! { dg-final { cleanup-modules "overwrite" } }
-Index: gcc/testsuite/gfortran.dg/typebound_call_26.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/typebound_call_26.f90	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/typebound_call_26.f90	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,30 @@
-+! { dg-do compile }
-+!
-+! PR 64244: [4.8/4.9/5 Regression] ICE at class.c:236 when using non_overridable
-+!
-+! Contributed by Ondřej Čertík <ondrej.certik@gmail.com>
-+
-+module m
-+  implicit none
-+
-+  type :: A
-+  contains
-+    generic :: f => g
-+    procedure, non_overridable :: g
-+  end type
-+
-+contains
-+
-+  subroutine g(this)
-+    class(A), intent(in) :: this
-+  end subroutine
-+
-+end module
-+
-+
-+program test_non_overridable
-+  use m, only: A
-+  implicit none
-+  class(A), allocatable :: h
-+  call h%f()
-+end
-Index: gcc/testsuite/gfortran.dg/dependency_45.f90
-===================================================================
---- a/src/gcc/testsuite/gfortran.dg/dependency_45.f90	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gfortran.dg/dependency_45.f90	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,12 @@
-+! { dg-do run }
-+! { dg-options "-Warray-temporaries" }
-+! PR 56867 - substrings were not checked for dependency.
-+program main
-+  character(len=4) :: a
-+  character(len=4) :: c(3)
-+  c(1) = 'abcd'
-+  c(2) = '1234'
-+  c(3) = 'wxyz'
-+  c(:)(1:2) = c(2)(2:3)   ! { dg-warning "array temporary" }
-+  if (c(3) .ne. '23yz') call abort
-+end program main
-Index: gcc/testsuite/gcc.c-torture/execute/pr63659.c
-===================================================================
---- a/src/gcc/testsuite/gcc.c-torture/execute/pr63659.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr63659.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,29 @@
-+/* PR rtl-optimization/63659 */
-+
-+int a, b, c, *d = &b, g, h, i;
-+unsigned char e;
-+char f;
-+
-+int
-+main ()
-+{
-+  while (a)
-+    {
-+      for (a = 0; a; a++)
-+	for (; c; c++)
-+	  ;
-+      if (i)
-+	break;
-+    }
-+
-+  char j = c, k = -1, l;
-+  l = g = j >> h;
-+  f = l == 0 ? k : k % l;
-+  e = 0 ? 0 : f;
-+  *d = e;
-+
-+  if (b != 255)
-+    __builtin_abort ();
-+
-+  return 0;
-+}
-Index: gcc/testsuite/gcc.c-torture/compile/pr64067.c
-===================================================================
---- a/src/gcc/testsuite/gcc.c-torture/compile/pr64067.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.c-torture/compile/pr64067.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,10 @@
-+/* PR middle-end/64067 */
-+
-+struct S { int s; };
-+int *const v[1] = { &((struct S) { .s = 42 }).s };
-+
-+int *
-+foo (void)
-+{
-+  return v[0];
-+}
-Index: gcc/testsuite/gcc.c-torture/compile/pr64269.c
-===================================================================
---- a/src/gcc/testsuite/gcc.c-torture/compile/pr64269.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.c-torture/compile/pr64269.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,9 @@
-+/* PR tree-optimization/64269 */
-+
-+void
-+foo (char *p)
-+{
-+  __SIZE_TYPE__ s = ~(__SIZE_TYPE__)0;
-+  *p = 0;
-+  __builtin_memset (p + 1, 0, s);
-+}
-Index: gcc/testsuite/gnat.dg/opt45.adb
-===================================================================
---- a/src/gcc/testsuite/gnat.dg/opt45.adb	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gnat.dg/opt45.adb	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,38 @@
-+-- { dg-do compile }

-+-- { dg-options "-O3" }

-+

-+procedure Opt45 is

-+

-+  type Index_T is mod 2 ** 32;

-+  for Index_T'Size use 32;

-+  for Index_T'Alignment use 1;

-+

-+  type Array_T is array (Index_T range <>) of Natural;

-+  type Array_Ptr_T is access all Array_T;

-+

-+  My_Array_1 : aliased Array_T := (1, 2);

-+  My_Array_2 : aliased Array_T := (3, 4);

-+

-+  Array_Ptr : Array_Ptr_T := null;

-+  Index : Index_T := Index_T'First;

-+

-+  My_Value : Natural := Natural'First;

-+

-+  procedure Proc (Selection : Positive) is

-+  begin

-+    if Selection = 1 then

-+      Array_Ptr := My_Array_1'Access;

-+      Index := My_Array_1'First;

-+    else

-+      Array_Ptr := My_Array_2'Access;

-+      Index := My_Array_2'First;

-+    end if;

-+

-+    if My_Value = Natural'First then

-+      My_Value := Array_Ptr.all (Index);

-+    end if;

-+  end;

-+

-+begin

-+  Proc (2);

-+end;

-Index: gcc/testsuite/gnat.dg/opt47.adb
-===================================================================
---- a/src/gcc/testsuite/gnat.dg/opt47.adb	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gnat.dg/opt47.adb	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,31 @@
-+-- { dg-do run { target i?86-*-* x86_64-*-* alpha*-*-* ia64-*-* } }
-+-- { dg-options "-O2" }
-+
-+with Ada.Characters.Handling;   use Ada.Characters.Handling;
-+with Interfaces;                use Interfaces;
-+with Ada.Unchecked_Conversion;
-+
-+procedure Opt47 is
-+
-+   subtype String4 is String (1 .. 4);
-+   function To_String4 is new Ada.Unchecked_Conversion (Unsigned_32, String4);
-+   type Arr is array (Integer range <>) of Unsigned_32;
-+   Leaf : Arr (1 .. 4) := (1349478766, 1948272498, 1702436946, 1702061409);
-+   Value : Unsigned_32;
-+   Result : String (1 .. 32);
-+   Last : Integer := 0;
-+
-+begin
-+   for I in 1 .. 4 loop
-+      Value := Leaf (I);
-+      for J in reverse String4'Range loop
-+         if Is_Graphic (To_String4 (Value)(J)) then
-+            Last := Last + 1;
-+            Result (Last) := To_String4 (Value)(J);
-+         end if;
-+      end loop;
-+   end loop;
-+   if Result (1) /= 'P' then
-+      raise Program_Error;
-+   end if;
-+end;
-Index: gcc/testsuite/gcc.dg/pr63762.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/pr63762.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/pr63762.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,77 @@
-+/* PR middle-end/63762 */
-+/* { dg-do assemble } */
-+/* { dg-options "-O2" } */
-+
-+#include <stdlib.h>
-+
-+void *astFree ();
-+void *astMalloc ();
-+void astNegate (void *);
-+int astGetNegated (void *);
-+void astGetRegionBounds (void *, double *, double *);
-+int astResampleF (void *, ...);
-+
-+extern int astOK;
-+
-+int
-+MaskF (int inside, int ndim, const int lbnd[], const int ubnd[],
-+       float in[], float val)
-+{
-+
-+  void *used_region;
-+  float *c, *d, *out, *tmp_out;
-+  double *lbndgd, *ubndgd;
-+  int *lbndg, *ubndg, idim, ipix, nax, nin, nout, npix, npixg, result = 0;
-+  if (!astOK) return result;
-+  lbndg = astMalloc (sizeof (int)*(size_t) ndim);
-+  ubndg = astMalloc (sizeof (int)*(size_t) ndim);
-+  lbndgd = astMalloc (sizeof (double)*(size_t) ndim);
-+  ubndgd = astMalloc (sizeof (double)*(size_t) ndim);
-+  if (astOK)
-+    {
-+      astGetRegionBounds (used_region, lbndgd, ubndgd);
-+      npix = 1;
-+      npixg = 1;
-+      for (idim = 0; idim < ndim; idim++)
-+        {
-+          lbndg[ idim ] = lbnd[ idim ];
-+          ubndg[ idim ] = ubnd[ idim ];
-+          npix *= (ubnd[ idim ] - lbnd[ idim ] + 1);
-+          if (npixg >= 0) npixg *= (ubndg[ idim ] - lbndg[ idim ] + 1);
-+        }
-+      if (npixg <= 0 && astOK)
-+        {
-+          if ((inside != 0) == (astGetNegated( used_region ) != 0))
-+            {
-+              c = in;
-+              for (ipix = 0; ipix < npix; ipix++) *(c++) = val;
-+              result = npix;
-+            }
-+        }
-+      else if (npixg > 0 && astOK)
-+        {
-+          if ((inside != 0) == (astGetNegated (used_region) != 0))
-+            {
-+              tmp_out = astMalloc (sizeof (float)*(size_t) npix);
-+              if (tmp_out)
-+                {
-+                  c = tmp_out;
-+                  for (ipix = 0; ipix < npix; ipix++) *(c++) = val;
-+                  result = npix - npixg;
-+                }
-+              out = tmp_out;
-+            }
-+          else
-+            {
-+              tmp_out = NULL;
-+              out = in;
-+            }
-+          if (inside) astNegate (used_region);
-+          result += astResampleF (used_region, ndim, lbnd, ubnd, in, NULL,
-+                                  NULL, NULL, 0, 0.0, 100, val, ndim,
-+                                  lbnd, ubnd, lbndg, ubndg, out, NULL);
-+          if (inside) astNegate (used_region);
-+        }
-+    }
-+  return result;
-+}
-Index: gcc/testsuite/gcc.dg/pr51879-12.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/pr51879-12.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/pr51879-12.c	(.../branches/gcc-4_9-branch)
-@@ -24,6 +24,6 @@
-   baz (a);
- }
- 
--/* { dg-final { scan-tree-dump-times "bar \\(" 1 "pre"} } */
--/* { dg-final { scan-tree-dump-times "bar2 \\(" 1 "pre"} } */
-+/* { dg-final { scan-tree-dump-times "bar \\(" 1 "pre" { xfail *-*-* } } } */
-+/* { dg-final { scan-tree-dump-times "bar2 \\(" 1 "pre" { xfail *-*-* } } } */
- /* { dg-final { cleanup-tree-dump "pre" } } */
-Index: gcc/testsuite/gcc.dg/pr64536.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/pr64536.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/pr64536.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,67 @@
-+/* PR rtl-optimization/64536 */
-+/* { dg-do link } */
-+/* { dg-options "-O2" } */
-+/* { dg-additional-options "-fPIC" { target fpic } } */
-+
-+struct S { long q; } *h;
-+long a, b, g, j, k, *c, *d, *e, *f, *i;
-+long *baz (void)
-+{
-+  asm volatile ("" : : : "memory");
-+  return e;
-+}
-+
-+void
-+bar (int x)
-+{
-+  int y;
-+  for (y = 0; y < x; y++)
-+    {
-+      switch (b)
-+	{
-+	case 0:
-+	case 2:
-+	  a++;
-+	  break;
-+	case 3:
-+	  a++;
-+	  break;
-+	case 1:
-+	  a++;
-+	}
-+      if (d)
-+	{
-+	  f = baz ();
-+	  g = k++;
-+	  if (&h->q)
-+	    {
-+	      j = *f;
-+	      h->q = *f;
-+	    }
-+	  else
-+	    i = (long *) (h->q = *f);
-+	  *c++ = (long) f;
-+	  e += 6;
-+	}
-+      else
-+	{
-+	  f = baz ();
-+	  g = k++;
-+	  if (&h->q)
-+	    {
-+	      j = *f;
-+	      h->q = *f;
-+	    }
-+	  else
-+	    i = (long *) (h->q = *f);
-+	  *c++ = (long) f;
-+	  e += 6;
-+	}
-+    }
-+}
-+
-+int
-+main ()
-+{
-+  return 0;
-+}
-Index: gcc/testsuite/gcc.dg/pr63665.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/pr63665.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/pr63665.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,18 @@
-+/* { dg-do run } */
-+/* { dg-require-effective-target int32plus } */
-+/* { dg-options "-O -fno-tree-ccp -fno-tree-fre -fno-tree-copy-prop -fwrapv" } */
-+
-+static inline int
-+test5 (int x)
-+{
-+  int y = 0x80000000;
-+  return x + y;
-+}
-+
-+int
-+main ()
-+{
-+  if (test5 (0x80000000) != 0)
-+    __builtin_abort ();
-+  return 0;
-+}
-Index: gcc/testsuite/gcc.dg/pr62167-run.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/pr62167-run.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/pr62167-run.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,47 @@
-+/* { dg-do run } */
-+/* { dg-options "-O2 -ftree-tail-merge" } */
-+
-+struct node
-+{
-+  struct node *next;
-+  struct node *prev;
-+};
-+
-+struct node node;
-+
-+struct head
-+{
-+  struct node *first;
-+};
-+
-+struct head heads[5];
-+
-+int k = 2;
-+
-+struct head *head = &heads[2];
-+
-+int
-+main ()
-+{
-+  struct node *p;
-+
-+  node.next = (void*)0;
-+
-+  node.prev = (void *)head;
-+
-+  head->first = &node;
-+
-+  struct node *n = head->first;
-+
-+  struct head *h = &heads[k];
-+
-+  heads[2].first = n->next;
-+
-+  if ((void*)n->prev == (void *)h)
-+    p = h->first;
-+  else
-+    /* Dead tbaa-unsafe load from ((struct node *)&heads[2])->next.  */
-+    p = n->prev->next;
-+
-+  return !(p == (void*)0);
-+}
-Index: gcc/testsuite/gcc.dg/pr52769.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/pr52769.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/pr52769.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,24 @@
-+/* PR c/52769 */
-+/* { dg-do run } */
-+/* { dg-options "-O3" } */
-+
-+typedef struct
-+{
-+  int should_be_zero;
-+  char s[6];
-+  int x;
-+} foo_t;
-+
-+int
-+main (void)
-+{
-+  volatile foo_t foo = {
-+    .s = "123456",
-+    .x = 2
-+  };
-+
-+  if (foo.should_be_zero != 0)
-+    __builtin_abort ();
-+
-+  return 0;
-+}
-Index: gcc/testsuite/gcc.dg/pr62167.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/pr62167.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/pr62167.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,50 @@
-+/* { dg-do compile } */
-+/* { dg-options "-O2 -ftree-tail-merge -fdump-tree-pre" } */
-+
-+struct node
-+{
-+  struct node *next;
-+  struct node *prev;
-+};
-+
-+struct node node;
-+
-+struct head
-+{
-+  struct node *first;
-+};
-+
-+struct head heads[5];
-+
-+int k = 2;
-+
-+struct head *head = &heads[2];
-+
-+int
-+main ()
-+{
-+  struct node *p;
-+
-+  node.next = (void*)0;
-+
-+  node.prev = (void *)head;
-+
-+  head->first = &node;
-+
-+  struct node *n = head->first;
-+
-+  struct head *h = &heads[k];
-+
-+  heads[2].first = n->next;
-+
-+  if ((void*)n->prev == (void *)h)
-+    p = h->first;
-+  else
-+    /* Dead tbaa-unsafe load from ((struct node *)&heads[2])->next.  */
-+    p = n->prev->next;
-+
-+  return !(p == (void*)0);
-+}
-+
-+/* { dg-final { scan-tree-dump-not "Removing basic block" "pre"} } */
-+/* { dg-final { cleanup-tree-dump "pre" } } */
-Index: gcc/testsuite/gcc.dg/torture/pr63738.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/torture/pr63738.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/torture/pr63738.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,27 @@
-+/*  { dg-do compile } */
-+
-+#include <setjmp.h>
-+
-+struct longjmp_buffer {
-+  jmp_buf buf;
-+};
-+
-+void plouf();
-+
-+extern long interprete()
-+{
-+  long * sp;
-+  int i;
-+  long *args;
-+  int n;
-+
-+  struct longjmp_buffer raise_buf;
-+  setjmp (raise_buf.buf);
-+
-+  plouf();
-+  sp -= 4;
-+  for (i = 0; i < n; i++)
-+    args[i] = sp[10-i];
-+  plouf();
-+  return 0;
-+}
-Index: gcc/testsuite/gcc.dg/torture/pr62238.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/torture/pr62238.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/torture/pr62238.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,30 @@
-+/* { dg-do run } */
-+
-+int a[4], b, c, d; 
-+
-+int
-+fn1 (int p)
-+{
-+  for (; d; d++)
-+    {
-+      unsigned int h;
-+      for (h = 0; h < 3; h++)
-+	{
-+	  if (a[c+c+h])
-+	    {
-+	      if (p)
-+		break;
-+	      return 0;
-+	    }
-+	  b = 0;
-+	}
-+    }
-+  return 0;
-+}
-+
-+int
-+main ()
-+{
-+  fn1 (0);
-+  return 0;
-+}
-Index: gcc/testsuite/gcc.dg/pr64563.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/pr64563.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/pr64563.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,14 @@
-+/* PR tree-optimization/64563 */
-+/* { dg-do compile } */
-+/* { dg-options "-Os -Wtype-limits" } */
-+
-+int a, b, c, d, f;
-+unsigned int e;
-+
-+void
-+foo (void)
-+{
-+  d = b = (a != (e | 4294967288UL));
-+  if (!d)
-+    c = f || b;
-+}
-Index: gcc/testsuite/gcc.dg/ipa/pr64041.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/ipa/pr64041.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/ipa/pr64041.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,64 @@
-+/* { dg-do run } */
-+/* { dg-options "-O2" } */
-+
-+int printf (const char *, ...);
-+
-+int a, b = 1, d;
-+
-+union U1
-+{
-+  unsigned int f0;
-+  int f1;
-+};
-+
-+union U2
-+{
-+  int f2;
-+  int f3;
-+} c;
-+
-+int
-+fn1 (int p)
-+{
-+  int t = p && a || p && a && p; 
-+  return t ? t : a;
-+}
-+
-+unsigned
-+fn2 (union U1 p1, union U2 p2)
-+{
-+  if (p1.f1 <= 0)
-+    {
-+      for (; p2.f2;)
-+	c.f2 = 0;
-+      p2.f2 = fn1 (d);
-+    }
-+  return p2.f3;
-+}
-+
-+int g = 0;
-+
-+int
-+foo ()
-+{
-+  if (b)
-+    {
-+      union U1 f = { 0xFFFFFFFFU }; 
-+
-+      fn2 (f, c);
-+    }
-+  g = 1;
-+  return 0; 
-+}
-+
-+
-+int
-+main ()
-+{
-+  foo ();
-+
-+  if (g == 0)
-+    __builtin_abort ();
-+
-+  return 0;
-+}
-Index: gcc/testsuite/gcc.dg/ipa/pr63551.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/ipa/pr63551.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/ipa/pr63551.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,33 @@
-+/* { dg-do run } */
-+/* { dg-options "-Os" } */
-+
-+union U
-+{
-+  unsigned int f0;
-+  int f1;
-+};
-+
-+int a, d;
-+
-+void
-+fn1 (union U p)
-+{
-+  if (p.f1 <= 0)
-+    if (a)
-+      d = 0;
-+}
-+
-+void
-+fn2 ()
-+{
-+  d = 0;
-+  union U b = { 4294967286U };
-+  fn1 (b);
-+}
-+
-+int
-+main ()
-+{
-+  fn2 ();
-+  return 0;
-+}
-Index: gcc/testsuite/gcc.dg/tm/pr64391.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/tm/pr64391.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/tm/pr64391.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,10 @@
-+/* PR middle-end/64391 */
-+/* { dg-do compile } */
-+/* { dg-options "-fgnu-tm" } */
-+
-+void
-+foo (void)
-+{
-+#pragma GCC ivdep
-+  while (1);
-+}
-Index: gcc/testsuite/gcc.dg/vect/pr63605.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vect/pr63605.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vect/pr63605.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,22 @@
-+/* { dg-do run } */
-+
-+#include "tree-vect.h"
-+
-+extern void abort (void);
-+
-+int a, b[8] = { 2, 0, 0, 0, 0, 0, 0, 0 }, c[8];
-+
-+int
-+main ()
-+{
-+  int d;
-+  check_vect ();
-+  for (; a < 8; a++)
-+    {
-+      d = b[a] >> 1;
-+      c[a] = d != 0;
-+    }
-+  if (c[0] != 1)
-+    abort ();
-+  return 0;
-+}
-Index: gcc/testsuite/gcc.dg/vect/pr62021.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/vect/pr62021.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/vect/pr62021.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,30 @@
-+/* { dg-require-effective-target vect_simd_clones } */
-+/* { dg-additional-options "-fopenmp-simd" } */
-+/* { dg-additional-options "-mavx" { target avx_runtime } } */
-+
-+#pragma omp declare simd linear(y)
-+__attribute__((noinline)) int *
-+foo (int *x, int y)
-+{
-+  return x + y;
-+}
-+
-+int a[1024];
-+int *b[1024] = { &a[0] };
-+
-+int
-+main ()
-+{
-+  int i;
-+  for (i = 0; i < 1024; i++)
-+    b[i] = &a[1023 - i];
-+  #pragma omp simd
-+  for (i = 0; i < 1024; i++)
-+    b[i] = foo (b[i], i);
-+  for (i = 0; i < 1024; i++)
-+    if (b[i] != &a[1023])
-+      __builtin_abort ();
-+  return 0;
-+}
-+
-+/* { dg-final { cleanup-tree-dump "vect" } } */
-Index: gcc/testsuite/gcc.dg/20141029-1.c
-===================================================================
---- a/src/gcc/testsuite/gcc.dg/20141029-1.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/gcc.dg/20141029-1.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,28 @@
-+/* { dg-do compile } */
-+/* { dg-options "-fstrict-volatile-bitfields -fdump-rtl-final" } */
-+
-+#define PERIPH (*(volatile struct system_periph *)0x81234)
-+
-+struct system_periph {
-+  union {
-+    unsigned short WORD;
-+    struct {
-+      unsigned short a:1;
-+      unsigned short b:1;
-+      unsigned short  :5;
-+      unsigned short c:1;
-+      unsigned short  :8;
-+    } BIT;
-+  } ALL;
-+};
-+
-+void
-+foo()
-+{
-+  while (1)
-+    {
-+      PERIPH.ALL.BIT.a = 1;
-+    }
-+}
-+/* { dg-final { scan-rtl-dump-times "mem/v(/.)*:HI" 4 "final" } } */
-+/* { dg-final { cleanup-rtl-dump "final" } } */
-Index: gcc/testsuite/ChangeLog
-===================================================================
---- a/src/gcc/testsuite/ChangeLog	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/ChangeLog	(.../branches/gcc-4_9-branch)
-@@ -1,3 +1,378 @@
-+2015-01-16  Bernd Edlinger  <bernd.edlinger@hotmail.de>
-+
-+	* c-c++-common/tsan/tsan_barrier.h: New.
-+	* c-c++-common/tsan/atomic_stack.c: Reworked to not depend on sleep.
-+	* c-c++-common/tsan/fd_pipe_race.c: Likewise.
-+	* c-c++-common/tsan/mutexset1.c: Likewise.
-+	* c-c++-common/tsan/race_on_barrier.c: Likewise.
-+	* c-c++-common/tsan/race_on_mutex.c: Likewise.
-+	* c-c++-common/tsan/race_on_mutex2.c: Likewise.
-+	* c-c++-common/tsan/simple_race.c: Likewise.
-+	* c-c++-common/tsan/simple_stack.c: Likewise.
-+	* c-c++-common/tsan/sleep_sync.c: Likewise.
-+	* c-c++-common/tsan/tiny_race.c: Likewise.
-+	* c-c++-common/tsan/tls_race.c: Likewise.
-+	* c-c++-common/tsan/write_in_reader_lock.c: Likewise.
-+	* g++.dg/tsan/atomic_free.C: Likewise.
-+	* g++.dg/tsan/atomic_free2.C: Likewise.
-+	* g++.dg/tsan/cond_race.C: Likewise.
-+	* g++.dg/tsan/tsan_barrier.h: Copied from c-c++-common/tsan. 
-+
-+2015-01-15  Eric Botcazou  <ebotcazou@adacore.com>
-+
-+	* gnat.dg/opt47.adb: New test.
-+
-+2015-01-14  Jakub Jelinek  <jakub@redhat.com>
-+
-+	Backported from mainline
-+	2015-01-12  Jakub Jelinek  <jakub@redhat.com>
-+
-+	PR target/64513
-+	* gcc.target/i386/pr64513.c: New test.
-+
-+	2015-01-13  Jakub Jelinek  <jakub@redhat.com>
-+
-+	PR rtl-optimization/64286
-+	* gcc.target/i386/avx2-pr64286.c: New test.
-+
-+	PR fortran/64528
-+	* gfortran.dg/pr64528.f90: New test.
-+
-+	2015-01-12  Jakub Jelinek  <jakub@redhat.com>
-+
-+	PR tree-optimization/64563
-+	* gcc.dg/pr64563.c: New test.
-+
-+2015-01-14  Marek Polacek  <polacek@redhat.com>
-+
-+	Backport from mainline
-+	2015-01-13  Marek Polacek  <polacek@redhat.com>
-+
-+	PR middle-end/64391
-+	* gcc.dg/tm/pr64391.c: New test.
-+
-+2015-01-13  Marc Glisse  <marc.glisse@inria.fr>
-+
-+	PR c++/54442
-+	* g++.dg/pr54442.C: New file.
-+
-+2015-01-13  Renlin Li  <renlin.li@arm.com>
-+
-+	Backported from mainline
-+	2014-11-19 Renlin Li <renlin.li@arm.com>
-+
-+	PR target/63424
-+	* gcc.target/aarch64/pr63424.c: New Test.
-+
-+2015-01-12  Janus Weil  <janus@gcc.gnu.org>
-+
-+	Backport from mainline
-+	PR fortran/63733
-+	* gfortran.dg/typebound_operator_20.f90: New.
-+
-+2015-01-09  Jakub Jelinek  <jakub@redhat.com>
-+
-+	PR rtl-optimization/64536
-+	* gcc.dg/pr64536.c: New test.
-+
-+2015-01-09  Michael Meissner  <meissner@linux.vnet.ibm.com>
-+
-+	Backport from mainline:
-+	2015-01-06  Michael Meissner  <meissner@linux.vnet.ibm.com>
-+
-+	PR target/64505
-+	* gcc.target/powerpc/pr64505.c: New file to test -m32 -mpowerpc64
-+	fix is correct.
-+
-+2014-01-08  Thomas Koenig  <tkoenig@gcc.gnu.org>
-+
-+	PR fortran/56867
-+	* gfortran.dg/dependency_45.f90:  New test.
-+
-+2015-01-08  Christian Bruel  <christian.bruel@st.com>
-+
-+	PR target/64507
-+	* gcc.target/sh/pr64507.c: New test.
-+
-+2015-01-05  Ian Lance Taylor  <iant@google.com>
-+
-+	Backport from mainline:
-+	2014-11-21  Lynn Boger  <laboger@linux.vnet.ibm.com>
-+
-+	* go.test/go-test.exp (go-set-goarch): Add case for ppc64le goarch
-+	value for go testing.
-+
-+2014-12-28  H.J. Lu  <hongjiu.lu@intel.com>
-+
-+	Backport from mainline:
-+	2014-12-28  H.J. Lu  <hongjiu.lu@intel.com>
-+
-+	* gcc.target/i386/pr57003.c: Skip on x32.
-+	* gcc.target/i386/pr59927.c: Likewise.
-+	* gcc.target/i386/pr60516.c: Likewise.
-+
-+2014-12-27  H.J. Lu  <hongjiu.lu@intel.com>
-+
-+	Backport from mainline:
-+	2014-12-26  H.J. Lu  <hongjiu.lu@intel.com>
-+
-+	PR target/64409
-+	* gcc.target/i386/pr64409.c: New test.
-+
-+2014-12-23  Janus Weil  <janus@gcc.gnu.org>
-+
-+	Backport from mainline
-+	PR fortran/64244
-+	* gfortran.dg/typebound_call_26.f90: New.
-+
-+2014-12-19  Paolo Carlini  <paolo.carlini@oracle.com>
-+
-+	PR c++/60955
-+	* g++.dg/warn/register-parm-1.C: New.
-+
-+2014-12-15  Jakub Jelinek  <jakub@redhat.com>
-+
-+	PR tree-optimization/63551
-+	* gcc.dg/ipa/pr63551.c (fn2): Use 4294967286U instead of
-+	4294967286 to avoid warnings.
-+
-+2014-12-14  H.J. Lu  <hongjiu.lu@intel.com>
-+
-+	Backported from mainline
-+	2014-12-14  H.J. Lu  <hongjiu.lu@intel.com>
-+
-+	PR rtl-optimization/64037
-+	* g++.dg/pr64037.C: New test.
-+
-+2014-12-14  H.J. Lu  <hongjiu.lu@intel.com>
-+
-+	Backported from mainline
-+	2014-12-06  H.J. Lu  <hongjiu.lu@intel.com>
-+
-+	PR target/64200
-+	* gcc.target/i386/memcpy-strategy-4.c: New test.
-+
-+2014-12-13  Jakub Jelinek  <jakub@redhat.com>
-+
-+	Backported from mainline
-+	2014-12-12  Jakub Jelinek  <jakub@redhat.com>
-+
-+	PR tree-optimization/64269
-+	* gcc.c-torture/compile/pr64269.c: New test.
-+
-+2014-12-10  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
-+
-+	Backport from mainline
-+	2014-09-02  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
-+
-+	* gcc.target/powerpc/builtins-1.c: Add tests for vec_ctf,
-+	vec_cts, and vec_ctu.
-+	* gcc.target/powerpc/builtins-2.c: Likewise.
-+
-+	Backport from mainline
-+	2014-08-28  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
-+
-+	* gcc.target/powerpc/builtins-1.c: Add tests for vec_xl, vec_xst,
-+	vec_round, vec_splat, vec_div, and vec_mul.
-+	* gcc.target/powerpc/builtins-2.c: New test.
-+
-+	Backport from mainline
-+	2014-08-20  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
-+
-+	* testsuite/gcc.target/powerpc/builtins-1.c: New test.
-+
-+2014-12-10  Jakub Jelinek  <jakub@redhat.com>
-+
-+	PR tree-optimization/62021
-+	* gcc.dg/vect/pr62021.c: New test.
-+
-+2014-12-09  Uros Bizjak  <ubizjak@gmail.com>
-+
-+	PR bootstrap/64213
-+	Revert:
-+	2014-11-28  H.J. Lu  <hongjiu.lu@intel.com>
-+
-+	PR rtl-optimization/64037
-+	* g++.dg/pr64037.C: New test.
-+
-+2014-12-07  Oleg Endo  <olegendo@gcc.gnu.org>
-+
-+	Backport from mainline
-+	2014-12-07  Oleg Endo  <olegendo@gcc.gnu.org>
-+
-+	* gcc.target/h8300/h8300.exp: Fix duplicated text.
-+	* gcc.target/h8300/pragma-isr.c: Likewise.
-+	* gcc.target/h8300/pragma-isr2.c: Likewise.
-+
-+2014-12-05  H.J. Lu  <hongjiu.lu@intel.com>
-+
-+	Backport from mainline
-+	2014-12-02  H.J. Lu  <hongjiu.lu@intel.com>
-+
-+	PR target/64108
-+	* gcc.target/i386/memset-strategy-2.c: New test.
-+
-+2014-12-05  H.J. Lu  <hongjiu.lu@intel.com>
-+
-+	Backport from mainline
-+	2014-11-28  H.J. Lu  <hongjiu.lu@intel.com>
-+
-+	PR rtl-optimization/64037
-+	* g++.dg/pr64037.C: New test.
-+
-+2014-12-04  Jakub Jelinek  <jakub@redhat.com>
-+
-+	PR c++/56493
-+	* c-c++-common/pr56493.c: New test.
-+
-+2014-12-03  Renlin Li  <Renlin.Li@arm.com>
-+
-+	Backported from mainline
-+	2014-12-03  Renlin Li  <Renlin.Li@arm.com>
-+		    H.J. Lu  <hongjiu.lu@intel.com>
-+
-+	 PR middle-end/63762
-+	 PR target/63661
-+	 * gcc.dg/pr63762.c: New test.
-+	 * gcc.target/i386/pr63661.c: New test.
-+
-+2014-12-01  Martin Jambor  <mjambor@suse.cz>
-+
-+	PR ipa/63551
-+	* gcc.dg/ipa/pr63551.c: New test.
-+	* gcc.dg/ipa/pr64041.c: Likewise.
-+
-+2014-12-01  Richard Biener  <rguenther@suse.de>
-+
-+	PR tree-optimization/63738
-+	* gcc.dg/torture/pr63738.c: Fix call to setjmp.
-+
-+2014-11-28  Jakub Jelinek  <jakub@redhat.com>
-+
-+	Backported from mainline
-+	2014-11-27  Jakub Jelinek  <jakub@redhat.com>
-+
-+	PR middle-end/64067
-+	* gcc.c-torture/compile/pr64067.c: New test.
-+
-+	2014-11-19  Jakub Jelinek  <jakub@redhat.com>
-+
-+	PR tree-optimization/63915
-+	* c-c++-common/gomp/pr60823-4.c: New test.
-+
-+	PR sanitizer/63913
-+	* g++.dg/ubsan/pr63913.C: New test.
-+
-+	2014-10-31  Jakub Jelinek  <jakub@redhat.com>
-+
-+	PR rtl-optimization/63659
-+	* gcc.c-torture/execute/pr63659.c: New test.
-+
-+2014-11-26  Richard Biener  <rguenther@suse.de>
-+
-+	PR middle-end/63738
-+	* gcc.dg/torture/pr63738.c: New testcase.
-+
-+2014-11-26  Richard Biener  <rguenther@suse.de>
-+
-+	Backport from mainline
-+	2014-11-26  Richard Biener  <rguenther@suse.de>
-+
-+	PR tree-optimization/62238
-+	* gcc.dg/torture/pr62238.c: New testcase.
-+
-+	2014-11-07  Richard Biener  <rguenther@suse.de>
-+
-+	PR tree-optimization/63605
-+	* gcc.dg/vect/pr63605.c: New testcase.
-+
-+	2014-10-28  Richard Biener  <rguenther@suse.de>
-+
-+	PR middle-end/63665
-+	* gcc.dg/pr63665.c: New testcase.
-+
-+2014-11-24  Eric Botcazou  <ebotcazou@adacore.com>
-+
-+	* gnat.dg/opt45.adb: New test.
-+
-+2014-11-22  Oleg Endo  <olegendo@gcc.gnu.org>
-+
-+	Backport from mainline
-+	2014-11-22  Oleg Endo  <olegendo@gcc.gnu.org>
-+
-+	PR target/63783
-+	PR target/51244
-+	* gcc.target/sh/torture/pr63783-1.c: New.
-+	* gcc.target/sh/torture/pr63783-2.c: New.
-+	* gcc.target/sh/pr51244-20.c: Adjust.
-+	* gcc.target/sh/pr51244-20-sh2a.c: Adjust.
-+
-+2014-11-19  Uros Bizjak  <ubizjak@gmail.com>
-+
-+	PR target/63947
-+	* gcc.target/i386/pr63947.c: New test.
-+
-+2014-11-19  Tom de Vries  <tom@codesourcery.com>
-+
-+	Backport from mainline
-+	PR tree-optimization/62167
-+	* gcc.dg/pr51879-12.c: Add xfails.
-+	* gcc.dg/pr62167-run.c: New test.
-+	* gcc.dg/pr62167.c: New test.
-+
-+2014-11-13  Teresa Johnson  <tejohnson@google.com>
-+
-+	PR tree-optimization/63841
-+	* g++.dg/tree-ssa/pr63841.C: New test.
-+
-+2014-11-12  Jakub Jelinek  <jakub@redhat.com>
-+
-+	PR ipa/63838
-+	* g++.dg/ipa/pr63838.C: New test.
-+
-+2014-11-11  Paolo Carlini  <paolo.carlini@oracle.com>
-+
-+	PR c++/63265
-+	* g++.dg/cpp0x/constexpr-63265.C: New.
-+
-+2014-11-09  H.J. Lu  <hongjiu.lu@intel.com>
-+
-+	Backported from mainline
-+	2014-11-09  H.J. Lu  <hongjiu.lu@intel.com>
-+
-+	PR testsuite/63305
-+	* gcc.target/i386/avx256-unaligned-load-7.c (avx_test): Fix
-+	buffer overflow.
-+	* gcc.target/i386/avx256-unaligned-store-7.c (avx_test): Likewise.
-+
-+2014-11-07  Marek Polacek  <polacek@redhat.com>
-+
-+	* c-c++-common/ubsan/undefined-2.c: New test.
-+
-+2014-11-05  Uros Bizjak  <ubizjak@gmail.com>
-+
-+	PR target/63538
-+	* gcc.target/i386/pr63538.c: New test.
-+
-+2014-11-03  Marek Polacek  <polacek@redhat.com>
-+
-+	PR c/52769
-+	* gcc.dg/pr52769.c: New test.
-+
-+2014-10-31  DJ Delorie  <dj@redhat.com>
-+
-+	* gcc.dg/20141029-1.c: New.
-+
-+2014-10-31  Jakub Jelinek  <jakub@redhat.com>
-+
-+	PR sanitizer/63697
-+	* c-c++-common/ubsan/overflow-sub-3.c: New test.
-+
-+2014-10-30  Georg-Johann Lay  <avr@gjlay.de>
-+
-+	PR63633
-+	* gcc.target/avr/torture/pr63633-ice-mult.c: New test.
-+
- 2014-10-30  Release Manager
- 
- 	* GCC 4.9.2 released.
-Index: gcc/testsuite/g++.dg/pr54442.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/pr54442.C	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/g++.dg/pr54442.C	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,12 @@
-+/* { dg-do compile } */
-+
-+struct S
-+{
-+  void s (int) const throw ();
-+  void s (int) throw ();
-+};
-+
-+typedef int index_t;
-+
-+void (S::*f) (index_t)       = &S::s;
-+void (S::*g) (index_t) const = &S::s;
-Index: gcc/testsuite/g++.dg/tsan/atomic_free2.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/tsan/atomic_free2.C	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/g++.dg/tsan/atomic_free2.C	(.../branches/gcc-4_9-branch)
-@@ -1,19 +1,24 @@
- /* { dg-shouldfail "tsan" } */
-+/* { dg-additional-options "-ldl" } */
- 
- #include <pthread.h>
--#include <unistd.h>
-+#include "tsan_barrier.h"
- 
-+static pthread_barrier_t barrier;
-+
- void *Thread(void *a) {
--  sleep(1);
-+  barrier_wait(&barrier);
-   __atomic_fetch_add((int*)a, 1, __ATOMIC_SEQ_CST);
-   return 0;
- }
- 
- int main() {
-+  barrier_init(&barrier, 2);
-   int *a = new int(0);
-   pthread_t t;
-   pthread_create(&t, 0, Thread, a);
-   delete a;
-+  barrier_wait(&barrier);
-   pthread_join(t, 0);
- }
- 
-Index: gcc/testsuite/g++.dg/tsan/tsan_barrier.h
-===================================================================
---- a/src/gcc/testsuite/g++.dg/tsan/tsan_barrier.h	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/g++.dg/tsan/tsan_barrier.h	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,14 @@
-+/* TSAN-invisible barriers.  Link with -ldl.  */
-+#include <pthread.h>
-+#include <dlfcn.h>
-+
-+static __typeof(pthread_barrier_wait) *barrier_wait;
-+
-+static
-+void barrier_init (pthread_barrier_t *barrier, unsigned count)
-+{
-+  void *h = dlopen ("libpthread.so.0", RTLD_LAZY);
-+  barrier_wait = (__typeof (pthread_barrier_wait) *)
-+	 	 dlsym (h, "pthread_barrier_wait");
-+  pthread_barrier_init (barrier, NULL, count);
-+}
-Index: gcc/testsuite/g++.dg/tsan/atomic_free.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/tsan/atomic_free.C	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/g++.dg/tsan/atomic_free.C	(.../branches/gcc-4_9-branch)
-@@ -1,18 +1,23 @@
- /* { dg-shouldfail "tsan" } */
-+/* { dg-additional-options "-ldl" } */
- 
- #include <pthread.h>
--#include <unistd.h>
-+#include "tsan_barrier.h"
- 
-+static pthread_barrier_t barrier;
-+
- void *Thread(void *a) {
-   __atomic_fetch_add((int*)a, 1, __ATOMIC_SEQ_CST);
-+  barrier_wait(&barrier);
-   return 0;
- }
- 
- int main() {
-+  barrier_init(&barrier, 2);
-   int *a = new int(0);
-   pthread_t t;
-   pthread_create(&t, 0, Thread, a);
--  sleep(1);
-+  barrier_wait(&barrier);
-   delete a;
-   pthread_join(t, 0);
- }
-Index: gcc/testsuite/g++.dg/tsan/cond_race.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/tsan/cond_race.C	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/g++.dg/tsan/cond_race.C	(.../branches/gcc-4_9-branch)
-@@ -1,11 +1,13 @@
- /* { dg-shouldfail "tsan" } */
-+/* { dg-additional-options "-ldl" } */
- /* { dg-output "ThreadSanitizer: data race.*" } */
- /* { dg-output "pthread_cond_signal.*" } */
- 
--#include <stdio.h>
--#include <stdlib.h>
- #include <pthread.h>
-+#include "tsan_barrier.h"
- 
-+static pthread_barrier_t barrier;
-+
- struct Ctx {
-   pthread_mutex_t m;
-   pthread_cond_t c;
-@@ -18,10 +20,12 @@
-   c->done = true;
-   pthread_mutex_unlock(&c->m);
-   pthread_cond_signal(&c->c);
-+  barrier_wait(&barrier);
-   return 0;
- }
- 
- int main() {
-+  barrier_init(&barrier, 2);
-   Ctx *c = new Ctx();
-   pthread_mutex_init(&c->m, 0);
-   pthread_cond_init(&c->c, 0);
-@@ -31,6 +35,7 @@
-   while (!c->done)
-     pthread_cond_wait(&c->c, &c->m);
-   pthread_mutex_unlock(&c->m);
-+  barrier_wait(&barrier);
-   delete c;
-   pthread_join(th, 0);
- }
-Index: gcc/testsuite/g++.dg/pr64037.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/pr64037.C	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/g++.dg/pr64037.C	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,27 @@
-+// { dg-do run { target i?86-*-* x86_64-*-* } }
-+// { dg-options "-std=c++11 -Os" }
-+
-+enum class X : unsigned char {
-+  V = 2,
-+};
-+
-+static void
-+__attribute__((noinline,noclone))
-+foo(unsigned &out, unsigned a, X b)
-+{
-+  out = static_cast<unsigned>(b);
-+}
-+
-+int main()
-+{
-+  unsigned deadbeef = 0xDEADBEEF;
-+  asm volatile ("" : "+d" (deadbeef), "+c" (deadbeef));
-+
-+  unsigned out;
-+  foo(out, 2, X::V);
-+
-+  if (out != 2)
-+    __builtin_abort ();
-+
-+  return 0;
-+}
-Index: gcc/testsuite/g++.dg/ubsan/pr63913.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/ubsan/pr63913.C	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/g++.dg/ubsan/pr63913.C	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,12 @@
-+// PR sanitizer/63913
-+// { dg-do compile }
-+// { dg-options "-fsanitize=bool -fnon-call-exceptions" }
-+
-+struct B { B (); ~B (); };
-+
-+double
-+foo (bool *x)
-+{
-+  B b;
-+  return *x;
-+}
-Index: gcc/testsuite/g++.dg/tree-ssa/pr63841.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/tree-ssa/pr63841.C	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/g++.dg/tree-ssa/pr63841.C	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,35 @@
-+/* { dg-do run } */
-+/* { dg-options "-O2" } */
-+
-+#include <string>
-+
-+std::string __attribute__ ((noinline)) comp_test_write() {
-+  std::string data;
-+
-+  for (int i = 0; i < 2; ++i) {
-+    char b = 1 >> (i * 8);
-+    data.append(&b, 1);
-+  }
-+
-+  return data;
-+}
-+
-+std::string __attribute__ ((noinline)) comp_test_write_good() {
-+  std::string data;
-+
-+  char b;
-+  for (int i = 0; i < 2; ++i) {
-+    b = 1 >> (i * 8);
-+    data.append(&b, 1);
-+  }
-+
-+  return data;
-+}
-+
-+int main() {
-+  std::string good = comp_test_write_good();
-+  std::string bad = comp_test_write();
-+
-+  if (good != bad)
-+    __builtin_abort ();
-+}
-Index: gcc/testsuite/g++.dg/warn/Wunused-var-22.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/warn/Wunused-var-22.C	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/g++.dg/warn/Wunused-var-22.C	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,12 @@
-+// PR c++/63657
-+// { dg-options "-Wunused-variable" }
-+
-+class Bar
-+{
-+  virtual ~Bar() {}
-+};
-+Bar& getbar();
-+void bar()
-+{
-+  Bar& b = getbar();		// { dg-warning "unused" }
-+}
-Index: gcc/testsuite/g++.dg/warn/register-parm-1.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/warn/register-parm-1.C	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/g++.dg/warn/register-parm-1.C	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,9 @@
-+// PR c++/60955
-+// { dg-options "-Wextra" }
-+
-+unsigned int erroneous_warning(register int a) {
-+    if ((a) & 0xff) return 1; else return 0;
-+}
-+unsigned int no_erroneous_warning(register int a) {
-+    if (a & 0xff) return 1; else return 0;
-+}
-Index: gcc/testsuite/g++.dg/cpp0x/ref-qual16.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/cpp0x/ref-qual16.C	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/g++.dg/cpp0x/ref-qual16.C	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,12 @@
-+// PR c++/64297
-+// { dg-do compile { target c++11 } }
-+
-+struct A {
-+  typedef int X;
-+  template <int> X m_fn1() const;
-+};
-+template <typename> struct is_function {};
-+is_function<int() const &> i;
-+struct D {
-+  template <typename Y, typename = is_function<Y>> D(Y);
-+} b(&A::m_fn1<0>);
-Index: gcc/testsuite/g++.dg/cpp0x/initlist89.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/cpp0x/initlist89.C	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/g++.dg/cpp0x/initlist89.C	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,4 @@
-+// PR c++/64029
-+// { dg-do compile { target c++11 } }
-+
-+const int (&in)[]{1,2,3,4,5};
-Index: gcc/testsuite/g++.dg/cpp0x/constexpr-63265.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/cpp0x/constexpr-63265.C	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/g++.dg/cpp0x/constexpr-63265.C	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,19 @@
-+// PR c++/63265
-+// { dg-do compile { target c++11 } }
-+
-+#define LSHIFT (sizeof(unsigned int) * __CHAR_BIT__)
-+
-+template <int lshift>
-+struct SpuriouslyWarns1 {
-+    static constexpr unsigned int v = lshift < LSHIFT ? 1U << lshift : 0;
-+};
-+
-+static_assert(SpuriouslyWarns1<LSHIFT>::v == 0, "Impossible occurred");
-+
-+template <int lshift>
-+struct SpuriouslyWarns2 {
-+    static constexpr bool okay = lshift < LSHIFT;
-+    static constexpr unsigned int v = okay ? 1U << lshift : 0;
-+};
-+
-+static_assert(SpuriouslyWarns2<LSHIFT>::v == 0, "Impossible occurred");
-Index: gcc/testsuite/g++.dg/cpp0x/alias-decl-44.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/cpp0x/alias-decl-44.C	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/g++.dg/cpp0x/alias-decl-44.C	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,43 @@
-+// PR c++/63849
-+// { dg-do compile { target c++11 } }
-+
-+template <class _T, class...>
-+using First = _T;            // we should not use this
-+                             // alias with only
-+                             // one pack parameter (?)
-+
-+template <template <class...> class _Successor,
-+          int,
-+          class... _Xs>
-+struct Overlay
-+{
-+    using O = _Successor<_Xs...>;
-+};
-+
-+template <class... _Pack>
-+struct List
-+{
-+    template <int _s>
-+    using O = typename Overlay<List, _s, _Pack...>::O;
-+
-+    template <template <class...> class _S>
-+    using Pass = _S<_Pack...>;
-+
-+    template <int _i>
-+    using At = typename O<_i>
-+    ::template Pass<First>;
-+};
-+
-+template <int _i>
-+using At = typename List<int, char>
-+::template At<_i>;
-+
-+template <int _i>
-+void func_crash(At<_i>&) {}
-+
-+int main(int argc, char *argv[])
-+{
-+    char ccc;
-+    int iii;
-+    func_crash<0>(iii);
-+}
-Index: gcc/testsuite/g++.dg/cpp0x/deleted9.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/cpp0x/deleted9.C	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/g++.dg/cpp0x/deleted9.C	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,31 @@
-+// PR c++/64352
-+// { dg-do compile { target c++11 } }
-+
-+template<bool B> struct bool_type
-+{ static constexpr bool value = B; };
-+
-+using true_type = bool_type<true>;
-+using false_type = bool_type<false>;
-+
-+template<typename T> T&& declval();
-+
-+template<typename...> struct void_ { using type = void; };
-+template<typename... I> using void_t = typename void_<I...>::type;
-+
-+template<typename _Tp, typename = void>
-+struct _Has_addressof_free: false_type { };
-+
-+template<typename _Tp>
-+struct _Has_addressof_free
-+<_Tp, void_t<decltype( operator&(declval<const _Tp&>()) )>>
-+: true_type { };
-+
-+struct foo {};
-+void operator&(foo) = delete;
-+
-+int main()
-+{
-+    static_assert( !_Has_addressof_free<int>::value, "" );
-+    // error: use of deleted function 'void operator&(foo)'
-+    static_assert( !_Has_addressof_free<foo>::value, "" );
-+}
-Index: gcc/testsuite/g++.dg/ipa/pr63838.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/ipa/pr63838.C	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/g++.dg/ipa/pr63838.C	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,56 @@
-+// PR ipa/63838
-+// { dg-do run }
-+// { dg-options "-O2 -fdump-ipa-pure-const" }
-+// { dg-final { scan-ipa-dump-not "Function found to be nothrow: void foo" "pure-const" } }
-+// { dg-final { scan-ipa-dump-not "Function found to be nothrow: void bar" "pure-const" } }
-+// { dg-final { cleanup-ipa-dump "pure-const" } }
-+
-+__attribute__((noinline, noclone)) static void bar (int);
-+volatile int v;
-+void (*fn) ();
-+struct S { S () { v++; } ~S () { v++; } };
-+
-+__attribute__((noinline, noclone)) static void
-+foo (int x)
-+{
-+  v++;
-+  if (x == 5)
-+    bar (x);
-+}
-+
-+__attribute__((noinline, noclone)) static void
-+bar (int x)
-+{
-+  v++;
-+  if (x == 6)
-+    foo (x);
-+  else if (x == 5)
-+    fn ();
-+}
-+
-+__attribute__((noinline, noclone)) int
-+baz (int x)
-+{
-+  S s;
-+  foo (x);
-+}
-+
-+void
-+throw0 ()
-+{
-+  throw 0;
-+}
-+
-+int
-+main ()
-+{
-+  fn = throw0;
-+  asm volatile ("" : : : "memory");
-+  try
-+    {
-+      baz (5);
-+    }
-+  catch (int)
-+    {
-+    }
-+}
-Index: gcc/testsuite/g++.dg/template/offsetof3.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/template/offsetof3.C	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/g++.dg/template/offsetof3.C	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,18 @@
-+// PR c++/64487
-+
-+struct foo {
-+      int member;
-+};
-+
-+template < int N>
-+struct bar {};
-+
-+template <int N>
-+struct qux {
-+        static bar<N+__builtin_offsetof(foo,member)> static_member;
-+};
-+
-+template <int N>
-+bar<N+__builtin_offsetof(foo,member)> qux<N>::static_member;
-+
-+int main() { }
-Index: gcc/testsuite/g++.dg/template/ref9.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/template/ref9.C	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/g++.dg/template/ref9.C	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,15 @@
-+// PR c++/63658
-+
-+struct Descriptor {};
-+
-+template <Descriptor & D>
-+struct foo
-+{
-+  void size ();
-+};
-+
-+Descriptor g_descriptor = {};
-+
-+template<> void foo<g_descriptor>::size()
-+{
-+}
-Index: gcc/testsuite/g++.dg/template/non-dependent14.C
-===================================================================
---- a/src/gcc/testsuite/g++.dg/template/non-dependent14.C	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/g++.dg/template/non-dependent14.C	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,7 @@
-+// PR c++/64251
-+
-+class DictionaryValue {};
-+template <typename T> void CreateValue(T) {
-+  DictionaryValue(0);
-+  CreateValue(0);
-+}
-Index: gcc/testsuite/c-c++-common/tsan/mutexset1.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/tsan/mutexset1.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/tsan/mutexset1.c	(.../branches/gcc-4_9-branch)
-@@ -1,14 +1,15 @@
- /* { dg-shouldfail "tsan" } */
-+/* { dg-additional-options "-ldl" } */
- 
- #include <pthread.h>
--#include <stdio.h>
--#include <unistd.h>
-+#include "tsan_barrier.h"
- 
-+static pthread_barrier_t barrier;
- int Global;
- pthread_mutex_t mtx;
- 
- void *Thread1(void *x) {
--  sleep(1);
-+  barrier_wait(&barrier);
-   pthread_mutex_lock(&mtx);
-   Global++;
-   pthread_mutex_unlock(&mtx);
-@@ -17,11 +18,13 @@
- 
- void *Thread2(void *x) {
-   Global--;
-+  barrier_wait(&barrier);
-   return NULL;/* { dg-output ".*" } */
- 
- }
- 
- int main() {
-+  barrier_init(&barrier, 2);
-   pthread_mutex_init(&mtx, 0);
-   pthread_t t[2];
-   pthread_create(&t[0], NULL, Thread1, NULL);
-Index: gcc/testsuite/c-c++-common/tsan/fd_pipe_race.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/tsan/fd_pipe_race.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/tsan/fd_pipe_race.c	(.../branches/gcc-4_9-branch)
-@@ -1,18 +1,21 @@
- /* { dg-shouldfail "tsan" } */
-+/* { dg-additional-options "-ldl" } */
- 
- #include <pthread.h>
--#include <stdio.h>
- #include <unistd.h>
-+#include "tsan_barrier.h"
- 
-+static pthread_barrier_t barrier;
- int fds[2];
- 
- void *Thread1(void *x) {
-   write(fds[1], "a", 1);
-+  barrier_wait(&barrier);
-   return NULL;
- }
- 
- void *Thread2(void *x) {
--  sleep(1);
-+  barrier_wait(&barrier);
-   close(fds[0]);
-   close(fds[1]);
-   return NULL;
-@@ -19,6 +22,7 @@
- }
- 
- int main() {
-+  barrier_init(&barrier, 2);
-   pipe(fds);
-   pthread_t t[2];
-   pthread_create(&t[0], NULL, Thread1, NULL);
-@@ -25,6 +29,7 @@
-   pthread_create(&t[1], NULL, Thread2, NULL);
-   pthread_join(t[0], NULL);
-   pthread_join(t[1], NULL);
-+  return 0;
- }
- 
- /* { dg-output "WARNING: ThreadSanitizer: data race.*\n" } */
-Index: gcc/testsuite/c-c++-common/tsan/atomic_stack.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/tsan/atomic_stack.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/tsan/atomic_stack.c	(.../branches/gcc-4_9-branch)
-@@ -1,12 +1,14 @@
- /* { dg-shouldfail "tsan" } */
-+/* { dg-additional-options "-ldl" } */
- 
- #include <pthread.h>
--#include <unistd.h>
-+#include "tsan_barrier.h"
- 
-+static pthread_barrier_t barrier;
- int Global;
- 
- void *Thread1(void *x) {
--  sleep(1);
-+  barrier_wait(&barrier);
-   __atomic_fetch_add(&Global, 1, __ATOMIC_RELAXED);
-   return NULL;
- }
-@@ -13,10 +15,12 @@
- 
- void *Thread2(void *x) {
-   Global++;
-+  barrier_wait(&barrier);
-   return NULL;
- }
- 
- int main() {
-+  barrier_init(&barrier, 2);
-   pthread_t t[2];
-   pthread_create(&t[0], NULL, Thread1, NULL);
-   pthread_create(&t[1], NULL, Thread2, NULL);
-Index: gcc/testsuite/c-c++-common/tsan/sleep_sync.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/tsan/sleep_sync.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/tsan/sleep_sync.c	(.../branches/gcc-4_9-branch)
-@@ -1,8 +1,11 @@
- /* { dg-shouldfail "tsan" } */
-+/* { dg-additional-options "-ldl" } */
- 
- #include <pthread.h>
- #include <unistd.h>
-+#include "tsan_barrier.h"
- 
-+static pthread_barrier_t barrier;
- int X = 0;
- 
- void MySleep() {
-@@ -10,6 +13,7 @@
- }
- 
- void *Thread(void *p) {
-+  barrier_wait(&barrier);
-   MySleep();  // Assume the main thread has done the write.
-   X = 42;
-   return 0;
-@@ -16,9 +20,11 @@
- }
- 
- int main() {
-+  barrier_init(&barrier, 2);
-   pthread_t t;
-   pthread_create(&t, 0, Thread, 0);
-   X = 43;
-+  barrier_wait(&barrier);
-   pthread_join(t, 0);
-   return 0;
- }
-Index: gcc/testsuite/c-c++-common/tsan/write_in_reader_lock.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/tsan/write_in_reader_lock.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/tsan/write_in_reader_lock.c	(.../branches/gcc-4_9-branch)
-@@ -1,8 +1,10 @@
- /* { dg-shouldfail "tsan" } */
-+/* { dg-additional-options "-ldl" } */
- 
- #include <pthread.h>
--#include <unistd.h>
-+#include "tsan_barrier.h"
- 
-+static pthread_barrier_t barrier;
- pthread_rwlock_t rwlock;
- int GLOB;
- 
-@@ -10,7 +12,7 @@
-  (void)p;
-   pthread_rwlock_rdlock(&rwlock);
-   // Write under reader lock.
--  sleep(1);
-+  barrier_wait(&barrier);
-   GLOB++;
-   pthread_rwlock_unlock(&rwlock);
-   return 0;
-@@ -17,6 +19,7 @@
- }
- 
- int main(int argc, char *argv[]) {
-+  barrier_init(&barrier, 2);
-   pthread_rwlock_init(&rwlock, NULL);
-   pthread_rwlock_rdlock(&rwlock);
-   pthread_t t;
-@@ -24,6 +27,7 @@
-   volatile int x = GLOB;
-  (void)x;
-   pthread_rwlock_unlock(&rwlock);
-+  barrier_wait(&barrier);
-   pthread_join(t, 0);
-   pthread_rwlock_destroy(&rwlock);
-   return 0;
-Index: gcc/testsuite/c-c++-common/tsan/race_on_mutex2.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/tsan/race_on_mutex2.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/tsan/race_on_mutex2.c	(.../branches/gcc-4_9-branch)
-@@ -1,22 +1,25 @@
- /* { dg-shouldfail "tsan" } */
-+/* { dg-additional-options "-ldl" } */
- 
- #include <pthread.h>
--#include <stdio.h>
--#include <stddef.h>
--#include <unistd.h>
-+#include "tsan_barrier.h"
- 
-+static pthread_barrier_t barrier;
-+
- void *Thread(void *x) {
-   pthread_mutex_lock((pthread_mutex_t*)x);
-   pthread_mutex_unlock((pthread_mutex_t*)x);
-+  barrier_wait(&barrier);
-   return 0;
- }
- 
- int main() {
-+  barrier_init(&barrier, 2);
-   pthread_mutex_t Mtx;
-   pthread_mutex_init(&Mtx, 0);
-   pthread_t t;
-   pthread_create(&t, 0, Thread, &Mtx);
--  sleep(1);
-+  barrier_wait(&barrier);
-   pthread_mutex_destroy(&Mtx);
-   pthread_join(t, 0);
-   return 0;
-Index: gcc/testsuite/c-c++-common/tsan/race_on_barrier.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/tsan/race_on_barrier.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/tsan/race_on_barrier.c	(.../branches/gcc-4_9-branch)
-@@ -1,26 +1,28 @@
- /* { dg-shouldfail "tsan" } */
-+/* { dg-additional-options "-ldl" } */
- 
- #include <pthread.h>
--#include <stdio.h>
--#include <stddef.h>
--#include <unistd.h>
-+#include "tsan_barrier.h"
- 
-+static pthread_barrier_t barrier;
- pthread_barrier_t B;
- int Global;
- 
- void *Thread1(void *x) {
-   pthread_barrier_init(&B, 0, 2);
-+  barrier_wait(&barrier);
-   pthread_barrier_wait(&B);
-   return NULL;
- }
- 
- void *Thread2(void *x) {
--  sleep(1);
-+  barrier_wait(&barrier);
-   pthread_barrier_wait(&B);
-   return NULL;
- }
- 
- int main() {
-+  barrier_init(&barrier, 2);
-   pthread_t t;
-   pthread_create(&t, NULL, Thread1, NULL);
-   Thread2(0);
-Index: gcc/testsuite/c-c++-common/tsan/tiny_race.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/tsan/tiny_race.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/tsan/tiny_race.c	(.../branches/gcc-4_9-branch)
-@@ -1,20 +1,24 @@
- /* { dg-shouldfail "tsan" } */
-+/* { dg-additional-options "-ldl" } */
- 
- #include <pthread.h>
--#include <unistd.h>
-+#include "tsan_barrier.h"
- 
-+static pthread_barrier_t barrier;
- int Global;
- 
- void *Thread1(void *x) {
--  sleep(1);
-+  barrier_wait(&barrier);
-   Global = 42;
-   return x;
- }
- 
- int main() {
-+  barrier_init(&barrier, 2);
-   pthread_t t;
-   pthread_create(&t, 0, Thread1, 0);
-   Global = 43;
-+  barrier_wait(&barrier);
-   pthread_join(t, 0);
-   return Global;
- }
-Index: gcc/testsuite/c-c++-common/tsan/simple_stack.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/tsan/simple_stack.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/tsan/simple_stack.c	(.../branches/gcc-4_9-branch)
-@@ -1,9 +1,10 @@
- /* { dg-shouldfail "tsan" } */
-+/* { dg-additional-options "-ldl" } */
- 
- #include <pthread.h>
--#include <stdio.h>
--#include <unistd.h>
-+#include "tsan_barrier.h"
- 
-+static pthread_barrier_t barrier;
- int Global;
- 
- void __attribute__((noinline)) foo1() {
-@@ -25,7 +26,7 @@
- }
- 
- void *Thread1(void *x) {
--  sleep(1);
-+  barrier_wait(&barrier);
-   bar1();
-   return NULL;
- }
-@@ -32,6 +33,7 @@
- 
- void *Thread2(void *x) {
-   bar2();
-+  barrier_wait(&barrier);
-   return NULL;
- }
- 
-@@ -40,6 +42,7 @@
- }
- 
- int main() {
-+  barrier_init(&barrier, 2);
-   pthread_t t[2];
-   StartThread(&t[0], Thread1);
-   StartThread(&t[1], Thread2);
-@@ -50,16 +53,16 @@
- 
- /* { dg-output "WARNING: ThreadSanitizer: data race.*" } */
- /* { dg-output "  Write of size 4 at .* by thread T1:(\n|\r\n|\r)" } */
--/* { dg-output "    #0 foo1.* .*(simple_stack.c:10|\\?{2}:0) (.*)" } */
--/* { dg-output "    #1 bar1.* .*(simple_stack.c:15|\\?{2}:0) (.*)" } */
--/* { dg-output "    #2 Thread1.* .*(simple_stack.c:29|\\?{2}:0) (.*)" } */
-+/* { dg-output "    #0 foo1.* .*(simple_stack.c:11|\\?{2}:0) (.*)" } */
-+/* { dg-output "    #1 bar1.* .*(simple_stack.c:16|\\?{2}:0) (.*)" } */
-+/* { dg-output "    #2 Thread1.* .*(simple_stack.c:30|\\?{2}:0) (.*)" } */
- /* { dg-output "  Previous read of size 4 at .* by thread T2:(\n|\r\n|\r)" } */
--/* { dg-output "    #0 foo2.* .*(simple_stack.c:19|\\?{2}:0) (.*)" } */
--/* { dg-output "    #1 bar2.* .*(simple_stack.c:24|\\?{2}:0) (.*)" } */
--/* { dg-output "    #2 Thread2.* .*(simple_stack.c:34|\\?{2}:0) (.*)" } */
-+/* { dg-output "    #0 foo2.* .*(simple_stack.c:20|\\?{2}:0) (.*)" } */
-+/* { dg-output "    #1 bar2.* .*(simple_stack.c:25|\\?{2}:0) (.*)" } */
-+/* { dg-output "    #2 Thread2.* .*(simple_stack.c:35|\\?{2}:0) (.*)" } */
- /* { dg-output "  Thread T1 \\(tid=.*, running\\) created by main thread at:(\n|\r\n|\r)" } */
- /* { dg-output "    #0 pthread_create .* (.*)" } */
--/* { dg-output "    #1 StartThread.* .*(simple_stack.c:39|\\?{2}:0) (.*)" } */
-+/* { dg-output "    #1 StartThread.* .*(simple_stack.c:41|\\?{2}:0) (.*)" } */
- /* { dg-output "  Thread T2 (.*) created by main thread at:(\n|\r\n|\r)" } */
- /* { dg-output "    #0 pthread_create .* (.*)" } */
--/* { dg-output "    #1 StartThread.* .*(simple_stack.c:39|\\?{2}:0) (.*)" } */
-+/* { dg-output "    #1 StartThread.* .*(simple_stack.c:41|\\?{2}:0) (.*)" } */
-Index: gcc/testsuite/c-c++-common/tsan/tsan_barrier.h
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/tsan/tsan_barrier.h	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/tsan/tsan_barrier.h	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,14 @@
-+/* TSAN-invisible barriers.  Link with -ldl.  */
-+#include <pthread.h>
-+#include <dlfcn.h>
-+
-+static __typeof(pthread_barrier_wait) *barrier_wait;
-+
-+static
-+void barrier_init (pthread_barrier_t *barrier, unsigned count)
-+{
-+  void *h = dlopen ("libpthread.so.0", RTLD_LAZY);
-+  barrier_wait = (__typeof (pthread_barrier_wait) *)
-+	 	 dlsym (h, "pthread_barrier_wait");
-+  pthread_barrier_init (barrier, NULL, count);
-+}
-Index: gcc/testsuite/c-c++-common/tsan/simple_race.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/tsan/simple_race.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/tsan/simple_race.c	(.../branches/gcc-4_9-branch)
-@@ -1,13 +1,15 @@
- /* { dg-set-target-env-var TSAN_OPTIONS "halt_on_error=1" } */
- /* { dg-shouldfail "tsan" } */
-+/* { dg-additional-options "-ldl" } */
- 
- #include <pthread.h>
--#include <stdio.h>
- #include <unistd.h>
-+#include "tsan_barrier.h"
- 
--#define MAX_ITERATIONS_NUMBER 100
--#define SLEEP_STEP 128000 
-+#define MAX_ITERATIONS_NUMBER 1
-+#define SLEEP_STEP 128000
- 
-+static pthread_barrier_t barrier;
- unsigned int delay_time = 1000;
- 
- static inline void delay () {
-@@ -17,6 +19,7 @@
- extern int main_1();
- 
- int main() {
-+  barrier_init(&barrier, 2);
-   int i;
-   for (i = 0; i < MAX_ITERATIONS_NUMBER; i++) {
-     main_1();
-@@ -28,6 +31,7 @@
- int Global;
- 
- void *Thread1(void *x) {
-+  barrier_wait(&barrier);
-   delay();
-   Global = 42;
-   return NULL;
-@@ -35,6 +39,7 @@
- 
- void *Thread2(void *x) {
-   Global = 43;
-+  barrier_wait(&barrier);
-   return NULL;
- }
- 
-Index: gcc/testsuite/c-c++-common/tsan/race_on_mutex.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/tsan/race_on_mutex.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/tsan/race_on_mutex.c	(.../branches/gcc-4_9-branch)
-@@ -1,10 +1,10 @@
- /* { dg-shouldfail "tsan" } */
-+/* { dg-additional-options "-ldl" } */
- 
- #include <pthread.h>
--#include <stdio.h>
--#include <stddef.h>
--#include <unistd.h>
-+#include "tsan_barrier.h"
- 
-+static pthread_barrier_t barrier;
- pthread_mutex_t Mtx;
- int Global;
- 
-@@ -13,11 +13,12 @@
-   pthread_mutex_lock(&Mtx);
-   Global = 42;
-   pthread_mutex_unlock(&Mtx);
-+  barrier_wait(&barrier);
-   return NULL;
- }
- 
- void *Thread2(void *x) {
--  sleep(1);
-+  barrier_wait(&barrier);
-   pthread_mutex_lock(&Mtx);
-   Global = 43;
-   pthread_mutex_unlock(&Mtx);
-@@ -25,6 +26,7 @@
- }
- 
- int main() {
-+  barrier_init(&barrier, 2);
-   pthread_t t[2];
-   pthread_create(&t[0], NULL, Thread1, NULL);
-   pthread_create(&t[1], NULL, Thread2, NULL);
-@@ -37,7 +39,7 @@
- /* { dg-output "WARNING: ThreadSanitizer: data race.*(\n|\r\n|\r)" } */
- /* { dg-output "  Atomic read of size 1 at .* by thread T2:(\n|\r\n|\r)" } */
- /* { dg-output "    #0 pthread_mutex_lock.*" } */
--/* { dg-output "    #1 Thread2.* .*(race_on_mutex.c:21|\\?{2}:0) (.*)" } */
-+/* { dg-output "    #1 Thread2.* .*(race_on_mutex.c:22|\\?{2}:0) (.*)" } */
- /* { dg-output "  Previous write of size 1 at .* by thread T1:(\n|\r\n|\r)" } */
- /* { dg-output "    #0 pthread_mutex_init .* (.)*" } */
- /* { dg-output "    #1 Thread1.* .*(race_on_mutex.c:12|\\?{2}:0) .*" } */
-Index: gcc/testsuite/c-c++-common/tsan/tls_race.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/tsan/tls_race.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/tsan/tls_race.c	(.../branches/gcc-4_9-branch)
-@@ -1,18 +1,24 @@
- /* { dg-shouldfail "tsan" } */
-+/* { dg-additional-options "-ldl" } */
- 
- #include <pthread.h>
--#include <stddef.h>
-+#include "tsan_barrier.h"
- 
-+static pthread_barrier_t barrier;
-+
- void *Thread(void *a) {
-+  barrier_wait(&barrier);
-   *(int*)a = 43;
-   return 0;
- }
- 
- int main() {
-+  barrier_init(&barrier, 2);
-   static __thread int Var = 42;
-   pthread_t t;
-   pthread_create(&t, 0, Thread, &Var);
-   Var = 43;
-+  barrier_wait(&barrier);
-   pthread_join(t, 0);
- }
- 
-Index: gcc/testsuite/c-c++-common/ubsan/overflow-sub-3.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/ubsan/overflow-sub-3.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/ubsan/overflow-sub-3.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,34 @@
-+/* { dg-do run } */
-+/* { dg-options "-fsanitize=signed-integer-overflow" } */
-+
-+__attribute__((noinline, noclone)) int
-+foo1 (int x, int y)
-+{
-+  return x - y;
-+}
-+
-+__attribute__((noinline, noclone)) int
-+foo2 (int x, int y)
-+{
-+  unsigned int xa = (unsigned int) x - (__INT_MAX__ - 3);
-+  xa &= 3;
-+  x = __INT_MAX__ - 3 + xa;
-+  unsigned int ya = y + 1U;
-+  ya &= 1;
-+  y = ya - 1;
-+  return x - y;
-+}
-+
-+int
-+main ()
-+{
-+  int xm1, y;
-+  for (xm1 = __INT_MAX__ - 4; xm1 < __INT_MAX__; xm1++)
-+    for (y = -1; y <= 0; y++)
-+      if (foo1 (xm1 + 1, y) != (int) (xm1 + 1U - y)
-+	  || foo2 (xm1 + 1, y) != (int) (xm1 + 1U - y))
-+	__builtin_abort ();
-+  return 0;
-+}
-+/* { dg-output ":7:\[0-9]\[^\n\r]*signed integer overflow: 2147483647 - -1 cannot be represented in type 'int'\[^\n\r]*(\n|\r\n|\r)" } */
-+/* { dg-output "\[^\n\r]*:19:\[0-9]\[^\n\r]*signed integer overflow: 2147483647 - -1 cannot be represented in type 'int'" } */
-Index: gcc/testsuite/c-c++-common/ubsan/undefined-2.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/ubsan/undefined-2.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/ubsan/undefined-2.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,26 @@
-+/* { dg-do run } */
-+/* { dg-options "-fsanitize=undefined" } */
-+/* { dg-additional-options "-std=gnu11" { target c } } */
-+/* { dg-additional-options "-std=c++11" { target c++ } } */
-+
-+#include <stdio.h>
-+
-+volatile int w, z;
-+
-+__attribute__ ((noinline, noclone)) int
-+foo (int x, int y)
-+{
-+  z++;
-+  return x << y;
-+}
-+
-+int
-+main ()
-+{
-+  fputs ("1st\n", stderr);
-+  w = foo (0, -__INT_MAX__);
-+  return 0;
-+}
-+
-+/* { dg-output "1st(\n|\r\n|\r)" } */
-+/* { dg-output "\[^\n\r]*shift exponent -\[^\n\r]* is negative\[^\n\r]*(\n|\r\n|\r)" } */
-Index: gcc/testsuite/c-c++-common/pr56493.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/pr56493.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/pr56493.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,16 @@
-+/* PR c++/56493 */
-+/* { dg-do compile } */
-+/* { dg-options "-O2 -fdump-tree-gimple" } */
-+
-+unsigned long long bar (void);
-+int x;
-+
-+void
-+foo (void)
-+{
-+  x += bar ();
-+}
-+
-+/* Verify we narrow the addition from unsigned long long to unsigned int type.  */
-+/* { dg-final { scan-tree-dump "  (\[a-zA-Z._0-9]*) = \\(unsigned int\\) \[^;\n\r]*;.*  (\[a-zA-Z._0-9]*) = \\(unsigned int\\) \[^;\n\r]*;.* = \\1 \\+ \\2;" "gimple" { target { ilp32 || lp64 } } } } */
-+/* { dg-final { cleanup-tree-dump "gimple" } } */
-Index: gcc/testsuite/c-c++-common/gomp/pr60823-4.c
-===================================================================
---- a/src/gcc/testsuite/c-c++-common/gomp/pr60823-4.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/testsuite/c-c++-common/gomp/pr60823-4.c	(.../branches/gcc-4_9-branch)
-@@ -0,0 +1,7 @@
-+/* PR tree-optimization/63915 */
-+/* { dg-do run } */
-+/* { dg-require-effective-target vect_simd_clones } */
-+/* { dg-options "-O2 -fopenmp-simd" } */
-+/* { dg-additional-options "-fpic" { target fpic } } */
-+
-+#include "pr60823-2.c"
-Index: gcc/cp/typeck.c
-===================================================================
---- a/src/gcc/cp/typeck.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/cp/typeck.c	(.../branches/gcc-4_9-branch)
-@@ -8881,6 +8881,12 @@
-   /* This should really have a different TYPE_MAIN_VARIANT, but that gets
-      complex.  */
-   tree result = build_qualified_type (type, memfn_quals);
-+  if (tree canon = TYPE_CANONICAL (result))
-+    if (canon != result)
-+      /* check_qualified_type doesn't check the ref-qualifier, so make sure
-+	 TYPE_CANONICAL is correct.  */
-+      TYPE_CANONICAL (result)
-+	= build_ref_qualified_type (canon, type_memfn_rqual (result));
-   result = build_exception_variant (result, TYPE_RAISES_EXCEPTIONS (type));
-   return build_ref_qualified_type (result, rqual);
- }
-Index: gcc/cp/decl.c
-===================================================================
---- a/src/gcc/cp/decl.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/cp/decl.c	(.../branches/gcc-4_9-branch)
-@@ -630,8 +630,7 @@
- 	   push_local_binding where the list of decls returned by
- 	   getdecls is built.  */
- 	decl = TREE_CODE (d) == TREE_LIST ? TREE_VALUE (d) : d;
--	// See through references for improved -Wunused-variable (PR 38958).
--	tree type = non_reference (TREE_TYPE (decl));
-+	tree type = TREE_TYPE (decl);
- 	if (VAR_P (decl)
- 	    && (! TREE_USED (decl) || !DECL_READ_P (decl))
- 	    && ! DECL_IN_SYSTEM_HEADER (decl)
-@@ -4792,11 +4791,26 @@
-     init = build_x_compound_expr_from_list (init, ELK_INIT,
- 					    tf_warning_or_error);
- 
--  if (TREE_CODE (TREE_TYPE (type)) != ARRAY_TYPE
-+  tree ttype = TREE_TYPE (type);
-+  if (TREE_CODE (ttype) != ARRAY_TYPE
-       && TREE_CODE (TREE_TYPE (init)) == ARRAY_TYPE)
-     /* Note: default conversion is only called in very special cases.  */
-     init = decay_conversion (init, tf_warning_or_error);
- 
-+  /* check_initializer handles this for non-reference variables, but for
-+     references we need to do it here or the initializer will get the
-+     incomplete array type and confuse later calls to
-+     cp_complete_array_type.  */
-+  if (TREE_CODE (ttype) == ARRAY_TYPE
-+      && TYPE_DOMAIN (ttype) == NULL_TREE
-+      && (BRACE_ENCLOSED_INITIALIZER_P (init)
-+	  || TREE_CODE (init) == STRING_CST))
-+    {
-+      cp_complete_array_type (&ttype, init, false);
-+      if (ttype != TREE_TYPE (type))
-+	type = cp_build_reference_type (ttype, TYPE_REF_IS_RVALUE (type));
-+    }
-+
-   /* Convert INIT to the reference type TYPE.  This may involve the
-      creation of a temporary, whose lifetime must be the same as that
-      of the reference.  If so, a DECL_EXPR for the temporary will be
-Index: gcc/cp/ChangeLog
-===================================================================
---- a/src/gcc/cp/ChangeLog	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/cp/ChangeLog	(.../branches/gcc-4_9-branch)
-@@ -1,3 +1,51 @@
-+2015-01-07  Jason Merrill  <jason@redhat.com>
-+
-+	PR c++/64487
-+	* semantics.c (finish_offsetof): Handle templates here.
-+	* parser.c (cp_parser_builtin_offsetof): Not here.
-+
-+	PR c++/64352
-+	* pt.c (tsubst_copy_and_build): Pass complain to mark_used.
-+
-+	PR c++/64251
-+	* decl2.c (mark_used): Don't mark if in_template_function.
-+
-+	PR c++/64297
-+	* typeck.c (apply_memfn_quals): Correct wrong TYPE_CANONICAL.
-+
-+	PR c++/64029
-+	* decl.c (grok_reference_init): Complete array type.
-+
-+	PR c++/63657
-+	PR c++/38958
-+	* call.c (set_up_extended_ref_temp): Set TREE_USED on the reference
-+	if the temporary has a non-trivial destructor.
-+	* decl.c (poplevel): Don't look through references.
-+
-+	PR c++/63658
-+	* pt.c (convert_nontype_argument): Call convert_from_reference.
-+	(check_instantiated_arg): Don't be confused by reference refs.
-+	(unify): Look through reference refs on the arg, too.
-+	* mangle.c (write_template_arg): Look through reference refs.
-+
-+2014-12-19  Paolo Carlini  <paolo.carlini@oracle.com>
-+
-+	PR c++/60955
-+	* pt.c (struct warning_sentinel): Move it...
-+	* cp-tree.h: ... here.
-+	* semantics.c (force_paren_expr): Use it.
-+
-+2014-11-21  Jason Merrill  <jason@redhat.com>
-+
-+	PR c++/63849
-+	* mangle.c (decl_mangling_context): Use template_type_parameter_p.
-+
-+2014-11-11  Paolo Carlini  <paolo.carlini@oracle.com>
-+
-+	PR c++/63265
-+	* pt.c (tsubst_copy_and_build, case COND_EXPR): Maybe fold to
-+	constant the condition.
-+
- 2014-10-30  Release Manager
- 
- 	* GCC 4.9.2 released.
-Index: gcc/cp/pt.c
-===================================================================
---- a/src/gcc/cp/pt.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/cp/pt.c	(.../branches/gcc-4_9-branch)
-@@ -6084,7 +6084,7 @@
-      right type?  */
-   gcc_assert (same_type_ignoring_top_level_qualifiers_p
- 	      (type, TREE_TYPE (expr)));
--  return expr;
-+  return convert_from_reference (expr);
- }
- 
- /* Subroutine of coerce_template_template_parms, which returns 1 if
-@@ -14151,16 +14151,6 @@
-   return t;
- }
- 
--/* Sentinel to disable certain warnings during template substitution.  */
--
--struct warning_sentinel {
--  int &flag;
--  int val;
--  warning_sentinel(int& flag, bool suppress=true)
--    : flag(flag), val(flag) { if (suppress) flag = 0; }
--  ~warning_sentinel() { flag = val; }
--};
--
- /* Like tsubst but deals with expressions and performs semantic
-    analysis.  FUNCTION_P is true if T is the "F" in "F (ARGS)".  */
- 
-@@ -14828,7 +14818,7 @@
- 
- 	/* Remember that there was a reference to this entity.  */
- 	if (DECL_P (function))
--	  mark_used (function);
-+	  mark_used (function, complain);
- 
- 	/* Put back tf_decltype for the actual call.  */
- 	complain |= decltype_flag;
-@@ -14875,11 +14865,13 @@
-     case COND_EXPR:
-       {
- 	tree cond = RECUR (TREE_OPERAND (t, 0));
-+	tree folded_cond = (maybe_constant_value
-+			    (fold_non_dependent_expr_sfinae (cond, tf_none)));
- 	tree exp1, exp2;
- 
--	if (TREE_CODE (cond) == INTEGER_CST)
-+	if (TREE_CODE (folded_cond) == INTEGER_CST)
- 	  {
--	    if (integer_zerop (cond))
-+	    if (integer_zerop (folded_cond))
- 	      {
- 		++c_inhibit_evaluation_warnings;
- 		exp1 = RECUR (TREE_OPERAND (t, 1));
-@@ -14893,6 +14885,7 @@
- 		exp2 = RECUR (TREE_OPERAND (t, 2));
- 		--c_inhibit_evaluation_warnings;
- 	      }
-+	    cond = folded_cond;
- 	  }
- 	else
- 	  {
-@@ -15443,6 +15436,7 @@
-      constant.  */
-   else if (TREE_TYPE (t)
- 	   && INTEGRAL_OR_ENUMERATION_TYPE_P (TREE_TYPE (t))
-+	   && !REFERENCE_REF_P (t)
- 	   && !TREE_CONSTANT (t))
-     {
-       if (complain & tf_error)
-@@ -18166,8 +18160,12 @@
- 
-     case INDIRECT_REF:
-       if (REFERENCE_REF_P (parm))
--	return unify (tparms, targs, TREE_OPERAND (parm, 0), arg,
--		      strict, explain_p);
-+	{
-+	  if (REFERENCE_REF_P (arg))
-+	    arg = TREE_OPERAND (arg, 0);
-+	  return unify (tparms, targs, TREE_OPERAND (parm, 0), arg,
-+			strict, explain_p);
-+	}
-       /* FALLTHRU */
- 
-     default:
-Index: gcc/cp/semantics.c
-===================================================================
---- a/src/gcc/cp/semantics.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/cp/semantics.c	(.../branches/gcc-4_9-branch)
-@@ -1629,6 +1629,9 @@
- 	  tree type = unlowered_expr_type (expr);
- 	  bool rval = !!(kind & clk_rvalueref);
- 	  type = cp_build_reference_type (type, rval);
-+	  /* This inhibits warnings in, eg, cxx_mark_addressable
-+	     (c++/60955).  */
-+	  warning_sentinel s (extra_warnings);
- 	  expr = build_static_cast (type, expr, tf_error);
- 	  if (expr != error_mark_node)
- 	    REF_PARENTHESIZED_P (expr) = true;
-@@ -3800,6 +3803,14 @@
- tree
- finish_offsetof (tree expr)
- {
-+  /* If we're processing a template, we can't finish the semantics yet.
-+     Otherwise we can fold the entire expression now.  */
-+  if (processing_template_decl)
-+    {
-+      expr = build1 (OFFSETOF_EXPR, size_type_node, expr);
-+      return expr;
-+    }
-+
-   if (TREE_CODE (expr) == PSEUDO_DTOR_EXPR)
-     {
-       error ("cannot apply %<offsetof%> to destructor %<~%T%>",
-Index: gcc/cp/decl2.c
-===================================================================
---- a/src/gcc/cp/decl2.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/cp/decl2.c	(.../branches/gcc-4_9-branch)
-@@ -4914,7 +4914,7 @@
-       --function_depth;
-     }
- 
--  if (processing_template_decl)
-+  if (processing_template_decl || in_template_function ())
-     return true;
- 
-   /* Check this too in case we're within fold_non_dependent_expr.  */
-Index: gcc/cp/parser.c
-===================================================================
---- a/src/gcc/cp/parser.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/cp/parser.c	(.../branches/gcc-4_9-branch)
-@@ -8479,12 +8479,7 @@
-     }
- 
-  success:
--  /* If we're processing a template, we can't finish the semantics yet.
--     Otherwise we can fold the entire expression now.  */
--  if (processing_template_decl)
--    expr = build1 (OFFSETOF_EXPR, size_type_node, expr);
--  else
--    expr = finish_offsetof (expr);
-+  expr = finish_offsetof (expr);
- 
-  failure:
-   parser->integral_constant_expression_p = save_ice_p;
-Index: gcc/cp/call.c
-===================================================================
---- a/src/gcc/cp/call.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/cp/call.c	(.../branches/gcc-4_9-branch)
-@@ -9393,6 +9393,10 @@
- 	/* Check whether the dtor is callable.  */
- 	cxx_maybe_build_cleanup (var, tf_warning_or_error);
-     }
-+  /* Avoid -Wunused-variable warning (c++/38958).  */
-+  if (TYPE_HAS_NONTRIVIAL_DESTRUCTOR (type)
-+      && TREE_CODE (decl) == VAR_DECL)
-+    TREE_USED (decl) = DECL_READ_P (decl) = true;
- 
-   *initp = init;
-   return var;
-Index: gcc/cp/mangle.c
-===================================================================
---- a/src/gcc/cp/mangle.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/cp/mangle.c	(.../branches/gcc-4_9-branch)
-@@ -763,8 +763,7 @@
-       if (extra)
- 	return extra;
-     }
--    else if (TREE_CODE (decl) == TYPE_DECL
--	     && TREE_CODE (TREE_TYPE (decl)) == TEMPLATE_TYPE_PARM)
-+  else if (template_type_parameter_p (decl))
-      /* template type parms have no mangling context.  */
-       return NULL_TREE;
-   return CP_DECL_CONTEXT (decl);
-@@ -3112,6 +3111,8 @@
- 	}
-     }
- 
-+  if (REFERENCE_REF_P (node))
-+    node = TREE_OPERAND (node, 0);
-   if (TREE_CODE (node) == NOP_EXPR
-       && TREE_CODE (TREE_TYPE (node)) == REFERENCE_TYPE)
-     {
-Index: gcc/cp/cp-tree.h
-===================================================================
---- a/src/gcc/cp/cp-tree.h	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/cp/cp-tree.h	(.../branches/gcc-4_9-branch)
-@@ -1098,6 +1098,18 @@
- #define processing_specialization scope_chain->x_processing_specialization
- #define processing_explicit_instantiation scope_chain->x_processing_explicit_instantiation
- 
-+/* RAII sentinel to disable certain warnings during template substitution
-+   and elsewhere.  */
-+
-+struct warning_sentinel
-+{
-+  int &flag;
-+  int val;
-+  warning_sentinel(int& flag, bool suppress=true)
-+    : flag(flag), val(flag) { if (suppress) flag = 0; }
-+  ~warning_sentinel() { flag = val; }
-+};
-+
- /* The cached class binding level, from the most recently exited
-    class, or NULL if none.  */
- 
-Index: gcc/ipa-pure-const.c
-===================================================================
---- a/src/gcc/ipa-pure-const.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/ipa-pure-const.c	(.../branches/gcc-4_9-branch)
-@@ -1434,7 +1434,7 @@
- 	      else if (e->can_throw_external && !TREE_NOTHROW (y->decl))
- 	        can_throw = true;
- 	    }
--          for (ie = node->indirect_calls; ie; ie = ie->next_callee)
-+          for (ie = w->indirect_calls; ie; ie = ie->next_callee)
- 	    if (ie->can_throw_external)
- 	      {
- 		can_throw = true;
-Index: gcc/config.in
-===================================================================
---- a/src/gcc/config.in	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config.in	(.../branches/gcc-4_9-branch)
-@@ -1211,6 +1211,12 @@
- #endif
- 
- 
-+/* Define if isl_schedule_constraints_compute_schedule exists. */
-+#ifndef USED_FOR_TARGET
-+#undef HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE
-+#endif
-+
-+
- /* Define to 1 if you have the `kill' function. */
- #ifndef USED_FOR_TARGET
- #undef HAVE_KILL
-Index: gcc/expr.c
-===================================================================
---- a/src/gcc/expr.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/expr.c	(.../branches/gcc-4_9-branch)
-@@ -7630,11 +7630,13 @@
-       break;
- 
-     case COMPOUND_LITERAL_EXPR:
--      /* Allow COMPOUND_LITERAL_EXPR in initializers, if e.g.
--	 rtl_for_decl_init is called on DECL_INITIAL with
--	 COMPOUNT_LITERAL_EXPRs in it, they aren't gimplified.  */
--      if (modifier == EXPAND_INITIALIZER
--	  && COMPOUND_LITERAL_EXPR_DECL (exp))
-+      /* Allow COMPOUND_LITERAL_EXPR in initializers or coming from
-+	 initializers, if e.g. rtl_for_decl_init is called on DECL_INITIAL
-+	 with COMPOUND_LITERAL_EXPRs in it, or ARRAY_REF on a const static
-+	 array with address of COMPOUND_LITERAL_EXPR in DECL_INITIAL;
-+	 the initializers aren't gimplified.  */
-+      if (COMPOUND_LITERAL_EXPR_DECL (exp)
-+	  && TREE_STATIC (COMPOUND_LITERAL_EXPR_DECL (exp)))
- 	return expand_expr_addr_expr_1 (COMPOUND_LITERAL_EXPR_DECL (exp),
- 					target, tmode, modifier, as);
-       /* FALLTHRU */
-@@ -9990,7 +9992,7 @@
- 	tree tem = get_inner_reference (exp, &bitsize, &bitpos, &offset,
- 					&mode1, &unsignedp, &volatilep, true);
- 	rtx orig_op0, memloc;
--	bool mem_attrs_from_type = false;
-+	bool clear_mem_expr = false;
- 
- 	/* If we got back the original object, something is wrong.  Perhaps
- 	   we are evaluating an expression too early.  In any event, don't
-@@ -10086,7 +10088,7 @@
- 	    memloc = assign_temp (TREE_TYPE (tem), 1, 1);
- 	    emit_move_insn (memloc, op0);
- 	    op0 = memloc;
--	    mem_attrs_from_type = true;
-+	    clear_mem_expr = true;
- 	  }
- 
- 	if (offset)
-@@ -10271,17 +10273,17 @@
- 	if (op0 == orig_op0)
- 	  op0 = copy_rtx (op0);
- 
--	/* If op0 is a temporary because of forcing to memory, pass only the
--	   type to set_mem_attributes so that the original expression is never
--	   marked as ADDRESSABLE through MEM_EXPR of the temporary.  */
--	if (mem_attrs_from_type)
--	  set_mem_attributes (op0, type, 0);
--	else
--	  set_mem_attributes (op0, exp, 0);
-+	set_mem_attributes (op0, exp, 0);
- 
- 	if (REG_P (XEXP (op0, 0)))
- 	  mark_reg_pointer (XEXP (op0, 0), MEM_ALIGN (op0));
- 
-+	/* If op0 is a temporary because the original expressions was forced
-+	   to memory, clear MEM_EXPR so that the original expression cannot
-+	   be marked as addressable through MEM_EXPR of the temporary.  */
-+	if (clear_mem_expr)
-+	  set_mem_expr (op0, NULL_TREE);
-+
- 	MEM_VOLATILE_P (op0) |= volatilep;
- 	if (mode == mode1 || mode1 == BLKmode || mode1 == tmode
- 	    || modifier == EXPAND_CONST_ADDRESS
-Index: gcc/go/gofrontend/import-archive.cc
-===================================================================
---- a/src/gcc/go/gofrontend/import-archive.cc	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/go/gofrontend/import-archive.cc	(.../branches/gcc-4_9-branch)
-@@ -295,6 +295,15 @@
-       // This is the symbol table.
-       pname->clear();
-     }
-+  else if (hdr->ar_name[1] == 'S' && hdr->ar_name[2] == 'Y'
-+          && hdr->ar_name[3] == 'M' && hdr->ar_name[4] == '6'
-+          && hdr->ar_name[5] == '4' && hdr->ar_name[6] == '/'
-+          && hdr->ar_name[7] == ' '
-+         )
-+    {
-+      // 64-bit symbol table.
-+      pname->clear();
-+    }
-   else if (hdr->ar_name[1] == '/')
-     {
-       // This is the extended name table.
-Index: gcc/ada/mlib-utl.adb
-===================================================================
---- a/src/gcc/ada/mlib-utl.adb	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/ada/mlib-utl.adb	(.../branches/gcc-4_9-branch)
-@@ -282,6 +282,10 @@
-          if not Opt.Quiet_Output then
-             Write_Str  (Ranlib_Name.all);
-             Write_Char (' ');
-+            for J in Ranlib_Options'Range loop
-+               Write_Str  (Ranlib_Options (J).all);
-+               Write_Char (' ');
-+            end loop;
-             Write_Line (Arguments (Ar_Options'Length + 1).all);
-          end if;
- 
-Index: gcc/ada/ChangeLog
-===================================================================
---- a/src/gcc/ada/ChangeLog	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/ada/ChangeLog	(.../branches/gcc-4_9-branch)
-@@ -1,3 +1,32 @@
-+2015-01-05  Eric Botcazou  <ebotcazou@adacore.com>
-+
-+	PR ada/64492
-+	* gcc-interface/Makefile.in (../stamp-tools): Reinstate dropped code.
-+
-+2014-11-24  Eric Botcazou  <ebotcazou@adacore.com>
-+
-+	* gcc-interface/trans.c (push_range_check_info): Replace early test
-+	with assertion.
-+	(Raise_Error_to_gnu): Do not call push_range_check_info if the loop
-+	stack is empty.
-+	* gcc-interface/utils.c (convert_to_fat_pointer): Fix formatting.
-+	* gcc-interface/utils2.c (gnat_invariant_expr): Deal with padded types
-+	and revert latest change.
-+
-+2014-11-22  Eric Botcazou  <ebotcazou@adacore.com>
-+
-+	Backport from mainline
-+	2014-11-20  Vincent Celier  <celier@adacore.com>
-+
-+	PR ada/47500
-+	* back_end.adb (Scan_Back_End_Switches): Skip switch -G and
-+	its argument.
-+
-+2014-11-11  Simon Wright  <simon@pushface.org>
-+
-+	PR ada/42978
-+	* mlib-utl.adb (ar): Output the options passed to ranlib.
-+
- 2014-10-30  Release Manager
- 
- 	* GCC 4.9.2 released.
-Index: gcc/ada/back_end.adb
-===================================================================
---- a/src/gcc/ada/back_end.adb	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/ada/back_end.adb	(.../branches/gcc-4_9-branch)
-@@ -210,9 +210,10 @@
-          Last  : constant Natural  := Switch_Last (Switch_Chars);
- 
-       begin
--         --  Skip -o or internal GCC switches together with their argument
-+         --  Skip -o, -G or internal GCC switches together with their argument.
- 
-          if Switch_Chars (First .. Last) = "o"
-+           or else Switch_Chars (First .. Last) = "G"
-            or else Is_Internal_GCC_Switch (Switch_Chars)
-          then
-             Next_Arg := Next_Arg + 1;
-Index: gcc/ada/gcc-interface/utils.c
-===================================================================
---- a/src/gcc/ada/gcc-interface/utils.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/ada/gcc-interface/utils.c	(.../branches/gcc-4_9-branch)
-@@ -4371,8 +4371,7 @@
- 	{
- 	  /* The template type can still be dummy at this point so we build an
- 	     empty constructor.  The middle-end will fill it in with zeros.  */
--	  t = build_constructor (template_type,
--				 NULL);
-+	  t = build_constructor (template_type, NULL);
- 	  TREE_CONSTANT (t) = TREE_STATIC (t) = 1;
- 	  null_bounds = build_unary_op (ADDR_EXPR, NULL_TREE, t);
- 	  SET_TYPE_NULL_BOUNDS (ptr_template_type, null_bounds);
-Index: gcc/ada/gcc-interface/Makefile.in
-===================================================================
---- a/src/gcc/ada/gcc-interface/Makefile.in	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/ada/gcc-interface/Makefile.in	(.../branches/gcc-4_9-branch)
-@@ -2510,9 +2510,16 @@
- # Build directory for the tools. Let's copy the target-dependent
- # sources using the same mechanism as for gnatlib. The other sources are
- # accessed using the vpath directive below
--# Note: dummy target, stamp-tools is mainly handled by gnattools.
- 
- ../stamp-tools:
-+	-$(RM) tools/*
-+	-$(RMDIR) tools
-+	-$(MKDIR) tools
-+	-(cd tools; $(LN_S) ../sdefault.adb ../snames.ads ../snames.adb .)
-+	-$(foreach PAIR,$(TOOLS_TARGET_PAIRS), \
-+	          $(RM) tools/$(word 1,$(subst <, ,$(PAIR)));\
-+	          $(LN_S) $(fsrcpfx)ada/$(word 2,$(subst <, ,$(PAIR))) \
-+	                tools/$(word 1,$(subst <, ,$(PAIR)));)
- 	touch ../stamp-tools
- 
- # when compiling the tools, the runtime has to be first on the path so that
-Index: gcc/ada/gcc-interface/utils2.c
-===================================================================
---- a/src/gcc/ada/gcc-interface/utils2.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/ada/gcc-interface/utils2.c	(.../branches/gcc-4_9-branch)
-@@ -2784,7 +2784,13 @@
- 	  || (TREE_CODE (expr) == VAR_DECL && TREE_READONLY (expr)))
- 	 && decl_function_context (expr) == current_function_decl
- 	 && DECL_INITIAL (expr))
--    expr = remove_conversions (DECL_INITIAL (expr), false);
-+    {
-+      expr = DECL_INITIAL (expr);
-+      /* Look into CONSTRUCTORs built to initialize padded types.  */
-+      if (TYPE_IS_PADDING_P (TREE_TYPE (expr)))
-+	expr = convert (TREE_TYPE (TYPE_FIELDS (TREE_TYPE (expr))), expr);
-+      expr = remove_conversions (expr, false);
-+    }
- 
-   if (TREE_CONSTANT (expr))
-     return fold_convert (type, expr);
-@@ -2840,7 +2846,7 @@
-   if (!TREE_READONLY (t))
-     return NULL_TREE;
- 
--  if (TREE_CODE (t) == CONSTRUCTOR || TREE_CODE (t) == PARM_DECL)
-+  if (TREE_CODE (t) == PARM_DECL)
-     return fold_convert (type, expr);
- 
-   if (TREE_CODE (t) == VAR_DECL
-Index: gcc/ada/gcc-interface/trans.c
-===================================================================
---- a/src/gcc/ada/gcc-interface/trans.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/ada/gcc-interface/trans.c	(.../branches/gcc-4_9-branch)
-@@ -2424,9 +2424,6 @@
-   struct loop_info_d *iter = NULL;
-   unsigned int i;
- 
--  if (vec_safe_is_empty (gnu_loop_stack))
--    return NULL;
--
-   var = remove_conversions (var, false);
- 
-   if (TREE_CODE (var) != VAR_DECL)
-@@ -2435,6 +2432,8 @@
-   if (decl_function_context (var) != current_function_decl)
-     return NULL;
- 
-+  gcc_assert (vec_safe_length (gnu_loop_stack) > 0);
-+
-   for (i = vec_safe_length (gnu_loop_stack) - 1;
-        vec_safe_iterate (gnu_loop_stack, i, &iter);
-        i--)
-@@ -5165,6 +5164,7 @@
- 	     the original checks reinstated, and a run time selection.
- 	     The former loop will be suitable for vectorization.  */
- 	  if (flag_unswitch_loops
-+	      && !vec_safe_is_empty (gnu_loop_stack)
- 	      && (!gnu_low_bound
- 		  || (gnu_low_bound = gnat_invariant_expr (gnu_low_bound)))
- 	      && (!gnu_high_bound
-Index: gcc/tsan.c
-===================================================================
---- a/src/gcc/tsan.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/tsan.c	(.../branches/gcc-4_9-branch)
-@@ -651,25 +651,24 @@
- static void
- instrument_func_entry (void)
- {
--  basic_block succ_bb;
--  gimple_stmt_iterator gsi;
-   tree ret_addr, builtin_decl;
-   gimple g;
-+  gimple_seq seq = NULL;
- 
--  succ_bb = single_succ (ENTRY_BLOCK_PTR_FOR_FN (cfun));
--  gsi = gsi_after_labels (succ_bb);
--
-   builtin_decl = builtin_decl_implicit (BUILT_IN_RETURN_ADDRESS);
-   g = gimple_build_call (builtin_decl, 1, integer_zero_node);
-   ret_addr = make_ssa_name (ptr_type_node, NULL);
-   gimple_call_set_lhs (g, ret_addr);
-   gimple_set_location (g, cfun->function_start_locus);
--  gsi_insert_before (&gsi, g, GSI_SAME_STMT);
-+  gimple_seq_add_stmt_without_update (&seq, g);
- 
--  builtin_decl =  builtin_decl_implicit (BUILT_IN_TSAN_FUNC_ENTRY);
-+  builtin_decl = builtin_decl_implicit (BUILT_IN_TSAN_FUNC_ENTRY);
-   g = gimple_build_call (builtin_decl, 1, ret_addr);
-   gimple_set_location (g, cfun->function_start_locus);
--  gsi_insert_before (&gsi, g, GSI_SAME_STMT);
-+  gimple_seq_add_stmt_without_update (&seq, g);
-+
-+  edge e = single_succ_edge (ENTRY_BLOCK_PTR_FOR_FN (cfun));
-+  gsi_insert_seq_on_edge_immediate (e, seq);
- }
- 
- /* Instruments function exits.  */
-Index: gcc/fortran/interface.c
-===================================================================
---- a/src/gcc/fortran/interface.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/fortran/interface.c	(.../branches/gcc-4_9-branch)
-@@ -3675,6 +3675,8 @@
-   gfc_user_op *uop;
-   gfc_intrinsic_op i;
-   const char *gname;
-+  gfc_typebound_proc* tbo;
-+  gfc_expr* tb_base;
- 
-   sym = NULL;
- 
-@@ -3691,8 +3693,50 @@
- 
-   i = fold_unary_intrinsic (e->value.op.op);
- 
-+  /* See if we find a matching type-bound operator.  */
-   if (i == INTRINSIC_USER)
-+    tbo = matching_typebound_op (&tb_base, actual,
-+				  i, e->value.op.uop->name, &gname);
-+  else
-+    switch (i)
-+      {
-+#define CHECK_OS_COMPARISON(comp) \
-+  case INTRINSIC_##comp: \
-+  case INTRINSIC_##comp##_OS: \
-+    tbo = matching_typebound_op (&tb_base, actual, \
-+				 INTRINSIC_##comp, NULL, &gname); \
-+    if (!tbo) \
-+      tbo = matching_typebound_op (&tb_base, actual, \
-+				   INTRINSIC_##comp##_OS, NULL, &gname); \
-+    break;
-+	CHECK_OS_COMPARISON(EQ)
-+	CHECK_OS_COMPARISON(NE)
-+	CHECK_OS_COMPARISON(GT)
-+	CHECK_OS_COMPARISON(GE)
-+	CHECK_OS_COMPARISON(LT)
-+	CHECK_OS_COMPARISON(LE)
-+#undef CHECK_OS_COMPARISON
-+
-+	default:
-+	  tbo = matching_typebound_op (&tb_base, actual, i, NULL, &gname);
-+	  break;
-+      }
-+
-+  /* If there is a matching typebound-operator, replace the expression with
-+      a call to it and succeed.  */
-+  if (tbo)
-     {
-+      gcc_assert (tb_base);
-+      build_compcall_for_operator (e, actual, tb_base, tbo, gname);
-+
-+      if (!gfc_resolve_expr (e))
-+	return MATCH_ERROR;
-+      else
-+	return MATCH_YES;
-+    }
-+ 
-+  if (i == INTRINSIC_USER)
-+    {
-       for (ns = gfc_current_ns; ns; ns = ns->parent)
- 	{
- 	  uop = gfc_find_uop (e->value.op.uop->name, ns);
-@@ -3741,58 +3785,9 @@
- 
-   if (sym == NULL)
-     {
--      gfc_typebound_proc* tbo;
--      gfc_expr* tb_base;
--
--      /* See if we find a matching type-bound operator.  */
--      if (i == INTRINSIC_USER)
--	tbo = matching_typebound_op (&tb_base, actual,
--				     i, e->value.op.uop->name, &gname);
--      else
--	switch (i)
--	  {
--#define CHECK_OS_COMPARISON(comp) \
--  case INTRINSIC_##comp: \
--  case INTRINSIC_##comp##_OS: \
--    tbo = matching_typebound_op (&tb_base, actual, \
--				 INTRINSIC_##comp, NULL, &gname); \
--    if (!tbo) \
--      tbo = matching_typebound_op (&tb_base, actual, \
--				   INTRINSIC_##comp##_OS, NULL, &gname); \
--    break;
--	    CHECK_OS_COMPARISON(EQ)
--	    CHECK_OS_COMPARISON(NE)
--	    CHECK_OS_COMPARISON(GT)
--	    CHECK_OS_COMPARISON(GE)
--	    CHECK_OS_COMPARISON(LT)
--	    CHECK_OS_COMPARISON(LE)
--#undef CHECK_OS_COMPARISON
--
--	    default:
--	      tbo = matching_typebound_op (&tb_base, actual, i, NULL, &gname);
--	      break;
--	  }
--
--      /* If there is a matching typebound-operator, replace the expression with
--	 a call to it and succeed.  */
--      if (tbo)
--	{
--	  bool result;
--
--	  gcc_assert (tb_base);
--	  build_compcall_for_operator (e, actual, tb_base, tbo, gname);
--
--	  result = gfc_resolve_expr (e);
--	  if (!result)
--	    return MATCH_ERROR;
--
--	  return MATCH_YES;
--	}
--
-       /* Don't use gfc_free_actual_arglist().  */
-       free (actual->next);
-       free (actual);
--
-       return MATCH_NO;
-     }
- 
-Index: gcc/fortran/trans-array.c
-===================================================================
---- a/src/gcc/fortran/trans-array.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/fortran/trans-array.c	(.../branches/gcc-4_9-branch)
-@@ -4350,6 +4350,13 @@
- 	      && ss_expr->rank)
- 	    nDepend = gfc_check_dependency (dest_expr, ss_expr, true);
- 
-+	  /* Check for cases like   c(:)(1:2) = c(2)(2:3)  */
-+	  if (!nDepend && dest_expr->rank > 0
-+	      && dest_expr->ts.type == BT_CHARACTER
-+	      && ss_expr->expr_type == EXPR_VARIABLE)
-+	    
-+	    nDepend = gfc_check_dependency (dest_expr, ss_expr, false);
-+
- 	  continue;
- 	}
- 
-Index: gcc/fortran/trans-openmp.c
-===================================================================
---- a/src/gcc/fortran/trans-openmp.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/fortran/trans-openmp.c	(.../branches/gcc-4_9-branch)
-@@ -2683,6 +2683,18 @@
-     }
- 
-   lhsaddr = save_expr (lhsaddr);
-+  if (TREE_CODE (lhsaddr) != SAVE_EXPR
-+      && (TREE_CODE (lhsaddr) != ADDR_EXPR
-+	  || TREE_CODE (TREE_OPERAND (lhsaddr, 0)) != VAR_DECL))
-+    {
-+      /* Make sure LHS is simple enough so that goa_lhs_expr_p can recognize
-+	 it even after unsharing function body.  */
-+      tree var = create_tmp_var_raw (TREE_TYPE (lhsaddr), NULL);
-+      DECL_CONTEXT (var) = current_function_decl;
-+      lhsaddr = build4 (TARGET_EXPR, TREE_TYPE (lhsaddr), var, lhsaddr,
-+			NULL_TREE, NULL_TREE);
-+    }
-+
-   rhs = gfc_evaluate_now (rse.expr, &block);
- 
-   if (((atomic_code->ext.omp_atomic & GFC_OMP_ATOMIC_MASK)
-Index: gcc/fortran/ChangeLog
-===================================================================
---- a/src/gcc/fortran/ChangeLog	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/fortran/ChangeLog	(.../branches/gcc-4_9-branch)
-@@ -1,3 +1,44 @@
-+2015-01-14  Jakub Jelinek  <jakub@redhat.com>
-+
-+	Backported from mainline
-+	2015-01-13  Jakub Jelinek  <jakub@redhat.com>
-+
-+	PR fortran/64528
-+	* trans-decl.c (create_function_arglist): Don't set TREE_READONLY
-+	on dummy args with VALUE attribute.
-+
-+2015-01-12  Janus Weil  <janus@gcc.gnu.org>
-+
-+	Backport from mainline
-+	PR fortran/63733
-+	* interface.c (gfc_extend_expr): Look for type-bound operators before
-+	non-typebound ones.
-+
-+2015-01-08  Thomas Koenig  <tkoenig@gcc.gnu.org>
-+
-+	Backport from trunk
-+	PR fortran/56867
-+	* trans-array.c (gfc_conv_resolve_dependencies):  Also check
-+	dependencies when there may be substrings of character arrays.
-+
-+2014-12-23  Janus Weil  <janus@gcc.gnu.org>
-+
-+	Backport from mainline
-+	PR fortran/64244
-+	* resolve.c (resolve_typebound_call): New argument to pass out the
-+	non-overridable attribute of the specific procedure.
-+	(resolve_typebound_subroutine): Get overridable flag from
-+	resolve_typebound_call.
-+
-+2014-11-28  Jakub Jelinek  <jakub@redhat.com>
-+
-+	Backported from mainline
-+	2014-11-24  Jakub Jelinek  <jakub@redhat.com>
-+
-+	PR fortran/63938
-+	* trans-openmp.c (gfc_trans_omp_atomic): Make sure lhsaddr is
-+	simple enough for goa_lhs_expr_p.
-+
- 2014-10-30  Release Manager
- 
- 	* GCC 4.9.2 released.
-Index: gcc/fortran/resolve.c
-===================================================================
---- a/src/gcc/fortran/resolve.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/fortran/resolve.c	(.../branches/gcc-4_9-branch)
-@@ -5590,7 +5590,7 @@
- /* Resolve a call to a type-bound subroutine.  */
- 
- static bool
--resolve_typebound_call (gfc_code* c, const char **name)
-+resolve_typebound_call (gfc_code* c, const char **name, bool *overridable)
- {
-   gfc_actual_arglist* newactual;
-   gfc_symtree* target;
-@@ -5614,6 +5614,10 @@
-   if (!resolve_typebound_generic_call (c->expr1, name))
-     return false;
- 
-+  /* Pass along the NON_OVERRIDABLE attribute of the specific TBP. */
-+  if (overridable)
-+    *overridable = !c->expr1->value.compcall.tbp->non_overridable;
-+
-   /* Transform into an ordinary EXEC_CALL for now.  */
- 
-   if (!resolve_typebound_static (c->expr1, &target, &newactual))
-@@ -5873,7 +5877,7 @@
-       if (c->ts.u.derived == NULL)
- 	c->ts.u.derived = gfc_find_derived_vtab (declared);
- 
--      if (!resolve_typebound_call (code, &name))
-+      if (!resolve_typebound_call (code, &name, NULL))
- 	return false;
- 
-       /* Use the generic name if it is there.  */
-@@ -5905,7 +5909,7 @@
-     }
- 
-   if (st == NULL)
--    return resolve_typebound_call (code, NULL);
-+    return resolve_typebound_call (code, NULL, NULL);
- 
-   if (!resolve_ref (code->expr1))
-     return false;
-@@ -5918,10 +5922,10 @@
- 	 || (!class_ref && st->n.sym->ts.type != BT_CLASS))
-     {
-       gfc_free_ref_list (new_ref);
--      return resolve_typebound_call (code, NULL);
-+      return resolve_typebound_call (code, NULL, NULL);
-     }
- 
--  if (!resolve_typebound_call (code, &name))
-+  if (!resolve_typebound_call (code, &name, &overridable))
-     {
-       gfc_free_ref_list (new_ref);
-       return false;
-Index: gcc/fortran/trans-decl.c
-===================================================================
---- a/src/gcc/fortran/trans-decl.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/fortran/trans-decl.c	(.../branches/gcc-4_9-branch)
-@@ -2262,8 +2262,9 @@
-       /* Fill in arg stuff.  */
-       DECL_CONTEXT (parm) = fndecl;
-       DECL_ARG_TYPE (parm) = TREE_VALUE (typelist);
--      /* All implementation args are read-only.  */
--      TREE_READONLY (parm) = 1;
-+      /* All implementation args except for VALUE are read-only.  */
-+      if (!f->sym->attr.value)
-+	TREE_READONLY (parm) = 1;
-       if (POINTER_TYPE_P (type)
- 	  && (!f->sym->attr.proc_pointer
- 	      && f->sym->attr.flavor != FL_PROCEDURE))
-Index: gcc/configure.ac
-===================================================================
---- a/src/gcc/configure.ac	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/configure.ac	(.../branches/gcc-4_9-branch)
-@@ -5495,8 +5495,31 @@
- AC_ARG_VAR(CLOOGINC,[How to find CLOOG include files])
- if test "x${CLOOGLIBS}" != "x" ; then 
-    AC_DEFINE(HAVE_cloog, 1, [Define if cloog is in use.])
-+
-+  # Check whether isl_schedule_constraints_compute_schedule is available;
-+  # it's new in ISL-0.13.
-+  saved_CFLAGS="$CFLAGS"
-+  CFLAGS="$CFLAGS $ISLINC"
-+  saved_LIBS="$LIBS"
-+  LIBS="$LIBS $CLOOGLIBS $ISLLIBS $GMPLIBS"
-+
-+  AC_MSG_CHECKING([Checking for isl_schedule_constraints_compute_schedule])
-+  AC_TRY_LINK([#include <isl/schedule.h>],
-+              [isl_schedule_constraints_compute_schedule (NULL);],
-+              [ac_has_isl_schedule_constraints_compute_schedule=yes],
-+              [ac_has_isl_schedule_constraints_compute_schedule=no])
-+  AC_MSG_RESULT($ac_has_isl_schedule_constraints_compute_schedule)
-+
-+  LIBS="$saved_LIBS"
-+  CFLAGS="$saved_CFLAGS"
-+
-+  if test x"$ac_has_isl_schedule_constraints_compute_schedule" = x"yes"; then
-+     AC_DEFINE(HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE, 1,
-+               [Define if isl_schedule_constraints_compute_schedule exists.])
-+  fi
- fi
- 
-+
- # Check for plugin support
- AC_ARG_ENABLE(plugin,
- [AS_HELP_STRING([--enable-plugin], [enable plugin support])],
-Index: gcc/alias.c
-===================================================================
---- a/src/gcc/alias.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/alias.c	(.../branches/gcc-4_9-branch)
-@@ -383,17 +383,9 @@
- static inline int
- mems_in_disjoint_alias_sets_p (const_rtx mem1, const_rtx mem2)
- {
--/* Perform a basic sanity check.  Namely, that there are no alias sets
--   if we're not using strict aliasing.  This helps to catch bugs
--   whereby someone uses PUT_CODE, but doesn't clear MEM_ALIAS_SET, or
--   where a MEM is allocated in some way other than by the use of
--   gen_rtx_MEM, and the MEM_ALIAS_SET is not cleared.  If we begin to
--   use alias sets to indicate that spilled registers cannot alias each
--   other, we might need to remove this check.  */
--  gcc_assert (flag_strict_aliasing
--	      || (!MEM_ALIAS_SET (mem1) && !MEM_ALIAS_SET (mem2)));
--
--  return ! alias_sets_conflict_p (MEM_ALIAS_SET (mem1), MEM_ALIAS_SET (mem2));
-+  return (flag_strict_aliasing
-+	  && ! alias_sets_conflict_p (MEM_ALIAS_SET (mem1),
-+				      MEM_ALIAS_SET (mem2)));
- }
- 
- /* Insert the NODE into the splay tree given by DATA.  Used by
-@@ -2517,6 +2509,7 @@
- true_dependence_1 (const_rtx mem, enum machine_mode mem_mode, rtx mem_addr,
- 		   const_rtx x, rtx x_addr, bool mem_canonicalized)
- {
-+  rtx true_mem_addr;
-   rtx base;
-   int ret;
- 
-@@ -2536,10 +2529,26 @@
-       || MEM_ALIAS_SET (mem) == ALIAS_SET_MEMORY_BARRIER)
-     return 1;
- 
-+  if (! x_addr)
-+    x_addr = XEXP (x, 0);
-+  x_addr = get_addr (x_addr);
-+
-+  if (! mem_addr)
-+    {
-+      mem_addr = XEXP (mem, 0);
-+      if (mem_mode == VOIDmode)
-+	mem_mode = GET_MODE (mem);
-+    }
-+  true_mem_addr = get_addr (mem_addr);
-+
-   /* Read-only memory is by definition never modified, and therefore can't
--     conflict with anything.  We don't expect to find read-only set on MEM,
--     but stupid user tricks can produce them, so don't die.  */
--  if (MEM_READONLY_P (x))
-+     conflict with anything.  However, don't assume anything when AND
-+     addresses are involved and leave to the code below to determine
-+     dependence.  We don't expect to find read-only set on MEM, but
-+     stupid user tricks can produce them, so don't die.  */
-+  if (MEM_READONLY_P (x)
-+      && GET_CODE (x_addr) != AND
-+      && GET_CODE (true_mem_addr) != AND)
-     return 0;
- 
-   /* If we have MEMs referring to different address spaces (which can
-@@ -2548,29 +2557,6 @@
-   if (MEM_ADDR_SPACE (mem) != MEM_ADDR_SPACE (x))
-     return 1;
- 
--  if (! mem_addr)
--    {
--      mem_addr = XEXP (mem, 0);
--      if (mem_mode == VOIDmode)
--	mem_mode = GET_MODE (mem);
--    }
--
--  if (! x_addr)
--    {
--      x_addr = XEXP (x, 0);
--      if (!((GET_CODE (x_addr) == VALUE
--	     && GET_CODE (mem_addr) != VALUE
--	     && reg_mentioned_p (x_addr, mem_addr))
--	    || (GET_CODE (x_addr) != VALUE
--		&& GET_CODE (mem_addr) == VALUE
--		&& reg_mentioned_p (mem_addr, x_addr))))
--	{
--	  x_addr = get_addr (x_addr);
--	  if (! mem_canonicalized)
--	    mem_addr = get_addr (mem_addr);
--	}
--    }
--
-   base = find_base_term (x_addr);
-   if (base && (GET_CODE (base) == LABEL_REF
- 	       || (GET_CODE (base) == SYMBOL_REF
-@@ -2577,14 +2563,14 @@
- 		   && CONSTANT_POOL_ADDRESS_P (base))))
-     return 0;
- 
--  rtx mem_base = find_base_term (mem_addr);
--  if (! base_alias_check (x_addr, base, mem_addr, mem_base,
-+  rtx mem_base = find_base_term (true_mem_addr);
-+  if (! base_alias_check (x_addr, base, true_mem_addr, mem_base,
- 			  GET_MODE (x), mem_mode))
-     return 0;
- 
-   x_addr = canon_rtx (x_addr);
-   if (!mem_canonicalized)
--    mem_addr = canon_rtx (mem_addr);
-+    mem_addr = canon_rtx (true_mem_addr);
- 
-   if ((ret = memrefs_conflict_p (GET_MODE_SIZE (mem_mode), mem_addr,
- 				 SIZE_FOR_MODE (x), x_addr, 0)) != -1)
-@@ -2637,6 +2623,7 @@
- 		    bool mem_canonicalized, bool x_canonicalized, bool writep)
- {
-   rtx mem_addr;
-+  rtx true_mem_addr, true_x_addr;
-   rtx base;
-   int ret;
- 
-@@ -2657,8 +2644,20 @@
-       || MEM_ALIAS_SET (mem) == ALIAS_SET_MEMORY_BARRIER)
-     return 1;
- 
--  /* A read from read-only memory can't conflict with read-write memory.  */
--  if (!writep && MEM_READONLY_P (mem))
-+  if (!x_addr)
-+    x_addr = XEXP (x, 0);
-+  true_x_addr = get_addr (x_addr);
-+
-+  mem_addr = XEXP (mem, 0);
-+  true_mem_addr = get_addr (mem_addr);
-+
-+  /* A read from read-only memory can't conflict with read-write memory.
-+     Don't assume anything when AND addresses are involved and leave to
-+     the code below to determine dependence.  */
-+  if (!writep
-+      && MEM_READONLY_P (mem)
-+      && GET_CODE (true_x_addr) != AND
-+      && GET_CODE (true_mem_addr) != AND)
-     return 0;
- 
-   /* If we have MEMs referring to different address spaces (which can
-@@ -2667,24 +2666,7 @@
-   if (MEM_ADDR_SPACE (mem) != MEM_ADDR_SPACE (x))
-     return 1;
- 
--  mem_addr = XEXP (mem, 0);
--  if (!x_addr)
--    {
--      x_addr = XEXP (x, 0);
--      if (!((GET_CODE (x_addr) == VALUE
--	     && GET_CODE (mem_addr) != VALUE
--	     && reg_mentioned_p (x_addr, mem_addr))
--	    || (GET_CODE (x_addr) != VALUE
--		&& GET_CODE (mem_addr) == VALUE
--		&& reg_mentioned_p (mem_addr, x_addr))))
--	{
--	  x_addr = get_addr (x_addr);
--	  if (!mem_canonicalized)
--	    mem_addr = get_addr (mem_addr);
--	}
--    }
--
--  base = find_base_term (mem_addr);
-+  base = find_base_term (true_mem_addr);
-   if (! writep
-       && base
-       && (GET_CODE (base) == LABEL_REF
-@@ -2692,18 +2674,18 @@
- 	      && CONSTANT_POOL_ADDRESS_P (base))))
-     return 0;
- 
--  rtx x_base = find_base_term (x_addr);
--  if (! base_alias_check (x_addr, x_base, mem_addr, base, GET_MODE (x),
--			  GET_MODE (mem)))
-+  rtx x_base = find_base_term (true_x_addr);
-+  if (! base_alias_check (true_x_addr, x_base, true_mem_addr, base,
-+			  GET_MODE (x), GET_MODE (mem)))
-     return 0;
- 
-   if (!x_canonicalized)
-     {
--      x_addr = canon_rtx (x_addr);
-+      x_addr = canon_rtx (true_x_addr);
-       x_mode = GET_MODE (x);
-     }
-   if (!mem_canonicalized)
--    mem_addr = canon_rtx (mem_addr);
-+    mem_addr = canon_rtx (true_mem_addr);
- 
-   if ((ret = memrefs_conflict_p (SIZE_FOR_MODE (mem), mem_addr,
- 				 GET_MODE_SIZE (x_mode), x_addr, 0)) != -1)
-@@ -2771,10 +2753,20 @@
-       || MEM_ALIAS_SET (mem) == ALIAS_SET_MEMORY_BARRIER)
-     return 1;
- 
-+  x_addr = XEXP (x, 0);
-+  x_addr = get_addr (x_addr);
-+
-+  mem_addr = XEXP (mem, 0);
-+  mem_addr = get_addr (mem_addr);
-+
-   /* Read-only memory is by definition never modified, and therefore can't
--     conflict with anything.  We don't expect to find read-only set on MEM,
--     but stupid user tricks can produce them, so don't die.  */
--  if (MEM_READONLY_P (x))
-+     conflict with anything.  However, don't assume anything when AND
-+     addresses are involved and leave to the code below to determine
-+     dependence.  We don't expect to find read-only set on MEM, but
-+     stupid user tricks can produce them, so don't die.  */
-+  if (MEM_READONLY_P (x)
-+      && GET_CODE (x_addr) != AND
-+      && GET_CODE (mem_addr) != AND)
-     return 0;
- 
-   /* If we have MEMs referring to different address spaces (which can
-@@ -2783,19 +2775,6 @@
-   if (MEM_ADDR_SPACE (mem) != MEM_ADDR_SPACE (x))
-     return 1;
- 
--  x_addr = XEXP (x, 0);
--  mem_addr = XEXP (mem, 0);
--  if (!((GET_CODE (x_addr) == VALUE
--	 && GET_CODE (mem_addr) != VALUE
--	 && reg_mentioned_p (x_addr, mem_addr))
--	|| (GET_CODE (x_addr) != VALUE
--	    && GET_CODE (mem_addr) == VALUE
--	    && reg_mentioned_p (mem_addr, x_addr))))
--    {
--      x_addr = get_addr (x_addr);
--      mem_addr = get_addr (mem_addr);
--    }
--
-   rtx x_base = find_base_term (x_addr);
-   rtx mem_base = find_base_term (mem_addr);
-   if (! base_alias_check (x_addr, x_base, mem_addr, mem_base,
-@@ -2802,9 +2781,6 @@
- 			  GET_MODE (x), GET_MODE (mem_addr)))
-     return 0;
- 
--  x_addr = canon_rtx (x_addr);
--  mem_addr = canon_rtx (mem_addr);
--
-   if (nonoverlapping_memrefs_p (mem, x, true))
-     return 0;
- 
-Index: gcc/tree-vect-loop.c
-===================================================================
---- a/src/gcc/tree-vect-loop.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/tree-vect-loop.c	(.../branches/gcc-4_9-branch)
-@@ -1647,6 +1647,13 @@
-       return false;
-     }
- 
-+  /* Classify all cross-iteration scalar data-flow cycles.
-+     Cross-iteration cycles caused by virtual phis are analyzed separately.  */
-+
-+  vect_analyze_scalar_cycles (loop_vinfo);
-+
-+  vect_pattern_recog (loop_vinfo, NULL);
-+
-   /* Analyze the access patterns of the data-refs in the loop (consecutive,
-      complex, etc.). FORNOW: Only handle consecutive access pattern.  */
- 
-@@ -1659,13 +1666,6 @@
-       return false;
-     }
- 
--  /* Classify all cross-iteration scalar data-flow cycles.
--     Cross-iteration cycles caused by virtual phis are analyzed separately.  */
--
--  vect_analyze_scalar_cycles (loop_vinfo);
--
--  vect_pattern_recog (loop_vinfo, NULL);
--
-   /* Data-flow analysis to detect stmts that do not need to be vectorized.  */
- 
-   ok = vect_mark_stmts_to_be_vectorized (loop_vinfo);
-Index: gcc/tree-data-ref.c
-===================================================================
---- a/src/gcc/tree-data-ref.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/tree-data-ref.c	(.../branches/gcc-4_9-branch)
-@@ -663,6 +663,9 @@
- 
-     case SSA_NAME:
-       {
-+	if (SSA_NAME_OCCURS_IN_ABNORMAL_PHI (op0))
-+	  return false;
-+
- 	gimple def_stmt = SSA_NAME_DEF_STMT (op0);
- 	enum tree_code subcode;
- 
-Index: gcc/trans-mem.c
-===================================================================
---- a/src/gcc/trans-mem.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/trans-mem.c	(.../branches/gcc-4_9-branch)
-@@ -164,6 +164,9 @@
- static tree
- get_attrs_for (const_tree x)
- {
-+  if (x == NULL_TREE)
-+    return NULL_TREE;
-+
-   switch (TREE_CODE (x))
-     {
-     case FUNCTION_DECL:
-@@ -172,16 +175,16 @@
- 
-     default:
-       if (TYPE_P (x))
--	return NULL;
-+	return NULL_TREE;
-       x = TREE_TYPE (x);
-       if (TREE_CODE (x) != POINTER_TYPE)
--	return NULL;
-+	return NULL_TREE;
-       /* FALLTHRU */
- 
-     case POINTER_TYPE:
-       x = TREE_TYPE (x);
-       if (TREE_CODE (x) != FUNCTION_TYPE && TREE_CODE (x) != METHOD_TYPE)
--	return NULL;
-+	return NULL_TREE;
-       /* FALLTHRU */
- 
-     case FUNCTION_TYPE:
-Index: gcc/ipa-inline-analysis.c
-===================================================================
---- a/src/gcc/ipa-inline-analysis.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/ipa-inline-analysis.c	(.../branches/gcc-4_9-branch)
-@@ -861,9 +861,19 @@
- 	}
-       if (c->code == IS_NOT_CONSTANT || c->code == CHANGED)
- 	continue;
--      res = fold_binary_to_constant (c->code, boolean_type_node, val, c->val);
--      if (res && integer_zerop (res))
--	continue;
-+
-+      if (operand_equal_p (TYPE_SIZE (TREE_TYPE (c->val)),
-+			   TYPE_SIZE (TREE_TYPE (val)), 0))
-+	{
-+	  val = fold_unary (VIEW_CONVERT_EXPR, TREE_TYPE (c->val), val);
-+
-+	  res = val
-+	    ? fold_binary_to_constant (c->code, boolean_type_node, val, c->val)
-+	    : NULL;
-+
-+	  if (res && integer_zerop (res))
-+	    continue;
-+	}
-       clause |= 1 << (i + predicate_first_dynamic_condition);
-     }
-   return clause;
-Index: gcc/expmed.c
-===================================================================
---- a/src/gcc/expmed.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/expmed.c	(.../branches/gcc-4_9-branch)
-@@ -463,7 +463,7 @@
-   /* Check for cases where the C++ memory model applies.  */
-   if (bitregion_end != 0
-       && (bitnum - bitnum % modesize < bitregion_start
--	  || bitnum - bitnum % modesize + modesize > bitregion_end))
-+	  || bitnum - bitnum % modesize + modesize - 1 > bitregion_end))
-     return false;
- 
-   return true;
-@@ -3321,6 +3321,9 @@
-       enum mult_variant variant;
-       struct algorithm algorithm;
- 
-+      if (coeff == 0)
-+	return CONST0_RTX (mode);
-+
-       /* Special case powers of two.  */
-       if (EXACT_POWER_OF_2_OR_ZERO_P (coeff))
- 	{
-Index: gcc/tree-predcom.c
-===================================================================
---- a/src/gcc/tree-predcom.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/tree-predcom.c	(.../branches/gcc-4_9-branch)
-@@ -1391,8 +1391,8 @@
-     off = size_binop (PLUS_EXPR, off,
- 		      size_binop (MULT_EXPR, DR_STEP (dr), ssize_int (iter)));
-   tree addr = fold_build_pointer_plus (DR_BASE_ADDRESS (dr), off);
--  addr = force_gimple_operand_1 (addr, stmts, is_gimple_mem_ref_addr,
--				 NULL_TREE);
-+  addr = force_gimple_operand_1 (unshare_expr (addr), stmts,
-+				 is_gimple_mem_ref_addr, NULL_TREE);
-   tree alias_ptr = fold_convert (reference_alias_ptr_type (DR_REF (dr)), coff);
-   /* While data-ref analysis punts on bit offsets it still handles
-      bitfield accesses at byte boundaries.  Cope with that.  Note that
-Index: gcc/ubsan.c
-===================================================================
---- a/src/gcc/ubsan.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/ubsan.c	(.../branches/gcc-4_9-branch)
-@@ -47,6 +47,7 @@
- #include "asan.h"
- #include "gimplify-me.h"
- #include "intl.h"
-+#include "tree-eh.h"
- 
- /* Map from a tree to a VAR_DECL tree.  */
- 
-@@ -807,7 +808,9 @@
-       || TREE_CODE (gimple_assign_lhs (stmt)) != SSA_NAME)
-     return;
- 
-+  bool can_throw = stmt_could_throw_p (stmt);
-   location_t loc = gimple_location (stmt);
-+  tree lhs = gimple_assign_lhs (stmt);
-   tree ptype = build_pointer_type (TREE_TYPE (rhs));
-   tree atype = reference_alias_ptr_type (rhs);
-   gimple g = gimple_build_assign (make_ssa_name (ptype, NULL),
-@@ -817,9 +820,24 @@
-   tree mem = build2 (MEM_REF, utype, gimple_assign_lhs (g),
- 		     build_int_cst (atype, 0));
-   tree urhs = make_ssa_name (utype, NULL);
--  g = gimple_build_assign (urhs, mem);
--  gimple_set_location (g, loc);
--  gsi_insert_before (gsi, g, GSI_SAME_STMT);
-+  if (can_throw)
-+    {
-+      gimple_assign_set_lhs (stmt, urhs);
-+      g = gimple_build_assign_with_ops (NOP_EXPR, lhs, urhs, NULL_TREE);
-+      gimple_set_location (g, loc);
-+      edge e = find_fallthru_edge (gimple_bb (stmt)->succs);
-+      gsi_insert_on_edge_immediate (e, g);
-+      gimple_assign_set_rhs_from_tree (gsi, mem);
-+      update_stmt (stmt);
-+      *gsi = gsi_for_stmt (g);
-+      g = stmt;
-+    }
-+  else
-+    {
-+      g = gimple_build_assign (urhs, mem);
-+      gimple_set_location (g, loc);
-+      gsi_insert_before (gsi, g, GSI_SAME_STMT);
-+    }
-   minv = fold_convert (utype, minv);
-   maxv = fold_convert (utype, maxv);
-   if (!integer_zerop (minv))
-@@ -841,8 +859,11 @@
-   gimple_set_location (g, loc);
-   gsi_insert_after (gsi, g, GSI_NEW_STMT);
- 
--  gimple_assign_set_rhs_with_ops (&gsi2, NOP_EXPR, urhs, NULL_TREE);
--  update_stmt (stmt);
-+  if (!can_throw)
-+    {
-+      gimple_assign_set_rhs_with_ops (&gsi2, NOP_EXPR, urhs, NULL_TREE);
-+      update_stmt (stmt);
-+    }
- 
-   tree data = ubsan_create_data ("__ubsan_invalid_value_data",
- 				 &loc, NULL,
-Index: gcc/tree-ssa-forwprop.c
-===================================================================
---- a/src/gcc/tree-ssa-forwprop.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/tree-ssa-forwprop.c	(.../branches/gcc-4_9-branch)
-@@ -1534,7 +1534,8 @@
- 	  use_operand_p use_p;
- 
- 	  if (!tree_fits_shwi_p (val2)
--	      || !tree_fits_uhwi_p (len2))
-+	      || !tree_fits_uhwi_p (len2)
-+	      || compare_tree_int (len2, 1024) == 1)
- 	    break;
- 	  if (is_gimple_call (stmt1))
- 	    {
-@@ -1600,7 +1601,8 @@
- 	     is not constant, or is bigger than memcpy length, bail out.  */
- 	  if (diff == NULL
- 	      || !tree_fits_uhwi_p (diff)
--	      || tree_int_cst_lt (len1, diff))
-+	      || tree_int_cst_lt (len1, diff)
-+	      || compare_tree_int (diff, 1024) == 1)
- 	    break;
- 
- 	  /* Use maximum of difference plus memset length and memcpy length
-@@ -3178,7 +3180,9 @@
- 	  && (INTEGRAL_TYPE_P (TREE_TYPE (def_op))
- 	      || POINTER_TYPE_P (TREE_TYPE (def_op)))
- 	  && (TYPE_PRECISION (TREE_TYPE (op))
--	      == TYPE_PRECISION (TREE_TYPE (def_op))))
-+	      == TYPE_PRECISION (TREE_TYPE (def_op)))
-+	  && (TYPE_SIZE (TREE_TYPE (op))
-+	      == TYPE_SIZE (TREE_TYPE (def_op))))
- 	{
- 	  TREE_OPERAND (gimple_assign_rhs1 (stmt), 0) = def_op;
- 	  update_stmt (stmt);
-Index: gcc/graphite-clast-to-gimple.c
-===================================================================
---- a/src/gcc/graphite-clast-to-gimple.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/graphite-clast-to-gimple.c	(.../branches/gcc-4_9-branch)
-@@ -30,7 +30,12 @@
- #include <isl/aff.h>
- #include <cloog/cloog.h>
- #include <cloog/isl/domain.h>
-+#ifdef HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE
-+#include <isl/deprecated/int.h>
-+#include <isl/lp.h>
-+#include <isl/deprecated/ilp_int.h>
- #endif
-+#endif
- 
- #include "system.h"
- #include "coretypes.h"
-Index: gcc/graphite-optimize-isl.c
-===================================================================
---- a/src/gcc/graphite-optimize-isl.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/graphite-optimize-isl.c	(.../branches/gcc-4_9-branch)
-@@ -28,7 +28,11 @@
- #include <isl/band.h>
- #include <isl/aff.h>
- #include <isl/options.h>
-+#ifdef HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE
-+#include <isl/deprecated/int.h>
-+#include <isl/deprecated/aff_int.h>
- #endif
-+#endif
- 
- #include "system.h"
- #include "coretypes.h"
-@@ -373,7 +377,11 @@
- 	{
- 	  for (i = ScheduleDimensions - 1 ;  i >= 0 ; i--)
- 	    {
-+#ifdef HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE
-+	      if (isl_band_member_is_coincident (Band, i))
-+#else
- 	      if (isl_band_member_is_zero_distance (Band, i))
-+#endif
- 		{
- 		  isl_map *TileMap;
- 		  isl_union_map *TileUMap;
-Index: gcc/varasm.c
-===================================================================
---- a/src/gcc/varasm.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/varasm.c	(.../branches/gcc-4_9-branch)
-@@ -95,11 +95,6 @@
- 
- bool first_function_block_is_cold;
- 
--/* We give all constants their own alias set.  Perhaps redundant with
--   MEM_READONLY_P, but pre-dates it.  */
--
--static alias_set_type const_alias_set;
--
- /* Whether we saw any functions with no_split_stack.  */
- 
- static bool saw_no_split_stack;
-@@ -3250,7 +3245,6 @@
-   rtl = gen_const_mem (TYPE_MODE (TREE_TYPE (exp)), symbol);
-   set_mem_attributes (rtl, exp, 1);
-   set_mem_alias_set (rtl, 0);
--  set_mem_alias_set (rtl, const_alias_set);
- 
-   /* We cannot share RTX'es in pool entries.
-      Mark this piece of RTL as required for unsharing.  */
-@@ -5957,7 +5951,6 @@
-   const_desc_htab = htab_create_ggc (1009, const_desc_hash,
- 				     const_desc_eq, NULL);
- 
--  const_alias_set = new_alias_set ();
-   shared_constant_pool = create_constant_pool ();
- 
- #ifdef TEXT_SECTION_ASM_OP
-Index: gcc/ira.c
-===================================================================
---- a/src/gcc/ira.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/ira.c	(.../branches/gcc-4_9-branch)
-@@ -5347,7 +5347,18 @@
- 	      ira_allocno_iterator ai;
- 
- 	      FOR_EACH_ALLOCNO (a, ai)
--		ALLOCNO_REGNO (a) = REGNO (ALLOCNO_EMIT_DATA (a)->reg);
-+		{
-+		  int old_regno = ALLOCNO_REGNO (a);
-+		  int new_regno = REGNO (ALLOCNO_EMIT_DATA (a)->reg);
-+
-+		  ALLOCNO_REGNO (a) = new_regno;
-+
-+		  if (old_regno != new_regno)
-+		    setup_reg_classes (new_regno, reg_preferred_class (old_regno),
-+		                       reg_alternate_class (old_regno),
-+		                       reg_allocno_class (old_regno));
-+		}
-+
- 	    }
- 	  else
- 	    {
-Index: gcc/graphite-poly.c
-===================================================================
---- a/src/gcc/graphite-poly.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/graphite-poly.c	(.../branches/gcc-4_9-branch)
-@@ -30,7 +30,11 @@
- #include <isl/aff.h>
- #include <cloog/cloog.h>
- #include <cloog/isl/domain.h>
-+#ifdef HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE
-+#include <isl/deprecated/int.h>
-+#include <isl/deprecated/ilp_int.h>
- #endif
-+#endif
- 
- #include "system.h"
- #include "coretypes.h"
-Index: gcc/tree-vect-stmts.c
-===================================================================
---- a/src/gcc/tree-vect-stmts.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/tree-vect-stmts.c	(.../branches/gcc-4_9-branch)
-@@ -325,7 +325,8 @@
- 
-   /* changing memory.  */
-   if (gimple_code (stmt) != GIMPLE_PHI)
--    if (gimple_vdef (stmt))
-+    if (gimple_vdef (stmt)
-+	&& !gimple_clobber_p (stmt))
-       {
- 	if (dump_enabled_p ())
- 	  dump_printf_loc (MSG_NOTE, vect_location,
-@@ -3184,7 +3185,7 @@
-   set_vinfo_for_stmt (new_stmt, stmt_info);
-   set_vinfo_for_stmt (stmt, NULL);
-   STMT_VINFO_STMT (stmt_info) = new_stmt;
--  gsi_replace (gsi, new_stmt, false);
-+  gsi_replace (gsi, new_stmt, true);
-   unlink_stmt_vdef (stmt);
- 
-   return true;
-Index: gcc/graphite-sese-to-poly.c
-===================================================================
---- a/src/gcc/graphite-sese-to-poly.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/graphite-sese-to-poly.c	(.../branches/gcc-4_9-branch)
-@@ -29,7 +29,12 @@
- #include <cloog/cloog.h>
- #include <cloog/cloog.h>
- #include <cloog/isl/domain.h>
-+#ifdef HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE
-+#include <isl/deprecated/int.h>
-+#include <isl/deprecated/aff_int.h>
-+#include <isl/deprecated/constraint_int.h>
- #endif
-+#endif
- 
- #include "system.h"
- #include "coretypes.h"
-Index: gcc/combine.c
-===================================================================
---- a/src/gcc/combine.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/combine.c	(.../branches/gcc-4_9-branch)
-@@ -1529,8 +1529,8 @@
-       uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
- 
-       /* The mode and signedness of the argument as it is actually passed,
--         after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions.  */
--      mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
-+         see assign_parm_setup_reg in function.c.  */
-+      mode3 = promote_function_mode (TREE_TYPE (arg), mode1, &uns3,
- 				     TREE_TYPE (cfun->decl), 0);
- 
-       /* The mode of the register in which the argument is being passed.  */
-Index: gcc/config.gcc
-===================================================================
---- a/src/gcc/config.gcc	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config.gcc	(.../branches/gcc-4_9-branch)
-@@ -2662,7 +2662,7 @@
- 	;;
- sparc-*-rtems*)
- 	tm_file="${tm_file} dbxelf.h elfos.h sparc/sysv4.h sparc/sp-elf.h sparc/rtemself.h rtems.h newlib-stdint.h"
--	tmake_file="${tmake_file} sparc/t-sparc sparc/t-elf sparc/t-rtems"
-+	tmake_file="${tmake_file} sparc/t-sparc sparc/t-rtems"
- 	;;
- sparc-*-linux*)
- 	tm_file="${tm_file} dbxelf.h elfos.h sparc/sysv4.h gnu-user.h linux.h glibc-stdint.h sparc/tso.h"
-@@ -3205,6 +3205,9 @@
- 	*-leon[3-9]*)
- 	  with_cpu=leon3
- 	  ;;
-+	*-leon[3-9]v7*)
-+	  with_cpu=leon3v7
-+	  ;;
- 	*)
- 	  with_cpu="`echo ${target} | sed 's/-.*$//'`"
- 	  ;;
-@@ -3993,7 +3996,7 @@
- 			case ${val} in
- 			"" | sparc | sparcv9 | sparc64 \
- 			| v7 | cypress \
--			| v8 | supersparc | hypersparc | leon | leon3 \
-+			| v8 | supersparc | hypersparc | leon | leon3 | leon3v7 \
- 			| sparclite | f930 | f934 | sparclite86x \
- 			| sparclet | tsc701 \
- 			| v9 | ultrasparc | ultrasparc3 | niagara | niagara2 \
-Index: gcc/ree.c
-===================================================================
---- a/src/gcc/ree.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/ree.c	(.../branches/gcc-4_9-branch)
-@@ -261,6 +261,50 @@
- 
- static int max_insn_uid;
- 
-+/* Update or remove REG_EQUAL or REG_EQUIV notes for INSN.  */
-+
-+static bool
-+update_reg_equal_equiv_notes (rtx insn, enum machine_mode new_mode,
-+			      enum machine_mode old_mode, enum rtx_code code)
-+{
-+  rtx *loc = &REG_NOTES (insn);
-+  while (*loc)
-+    {
-+      enum reg_note kind = REG_NOTE_KIND (*loc);
-+      if (kind == REG_EQUAL || kind == REG_EQUIV)
-+	{
-+	  rtx orig_src = XEXP (*loc, 0);
-+	  /* Update equivalency constants.  Recall that RTL constants are
-+	     sign-extended.  */
-+	  if (GET_CODE (orig_src) == CONST_INT
-+	      && HOST_BITS_PER_WIDE_INT >= GET_MODE_BITSIZE (new_mode))
-+	    {
-+	      if (INTVAL (orig_src) >= 0 || code == SIGN_EXTEND)
-+		/* Nothing needed.  */;
-+	      else
-+		{
-+		  /* Zero-extend the negative constant by masking out the
-+		     bits outside the source mode.  */
-+		  rtx new_const_int
-+		    = gen_int_mode (INTVAL (orig_src)
-+				    & GET_MODE_MASK (old_mode),
-+				    new_mode);
-+		  if (!validate_change (insn, &XEXP (*loc, 0),
-+					new_const_int, true))
-+		    return false;
-+		}
-+	      loc = &XEXP (*loc, 1);
-+	    }
-+	  /* Drop all other notes, they assume a wrong mode.  */
-+	  else if (!validate_change (insn, loc, XEXP (*loc, 1), true))
-+	    return false;
-+	}
-+      else
-+	loc = &XEXP (*loc, 1);
-+    }
-+  return true;
-+}
-+
- /* Given a insn (CURR_INSN), an extension candidate for removal (CAND)
-    and a pointer to the SET rtx (ORIG_SET) that needs to be modified,
-    this code modifies the SET rtx to a new SET rtx that extends the
-@@ -282,6 +326,7 @@
- combine_set_extension (ext_cand *cand, rtx curr_insn, rtx *orig_set)
- {
-   rtx orig_src = SET_SRC (*orig_set);
-+  enum machine_mode orig_mode = GET_MODE (SET_DEST (*orig_set));
-   rtx new_set;
-   rtx cand_pat = PATTERN (cand->insn);
- 
-@@ -318,9 +363,8 @@
- 	{
- 	  /* Zero-extend the negative constant by masking out the bits outside
- 	     the source mode.  */
--	  enum machine_mode src_mode = GET_MODE (SET_DEST (*orig_set));
- 	  rtx new_const_int
--	    = gen_int_mode (INTVAL (orig_src) & GET_MODE_MASK (src_mode),
-+	    = gen_int_mode (INTVAL (orig_src) & GET_MODE_MASK (orig_mode),
- 			    GET_MODE (new_reg));
- 	  new_set = gen_rtx_SET (VOIDmode, new_reg, new_const_int);
- 	}
-@@ -359,7 +403,9 @@
- 
-   /* This change is a part of a group of changes.  Hence,
-      validate_change will not try to commit the change.  */
--  if (validate_change (curr_insn, orig_set, new_set, true))
-+  if (validate_change (curr_insn, orig_set, new_set, true)
-+      && update_reg_equal_equiv_notes (curr_insn, cand->mode, orig_mode,
-+				       cand->code))
-     {
-       if (dump_file)
-         {
-@@ -409,7 +455,9 @@
-   ifexpr = gen_rtx_IF_THEN_ELSE (cand->mode, cond, map_srcreg, map_srcreg2);
-   new_set = gen_rtx_SET (VOIDmode, map_dstreg, ifexpr);
- 
--  if (validate_change (def_insn, &PATTERN (def_insn), new_set, true))
-+  if (validate_change (def_insn, &PATTERN (def_insn), new_set, true)
-+      && update_reg_equal_equiv_notes (def_insn, cand->mode, GET_MODE (dstreg),
-+				       cand->code))
-     {
-       if (dump_file)
-         {
-@@ -719,6 +767,17 @@
-        != REGNO (get_extended_src_reg (SET_SRC (PATTERN (cand->insn)))));
-   if (copy_needed)
-     {
-+      /* Considering transformation of
-+	 (set (reg1) (expression))
-+	 ...
-+	 (set (reg2) (any_extend (reg1)))
-+
-+	 into
-+
-+	 (set (reg2) (any_extend (expression)))
-+	 (set (reg1) (reg2))
-+	 ...  */
-+
-       /* In theory we could handle more than one reaching def, it
- 	 just makes the code to update the insn stream more complex.  */
-       if (state->defs_list.length () != 1)
-@@ -734,18 +793,6 @@
-       if (state->modified[INSN_UID (cand->insn)].kind != EXT_MODIFIED_NONE)
- 	return false;
- 
--      /* Transformation of
--	 (set (reg1) (expression))
--	 (set (reg2) (any_extend (reg1)))
--	 into
--	 (set (reg2) (any_extend (expression)))
--	 (set (reg1) (reg2))
--	 is only valid for scalar integral modes, as it relies on the low
--	 subreg of reg1 to have the value of (expression), which is not true
--	 e.g. for vector modes.  */
--      if (!SCALAR_INT_MODE_P (GET_MODE (SET_DEST (PATTERN (cand->insn)))))
--	return false;
--
-       /* There's only one reaching def.  */
-       rtx def_insn = state->defs_list[0];
- 
-@@ -954,6 +1001,7 @@
- 	 different extension.  FIXME: this obviously can be improved.  */
-       for (def = defs; def; def = def->next)
- 	if ((idx = def_map[INSN_UID (DF_REF_INSN (def->ref))])
-+	    && idx != -1U
- 	    && (cand = &(*insn_list)[idx - 1])
- 	    && cand->code != code)
- 	  {
-@@ -965,7 +1013,58 @@
- 	      }
- 	    return;
- 	  }
-+	/* For vector mode extensions, ensure that all uses of the
-+	   XEXP (src, 0) register are the same extension (both code
-+	   and to which mode), as unlike integral extensions lowpart
-+	   subreg of the sign/zero extended register are not equal
-+	   to the original register, so we have to change all uses or
-+	   none.  */
-+	else if (VECTOR_MODE_P (GET_MODE (XEXP (src, 0))))
-+	  {
-+	    if (idx == 0)
-+	      {
-+		struct df_link *ref_chain, *ref_link;
- 
-+		ref_chain = DF_REF_CHAIN (def->ref);
-+		for (ref_link = ref_chain; ref_link; ref_link = ref_link->next)
-+		  {
-+		    if (ref_link->ref == NULL
-+			|| DF_REF_INSN_INFO (ref_link->ref) == NULL)
-+		      {
-+			idx = -1U;
-+			break;
-+		      }
-+		    rtx use_insn = DF_REF_INSN (ref_link->ref);
-+		    const_rtx use_set;
-+		    if (use_insn == insn || DEBUG_INSN_P (use_insn))
-+		      continue;
-+		    if (!(use_set = single_set (use_insn))
-+			|| !REG_P (SET_DEST (use_set))
-+			|| GET_MODE (SET_DEST (use_set)) != GET_MODE (dest)
-+			|| GET_CODE (SET_SRC (use_set)) != code
-+			|| !rtx_equal_p (XEXP (SET_SRC (use_set), 0),
-+					 XEXP (src, 0)))
-+		      {
-+			idx = -1U;
-+			break;
-+		      }
-+		  }
-+		if (idx == -1U)
-+		  def_map[INSN_UID (DF_REF_INSN (def->ref))] = idx;
-+	      }
-+	    if (idx == -1U)
-+	      {
-+		if (dump_file)
-+		  {
-+		    fprintf (dump_file, "Cannot eliminate extension:\n");
-+		    print_rtl_single (dump_file, insn);
-+		    fprintf (dump_file,
-+			     " because some vector uses aren't extension\n");
-+		  }
-+		return;
-+	      }
-+	  }
-+
-       /* Then add the candidate to the list and insert the reaching definitions
-          into the definition map.  */
-       ext_cand e = {expr, code, mode, insn};
-Index: gcc/tree-ssa-reassoc.c
-===================================================================
---- a/src/gcc/tree-ssa-reassoc.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/tree-ssa-reassoc.c	(.../branches/gcc-4_9-branch)
-@@ -2047,7 +2047,7 @@
- 	      else
- 		return -1;
- 	    }
--	  else if (p->high != NULL_TREE)
-+	  else if (q->high != NULL_TREE)
- 	    return 1;
- 	  /* If both ranges are the same, sort below by ascending idx.  */
- 	}
-@@ -3692,6 +3692,9 @@
-   switch (DECL_FUNCTION_CODE (fndecl))
-     {
-     CASE_FLT_FN (BUILT_IN_POW):
-+      if (flag_errno_math)
-+	return false;
-+
-       *base = gimple_call_arg (stmt, 0);
-       arg1 = gimple_call_arg (stmt, 1);
- 
-Index: gcc/config/alpha/alpha.md
-===================================================================
---- a/src/gcc/config/alpha/alpha.md	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/alpha/alpha.md	(.../branches/gcc-4_9-branch)
-@@ -5984,16 +5984,38 @@
-   [(set_attr "type" "jsr")
-    (set_attr "length" "*,*,8")])
- 
--(define_insn_and_split "call_value_osf_tlsgd"
-+(define_int_iterator TLS_CALL
-+	[UNSPEC_TLSGD_CALL
-+	 UNSPEC_TLSLDM_CALL])
-+
-+(define_int_attr tls
-+	[(UNSPEC_TLSGD_CALL "tlsgd")
-+	 (UNSPEC_TLSLDM_CALL "tlsldm")])
-+
-+(define_insn "call_value_osf_<tls>"
-   [(set (match_operand 0)
- 	(call (mem:DI (match_operand:DI 1 "symbolic_operand"))
- 	      (const_int 0)))
--   (unspec [(match_operand:DI 2 "const_int_operand")] UNSPEC_TLSGD_CALL)
-+   (unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL)
-    (use (reg:DI 29))
-    (clobber (reg:DI 26))]
-   "HAVE_AS_TLS"
--  "#"
--  "&& reload_completed"
-+  "ldq $27,%1($29)\t\t!literal!%2\;jsr $26,($27),%1\t\t!lituse_<tls>!%2\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
-+  [(set_attr "type" "jsr")
-+   (set_attr "length" "16")])
-+
-+;; We must use peep2 instead of a split because we need accurate life
-+;; information for $gp.
-+(define_peephole2
-+  [(parallel
-+    [(set (match_operand 0)
-+	  (call (mem:DI (match_operand:DI 1 "symbolic_operand"))
-+		(const_int 0)))
-+     (unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL)
-+     (use (reg:DI 29))
-+     (clobber (reg:DI 26))])]
-+  "HAVE_AS_TLS && reload_completed
-+   && peep2_regno_dead_p (1, 29)"
-   [(set (match_dup 3)
- 	(unspec:DI [(match_dup 5)
- 		    (match_dup 1)
-@@ -6001,10 +6023,9 @@
-    (parallel [(set (match_dup 0)
- 		   (call (mem:DI (match_dup 3))
- 			 (const_int 0)))
--	      (set (match_dup 5)
--		   (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP1))
-+	      (use (match_dup 5))
- 	      (use (match_dup 1))
--	      (use (unspec [(match_dup 2)] UNSPEC_TLSGD_CALL))
-+	      (use (unspec [(match_dup 2)] TLS_CALL))
- 	      (clobber (reg:DI 26))])
-    (set (match_dup 5)
- 	(unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))]
-@@ -6012,19 +6033,18 @@
-   operands[3] = gen_rtx_REG (Pmode, 27);
-   operands[4] = GEN_INT (alpha_next_sequence_number++);
-   operands[5] = pic_offset_table_rtx;
--}
--  [(set_attr "type" "multi")])
-+})
- 
--(define_insn_and_split "call_value_osf_tlsldm"
--  [(set (match_operand 0)
--	(call (mem:DI (match_operand:DI 1 "symbolic_operand"))
--	      (const_int 0)))
--   (unspec [(match_operand:DI 2 "const_int_operand")] UNSPEC_TLSLDM_CALL)
--   (use (reg:DI 29))
--   (clobber (reg:DI 26))]
--  "HAVE_AS_TLS"
--  "#"
--  "&& reload_completed"
-+(define_peephole2
-+  [(parallel
-+    [(set (match_operand 0)
-+	  (call (mem:DI (match_operand:DI 1 "symbolic_operand"))
-+		(const_int 0)))
-+     (unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL)
-+     (use (reg:DI 29))
-+     (clobber (reg:DI 26))])]
-+  "HAVE_AS_TLS && reload_completed
-+   && !peep2_regno_dead_p (1, 29)"
-   [(set (match_dup 3)
- 	(unspec:DI [(match_dup 5)
- 		    (match_dup 1)
-@@ -6035,7 +6055,7 @@
- 	      (set (match_dup 5)
- 		   (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP1))
- 	      (use (match_dup 1))
--	      (use (unspec [(match_dup 2)] UNSPEC_TLSLDM_CALL))
-+	      (use (unspec [(match_dup 2)] TLS_CALL))
- 	      (clobber (reg:DI 26))])
-    (set (match_dup 5)
- 	(unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))]
-@@ -6043,8 +6063,7 @@
-   operands[3] = gen_rtx_REG (Pmode, 27);
-   operands[4] = GEN_INT (alpha_next_sequence_number++);
-   operands[5] = pic_offset_table_rtx;
--}
--  [(set_attr "type" "multi")])
-+})
- 
- (define_insn "*call_value_osf_1"
-   [(set (match_operand 0)
-Index: gcc/config/sparc/t-rtems
-===================================================================
---- a/src/gcc/config/sparc/t-rtems	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/sparc/t-rtems	(.../branches/gcc-4_9-branch)
-@@ -17,6 +17,15 @@
- # <http://www.gnu.org/licenses/>.
- #
- 
--MULTILIB_OPTIONS = msoft-float mcpu=v8/mcpu=leon3
--MULTILIB_DIRNAMES = soft v8 leon3
-+MULTILIB_OPTIONS = msoft-float mcpu=v8/mcpu=leon3/mcpu=leon3v7 muser-mode
-+MULTILIB_DIRNAMES = soft v8 leon3 leon3v7 user-mode
- MULTILIB_MATCHES = msoft-float=mno-fpu
-+
-+MULTILIB_EXCEPTIONS = muser-mode
-+MULTILIB_EXCEPTIONS += mcpu=leon3
-+MULTILIB_EXCEPTIONS += mcpu=leon3v7
-+MULTILIB_EXCEPTIONS += msoft-float/mcpu=leon3
-+MULTILIB_EXCEPTIONS += msoft-float/mcpu=leon3v7
-+MULTILIB_EXCEPTIONS += msoft-float/muser-mode
-+MULTILIB_EXCEPTIONS += msoft-float/mcpu=v8/muser-mode
-+MULTILIB_EXCEPTIONS += mcpu=v8/muser-mode
-Index: gcc/config/sparc/sparc.md
-===================================================================
---- a/src/gcc/config/sparc/sparc.md	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/sparc/sparc.md	(.../branches/gcc-4_9-branch)
-@@ -221,6 +221,7 @@
-    hypersparc,
-    leon,
-    leon3,
-+   leon3v7,
-    sparclite,
-    f930,
-    f934,
-Index: gcc/config/sparc/sparc.opt
-===================================================================
---- a/src/gcc/config/sparc/sparc.opt	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/sparc/sparc.opt	(.../branches/gcc-4_9-branch)
-@@ -153,6 +153,9 @@
- Enum(sparc_processor_type) String(leon3) Value(PROCESSOR_LEON3)
- 
- EnumValue
-+Enum(sparc_processor_type) String(leon3v7) Value(PROCESSOR_LEON3V7)
-+
-+EnumValue
- Enum(sparc_processor_type) String(sparclite) Value(PROCESSOR_SPARCLITE)
- 
- EnumValue
-Index: gcc/config/sparc/sparc-opts.h
-===================================================================
---- a/src/gcc/config/sparc/sparc-opts.h	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/sparc/sparc-opts.h	(.../branches/gcc-4_9-branch)
-@@ -31,6 +31,7 @@
-   PROCESSOR_HYPERSPARC,
-   PROCESSOR_LEON,
-   PROCESSOR_LEON3,
-+  PROCESSOR_LEON3V7,
-   PROCESSOR_SPARCLITE,
-   PROCESSOR_F930,
-   PROCESSOR_F934,
-Index: gcc/config/sparc/sparc.c
-===================================================================
---- a/src/gcc/config/sparc/sparc.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/sparc/sparc.c	(.../branches/gcc-4_9-branch)
-@@ -1246,6 +1246,7 @@
-     { TARGET_CPU_hypersparc, PROCESSOR_HYPERSPARC },
-     { TARGET_CPU_leon, PROCESSOR_LEON },
-     { TARGET_CPU_leon3, PROCESSOR_LEON3 },
-+    { TARGET_CPU_leon3v7, PROCESSOR_LEON3V7 },
-     { TARGET_CPU_sparclite, PROCESSOR_F930 },
-     { TARGET_CPU_sparclite86x, PROCESSOR_SPARCLITE86X },
-     { TARGET_CPU_sparclet, PROCESSOR_TSC701 },
-@@ -1274,6 +1275,7 @@
-     { "hypersparc",	MASK_ISA, MASK_V8|MASK_FPU },
-     { "leon",		MASK_ISA, MASK_V8|MASK_LEON|MASK_FPU },
-     { "leon3",		MASK_ISA, MASK_V8|MASK_LEON3|MASK_FPU },
-+    { "leon3v7",	MASK_ISA, MASK_LEON3|MASK_FPU },
-     { "sparclite",	MASK_ISA, MASK_SPARCLITE },
-     /* The Fujitsu MB86930 is the original sparclite chip, with no FPU.  */
-     { "f930",		MASK_ISA|MASK_FPU, MASK_SPARCLITE },
-@@ -1526,6 +1528,7 @@
-       sparc_costs = &leon_costs;
-       break;
-     case PROCESSOR_LEON3:
-+    case PROCESSOR_LEON3V7:
-       sparc_costs = &leon3_costs;
-       break;
-     case PROCESSOR_SPARCLET:
-@@ -6801,28 +6804,30 @@
- }
- 
- /* Used by function_arg and sparc_function_value_1 to implement the conventions
--   for passing and returning large (BLKmode) vectors.
-+   for passing and returning BLKmode vectors.
-    Return an expression valid as a return value for the FUNCTION_ARG
-    and TARGET_FUNCTION_VALUE.
- 
--   SIZE is the size in bytes of the vector (at least 8 bytes).
-+   SIZE is the size in bytes of the vector.
-    REGNO is the FP hard register the vector will be passed in.  */
- 
- static rtx
- function_arg_vector_value (int size, int regno)
- {
--  int i, nregs = size / 8;
--  rtx regs;
-+  const int nregs = MAX (1, size / 8);
-+  rtx regs = gen_rtx_PARALLEL (BLKmode, rtvec_alloc (nregs));
- 
--  regs = gen_rtx_PARALLEL (BLKmode, rtvec_alloc (nregs));
--
--  for (i = 0; i < nregs; i++)
--    {
-+  if (size < 8)
-+    XVECEXP (regs, 0, 0)
-+      = gen_rtx_EXPR_LIST (VOIDmode,
-+			   gen_rtx_REG (SImode, regno),
-+			   const0_rtx);
-+  else
-+    for (int i = 0; i < nregs; i++)
-       XVECEXP (regs, 0, i)
- 	= gen_rtx_EXPR_LIST (VOIDmode,
- 			     gen_rtx_REG (DImode, regno + 2*i),
- 			     GEN_INT (i*8));
--    }
- 
-   return regs;
- }
-@@ -6868,10 +6873,9 @@
- 		  || (TARGET_ARCH64 && size <= 16));
- 
-       if (mode == BLKmode)
--	return function_arg_vector_value (size,
--					  SPARC_FP_ARG_FIRST + 2*slotno);
--      else
--	mclass = MODE_FLOAT;
-+	return function_arg_vector_value (size, SPARC_FP_ARG_FIRST + 2*slotno);
-+
-+      mclass = MODE_FLOAT;
-     }
- 
-   if (TARGET_ARCH32)
-@@ -7315,10 +7319,9 @@
- 		  || (TARGET_ARCH64 && size <= 32));
- 
-       if (mode == BLKmode)
--	return function_arg_vector_value (size,
--					  SPARC_FP_ARG_FIRST);
--      else
--	mclass = MODE_FLOAT;
-+	return function_arg_vector_value (size, SPARC_FP_ARG_FIRST);
-+
-+      mclass = MODE_FLOAT;
-     }
- 
-   if (TARGET_ARCH64 && type)
-Index: gcc/config/sparc/leon.md
-===================================================================
---- a/src/gcc/config/sparc/leon.md	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/sparc/leon.md	(.../branches/gcc-4_9-branch)
-@@ -29,11 +29,11 @@
- 
- ;; Use a double reservation to work around the load pipeline hazard on UT699.
- (define_insn_reservation "leon3_load" 1
--  (and (eq_attr "cpu" "leon3") (eq_attr "type" "load,sload"))
-+  (and (eq_attr "cpu" "leon3,leon3v7") (eq_attr "type" "load,sload"))
-   "leon_memory*2")
- 
- (define_insn_reservation "leon_store" 2
--  (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "store"))
-+  (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "store"))
-   "leon_memory*2")
- 
- ;; This describes Gaisler Research's FPU
-@@ -44,21 +44,21 @@
- (define_cpu_unit "grfpu_ds" "grfpu")
- 
- (define_insn_reservation "leon_fp_alu" 4
--  (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fp,fpcmp,fpmul"))
-+  (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "fp,fpcmp,fpmul"))
-   "grfpu_alu, nothing*3")
- 
- (define_insn_reservation "leon_fp_divs" 16
--  (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpdivs"))
-+  (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "fpdivs"))
-   "grfpu_ds*14, nothing*2")
- 
- (define_insn_reservation "leon_fp_divd" 17
--  (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpdivd"))
-+  (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "fpdivd"))
-   "grfpu_ds*15, nothing*2")
- 
- (define_insn_reservation "leon_fp_sqrts" 24
--  (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpsqrts"))
-+  (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "fpsqrts"))
-   "grfpu_ds*22, nothing*2")
- 
- (define_insn_reservation "leon_fp_sqrtd" 25
--  (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpsqrtd"))
-+  (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "fpsqrtd"))
-   "grfpu_ds*23, nothing*2")
-Index: gcc/config/sparc/sparc.h
-===================================================================
---- a/src/gcc/config/sparc/sparc.h	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/sparc/sparc.h	(.../branches/gcc-4_9-branch)
-@@ -137,21 +137,22 @@
- #define TARGET_CPU_hypersparc	3
- #define TARGET_CPU_leon		4
- #define TARGET_CPU_leon3	5
--#define TARGET_CPU_sparclite	6
--#define TARGET_CPU_f930		6       /* alias */
--#define TARGET_CPU_f934		6       /* alias */
--#define TARGET_CPU_sparclite86x	7
--#define TARGET_CPU_sparclet	8
--#define TARGET_CPU_tsc701	8       /* alias */
--#define TARGET_CPU_v9		9	/* generic v9 implementation */
--#define TARGET_CPU_sparcv9	9	/* alias */
--#define TARGET_CPU_sparc64	9	/* alias */
--#define TARGET_CPU_ultrasparc	10
--#define TARGET_CPU_ultrasparc3	11
--#define TARGET_CPU_niagara	12
--#define TARGET_CPU_niagara2	13
--#define TARGET_CPU_niagara3	14
--#define TARGET_CPU_niagara4	15
-+#define TARGET_CPU_leon3v7	6
-+#define TARGET_CPU_sparclite	7
-+#define TARGET_CPU_f930		7       /* alias */
-+#define TARGET_CPU_f934		7       /* alias */
-+#define TARGET_CPU_sparclite86x	8
-+#define TARGET_CPU_sparclet	9
-+#define TARGET_CPU_tsc701	9       /* alias */
-+#define TARGET_CPU_v9		10	/* generic v9 implementation */
-+#define TARGET_CPU_sparcv9	10	/* alias */
-+#define TARGET_CPU_sparc64	10	/* alias */
-+#define TARGET_CPU_ultrasparc	11
-+#define TARGET_CPU_ultrasparc3	12
-+#define TARGET_CPU_niagara	13
-+#define TARGET_CPU_niagara2	14
-+#define TARGET_CPU_niagara3	15
-+#define TARGET_CPU_niagara4	16
- 
- #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
-  || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
-@@ -239,8 +240,13 @@
- #define ASM_CPU32_DEFAULT_SPEC AS_LEON_FLAG
- #endif
- 
-+#if TARGET_CPU_DEFAULT == TARGET_CPU_leon3v7
-+#define CPP_CPU32_DEFAULT_SPEC "-D__leon__"
-+#define ASM_CPU32_DEFAULT_SPEC AS_LEONV7_FLAG
- #endif
- 
-+#endif
-+
- #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC)
-  #error Unrecognized value in TARGET_CPU_DEFAULT.
- #endif
-@@ -285,6 +291,7 @@
- %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \
- %{mcpu=leon:-D__leon__ -D__sparc_v8__} \
- %{mcpu=leon3:-D__leon__ -D__sparc_v8__} \
-+%{mcpu=leon3v7:-D__leon__} \
- %{mcpu=v9:-D__sparc_v9__} \
- %{mcpu=ultrasparc:-D__sparc_v9__} \
- %{mcpu=ultrasparc3:-D__sparc_v9__} \
-@@ -334,6 +341,7 @@
- %{mcpu=hypersparc:-Av8} \
- %{mcpu=leon:" AS_LEON_FLAG "} \
- %{mcpu=leon3:" AS_LEON_FLAG "} \
-+%{mcpu=leon3v7:" AS_LEONV7_FLAG "} \
- %{mv8plus:-Av8plus} \
- %{mcpu=v9:-Av9} \
- %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
-@@ -1760,8 +1768,10 @@
- 
- #ifdef HAVE_AS_LEON
- #define AS_LEON_FLAG "-Aleon"
-+#define AS_LEONV7_FLAG "-Aleon"
- #else
- #define AS_LEON_FLAG "-Av8"
-+#define AS_LEONV7_FLAG "-Av7"
- #endif
- 
- /* We use gcc _mcount for profiling.  */
-Index: gcc/config/i386/mmx.md
-===================================================================
---- a/src/gcc/config/i386/mmx.md	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/i386/mmx.md	(.../branches/gcc-4_9-branch)
-@@ -600,20 +600,25 @@
- ;; Avoid combining registers from different units in a single alternative,
- ;; see comment above inline_secondary_memory_needed function in i386.c
- (define_insn "*vec_extractv2sf_1"
--  [(set (match_operand:SF 0 "nonimmediate_operand"     "=y,x,y,x,f,r")
-+  [(set (match_operand:SF 0 "nonimmediate_operand"     "=y,x,x,y,x,f,r")
- 	(vec_select:SF
--	  (match_operand:V2SF 1 "nonimmediate_operand" " 0,0,o,o,o,o")
-+	  (match_operand:V2SF 1 "nonimmediate_operand" " 0,x,x,o,o,o,o")
- 	  (parallel [(const_int 1)])))]
-   "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
-   "@
-    punpckhdq\t%0, %0
--   unpckhps\t%0, %0
-+   %vmovshdup\t{%1, %0|%0, %1}
-+   shufps\t{$0xe5, %1, %0|%0, %1, 0xe5}
-    #
-    #
-    #
-    #"
--  [(set_attr "type" "mmxcvt,sselog1,mmxmov,ssemov,fmov,imov")
--   (set_attr "mode" "DI,V4SF,SF,SF,SF,SF")])
-+  [(set_attr "isa" "*,sse3,noavx,*,*,*,*")
-+   (set_attr "type" "mmxcvt,sse,sseshuf1,mmxmov,ssemov,fmov,imov")
-+   (set_attr "length_immediate" "*,*,1,*,*,*,*")
-+   (set_attr "prefix_rep" "*,1,*,*,*,*,*")
-+   (set_attr "prefix" "orig,maybe_vex,orig,orig,orig,orig,orig")
-+   (set_attr "mode" "DI,V4SF,V4SF,SF,SF,SF,SF")])
- 
- (define_split
-   [(set (match_operand:SF 0 "register_operand")
-@@ -1288,26 +1293,23 @@
- ;; Avoid combining registers from different units in a single alternative,
- ;; see comment above inline_secondary_memory_needed function in i386.c
- (define_insn "*vec_extractv2si_1"
--  [(set (match_operand:SI 0 "nonimmediate_operand"     "=y,x,x,x,y,x,r")
-+  [(set (match_operand:SI 0 "nonimmediate_operand"     "=y,x,x,y,x,r")
- 	(vec_select:SI
--	  (match_operand:V2SI 1 "nonimmediate_operand" " 0,0,x,0,o,o,o")
-+	  (match_operand:V2SI 1 "nonimmediate_operand" " 0,x,x,o,o,o")
- 	  (parallel [(const_int 1)])))]
-   "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
-   "@
-    punpckhdq\t%0, %0
--   punpckhdq\t%0, %0
--   pshufd\t{$85, %1, %0|%0, %1, 85}
--   unpckhps\t%0, %0
-+   %vpshufd\t{$0xe5, %1, %0|%0, %1, 0xe5}
-+   shufps\t{$0xe5, %1, %0|%0, %1, 0xe5}
-    #
-    #
-    #"
--  [(set (attr "isa")
--     (if_then_else (eq_attr "alternative" "1,2")
--       (const_string "sse2")
--       (const_string "*")))
--   (set_attr "type" "mmxcvt,sselog1,sselog1,sselog1,mmxmov,ssemov,imov")
--   (set_attr "length_immediate" "*,*,1,*,*,*,*")
--   (set_attr "mode" "DI,TI,TI,V4SF,SI,SI,SI")])
-+  [(set_attr "isa" "*,sse2,noavx,*,*,*")
-+   (set_attr "type" "mmxcvt,sseshuf1,sseshuf1,mmxmov,ssemov,imov")
-+   (set_attr "length_immediate" "*,1,1,*,*,*")
-+   (set_attr "prefix" "orig,maybe_vex,orig,orig,orig,orig")
-+   (set_attr "mode" "DI,TI,V4SF,SI,SI,SI")])
- 
- (define_split
-   [(set (match_operand:SI 0 "register_operand")
-Index: gcc/config/i386/i386.c
-===================================================================
---- a/src/gcc/config/i386/i386.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/i386/i386.c	(.../branches/gcc-4_9-branch)
-@@ -5006,6 +5006,10 @@
-   if (TREE_CODE (exp) == FUNCTION_DECL)
-     return false;
- 
-+  /* Automatic variables are never large data.  */
-+  if (TREE_CODE (exp) == VAR_DECL && !is_global_var (exp))
-+    return false;
-+
-   if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
-     {
-       const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
-@@ -5036,8 +5040,7 @@
- x86_64_elf_select_section (tree decl, int reloc,
- 			   unsigned HOST_WIDE_INT align)
- {
--  if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
--      && ix86_in_large_data_p (decl))
-+  if (ix86_in_large_data_p (decl))
-     {
-       const char *sname = NULL;
-       unsigned int flags = SECTION_WRITE;
-@@ -5123,8 +5126,7 @@
- static void ATTRIBUTE_UNUSED
- x86_64_elf_unique_section (tree decl, int reloc)
- {
--  if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
--      && ix86_in_large_data_p (decl))
-+  if (ix86_in_large_data_p (decl))
-     {
-       const char *prefix = NULL;
-       /* We only need to use .gnu.linkonce if we don't have COMDAT groups.  */
-@@ -5193,7 +5195,7 @@
- {
-   if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
-       && size > (unsigned int)ix86_section_threshold)
--    fputs (".largecomm\t", file);
-+    fputs ("\t.largecomm\t", file);
-   else
-     fputs (COMMON_ASM_OP, file);
-   assemble_name (file, name);
-@@ -5972,7 +5974,18 @@
-       if (abi == SYSV_ABI)
- 	{
- 	  if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (fntype)))
--	    abi = MS_ABI;
-+	    {
-+	      if (TARGET_X32)
-+		{
-+		  static bool warned = false;
-+		  if (!warned)
-+		    {
-+		      error ("X32 does not support ms_abi attribute");
-+		      warned = true;
-+		    }
-+		}
-+	      abi = MS_ABI;
-+	    }
- 	}
-       else if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (fntype)))
- 	abi = SYSV_ABI;
-@@ -11063,6 +11076,10 @@
- 	      if (sp_is_cfa_reg)
- 		m->fs.cfa_offset += UNITS_PER_WORD;
- 	      RTX_FRAME_RELATED_P (insn) = 1;
-+	      add_reg_note (insn, REG_FRAME_RELATED_EXPR,
-+			    gen_rtx_SET (VOIDmode, stack_pointer_rtx,
-+					 plus_constant (Pmode, stack_pointer_rtx,
-+							-UNITS_PER_WORD)));
- 	    }
- 	}
- 
-@@ -11076,6 +11093,10 @@
- 	      if (sp_is_cfa_reg)
- 		m->fs.cfa_offset += UNITS_PER_WORD;
- 	      RTX_FRAME_RELATED_P (insn) = 1;
-+	      add_reg_note (insn, REG_FRAME_RELATED_EXPR,
-+			    gen_rtx_SET (VOIDmode, stack_pointer_rtx,
-+					 plus_constant (Pmode, stack_pointer_rtx,
-+							-UNITS_PER_WORD)));
- 	    }
- 	}
- 
-@@ -14503,7 +14524,7 @@
-       if (mode == CCmode)
- 	suffix = "b";
-       else if (mode == CCCmode)
--	suffix = "c";
-+	suffix = fp ? "b" : "c";
-       else
- 	gcc_unreachable ();
-       break;
-@@ -14526,9 +14547,9 @@
-       break;
-     case GEU:
-       if (mode == CCmode)
--	suffix = fp ? "nb" : "ae";
-+	suffix = "nb";
-       else if (mode == CCCmode)
--	suffix = "nc";
-+	suffix = fp ? "nb" : "nc";
-       else
- 	gcc_unreachable ();
-       break;
-@@ -23890,7 +23911,8 @@
- 		      *noalign = alg_noalign;
- 		      return alg;
- 		    }
--		  break;
-+		  else if (!any_alg_usable_p)
-+		    break;
- 		}
- 	      else if (alg_usable_p (candidate, memset))
- 		{
-@@ -23928,9 +23950,10 @@
-       alg = decide_alg (count, max / 2, min_size, max_size, memset,
- 			zero_memset, dynamic_check, noalign);
-       gcc_assert (*dynamic_check == -1);
--      gcc_assert (alg != libcall);
-       if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
- 	*dynamic_check = max;
-+      else
-+	gcc_assert (alg != libcall);
-       return alg;
-     }
-   return (alg_usable_p (algs->unknown_size, memset)
-@@ -41076,9 +41099,7 @@
- {
-   default_encode_section_info (decl, rtl, first);
- 
--  if (TREE_CODE (decl) == VAR_DECL
--      && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
--      && ix86_in_large_data_p (decl))
-+  if (ix86_in_large_data_p (decl))
-     SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
- }
- 
-Index: gcc/config/rx/rx.h
-===================================================================
---- a/src/gcc/config/rx/rx.h	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/rx/rx.h	(.../branches/gcc-4_9-branch)
-@@ -433,9 +433,9 @@
- /* Compute the alignment needed for label X in various situations.
-    If the user has specified an alignment then honour that, otherwise
-    use rx_align_for_label.  */
--#define JUMP_ALIGN(x)				(align_jumps ? align_jumps : rx_align_for_label (x, 0))
--#define LABEL_ALIGN(x)				(align_labels ? align_labels : rx_align_for_label (x, 3))
--#define LOOP_ALIGN(x)				(align_loops ? align_loops : rx_align_for_label (x, 2))
-+#define JUMP_ALIGN(x)				(align_jumps > 1 ? align_jumps_log : rx_align_for_label (x, 0))
-+#define LABEL_ALIGN(x)				(align_labels > 1 ? align_labels_log : rx_align_for_label (x, 3))
-+#define LOOP_ALIGN(x)				(align_loops > 1 ? align_loops_log : rx_align_for_label (x, 2))
- #define LABEL_ALIGN_AFTER_BARRIER(x)		rx_align_for_label (x, 0)
- 
- #define ASM_OUTPUT_MAX_SKIP_ALIGN(STREAM, LOG, MAX_SKIP)	\
-Index: gcc/config/rx/rx.c
-===================================================================
---- a/src/gcc/config/rx/rx.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/rx/rx.c	(.../branches/gcc-4_9-branch)
-@@ -733,7 +733,7 @@
-       break;
- 
-     case 'R':
--      gcc_assert (GET_MODE_SIZE (GET_MODE (op)) < 4);
-+      gcc_assert (GET_MODE_SIZE (GET_MODE (op)) <= 4);
-       unsigned_load = true;
-       /* Fall through.  */
-     case 'Q':
-Index: gcc/config/sh/sh.c
-===================================================================
---- a/src/gcc/config/sh/sh.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/sh/sh.c	(.../branches/gcc-4_9-branch)
-@@ -2957,7 +2957,7 @@
- struct ashl_lshr_sequence
- {
-   char insn_count;
--  char amount[6];
-+  signed char amount[6];
-   char clobbers_t;
- };
- 
-Index: gcc/config/sh/sh_optimize_sett_clrt.cc
-===================================================================
---- a/src/gcc/config/sh/sh_optimize_sett_clrt.cc	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/sh/sh_optimize_sett_clrt.cc	(.../branches/gcc-4_9-branch)
-@@ -111,7 +111,7 @@
-   // Given a start insn and its basic block, recursively determine all
-   // possible ccreg values in all basic block paths that can lead to the
-   // start insn.
--  void find_last_ccreg_values (rtx start_insn, basic_block bb,
-+  bool find_last_ccreg_values (rtx start_insn, basic_block bb,
- 			       std::vector<ccreg_value>& values_out,
- 			       std::vector<basic_block>& prev_visited_bb) const;
- 
-@@ -226,8 +226,8 @@
- 
- 	    ccreg_values.clear ();
- 	    visited_bbs.clear ();
--	    find_last_ccreg_values (PREV_INSN (i), bb, ccreg_values,
--				    visited_bbs);
-+	    bool ok = find_last_ccreg_values (PREV_INSN (i), bb, ccreg_values,
-+					      visited_bbs);
- 
- 	    log_msg ("number of ccreg values collected: %u\n",
- 		     (unsigned int)ccreg_values.size ());
-@@ -235,7 +235,7 @@
- 	    // If all the collected values are equal and are equal to the
- 	    // constant value of the setcc insn, the setcc insn can be
- 	    // removed.
--	    if (all_ccreg_values_equal (ccreg_values)
-+	    if (ok && all_ccreg_values_equal (ccreg_values)
- 		&& rtx_equal_p (ccreg_values.front ().value, setcc_val))
- 	      {
- 		log_msg ("all values are ");
-@@ -309,7 +309,7 @@
-     gcc_unreachable ();
- }
- 
--void
-+bool
- sh_optimize_sett_clrt
- ::find_last_ccreg_values (rtx start_insn, basic_block bb,
- 			  std::vector<ccreg_value>& values_out,
-@@ -348,7 +348,7 @@
- 	  log_msg ("\n");
- 
- 	  values_out.push_back (v);
--	  return;
-+	  return true;
- 	}
- 
-       if (any_condjump_p (i) && onlyjump_p (i) && !prev_visited_bb.empty ())
-@@ -372,7 +372,7 @@
- 	  log_msg ("\n");
- 
- 	  values_out.push_back (v);
--	  return;
-+	  return true;
- 	}
-     }
- 
-@@ -393,10 +393,14 @@
-       for (edge_iterator ei = ei_start (bb->preds); !ei_end_p (ei);
- 	   ei_next (&ei))
- 	{
-+	  if (ei_edge (ei)->flags & EDGE_COMPLEX)
-+	    log_return (false, "aborting due to complex edge\n");
-+
- 	  basic_block pred_bb = ei_edge (ei)->src;
- 	  pred_bb_count += 1;
--	  find_last_ccreg_values (BB_END (pred_bb), pred_bb, values_out,
--				  prev_visited_bb);
-+	  if (!find_last_ccreg_values (BB_END (pred_bb), pred_bb, values_out,
-+				       prev_visited_bb))
-+	    return false;
- 	}
- 
-       prev_visited_bb.pop_back ();
-@@ -419,6 +423,8 @@
- 
-     values_out.push_back (v);
-   }
-+
-+  return true;
- }
- 
- bool
-Index: gcc/config/sh/sh-mem.cc
-===================================================================
---- a/src/gcc/config/sh/sh-mem.cc	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/sh/sh-mem.cc	(.../branches/gcc-4_9-branch)
-@@ -1,5 +1,5 @@
- /* Helper routines for memory move and comparison insns.
--   Copyright (C) 2013-2014 Free Software Foundation, Inc.
-+   Copyright (C) 2013-2015 Free Software Foundation, Inc.
- 
- This file is part of GCC.
- 
-@@ -226,7 +226,7 @@
-   emit_move_insn (tmp3, addr2);
-   emit_move_insn (s2_addr, plus_constant (Pmode, s2_addr, 4));
- 
--  /*start long loop.  */
-+  /* start long loop.  */
-   emit_label (L_loop_long);
- 
-   emit_move_insn (tmp2, tmp3);
-@@ -335,7 +335,7 @@
-   rtx len = force_reg (SImode, operands[3]);
-   int constp = CONST_INT_P (operands[3]);
- 
--  /* Loop on a register count. */
-+  /* Loop on a register count.  */
-   if (constp)
-     {
-       rtx tmp0 = gen_reg_rtx (SImode);
-@@ -364,7 +364,7 @@
-               add_int_reg_note (jump, REG_BR_PROB, prob_likely);
-             }
- 
--          /* word count. Do we have iterations ? */
-+          /* word count. Do we have iterations ?  */
-           emit_insn (gen_lshrsi3 (lenw, len, GEN_INT (2)));
- 
-           /*start long loop.  */
-@@ -407,6 +407,7 @@
-           /* end loop.  Reached max iterations.  */
-           if (! sbytes)
-             {
-+              emit_insn (gen_subsi3 (operands[0], tmp1, tmp2));
-               jump = emit_jump_insn (gen_jump_compact (L_return));
-               emit_barrier_after (jump);
-             }
-@@ -482,6 +483,13 @@
-       jump = emit_jump_insn (gen_jump_compact( L_end_loop_byte));
-       emit_barrier_after (jump);
-     }
-+  else
-+    {
-+      emit_insn (gen_cmpeqsi_t (len, const0_rtx));
-+      emit_move_insn (operands[0], const0_rtx);
-+      jump = emit_jump_insn (gen_branch_true (L_return));
-+      add_int_reg_note (jump, REG_BR_PROB, prob_unlikely);
-+    }
- 
-   addr1 = adjust_automodify_address (addr1, QImode, s1_addr, 0);
-   addr2 = adjust_automodify_address (addr2, QImode, s2_addr, 0);
-@@ -522,14 +530,14 @@
-     emit_insn (gen_zero_extendqisi2 (tmp2, gen_lowpart (QImode, tmp2)));
-   emit_insn (gen_zero_extendqisi2 (tmp1, gen_lowpart (QImode, tmp1)));
- 
-+  emit_insn (gen_subsi3 (operands[0], tmp1, tmp2));
-+
-   emit_label (L_return);
- 
--  emit_insn (gen_subsi3 (operands[0], tmp1, tmp2));
--
-   return true;
- }
- 
--/* Emit code to perform a strlen
-+/* Emit code to perform a strlen.
- 
-    OPERANDS[0] is the destination.
-    OPERANDS[1] is the string.
-@@ -568,7 +576,7 @@
- 
-   addr1 = adjust_automodify_address (addr1, SImode, current_addr, 0);
- 
--  /*start long loop.  */
-+  /* start long loop.  */
-   emit_label (L_loop_long);
- 
-   /* tmp1 is aligned, OK to load.  */
-Index: gcc/config/sh/sh_treg_combine.cc
-===================================================================
---- a/src/gcc/config/sh/sh_treg_combine.cc	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/sh/sh_treg_combine.cc	(.../branches/gcc-4_9-branch)
-@@ -78,7 +78,9 @@
- 
- In [bb 4] elimination of the comparison would require inversion of the branch
- condition and compensation of other BBs.
--Instead an inverting reg-move can be used:
-+Instead the comparison in [bb 3] can be replaced with the comparison in [bb 5]
-+by using a reg-reg move.  In [bb 4] a logical not is used to compensate the
-+inverted condition.
- 
- [bb 3]
- (set (reg:SI 167) (reg:SI 173))
-@@ -85,7 +87,8 @@
- -> bb 5
- 
- [BB 4]
--(set (reg:SI 167) (not:SI (reg:SI 177)))
-+(set (reg:SI 147 t) (eq:SI (reg:SI 177) (const_int 0)))
-+(set (reg:SI 167) (reg:SI 147 t))
- -> bb 5
- 
- [bb 5]
-@@ -214,9 +217,9 @@
-       and replace the comparisons in the BBs with reg-reg copies to get the
-       operands in place (create new pseudo regs).
- 
--    - If the cstores differ, try to apply the special case
--        (eq (reg) (const_int 0)) -> inverted = (not (reg)).
--      for the subordinate cstore types and eliminate the dominating ones.
-+    - If the cstores differ and the comparison is a test against zero,
-+      use reg-reg copies for the dominating cstores and logical not cstores
-+      for the subordinate cstores.
- 
- - If the comparison types in the BBs are not the same, or the first approach
-   doesn't work out for some reason, try to eliminate the comparison before the
-@@ -558,7 +561,8 @@
-   bool can_extend_ccreg_usage (const bb_entry& e,
- 			       const cbranch_trace& trace) const;
- 
--  // Create an insn rtx that is a negating reg move (not operation).
-+  // Create an insn rtx that performs a logical not (test != 0) on the src_reg
-+  // and stores the result in dst_reg.
-   rtx make_not_reg_insn (rtx dst_reg, rtx src_reg) const;
- 
-   // Create an insn rtx that inverts the ccreg.
-@@ -892,12 +896,32 @@
- rtx
- sh_treg_combine::make_not_reg_insn (rtx dst_reg, rtx src_reg) const
- {
--  // This will to go through expanders and may output multiple insns
--  // for multi-word regs.
-+  // On SH we can do only SImode and DImode comparisons.
-+  if (! (GET_MODE (src_reg) == SImode || GET_MODE (src_reg) == DImode))
-+    return NULL;
-+
-+  // On SH we can store the ccreg into an SImode or DImode reg only.
-+  if (! (GET_MODE (dst_reg) == SImode || GET_MODE (dst_reg) == DImode))
-+    return NULL;
-+
-   start_sequence ();
--  expand_simple_unop (GET_MODE (dst_reg), NOT, src_reg, dst_reg, 0);
-+
-+  emit_insn (gen_rtx_SET (VOIDmode, m_ccreg,
-+			  gen_rtx_fmt_ee (EQ, SImode, src_reg, const0_rtx)));
-+
-+  if (GET_MODE (dst_reg) == SImode)
-+    emit_move_insn (dst_reg, m_ccreg);
-+  else if (GET_MODE (dst_reg) == DImode)
-+    {
-+      emit_move_insn (gen_lowpart (SImode, dst_reg), m_ccreg);
-+      emit_move_insn (gen_highpart (SImode, dst_reg), const0_rtx);
-+    }
-+  else
-+    gcc_unreachable ();
-+
-   rtx i = get_insns ();
-   end_sequence ();
-+
-   return i;
- }
- 
-@@ -1080,7 +1104,12 @@
-   // There is one special case though, where an integer comparison
-   //     (eq (reg) (const_int 0))
-   // can be inverted with a sequence
--  //     (eq (not (reg)) (const_int 0))
-+  //     (set (t) (eq (reg) (const_int 0))
-+  //     (set (reg) (t))
-+  //     (eq (reg) (const_int 0))
-+  //
-+  // FIXME: On SH2A it might be better to use the nott insn in this case,
-+  // i.e. do the try_eliminate_cstores approach instead.
-   if (inv_cstore_count != 0 && cstore_count != 0)
-     {
-       if (make_not_reg_insn (comp_op0, comp_op0) == NULL_RTX)
-Index: gcc/config/sh/sh.md
-===================================================================
---- a/src/gcc/config/sh/sh.md	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/sh/sh.md	(.../branches/gcc-4_9-branch)
-@@ -6331,10 +6331,9 @@
- })
- 
- (define_expand "extendqihi2"
--  [(set (match_operand:HI 0 "arith_reg_dest" "")
--	(sign_extend:HI (match_operand:QI 1 "arith_reg_operand" "")))]
--  ""
--  "")
-+  [(set (match_operand:HI 0 "arith_reg_dest")
-+	(sign_extend:HI (match_operand:QI 1 "arith_reg_operand")))]
-+  "TARGET_SH1")
- 
- (define_insn "*extendqihi2_compact_reg"
-   [(set (match_operand:HI 0 "arith_reg_dest" "=r")
-Index: gcc/config/avr/avr-fixed.md
-===================================================================
---- a/src/gcc/config/avr/avr-fixed.md	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/avr/avr-fixed.md	(.../branches/gcc-4_9-branch)
-@@ -231,8 +231,12 @@
-               (clobber (reg:HI 24))])
-    (set (match_operand:QQ 0 "register_operand" "")
-         (reg:QQ 23))]
--  "!AVR_HAVE_MUL")
-+  "!AVR_HAVE_MUL"
-+  {
-+    avr_fix_inputs (operands, 1 << 2, regmask (QQmode, 24));
-+  })
- 
-+
- (define_expand "muluqq3_nomul"
-   [(set (reg:UQQ 22)
-         (match_operand:UQQ 1 "register_operand" ""))
-@@ -246,7 +250,10 @@
-               (clobber (reg:HI 22))])
-    (set (match_operand:UQQ 0 "register_operand" "")
-         (reg:UQQ 25))]
--  "!AVR_HAVE_MUL")
-+  "!AVR_HAVE_MUL"
-+  {
-+    avr_fix_inputs (operands, 1 << 2, regmask (UQQmode, 22));
-+  })
- 
- (define_insn "*mulqq3.call"
-   [(set (reg:QQ 23)
-@@ -274,7 +281,10 @@
-               (clobber (reg:HI 22))])
-    (set (match_operand:ALL2QA 0 "register_operand" "")
-         (reg:ALL2QA 24))]
--  "AVR_HAVE_MUL")
-+  "AVR_HAVE_MUL"
-+  {
-+    avr_fix_inputs (operands, 1 << 2, regmask (<MODE>mode, 18));
-+  })
- 
- ;; "*mulhq3.call"  "*muluhq3.call"
- ;; "*mulha3.call"  "*muluha3.call"
-@@ -302,7 +312,10 @@
-                     (reg:ALL4A 20)))
-    (set (match_operand:ALL4A 0 "register_operand" "")
-         (reg:ALL4A 24))]
--  "AVR_HAVE_MUL")
-+  "AVR_HAVE_MUL"
-+  {
-+    avr_fix_inputs (operands, 1 << 2, regmask (<MODE>mode, 16));
-+  })
- 
- ;; "*mulsa3.call" "*mulusa3.call"
- (define_insn "*mul<mode>3.call"
-@@ -330,8 +343,13 @@
-                                 (reg:ALL1Q 22)))
-               (clobber (reg:QI 25))])
-    (set (match_operand:ALL1Q 0 "register_operand" "")
--        (reg:ALL1Q 24))])
-+        (reg:ALL1Q 24))]
-+  ""
-+  {
-+    avr_fix_inputs (operands, 1 << 2, regmask (<MODE>mode, 25));
-+  })
- 
-+
- ;; "*divqq3.call" "*udivuqq3.call"
- (define_insn "*<code><mode>3.call"
-   [(set (reg:ALL1Q 24)
-@@ -356,7 +374,11 @@
-               (clobber (reg:HI 26))
-               (clobber (reg:QI 21))])
-    (set (match_operand:ALL2QA 0 "register_operand" "")
--        (reg:ALL2QA 24))])
-+        (reg:ALL2QA 24))]
-+  ""
-+  {
-+    avr_fix_inputs (operands, 1 << 2, regmask (<MODE>mode, 26));
-+  })
- 
- ;; "*divhq3.call" "*udivuhq3.call"
- ;; "*divha3.call" "*udivuha3.call"
-@@ -385,7 +407,11 @@
-               (clobber (reg:HI 26))
-               (clobber (reg:HI 30))])
-    (set (match_operand:ALL4A 0 "register_operand" "")
--        (reg:ALL4A 22))])
-+        (reg:ALL4A 22))]
-+  ""
-+  {
-+    avr_fix_inputs (operands, 1 << 2, regmask (<MODE>mode, 24));
-+  })
- 
- ;; "*divsa3.call" "*udivusa3.call"
- (define_insn "*<code><mode>3.call"
-@@ -435,6 +461,7 @@
- 
-     operands[3] = gen_rtx_REG (<MODE>mode, regno_out[(size_t) GET_MODE_SIZE (<MODE>mode)]);
-     operands[4] = gen_rtx_REG (<MODE>mode,  regno_in[(size_t) GET_MODE_SIZE (<MODE>mode)]);
-+    avr_fix_inputs (operands, 1 << 2, regmask (<MODE>mode, REGNO (operands[4])));
-     operands[5] = simplify_gen_subreg (QImode, force_reg (HImode, operands[2]), HImode, 0);
-     // $2 is no more needed, but is referenced for expand.
-     operands[2] = const0_rtx;
-Index: gcc/config/avr/avr-dimode.md
-===================================================================
---- a/src/gcc/config/avr/avr-dimode.md	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/avr/avr-dimode.md	(.../branches/gcc-4_9-branch)
-@@ -68,6 +68,7 @@
-   {
-     rtx acc_a = gen_rtx_REG (<MODE>mode, ACC_A);
- 
-+    avr_fix_inputs (operands, 1 << 2, regmask (<MODE>mode, ACC_A));
-     emit_move_insn (acc_a, operands[1]);
- 
-     if (DImode == <MODE>mode
-@@ -145,6 +146,7 @@
-   {
-     rtx acc_a = gen_rtx_REG (<MODE>mode, ACC_A);
- 
-+    avr_fix_inputs (operands, 1 << 2, regmask (<MODE>mode, ACC_A));
-     emit_move_insn (acc_a, operands[1]);
- 
-     if (const_operand (operands[2], GET_MODE (operands[2])))
-@@ -201,6 +203,7 @@
-   {
-     rtx acc_a = gen_rtx_REG (<MODE>mode, ACC_A);
- 
-+    avr_fix_inputs (operands, 1 << 2, regmask (<MODE>mode, ACC_A));
-     emit_move_insn (acc_a, operands[1]);
- 
-     if (const_operand (operands[2], GET_MODE (operands[2])))
-@@ -249,6 +252,7 @@
-   {
-     rtx acc_a = gen_rtx_REG (<MODE>mode, ACC_A);
- 
-+    avr_fix_inputs (operands, 1 << 2, regmask (<MODE>mode, ACC_A));
-     emit_move_insn (acc_a, operands[1]);
- 
-     if (const_operand (operands[2], GET_MODE (operands[2])))
-@@ -338,6 +342,7 @@
-   {
-     rtx acc_a = gen_rtx_REG (<MODE>mode, ACC_A);
- 
-+    avr_fix_inputs (operands, 1 << 2, regmask (<MODE>mode, ACC_A));
-     emit_move_insn (acc_a, operands[1]);
- 
-     if (s8_operand (operands[2], VOIDmode))
-@@ -424,6 +429,7 @@
-   {
-     rtx acc_a = gen_rtx_REG (<MODE>mode, ACC_A);
- 
-+    avr_fix_inputs (operands, 1 << 2, regmask (<MODE>mode, ACC_A));
-     emit_move_insn (acc_a, operands[1]);
-     emit_move_insn (gen_rtx_REG (QImode, 16), operands[2]);
-     emit_insn (gen_<code_stdname><mode>3_insn ());
-@@ -457,6 +463,7 @@
-               (clobber (any_extend:SI (match_dup 1)))])]
-   "avr_have_dimode"
-   {
-+    avr_fix_inputs (operands, 1 << 2, regmask (SImode, 22));
-     emit_move_insn (gen_rtx_REG (SImode, 22), operands[1]);
-     emit_move_insn (gen_rtx_REG (SImode, 18), operands[2]);
-     emit_insn (gen_<extend_u>mulsidi3_insn());
-Index: gcc/config/avr/avr.md
-===================================================================
---- a/src/gcc/config/avr/avr.md	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/avr/avr.md	(.../branches/gcc-4_9-branch)
-@@ -1482,7 +1482,11 @@
-    (set (reg:QI 22) (match_operand:QI 2 "register_operand" ""))
-    (parallel [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
-               (clobber (reg:QI 22))])
--   (set (match_operand:QI 0 "register_operand" "") (reg:QI 24))])
-+   (set (match_operand:QI 0 "register_operand" "") (reg:QI 24))]
-+  ""
-+  {
-+    avr_fix_inputs (operands, 1 << 2, regmask (QImode, 24));
-+  })
- 
- (define_insn "*mulqi3_call"
-   [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
-@@ -2210,8 +2214,14 @@
-    (parallel [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
-               (clobber (reg:HI 22))
-               (clobber (reg:QI 21))])
--   (set (match_operand:HI 0 "register_operand" "") (reg:HI 24))])
-+   (set (match_operand:HI 0 "register_operand" "")
-+        (reg:HI 24))]
-+  ""
-+  {
-+    avr_fix_inputs (operands, (1 << 2), regmask (HImode, 24));
-+  })
- 
-+
- (define_insn "*mulhi3_call"
-   [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
-    (clobber (reg:HI 22))
-@@ -2248,6 +2258,10 @@
-         emit_insn (gen_mulohisi3 (operands[0], operands[2], operands[1]));
-         DONE;
-       }
-+
-+    if (avr_emit3_fix_outputs (gen_mulsi3, operands, 1 << 0,
-+                               regmask (DImode, 18) | regmask (HImode, 26)))
-+      DONE;
-   })
- 
- (define_insn_and_split "*mulsi3"
-@@ -2287,7 +2301,23 @@
- 
- ;; "muluqisi3"
- ;; "muluhisi3"
--(define_insn_and_split "mulu<mode>si3"
-+(define_expand "mulu<mode>si3"
-+  [(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "")
-+                   (mult:SI (zero_extend:SI (match_operand:QIHI 1 "pseudo_register_operand" ""))
-+                            (match_operand:SI 2 "pseudo_register_or_const_int_operand" "")))
-+              (clobber (reg:HI 26))
-+              (clobber (reg:DI 18))])]
-+  "AVR_HAVE_MUL"
-+  {
-+    avr_fix_inputs (operands, (1 << 1) | (1 << 2), -1u);
-+    if (avr_emit3_fix_outputs (gen_mulu<mode>si3, operands, 1 << 0,
-+                               regmask (DImode, 18) | regmask (HImode, 26)))
-+      DONE;
-+  })
-+
-+;; "*muluqisi3"
-+;; "*muluhisi3"
-+(define_insn_and_split "*mulu<mode>si3"
-   [(set (match_operand:SI 0 "pseudo_register_operand"                           "=r")
-         (mult:SI (zero_extend:SI (match_operand:QIHI 1 "pseudo_register_operand" "r"))
-                  (match_operand:SI 2 "pseudo_register_or_const_int_operand"      "rn")))
-@@ -2323,7 +2353,23 @@
- 
- ;; "mulsqisi3"
- ;; "mulshisi3"
--(define_insn_and_split "muls<mode>si3"
-+(define_expand "muls<mode>si3"
-+  [(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "")
-+                   (mult:SI (sign_extend:SI (match_operand:QIHI 1 "pseudo_register_operand" ""))
-+                            (match_operand:SI 2 "pseudo_register_or_const_int_operand" "")))
-+              (clobber (reg:HI 26))
-+              (clobber (reg:DI 18))])]
-+  "AVR_HAVE_MUL"
-+  {
-+    avr_fix_inputs (operands, (1 << 1) | (1 << 2), -1u);
-+    if (avr_emit3_fix_outputs (gen_muls<mode>si3, operands, 1 << 0,
-+                               regmask (DImode, 18) | regmask (HImode, 26)))
-+      DONE;
-+  })
-+
-+;; "*mulsqisi3"
-+;; "*mulshisi3"
-+(define_insn_and_split "*muls<mode>si3"
-   [(set (match_operand:SI 0 "pseudo_register_operand"                           "=r")
-         (mult:SI (sign_extend:SI (match_operand:QIHI 1 "pseudo_register_operand" "r"))
-                  (match_operand:SI 2 "pseudo_register_or_const_int_operand"      "rn")))
-@@ -2366,7 +2412,22 @@
- 
- ;; One-extend operand 1
- 
--(define_insn_and_split "mulohisi3"
-+(define_expand "mulohisi3"
-+  [(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "")
-+                   (mult:SI (not:SI (zero_extend:SI
-+                                     (not:HI (match_operand:HI 1 "pseudo_register_operand" ""))))
-+                            (match_operand:SI 2 "pseudo_register_or_const_int_operand" "")))
-+              (clobber (reg:HI 26))
-+              (clobber (reg:DI 18))])]
-+  "AVR_HAVE_MUL"
-+  {
-+    avr_fix_inputs (operands, (1 << 1) | (1 << 2), -1u);
-+    if (avr_emit3_fix_outputs (gen_mulohisi3, operands, 1 << 0,
-+                               regmask (DImode, 18) | regmask (HImode, 26)))
-+      DONE;
-+  })
-+
-+(define_insn_and_split "*mulohisi3"
-   [(set (match_operand:SI 0 "pseudo_register_operand"                          "=r")
-         (mult:SI (not:SI (zero_extend:SI
-                           (not:HI (match_operand:HI 1 "pseudo_register_operand" "r"))))
-@@ -2394,7 +2455,12 @@
-                             (any_extend:SI (match_operand:HI 2 "register_operand" ""))))
-               (clobber (reg:HI 26))
-               (clobber (reg:DI 18))])]
--  "AVR_HAVE_MUL")
-+  "AVR_HAVE_MUL"
-+  {
-+    if (avr_emit3_fix_outputs (gen_<extend_u>mulhisi3, operands, 1 << 0,
-+                               regmask (DImode, 18) | regmask (HImode, 26)))
-+      DONE;
-+  })
- 
- (define_expand "usmulhisi3"
-   [(parallel [(set (match_operand:SI 0 "register_operand" "")
-@@ -2402,7 +2468,12 @@
-                             (sign_extend:SI (match_operand:HI 2 "register_operand" ""))))
-               (clobber (reg:HI 26))
-               (clobber (reg:DI 18))])]
--  "AVR_HAVE_MUL")
-+  "AVR_HAVE_MUL"
-+  {
-+    if (avr_emit3_fix_outputs (gen_usmulhisi3, operands, 1 << 0,
-+                               regmask (DImode, 18) | regmask (HImode, 26)))
-+      DONE;
-+  })
- 
- ;; "*uumulqihisi3" "*uumulhiqisi3" "*uumulhihisi3" "*uumulqiqisi3"
- ;; "*usmulqihisi3" "*usmulhiqisi3" "*usmulhihisi3" "*usmulqiqisi3"
-@@ -2474,7 +2545,10 @@
-               (clobber (reg:HI 22))])
-    (set (match_operand:HI 0 "register_operand" "")
-         (reg:HI 24))]
--  "AVR_HAVE_MUL")
-+  "AVR_HAVE_MUL"
-+  {
-+    avr_fix_inputs (operands, 1 << 2, regmask (HImode, 18));
-+  })
- 
- 
- (define_insn "*mulsi3_call"
-@@ -2697,6 +2771,10 @@
-         emit_insn (gen_mulsqipsi3 (operands[0], reg, operands[1]));
-         DONE;
-       }
-+
-+    if (avr_emit3_fix_outputs (gen_mulpsi3, operands, 1u << 0,
-+                               regmask (DImode, 18) | regmask (HImode, 26)))
-+      DONE;
-   })
- 
- (define_insn "*umulqihipsi3"
-@@ -2729,7 +2807,21 @@
-   [(set_attr "length" "7")
-    (set_attr "cc" "clobber")])
- 
--(define_insn_and_split "mulsqipsi3"
-+(define_expand "mulsqipsi3"
-+  [(parallel [(set (match_operand:PSI 0 "pseudo_register_operand" "")
-+                   (mult:PSI (sign_extend:PSI (match_operand:QI 1 "pseudo_register_operand" ""))
-+                             (match_operand:PSI 2 "pseudo_register_or_const_int_operand""")))
-+              (clobber (reg:HI 26))
-+              (clobber (reg:DI 18))])]
-+  "AVR_HAVE_MUL"
-+  {
-+    avr_fix_inputs (operands, (1 << 1) | (1 << 2), -1u);
-+    if (avr_emit3_fix_outputs (gen_mulsqipsi3, operands, 1 << 0,
-+                               regmask (DImode, 18) | regmask (HImode, 26)))
-+      DONE;
-+  })
-+
-+(define_insn_and_split "*mulsqipsi3"
-   [(set (match_operand:PSI 0 "pseudo_register_operand"                          "=r")
-         (mult:PSI (sign_extend:PSI (match_operand:QI 1 "pseudo_register_operand" "r"))
-                   (match_operand:PSI 2 "pseudo_register_or_const_int_operand"    "rn")))
-@@ -6064,6 +6156,7 @@
-         emit_insn (gen_fmul_insn (operand0, operand1, operand2));
-         DONE;
-       }
-+    avr_fix_inputs (operands, 1 << 2, regmask (QImode, 24));
-   })
- 
- (define_insn "fmul_insn"
-@@ -6107,6 +6200,7 @@
-         emit_insn (gen_fmuls_insn (operand0, operand1, operand2));
-         DONE;
-       }
-+    avr_fix_inputs (operands, 1 << 2, regmask (QImode, 24));
-   })
- 
- (define_insn "fmuls_insn"
-@@ -6150,6 +6244,7 @@
-         emit_insn (gen_fmulsu_insn (operand0, operand1, operand2));
-         DONE;
-       }
-+    avr_fix_inputs (operands, 1 << 2, regmask (QImode, 24));
-   })
- 
- (define_insn "fmulsu_insn"
-Index: gcc/config/avr/avr-protos.h
-===================================================================
---- a/src/gcc/config/avr/avr-protos.h	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/avr/avr-protos.h	(.../branches/gcc-4_9-branch)
-@@ -124,6 +124,15 @@
- extern bool avr_load_libgcc_p (rtx);
- extern bool avr_xload_libgcc_p (enum machine_mode);
- 
-+static inline unsigned
-+regmask (enum machine_mode mode, unsigned regno)
-+{
-+  return ((1u << GET_MODE_SIZE (mode)) - 1) << regno;
-+}
-+
-+extern void avr_fix_inputs (rtx*, unsigned, unsigned);
-+extern bool avr_emit3_fix_outputs (rtx (*)(rtx,rtx,rtx), rtx*, unsigned, unsigned);
-+
- extern rtx lpm_reg_rtx;
- extern rtx lpm_addr_reg_rtx;
- extern rtx tmp_reg_rtx;
-Index: gcc/config/avr/avr.c
-===================================================================
---- a/src/gcc/config/avr/avr.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/avr/avr.c	(.../branches/gcc-4_9-branch)
-@@ -11118,6 +11118,115 @@
- }
- 
- 
-+/* PR63633: The middle-end might come up with hard regs as input operands.
-+
-+   RMASK is a bit mask representing a subset of hard registers R0...R31:
-+   Rn is an element of that set iff bit n of RMASK is set.
-+   OPMASK describes a subset of OP[]:  If bit n of OPMASK is 1 then
-+   OP[n] has to be fixed; otherwise OP[n] is left alone.
-+
-+   For each element of OPMASK which is a hard register overlapping RMASK,
-+   replace OP[n] with a newly created pseudo register
-+
-+   HREG == 0:  Also emit a move insn that copies the contents of that
-+               hard register into the new pseudo.
-+
-+   HREG != 0:  Also set HREG[n] to the hard register.  */
-+
-+static void
-+avr_fix_operands (rtx *op, rtx *hreg, unsigned opmask, unsigned rmask)
-+{
-+  for (; opmask; opmask >>= 1, op++)
-+    {
-+      rtx reg = *op;
-+
-+      if (hreg)
-+        *hreg = NULL_RTX;
-+
-+      if ((opmask & 1)
-+          && REG_P (reg)
-+          && REGNO (reg) < FIRST_PSEUDO_REGISTER
-+          // This hard-reg overlaps other prohibited hard regs?
-+          && (rmask & regmask (GET_MODE (reg), REGNO (reg))))
-+        {
-+          *op = gen_reg_rtx (GET_MODE (reg));
-+          if (hreg == NULL)
-+            emit_move_insn (*op, reg);
-+          else
-+            *hreg = reg;
-+        }
-+
-+      if (hreg)
-+        hreg++;
-+    }
-+}
-+
-+
-+void
-+avr_fix_inputs (rtx *op, unsigned opmask, unsigned rmask)
-+{
-+  avr_fix_operands (op, NULL, opmask, rmask);
-+}
-+
-+
-+/* Helper for the function below:  If bit n of MASK is set and
-+   HREG[n] != NULL, then emit a move insn to copy OP[n] to HREG[n].
-+   Otherwise do nothing for that n.  Return TRUE.  */
-+
-+static bool
-+avr_move_fixed_operands (rtx *op, rtx *hreg, unsigned mask)
-+{
-+  for (; mask; mask >>= 1, op++, hreg++)
-+    if ((mask & 1)
-+        && *hreg)
-+      emit_move_insn (*hreg, *op);
-+
-+  return true;
-+}
-+
-+
-+/* PR63633: The middle-end might come up with hard regs as output operands.
-+
-+   GEN is a sequence generating function like gen_mulsi3 with 3 operands OP[].
-+   RMASK is a bit mask representing a subset of hard registers R0...R31:
-+   Rn is an element of that set iff bit n of RMASK is set.
-+   OPMASK describes a subset of OP[]:  If bit n of OPMASK is 1 then
-+   OP[n] has to be fixed; otherwise OP[n] is left alone.
-+
-+   Emit the insn sequence as generated by GEN() with all elements of OPMASK
-+   which are hard registers overlapping RMASK replaced by newly created
-+   pseudo registers.  After the sequence has been emitted, emit insns that
-+   move the contents of respective pseudos to their hard regs.  */
-+
-+bool
-+avr_emit3_fix_outputs (rtx (*gen)(rtx,rtx,rtx), rtx *op,
-+                       unsigned opmask, unsigned rmask)
-+{
-+  const int n = 3;
-+  rtx hreg[n];
-+
-+  /* It is legitimate for GEN to call this function, and in order not to
-+     get self-recursive we use the following static kludge.  This is the
-+     only way not to duplicate all expanders and to avoid ugly and
-+     hard-to-maintain C-code instead of the much more appreciated RTL
-+     representation as supplied by define_expand.  */
-+  static bool lock = false;
-+
-+  gcc_assert (opmask < (1u << n));
-+
-+  if (lock)
-+    return false;
-+
-+  avr_fix_operands (op, hreg, opmask, rmask);
-+
-+  lock = true;
-+  emit_insn (gen (op[0], op[1], op[2]));
-+  lock = false;
-+
-+  return avr_move_fixed_operands (op, hreg, opmask);
-+}
-+
-+
- /* Worker function for movmemhi expander.
-    XOP[0]  Destination as MEM:BLK
-    XOP[1]  Source      "     "
-Index: gcc/config/aarch64/aarch64-simd.md
-===================================================================
---- a/src/gcc/config/aarch64/aarch64-simd.md	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/aarch64/aarch64-simd.md	(.../branches/gcc-4_9-branch)
-@@ -934,6 +934,41 @@
-   [(set_attr "type" "neon_minmax<q>")]
- )
- 
-+(define_expand "<su><maxmin>v2di3"
-+  [(parallel [
-+    (set (match_operand:V2DI 0 "register_operand" "")
-+	 (MAXMIN:V2DI (match_operand:V2DI 1 "register_operand" "")
-+		  (match_operand:V2DI 2 "register_operand" "")))
-+    (clobber (reg:CC CC_REGNUM))])]
-+  "TARGET_SIMD"
-+{
-+  enum rtx_code cmp_operator;
-+  rtx cmp_fmt;
-+
-+  switch (<CODE>)
-+    {
-+    case UMIN:
-+      cmp_operator = LTU;
-+      break;
-+    case SMIN:
-+      cmp_operator = LT;
-+      break;
-+    case UMAX:
-+      cmp_operator = GTU;
-+      break;
-+    case SMAX:
-+      cmp_operator = GT;
-+      break;
-+    default:
-+      gcc_unreachable ();
-+    }
-+
-+  cmp_fmt = gen_rtx_fmt_ee (cmp_operator, V2DImode, operands[1], operands[2]);
-+  emit_insn (gen_aarch64_vcond_internalv2div2di (operands[0], operands[1],
-+              operands[2], cmp_fmt, operands[1], operands[2]));
-+  DONE;
-+})
-+
- ;; vec_concat gives a new vector with the low elements from operand 1, and
- ;; the high elements from operand 2.  That is to say, given op1 = { a, b }
- ;; op2 = { c, d }, vec_concat (op1, op2) = { a, b, c, d }.
-@@ -4565,8 +4600,8 @@
- })
- 
- (define_insn "*aarch64_simd_ld1r<mode>"
--  [(set (match_operand:VALLDI 0 "register_operand" "=w")
--	(vec_duplicate:VALLDI
-+  [(set (match_operand:VALL 0 "register_operand" "=w")
-+	(vec_duplicate:VALL
- 	  (match_operand:<VEL> 1 "aarch64_simd_struct_operand" "Utv")))]
-   "TARGET_SIMD"
-   "ld1r\\t{%0.<Vtype>}, %1"
-Index: gcc/config/aarch64/aarch64.c
-===================================================================
---- a/src/gcc/config/aarch64/aarch64.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/aarch64/aarch64.c	(.../branches/gcc-4_9-branch)
-@@ -5152,7 +5152,6 @@
-       if (strlen (cpu->name) == len && strncmp (cpu->name, str, len) == 0)
- 	{
- 	  selected_cpu = cpu;
--	  selected_tune = cpu;
- 	  aarch64_isa_flags = selected_cpu->flags;
- 
- 	  if (ext != NULL)
-@@ -5248,9 +5247,8 @@
- 
-   gcc_assert (selected_cpu);
- 
--  /* The selected cpu may be an architecture, so lookup tuning by core ID.  */
-   if (!selected_tune)
--    selected_tune = &all_cores[selected_cpu->core];
-+    selected_tune = selected_cpu;
- 
-   aarch64_tune_flags = selected_tune->flags;
-   aarch64_tune = selected_tune->core;
-Index: gcc/config/aarch64/aarch64-elf-raw.h
-===================================================================
---- a/src/gcc/config/aarch64/aarch64-elf-raw.h	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/aarch64/aarch64-elf-raw.h	(.../branches/gcc-4_9-branch)
-@@ -25,9 +25,18 @@
- #define STARTFILE_SPEC " crti%O%s crtbegin%O%s crt0%O%s"
- #define ENDFILE_SPEC " crtend%O%s crtn%O%s"
- 
-+#ifdef TARGET_FIX_ERR_A53_835769_DEFAULT
-+#define CA53_ERR_835769_SPEC \
-+  " %{!mno-fix-cortex-a53-835769:--fix-cortex-a53-835769}"
-+#else
-+#define CA53_ERR_835769_SPEC \
-+  " %{mfix-cortex-a53-835769:--fix-cortex-a53-835769}"
-+#endif
-+
- #ifndef LINK_SPEC
- #define LINK_SPEC "%{mbig-endian:-EB} %{mlittle-endian:-EL} -X \
--  -maarch64elf%{mabi=ilp32*:32}%{mbig-endian:b}"
-+  -maarch64elf%{mabi=ilp32*:32}%{mbig-endian:b}" \
-+  CA53_ERR_835769_SPEC
- #endif
- 
- #endif /* GCC_AARCH64_ELF_RAW_H */
-Index: gcc/config/aarch64/aarch64-linux.h
-===================================================================
---- a/src/gcc/config/aarch64/aarch64-linux.h	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/aarch64/aarch64-linux.h	(.../branches/gcc-4_9-branch)
-@@ -35,8 +35,17 @@
-    %{mbig-endian:-EB} %{mlittle-endian:-EL}     \
-    -maarch64linux%{mbig-endian:b}"
- 
--#define LINK_SPEC LINUX_TARGET_LINK_SPEC
-+#ifdef TARGET_FIX_ERR_A53_835769_DEFAULT
-+#define CA53_ERR_835769_SPEC \
-+  " %{!mno-fix-cortex-a53-835769:--fix-cortex-a53-835769}"
-+#else
-+#define CA53_ERR_835769_SPEC \
-+  " %{mfix-cortex-a53-835769:--fix-cortex-a53-835769}"
-+#endif
- 
-+#define LINK_SPEC LINUX_TARGET_LINK_SPEC \
-+                  CA53_ERR_835769_SPEC
-+
- #define TARGET_OS_CPP_BUILTINS()		\
-   do						\
-     {						\
-Index: gcc/config/rs6000/t-rtems
-===================================================================
---- a/src/gcc/config/rs6000/t-rtems	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/rs6000/t-rtems	(.../branches/gcc-4_9-branch)
-@@ -18,16 +18,24 @@
- # along with GCC; see the file COPYING3.  If not see
- # <http://www.gnu.org/licenses/>.
- 
--MULTILIB_OPTIONS	= \
--mcpu=403/mcpu=505/mcpu=603e/mcpu=604/mcpu=860/mcpu=7400/mcpu=8540 \
--msoft-float/mfloat-gprs=double
-+MULTILIB_OPTIONS =
-+MULTILIB_DIRNAMES =
-+MULTILIB_MATCHES =
-+MULTILIB_EXCEPTIONS =
-+MULTILIB_REQUIRED =
- 
--MULTILIB_DIRNAMES	= \
--m403 m505 m603e m604 m860 m7400 m8540 \
--nof gprsdouble
-+MULTILIB_OPTIONS += mcpu=403/mcpu=505/mcpu=603e/mcpu=604/mcpu=860/mcpu=7400/mcpu=8540/mcpu=e6500
-+MULTILIB_DIRNAMES += m403 m505 m603e m604 m860 m7400 m8540 me6500
- 
--# MULTILIB_MATCHES	= ${MULTILIB_MATCHES_FLOAT}
--MULTILIB_MATCHES	=
-+MULTILIB_OPTIONS += m32
-+MULTILIB_DIRNAMES += m32
-+
-+MULTILIB_OPTIONS += msoft-float/mfloat-gprs=double
-+MULTILIB_DIRNAMES += nof gprsdouble
-+
-+MULTILIB_OPTIONS += mno-spe/mno-altivec
-+MULTILIB_DIRNAMES += nospe noaltivec
-+
- MULTILIB_MATCHES  	+= ${MULTILIB_MATCHES_ENDIAN}
- MULTILIB_MATCHES	+= ${MULTILIB_MATCHES_SYSV}
- # Map 405 to 403
-@@ -52,37 +60,20 @@
- # (mfloat-gprs=single is implicit default)
- MULTILIB_MATCHES	+= mcpu?8540=mcpu?8540/mfloat-gprs?single
- 
--# Soft-float only, default implies msoft-float
--# NOTE: Must match with MULTILIB_MATCHES_FLOAT and MULTILIB_MATCHES
--MULTILIB_SOFTFLOAT_ONLY = \
--*mcpu=401/*msoft-float* \
--*mcpu=403/*msoft-float* \
--*mcpu=405/*msoft-float* \
--*mcpu=801/*msoft-float* \
--*mcpu=821/*msoft-float* \
--*mcpu=823/*msoft-float* \
--*mcpu=860/*msoft-float*
-+# Enumeration of multilibs
- 
--# Hard-float only, take out msoft-float
--MULTILIB_HARDFLOAT_ONLY = \
--*mcpu=505/*msoft-float*
--
--# Targets which do not support gprs
--MULTILIB_NOGPRS = \
--mfloat-gprs=* \
--*mcpu=403/*mfloat-gprs=* \
--*mcpu=505/*mfloat-gprs=* \
--*mcpu=603e/*mfloat-gprs=* \
--*mcpu=604/*mfloat-gprs=* \
--*mcpu=860/*mfloat-gprs=* \
--*mcpu=7400/*mfloat-gprs=*
--
--MULTILIB_EXCEPTIONS =
--
--# Disallow -Dppc and -Dmpc without other options
--MULTILIB_EXCEPTIONS 	+= Dppc* Dmpc*
--
--MULTILIB_EXCEPTIONS	+= \
--${MULTILIB_SOFTFLOAT_ONLY} \
--${MULTILIB_HARDFLOAT_ONLY} \
--${MULTILIB_NOGPRS}
-+MULTILIB_REQUIRED += msoft-float
-+MULTILIB_REQUIRED += mcpu=403
-+MULTILIB_REQUIRED += mcpu=505
-+MULTILIB_REQUIRED += mcpu=603e
-+MULTILIB_REQUIRED += mcpu=603e/msoft-float
-+MULTILIB_REQUIRED += mcpu=604
-+MULTILIB_REQUIRED += mcpu=604/msoft-float
-+MULTILIB_REQUIRED += mcpu=7400
-+MULTILIB_REQUIRED += mcpu=7400/msoft-float
-+MULTILIB_REQUIRED += mcpu=8540
-+MULTILIB_REQUIRED += mcpu=8540/msoft-float/mno-spe
-+MULTILIB_REQUIRED += mcpu=8540/mfloat-gprs=double
-+MULTILIB_REQUIRED += mcpu=860
-+MULTILIB_REQUIRED += mcpu=e6500/m32
-+MULTILIB_REQUIRED += mcpu=e6500/m32/msoft-float/mno-altivec
-Index: gcc/config/rs6000/rs6000-protos.h
-===================================================================
---- a/src/gcc/config/rs6000/rs6000-protos.h	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/rs6000/rs6000-protos.h	(.../branches/gcc-4_9-branch)
-@@ -65,6 +65,7 @@
- extern void altivec_expand_stvex_be (rtx, rtx, enum machine_mode, unsigned);
- extern void rs6000_expand_extract_even (rtx, rtx, rtx);
- extern void rs6000_expand_interleave (rtx, rtx, rtx, bool);
-+extern void rs6000_scale_v2df (rtx, rtx, int);
- extern void build_mask64_2_operands (rtx, rtx *);
- extern int expand_block_clear (rtx[]);
- extern int expand_block_move (rtx[]);
-Index: gcc/config/rs6000/xcoff.h
-===================================================================
---- a/src/gcc/config/rs6000/xcoff.h	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/rs6000/xcoff.h	(.../branches/gcc-4_9-branch)
-@@ -304,14 +304,15 @@
-   do { fputs (LOCAL_COMMON_ASM_OP, (FILE));			\
-        RS6000_OUTPUT_BASENAME ((FILE), (NAME));			\
-        if ((ALIGN) > 32)					\
--	 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%s,%u\n",	\
-+	 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%s%u_,%u\n",	\
- 		  (SIZE), xcoff_bss_section_name,			\
-+		  floor_log2 ((ALIGN) / BITS_PER_UNIT),			\
- 		  floor_log2 ((ALIGN) / BITS_PER_UNIT));		\
-        else if ((SIZE) > 4)					\
--	 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%s,3\n",	\
-+	 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%s3_,3\n",	\
- 		  (SIZE), xcoff_bss_section_name);		\
-        else							\
--	 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%s\n",	\
-+	 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%s,2\n",	\
- 		  (SIZE), xcoff_bss_section_name);		\
-      } while (0)
- #endif
-Index: gcc/config/rs6000/rtems.h
-===================================================================
---- a/src/gcc/config/rs6000/rtems.h	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/rs6000/rtems.h	(.../branches/gcc-4_9-branch)
-@@ -52,7 +52,8 @@
- %{mcpu=750:  %{!Dppc*: %{!Dmpc*: -Dmpc750}  } } \
- %{mcpu=821:  %{!Dppc*: %{!Dmpc*: -Dmpc821}  } } \
- %{mcpu=860:  %{!Dppc*: %{!Dmpc*: -Dmpc860}  } } \
--%{mcpu=8540: %{!Dppc*: %{!Dmpc*: -Dppc8540}  } }" 
-+%{mcpu=8540: %{!Dppc*: %{!Dmpc*: -Dppc8540}  } } \
-+%{mcpu=e6500: -D__PPC_CPU_E6500__}"
- 
- #undef  SUBSUBTARGET_EXTRA_SPECS
- #define SUBSUBTARGET_EXTRA_SPECS \
-Index: gcc/config/rs6000/rs6000-builtin.def
-===================================================================
---- a/src/gcc/config/rs6000/rs6000-builtin.def	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/rs6000/rs6000-builtin.def	(.../branches/gcc-4_9-branch)
-@@ -1258,7 +1258,17 @@
- BU_VSX_2 (VEC_MERGEL_V2DI,    "mergel_2di",	CONST,	vsx_mergel_v2di)
- BU_VSX_2 (VEC_MERGEH_V2DF,    "mergeh_2df",	CONST,	vsx_mergeh_v2df)
- BU_VSX_2 (VEC_MERGEH_V2DI,    "mergeh_2di",	CONST,	vsx_mergeh_v2di)
-+BU_VSX_2 (XXSPLTD_V2DF,       "xxspltd_2df",    CONST,  vsx_xxspltd_v2df)
-+BU_VSX_2 (XXSPLTD_V2DI,       "xxspltd_2di",    CONST,  vsx_xxspltd_v2di)
-+BU_VSX_2 (DIV_V2DI,           "div_2di",        CONST,  vsx_div_v2di)
-+BU_VSX_2 (UDIV_V2DI,          "udiv_2di",       CONST,  vsx_udiv_v2di)
-+BU_VSX_2 (MUL_V2DI,           "mul_2di",        CONST,  vsx_mul_v2di)
- 
-+BU_VSX_2 (XVCVSXDDP_SCALE,    "xvcvsxddp_scale", CONST, vsx_xvcvsxddp_scale)
-+BU_VSX_2 (XVCVUXDDP_SCALE,    "xvcvuxddp_scale", CONST, vsx_xvcvuxddp_scale)
-+BU_VSX_2 (XVCVDPSXDS_SCALE,   "xvcvdpsxds_scale", CONST, vsx_xvcvdpsxds_scale)
-+BU_VSX_2 (XVCVDPUXDS_SCALE,   "xvcvdpuxds_scale", CONST, vsx_xvcvdpuxds_scale)
-+
- /* VSX abs builtin functions.  */
- BU_VSX_A (XVABSDP,	      "xvabsdp",	CONST,	absv2df2)
- BU_VSX_A (XVNABSDP,	      "xvnabsdp",	CONST,	vsx_nabsv2df2)
-Index: gcc/config/rs6000/rs6000-c.c
-===================================================================
---- a/src/gcc/config/rs6000/rs6000-c.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/rs6000/rs6000-c.c	(.../branches/gcc-4_9-branch)
-@@ -597,6 +597,8 @@
-     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
-   { ALTIVEC_BUILTIN_VEC_ROUND, ALTIVEC_BUILTIN_VRFIN,
-     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
-+  { ALTIVEC_BUILTIN_VEC_ROUND, VSX_BUILTIN_XVRDPI,
-+    RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
-   { ALTIVEC_BUILTIN_VEC_RECIP, ALTIVEC_BUILTIN_VRECIPFP,
-     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
-   { ALTIVEC_BUILTIN_VEC_RECIP, VSX_BUILTIN_RECIP_V2DF,
-@@ -877,6 +879,18 @@
-   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
-     RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
-   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
-+    RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
-+    RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
-+    RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
-+    RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
-+    RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
-+    RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
-     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
-   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
-     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
-@@ -931,6 +945,18 @@
-   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
-     RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
-   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
-+    RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
-+    RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
-+    RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
-+    RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
-+    RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
-+    RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
-     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
-   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
-     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
-@@ -1118,6 +1144,10 @@
-     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
-   { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFSX,
-     RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVSXDDP_SCALE,
-+    RS6000_BTI_V2DF, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0},
-+  { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVUXDDP_SCALE,
-+    RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0},
-   { ALTIVEC_BUILTIN_VEC_VCFSX, ALTIVEC_BUILTIN_VCFSX,
-     RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
-   { ALTIVEC_BUILTIN_VEC_VCFUX, ALTIVEC_BUILTIN_VCFUX,
-@@ -1124,12 +1154,20 @@
-     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
-   { ALTIVEC_BUILTIN_VEC_CTS, ALTIVEC_BUILTIN_VCTSXS,
-     RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_CTS, VSX_BUILTIN_XVCVDPSXDS_SCALE,
-+    RS6000_BTI_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
-   { ALTIVEC_BUILTIN_VEC_CTU, ALTIVEC_BUILTIN_VCTUXS,
-     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_CTU, VSX_BUILTIN_XVCVDPUXDS_SCALE,
-+    RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
-   { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVSP,
-     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
-   { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVDP,
-     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
-+  { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_DIV_V2DI,
-+    RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
-+  { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_UDIV_V2DI,
-+    RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF,
-     RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
-   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
-@@ -1595,6 +1633,16 @@
-     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
-   { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
-     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
-+    RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
-+    RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
-+    RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
-+    RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
-+    RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-   { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
-     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
-   { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
-@@ -1643,6 +1691,16 @@
-     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
-   { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
-     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
-+    RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
-+    RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
-+    RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
-+    RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
-+    RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-   { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
-     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
-   { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
-@@ -1771,6 +1829,10 @@
-     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
-   { VSX_BUILTIN_VEC_MUL, VSX_BUILTIN_XVMULDP,
-     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
-+  { VSX_BUILTIN_VEC_MUL, VSX_BUILTIN_MUL_V2DI,
-+    RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
-+  { VSX_BUILTIN_VEC_MUL, VSX_BUILTIN_MUL_V2DI,
-+    RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-   { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUB,
-     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
-   { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESB,
-@@ -1812,6 +1874,18 @@
-   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
-     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
-   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
-+    RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
-+    RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
-+    RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
-+    RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
-+    RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
-+    RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
-     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
-   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
-     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
-@@ -1842,6 +1916,18 @@
-   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
-     RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
-   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
-+    RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
-+    RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
-+    RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
-+    RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
-+    RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
-+    RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
-     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
-   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
-     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
-@@ -1945,6 +2031,8 @@
-     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
-   { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS,
-     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS,
-+    RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-   { ALTIVEC_BUILTIN_VEC_VPKSWUS, ALTIVEC_BUILTIN_VPKSWUS,
-     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
-   { ALTIVEC_BUILTIN_VEC_VPKSHUS, ALTIVEC_BUILTIN_VPKSHUS,
-@@ -2127,6 +2215,14 @@
-     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
-   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
-     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DF,
-+    RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
-+    RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
-+    RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
-+    RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 0 },
-   { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
-     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
-   { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
-@@ -2519,6 +2615,18 @@
-   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
-     RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
-   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
-+    RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
-+    RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
-+    RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
-+    RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
-+    RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
-+    RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
-+  { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
-     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
-   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
-     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
-@@ -2778,6 +2886,8 @@
-     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V16QI },
-   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
-     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI },
-+  { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
-+    RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI },
-   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SF,
-     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI },
-   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
-@@ -2818,6 +2928,12 @@
-     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI },
-   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
-     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
-+  { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
-+    RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
-+  { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
-+    RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
-+  { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
-+    RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI },
-   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF,
-     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI },
-   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF,
-@@ -3267,6 +3383,8 @@
- 
-   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF,
-     RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
-+  { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF,
-+    RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
-   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
-     RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
-   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
-@@ -3321,6 +3439,8 @@
- 
-   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF,
-     RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
-+  { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF,
-+    RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
-   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
-     RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
-   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
-@@ -3431,6 +3551,18 @@
-     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
-   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
-     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
-+  { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
-+    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
-+  { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
-+    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
-+  { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
-+    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
-+  { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
-+    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
-+  { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
-+    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
-+  { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
-+    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
-   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTFP_P,
-     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
-   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, VSX_BUILTIN_XVCMPGTDP_P,
-@@ -3889,6 +4021,8 @@
-   { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW,
-     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
-     RS6000_BTI_unsigned_V4SI, 0 },
-+  { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW,
-+    RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
- 
-   { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW,
-     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
-@@ -3895,6 +4029,8 @@
-   { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW,
-     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
-     RS6000_BTI_unsigned_V4SI, 0 },
-+  { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW,
-+    RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
- 
-   { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB,
-     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
-Index: gcc/config/rs6000/darwin.h
-===================================================================
---- a/src/gcc/config/rs6000/darwin.h	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/rs6000/darwin.h	(.../branches/gcc-4_9-branch)
-@@ -206,7 +206,11 @@
-     "vrsave", "vscr",							\
-     "spe_acc", "spefscr",                                               \
-     "sfp",								\
--    "tfhar", "tfiar", "texasr"						\
-+    "tfhar", "tfiar", "texasr",						\
-+    "rh0",  "rh1",  "rh2",  "rh3",  "rh4",  "rh5",  "rh6",  "rh7",	\
-+    "rh8",  "rh9",  "rh10", "rh11", "rh12", "rh13", "rh14", "rh15",	\
-+    "rh16", "rh17", "rh18", "rh19", "rh20", "rh21", "rh22", "rh23",	\
-+    "rh24", "rh25", "rh26", "rh27", "rh28", "rh29", "rh30", "rh31"	\
- }
- 
- /* This outputs NAME to FILE.  */
-Index: gcc/config/rs6000/rs6000.c
-===================================================================
---- a/src/gcc/config/rs6000/rs6000.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/rs6000/rs6000.c	(.../branches/gcc-4_9-branch)
-@@ -79,6 +79,7 @@
- #include "dumpfile.h"
- #include "cgraph.h"
- #include "target-globals.h"
-+#include "real.h"
- #if TARGET_XCOFF
- #include "xcoffout.h"  /* get declarations of xcoff_*_section_name */
- #endif
-@@ -6896,24 +6897,6 @@
-   if (GET_CODE (y) == UNSPEC
-       && XINT (y, 1) == UNSPEC_TOCREL)
-     {
--#ifdef ENABLE_CHECKING
--      if (REG_P (XVECEXP (y, 0, 1))
--	  && REGNO (XVECEXP (y, 0, 1)) == TOC_REGISTER)
--	{
--	  /* All good.  */
--	}
--      else if (GET_CODE (XVECEXP (y, 0, 1)) == DEBUG_EXPR)
--	{
--	  /* Weirdness alert.  df_note_compute can replace r2 with a
--	     debug_expr when this unspec is in a debug_insn.
--	     Seen in gcc.dg/pr51957-1.c  */
--	}
--      else
--	{
--	  debug_rtx (orig_x);
--	  abort ();
--	}
--#endif
-       y = XVECEXP (y, 0, 0);
- 
- #ifdef HAVE_AS_TLS
-@@ -16653,10 +16636,13 @@
- 	      : (offset + 0x8000 < 0x10000 - extra /* legitimate_address_p */
- 		 && (offset & 3) != 0))
- 	    {
-+	      /* -m32 -mpowerpc64 needs to use a 32-bit scratch register.  */
- 	      if (in_p)
--		sri->icode = CODE_FOR_reload_di_load;
-+		sri->icode = ((TARGET_32BIT) ? CODE_FOR_reload_si_load
-+			      : CODE_FOR_reload_di_load);
- 	      else
--		sri->icode = CODE_FOR_reload_di_store;
-+		sri->icode = ((TARGET_32BIT) ? CODE_FOR_reload_si_store
-+			      : CODE_FOR_reload_di_store);
- 	      sri->extra_cost = 2;
- 	      ret = NO_REGS;
- 	    }
-@@ -30922,6 +30908,23 @@
-   rs6000_do_expand_vec_perm (target, op0, op1, vmode, nelt, perm);
- }
- 
-+/* Scale a V2DF vector SRC by two to the SCALE and place in TGT.  */
-+void
-+rs6000_scale_v2df (rtx tgt, rtx src, int scale)
-+{
-+  HOST_WIDE_INT hwi_scale (scale);
-+  REAL_VALUE_TYPE r_pow;
-+  rtvec v = rtvec_alloc (2);
-+  rtx elt;
-+  rtx scale_vec = gen_reg_rtx (V2DFmode);
-+  (void)real_powi (&r_pow, DFmode, &dconst2, hwi_scale);
-+  elt = CONST_DOUBLE_FROM_REAL_VALUE (r_pow, DFmode);
-+  RTVEC_ELT (v, 0) = elt;
-+  RTVEC_ELT (v, 1) = elt;
-+  rs6000_expand_vector_init (scale_vec, gen_rtx_PARALLEL (V2DFmode, v));
-+  emit_insn (gen_mulv2df3 (tgt, src, scale_vec));
-+}
-+
- /* Return an RTX representing where to find the function value of a
-    function returning MODE.  */
- static rtx
-@@ -32550,6 +32553,14 @@
-   if (complement_op2_p)
-     op2 = gen_rtx_NOT (mode, op2);
- 
-+  /* For canonical RTL, if only one arm is inverted it is the first.  */
-+  if (!complement_op1_p && complement_op2_p)
-+    {
-+      rtx temp = op1;
-+      op1 = op2;
-+      op2 = temp;
-+    }
-+
-   bool_rtx = ((code == NOT)
- 	      ? gen_rtx_NOT (mode, op1)
- 	      : gen_rtx_fmt_ee (code, mode, op1, op2));
-Index: gcc/config/rs6000/vsx.md
-===================================================================
---- a/src/gcc/config/rs6000/vsx.md	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/rs6000/vsx.md	(.../branches/gcc-4_9-branch)
-@@ -260,6 +260,14 @@
-    UNSPEC_VSX_ROUND_IC
-    UNSPEC_VSX_SLDWI
-    UNSPEC_VSX_XXSPLTW
-+   UNSPEC_VSX_XXSPLTD
-+   UNSPEC_VSX_DIVSD
-+   UNSPEC_VSX_DIVUD
-+   UNSPEC_VSX_MULSD
-+   UNSPEC_VSX_XVCVSXDDP
-+   UNSPEC_VSX_XVCVUXDDP
-+   UNSPEC_VSX_XVCVDPSXDS
-+   UNSPEC_VSX_XVCVDPUXDS
-   ])
- 
- ;; VSX moves
-@@ -746,6 +754,34 @@
-   [(set_attr "type" "<VStype_simple>")
-    (set_attr "fp_type" "<VSfptype_mul>")])
- 
-+; Emulate vector with scalar for vec_mul in V2DImode
-+(define_insn_and_split "vsx_mul_v2di"
-+  [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa")
-+        (unspec:V2DI [(match_operand:V2DI 1 "vsx_register_operand" "wa")
-+                      (match_operand:V2DI 2 "vsx_register_operand" "wa")]
-+                     UNSPEC_VSX_MULSD))]
-+  "VECTOR_MEM_VSX_P (V2DImode)"
-+  "#"
-+  "VECTOR_MEM_VSX_P (V2DImode) && !reload_completed && !reload_in_progress"
-+  [(const_int 0)]
-+  "
-+{
-+  rtx op0 = operands[0];
-+  rtx op1 = operands[1];
-+  rtx op2 = operands[2];
-+  rtx op3 = gen_reg_rtx (DImode);
-+  rtx op4 = gen_reg_rtx (DImode);
-+  rtx op5 = gen_reg_rtx (DImode);
-+  emit_insn (gen_vsx_extract_v2di (op3, op1, GEN_INT (0)));
-+  emit_insn (gen_vsx_extract_v2di (op4, op2, GEN_INT (0)));
-+  emit_insn (gen_muldi3 (op5, op3, op4));
-+  emit_insn (gen_vsx_extract_v2di (op3, op1, GEN_INT (1)));
-+  emit_insn (gen_vsx_extract_v2di (op4, op2, GEN_INT (1)));
-+  emit_insn (gen_muldi3 (op3, op3, op4));
-+  emit_insn (gen_vsx_concat_v2di (op0, op5, op3));
-+}"
-+  [(set_attr "type" "vecdouble")])
-+
- (define_insn "*vsx_div<mode>3"
-   [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
-         (div:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")
-@@ -755,6 +791,61 @@
-   [(set_attr "type" "<VStype_div>")
-    (set_attr "fp_type" "<VSfptype_div>")])
- 
-+; Emulate vector with scalar for vec_div in V2DImode
-+(define_insn_and_split "vsx_div_v2di"
-+  [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa")
-+        (unspec:V2DI [(match_operand:V2DI 1 "vsx_register_operand" "wa")
-+                      (match_operand:V2DI 2 "vsx_register_operand" "wa")]
-+                     UNSPEC_VSX_DIVSD))]
-+  "VECTOR_MEM_VSX_P (V2DImode)"
-+  "#"
-+  "VECTOR_MEM_VSX_P (V2DImode) && !reload_completed && !reload_in_progress"
-+  [(const_int 0)]
-+  "
-+{
-+  rtx op0 = operands[0];
-+  rtx op1 = operands[1];
-+  rtx op2 = operands[2];
-+  rtx op3 = gen_reg_rtx (DImode);
-+  rtx op4 = gen_reg_rtx (DImode);
-+  rtx op5 = gen_reg_rtx (DImode);
-+  emit_insn (gen_vsx_extract_v2di (op3, op1, GEN_INT (0)));
-+  emit_insn (gen_vsx_extract_v2di (op4, op2, GEN_INT (0)));
-+  emit_insn (gen_divdi3 (op5, op3, op4));
-+  emit_insn (gen_vsx_extract_v2di (op3, op1, GEN_INT (1)));
-+  emit_insn (gen_vsx_extract_v2di (op4, op2, GEN_INT (1)));
-+  emit_insn (gen_divdi3 (op3, op3, op4));
-+  emit_insn (gen_vsx_concat_v2di (op0, op5, op3));
-+}"
-+  [(set_attr "type" "vecdiv")])
-+
-+(define_insn_and_split "vsx_udiv_v2di"
-+  [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa")
-+        (unspec:V2DI [(match_operand:V2DI 1 "vsx_register_operand" "wa")
-+                      (match_operand:V2DI 2 "vsx_register_operand" "wa")]
-+                     UNSPEC_VSX_DIVUD))]
-+  "VECTOR_MEM_VSX_P (V2DImode)"
-+  "#"
-+  "VECTOR_MEM_VSX_P (V2DImode) && !reload_completed && !reload_in_progress"
-+  [(const_int 0)]
-+  "
-+{
-+  rtx op0 = operands[0];
-+  rtx op1 = operands[1];
-+  rtx op2 = operands[2];
-+  rtx op3 = gen_reg_rtx (DImode);
-+  rtx op4 = gen_reg_rtx (DImode);
-+  rtx op5 = gen_reg_rtx (DImode);
-+  emit_insn (gen_vsx_extract_v2di (op3, op1, GEN_INT (0)));
-+  emit_insn (gen_vsx_extract_v2di (op4, op2, GEN_INT (0)));
-+  emit_insn (gen_udivdi3 (op5, op3, op4));
-+  emit_insn (gen_vsx_extract_v2di (op3, op1, GEN_INT (1)));
-+  emit_insn (gen_vsx_extract_v2di (op4, op2, GEN_INT (1)));
-+  emit_insn (gen_udivdi3 (op3, op3, op4));
-+  emit_insn (gen_vsx_concat_v2di (op0, op5, op3));
-+}"
-+  [(set_attr "type" "vecdiv")])
-+
- ;; *tdiv* instruction returning the FG flag
- (define_expand "vsx_tdiv<mode>3_fg"
-   [(set (match_dup 3)
-@@ -1268,6 +1359,102 @@
-   "xscvspdpn %x0,%x1"
-   [(set_attr "type" "fp")])
- 
-+;; Convert and scale (used by vec_ctf, vec_cts, vec_ctu for double/long long)
-+
-+(define_expand "vsx_xvcvsxddp_scale"
-+  [(match_operand:V2DF 0 "vsx_register_operand" "")
-+   (match_operand:V2DI 1 "vsx_register_operand" "")
-+   (match_operand:QI 2 "immediate_operand" "")]
-+  "VECTOR_UNIT_VSX_P (V2DFmode)"
-+{
-+  rtx op0 = operands[0];
-+  rtx op1 = operands[1];
-+  int scale = INTVAL(operands[2]);
-+  emit_insn (gen_vsx_xvcvsxddp (op0, op1));
-+  if (scale != 0)
-+    rs6000_scale_v2df (op0, op0, -scale);
-+  DONE;
-+})
-+
-+(define_insn "vsx_xvcvsxddp"
-+  [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa")
-+        (unspec:V2DF [(match_operand:V2DI 1 "vsx_register_operand" "wa")]
-+                     UNSPEC_VSX_XVCVSXDDP))]
-+  "VECTOR_UNIT_VSX_P (V2DFmode)"
-+  "xvcvsxddp %x0,%x1"
-+  [(set_attr "type" "vecdouble")])
-+
-+(define_expand "vsx_xvcvuxddp_scale"
-+  [(match_operand:V2DF 0 "vsx_register_operand" "")
-+   (match_operand:V2DI 1 "vsx_register_operand" "")
-+   (match_operand:QI 2 "immediate_operand" "")]
-+  "VECTOR_UNIT_VSX_P (V2DFmode)"
-+{
-+  rtx op0 = operands[0];
-+  rtx op1 = operands[1];
-+  int scale = INTVAL(operands[2]);
-+  emit_insn (gen_vsx_xvcvuxddp (op0, op1));
-+  if (scale != 0)
-+    rs6000_scale_v2df (op0, op0, -scale);
-+  DONE;
-+})
-+
-+(define_insn "vsx_xvcvuxddp"
-+  [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa")
-+        (unspec:V2DF [(match_operand:V2DI 1 "vsx_register_operand" "wa")]
-+                     UNSPEC_VSX_XVCVUXDDP))]
-+  "VECTOR_UNIT_VSX_P (V2DFmode)"
-+  "xvcvuxddp %x0,%x1"
-+  [(set_attr "type" "vecdouble")])
-+
-+(define_expand "vsx_xvcvdpsxds_scale"
-+  [(match_operand:V2DI 0 "vsx_register_operand" "")
-+   (match_operand:V2DF 1 "vsx_register_operand" "")
-+   (match_operand:QI 2 "immediate_operand" "")]
-+  "VECTOR_UNIT_VSX_P (V2DFmode)"
-+{
-+  rtx op0 = operands[0];
-+  rtx op1 = operands[1];
-+  rtx tmp = gen_reg_rtx (V2DFmode);
-+  int scale = INTVAL(operands[2]);
-+  if (scale != 0)
-+    rs6000_scale_v2df (tmp, op1, scale);
-+  emit_insn (gen_vsx_xvcvdpsxds (op0, tmp));
-+  DONE;
-+})
-+
-+(define_insn "vsx_xvcvdpsxds"
-+  [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa")
-+        (unspec:V2DI [(match_operand:V2DF 1 "vsx_register_operand" "wa")]
-+                     UNSPEC_VSX_XVCVDPSXDS))]
-+  "VECTOR_UNIT_VSX_P (V2DFmode)"
-+  "xvcvdpsxds %x0,%x1"
-+  [(set_attr "type" "vecdouble")])
-+
-+(define_expand "vsx_xvcvdpuxds_scale"
-+  [(match_operand:V2DI 0 "vsx_register_operand" "")
-+   (match_operand:V2DF 1 "vsx_register_operand" "")
-+   (match_operand:QI 2 "immediate_operand" "")]
-+  "VECTOR_UNIT_VSX_P (V2DFmode)"
-+{
-+  rtx op0 = operands[0];
-+  rtx op1 = operands[1];
-+  rtx tmp = gen_reg_rtx (V2DFmode);
-+  int scale = INTVAL(operands[2]);
-+  if (scale != 0)
-+    rs6000_scale_v2df (tmp, op1, scale);
-+  emit_insn (gen_vsx_xvcvdpuxds (op0, tmp));
-+  DONE;
-+})
-+
-+(define_insn "vsx_xvcvdpuxds"
-+  [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa")
-+        (unspec:V2DI [(match_operand:V2DF 1 "vsx_register_operand" "wa")]
-+                     UNSPEC_VSX_XVCVDPUXDS))]
-+  "VECTOR_UNIT_VSX_P (V2DFmode)"
-+  "xvcvdpuxds %x0,%x1"
-+  [(set_attr "type" "vecdouble")])
-+
- ;; Convert from 64-bit to 32-bit types
- ;; Note, favor the Altivec registers since the usual use of these instructions
- ;; is in vector converts and we need to use the Altivec vperm instruction.
-@@ -1921,6 +2108,22 @@
-   "xxspltw %x0,%x1,%2"
-   [(set_attr "type" "vecperm")])
- 
-+;; V2DF/V2DI splat for use by vec_splat builtin
-+(define_insn "vsx_xxspltd_<mode>"
-+  [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")
-+        (unspec:VSX_D [(match_operand:VSX_D 1 "vsx_register_operand" "wa")
-+	               (match_operand:QI 2 "u5bit_cint_operand" "i")]
-+                      UNSPEC_VSX_XXSPLTD))]
-+  "VECTOR_MEM_VSX_P (<MODE>mode)"
-+{
-+  if ((VECTOR_ELT_ORDER_BIG && INTVAL (operands[2]) == 0)
-+      || (!VECTOR_ELT_ORDER_BIG && INTVAL (operands[2]) == 1))
-+    return "xxpermdi %x0,%x1,%x1,0";
-+  else
-+    return "xxpermdi %x0,%x1,%x1,3";
-+}
-+  [(set_attr "type" "vecperm")])
-+
- ;; V4SF/V4SI interleave
- (define_insn "vsx_xxmrghw_<mode>"
-   [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?<VSa>")
-Index: gcc/config/rs6000/altivec.md
-===================================================================
---- a/src/gcc/config/rs6000/altivec.md	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/rs6000/altivec.md	(.../branches/gcc-4_9-branch)
-@@ -67,7 +67,7 @@
-    UNSPEC_VCTSXS
-    UNSPEC_VLOGEFP
-    UNSPEC_VEXPTEFP
--   UNSPEC_VLSDOI
-+   UNSPEC_VSLDOI
-    UNSPEC_VUNPACK_HI_SIGN
-    UNSPEC_VUNPACK_LO_SIGN
-    UNSPEC_VUNPACK_HI_SIGN_DIRECT
-@@ -2077,7 +2077,7 @@
-         (unspec:VM [(match_operand:VM 1 "register_operand" "v")
- 		    (match_operand:VM 2 "register_operand" "v")
- 		    (match_operand:QI 3 "immediate_operand" "i")]
--		  UNSPEC_VLSDOI))]
-+		  UNSPEC_VSLDOI))]
-   "TARGET_ALTIVEC"
-   "vsldoi %0,%1,%2,%3"
-   [(set_attr "type" "vecperm")])
-Index: gcc/config/rs6000/rs6000.md
-===================================================================
---- a/src/gcc/config/rs6000/rs6000.md	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/rs6000/rs6000.md	(.../branches/gcc-4_9-branch)
-@@ -8600,8 +8600,8 @@
-   [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
- 	(match_operator:BOOL_128 3 "boolean_operator"
- 	 [(not:BOOL_128
--	   (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP1>"))
--	  (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
-+	   (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))
-+	  (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>")]))]
-   "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
- {
-   if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
-@@ -8616,7 +8616,7 @@
-    && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
-   [(const_int 0)]
- {
--  rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false,
-+  rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, true,
- 			NULL_RTX);
-   DONE;
- }
-@@ -8638,14 +8638,14 @@
-   [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
- 	(match_operator:TI2 3 "boolean_operator"
- 	 [(not:TI2
--	   (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
--	  (match_operand:TI2 2 "int_reg_operand" "r,r,0")]))]
-+	   (match_operand:TI2 2 "int_reg_operand" "r,0,r"))
-+	  (match_operand:TI2 1 "int_reg_operand" "r,r,0")]))]
-   "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
-   "#"
-   "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
-   [(const_int 0)]
- {
--  rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false,
-+  rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, true,
- 			NULL_RTX);
-   DONE;
- }
-Index: gcc/config/rs6000/altivec.h
-===================================================================
---- a/src/gcc/config/rs6000/altivec.h	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/rs6000/altivec.h	(.../branches/gcc-4_9-branch)
-@@ -124,6 +124,7 @@
- #define vec_vcfux __builtin_vec_vcfux
- #define vec_cts __builtin_vec_cts
- #define vec_ctu __builtin_vec_ctu
-+#define vec_cpsgn __builtin_vec_copysign
- #define vec_expte __builtin_vec_expte
- #define vec_floor __builtin_vec_floor
- #define vec_loge __builtin_vec_loge
-@@ -214,8 +215,10 @@
- #define vec_lvsl __builtin_vec_lvsl
- #define vec_lvsr __builtin_vec_lvsr
- #define vec_max __builtin_vec_max
-+#define vec_mergee __builtin_vec_vmrgew
- #define vec_mergeh __builtin_vec_mergeh
- #define vec_mergel __builtin_vec_mergel
-+#define vec_mergeo __builtin_vec_vmrgow
- #define vec_min __builtin_vec_min
- #define vec_mladd __builtin_vec_mladd
- #define vec_msum __builtin_vec_msum
-@@ -319,6 +322,8 @@
- #define vec_sqrt __builtin_vec_sqrt
- #define vec_vsx_ld __builtin_vec_vsx_ld
- #define vec_vsx_st __builtin_vec_vsx_st
-+#define vec_xl __builtin_vec_vsx_ld
-+#define vec_xst __builtin_vec_vsx_st
- 
- /* Note, xxsldi and xxpermdi were added as __builtin_vsx_<xxx> functions
-    instead of __builtin_vec_<xxx>  */
-@@ -336,6 +341,7 @@
- #define vec_vadduqm __builtin_vec_vadduqm
- #define vec_vbpermq __builtin_vec_vbpermq
- #define vec_vclz __builtin_vec_vclz
-+#define vec_cntlz __builtin_vec_vclz
- #define vec_vclzb __builtin_vec_vclzb
- #define vec_vclzd __builtin_vec_vclzd
- #define vec_vclzh __builtin_vec_vclzh
-Index: gcc/config/arm/arm.c
-===================================================================
---- a/src/gcc/config/arm/arm.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/arm/arm.c	(.../branches/gcc-4_9-branch)
-@@ -28492,7 +28492,11 @@
- 
- 	  addr = plus_constant (Pmode, addr, delta);
- 	}
--      emit_move_insn (gen_frame_mem (Pmode, addr), source);
-+      /* The store needs to be marked as frame related in order to prevent
-+	 DSE from deleting it as dead if it is based on fp.  */
-+      rtx insn = emit_move_insn (gen_frame_mem (Pmode, addr), source);
-+      RTX_FRAME_RELATED_P (insn) = 1;
-+      add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (Pmode, LR_REGNUM));
-     }
- }
- 
-@@ -28544,7 +28548,11 @@
-       else
- 	addr = plus_constant (Pmode, addr, delta);
- 
--      emit_move_insn (gen_frame_mem (Pmode, addr), source);
-+      /* The store needs to be marked as frame related in order to prevent
-+	 DSE from deleting it as dead if it is based on fp.  */
-+      rtx insn = emit_move_insn (gen_frame_mem (Pmode, addr), source);
-+      RTX_FRAME_RELATED_P (insn) = 1;
-+      add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (Pmode, LR_REGNUM));
-     }
-   else
-     emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
-Index: gcc/config/arm/t-aprofile
-===================================================================
---- a/src/gcc/config/arm/t-aprofile	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/arm/t-aprofile	(.../branches/gcc-4_9-branch)
-@@ -88,6 +88,9 @@
- MULTILIB_MATCHES       += march?armv8-a=mcpu?cortex-a57
- MULTILIB_MATCHES       += march?armv8-a=mcpu?cortex-a57.cortex-a53
- 
-+# Arch Matches
-+MULTILIB_MATCHES       += march?armv8-a=march?armv8-a+crc
-+
- # FPU matches
- MULTILIB_MATCHES       += mfpu?vfpv3-d16=mfpu?vfpv3
- MULTILIB_MATCHES       += mfpu?vfpv3-d16=mfpu?vfpv3-fp16
-Index: gcc/config/arm/arm.h
-===================================================================
---- a/src/gcc/config/arm/arm.h	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/arm/arm.h	(.../branches/gcc-4_9-branch)
-@@ -74,8 +74,8 @@
- 	builtin_define_with_int_value (				\
- 	  "__ARM_SIZEOF_MINIMAL_ENUM",				\
- 	  flag_short_enums ? 1 : 4);				\
--	builtin_define_with_int_value (				\
--	  "__ARM_SIZEOF_WCHAR_T", WCHAR_TYPE_SIZE);		\
-+	builtin_define_type_sizeof ("__ARM_SIZEOF_WCHAR_T",	\
-+				    wchar_type_node);		\
- 	if (TARGET_ARM_ARCH_PROFILE)				\
- 	  builtin_define_with_int_value (			\
- 	    "__ARM_ARCH_PROFILE", TARGET_ARM_ARCH_PROFILE);	\
-@@ -2138,9 +2138,10 @@
-    ? reverse_condition_maybe_unordered (code) \
-    : reverse_condition (code))
- 
--/* The arm5 clz instruction returns 32.  */
--#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE)  ((VALUE) = 32, 1)
--#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE)  ((VALUE) = 32, 1)
-+#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
-+  ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE))
-+#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
-+  ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE))
- 
- #define CC_STATUS_INIT \
-   do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0)
-Index: gcc/config/arm/arm.md
-===================================================================
---- a/src/gcc/config/arm/arm.md	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/arm/arm.md	(.../branches/gcc-4_9-branch)
-@@ -125,9 +125,10 @@
- ; This can be "a" for ARM, "t" for either of the Thumbs, "32" for
- ; TARGET_32BIT, "t1" or "t2" to specify a specific Thumb mode.  "v6"
- ; for ARM or Thumb-2 with arm_arch6, and nov6 for ARM without
--; arm_arch6.  This attribute is used to compute attribute "enabled",
--; use type "any" to enable an alternative in all cases.
--(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,neon_for_64bits,avoid_neon_for_64bits,iwmmxt,iwmmxt2"
-+; arm_arch6.  "v6t2" for Thumb-2 with arm_arch6.  This attribute is
-+; used to compute attribute "enabled", use type "any" to enable an
-+; alternative in all cases.
-+(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,v6t2,neon_for_64bits,avoid_neon_for_64bits,iwmmxt,iwmmxt2"
-   (const_string "any"))
- 
- (define_attr "arch_enabled" "no,yes"
-@@ -162,6 +163,10 @@
- 	      (match_test "TARGET_32BIT && !arm_arch6"))
- 	 (const_string "yes")
- 
-+	 (and (eq_attr "arch" "v6t2")
-+	      (match_test "TARGET_32BIT && arm_arch6 && arm_arch_thumb2"))
-+	 (const_string "yes")
-+
- 	 (and (eq_attr "arch" "avoid_neon_for_64bits")
- 	      (match_test "TARGET_NEON")
- 	      (not (match_test "TARGET_PREFER_NEON_64BITS")))
-@@ -6961,8 +6966,8 @@
- 
- ;; Pattern to recognize insn generated default case above
- (define_insn "*movhi_insn_arch4"
--  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r")
--	(match_operand:HI 1 "general_operand"      "rI,K,r,mi"))]
-+  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m,r")
-+	(match_operand:HI 1 "general_operand"      "rI,K,n,r,mi"))]
-   "TARGET_ARM
-    && arm_arch4
-    && (register_operand (operands[0], HImode)
-@@ -6970,16 +6975,19 @@
-   "@
-    mov%?\\t%0, %1\\t%@ movhi
-    mvn%?\\t%0, #%B1\\t%@ movhi
-+   movw%?\\t%0, %L1\\t%@ movhi
-    str%(h%)\\t%1, %0\\t%@ movhi
-    ldr%(h%)\\t%0, %1\\t%@ movhi"
-   [(set_attr "predicable" "yes")
--   (set_attr "pool_range" "*,*,*,256")
--   (set_attr "neg_pool_range" "*,*,*,244")
-+   (set_attr "pool_range" "*,*,*,*,256")
-+   (set_attr "neg_pool_range" "*,*,*,*,244")
-+   (set_attr "arch" "*,*,v6t2,*,*")
-    (set_attr_alternative "type"
-                          [(if_then_else (match_operand 1 "const_int_operand" "")
-                                         (const_string "mov_imm" )
-                                         (const_string "mov_reg"))
-                           (const_string "mvn_imm")
-+                          (const_string "mov_imm")
-                           (const_string "store1")
-                           (const_string "load1")])]
- )
-Index: gcc/config/pa/predicates.md
-===================================================================
---- a/src/gcc/config/pa/predicates.md	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/pa/predicates.md	(.../branches/gcc-4_9-branch)
-@@ -528,20 +528,29 @@
- ;; This predicate is used for branch patterns that internally handle
- ;; register reloading.  We need to accept non-symbolic memory operands
- ;; after reload to ensure that the pattern is still valid if reload
--;; didn't find a hard register for the operand.
-+;; didn't find a hard register for the operand.  We also reject index
-+;; and lo_sum DLT address as these are invalid for move destinations.
- 
- (define_predicate "reg_before_reload_operand"
-   (match_code "reg,mem")
- {
-+  rtx op0;
-+
-   if (register_operand (op, mode))
-     return true;
- 
--  if (reload_completed
--      && memory_operand (op, mode)
--      && !symbolic_memory_operand (op, mode))
--    return true;
-+  if (!reload_in_progress && !reload_completed)
-+    return false;
- 
--  return false;
-+  if (! MEM_P (op))
-+    return false;
-+
-+  op0 = XEXP (op, 0);
-+
-+  return (memory_address_p (mode, op0)
-+	  && !IS_INDEX_ADDR_P (op0)
-+	  && !IS_LO_SUM_DLT_ADDR_P (op0)
-+	  && !symbolic_memory_operand (op, mode));
- })
- 
- ;; True iff OP is a register or const_0 operand for MODE.
-Index: gcc/config/pa/pa.md
-===================================================================
---- a/src/gcc/config/pa/pa.md	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/config/pa/pa.md	(.../branches/gcc-4_9-branch)
-@@ -123,7 +123,7 @@
- ;; type "binary" insns have two input operands (1,2) and one output (0)
- 
- (define_attr "type"
--  "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,sh_func_adrs,parallel_branch,fpstore_load,store_fpload"
-+  "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,sh_func_adrs,parallel_branch,fpstore_load,store_fpload,trap"
-   (const_string "binary"))
- 
- (define_attr "pa_combine_type"
-@@ -166,7 +166,7 @@
- ;; For conditional branches. Frame related instructions are not allowed
- ;; because they confuse the unwind support.
- (define_attr "in_branch_delay" "false,true"
--  (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch")
-+  (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch,trap")
- 		     (eq_attr "length" "4")
- 		     (not (match_test "RTX_FRAME_RELATED_P (insn)")))
- 		(const_string "true")
-@@ -175,7 +175,7 @@
- ;; Disallow instructions which use the FPU since they will tie up the FPU
- ;; even if the instruction is nullified.
- (define_attr "in_nullified_branch_delay" "false,true"
--  (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
-+  (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch,trap")
- 		     (eq_attr "length" "4")
- 		     (not (match_test "RTX_FRAME_RELATED_P (insn)")))
- 		(const_string "true")
-@@ -184,7 +184,7 @@
- ;; For calls and millicode calls.  Allow unconditional branches in the
- ;; delay slot.
- (define_attr "in_call_delay" "false,true"
--  (cond [(and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch")
-+  (cond [(and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch,trap")
- 	      (eq_attr "length" "4")
- 	      (not (match_test "RTX_FRAME_RELATED_P (insn)")))
- 	   (const_string "true")
-@@ -5331,6 +5331,15 @@
-   [(set_attr "type" "binary,binary")
-    (set_attr "length" "4,4")])
- 
-+;; Trap instructions.
-+
-+(define_insn "trap"
-+  [(trap_if (const_int 1) (const_int 0))]
-+  ""
-+  "{addit|addi,tc},<> 1,%%r0,%%r0"
-+  [(set_attr "type" "trap")
-+   (set_attr "length" "4")])
-+
- ;; Clobbering a "register_operand" instead of a match_scratch
- ;; in operand3 of millicode calls avoids spilling %r1 and
- ;; produces better code.
-@@ -8926,7 +8935,7 @@
- ;; strength reduction is used.  It is actually created when the instruction
- ;; combination phase combines the special loop test.  Since this insn
- ;; is both a jump insn and has an output, it must deal with its own
--;; reloads, hence the `m' constraints.  The `!' constraints direct reload
-+;; reloads, hence the `Q' constraints.  The `!' constraints direct reload
- ;; to not choose the register alternatives in the event a reload is needed.
- (define_insn "decrement_and_branch_until_zero"
-   [(set (pc)
-@@ -8933,7 +8942,7 @@
- 	(if_then_else
- 	  (match_operator 2 "comparison_operator"
- 	   [(plus:SI
--	      (match_operand:SI 0 "reg_before_reload_operand" "+!r,!*f,*m")
-+	      (match_operand:SI 0 "reg_before_reload_operand" "+!r,!*f,*Q")
- 	      (match_operand:SI 1 "int5_operand" "L,L,L"))
- 	    (const_int 0)])
- 	  (label_ref (match_operand 3 "" ""))
-@@ -9022,7 +9031,7 @@
- 	   [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
- 	  (label_ref (match_operand 3 "" ""))
- 	  (pc)))
--   (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
-+   (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*Q,!*q")
- 	(match_dup 1))]
-   ""
- "* return pa_output_movb (operands, insn, which_alternative, 0); "
-@@ -9094,7 +9103,7 @@
- 	   [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
- 	  (pc)
- 	  (label_ref (match_operand 3 "" ""))))
--   (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
-+   (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*Q,!*q")
- 	(match_dup 1))]
-   ""
- "* return pa_output_movb (operands, insn, which_alternative, 1); "
-Index: gcc/cfgrtl.c
-===================================================================
---- a/src/gcc/cfgrtl.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/cfgrtl.c	(.../branches/gcc-4_9-branch)
-@@ -1761,6 +1761,22 @@
-       && (any_uncondjump_p (q)
- 	  || single_succ_p (b)))
-     {
-+      rtx label, table;
-+
-+      if (tablejump_p (q, &label, &table))
-+	{
-+	  /* The label is likely mentioned in some instruction before
-+	     the tablejump and might not be DCEd, so turn it into
-+	     a note instead and move before the tablejump that is going to
-+	     be deleted.  */
-+	  const char *name = LABEL_NAME (label);
-+	  PUT_CODE (label, NOTE);
-+	  NOTE_KIND (label) = NOTE_INSN_DELETED_LABEL;
-+	  NOTE_DELETED_LABEL_NAME (label) = name;
-+	  reorder_insns (label, label, PREV_INSN (q));
-+	  delete_insn (table);
-+	}
-+
- #ifdef HAVE_cc0
-       /* If this was a conditional jump, we need to also delete
- 	 the insn that set cc0.  */
-Index: gcc/convert.c
-===================================================================
---- a/src/gcc/convert.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/convert.c	(.../branches/gcc-4_9-branch)
-@@ -97,6 +97,15 @@
-   enum built_in_function fcode = builtin_mathfn_code (expr);
-   tree itype = TREE_TYPE (expr);
- 
-+  if (TREE_CODE (expr) == COMPOUND_EXPR)
-+    {
-+      tree t = convert_to_real (type, TREE_OPERAND (expr, 1));
-+      if (t == TREE_OPERAND (expr, 1))
-+	return expr;
-+      return build2_loc (EXPR_LOCATION (expr), COMPOUND_EXPR, TREE_TYPE (t),
-+			 TREE_OPERAND (expr, 0), t);
-+    }    
-+
-   /* Disable until we figure out how to decide whether the functions are
-      present in runtime.  */
-   /* Convert (float)sqrt((double)x) where x is float into sqrtf(x) */
-@@ -403,6 +412,15 @@
-       return error_mark_node;
-     }
- 
-+  if (ex_form == COMPOUND_EXPR)
-+    {
-+      tree t = convert_to_integer (type, TREE_OPERAND (expr, 1));
-+      if (t == TREE_OPERAND (expr, 1))
-+	return expr;
-+      return build2_loc (EXPR_LOCATION (expr), COMPOUND_EXPR, TREE_TYPE (t),
-+			 TREE_OPERAND (expr, 0), t);
-+    }    
-+
-   /* Convert e.g. (long)round(d) -> lround(d).  */
-   /* If we're converting to char, we may encounter differing behavior
-      between converting from double->char vs double->long->char.
-@@ -891,6 +909,14 @@
- 
- 	if (TYPE_MAIN_VARIANT (elt_type) == TYPE_MAIN_VARIANT (subtype))
- 	  return expr;
-+	else if (TREE_CODE (expr) == COMPOUND_EXPR)
-+	  {
-+	    tree t = convert_to_complex (type, TREE_OPERAND (expr, 1));
-+	    if (t == TREE_OPERAND (expr, 1))
-+	      return expr;
-+	    return build2_loc (EXPR_LOCATION (expr), COMPOUND_EXPR,
-+			       TREE_TYPE (t), TREE_OPERAND (expr, 0), t);
-+	  }    
- 	else if (TREE_CODE (expr) == COMPLEX_EXPR)
- 	  return fold_build2 (COMPLEX_EXPR, type,
- 			      convert (subtype, TREE_OPERAND (expr, 0)),
-Index: gcc/graphite-interchange.c
-===================================================================
---- a/src/gcc/graphite-interchange.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/gcc/graphite-interchange.c	(.../branches/gcc-4_9-branch)
-@@ -31,7 +31,13 @@
- #include <isl/ilp.h>
- #include <cloog/cloog.h>
- #include <cloog/isl/domain.h>
-+#ifdef HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE
-+#include <isl/deprecated/int.h>
-+#include <isl/deprecated/aff_int.h>
-+#include <isl/deprecated/ilp_int.h>
-+#include <isl/deprecated/constraint_int.h>
- #endif
-+#endif
- 
- #include "system.h"
- #include "coretypes.h"
-Index: libgo/configure
-===================================================================
---- a/src/libgo/configure	(.../tags/gcc_4_9_2_release)
-+++ b/src/libgo/configure	(.../branches/gcc-4_9-branch)
-@@ -631,6 +631,8 @@
- LIBGO_IS_SPARC64_TRUE
- LIBGO_IS_SPARC_FALSE
- LIBGO_IS_SPARC_TRUE
-+LIBGO_IS_PPC64LE_FALSE
-+LIBGO_IS_PPC64LE_TRUE
- LIBGO_IS_PPC64_FALSE
- LIBGO_IS_PPC64_TRUE
- LIBGO_IS_PPC_FALSE
-@@ -11115,7 +11117,7 @@
-   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
-   lt_status=$lt_dlunknown
-   cat > conftest.$ac_ext <<_LT_EOF
--#line 11118 "configure"
-+#line 11120 "configure"
- #include "confdefs.h"
- 
- #if HAVE_DLFCN_H
-@@ -11221,7 +11223,7 @@
-   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
-   lt_status=$lt_dlunknown
-   cat > conftest.$ac_ext <<_LT_EOF
--#line 11224 "configure"
-+#line 11226 "configure"
- #include "confdefs.h"
- 
- #if HAVE_DLFCN_H
-@@ -13599,6 +13601,7 @@
- mips_abi=unknown
- is_ppc=no
- is_ppc64=no
-+is_ppc64le=no
- is_sparc=no
- is_sparc64=no
- is_x86_64=no
-@@ -13709,13 +13712,27 @@
- if ac_fn_c_try_compile "$LINENO"; then :
-   is_ppc=yes
- else
-+  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
-+/* end confdefs.h.  */
-+
-+#if defined(_BIG_ENDIAN) || defined(__BIG_ENDIAN__)
-+#error 64be
-+#endif
-+_ACEOF
-+if ac_fn_c_try_compile "$LINENO"; then :
-+  is_ppc64le=yes
-+else
-   is_ppc64=yes
- fi
- rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
-+fi
-+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
-     if test "$is_ppc" = "yes"; then
-       GOARCH=ppc
-+    elif test "$is_ppc64" = "yes"; then
-+      GOARCH=ppc64
-     else
--      GOARCH=ppc64
-+      GOARCH=ppc64le
-     fi
-     ;;
-   sparc*-*-*)
-@@ -13835,6 +13852,14 @@
-   LIBGO_IS_PPC64_FALSE=
- fi
- 
-+ if test $is_ppc64le = yes; then
-+  LIBGO_IS_PPC64LE_TRUE=
-+  LIBGO_IS_PPC64LE_FALSE='#'
-+else
-+  LIBGO_IS_PPC64LE_TRUE='#'
-+  LIBGO_IS_PPC64LE_FALSE=
-+fi
-+
-  if test $is_sparc = yes; then
-   LIBGO_IS_SPARC_TRUE=
-   LIBGO_IS_SPARC_FALSE='#'
-@@ -15591,6 +15616,10 @@
-   as_fn_error "conditional \"LIBGO_IS_PPC64\" was never defined.
- Usually this means the macro was only invoked conditionally." "$LINENO" 5
- fi
-+if test -z "${LIBGO_IS_PPC64LE_TRUE}" && test -z "${LIBGO_IS_PPC64LE_FALSE}"; then
-+  as_fn_error "conditional \"LIBGO_IS_PPC64LE\" was never defined.
-+Usually this means the macro was only invoked conditionally." "$LINENO" 5
-+fi
- if test -z "${LIBGO_IS_SPARC_TRUE}" && test -z "${LIBGO_IS_SPARC_FALSE}"; then
-   as_fn_error "conditional \"LIBGO_IS_SPARC\" was never defined.
- Usually this means the macro was only invoked conditionally." "$LINENO" 5
-Index: libgo/mksysinfo.sh
-===================================================================
---- a/src/libgo/mksysinfo.sh	(.../tags/gcc_4_9_2_release)
-+++ b/src/libgo/mksysinfo.sh	(.../branches/gcc-4_9-branch)
-@@ -174,6 +174,9 @@
- #ifdef TIOCGWINSZ
-   TIOCGWINSZ_val = TIOCGWINSZ,
- #endif
-+#ifdef TIOCSWINSZ
-+  TIOCSWINSZ_val = TIOCSWINSZ,
-+#endif
- #ifdef TIOCNOTTY
-   TIOCNOTTY_val = TIOCNOTTY,
- #endif
-@@ -192,6 +195,12 @@
- #ifdef TIOCSIG
-   TIOCSIG_val = TIOCSIG,
- #endif
-+#ifdef TCGETS
-+  TCGETS_val = TCGETS,
-+#endif
-+#ifdef TCSETS
-+  TCSETS_val = TCSETS,
-+#endif
- };
- EOF
- 
-@@ -780,6 +789,11 @@
-     echo 'const TIOCGWINSZ = _TIOCGWINSZ_val' >> ${OUT}
-   fi
- fi
-+if ! grep '^const TIOCSWINSZ' ${OUT} >/dev/null 2>&1; then
-+  if grep '^const _TIOCSWINSZ_val' ${OUT} >/dev/null 2>&1; then
-+    echo 'const TIOCSWINSZ = _TIOCSWINSZ_val' >> ${OUT}
-+  fi
-+fi
- if ! grep '^const TIOCNOTTY' ${OUT} >/dev/null 2>&1; then
-   if grep '^const _TIOCNOTTY_val' ${OUT} >/dev/null 2>&1; then
-     echo 'const TIOCNOTTY = _TIOCNOTTY_val' >> ${OUT}
-@@ -812,8 +826,18 @@
- fi
- 
- # The ioctl flags for terminal control
--grep '^const _TC[GS]ET' gen-sysinfo.go | \
-+grep '^const _TC[GS]ET' gen-sysinfo.go | grep -v _val | \
-     sed -e 's/^\(const \)_\(TC[GS]ET[^= ]*\)\(.*\)$/\1\2 = _\2/' >> ${OUT}
-+if ! grep '^const TCGETS' ${OUT} >/dev/null 2>&1; then
-+  if grep '^const _TCGETS_val' ${OUT} >/dev/null 2>&1; then
-+    echo 'const TCGETS = _TCGETS_val' >> ${OUT}
-+  fi
-+fi
-+if ! grep '^const TCSETS' ${OUT} >/dev/null 2>&1; then
-+  if grep '^const _TCSETS_val' ${OUT} >/dev/null 2>&1; then
-+    echo 'const TCSETS = _TCSETS_val' >> ${OUT}
-+  fi
-+fi
- 
- # ioctl constants.  Might fall back to 0 if TIOCNXCL is missing, too, but
- # needs handling in syscalls.exec.go.
-Index: libgo/configure.ac
-===================================================================
---- a/src/libgo/configure.ac	(.../tags/gcc_4_9_2_release)
-+++ b/src/libgo/configure.ac	(.../branches/gcc-4_9-branch)
-@@ -179,6 +179,7 @@
- mips_abi=unknown
- is_ppc=no
- is_ppc64=no
-+is_ppc64le=no
- is_sparc=no
- is_sparc64=no
- is_x86_64=no
-@@ -249,11 +250,18 @@
- #ifdef _ARCH_PPC64
- #error 64-bit
- #endif],
--[is_ppc=yes], [is_ppc64=yes])
-+[is_ppc=yes],
-+    [AC_COMPILE_IFELSE([
-+#if defined(_BIG_ENDIAN) || defined(__BIG_ENDIAN__)
-+#error 64be
-+#endif],
-+[is_ppc64le=yes],[is_ppc64=yes])])
-     if test "$is_ppc" = "yes"; then
-       GOARCH=ppc
-+    elif test "$is_ppc64" = "yes"; then
-+      GOARCH=ppc64
-     else
--      GOARCH=ppc64
-+      GOARCH=ppc64le
-     fi
-     ;;
-   sparc*-*-*)
-@@ -281,6 +289,7 @@
- AM_CONDITIONAL(LIBGO_IS_MIPSO64, test $mips_abi = o64)
- AM_CONDITIONAL(LIBGO_IS_PPC, test $is_ppc = yes)
- AM_CONDITIONAL(LIBGO_IS_PPC64, test $is_ppc64 = yes)
-+AM_CONDITIONAL(LIBGO_IS_PPC64LE, test $is_ppc64le = yes)
- AM_CONDITIONAL(LIBGO_IS_SPARC, test $is_sparc = yes)
- AM_CONDITIONAL(LIBGO_IS_SPARC64, test $is_sparc64 = yes)
- AM_CONDITIONAL(LIBGO_IS_X86_64, test $is_x86_64 = yes)
-Index: libgo/go/debug/elf/file_test.go
-===================================================================
---- a/src/libgo/go/debug/elf/file_test.go	(.../tags/gcc_4_9_2_release)
-+++ b/src/libgo/go/debug/elf/file_test.go	(.../branches/gcc-4_9-branch)
-@@ -261,6 +261,12 @@
- 		},
- 	},
- 	{
-+		"testdata/go-relocation-test-gcc447-ppc64.obj",
-+		[]relocationTestEntry{
-+			{0, &dwarf.Entry{Offset: 0xb, Tag: dwarf.TagCompileUnit, Children: true, Field: []dwarf.Field{dwarf.Field{Attr: dwarf.AttrProducer, Val: "GNU C 4.4.7 20120313 (Red Hat 4.4.7-4)"}, dwarf.Field{Attr: dwarf.AttrLanguage, Val: int64(1)}, dwarf.Field{Attr: dwarf.AttrName, Val: "t.c"}, dwarf.Field{Attr: dwarf.AttrCompDir, Val: "/tmp"}, dwarf.Field{Attr: dwarf.AttrLowpc, Val: uint64(0x0)}, dwarf.Field{Attr: dwarf.AttrHighpc, Val: uint64(0x24)}, dwarf.Field{Attr: dwarf.AttrStmtList, Val: int64(0)}}}},
-+		},
-+	},
-+	{
- 		"testdata/gcc-amd64-openbsd-debug-with-rela.obj",
- 		[]relocationTestEntry{
- 			{203, &dwarf.Entry{Offset: 0xc62, Tag: dwarf.TagMember, Children: false, Field: []dwarf.Field{{Attr: dwarf.AttrName, Val: "it_interval"}, {Attr: dwarf.AttrDeclFile, Val: int64(7)}, {Attr: dwarf.AttrDeclLine, Val: int64(236)}, {Attr: dwarf.AttrType, Val: dwarf.Offset(0xb7f)}, {Attr: dwarf.AttrDataMemberLoc, Val: []byte{0x23, 0x0}}}}},
-Index: libgo/go/debug/elf/file.go
-===================================================================
---- a/src/libgo/go/debug/elf/file.go	(.../tags/gcc_4_9_2_release)
-+++ b/src/libgo/go/debug/elf/file.go	(.../branches/gcc-4_9-branch)
-@@ -519,6 +519,9 @@
- 	if f.Class == ELFCLASS64 && f.Machine == EM_X86_64 {
- 		return f.applyRelocationsAMD64(dst, rels)
- 	}
-+	if f.Class == ELFCLASS64 && f.Machine == EM_PPC64 {
-+		return f.applyRelocationsPPC64(dst, rels)
-+	}
- 	if f.Class == ELFCLASS64 && f.Machine == EM_AARCH64 {
- 		return f.applyRelocationsARM64(dst, rels)
- 	}
-@@ -615,6 +618,47 @@
- 	return nil
- }
- 
-+func (f *File) applyRelocationsPPC64(dst []byte, rels []byte) error {
-+	// 24 is the size of Rela64.
-+	if len(rels)%24 != 0 {
-+		return errors.New("length of relocation section is not a multiple of Sym64Size")
-+	}
-+
-+	symbols, _, err := f.getSymbols(SHT_SYMTAB)
-+	if err != nil {
-+		return err
-+	}
-+
-+	b := bytes.NewBuffer(rels)
-+	var rela Rela64
-+
-+	for b.Len() > 0 {
-+		binary.Read(b, f.ByteOrder, &rela)
-+		symNo := rela.Info >> 32
-+		t := R_PPC64(rela.Info & 0xffff)
-+
-+		if symNo == 0 || symNo > uint64(len(symbols)) {
-+			continue
-+		}
-+		sym := &symbols[symNo-1]
-+
-+	switch t {
-+		case R_PPC64_ADDR64:
-+			if rela.Off+8 >= uint64(len(dst)) || rela.Addend < 0 {
-+				continue
-+			}
-+			f.ByteOrder.PutUint64(dst[rela.Off:rela.Off+8], uint64(rela.Addend) + uint64(sym.Value))
-+		case R_PPC64_ADDR32:
-+			if rela.Off+4 >= uint64(len(dst)) || rela.Addend < 0 {
-+				continue
-+			}
-+			f.ByteOrder.PutUint32(dst[rela.Off:rela.Off+4], uint32(rela.Addend) + uint32(sym.Value))
-+		}
-+	}
-+
-+	return nil
-+}
-+
- func (f *File) DWARF() (*dwarf.Data, error) {
- 	// There are many other DWARF sections, but these
- 	// are the required ones, and the debug/dwarf package
-@@ -637,7 +681,7 @@
- 	// If there's a relocation table for .debug_info, we have to process it
- 	// now otherwise the data in .debug_info is invalid for x86-64 objects.
- 	rela := f.Section(".rela.debug_info")
--	if rela != nil && rela.Type == SHT_RELA && (f.Machine == EM_X86_64 || f.Machine == EM_AARCH64) {
-+	if rela != nil && rela.Type == SHT_RELA && (f.Machine == EM_X86_64 || f.Machine == EM_AARCH64 || f.Machine == EM_PPC64) {
- 		data, err := rela.Data()
- 		if err != nil {
- 			return nil, err
-Index: libgo/go/debug/elf/testdata/go-relocation-test-gcc447-ppc64.obj
-===================================================================
-Cannot display: file marked as a binary type.
-svn:mime-type = application/octet-stream
-Index: libgo/go/debug/elf/testdata/go-relocation-test-gcc447-ppc64.obj
-===================================================================
---- a/src/libgo/go/debug/elf/testdata/go-relocation-test-gcc447-ppc64.obj	(.../tags/gcc_4_9_2_release)
-+++ b/src/libgo/go/debug/elf/testdata/go-relocation-test-gcc447-ppc64.obj	(.../branches/gcc-4_9-branch)
-
-Property changes on: libgo/go/debug/elf/testdata/go-relocation-test-gcc447-ppc64.obj
-___________________________________________________________________
-Added: svn:mime-type
-## -0,0 +1 ##
-+application/octet-stream
-\ No newline at end of property
-Index: libgo/go/debug/elf/elf.go
-===================================================================
---- a/src/libgo/go/debug/elf/elf.go	(.../tags/gcc_4_9_2_release)
-+++ b/src/libgo/go/debug/elf/elf.go	(.../branches/gcc-4_9-branch)
-@@ -1246,6 +1246,242 @@
- func (i R_386) String() string   { return stringName(uint32(i), r386Strings, false) }
- func (i R_386) GoString() string { return stringName(uint32(i), r386Strings, true) }
- 
-+// Relocation types for ppc64.
-+type R_PPC64 int
-+
-+const (
-+	R_PPC64_NONE                R_PPC64 = 0 /* No relocation. */
-+	R_PPC64_ADDR32              R_PPC64 = 1
-+	R_PPC64_ADDR24              R_PPC64 = 2
-+	R_PPC64_ADDR16              R_PPC64 = 3
-+	R_PPC64_ADDR16_LO           R_PPC64 = 4
-+	R_PPC64_ADDR16_HI           R_PPC64 = 5
-+	R_PPC64_ADDR16_HA           R_PPC64 = 6
-+	R_PPC64_ADDR14              R_PPC64 = 7
-+	R_PPC64_ADDR14_BRTAKEN      R_PPC64 = 8
-+	R_PPC64_ADDR14_BRNTAKEN     R_PPC64 = 9
-+	R_PPC64_REL24               R_PPC64 = 10
-+	R_PPC64_REL14               R_PPC64 = 11
-+	R_PPC64_REL14_BRTAKEN       R_PPC64 = 12
-+	R_PPC64_REL14_BRNTAKEN      R_PPC64 = 13
-+	R_PPC64_GOT16               R_PPC64 = 14
-+	R_PPC64_GOT16_LO            R_PPC64 = 15
-+	R_PPC64_GOT16_HI            R_PPC64 = 16
-+	R_PPC64_GOT16_HA            R_PPC64 = 17
-+				    
-+	R_PPC64_COPY                R_PPC64 = 19
-+	R_PPC64_GLOB_DAT            R_PPC64 = 20
-+	R_PPC64_JMP_SLOT            R_PPC64 = 21
-+	R_PPC64_RELATIVE            R_PPC64 = 22
-+				    
-+	R_PPC64_UADDR32             R_PPC64 = 24
-+	R_PPC64_UADDR16             R_PPC64 = 25
-+	R_PPC64_REL32               R_PPC64 = 26
-+	R_PPC64_PLT32               R_PPC64 = 27
-+	R_PPC64_PLTREL32            R_PPC64 = 28
-+	R_PPC64_PLT16_LO            R_PPC64 = 29
-+	R_PPC64_PLT16_HI            R_PPC64 = 30
-+	R_PPC64_PLT16_HA            R_PPC64 = 31
-+				    
-+	R_PPC64_SECTOFF             R_PPC64 = 33
-+	R_PPC64_SECTOFF_LO          R_PPC64 = 34
-+	R_PPC64_SECTOFF_HI          R_PPC64 = 35
-+	R_PPC64_SECTOFF_HA          R_PPC64 = 36
-+	R_PPC64_REL30	            R_PPC64 = 37
-+	R_PPC64_ADDR64		    R_PPC64 = 38
-+	R_PPC64_ADDR16_HIGHER	    R_PPC64 = 39
-+	R_PPC64_ADDR16_HIGHERA	    R_PPC64 = 40
-+	R_PPC64_ADDR16_HIGHEST	    R_PPC64 = 41
-+	R_PPC64_ADDR16_HIGHESTA     R_PPC64 = 42
-+	R_PPC64_UADDR64		    R_PPC64 = 43
-+	R_PPC64_REL64		    R_PPC64 = 44
-+	R_PPC64_PLT64		    R_PPC64 = 45
-+	R_PPC64_PLTREL64	    R_PPC64 = 46
-+	R_PPC64_TOC16		    R_PPC64 = 47
-+	R_PPC64_TOC16_LO	    R_PPC64 = 48
-+	R_PPC64_TOC16_HI	    R_PPC64 = 49
-+	R_PPC64_TOC16_HA	    R_PPC64 = 50
-+	R_PPC64_TOC		    R_PPC64 = 51
-+	R_PPC64_PLTGOT16	    R_PPC64 = 52
-+	R_PPC64_PLTGOT16_LO	    R_PPC64 = 53
-+	R_PPC64_PLTGOT16_HI	    R_PPC64 = 54
-+	R_PPC64_PLTGOT16_HA	    R_PPC64 = 55
-+				    
-+	R_PPC64_ADDR16_DS	    R_PPC64 = 56
-+	R_PPC64_ADDR16_LO_DS	    R_PPC64 = 57
-+	R_PPC64_GOT16_DS	    R_PPC64 = 58
-+	R_PPC64_GOT16_LO_DS	    R_PPC64 = 59
-+	R_PPC64_PLT16_LO_DS	    R_PPC64 = 60
-+	R_PPC64_SECTOFF_DS	    R_PPC64 = 61
-+	R_PPC64_SECTOFF_LO_DS	    R_PPC64 = 62
-+	R_PPC64_TOC16_DS	    R_PPC64 = 63
-+	R_PPC64_TOC16_LO_DS	    R_PPC64 = 64
-+	R_PPC64_PLTGOT16_DS	    R_PPC64 = 65
-+	R_PPC64_PLTGOT16_LO_DS	    R_PPC64 = 66
-+				    
-+	R_PPC64_TLS		    R_PPC64 = 67
-+	R_PPC64_DTPMOD64	    R_PPC64 = 68
-+	R_PPC64_TPREL16		    R_PPC64 = 69
-+	R_PPC64_TPREL16_LO 	    R_PPC64 = 70
-+	R_PPC64_TPREL16_HI          R_PPC64 = 71
-+	R_PPC64_TPREL16_HA          R_PPC64 = 72
-+	R_PPC64_TPREL64       	    R_PPC64 = 73
-+	R_PPC64_DTPREL16            R_PPC64 = 74
-+	R_PPC64_DTPREL16_LO   	    R_PPC64 = 75
-+	R_PPC64_DTPREL16_HI   	    R_PPC64 = 76
-+	R_PPC64_DTPREL16_HA         R_PPC64 = 77
-+	R_PPC64_DTPREL64            R_PPC64 = 78
-+	R_PPC64_GOT_TLSGD16    	    R_PPC64 = 79
-+	R_PPC64_GOT_TLSGD16_LO      R_PPC64 = 80
-+	R_PPC64_GOT_TLSGD16_HI      R_PPC64 = 81
-+	R_PPC64_GOT_TLSGD16_HA      R_PPC64 = 82
-+	R_PPC64_GOT_TLSLD16         R_PPC64 = 83
-+	R_PPC64_GOT_TLSLD16_LO      R_PPC64 = 84
-+	R_PPC64_GOT_TLSLD16_HI      R_PPC64 = 85
-+	R_PPC64_GOT_TLSLD16_HA      R_PPC64 = 86
-+	R_PPC64_GOT_TPREL16_DS      R_PPC64 = 87
-+	R_PPC64_GOT_TPREL16_LO_DS   R_PPC64 = 88
-+	R_PPC64_GOT_TPREL16_HI	    R_PPC64 = 89
-+	R_PPC64_GOT_TPREL16_HA      R_PPC64 = 90
-+	R_PPC64_GOT_DTPREL16_DS     R_PPC64 = 91
-+	R_PPC64_GOT_DTPREL16_LO_DS  R_PPC64 = 92
-+	R_PPC64_GOT_DTPREL16_HI     R_PPC64 = 93
-+	R_PPC64_GOT_DTPREL16_HA     R_PPC64 = 94
-+	R_PPC64_TPREL16_DS	    R_PPC64 = 95
-+	R_PPC64_TPREL16_LO_DS       R_PPC64 = 96
-+	R_PPC64_TPREL16_HIGHER      R_PPC64 = 97
-+	R_PPC64_TPREL16_HIGHERA     R_PPC64 = 98
-+	R_PPC64_TPREL16_HIGHEST     R_PPC64 = 99
-+	R_PPC64_TPREL16_HIGHESTA    R_PPC64 = 100
-+	R_PPC64_DTPREL16_DS	    R_PPC64 = 101
-+	R_PPC64_DTPREL16_LO_DS      R_PPC64 = 102
-+	R_PPC64_DTPREL16_HIGHER     R_PPC64 = 103
-+	R_PPC64_DTPREL16_HIGHERA    R_PPC64 = 104
-+	R_PPC64_DTPREL16_HIGHEST    R_PPC64 = 105
-+	R_PPC64_DTPREL16_HIGHESTA   R_PPC64 = 106
-+
-+	R_PPC64_GNU_VTINHERIT	    R_PPC64 = 253
-+	R_PPC64_GNU_VTENTRY	    R_PPC64 = 254
-+)
-+
-+var rppc64Strings = []intName{
-+        {0, "R_PPC64_NONE"},
-+	{1, "R_PPC64_ADDR32"},
-+	{2, "R_PPC64_ADDR24"},
-+	{3, "R_PPC64_ADDR16"},
-+	{4, "R_PPC64_ADDR16_LO"},
-+	{5, "R_PPC64_ADDR16_HI"},
-+	{6, "R_PPC64_ADDR16_HA"},
-+	{7, "R_PPC64_ADDR14"},
-+	{8, "R_PPC64_ADDR14_BRTAKEN"},
-+	{9, "R_PPC64_ADDR14_BRNTAKEN"},
-+	{10, "R_PPC64_REL24"},
-+	{11, "R_PPC64_REL14"},
-+	{12, "R_PPC64_REL14_BRTAKEN"},
-+	{13, "R_PPC64_REL14_BRNTAKEN"},
-+	{14, "R_PPC64_GOT16"},
-+	{15, "R_PPC64_GOT16_LO"},
-+	{16, "R_PPC64_GOT16_HI"},
-+	{17, "R_PPC64_GOT16_HA"},
-+
-+	{19, "R_PPC64_COPY"},
-+	{20, "R_PPC64_GLOB_DAT"},
-+	{21, "R_PPC64_JMP_SLOT"},
-+	{22, "R_PPC64_RELATIVE"},
-+
-+	{24, "R_PPC64_UADDR32"},
-+	{25, "R_PPC64_UADDR16"},
-+	{26, "R_PPC64_REL32"},
-+	{27, "R_PPC64_PLT32"},
-+	{28, "R_PPC64_PLTREL32"},
-+	{29, "R_PPC64_PLT16_LO"},
-+	{30, "R_PPC64_PLT16_HI"},
-+	{31, "R_PPC64_PLT16_HA"},
-+
-+	{33, "R_PPC64_SECTOFF"},
-+	{34, "R_PPC64_SECTOFF_LO"},
-+	{35, "R_PPC64_SECTOFF_HI"},
-+	{36, "R_PPC64_SECTOFF_HA"},
-+	{37, "R_PPC64_REL30"},
-+	{38, "R_PPC64_ADDR64"},
-+	{39, "R_PPC64_ADDR16_HIGHER"},
-+	{40, "R_PPC64_ADDR16_HIGHERA"},
-+	{41, "R_PPC64_ADDR16_HIGHEST"},
-+	{42, "R_PPC64_ADDR16_HIGHESTA"},
-+	{43, "R_PPC64_UADDR64"},
-+	{44, "R_PPC64_REL64"},
-+	{45, "R_PPC64_PLT64"},
-+	{46, "R_PPC64_PLTREL64"},
-+	{47, "R_PPC64_TOC16"},
-+	{48, "R_PPC64_TOC16_LO"},
-+	{49, "R_PPC64_TOC16_HI"},
-+	{50, "R_PPC64_TOC16_HA"},
-+	{51, "R_PPC64_TOC"},
-+	{52, "R_PPC64_PLTGOT16"},
-+	{53, "R_PPC64_PLTGOT16_LO"},
-+	{54, "R_PPC64_PLTGOT16_HI"},
-+	{55, "R_PPC64_PLTGOT16_HA"},
-+
-+	{56, "R_PPC64_ADDR16_DS"},
-+	{57, "R_PPC64_ADDR16_LO_DS"},
-+	{58, "R_PPC64_GOT16_DS"},
-+	{59, "R_PPC64_GOT16_LO_DS"},
-+	{60, "R_PPC64_PLT16_LO_DS"},
-+	{61, "R_PPC64_SECTOFF_DS"},
-+	{62, "R_PPC64_SECTOFF_LO_DS"},
-+	{63, "R_PPC64_TOC16_DS"},
-+	{64, "R_PPC64_TOC16_LO_DS"},
-+	{65, "R_PPC64_PLTGOT16_DS"},
-+	{66, "R_PPC64_PLTGOT16_LO_DS"},
-+
-+	{67, "R_PPC64_TLS"},
-+	{68, "R_PPC64_DTPMOD64"},
-+	{69, "R_PPC64_TPREL16"},
-+	{70, "R_PPC64_TPREL16_LO"},
-+	{71, "R_PPC64_TPREL16_HI"},
-+	{72, "R_PPC64_TPREL16_HA"},
-+	{73, "R_PPC64_TPREL64"},
-+	{74, "R_PPC64_DTPREL16"},
-+	{75, "R_PPC64_DTPREL16_LO"},
-+	{76, "R_PPC64_DTPREL16_HI"},
-+	{77, "R_PPC64_DTPREL16_HA"},
-+	{78, "R_PPC64_DTPREL64"},
-+	{79, "R_PPC64_GOT_TLSGD16"},
-+	{80, "R_PPC64_GOT_TLSGD16_LO"},
-+	{81, "R_PPC64_GOT_TLSGD16_HI"},
-+	{82, "R_PPC64_GOT_TLSGD16_HA"},
-+	{83, "R_PPC64_GOT_TLSLD16"},
-+	{84, "R_PPC64_GOT_TLSLD16_LO"},
-+	{85, "R_PPC64_GOT_TLSLD16_HI"},
-+	{86, "R_PPC64_GOT_TLSLD16_HA"},
-+	{87, "R_PPC64_GOT_TPREL16_DS"},
-+	{88, "R_PPC64_GOT_TPREL16_LO_DS"},
-+	{89, "R_PPC64_GOT_TPREL16_HI"},
-+	{90, "R_PPC64_GOT_TPREL16_HA"},
-+	{91, "R_PPC64_GOT_DTPREL16_DS"},
-+	{92, "R_PPC64_GOT_DTPREL16_LO_DS"},
-+	{93, "R_PPC64_GOT_DTPREL16_HI"},
-+	{94, "R_PPC64_GOT_DTPREL16_HA"},
-+	{95, "R_PPC64_TPREL16_DS"},
-+	{96, "R_PPC64_TPREL16_LO_DS"},
-+	{97, "R_PPC64_TPREL16_HIGHER"},
-+	{98, "R_PPC64_TPREL16_HIGHERA"},
-+	{99, "R_PPC64_TPREL16_HIGHEST"},
-+	{100, "R_PPC64_TPREL16_HIGHESTA"},
-+	{101, "R_PPC64_DTPREL16_DS"},
-+	{102, "R_PPC64_DTPREL16_LO_DS"},
-+	{103, "R_PPC64_DTPREL16_HIGHER"},
-+	{104, "R_PPC64_DTPREL16_HIGHERA"},
-+	{105, "R_PPC64_DTPREL16_HIGHEST"},
-+	{106, "R_PPC64_DTPREL16_HIGHESTA"},
-+
-+	{253, "R_PPC64_GNU_VTINHERIT"},
-+	{254, "R_PPC64_GNU_VTENTRY"},
-+}
-+
-+func (i R_PPC64) String() string   { return stringName(uint32(i), rppc64Strings, false) }
-+func (i R_PPC64) GoString() string { return stringName(uint32(i), rppc64Strings, true) }
-+
- // Relocation types for PowerPC.
- type R_PPC int
- 
-Index: libgo/go/go/build/syslist.go
-===================================================================
---- a/src/libgo/go/go/build/syslist.go	(.../tags/gcc_4_9_2_release)
-+++ b/src/libgo/go/go/build/syslist.go	(.../branches/gcc-4_9-branch)
-@@ -5,4 +5,4 @@
- package build
- 
- const goosList = "darwin dragonfly freebsd linux netbsd openbsd plan9 windows solaris "
--const goarchList = "386 amd64 arm arm64 alpha m68k mipso32 mipsn32 mipsn64 mipso64 ppc ppc64 sparc sparc64 "
-+const goarchList = "386 amd64 arm arm64 alpha m68k mipso32 mipsn32 mipsn64 mipso64 ppc ppc64 ppc64le sparc sparc64 "
-Index: Makefile.def
-===================================================================
---- a/src/Makefile.def	(.../tags/gcc_4_9_2_release)
-+++ b/src/Makefile.def	(.../branches/gcc-4_9-branch)
-@@ -296,6 +296,10 @@
- // Host modules specific to gcc.
- dependencies = { module=configure-gcc; on=configure-intl; };
- dependencies = { module=configure-gcc; on=all-gmp; };
-+dependencies = { module=configure-gcc; on=all-mpfr; };
-+dependencies = { module=configure-gcc; on=all-mpc; };
-+dependencies = { module=configure-gcc; on=all-isl; };
-+dependencies = { module=configure-gcc; on=all-cloog; };
- dependencies = { module=configure-gcc; on=all-lto-plugin; };
- dependencies = { module=configure-gcc; on=all-binutils; };
- dependencies = { module=configure-gcc; on=all-gas; };
-Index: libcpp/line-map.c
-===================================================================
---- a/src/libcpp/line-map.c	(.../tags/gcc_4_9_2_release)
-+++ b/src/libcpp/line-map.c	(.../branches/gcc-4_9-branch)
-@@ -527,10 +527,10 @@
- 	  && line_delta * ORDINARY_MAP_NUMBER_OF_COLUMN_BITS (map) > 1000)
-       || (max_column_hint >= (1U << ORDINARY_MAP_NUMBER_OF_COLUMN_BITS (map)))
-       || (max_column_hint <= 80
--	  && ORDINARY_MAP_NUMBER_OF_COLUMN_BITS (map) >= 10))
--    {
--      add_map = true;
--    }
-+	  && ORDINARY_MAP_NUMBER_OF_COLUMN_BITS (map) >= 10)
-+      || (highest > 0x60000000
-+	  && (set->max_column_hint || highest > 0x70000000)))
-+    add_map = true;
-   else
-     max_column_hint = set->max_column_hint;
-   if (add_map)
-@@ -541,7 +541,7 @@
- 	  /* If the column number is ridiculous or we've allocated a huge
- 	     number of source_locations, give up on column numbers. */
- 	  max_column_hint = 0;
--	  if (highest >0x70000000)
-+	  if (highest > 0x70000000)
- 	    return 0;
- 	  column_bits = 0;
- 	}
-Index: libcpp/ChangeLog
-===================================================================
---- a/src/libcpp/ChangeLog	(.../tags/gcc_4_9_2_release)
-+++ b/src/libcpp/ChangeLog	(.../branches/gcc-4_9-branch)
-@@ -1,3 +1,13 @@
-+2014-11-28  Jakub Jelinek  <jakub@redhat.com>
-+
-+	Backported from mainline
-+	2014-11-25  Jakub Jelinek  <jakub@redhat.com>
-+
-+	PR preprocessor/60436
-+	* line-map.c (linemap_line_start): If highest is above 0x60000000
-+	and we are still tracking columns or highest is above 0x70000000,
-+	force add_map.
-+
- 2014-10-30  Release Manager
- 
- 	* GCC 4.9.2 released.
-Index: libcpp/po/ChangeLog
-===================================================================
---- a/src/libcpp/po/ChangeLog	(.../tags/gcc_4_9_2_release)
-+++ b/src/libcpp/po/ChangeLog	(.../branches/gcc-4_9-branch)
-@@ -1,3 +1,7 @@
-+2014-11-07  Joseph Myers  <joseph@codesourcery.com>
-+
-+	* ja.po: Update.
-+
- 2014-10-30  Release Manager
- 
- 	* GCC 4.9.2 released.
-Index: libcpp/po/ja.po
-===================================================================
---- a/src/libcpp/po/ja.po	(.../tags/gcc_4_9_2_release)
-+++ b/src/libcpp/po/ja.po	(.../branches/gcc-4_9-branch)
-@@ -4,15 +4,15 @@
- # Daisuke Yamashita <yamad@mb.infoweb.ne.jp>, 1999-2001
- #    Masahito Yamaga <yamaga@ipc.chiba-u.ac.jp>, 1999.
- #    IIDA Yosiaki <iida@secom.ne.jp>, 1999.
--# Yasuaki Taniguchi <yasuakit@gmail.com>, 2010, 2011.
- # Takeshi Hamasaki <hmatrjp@users.sourceforge.jp>, 2012, 2013
-+# Yasuaki Taniguchi <yasuakit@gmail.com>, 2010, 2011, 2014.
- msgid ""
- msgstr ""
--"Project-Id-Version: cpplib 4.8-b20130224\n"
-+"Project-Id-Version: cpplib 4.9-b20140202\n"
- "Report-Msgid-Bugs-To: http://gcc.gnu.org/bugs.html\n"
- "POT-Creation-Date: 2014-02-02 17:35+0000\n"
--"PO-Revision-Date: 2013-03-04 18:01+0900\n"
--"Last-Translator: Takeshi Hamasaki <hmatrjp@users.sourceforge.jp>\n"
-+"PO-Revision-Date: 2014-11-07 08:19+0000\n"
-+"Last-Translator: Yasuaki Taniguchi <yasuakit@gmail.com>\n"
- "Language-Team: Japanese <translation-team-ja@lists.sourceforge.net>\n"
- "Language: ja\n"
- "MIME-Version: 1.0\n"
-@@ -19,7 +19,6 @@
- "Content-Type: text/plain; charset=UTF-8\n"
- "Content-Transfer-Encoding: 8bit\n"
- "Plural-Forms: nplurals=1; plural=0;\n"
--"X-Generator: Poedit 1.5.4\n"
- 
- #: charset.c:673
- #, c-format
-@@ -456,10 +455,8 @@
- msgstr "整数定数に無効な接尾辞 \"%.*s\" があります"
- 
- #: expr.c:667
--#, fuzzy
--#| msgid "use of C++0x long long integer constant"
- msgid "use of C++11 long long integer constant"
--msgstr "C++0x の long long 整数定数を使用しています"
-+msgstr "C++11 の long long 整数定数を使用しています"
- 
- #: expr.c:668
- msgid "use of C99 long long integer constant"
-@@ -470,10 +467,8 @@
- msgstr "虚数定数は GCC 拡張です"
- 
- #: expr.c:690
--#, fuzzy
--#| msgid "binary constants are a GCC extension"
- msgid "binary constants are a C++1y feature or GCC extension"
--msgstr "二進定数は GCC 拡張です"
-+msgstr "二進定数は C++1y の機能または GCC 拡張です"
- 
- #: expr.c:787
- msgid "integer constant is too large for its type"
-@@ -703,10 +698,8 @@
- msgstr "生の文字列区切りが 16 文字より大きいです"
- 
- #: lex.c:1558
--#, fuzzy
--#| msgid "invalid character '%c' in raw string delimiter"
- msgid "invalid new-line in raw string delimiter"
--msgstr "生の文字列区切り内に無効な文字 '%c' があります"
-+msgstr "生の文字列区切り内に無効な改行があります"
- 
- #: lex.c:1562
- #, c-format
-@@ -718,10 +711,8 @@
- msgstr "終端されていない生の文字列です"
- 
- #: lex.c:1654 lex.c:1783
--#, fuzzy
--#| msgid "invalid suffix on literal; C++11 requires a space between literal and identifier"
- msgid "invalid suffix on literal; C++11 requires a space between literal and string macro"
--msgstr "リテラルの接尾辞が無効です。C++11 では、リテラルと識別子の間にスペースを入れる必要があります。"
-+msgstr "リテラルの接尾辞が無効です。C++11 では、リテラルと文字列マクロの間にスペースを入れる必要があります。"
- 
- #: lex.c:1765
- msgid "null character(s) preserved in literal"
-@@ -762,7 +753,7 @@
- #: macro.c:236 macro.c:333
- #, c-format
- msgid "macro \"%s\" might prevent reproducible builds"
--msgstr ""
-+msgstr "マクロ \"%s\" は再生性可能なビルドを阻害するかもしれません"
- 
- #: macro.c:267
- msgid "could not determine file timestamp"
diff --git a/debian/patches/sys-auxv-header.diff b/debian/patches/sys-auxv-header.diff
index c2ca6c5..3034f29 100644
--- a/debian/patches/sys-auxv-header.diff
+++ b/debian/patches/sys-auxv-header.diff
@@ -4,7 +4,7 @@ Index: b/src/gcc/configure.ac
 ===================================================================
 --- a/src/gcc/configure.ac
 +++ b/src/gcc/configure.ac
-@@ -941,6 +941,7 @@ AC_HEADER_TIOCGWINSZ
+@@ -1032,6 +1032,7 @@ AC_HEADER_TIOCGWINSZ
  AC_CHECK_HEADERS(limits.h stddef.h string.h strings.h stdlib.h time.h iconv.h \
  		 fcntl.h unistd.h sys/file.h sys/time.h sys/mman.h \
  		 sys/resource.h sys/param.h sys/times.h sys/stat.h \
@@ -16,7 +16,7 @@ Index: b/src/gcc/config.in
 ===================================================================
 --- a/src/gcc/config.in
 +++ b/src/gcc/config.in
-@@ -1502,6 +1502,12 @@
+@@ -1610,6 +1610,12 @@
  #endif
  
  
diff --git a/debian/rules b/debian/rules
index 1636c6d..c1cccc6 100755
--- a/debian/rules
+++ b/debian/rules
@@ -29,6 +29,8 @@ $(configure_stamp): control $(unpack_stamp) $(patch_stamp)
 	$(MAKE) -f debian/rules2 $@
 $(configure_dummy_stamp): control
 	$(MAKE) -f debian/rules2 $@
+$(configure_jit_stamp): control
+	$(MAKE) -f debian/rules2 $@
 $(configure_hppa64_stamp): $(build_stamp)
 	$(MAKE) -f debian/rules2 $@
 $(configure_neon_stamp): $(build_stamp)
@@ -50,6 +52,8 @@ $(build_stamp): $(unpack_stamp) $(patch_stamp) $(configure_stamp)
 	$(MAKE) -f debian/rules2 $@
 $(build_dummy_stamp): $(configure_dummy_stamp)
 	$(MAKE) -f debian/rules2 $@
+$(build_jit_stamp): $(configure_jit_stamp)
+	$(MAKE) -f debian/rules2 $@
 $(build_javadoc_stamp): $(build_stamp)
 	$(MAKE) -f debian/rules2 $@
 $(build_hppa64_stamp): $(configure_hppa64_stamp)
@@ -82,6 +86,8 @@ $(install_snap_stamp): $(build_stamp)
 	$(MAKE) -f debian/rules2 $@
 $(install_dummy_stamp): $(build_dummy_stamp)
 	$(MAKE) -f debian/rules2 $@
+$(install_jit_stamp): $(build_jit_stamp)
+	$(MAKE) -f debian/rules2 $@
 $(install_hppa64_stamp): $(build_hppa64_stamp)
 	$(MAKE) -f debian/rules2 $@
 $(install_neon_stamp): $(build_neon_stamp)
diff --git a/debian/rules.conf b/debian/rules.conf
index 5ad66b0..0586bbd 100644
--- a/debian/rules.conf
+++ b/debian/rules.conf
@@ -136,7 +136,7 @@ linux_no_archs := !hurd-any !kfreebsd-any
 
 GCC_VERSION := $(strip $(shell cat $(firstword $(wildcard $(srcdir)/gcc/FULL-VER $(srcdir)/gcc/BASE-VER))))
 NEXT_GCC_VERSION := $(shell echo $(GCC_VERSION) | \
-	awk -F. '{OFS="."; if (NF==2) $$3=1; else $$NF += 1; print}')
+	awk -F. '{OFS="."; $$2 += 1; $$3=0; print}')
 GCC_MAJOR_VERSION := $(shell echo $(GCC_VERSION)   | sed -r 's/([0-9])\.[0-9]\.[0-9]/\1/')
 GCC_MINOR_VERSION := $(shell echo $(GCC_VERSION)   | sed -r 's/[0-9]\.([0-9])\.[0-9]/\1/')
 GCC_RELEASE_VERSION := $(shell echo $(GCC_VERSION) | sed -r 's/[0-9]\.[0-9]\.([0-9])/\1/')
@@ -150,7 +150,7 @@ endif
 
 GCC_SOURCE_VERSION := $(shell echo $(DEB_VERSION) | sed 's/-.*//')
 NEXT_GCC_SOURCE_VERSION := $(shell echo $(GCC_SOURCE_VERSION) | \
-	awk -F. '{OFS="."; if (NF==2) $$3=1; else $$NF += 1; print}')
+	awk -F. '{OFS="."; $$2 += 1; $$3=0; print}')
 
 MAINTAINER = Debian GCC Maintainers <debian-gcc@lists.debian.org>
 ifeq ($(distribution),Ubuntu)
@@ -411,8 +411,8 @@ ifneq (,$(java_awt_peers))
   JAVA_BUILD_DEP += fastjar$(bd_java_archs), libmagic-dev$(bd_java_archs),
   JAVA_BUILD_DEP += libecj-java (>= 3.3.0-2)$(bd_java_archs), zip$(bd_java_archs),
   ifeq ($(with_java_maintainer_mode),yes)
-    # gcj-4.9 needed for gjavah-4.9.
-    JAVA_BUILD_DEP += gcj-4.9$(bd_java_archs), ecj (>= 3.3.0-2)$(bd_java_archs),
+    # gcj-5 needed for gjavah-5.
+    JAVA_BUILD_DEP += gcj-5$(bd_java_archs), ecj (>= 3.3.0-2)$(bd_java_archs),
   endif
   JAVA_BUILD_DEP += libasound2-dev [$(java_no_archs) $(linux_no_archs)],
   ifneq (,$(findstring gtk,$(java_awt_peers)))
@@ -427,7 +427,7 @@ ifneq (,$(java_awt_peers))
   #JAVA_BUILD_DEP += libgstreamer-plugins-base0.10-dev$(bd_java_archs),
   # FIXME ... necessary only when built from separate source?
   #ifneq ($(single_package),yes)
-  #  JAVA_BUILD_DEP += g++-4.9 [armel armhf],
+  #  JAVA_BUILD_DEP += g++-5 [armel armhf],
   #endif
 endif
 ifneq ($(with_standalone_gcj),yes)
@@ -477,7 +477,7 @@ ifeq ($(PKGSOURCE),gcc-$(BASE_VERSION))
     # Build gnat as part of the combiled gcc-x.y source package.  Do not fail
     # if gnat is not present on unsupported architectures; the build scripts
     # will not use gnat anyway.
-    GNAT_BUILD_DEP := gnat-4.9 [$(ada_no_archs)],
+    GNAT_BUILD_DEP := gnat-5 [$(ada_no_archs)],
   endif
 else ifeq ($(single_package),yes)
   # Ditto, as part of the gcc-snapshot package.
@@ -534,8 +534,8 @@ NEXT_GCC_VERSION := $(shell echo $(GCC_VERSION) | \
 		awk -F. '{OFS="."; if (NF==2) $$3=1; else $$NF += 1; print}')
 # first version with a new path component in gcc_lib_dir (i.e. GCC_VERSION
 # or TARGET_ALIAS changes), or last version available for all architectures
-DEB_GCC_SOFT_VERSION := 4.9
-DEB_GCJ_SOFT_VERSION := 4.9
+DEB_GCC_SOFT_VERSION := 5
+DEB_GCJ_SOFT_VERSION := 5
 
 ifeq ($(with_d),yes)
   GDC_VERSION := $(BASE_VERSION)
@@ -544,10 +544,10 @@ endif
 
 # semiautomatic ...
 DEB_SOVERSION		:= $(DEB_VERSION)
-DEB_SOVERSION		:= 4.9
-DEB_SOEVERSION		:= $(EPOCH):4.9
-DEB_STDCXX_SOVERSION	:= 4.9
-DEB_GCJ_SOVERSION	:= 4.9
+DEB_SOVERSION		:= 5
+DEB_SOEVERSION		:= $(EPOCH):5
+DEB_STDCXX_SOVERSION	:= 5
+DEB_GCJ_SOVERSION	:= 5
 DEB_GOMP_SOVERSION	:= $(DEB_SOVERSION)
 DEB_GCCMATH_SOVERSION	:= $(DEB_SOVERSION)
 
@@ -770,6 +770,9 @@ ifeq ($(with_libqmath),yes)
   addons += $(if $(findstring armel,$(biarchhfarchs)),libhfqmath)
   addons += $(if $(findstring armhf,$(biarchsfarchs)),libsfqmath)
 endif
+ifeq ($(with_jit),yes)
+  addons += libjit
+endif
 ifeq ($(with_d),yes)
   languages += d
   ifeq ($(with_libphobos),yes)
@@ -920,6 +923,8 @@ control-file:
 	  -DQMATH_SO=$(QUADMATH_SONAME) \
 	  -DSSP_SO=$(SSP_SONAME) \
 	  -DGO_SO=$(GO_SONAME) \
+	  -DCC1_SO=$(CC1_SONAME) \
+	  -DGCCJIT_SO=$(GCCJIT_SONAME) \
 	  -Denabled_languages="$(languages) $(addons)" \
 	  -Dada_no_archs="$(ada_no_archs)" \
 	  -Djava_no_archs="$(java_no_archs)" \
@@ -1213,6 +1218,8 @@ parameters-file:
 		echo 'QMATH_SONAME	:= $(QUADMATH_SONAME)'; \
 		echo 'GCCMATH_SONAME	:= $(GCCMATH_SONAME)'; \
 		echo 'GO_SONAME		:= $(GO_SONAME)'; \
+		echo 'CC1_SONAME	:= $(CC1_SONAME)'; \
+		echo 'GCCJIT_SONAME	:= $(GCCJIT_SONAME)'; \
 		echo 'LIBC_DEP		:= $(LIBC_DEP)'; \
 	) > debian/rules.parameters.tmp
 	[ -e debian/rules.parameters ] \
diff --git a/debian/rules.d/binary-gcc.mk b/debian/rules.d/binary-gcc.mk
index 14aaf6a..a8fbbc0 100644
--- a/debian/rules.d/binary-gcc.mk
+++ b/debian/rules.d/binary-gcc.mk
@@ -5,7 +5,7 @@ ifeq ($(with_plugins),yes)
   arch_binaries  := $(arch_binaries) gcc-plugindev
 endif
 
-arch_binaries  := $(arch_binaries) gcc
+arch_binaries  := $(arch_binaries) libcc1 gcc
 
 ifneq ($(DEB_CROSS),yes)
   ifneq ($(GFDL_INVARIANT_FREE),yes)
@@ -29,7 +29,7 @@ dirs_gcc = \
 
 # XXX: what about triarch mapping?
 files_gcc = \
-	$(PF)/bin/$(cmd_prefix){gcc,gcov}$(pkg_ver) \
+	$(PF)/bin/$(cmd_prefix){gcc,gcov,gcov-tool}$(pkg_ver) \
 	$(PF)/bin/$(cmd_prefix)gcc-{ar,ranlib,nm}$(pkg_ver) \
 	$(PF)/share/man/man1/$(cmd_prefix)gcc-{ar,nm,ranlib}$(pkg_ver).1 \
 	$(gcc_lexec_dir)/{collect2,lto1,lto-wrapper} \
@@ -65,6 +65,9 @@ d_gcc_m	= debian/$(p_gcc_m)
 p_pld	= gcc$(pkg_ver)-plugin-dev$(cross_bin_arch)
 d_pld	= debian/$(p_pld)
 
+p_cc1	= libcc1-$(CC1_SONAME)
+d_cc1	= debian/$(p_cc1)
+
 # ----------------------------------------------------------------------
 $(binary_stamp)-gcc: $(install_dependencies)
 	dh_testdir
@@ -113,8 +116,12 @@ endif
 
 	DH_COMPAT=2 dh_movefiles -p$(p_gcc) $(files_gcc)
 
+	rm -f $(d)/$(usr_lib)/libcc1.so
+	dh_link -p$(p_gcc) \
+		/$(usr_lib)/libcc1.so.$(CC1_SO) /$(gcc_lib_dir)/libcc1.so
+
 ifneq ($(DEB_CROSS),yes)
-	for i in gcc gcov gcc-ar gcc-nm gcc-ranlib; do \
+	for i in gcc gcov gcov-tool gcc-ar gcc-nm gcc-ranlib; do \
 	  ln -sf $$i$(pkg_ver) \
 	    $(d_gcc)/$(PF)/bin/$(DEB_TARGET_GNU_TYPE)-$$i$(pkg_ver); \
 	  ln -sf $$i$(pkg_ver) \
@@ -197,6 +204,34 @@ $(binary_stamp)-gcc-multi: $(install_dependencies)
 	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
 
 # ----------------------------------------------------------------------
+$(binary_stamp)-libcc1: $(install_dependencies)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_cc1)
+	dh_installdirs -p$(p_cc1) \
+		$(docdir) \
+		$(usr_lib)
+	DH_COMPAT=2 dh_movefiles -p$(p_cc1) \
+		$(usr_lib)/libcc1.so.*
+
+	debian/dh_doclink -p$(p_cc1) $(p_xbase)
+	debian/dh_rmemptydirs -p$(p_cc1)
+
+	dh_strip -p$(p_cc1)
+	dh_compress -p$(p_cc1)
+	dh_makeshlibs -p$(p_cc1)
+	dh_shlibdeps -p$(p_cc1)
+	dh_fixperms -p$(p_cc1)
+	dh_installdeb -p$(p_cc1)
+	dh_gencontrol -p$(p_cc1) -- -v$(DEB_VERSION) $(common_substvars)
+	dh_md5sums -p$(p_cc1)
+	dh_builddeb -p$(p_cc1)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
 $(binary_stamp)-gcc-plugindev: $(install_dependencies)
 	dh_testdir
 	dh_testroot
diff --git a/debian/rules.d/binary-go.mk b/debian/rules.d/binary-go.mk
index 6226ccb..6b210fa 100644
--- a/debian/rules.d/binary-go.mk
+++ b/debian/rules.d/binary-go.mk
@@ -42,7 +42,8 @@ dirs_go = \
 	$(PF)/include \
 	$(PF)/share/man/man1
 files_go = \
-	$(PF)/bin/$(cmd_prefix)gccgo$(pkg_ver) \
+	$(PF)/bin/$(cmd_prefix){gccgo,go,gofmt}$(pkg_ver) \
+	$(gcc_lexec_dir)/cgo \
 	$(gcc_lexec_dir)/go1
 
 ifneq ($(GFDL_INVARIANT_FREE),yes)
@@ -203,11 +204,14 @@ $(binary_stamp)-gccgo: $(install_stamp)
 
 	$(call do_go_dev,,$(p_go))
 
+	mv $(d)/$(gcc_lexec_dir)/cgo$(pkg_ver) $(d)/$(gcc_lexec_dir)/cgo
+
 	DH_COMPAT=2 dh_movefiles -p$(p_go) $(files_go)
 
 ifneq (,$(findstring gccgo,$(PKGSOURCE)))
 	rm -rf $(d_go)/$(gcc_lib_dir)/include/cilk
 	rm -rf $(d_go)/$(gcc_lib_dir)/include/omp.h
+	rm -rf $(d_go)/$(gcc_lib_dir)/include/openacc.h
 endif
 
 ifneq ($(DEB_CROSS),yes)
@@ -248,7 +252,7 @@ endif
 #		$(d_go)/$(docdir)/$(p_base)/go/changelog
 	debian/dh_rmemptydirs -p$(p_go)
 
-	dh_strip -p$(p_go)
+	dh_strip -p$(p_go) -X/cgo -Xgo$(pkg_ver) -Xgofmt$(pkg_ver)
 	dh_compress -p$(p_go)
 	dh_fixperms -p$(p_go)
 	dh_shlibdeps -p$(p_go)
diff --git a/debian/rules.d/binary-libgcc.mk b/debian/rules.d/binary-libgcc.mk
index 44a4aad..a2c78bb 100644
--- a/debian/rules.d/binary-libgcc.mk
+++ b/debian/rules.d/binary-libgcc.mk
@@ -51,7 +51,9 @@ header_files = \
 		    {,a,b,e,i,n,p,s,t,w,x}mmintrin.h mmintrin-common.h \
 		    {abm,adx,avx,avx2,bmi,bmi2,f16c,fma,fma4,fxsr,ia32,}intrin.h \
 		    {lwp,lzcnt,popcnt,prfchw,rdseed,rtm,tbm,x86,xop,xsave{,opt},xtest,}intrin.h \
-		    {htm,htmxl,sha}intrin.h avx512{er,cd,f,pf}intrin.h \
+		    {htm,htmxl,sha}intrin.h \
+		    avx512{bw,er,cd,dq,f,ifma,ifmavl,pf,vlbw,vbmi,vldq,vbmivl,vl}intrin.h \
+		    {clflushopt,clwb,pcommit,xsavec,xsaves}intrin.h \
 		    {arm_acle,unwind-arm-common,s390intrin}.h \
 		    {cross-stdarg,syslimits,unwind,varargs}.h; \
 		do \
@@ -74,7 +76,7 @@ ifeq ($(with_libssp),yes)
     header_files += $(gcc_lib_dir)/include/ssp
 endif
 ifeq ($(with_gomp),yes)
-    header_files += $(gcc_lib_dir)/include/omp.h
+    header_files += $(gcc_lib_dir)/include/{omp,openacc}.h
 endif
 ifeq ($(with_qmath),yes)
     header_files += $(gcc_lib_dir)/include/quadmath{,_weak}.h
diff --git a/debian/rules.d/binary-libgccjit.mk b/debian/rules.d/binary-libgccjit.mk
new file mode 100644
index 0000000..fbedb1e
--- /dev/null
+++ b/debian/rules.d/binary-libgccjit.mk
@@ -0,0 +1,85 @@
+$(lib_binaries)  += libgccjit
+
+ifneq ($(DEB_CROSS),yes)
+  indep_binaries := $(indep_binaries) libgccjitdoc
+endif
+
+p_jitlib	= libgccjit$(GCCJIT_SONAME)
+p_jitdev	= libgccjit$(pkg_ver)-dev
+p_jitdbg	= libgccjit$(pkg_ver)-dbg
+p_jitdoc	= libgccjit$(pkg_ver)-doc
+
+d_jitlib	= debian/$(p_jitlib)
+d_jitdev	= debian/$(p_jitdev)
+d_jitdbg	= debian/$(p_jitdbg)
+d_jitdoc	= debian/$(p_jitdoc)
+
+$(binary_stamp)-libgccjit: $(install_jit_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_jitlib) $(d_jitdev) $(d_jitdbg)
+	dh_installdirs -p$(p_jitlib) \
+		$(usr_lib)
+
+	dh_installdirs -p$(p_jitdev) \
+		$(usr_lib) \
+		$(gcc_lib_dir)/include
+
+	dh_installdirs -p$(p_jitdbg)
+
+	DH_COMPAT=2 dh_movefiles -p$(p_jitlib) \
+		$(usr_lib)/libgccjit.so.*
+	rm -f $(d)/$(usr_lib)/libgccjit.so
+
+	DH_COMPAT=2 dh_movefiles -p$(p_jitdev) \
+		$(gcc_lib_dir)/include/libgccjit*.h
+	dh_link -p$(p_jitdev) \
+		$(usr_lib)/libgccjit.so $(gcc_lib_dir)/libgccjit.so
+
+	debian/dh_doclink -p$(p_jitlib) $(p_base)
+	debian/dh_doclink -p$(p_jitdev) $(p_base)
+	debian/dh_doclink -p$(p_jitdbg) $(p_base)
+
+	dh_strip -p$(p_jitlib) --dbg-package=$(p_jitdbg)
+	dh_compress -p$(p_jitlib) -p$(p_jitdev) -p$(p_jitdbg)
+	dh_fixperms -p$(p_jitlib) -p$(p_jitdev) -p$(p_jitdbg)
+	$(cross_makeshlibs) dh_makeshlibs -p$(p_jitlib)
+	$(call cross_mangle_shlibs,$(p_jitlib))
+	$(ignshld)$(cross_shlibdeps) dh_shlibdeps -p$(p_jitlib)
+	$(call cross_mangle_substvars,$(p_jitlib))
+	$(cross_gencontrol) dh_gencontrol -p$(p_jitlib) -p$(p_jitdev) -p$(p_jitdbg) \
+		-- -v$(DEB_VERSION) $(common_substvars)
+	$(call cross_mangle_control,$(p_jitlib))
+	dh_installdeb -p$(p_jitlib) -p$(p_jitdev) -p$(p_jitdbg)
+	dh_md5sums -p$(p_jitlib) -p$(p_jitdev) -p$(p_jitdbg)
+	dh_builddeb -p$(p_jitlib) -p$(p_jitdev) -p$(p_jitdbg)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+	touch $@
+
+$(binary_stamp)-libgccjitdoc: $(install_jit_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_jitdoc)
+	dh_installdirs -p$(p_jitdoc) \
+		$(PF)/share/info
+
+	DH_COMPAT=2 dh_movefiles -p$(p_jitdoc) \
+		$(PF)/share/info/libgccjit*
+
+	debian/dh_doclink -p$(p_jitdoc) $(p_base)
+
+	dh_compress -p$(p_jitdoc)
+	dh_fixperms -p$(p_jitdoc)
+	dh_gencontrol -p$(p_jitdoc) \
+		-- -v$(DEB_VERSION) $(common_substvars)
+	dh_installdeb -p$(p_jitdoc)
+	dh_md5sums -p$(p_jitdoc)
+	dh_builddeb -p$(p_jitdoc)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+	touch $@
diff --git a/debian/rules.defs b/debian/rules.defs
index d5fe4ed..f7e6a67 100644
--- a/debian/rules.defs
+++ b/debian/rules.defs
@@ -6,6 +6,8 @@ SHELL		= /bin/bash -e	# brace expansion used in rules file
 PWD		:= $(shell pwd)
 srcdir		= $(PWD)/src
 builddir	= $(PWD)/build
+builddir_jit	= $(PWD)/build-jit
+builddir_hppa64	= $(PWD)/build-hppa64
 stampdir	= stamps
 
 distribution	:= $(shell lsb_release -is)
@@ -90,7 +92,7 @@ DEB_VERSION := $(strip $(shell echo $(SOURCE_VERSION) | \
 # libraries: libgcc1, libobjc1
 EPOCH := 1
 DEB_EVERSION := $(EPOCH):$(DEB_VERSION)
-BASE_VERSION := $(shell echo $(DEB_VERSION) | sed -e 's/\([1-9]\.[0-9]\).*-.*/\1/')
+BASE_VERSION := $(shell echo $(DEB_VERSION) | sed -e 's/\([1-9]\).*-.*/\1/')
 
 # push glibc stack traces into stderr
 export LIBC_FATAL_STDERR_=1
@@ -345,14 +347,11 @@ endif
 # build using fsf or linaro
 ifeq ($(distribution),Ubuntu)
   ifeq (,$(findstring gnat, $(PKGSOURCE)))
-  ifneq (,$(findstring $(DEB_TARGET_ARCH),arm64 armel armhf))
-    with_linaro_branch = yes
-  endif
+  #ifneq (,$(findstring $(DEB_TARGET_ARCH),arm64 armel armhf))
+  #  with_linaro_branch = yes
+  #endif
   endif
 endif
-ifeq ($(distribution)-$(DEB_TARGET_ARCH),Debian-arm64)
-  with_linaro_branch = yes
-endif
 
 # check if we're building for armel or armhf
 ifeq ($(DEB_TARGET_ARCH),armhf)
@@ -504,6 +503,10 @@ endif
 # C ---------------------------
 enabled_languages := c
 
+with_jit = yes
+
+with_jit := $(call envfilt, jit, , , $(with_jit))
+
 # Build all packages needed for C development
 ifneq ($(with_base_only),yes)
   ifeq ($(with_dev),yes)
@@ -784,6 +787,7 @@ with_separate_gdc := no
 ifneq ($(separate_lang),yes)
   with_d := yes
 endif
+
 ifneq (,$(filter $(DEB_TARGET_ARCH_CPU),$(d_no_cpus)))
   with_d := disabled for cpu $(DEB_TARGET_ARCH_CPU)
 endif
@@ -796,6 +800,9 @@ ifeq ($(with_base_only),yes)
   with_d := no
 endif
 
+# FIXME: disabled for now
+with_d :=
+
 ifeq ($(with_d)-$(with_separate_gdc),yes-yes)
   ifneq (,$(findstring gdc,$(PKGSOURCE)))
     languages := c c++
@@ -1278,6 +1285,7 @@ ifneq (,$(filter $(DEB_HOST_ARCH), hppa mips))
     with_check := disabled for $(DEB_HOST_ARCH), testsuite timeouts with expect
   endif
 endif
+with_check := disabled for this upload
 
 # not a dependency on all archs, but if available, use it for the testsuite
 ifneq (,$(wildcard /usr/bin/localedef))
@@ -1635,7 +1643,7 @@ ifneq (,$(findstring $(DEB_TARGET_GNU_SYSTEM),$(locale_no_systems)))
   force_gnu_locales := disabled for system $(DEB_TARGET_GNU_SYSTEM)
 endif
 
-gcc_tarpath		:= $(firstword $(wildcard gcc-*.tar.* /usr/src/gcc-4.9/gcc-*.tar.*))
+gcc_tarpath		:= $(firstword $(wildcard gcc-*.tar.* /usr/src/gcc-5/gcc-*.tar.*))
 gcc_tarball		:= $(notdir $(gcc_tarpath))
 gcc_srcdir		:= $(subst -dfsg,,$(patsubst %.tar.xz,%,$(patsubst %.tar.lzma,%,$(patsubst %.tar.gz,%,$(gcc_tarball:.tar.bz2=)))))
 
@@ -1682,6 +1690,10 @@ configure_dummy_stamp	:= $(stampdir)/04-configure-dummy-stamp
 build_dummy_stamp	:= $(stampdir)/05-build-dummy-stamp
 install_dummy_stamp	:= $(stampdir)/07-install-dummy-stamp
 
+configure_jit_stamp	:= $(stampdir)/04-configure-jit-stamp
+build_jit_stamp		:= $(stampdir)/05-build-jit-stamp
+install_jit_stamp	:= $(stampdir)/07-install-jit-stamp
+
 configure_hppa64_stamp	:= $(stampdir)/04-configure-hppa64-stamp
 build_hppa64_stamp	:= $(stampdir)/05-build-hppa64-stamp
 install_hppa64_stamp	:= $(stampdir)/07-install-hppa64-stamp
@@ -1722,6 +1734,11 @@ ifneq (,$(findstring gcj-, $(PKGSOURCE)))
   endif
 endif
 
+ifeq ($(with_jit),yes)
+  build_dependencies += $(build_jit_stamp)
+  install_dependencies += $(install_jit_stamp)
+endif
+
 ifeq ($(with_neon),yes)
   build_dependencies += $(build_neon_stamp)
   install_dependencies += $(install_neon_stamp)
@@ -1788,3 +1805,7 @@ else
   define cross_mangle_control
   endef
 endif
+
+# FIXME: to build initial packages ...
+ignshld = -
+cross_makeshlibs = -
diff --git a/debian/rules.patch b/debian/rules.patch
index faeb4a3..9cfb9e3 100644
--- a/debian/rules.patch
+++ b/debian/rules.patch
@@ -13,7 +13,6 @@ series_file	?= $(patchdir)/series
 # which patches should be applied?
 
 debian_patches = \
-	svn-updates \
 	$(if $(with_linaro_branch),gcc-linaro) \
 	$(if $(with_linaro_branch),gcc-linaro-no-macros) \
 
@@ -75,21 +74,10 @@ debian_patches += \
 	kfreebsd-unwind \
 	kfreebsd-boehm-gc \
 	hurd-boehm-gc \
-	libffi-m68k \
 	libitm-no-fortify-source \
-	pr57653 \
-	pr61257 \
-	pr61046 \
-	pr61336 \
-	pr61126 \
-	gcc-setmultilib-fix \
 	sparc64-biarch-long-double-128 \
-	pr61841 \
-	pr61294 \
-	$(if $(filter yes, $(GFDL_INVARIANT_FREE)),,pr61294-doc) \
-	pr59586 \
-	pr60655-debug-loc \
-	pr63751
+	libobjc-extern-inline \
+	gotools-dynamic \
 
 # gccgo cgo patches
 debian_patches += \
@@ -161,7 +149,7 @@ endif
 
 ifeq ($(with_d),yes)
   debian_patches += \
-	gdc-4.9 \
+	gdc-5 \
 	gdc-versym-cpu \
 	gdc-versym-os \
 	gdc-frontend-posix \
@@ -169,7 +157,7 @@ ifeq ($(with_d),yes)
 #	gdc-updates
 #	gdc-multiarch
   ifneq ($(GFDL_INVARIANT_FREE),yes)
-    debian_patches += gdc-4.9-doc
+    debian_patches += gdc-5-doc
   else
     debian_patches += gdc-texinfo
   endif
@@ -255,7 +243,7 @@ ifeq ($(DEB_TARGET_ARCH_OS),hurd)
   debian_patches += hurd-changes
 endif
 
-debian_patches += gcc-ice-hack gcc-ice-apport
+debian_patches += gcc-ice-apport
 
 debian_patches += libjava-fixed-symlinks
 
@@ -307,7 +295,8 @@ endif
 debian_patches += mips-fix-loongson2f-nop$(if $(trunk_build),-trunk)
 debian_patches += libgomp-kfreebsd-testsuite
 debian_patches += go-testsuite
-debian_patches += fix-ffi_call_VFP-with-no-VFP-argument
+# FIXME: Still relevant?
+#debian_patches += fix-ffi_call_VFP-with-no-VFP-argument
 #debian_patches += pr61106
 
 # Ada patches needed for both the stable package and snapshot builds
diff --git a/debian/rules.sonames b/debian/rules.sonames
index 04d1f21..3c8b347 100644
--- a/debian/rules.sonames
+++ b/debian/rules.sonames
@@ -71,6 +71,8 @@ ifeq (,$(wildcard debian/soname-cache))
 	v=0; \
 	echo VTV_SONAME=$$v >> $$cache; \
 	echo CILKRTS_SONAME=5 >> $$cache; \
+	echo CC1_SONAME=0 >> $$cache; \
+	echo GCCJIT_SONAME=0 >> $$cache; \
 	cat $$cache)
 else
   SONAME_VARS := $(shell cat debian/soname-cache)
@@ -97,6 +99,8 @@ QUADMATH_SONAME	= $(call vafilt,$(SONAME_VARS),QUADMATH_SONAME)
 GNAT_SONAME	= $(call vafilt,$(SONAME_VARS),GNAT_SONAME)
 GO_SONAME	= $(call vafilt,$(SONAME_VARS),GO_SONAME)
 ITM_SONAME	= $(call vafilt,$(SONAME_VARS),ITM_SONAME)
+CC1_SONAME	= $(call vafilt,$(SONAME_VARS),CC1_SONAME)
+GCCJIT_SONAME	= $(call vafilt,$(SONAME_VARS),GCCJIT_SONAME)
 
 # alias
 GFORTRAN_SONAME = $(FORTRAN_SONAME)
diff --git a/debian/rules.unpack b/debian/rules.unpack
index 8ffc891..86cca5a 100644
--- a/debian/rules.unpack
+++ b/debian/rules.unpack
@@ -25,9 +25,6 @@ debian-chmod:
 # ---------------------------------------------------------------------------
 
 gfdl_texinfo_files = \
-	gcc/doc/arm-neon-intrinsics.texi \
-	gcc/doc/arm-acle-intrinsics.texi \
-	gcc/doc/aarch64-acle-intrinsics.texi \
 	gcc/doc/avr-mmcu.texi \
 	gcc/doc/bugreport.texi \
 	gcc/doc/cfg.texi \
@@ -63,6 +60,7 @@ gfdl_texinfo_files = \
 	gcc/doc/loop.texi \
 	gcc/doc/lto.texi \
 	gcc/doc/makefile.texi \
+	gcc/doc/match-and-simplify.texi \
 	gcc/doc/md.texi \
 	gcc/doc/objc.texi \
 	gcc/doc/optinfo.texi \
diff --git a/debian/rules2 b/debian/rules2
index 598b32a..673e9ce 100644
--- a/debian/rules2
+++ b/debian/rules2
@@ -1144,13 +1144,13 @@ else
     ifeq ($(with_java_maintainer_mode),yes)
 	( \
 	  echo '#!/bin/sh'; \
-	  echo 'exec gij-4.9 -cp /usr/share/java/ecj.jar org.eclipse.jdt.internal.compiler.batch.GCCMain "$$@"'; \
+	  echo 'exec gij-5 -cp /usr/share/java/ecj.jar org.eclipse.jdt.internal.compiler.batch.GCCMain "$$@"'; \
 	) > bin/ecj1
 	chmod +x bin/ecj1
 	: # If we don't have gjavah in PATH, try to build it with the old gij
 	mkdir -p bin
-	if [ -x /usr/bin/gjavah-4.9 ]; then \
-	  ln -sf /usr/bin/gjavah-4.9 bin/gjavah; \
+	if [ -x /usr/bin/gjavah-5 ]; then \
+	  ln -sf /usr/bin/gjavah-5 bin/gjavah; \
 	elif [ -x bin/gjavah ]; then \
 	  : ; \
 	else \
@@ -1163,10 +1163,10 @@ else
 	  cp -a $(srcdir)/libjava/classpath/tools/resource/gnu/classpath/tools/common/Messages.properties \
 	    gnu/classpath/tools/common; \
 	  cd external/asm; \
-	  for i in `find . -name \*.java`; do gcj-4.9 --encoding ISO-8859-1 -C $$i -I.; done; \
+	  for i in `find . -name \*.java`; do gcj-5 --encoding ISO-8859-1 -C $$i -I.; done; \
 	  cd ../..; \
-	  for i in `find gnu -name \*.java`; do gcj-4.9 -C $$i -I. -Iexternal/asm/; done; \
-	  gcj-4.9 -findirect-dispatch -O2 -fmain=gnu.classpath.tools.javah.Main \
+	  for i in `find gnu -name \*.java`; do gcj-5 -C $$i -I. -Iexternal/asm/; done; \
+	  gcj-5 -findirect-dispatch -O2 -fmain=gnu.classpath.tools.javah.Main \
 	    -I. -Iexternal/asm/ `find . -name \*.class` -o $(PWD)/bin/gjavah.real; \
 	  ( \
 	    echo '#!/bin/sh'; \
@@ -1192,8 +1192,9 @@ else
 	  echo $$? > status; \
 	) 2>&1 | tee bootstrap-protocol
 	s=`cat status`; rm -f status; \
-	if [ $$s -ne 0 ]; then \
+	if [ $$s -ne 0 ] && [ -z "$$NO_CONFIG_LOG_DUMP" ]; then \
 	  for log in $$(find $(builddir) -name config.log); do \
+	    case "$$log" in */prev-*/) continue; esac; \
 	    echo LOGFILE START $$log; \
 	    cat $$log; \
 	    echo LOGFILE END $$log; \
@@ -1211,9 +1212,35 @@ endif
 
 	touch $(build_stamp)
 
-ifeq ($(versioned_packages),yes)
-  hppa64_configure_flags += --program-suffix=-$(BASE_VERSION)
-endif
+CONFARGS_JIT := \
+	$(filter-out %bootstrap --enable-languages=%, $(CONFARGS)) \
+	--enable-languages=jit \
+	--enable-host-shared \
+	--disable-bootstrap
+
+$(configure_jit_stamp): $(build_stamp)
+	dh_testdir
+	rm -f $(configure_jit_stamp) $(build_jit_stamp)
+	rm -rf $(builddir_jit)
+	mkdir $(builddir_jit)
+	: # configure
+	cd $(builddir_jit) && \
+	  $(SET_PATH) \
+	  $(SET_SHELL) \
+	  CC="$(builddir)/gcc/xgcc -B$(builddir)/gcc/" \
+	     ../src/configure $(CONFARGS_JIT)
+	touch $(configure_jit_stamp)
+
+$(build_jit_stamp): $(configure_jit_stamp)
+	  $(SET_PATH) \
+	  $(SET_SHELL) \
+	  $(SET_LOCPATH) \
+	  LD_LIBRARY_PATH=$${LD_LIBRARY_PATH:+$$LD_LIBRARY_PATH:}$(builddir)/gcc \
+	    $(MAKE) -C $(builddir_jit) $(NJOBS) \
+		CC="$(builddir)/gcc/xgcc -B$(builddir)/gcc/" \
+		$(CFLAGS_TO_PASS) \
+		$(LDFLAGS_TO_PASS)
+	touch $(build_jit_stamp)
 
 ifeq ($(DEB_CROSS),yes)
   CC_for_hppa64_cross = $(CC)
@@ -1221,6 +1248,10 @@ else
   CC_for_hppa64_cross = $(builddir)/gcc/xgcc -B$(builddir)/gcc/
 endif
 
+ifeq ($(versioned_packages),yes)
+  hppa64_configure_flags += --program-suffix=-$(BASE_VERSION)
+endif
+
 $(configure_hppa64_stamp): $(build_stamp)
 	dh_testdir
 	rm -f $(configure_hppa64_stamp) $(build_hppa64_stamp)
@@ -1868,6 +1899,10 @@ ifeq ($(with_d),yes)
   include debian/rules.d/binary-d.mk
 endif
 
+ifeq ($(with_jit),yes)
+  include debian/rules.d/binary-libgccjit.mk
+endif
+
 ifeq ($(with_libnof),yes)
   ifeq ($(DEB_TARGET_GNU_CPU),powerpc)
     include debian/rules.d/binary-nof.mk
@@ -2198,6 +2233,30 @@ endif
 
 	touch $(install_stamp)
 
+$(install_jit_stamp): $(build_jit_stamp) $(install_stamp)
+	dh_testdir
+	dh_testroot
+	rm -rf $(d)-jit
+	mkdir -p $(d)-jit/$(PF)
+
+	$(SET_PATH) \
+	    $(MAKE) -C $(builddir_jit) \
+		CC="$(builddir)/gcc/xgcc -B$(builddir)/gcc/" \
+		$(CFLAGS_TO_PASS) \
+		$(LDFLAGS_TO_PASS) \
+		DESTDIR=$(PWD)/$(d)-jit \
+		    install
+
+	: # copy files to the standard build
+	cp -a $(d)-jit/$(PF)/include/libgccjit*.h \
+		$(d)/$(gcc_lib_dir)/include/.
+	cp -a $(d)-jit/$(PF)/lib/libgccjit.so* \
+		$(d)/$(usr_lib)/.
+	cp -a $(d)-jit/$(PF)/share/info/libgccjit* \
+		$(d)/$(PF)/share/info/.
+
+	touch $(install_jit_stamp)
+
 $(install_hppa64_stamp): $(build_hppa64_stamp)
 	dh_testdir
 	dh_testroot
diff --git a/debian/source.lintian-overrides b/debian/source.lintian-overrides
index d9bb145..58eb474 100644
--- a/debian/source.lintian-overrides
+++ b/debian/source.lintian-overrides
@@ -1,4 +1,4 @@
-gcc-4.9 source: invalid-arch-string-in-source-relation
-gcc-4.9 source: quilt-build-dep-but-no-series-file
+gcc-5 source: invalid-arch-string-in-source-relation
+gcc-5 source: quilt-build-dep-but-no-series-file
 # lintian can't handle (>= ${gcc:Version})
-gcc-4.9 source: weak-library-dev-dependency
+gcc-5 source: weak-library-dev-dependency