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| author | drochner <drochner@pkgsrc.org> | 2003-06-05 18:50:54 +0000 |
|---|---|---|
| committer | drochner <drochner@pkgsrc.org> | 2003-06-05 18:50:54 +0000 |
| commit | dfe2fe099e0431a71e9315f116a7d2e93d99cfed (patch) | |
| tree | 8ec2cc33e54efd8d5bc7ef0e689ac0c11227c763 /cad/py-MyHDL/DESCR | |
| parent | d32bf503811656ed47bd0054f87bbd6106bd3b17 (diff) | |
| download | pkgsrc-dfe2fe099e0431a71e9315f116a7d2e93d99cfed.tar.gz | |
a library which uses Python as a hardware description language, using
the new generator constructs (like pysim, at a first glance)
Diffstat (limited to 'cad/py-MyHDL/DESCR')
| -rw-r--r-- | cad/py-MyHDL/DESCR | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/cad/py-MyHDL/DESCR b/cad/py-MyHDL/DESCR new file mode 100644 index 00000000000..fd819237dc9 --- /dev/null +++ b/cad/py-MyHDL/DESCR @@ -0,0 +1,7 @@ +MyHDL is a Python package for using Python as a hardware +description language. Popular hardware description languages, like +Verilog and VHDL, are compiled languages. MyHDL with Python +can be viewed as a "scripting language" counterpart of such +languages. However, Python is more accurately described as a very +high level language (VHLL). MyHDL users have access to the +amazing power and elegance of Python for their modeling work. |