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-rw-r--r--cad/verilog/Makefile6
1 files changed, 3 insertions, 3 deletions
diff --git a/cad/verilog/Makefile b/cad/verilog/Makefile
index 80c4a0aac8e..d3a0ea56896 100644
--- a/cad/verilog/Makefile
+++ b/cad/verilog/Makefile
@@ -1,4 +1,4 @@
-# $NetBSD: Makefile,v 1.6 2001/02/16 13:46:29 wiz Exp $
+# $NetBSD: Makefile,v 1.7 2001/03/27 03:19:47 hubertf Exp $
#
DISTNAME= verilog-0.4
@@ -9,8 +9,8 @@ MAINTAINER= dmcmahill@netbsd.org
HOMEPAGE= http://icarus.com/eda/verilog/index.html
COMMENT= Verilog simulation and synthesis tool (stable release version)
-BUILD_DEPENDS+= bison:../../devel/bison
-BUILD_DEPENDS+= gperf:../../devel/gperf
+BUILD_DEPENDS+= bison-*:../../devel/bison
+BUILD_DEPENDS+= gperf-2.7.2:../../devel/gperf
DEPENDS+= ipal-current>=20001210:../../cad/ipal-current
CONFLICTS+= verilog-current