| Age | Commit message (Collapse) | Author | Files | Lines |
|---|
|
|
|
-----------------------------
From: http://klayout.de/development.html
Release date: 2016-11-29
Enhancements: The RBA::Region#smooth function was enhanced to give
somewhat better results
Enhancements: DXF's circle approximation can now also specified
through an "accuracy" parameter: if less than the number of specified
points is required to achieve the given accuracy, the number is
reduced accordingly. This also applies to the polygon interpolation
of spline and arc curves.
Enhancement: RBA integration now is compatible with Ruby 2.3 which
allows building on Ubuntu 16 as well.
Enhancement: OASIS files with instance angles >360 were rejected
before. Now, this has turned into a warning.
Bugfix: DEF reader was failing to read MASK/via combinations.
Bugfix: The marker browser's "show only rules with errors" option was
enabled again on sorting of errors.
Bugfix: DRC: Using Layout objects for inputs didn't work
Bugfix: Copying Hierarchy treets containing PCell's made the PCell's
being turned into static cells.
|
|
-----------------------------
3.3.79 31dec16 Disable accelerator keys in twinwave single window mode to
avoid focus conflicts.
Fixes for -fstrict-aliasing and other recent warnings.
Added fill_waveform rc variable and corresponding menu option
(/View/Show Filled High Values) to allow filling in the lower
portion of high values for increased visibility.
|
|
|
|
|
|
--------------------------
Release notes for EAGLE 7.7.0
=============================
* Licensing:
- Update of various spots in EAGLE regarding the license changes introduced
by Autodesk: Standard, Premium, Ultimate, Express and Educational.
The 30 day trial license has been removed.
* ULPs:
- Added 'manufacturing.ulp' provided by Autodesk. It supports an upload of EAGLE
drawing files to 'circuits.io' in order to generate manufacturing data which
can then be downloaded. The ULP is accessible as an icon in the board editor.
- Added 'ecadio.ulp' provided by Autodesk. It supports an upload of EAGLE boards
to 'ecad.io' in order to generate a 3D PCB for use in MCAD systems.
The ULP is accessible as an icon in the board editor.
* UI improvements:
- Added Option.SignalNames to display the signal names on the signal wires
and on the connected pads and SMDs.
It can be set in the Settings dialog under 'Misc/Display signal names'.
- The options Option.SignalNames, Option.PadNames and Option.ViaLength are
set to 'On' by default.
* Miscellaneous:
- Improved visibility of scrollbars for common window styles on Linux.
- Silently ignoring double references to a contact within a signal when loading
a board file.
- CAM Processor: when running 'Process Job' with more than one section,
it is checked if the job covers the Layer Setup only partially.
- The file locking option has been switched off by default. Use 'Backup/Locking'
under 'Options' in Control Panel to turn it on.
- Update of EAGLE logo to the new appearance since Autodesk acquisition.
- Update of Hungarian translation (GUI without help and manual).
* Bugfixes:
- Fixed UL functions strsplit() and lookup() to handle unusual UTF8 characters
as separator.
- Fixed potential crash of the 64 bit versions when loading EAGLE drawings
from old format (e.g. V3.55).
- Image export to TIFF format in monochrome: fixed a regression regarding the
compression method.
- The selected object is no longer removed from the group after running a ULP
started through 'SET CONTEXT Object ...'; the ULP might want to use this
one-object group afterwards with e.g. 'exit("move (>@)")'.
- Ensuring valid move of polygon wires or an entire polygon if selecting a
wire with 'SET CONTEXT Wire ...' or using setgroup() in a ULP.
- Fixed history of dlgStringEdit to become case sensitive.
- Fix for refresh of images in Control Panel preview on Windows.
- Added a check for identical pinrefs when loading a schematic to avoid a
possible crash.
- Fixed deleting/splitting busses with portrefs involved: it could happen that
new port connections couldn't be established anymore.
- Fixed selecting an end of a wire with the context menu.
- Fix for ULP function ingroup() returning true for too many objects after
UNDOing of transferring a group to another sheet.
|
|
Command Line Tools:
Add -block switch to dwg2pdf, dwg2bmp, dwg2svg and dwg2maptiles
dwg2svg:
Add -layer-attribute switch to export layer attributes (into QCAD namespace)
dwg2bmp:
Add -noweightmargin switch to avoid extra margin to account for lineweights
Command line widget:
allow for multi-line input (pasting list of coordinates for lines, polylines, splines, etc.)
Modify:
Explode:
Explode block arrays into separate block references
Explode solid fills into boundary
Break out:
Break out segments from self-intersecting polylines
Misc:
Highlight start point of lines, arcs, ellipse arcs, polylines, splines when selected
Bug fixes:
FS#1461 - Zoom in / out: not centred under mouse cursor if Retina resolution is enabled for graphics view
FS#1466 - Toolbars on second screen cannot be accessed if second screen is detached
FS#1474 - Dimension > Leader: changing options breaks tool
FS#1476 - Draw > Circle > 2 Tangents and Radius: exception with arcs and circle entities
FS#1479 - Modify > Explode: too many segments for splines with large tolerance
FS#1481 - Block List: update changes selected item
FS#1491 - Layer > Create Layer from Selection: cancelling dialog fails
FS#1497 - Autosnap: hangs with very complex splines
FS#1508 - QCAD CE: Subscript and superscript formatting lost when file re-opened
FS#1509 - Ellipse / circle, ellipse / ellipse intersections
Also as part of this update, I have removed the example plugins that do nothing (as
on the QCAD forum, the author states that these may slow down the operation)
|
|
## 2015.03-3
**OS X only: Auto-update vulnerability fix**
|
|
Patch Version 2.1.3
r-a-v-a-s released this on 23 Sep
Bugs eliminated:
* Shift would not activate the command line
* Command+Tab didn't always activate the current drawing on OS X
Commit Log => https://github.com/LibreCAD/LibreCAD/commits/2.1.3
Patch Version 2.1.2
r-a-v-a-s released this on 16 Sep 4 commits to 2.1 since this release
Bugs eliminated:
* wouldn't build with gcc 5.4 and 6
* mouse cursor was missing for `Arc Tangential'
* right-click with plugins could cause a crash
* construction lines were not drawn when the line segment was out of view
* DXF files with comments were not properly loaded
* drawings were not marked as modified after an `undo'
* the command line didn't accept numpad input
* the command widget didn't activate properly when floating
Commit Log => https://github.com/LibreCAD/LibreCAD/commits/2.1.2
|
|
-----------------------------
3.3.78 26oct16 Fixed crash when using multiple pattern searches.
|
|
This large commit accomplishes the following:
1) Switch USE_LANGUAGES=ada to require lang/gcc5-aux (gcc 5.4) instead
of lang/gcc-aux (gcc 4.9.2) on gcc.mk
2) Bump affected ports and fix paths as necessary
3) Upgrade devel/gprbuild to the latest release
- No longer requires lang/gnat_util
- gprslave requires gcc6-aux, so it was disabled for now
4) Fix lang/gnat_util but set PKG_SKIP_REASON
- It has no further purpose in the pkgsrc tree
- It has no practical purpose outside of the pkgsrc tree
- Indicate intent to remove from tree in Jan. 2017
5) Set devel/GPS as failed with PKG_FAIL_REASON
- This version of GPS is several years old and at the time they were
strongly tied to compiler.
- Latest release of GPS require gcc6-aux (not available) and several
new and complex dependencies
- maintainer (me) has no interest to continue supporting it
- Leaving GPS in place until Jan 2017 to give another person chance to
upgrade and take over support
- Latest version in FreeBSD Ports Collection as a reference point
|
|
|
|
|
|
-----------------------------
3.3.77 03oct16 Updated documentation to include an appendix on FST
implementation details.
Removed '!A || (A && B)' is equivalent to '!A || B' redundant
condition checks where found in source.
Added hier_ignore_escapes rc variable.
Dynamic resizing tweaks for when it is turned off.
Added HUWL-? value types to signal_change_list() to keep GHW
files from crashing Tcl scripts.
|
|
|
|
|
|
|
|
VeriWell is a full Verilog simulator. It supports nearly all of the
IEEE1364-1995 standard, as well as PLI 1.0.
Yes, VeriWell *is* the same simulator that was sold by Wellspring Solutions in
the mid-1990 and was included with the Thomas and Moorby book.
|
|
pkgsrc packages altered:
- cad/MyHDL-gplcver
- cad/MyHDL-iverilog
- cad/py-MyHDL
pkgsrc changes:
- Add common Makefile.common for MyHDL packages
- 0.9.0 supports now Python 3.x
- update LICENSE to gnu-lgpl-v2.1
- replace local patch in MyHDL-gplcver and use MAKE_FLAGS to enforce INCS
- set CC in MyHDL-gplcver
- setup test target in cad/py-MyHDL
- share common distinfo
- replace AUTO_MKDIRS with INSTALLATION_DIRS
- switch MASTER_SITES to GitHub
upstream changelog
==================
What’s new in MyHDL 0.9
Python 3 support
Experimental Python 3 support has been added to MyHDL 0.9. This was a major effort to modernize the code. As a result, Python 2 and 3 are supported from a single codebase.
See Python 3 Support for more info.
Interfaces (Conversion of attribute accesses)
Rationale
Complex designs often have many signals that are passed to different levels of hierarchy. Typically, many signals logically belong together. This can be modelled by an interface: an object that has a number of Signal objects as its attributes. Grouping signals into an interface simplifies the code, improves efficiency, and reduces errors.
The following is an example of an interface definition:
class Complex:
def __init__(self, min=-2, max=2):
self.real = Signal(intbv(0, min=min, max=max))
self.imag = Signal(intbv(0, min=min, max=max))
Although previous versions supported interfaces for modeling, they were not convertible. MyHDL 0.9 now supports conversion of designs that use interfaces.
The following is an example using the above Complex interface definition:
a,b = Complex(-8,8), Complex(-8,8)
c = Complex(-128,128)
def complex_multiply(clock, reset, a, b, c):
@always_seq(clock.posedge, reset=reset)
def cmult():
c.real.next = (a.real*b.real) - (a.imag*b.imag)
c.imag.next = (a.real*b.imag) + (a.imag*b.real)
return cmult
Solution
The proposed solution is to create unique names for attributes which are used by MyHDL generators. The converter will create a unique name by using the name of the parent and the name of the attribute along with the name of the MyHDL module instance. The converter will essentially replace the ”.” with an “_” for each interface element. In essence, interfaces are supported using hierarchical name expansion and name mangling.
Note that the MyHDL convertor supports interfaces, even though the target HDLs do not. This is another great example where the convertor supports a high-level feature that is not available in the target HDLs.
See also
For additional information see the original proposal mep-107.
Other noteworthy improvements
ConcatSignal interface
The interface of ConcatSignal was enhanced. In addition to signals, you can now also use constant values in the concatenation.
std_logic type ports
toVHDL() has a new attibute std_logic_ports. When set, only std_logic type ports are used in the interface of the top-level VHDL module.
Development flow
The MyHDL development flow has been modernized by moving to git and github for version control. In addition, travis has set up so that all pull requests are tested automatically, enabling continuous intergration.
Acknowledgments
The Python 3 support effort was coordinated by Keerthan Jaic, who also implemented most of if. Convertible interfaces were championed by Chris Felton, and implemented by Keerthan Jaic.
MyHDL development is a collaborative effort, as can be seen on github. Thanks to all who contributed with suggestions, issues and pull requests.
|
|
Use saner and more specific name for this package.
No objection for rename from <gdt>
|
|
No PKGREVISION bump as it was update as while ago.
|
|
Bump PKGREVISION to 1.
|
|
|
|
It's a rename of cad/verilog to a better name.
Updated DESCR for new package:
Icarus Verilog is intended to compile ALL of the Verilog HDL as described in
the IEEE-1364 standard. Of course, it's not quite there yet. It does currently
handle a mix of structural and behavioral constructs.
Icarus Verilog is not aimed at being a simulator in the traditional sense, but
a compiler that generates code employed by back-end tools.
No objections to rename from <gdt>
|
|
pkgsrc changes:
- note GitHub tags (but not use them for now)
- remove conflict with nonexistent verilog-current
- install additional documentation in share/doc/ivl (not share/ivl)
- drop DESTDIR gymnastics - build works without it
- (re)enable gperf dependency
- regenerate buildlink3.mk
- drop patches/patch-lexor_keyword.cc - no longer needed
- patches/patch-vpi_Makefile partially fixed upstream - rest not needed
upstream changelog
==================
Probably the only notes available:
Here are the release notes for Icarus Verilog release branch 10. The 10
release is a huge improvement over the 0.9 release series, in every
aspect. Much more of the Verilog and SystemVerilog language is supported,
many bugs have been fixed, and performance has improved. The changes
(improvements!) are so numerous that there is no point attempting to
enumerate them.
-- http://iverilog.wikia.com/wiki/Release_Notes_Icarus_Verilog_10
|
|
Local changes:
- set LICENSE (gnu-gpl-v2)
- replace DEPENDS of verilog to blk3
- stop replacing shebang for WISH - no longer needed
- stop helping to find tclConfig.sh and tkConfig.sh - no longer needed
- comment rationale for -DUSE_INTERP_RESULT (TCL/TK compatibility)
- drop patch-src_lxt2__read.c - fixed upstream (differently)
- comment and regenerate patch-src_lxt2__read.h
Upstream changelog (partial changes prior 0.7 not known)
==================
0.7.10
Stable release covered-0.7.10 made. This release updates the FST library to the latest version which contains some fixes and enhancements.
Stable release covered-0.7.9
11/21/2010 01:03 AM Filed in: Releases
Stable release covered-0.7.9 made. This release is a bug fix and minor feature enhancement release. Here are the details:
Cleaned up error messages emitted from the clang utility.
Updated GUI to use the ttk styled widgets for a more uniform look and allows the user to change the overall look of the GUI using a preference item.
Handling issue where a CDD file was created in a different directory and we attempt to load it in a different environment. Previously, a stack trace was emitted rather than just the user error message.
Updated copyright dates to include 2010
Added FST dumpfile scoring (new -fst option added to the score command to accommodate this option).
Adding support for "wire real" and associated code to Verilog parser.
Fixing issue with memory coverage.
Fixing bug 3054545. When a merged CDD file was used in an exclude command, a segmentation fault would occur.
Added support for constant assignment to reals.
Added support for "parameter integer" and "parameter real".
Added parsing support for the $fopenw system task.
Added support for performing +: and -: part selection on the left-hand-side of assignment expressions.
Fixed various memory overrun and memory leak issues that caused instability issues within the GUI.
Fixed GUI combinational logic issue where incorrect highlighting/underlining was occurring for uncovered expressions.
Fixed GUI issue with next/previous button traversal for combinational logic.
Enhanced the regression suite to verify all of the new features mentioned above.
Updated user guide HTML output to include the Covered banner to the top of each page.
User guide and man pages have been updated per these changes.
On a side note, active work on Covered's development branch(es) has stopped indefinitely. I plan to support the current feature set in the 0.7.x branch with possible minor enhancements as requested. Please feel free to continue to send me e-mail and/or submit bug reports against the 0.7.x stable releases.
Stable release covered-0.7.8
03/24/2010 10:20 PM Filed in: Releases
Stable release covered-0.7.8 made. This release is primarily a bug fix release, but it does contain a few new
minor features and Verilog language enhancements. Here are the details:
Fixed bug 2912587. Using the -f option with the merge command was causing errors.
Fixed bug 2912679. If the GUI was invoked (i.e., covered report -view) and an error in command-line parsing occurred, Covered segfaulted.
Added ability to specify the CDD on the report command-line when starting the GUI (i.e., covered report -view foobar.cdd) which will automatically load the specified CDD files into the GUI on startup. Feature request 2912698.
Fixed bug 2925756. An expression surrounded by the parenthesis could cause a segmentation fault when parsing.
Support has been added for NC-Verilog VPI usage.
Fixed bug 2926579. Changing from a known value to an X value should cause no change in toggle coverage; however, when we transition back to a known value and it differs from the previously known value, we record a toggle coverage change. Example: 0 -> X -> 0 (no change in coverage), 0 -> X -> 1 (change in coverage).
Fixed bug 2927285. Segmentation faults could occur when excluding FSM and combinational logic cases.
Added support for the $clog system function call.
Fixed bug 2929948. Assignments to a concatentation of signals could lead to segmentation fault.
Fixed issue in the LXT2 reader that resulted in a memory leak.
Fixed bug 2933112. Added full support for out-of-bounds assignment.
Added new -T global option that provides a "terse" output which outputs the Covered header and warnings/errors only (less output than using none of the global output verbosity options). Feature request 2952492.
Fixed bug 2960887. Adds support for creating a definition which contains no user value (i.e., `define FOO). Covered was incorrectly assigning a value of 1 to these types of defines.
Fixed bug 2958529. Zero width replications are now supported by Covered (i.e., {0{a & b}})
Fixed bug 2974860. Fixed issue with FSM state input/output variables being output to an ASCII report file correctly.
Added ability to allow the "trans" parameter to Covered FSM attributes to contain additional characters after it. Some simulators don't like Verilog attributes having the same name for multiple parameters. Feature request 2976039.
User guide has been updated per these changes.
Development release covered-20091126
11/26/2009 10:10 PM Filed in: Releases
Development release covered-20091126 made. This is a bug fix release only.
Stable release covered-0.7.7
10/24/2009 10:09 PM Filed in: Releases
Stable release covered-0.7.7 made. This is a bug fix release only.
Fixed compilation warnings when compiling on 64-bit Mac OS X and Debian-based platforms.
Updates to build scripts to help downstream Debian releases builds.
Fixed bug 2880705. $Id: keywords containing newlines are now handled properly. Additionally, fixing issues with multiply instantiated modules within a generate block.
Fixed bug 2881869. Fixed a stack overflow issue in the gen_item_resolve function that would cause segmentation faults when too many items were being generated within a single generate block.
Fixed bug 2882433. Fixed the "ERROR! Parameter used in expression but not defined in current module" error when a generated module instance has a parameter override of a parameter with the same name as the parameter within the module that contains the generate block.
Stable release covered-0.7.6
08/24/2009 10:12 PM Filed in: Releases
Stable release covered-0.7.6 made. This is a bug fix release only.
Fixed misspelling in report generator code (misspelling showed up in text reports)
Fixed issues with performing module merging with modules containing generate blocks configured differently for different instantiations of the same module.
Stable release covered-0.7.5
08/02/2009 10:20 PM Filed in: Releases
Stable release covered-0.7.5 made. This is a bug fix release only.
Fixed bug 2808818. If a generate variable name collided with a reg/wire name, Covered was not emitting an error.
Fixed bug 2808820. If no signal was used from the dumpfile and at least one signal needs information from the dumpfile, Covered needed to signal a user error.
Fixed bug 2812321. Parameterized/generated modules could get incorrect coverage calculated for them.
Fixed bug 2812495. Fixed a crash issue. There is another part to this bug report that is not fixed, however.
Fixed bug 2813405. A design run with the -g score option caused the GUI to freeze when viewed.
Fixed bug 2813948. Fixed assertion issue with merging scored and unscored CDD files.
Development release covered-20090802
08/02/2009 10:19 PM Filed in: Releases
Development release covered-20090802 made. This development release adds several performance enhancements and bug fixes to the new inlined code coverage flow, including the following:
Adding support for $random and $urandom system calls to inlined coverage.
Includes all fixes made to the stable 0.7.5 release.
Adding support for $value$plusargs system calls to inlined coverage.
Fixing issue with generated IF statements.
Added user documentation for inlined coverage flow and score options.
Fixing issue with generated code interrupting comma-separated assign statements.
Performed code simplification and performance improvement with the way statements were handled internally.
Removed unnecessary calls to simulation functions when using inlined code coverage (this added a performance penalty).
Improved performance of inlined code generator for sizing generated signals.
Fixed memory indexing issues related to memory coverage.
Added support for static function and static ternary operators for inlined code coverage.
Added code to differentiate functions used statically and not to do the right thing for inlined code coverage accumulation.
Added vcd_diff script which checks the dumpfile output from non-inlined and inlined design files to verify that the inlined code generator does not change the result. This check is now a part of all inlined regression runs.
Made several performance improvements to the VCD file reader. The reader is now 10-20% faster.
Added support for Verilator regressions runs and ported a couple of diagnostics to Verilator format.
Adding check to make sure that a CDD file without inlined mode set that reads a VCD file containing inlined coverage data emits an error to the user and exits gracefully.
Added -inline-comb-depth score option to allow the user to specify a shallower combinational coverage depth to be generated -- improving inlined simulation and coverage performance.
For Verilator runs, inserted pragmas around intermediate combinational logic expression signals to exclude them from being output to VCD files. This improves simulation and coverage performance for Verilator runs (other simulators that have a VPI that automatically remove these signals from generating change callbacks).
Performing code replace of some actual code with pre-calculated intermediate expression values for further simulation performance improvements.
Added "e" option to -inline-metrics which allows event coverage to be turned on/off independently of other combinational logic coverage. This allows further simulation and coverage performance improvements (especially for Verilator runs).
Added optimization that causes code generation to be skipped for assertion files when assertion coverage is not required.
Full regressions now runs cleanly with all code changes.
Stable release covered-0.7.4
06/17/2009 10:21 PM Filed in: Releases
Stable release covered-0.7.4 made. This is a bug fix release only.
Updated regression files for the new 2.4 version of the OVL.
Fixed bug 2804585. Memory reads in LHS part selects were not being marked for memory coverage.
Fixed issue with VPI usage in a VCS simulation with generate statements.
Fixed bug 2805191. Automatic tasks/functions that manipulate variables outside of the task/function can cause incorrect toggle coverage for those signals.
Fixed bug 2806855. Generate blocks generating module instantiations could lead to score command errors (segfaults, internal assertion errors, etc.)
Stable release covered-0.7.3
06/04/2009 10:22 PM Filed in: Releases
Stable release covered-0.7.3 made. This primarily fixes a few bugs in the compile of Covered "out of the box". It seems that even with the regression testbench, things can still slip through the cracks :( Anyhow, please use this release instead of the 0.7.2 release.
Stable release covered-0.7.2
05/09/2009 10:23 PM Filed in: Releases
Stable release covered-0.7.2 made. This is primarily a bug fix release with a few new features added to the CLI. Here are the details of the changes.
Fixed bug 2791651. Memory deallocation errors occurred when syntax errors were being reported by the parser.
Fixed bug 2791599. Whitespace prior to a `line or #line directive were not being handled properly.
Fixed bug 2794588. If a module was specified in a -v option after its directory was specified by the -y option to the score command, the module was not found for parsing.
Fixed bug 2794684. If a normal (not generate) case statement within a generate block will output the case expression to be output to the CDD more than once, leading to internal assertion errors when the CDD file is read.
Fixed bug 2795088. When a CDD file is opened from the wizard GUI window, the open file window can be placed behind the wizard window. Instead the wizard window should disappear once a selection button has been clicked.
Fixed bug 2795086. If the user clicked on the global exclusion reason listbox when it is empty, a Tcl/Tk error message box was raised.
Fixed bug 2795089. If the GUI detailed combinational logic window is used to view several expressions one after the other, Covered can segfault.
Fixed bug 2795583. Score command segfaults when a module is instantiated within a generate block and overrides a parameter value within the module.
Fixed bug 2795640. Variables instantiated within a generate block caused issues with Covered when simulated with VCS.
Fixed bug where memory elements being assigned via non-blocking assignments were not being evaluated, leading to incorrect coverage output.
CLI updates/fixes:
When the 'debug on' command is specified, a line specifying that the debug mode is now on is output (previously nothing was output (because the debug mode was off).
Changed the 'debug on' command to 'debug less' and 'debug more' where the prior only outputs the executed statements and timestep information during simulation while the latter outputs what 'debug on' used to output (extremely verbose).
Fixed bug 2795209. When an unknown CLI command was specified, a memory error occurred.
Fixed bug 2795215. Status bar was attempting to be output during simulation when debug mode was turned on. This created some unreadable/messy output.
Changed the 'goto ' command to 'goto time '.
Added 'goto line [:]' command which simulates until the specified line number is about to be simulated.
Added 'goto expr ' command which simulates until the given expression evaluates to a value of true.
Added support for handling the Ctrl-C interrupt when the score command is simulating with the -cli option specified. In this case, simulation will immediately stop and return a CLI prompt which will allow the user to continue interacting with the simulation.
Updated user guide documentation to include the changes made to the CLI.
Stable release covered-0.7.1
05/07/2009 10:24 PM Filed in: Releases
Stable release covered-0.7.1 made. This is a bug fix release only. Here are the details:
Fixed bug 2782473. CDD files being merged from different testbenches but with similar leading hierarchy (but different top-level modules) which would lead to internal assertion errors.
Fixed bug 2785453. Wires declared in generated named scopes were not handled correctly by Covered in VPI mode of operation, leading to inaccurate coverage information.
Fixed bug 2786986. An always block with a part select in the sensitivity list was triggering on the entire signal change rather than the specific part select, leading to a potential degradation in performance and inaccuracy in coverage information.
Allow time variable types to be included for coverage.
Fixing permission issue with the install-sh script that some people would get after first downloading and installing.
Updated README and INSTALL files to be more accurate.
Fixed coverage accuracy issue for code that uses variable part selects in LHS of expressions.
Stable release covered-0.7
04/26/2009 10:24 PM Filed in: Releases
Stable release covered-0.7 made. This is a significant improvement over the 0.6 release, providing Verilog language enhancements, significant score optimizations, new rank and exclude commands, an enhanced merging capability, a multitude of GUI enhancements, a complete overhaul of the user documentation, many bug fixes, and much more.
|
|
|
|
Bump PKGREVISION to 6.
|
|
It used to track cad/covered but the last upgrade happened to be 20060904.
|
|
|
|
It used to track icarus verilog but there is no update since 20090923.
No objections from <gdt>
|
|
|
|
|
|
|
|
|
|
thanks wiz.
|
|
|
|
|
|
lang/python/*.mk files
|
|
|
|
Last release was in 2009, last activity a couple years later.
Does not build.
Ok dmcmahill@ (maintainer).
|
|
|
|
|
|
to bump their dependencies (except those that were bumped in the last 24
hours already).
|
|
-------------------------
Version 1.0 is officially released, including the newest contribution:
point-in-polygon logical testing.
|
|
|
|
|
|
|
|
to make it build with newer boost library.
Changes since 4.0.1:
Do not allow spaces in component name (value field) in
component library editor, in dialogs (Edit field, Create component).
Remove front silkscreen default setting for PTH and NPTH pads.
OSX: back port touchpad support from development branch.
Add support for optional touchpad panning (merge of rev. 6586 from
development branch)
OSX: legacy canvas rendering speed improvements.
PolyLine.cpp: NormalizeAreaOutlines now removes null segments.
Remove support for in processing setting of ld library path.
Eeschema: make footprint and datasheet initially invisible, when creating a
component.
Make color names translatable in color selection dialog.
Mark locked tracks with 'L' letter in status field.
Added 'Reset Grid Origin' hot key (GAL).
Add support for PCB and footprint format versioning
Highlight a net when crossprobing with eeschema and highlight net tool
is enabled.
Make DRC markers not editable with the standard tools (GAL).
Draw arrows for DRC markers (GAL).
and lots of bug fixes.
|
|
There has been a lot of development since the previous version in
pkgsrc. DWG read/write support and SVG export are major features,
along with moving to Qt4 and onwards. The QCAD toolbar is no longer
supported, and the program is faster in operation than the previous
pkgsrc version.
Apart from the github commit log which is overly detailed, the
previous release information with some change logs is at
https://github.com/LibreCAD/LibreCAD/releases
|
